drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2022 Intel Corporation
   4  */
   5
   6 #include <drm/drm_edid.h>
   7 #include <drm/drm_eld.h>
   8
   9 #include "i915_drv.h"
  10 #include "intel_crtc_state_dump.h"
  11 #include "intel_display_types.h"
  12 #include "intel_hdmi.h"
  13 #include "intel_vrr.h"
  14
  15 static void intel_dump_crtc_timings(struct drm_i915_private *i915,
  16                                     const struct drm_display_mode *mode)
  17 {
  18         drm_dbg_kms(&i915->drm, "crtc timings: clock=%d, "
  19                     "hd=%d hb=%d-%d hs=%d-%d ht=%d, "
  20                     "vd=%d vb=%d-%d vs=%d-%d vt=%d, "
  21                     "flags=0x%x\n",
  22                     mode->crtc_clock,
  23                     mode->crtc_hdisplay, mode->crtc_hblank_start, mode->crtc_hblank_end,
  24                     mode->crtc_hsync_start, mode->crtc_hsync_end, mode->crtc_htotal,
  25                     mode->crtc_vdisplay, mode->crtc_vblank_start, mode->crtc_vblank_end,
  26                     mode->crtc_vsync_start, mode->crtc_vsync_end, mode->crtc_vtotal,
  27                     mode->flags);
  28 }
  29
  30 static void
  31 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
  32                       const char *id, unsigned int lane_count,
  33                       const struct intel_link_m_n *m_n)
  34 {
  35         struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
  36
  37         drm_dbg_kms(&i915->drm,
  38                     "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
  39                     id, lane_count,
  40                     m_n->data_m, m_n->data_n,
  41                     m_n->link_m, m_n->link_n, m_n->tu);
  42 }
  43
  44 static void
  45 intel_dump_infoframe(struct drm_i915_private *i915,
  46                      const union hdmi_infoframe *frame)
  47 {
  48         if (!drm_debug_enabled(DRM_UT_KMS))
  49                 return;
  50
  51         hdmi_infoframe_log(KERN_DEBUG, i915->drm.dev, frame);
  52 }
  53
  54 static void
  55 intel_dump_dp_vsc_sdp(struct drm_i915_private *i915,
  56                       const struct drm_dp_vsc_sdp *vsc)
  57 {
  58         if (!drm_debug_enabled(DRM_UT_KMS))
  59                 return;
  60
  61         drm_dp_vsc_sdp_log(KERN_DEBUG, i915->drm.dev, vsc);
  62 }
  63
  64 static void
  65 intel_dump_buffer(struct drm_i915_private *i915,
  66                   const char *prefix, const u8 *buf, size_t len)
  67 {
  68         if (!drm_debug_enabled(DRM_UT_KMS))
  69                 return;
  70
  71         print_hex_dump(KERN_DEBUG, prefix, DUMP_PREFIX_NONE,
  72                        16, 0, buf, len, false);
  73 }
  74
  75 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
  76
  77 static const char * const output_type_str[] = {
  78         OUTPUT_TYPE(UNUSED),
  79         OUTPUT_TYPE(ANALOG),
  80         OUTPUT_TYPE(DVO),
  81         OUTPUT_TYPE(SDVO),
  82         OUTPUT_TYPE(LVDS),
  83         OUTPUT_TYPE(TVOUT),
  84         OUTPUT_TYPE(HDMI),
  85         OUTPUT_TYPE(DP),
  86         OUTPUT_TYPE(EDP),
  87         OUTPUT_TYPE(DSI),
  88         OUTPUT_TYPE(DDI),
  89         OUTPUT_TYPE(DP_MST),
  90 };
  91
  92 #undef OUTPUT_TYPE
  93
  94 static void snprintf_output_types(char *buf, size_t len,
  95                                   unsigned int output_types)
  96 {
  97         char *str = buf;
  98         int i;
  99
 100         str[0] = '\0';
 101
 102         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
 103                 int r;
 104
 105                 if ((output_types & BIT(i)) == 0)
 106                         continue;
 107
 108                 r = snprintf(str, len, "%s%s",
 109                              str != buf ? "," : "", output_type_str[i]);
 110                 if (r >= len)
 111                         break;
 112                 str += r;
 113                 len -= r;
 114
 115                 output_types &= ~BIT(i);
 116         }
 117
 118         WARN_ON_ONCE(output_types != 0);
 119 }
 120
 121 static const char * const output_format_str[] = {
 122         [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
 123         [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
 124         [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
 125 };
 126
 127 const char *intel_output_format_name(enum intel_output_format format)
 128 {
 129         if (format >= ARRAY_SIZE(output_format_str))
 130                 return "invalid";
 131         return output_format_str[format];
 132 }
 133
 134 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
 135 {
 136         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 137         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 138         const struct drm_framebuffer *fb = plane_state->hw.fb;
 139
 140         if (!fb) {
 141                 drm_dbg_kms(&i915->drm,
 142                             "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
 143                             plane->base.base.id, plane->base.name,
 144                             str_yes_no(plane_state->uapi.visible));
 145                 return;
 146         }
 147
 148         drm_dbg_kms(&i915->drm,
 149                     "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n",
 150                     plane->base.base.id, plane->base.name,
 151                     fb->base.id, fb->width, fb->height, &fb->format->format,
 152                     fb->modifier, str_yes_no(plane_state->uapi.visible));
 153         drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d, scaling_filter: %d\n",
 154                     plane_state->hw.rotation, plane_state->scaler_id, plane_state->hw.scaling_filter);
 155         if (plane_state->uapi.visible)
 156                 drm_dbg_kms(&i915->drm,
 157                             "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
 158                             DRM_RECT_FP_ARG(&plane_state->uapi.src),
 159                             DRM_RECT_ARG(&plane_state->uapi.dst));
 160 }
 161
 162 static void
 163 ilk_dump_csc(struct drm_i915_private *i915, const char *name,
 164              const struct intel_csc_matrix *csc)
 165 {
 166         int i;
 167
 168         drm_dbg_kms(&i915->drm,
 169                     "%s: pre offsets: 0x%04x 0x%04x 0x%04x\n", name,
 170                     csc->preoff[0], csc->preoff[1], csc->preoff[2]);
 171
 172         for (i = 0; i < 3; i++)
 173                 drm_dbg_kms(&i915->drm,
 174                             "%s: coefficients: 0x%04x 0x%04x 0x%04x\n", name,
 175                             csc->coeff[3 * i + 0],
 176                             csc->coeff[3 * i + 1],
 177                             csc->coeff[3 * i + 2]);
 178
 179         if (DISPLAY_VER(i915) < 7)
 180                 return;
 181
 182         drm_dbg_kms(&i915->drm,
 183                     "%s: post offsets: 0x%04x 0x%04x 0x%04x\n", name,
 184                     csc->postoff[0], csc->postoff[1], csc->postoff[2]);
 185 }
 186
 187 static void
 188 vlv_dump_csc(struct drm_i915_private *i915, const char *name,
 189              const struct intel_csc_matrix *csc)
 190 {
 191         int i;
 192
 193         for (i = 0; i < 3; i++)
 194                 drm_dbg_kms(&i915->drm,
 195                             "%s: coefficients: 0x%04x 0x%04x 0x%04x\n", name,
 196                             csc->coeff[3 * i + 0],
 197                             csc->coeff[3 * i + 1],
 198                             csc->coeff[3 * i + 2]);
 199 }
 200
 201 void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 202                            struct intel_atomic_state *state,
 203                            const char *context)
 204 {
 205         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 206         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 207         const struct intel_plane_state *plane_state;
 208         struct intel_plane *plane;
 209         char buf[64];
 210         int i;
 211
 212         drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] enable: %s [%s]\n",
 213                     crtc->base.base.id, crtc->base.name,
 214                     str_yes_no(pipe_config->hw.enable), context);
 215
 216         if (!pipe_config->hw.enable)
 217                 goto dump_planes;
 218
 219         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
 220         drm_dbg_kms(&i915->drm,
 221                     "active: %s, output_types: %s (0x%x), output format: %s, sink format: %s\n",
 222                     str_yes_no(pipe_config->hw.active),
 223                     buf, pipe_config->output_types,
 224                     intel_output_format_name(pipe_config->output_format),
 225                     intel_output_format_name(pipe_config->sink_format));
 226
 227         drm_dbg_kms(&i915->drm,
 228                     "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
 229                     transcoder_name(pipe_config->cpu_transcoder),
 230                     pipe_config->pipe_bpp, pipe_config->dither);
 231
 232         drm_dbg_kms(&i915->drm, "MST master transcoder: %s\n",
 233                     transcoder_name(pipe_config->mst_master_transcoder));
 234
 235         drm_dbg_kms(&i915->drm,
 236                     "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
 237                     transcoder_name(pipe_config->master_transcoder),
 238                     pipe_config->sync_mode_slaves_mask);
 239
 240         drm_dbg_kms(&i915->drm, "bigjoiner: %s, pipes: 0x%x\n",
 241                     intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" :
 242                     intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no",
 243                     pipe_config->bigjoiner_pipes);
 244
 245         drm_dbg_kms(&i915->drm, "splitter: %s, link count %d, overlap %d\n",
 246                     str_enabled_disabled(pipe_config->splitter.enable),
 247                     pipe_config->splitter.link_count,
 248                     pipe_config->splitter.pixel_overlap);
 249
 250         if (pipe_config->has_pch_encoder)
 251                 intel_dump_m_n_config(pipe_config, "fdi",
 252                                       pipe_config->fdi_lanes,
 253                                       &pipe_config->fdi_m_n);
 254
 255         if (intel_crtc_has_dp_encoder(pipe_config)) {
 256                 intel_dump_m_n_config(pipe_config, "dp m_n",
 257                                       pipe_config->lane_count,
 258                                       &pipe_config->dp_m_n);
 259                 intel_dump_m_n_config(pipe_config, "dp m2_n2",
 260                                       pipe_config->lane_count,
 261                                       &pipe_config->dp_m2_n2);
 262                 drm_dbg_kms(&i915->drm, "fec: %s, enhanced framing: %s\n",
 263                             str_enabled_disabled(pipe_config->fec_enable),
 264                             str_enabled_disabled(pipe_config->enhanced_framing));
 265
 266                 drm_dbg_kms(&i915->drm, "sdp split: %s\n",
 267                             str_enabled_disabled(pipe_config->sdp_split_enable));
 268
 269                 drm_dbg_kms(&i915->drm, "psr: %s, psr2: %s, panel replay: %s, selective fetch: %s\n",
 270                             str_enabled_disabled(pipe_config->has_psr),
 271                             str_enabled_disabled(pipe_config->has_psr2),
 272                             str_enabled_disabled(pipe_config->has_panel_replay),
 273                             str_enabled_disabled(pipe_config->enable_psr2_sel_fetch));
 274         }
 275
 276         drm_dbg_kms(&i915->drm, "framestart delay: %d, MSA timing delay: %d\n",
 277                     pipe_config->framestart_delay, pipe_config->msa_timing_delay);
 278
 279         drm_dbg_kms(&i915->drm,
 280                     "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
 281                     pipe_config->has_audio, pipe_config->has_infoframe,
 282                     pipe_config->infoframes.enable);
 283
 284         if (pipe_config->infoframes.enable &
 285             intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
 286                 drm_dbg_kms(&i915->drm, "GCP: 0x%x\n",
 287                             pipe_config->infoframes.gcp);
 288         if (pipe_config->infoframes.enable &
 289             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
 290                 intel_dump_infoframe(i915, &pipe_config->infoframes.avi);
 291         if (pipe_config->infoframes.enable &
 292             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
 293                 intel_dump_infoframe(i915, &pipe_config->infoframes.spd);
 294         if (pipe_config->infoframes.enable &
 295             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
 296                 intel_dump_infoframe(i915, &pipe_config->infoframes.hdmi);
 297         if (pipe_config->infoframes.enable &
 298             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
 299                 intel_dump_infoframe(i915, &pipe_config->infoframes.drm);
 300         if (pipe_config->infoframes.enable &
 301             intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
 302                 intel_dump_infoframe(i915, &pipe_config->infoframes.drm);
 303         if (pipe_config->infoframes.enable &
 304             intel_hdmi_infoframe_enable(DP_SDP_VSC))
 305                 intel_dump_dp_vsc_sdp(i915, &pipe_config->infoframes.vsc);
 306
 307         if (pipe_config->has_audio)
 308                 intel_dump_buffer(i915, "ELD: ", pipe_config->eld,
 309                                   drm_eld_size(pipe_config->eld));
 310
 311         drm_dbg_kms(&i915->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
 312                     str_yes_no(pipe_config->vrr.enable),
 313                     pipe_config->vrr.vmin, pipe_config->vrr.vmax,
 314                     pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
 315                     pipe_config->vrr.flipline,
 316                     intel_vrr_vmin_vblank_start(pipe_config),
 317                     intel_vrr_vmax_vblank_start(pipe_config));
 318
 319         drm_dbg_kms(&i915->drm, "requested mode: " DRM_MODE_FMT "\n",
 320                     DRM_MODE_ARG(&pipe_config->hw.mode));
 321         drm_dbg_kms(&i915->drm, "adjusted mode: " DRM_MODE_FMT "\n",
 322                     DRM_MODE_ARG(&pipe_config->hw.adjusted_mode));
 323         intel_dump_crtc_timings(i915, &pipe_config->hw.adjusted_mode);
 324         drm_dbg_kms(&i915->drm, "pipe mode: " DRM_MODE_FMT "\n",
 325                     DRM_MODE_ARG(&pipe_config->hw.pipe_mode));
 326         intel_dump_crtc_timings(i915, &pipe_config->hw.pipe_mode);
 327         drm_dbg_kms(&i915->drm,
 328                     "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n",
 329                     pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src),
 330                     pipe_config->pixel_rate);
 331
 332         drm_dbg_kms(&i915->drm, "linetime: %d, ips linetime: %d\n",
 333                     pipe_config->linetime, pipe_config->ips_linetime);
 334
 335         if (DISPLAY_VER(i915) >= 9)
 336                 drm_dbg_kms(&i915->drm,
 337                             "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d, scaling_filter: %d\n",
 338                             crtc->num_scalers,
 339                             pipe_config->scaler_state.scaler_users,
 340                             pipe_config->scaler_state.scaler_id,
 341                             pipe_config->hw.scaling_filter);
 342
 343         if (HAS_GMCH(i915))
 344                 drm_dbg_kms(&i915->drm,
 345                             "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
 346                             pipe_config->gmch_pfit.control,
 347                             pipe_config->gmch_pfit.pgm_ratios,
 348                             pipe_config->gmch_pfit.lvds_border_bits);
 349         else
 350                 drm_dbg_kms(&i915->drm,
 351                             "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
 352                             DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
 353                             str_enabled_disabled(pipe_config->pch_pfit.enabled),
 354                             str_yes_no(pipe_config->pch_pfit.force_thru));
 355
 356         drm_dbg_kms(&i915->drm, "ips: %i, double wide: %i, drrs: %i\n",
 357                     pipe_config->ips_enabled, pipe_config->double_wide,
 358                     pipe_config->has_drrs);
 359
 360         intel_dpll_dump_hw_state(i915, &pipe_config->dpll_hw_state);
 361
 362         if (IS_CHERRYVIEW(i915))
 363                 drm_dbg_kms(&i915->drm,
 364                             "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
 365                             pipe_config->cgm_mode, pipe_config->gamma_mode,
 366                             pipe_config->gamma_enable, pipe_config->csc_enable);
 367         else
 368                 drm_dbg_kms(&i915->drm,
 369                             "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
 370                             pipe_config->csc_mode, pipe_config->gamma_mode,
 371                             pipe_config->gamma_enable, pipe_config->csc_enable);
 372
 373         drm_dbg_kms(&i915->drm, "pre csc lut: %s%d entries, post csc lut: %d entries\n",
 374                     pipe_config->pre_csc_lut && pipe_config->pre_csc_lut ==
 375                     i915->display.color.glk_linear_degamma_lut ? "(linear) " : "",
 376                     pipe_config->pre_csc_lut ?
 377                     drm_color_lut_size(pipe_config->pre_csc_lut) : 0,
 378                     pipe_config->post_csc_lut ?
 379                     drm_color_lut_size(pipe_config->post_csc_lut) : 0);
 380
 381         if (DISPLAY_VER(i915) >= 11)
 382                 ilk_dump_csc(i915, "output csc", &pipe_config->output_csc);
 383
 384         if (!HAS_GMCH(i915))
 385                 ilk_dump_csc(i915, "pipe csc", &pipe_config->csc);
 386         else if (IS_CHERRYVIEW(i915))
 387                 vlv_dump_csc(i915, "cgm csc", &pipe_config->csc);
 388         else if (IS_VALLEYVIEW(i915))
 389                 vlv_dump_csc(i915, "wgc csc", &pipe_config->csc);
 390
 391 dump_planes:
 392         if (!state)
 393                 return;
 394
 395         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
 396                 if (plane->pipe == crtc->pipe)
 397                         intel_dump_plane_state(plane_state);
 398         }
 399 }