1 // SPDX-License-Identifier: MIT
3 * Copyright © 2018 Intel Corporation
6 #include "intel_combo_phy.h"
7 #include "intel_combo_phy_regs.h"
9 #include "intel_display_types.h"
11 #define for_each_combo_phy(__dev_priv, __phy) \
12 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
13 for_each_if(intel_phy_is_combo(__dev_priv, __phy))
15 #define for_each_combo_phy_reverse(__dev_priv, __phy) \
16 for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
17 for_each_if(intel_phy_is_combo(__dev_priv, __phy))
27 static const struct icl_procmon {
30 } icl_procmon_values[] = {
31 [PROCMON_0_85V_DOT_0] = {
32 .name = "0.85V dot0 (low-voltage)",
33 .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96,
35 [PROCMON_0_95V_DOT_0] = {
37 .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB,
39 [PROCMON_0_95V_DOT_1] = {
41 .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5,
43 [PROCMON_1_05V_DOT_0] = {
45 .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1,
47 [PROCMON_1_05V_DOT_1] = {
49 .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1,
53 static const struct icl_procmon *
54 icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
56 const struct icl_procmon *procmon;
59 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy));
60 switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
64 case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
65 procmon = &icl_procmon_values[PROCMON_0_85V_DOT_0];
67 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
68 procmon = &icl_procmon_values[PROCMON_0_95V_DOT_0];
70 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
71 procmon = &icl_procmon_values[PROCMON_0_95V_DOT_1];
73 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
74 procmon = &icl_procmon_values[PROCMON_1_05V_DOT_0];
76 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
77 procmon = &icl_procmon_values[PROCMON_1_05V_DOT_1];
84 static void icl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
87 const struct icl_procmon *procmon;
90 procmon = icl_get_procmon_ref_values(dev_priv, phy);
92 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy));
93 val &= ~((0xff << 16) | 0xff);
95 intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val);
97 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9);
98 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10);
101 static bool check_phy_reg(struct drm_i915_private *dev_priv,
102 enum phy phy, i915_reg_t reg, u32 mask,
105 u32 val = intel_de_read(dev_priv, reg);
107 if ((val & mask) != expected_val) {
108 drm_dbg(&dev_priv->drm,
109 "Combo PHY %c reg %08x state mismatch: "
110 "current %08x mask %08x expected %08x\n",
112 reg.reg, val, mask, expected_val);
119 static bool icl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
122 const struct icl_procmon *procmon;
125 procmon = icl_get_procmon_ref_values(dev_priv, phy);
127 drm_dbg_kms(&dev_priv->drm,
128 "Combo PHY %c Voltage/Process Info : %s\n",
129 phy_name(phy), procmon->name);
131 ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
132 (0xff << 16) | 0xff, procmon->dw1);
133 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),
135 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),
141 static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
144 * Some platforms only expect PHY_MISC to be programmed for PHY-A and
145 * PHY-B and may not even have instances of the register for the
148 * ADL-S technically has three instances of PHY_MISC, but only requires
149 * that we program it for PHY A.
152 if (IS_ALDERLAKE_S(i915))
154 else if (IS_JSL_EHL(i915) ||
155 IS_ROCKETLAKE(i915) ||
162 static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
165 /* The PHY C added by EHL has no PHY_MISC register */
166 if (!has_phy_misc(dev_priv, phy))
167 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
169 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) &
170 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
171 (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);
174 static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915)
176 bool ddi_a_present = intel_bios_is_port_present(i915, PORT_A);
177 bool ddi_d_present = intel_bios_is_port_present(i915, PORT_D);
178 bool dsi_present = intel_bios_is_dsi_present(i915, NULL);
181 * VBT's 'dvo port' field for child devices references the DDI, not
182 * the PHY. So if combo PHY A is wired up to drive an external
183 * display, we should see a child device present on PORT_D and
184 * nothing on PORT_A and no DSI.
186 if (ddi_d_present && !ddi_a_present && !dsi_present)
190 * If we encounter a VBT that claims to have an external display on
191 * DDI-D _and_ an internal display on DDI-A/DSI leave an error message
192 * in the log and let the internal display win.
196 "VBT claims to have both internal and external displays on PHY A. Configuring for internal.\n");
201 static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
204 * Certain PHYs are connected to compensation resistors and act
205 * as masters to other PHYs.
208 * A(master) -> B(slave), C(slave)
210 * A(master) -> B(slave)
211 * C(master) -> D(slave)
213 * A(master) -> B(slave), C(slave)
214 * D(master) -> E(slave)
216 * We must set the IREFGEN bit for any PHY acting as a master
221 else if (IS_ALDERLAKE_S(dev_priv))
223 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
229 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
233 u32 expected_val = 0;
235 if (!icl_combo_phy_enabled(dev_priv, phy))
238 if (DISPLAY_VER(dev_priv) >= 12) {
239 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN(0, phy),
240 ICL_PORT_TX_DW8_ODCC_CLK_SEL |
241 ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK,
242 ICL_PORT_TX_DW8_ODCC_CLK_SEL |
243 ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
245 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy),
246 DCC_MODE_SELECT_MASK,
247 DCC_MODE_SELECT_CONTINUOSLY);
250 ret &= icl_verify_procmon_ref_values(dev_priv, phy);
252 if (phy_is_master(dev_priv, phy)) {
253 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
256 if (IS_JSL_EHL(dev_priv)) {
257 if (ehl_vbt_ddi_d_present(dev_priv))
258 expected_val = ICL_PHY_MISC_MUX_DDID;
260 ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy),
261 ICL_PHY_MISC_MUX_DDID,
266 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),
267 CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
272 void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
273 enum phy phy, bool is_dsi,
274 int lane_count, bool lane_reversal)
280 drm_WARN_ON(&dev_priv->drm, lane_reversal);
282 switch (lane_count) {
284 lane_mask = PWR_DOWN_LN_3_1_0;
287 lane_mask = PWR_DOWN_LN_3_1;
290 lane_mask = PWR_DOWN_LN_3;
293 MISSING_CASE(lane_count);
296 lane_mask = PWR_UP_ALL_LANES;
300 switch (lane_count) {
302 lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 :
306 lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 :
310 MISSING_CASE(lane_count);
313 lane_mask = PWR_UP_ALL_LANES;
318 val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy));
319 val &= ~PWR_DOWN_LN_MASK;
321 intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val);
324 static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
328 for_each_combo_phy(dev_priv, phy) {
331 if (icl_combo_phy_verify_state(dev_priv, phy)) {
332 drm_dbg(&dev_priv->drm,
333 "Combo PHY %c already enabled, won't reprogram it.\n",
338 if (!has_phy_misc(dev_priv, phy))
342 * EHL's combo PHY A can be hooked up to either an external
343 * display (via DDI-D) or an internal display (via DDI-A or
344 * the DSI DPHY). This is a motherboard design decision that
345 * can't be changed on the fly, so initialize the PHY's mux
346 * based on whether our VBT indicates the presence of any
347 * "internal" child devices.
349 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
350 if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {
351 val &= ~ICL_PHY_MISC_MUX_DDID;
353 if (ehl_vbt_ddi_d_present(dev_priv))
354 val |= ICL_PHY_MISC_MUX_DDID;
357 val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
358 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);
361 if (DISPLAY_VER(dev_priv) >= 12) {
362 val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy));
363 val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;
364 val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;
365 val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;
366 intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
368 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
369 val &= ~DCC_MODE_SELECT_MASK;
370 val |= DCC_MODE_SELECT_CONTINUOSLY;
371 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
374 icl_set_procmon_ref_values(dev_priv, phy);
376 if (phy_is_master(dev_priv, phy)) {
377 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy));
379 intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val);
382 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy));
384 intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val);
386 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
387 val |= CL_POWER_DOWN_ENABLE;
388 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
392 static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
396 for_each_combo_phy_reverse(dev_priv, phy) {
400 !icl_combo_phy_verify_state(dev_priv, phy)) {
401 if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) {
403 * A known problem with old ifwi:
404 * https://gitlab.freedesktop.org/drm/intel/-/issues/2411
405 * Suppress the warning for CI. Remove ASAP!
407 drm_dbg_kms(&dev_priv->drm,
408 "Combo PHY %c HW state changed unexpectedly\n",
411 drm_warn(&dev_priv->drm,
412 "Combo PHY %c HW state changed unexpectedly\n",
417 if (!has_phy_misc(dev_priv, phy))
420 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
421 val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
422 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);
425 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy));
427 intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val);
431 void intel_combo_phy_init(struct drm_i915_private *i915)
433 icl_combo_phys_init(i915);
436 void intel_combo_phy_uninit(struct drm_i915_private *i915)
438 icl_combo_phys_uninit(i915);