drivers/gpu/drm/i915/display/intel_atomic.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: atomic modeset support
  26  *
  27  * The functions here implement the state management and hardware programming
  28  * dispatch required by the atomic modeset infrastructure.
  29  * See intel_atomic_plane.c for the plane-specific atomic functionality.
  30  */
  31
  32 #include <drm/drm_atomic.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_fourcc.h>
  35
  36 #include "i915_drv.h"
  37 #include "i915_reg.h"
  38 #include "intel_atomic.h"
  39 #include "intel_cdclk.h"
  40 #include "intel_display_types.h"
  41 #include "intel_global_state.h"
  42 #include "intel_hdcp.h"
  43 #include "intel_psr.h"
  44 #include "skl_universal_plane.h"
  45
  46 /**
  47  * intel_digital_connector_atomic_get_property - hook for connector->atomic_get_property.
  48  * @connector: Connector to get the property for.
  49  * @state: Connector state to retrieve the property from.
  50  * @property: Property to retrieve.
  51  * @val: Return value for the property.
  52  *
  53  * Returns the atomic property value for a digital connector.
  54  */
  55 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
  56                                                 const struct drm_connector_state *state,
  57                                                 struct drm_property *property,
  58                                                 u64 *val)
  59 {
  60         struct drm_device *dev = connector->dev;
  61         struct drm_i915_private *dev_priv = to_i915(dev);
  62         struct intel_digital_connector_state *intel_conn_state =
  63                 to_intel_digital_connector_state(state);
  64
  65         if (property == dev_priv->display.properties.force_audio)
  66                 *val = intel_conn_state->force_audio;
  67         else if (property == dev_priv->display.properties.broadcast_rgb)
  68                 *val = intel_conn_state->broadcast_rgb;
  69         else {
  70                 drm_dbg_atomic(&dev_priv->drm,
  71                                "Unknown property [PROP:%d:%s]\n",
  72                                property->base.id, property->name);
  73                 return -EINVAL;
  74         }
  75
  76         return 0;
  77 }
  78
  79 /**
  80  * intel_digital_connector_atomic_set_property - hook for connector->atomic_set_property.
  81  * @connector: Connector to set the property for.
  82  * @state: Connector state to set the property on.
  83  * @property: Property to set.
  84  * @val: New value for the property.
  85  *
  86  * Sets the atomic property value for a digital connector.
  87  */
  88 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
  89                                                 struct drm_connector_state *state,
  90                                                 struct drm_property *property,
  91                                                 u64 val)
  92 {
  93         struct drm_device *dev = connector->dev;
  94         struct drm_i915_private *dev_priv = to_i915(dev);
  95         struct intel_digital_connector_state *intel_conn_state =
  96                 to_intel_digital_connector_state(state);
  97
  98         if (property == dev_priv->display.properties.force_audio) {
  99                 intel_conn_state->force_audio = val;
 100                 return 0;
 101         }
 102
 103         if (property == dev_priv->display.properties.broadcast_rgb) {
 104                 intel_conn_state->broadcast_rgb = val;
 105                 return 0;
 106         }
 107
 108         drm_dbg_atomic(&dev_priv->drm, "Unknown property [PROP:%d:%s]\n",
 109                        property->base.id, property->name);
 110         return -EINVAL;
 111 }
 112
 113 int intel_digital_connector_atomic_check(struct drm_connector *conn,
 114                                          struct drm_atomic_state *state)
 115 {
 116         struct drm_connector_state *new_state =
 117                 drm_atomic_get_new_connector_state(state, conn);
 118         struct intel_digital_connector_state *new_conn_state =
 119                 to_intel_digital_connector_state(new_state);
 120         struct drm_connector_state *old_state =
 121                 drm_atomic_get_old_connector_state(state, conn);
 122         struct intel_digital_connector_state *old_conn_state =
 123                 to_intel_digital_connector_state(old_state);
 124         struct drm_crtc_state *crtc_state;
 125
 126         intel_hdcp_atomic_check(conn, old_state, new_state);
 127
 128         if (!new_state->crtc)
 129                 return 0;
 130
 131         crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);
 132
 133         /*
 134          * These properties are handled by fastset, and might not end
 135          * up in a modeset.
 136          */
 137         if (new_conn_state->force_audio != old_conn_state->force_audio ||
 138             new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb ||
 139             new_conn_state->base.colorspace != old_conn_state->base.colorspace ||
 140             new_conn_state->base.picture_aspect_ratio != old_conn_state->base.picture_aspect_ratio ||
 141             new_conn_state->base.content_type != old_conn_state->base.content_type ||
 142             new_conn_state->base.scaling_mode != old_conn_state->base.scaling_mode ||
 143             new_conn_state->base.privacy_screen_sw_state != old_conn_state->base.privacy_screen_sw_state ||
 144             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state))
 145                 crtc_state->mode_changed = true;
 146
 147         return 0;
 148 }
 149
 150 /**
 151  * intel_digital_connector_duplicate_state - duplicate connector state
 152  * @connector: digital connector
 153  *
 154  * Allocates and returns a copy of the connector state (both common and
 155  * digital connector specific) for the specified connector.
 156  *
 157  * Returns: The newly allocated connector state, or NULL on failure.
 158  */
 159 struct drm_connector_state *
 160 intel_digital_connector_duplicate_state(struct drm_connector *connector)
 161 {
 162         struct intel_digital_connector_state *state;
 163
 164         state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
 165         if (!state)
 166                 return NULL;
 167
 168         __drm_atomic_helper_connector_duplicate_state(connector, &state->base);
 169         return &state->base;
 170 }
 171
 172 /**
 173  * intel_connector_needs_modeset - check if connector needs a modeset
 174  * @state: the atomic state corresponding to this modeset
 175  * @connector: the connector
 176  */
 177 bool
 178 intel_connector_needs_modeset(struct intel_atomic_state *state,
 179                               struct drm_connector *connector)
 180 {
 181         const struct drm_connector_state *old_conn_state, *new_conn_state;
 182
 183         old_conn_state = drm_atomic_get_old_connector_state(&state->base, connector);
 184         new_conn_state = drm_atomic_get_new_connector_state(&state->base, connector);
 185
 186         return old_conn_state->crtc != new_conn_state->crtc ||
 187                (new_conn_state->crtc &&
 188                 drm_atomic_crtc_needs_modeset(drm_atomic_get_new_crtc_state(&state->base,
 189                                                                             new_conn_state->crtc)));
 190 }
 191
 192 /**
 193  * intel_any_crtc_needs_modeset - check if any CRTC needs a modeset
 194  * @state: the atomic state corresponding to this modeset
 195  *
 196  * Returns true if any CRTC in @state needs a modeset.
 197  */
 198 bool intel_any_crtc_needs_modeset(struct intel_atomic_state *state)
 199 {
 200         struct intel_crtc *crtc;
 201         struct intel_crtc_state *crtc_state;
 202         int i;
 203
 204         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
 205                 if (intel_crtc_needs_modeset(crtc_state))
 206                         return true;
 207         }
 208
 209         return false;
 210 }
 211
 212 struct intel_digital_connector_state *
 213 intel_atomic_get_digital_connector_state(struct intel_atomic_state *state,
 214                                          struct intel_connector *connector)
 215 {
 216         struct drm_connector_state *conn_state;
 217
 218         conn_state = drm_atomic_get_connector_state(&state->base,
 219                                                     &connector->base);
 220         if (IS_ERR(conn_state))
 221                 return ERR_CAST(conn_state);
 222
 223         return to_intel_digital_connector_state(conn_state);
 224 }
 225
 226 /**
 227  * intel_crtc_duplicate_state - duplicate crtc state
 228  * @crtc: drm crtc
 229  *
 230  * Allocates and returns a copy of the crtc state (both common and
 231  * Intel-specific) for the specified crtc.
 232  *
 233  * Returns: The newly allocated crtc state, or NULL on failure.
 234  */
 235 struct drm_crtc_state *
 236 intel_crtc_duplicate_state(struct drm_crtc *crtc)
 237 {
 238         const struct intel_crtc_state *old_crtc_state = to_intel_crtc_state(crtc->state);
 239         struct intel_crtc_state *crtc_state;
 240
 241         crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);
 242         if (!crtc_state)
 243                 return NULL;
 244
 245         __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
 246
 247         /* copy color blobs */
 248         if (crtc_state->hw.degamma_lut)
 249                 drm_property_blob_get(crtc_state->hw.degamma_lut);
 250         if (crtc_state->hw.ctm)
 251                 drm_property_blob_get(crtc_state->hw.ctm);
 252         if (crtc_state->hw.gamma_lut)
 253                 drm_property_blob_get(crtc_state->hw.gamma_lut);
 254
 255         crtc_state->update_pipe = false;
 256         crtc_state->disable_lp_wm = false;
 257         crtc_state->disable_cxsr = false;
 258         crtc_state->update_wm_pre = false;
 259         crtc_state->update_wm_post = false;
 260         crtc_state->fifo_changed = false;
 261         crtc_state->preload_luts = false;
 262         crtc_state->inherited = false;
 263         crtc_state->wm.need_postvbl_update = false;
 264         crtc_state->do_async_flip = false;
 265         crtc_state->fb_bits = 0;
 266         crtc_state->update_planes = 0;
 267         crtc_state->dsb = NULL;
 268
 269         return &crtc_state->uapi;
 270 }
 271
 272 static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state)
 273 {
 274         drm_property_blob_put(crtc_state->hw.degamma_lut);
 275         drm_property_blob_put(crtc_state->hw.gamma_lut);
 276         drm_property_blob_put(crtc_state->hw.ctm);
 277 }
 278
 279 void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
 280 {
 281         intel_crtc_put_color_blobs(crtc_state);
 282 }
 283
 284 /**
 285  * intel_crtc_destroy_state - destroy crtc state
 286  * @crtc: drm crtc
 287  * @state: the state to destroy
 288  *
 289  * Destroys the crtc state (both common and Intel-specific) for the
 290  * specified crtc.
 291  */
 292 void
 293 intel_crtc_destroy_state(struct drm_crtc *crtc,
 294                          struct drm_crtc_state *state)
 295 {
 296         struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
 297
 298         drm_WARN_ON(crtc->dev, crtc_state->dsb);
 299
 300         __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
 301         intel_crtc_free_hw_state(crtc_state);
 302         kfree(crtc_state);
 303 }
 304
 305 static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
 306                                       int num_scalers_need, struct intel_crtc *intel_crtc,
 307                                       const char *name, int idx,
 308                                       struct intel_plane_state *plane_state,
 309                                       int *scaler_id)
 310 {
 311         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
 312         int j;
 313         u32 mode;
 314
 315         if (*scaler_id < 0) {
 316                 /* find a free scaler */
 317                 for (j = 0; j < intel_crtc->num_scalers; j++) {
 318                         if (scaler_state->scalers[j].in_use)
 319                                 continue;
 320
 321                         *scaler_id = j;
 322                         scaler_state->scalers[*scaler_id].in_use = 1;
 323                         break;
 324                 }
 325         }
 326
 327         if (drm_WARN(&dev_priv->drm, *scaler_id < 0,
 328                      "Cannot find scaler for %s:%d\n", name, idx))
 329                 return;
 330
 331         /* set scaler mode */
 332         if (plane_state && plane_state->hw.fb &&
 333             plane_state->hw.fb->format->is_yuv &&
 334             plane_state->hw.fb->format->num_planes > 1) {
 335                 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 336                 if (DISPLAY_VER(dev_priv) == 9) {
 337                         mode = SKL_PS_SCALER_MODE_NV12;
 338                 } else if (icl_is_hdr_plane(dev_priv, plane->id)) {
 339                         /*
 340                          * On gen11+'s HDR planes we only use the scaler for
 341                          * scaling. They have a dedicated chroma upsampler, so
 342                          * we don't need the scaler to upsample the UV plane.
 343                          */
 344                         mode = PS_SCALER_MODE_NORMAL;
 345                 } else {
 346                         struct intel_plane *linked =
 347                                 plane_state->planar_linked_plane;
 348
 349                         mode = PS_SCALER_MODE_PLANAR;
 350
 351                         if (linked)
 352                                 mode |= PS_PLANE_Y_SEL(linked->id);
 353                 }
 354         } else if (DISPLAY_VER(dev_priv) >= 10) {
 355                 mode = PS_SCALER_MODE_NORMAL;
 356         } else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
 357                 /*
 358                  * when only 1 scaler is in use on a pipe with 2 scalers
 359                  * scaler 0 operates in high quality (HQ) mode.
 360                  * In this case use scaler 0 to take advantage of HQ mode
 361                  */
 362                 scaler_state->scalers[*scaler_id].in_use = 0;
 363                 *scaler_id = 0;
 364                 scaler_state->scalers[0].in_use = 1;
 365                 mode = SKL_PS_SCALER_MODE_HQ;
 366         } else {
 367                 mode = SKL_PS_SCALER_MODE_DYN;
 368         }
 369
 370         drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n",
 371                     intel_crtc->pipe, *scaler_id, name, idx);
 372         scaler_state->scalers[*scaler_id].mode = mode;
 373 }
 374
 375 /**
 376  * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
 377  * @dev_priv: i915 device
 378  * @intel_crtc: intel crtc
 379  * @crtc_state: incoming crtc_state to validate and setup scalers
 380  *
 381  * This function sets up scalers based on staged scaling requests for
 382  * a @crtc and its planes. It is called from crtc level check path. If request
 383  * is a supportable request, it attaches scalers to requested planes and crtc.
 384  *
 385  * This function takes into account the current scaler(s) in use by any planes
 386  * not being part of this atomic state
 387  *
 388  *  Returns:
 389  *         0 - scalers were setup succesfully
 390  *         error code - otherwise
 391  */
 392 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
 393                                struct intel_crtc *intel_crtc,
 394                                struct intel_crtc_state *crtc_state)
 395 {
 396         struct drm_plane *plane = NULL;
 397         struct intel_plane *intel_plane;
 398         struct intel_plane_state *plane_state = NULL;
 399         struct intel_crtc_scaler_state *scaler_state =
 400                 &crtc_state->scaler_state;
 401         struct drm_atomic_state *drm_state = crtc_state->uapi.state;
 402         struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
 403         int num_scalers_need;
 404         int i;
 405
 406         num_scalers_need = hweight32(scaler_state->scaler_users);
 407
 408         /*
 409          * High level flow:
 410          * - staged scaler requests are already in scaler_state->scaler_users
 411          * - check whether staged scaling requests can be supported
 412          * - add planes using scalers that aren't in current transaction
 413          * - assign scalers to requested users
 414          * - as part of plane commit, scalers will be committed
 415          *   (i.e., either attached or detached) to respective planes in hw
 416          * - as part of crtc_commit, scaler will be either attached or detached
 417          *   to crtc in hw
 418          */
 419
 420         /* fail if required scalers > available scalers */
 421         if (num_scalers_need > intel_crtc->num_scalers){
 422                 drm_dbg_kms(&dev_priv->drm,
 423                             "Too many scaling requests %d > %d\n",
 424                             num_scalers_need, intel_crtc->num_scalers);
 425                 return -EINVAL;
 426         }
 427
 428         /* walkthrough scaler_users bits and start assigning scalers */
 429         for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
 430                 int *scaler_id;
 431                 const char *name;
 432                 int idx;
 433
 434                 /* skip if scaler not required */
 435                 if (!(scaler_state->scaler_users & (1 << i)))
 436                         continue;
 437
 438                 if (i == SKL_CRTC_INDEX) {
 439                         name = "CRTC";
 440                         idx = intel_crtc->base.base.id;
 441
 442                         /* panel fitter case: assign as a crtc scaler */
 443                         scaler_id = &scaler_state->scaler_id;
 444                 } else {
 445                         name = "PLANE";
 446
 447                         /* plane scaler case: assign as a plane scaler */
 448                         /* find the plane that set the bit as scaler_user */
 449                         plane = drm_state->planes[i].ptr;
 450
 451                         /*
 452                          * to enable/disable hq mode, add planes that are using scaler
 453                          * into this transaction
 454                          */
 455                         if (!plane) {
 456                                 struct drm_plane_state *state;
 457
 458                                 /*
 459                                  * GLK+ scalers don't have a HQ mode so it
 460                                  * isn't necessary to change between HQ and dyn mode
 461                                  * on those platforms.
 462                                  */
 463                                 if (DISPLAY_VER(dev_priv) >= 10)
 464                                         continue;
 465
 466                                 plane = drm_plane_from_index(&dev_priv->drm, i);
 467                                 state = drm_atomic_get_plane_state(drm_state, plane);
 468                                 if (IS_ERR(state)) {
 469                                         drm_dbg_kms(&dev_priv->drm,
 470                                                     "Failed to add [PLANE:%d] to drm_state\n",
 471                                                     plane->base.id);
 472                                         return PTR_ERR(state);
 473                                 }
 474                         }
 475
 476                         intel_plane = to_intel_plane(plane);
 477                         idx = plane->base.id;
 478
 479                         /* plane on different crtc cannot be a scaler user of this crtc */
 480                         if (drm_WARN_ON(&dev_priv->drm,
 481                                         intel_plane->pipe != intel_crtc->pipe))
 482                                 continue;
 483
 484                         plane_state = intel_atomic_get_new_plane_state(intel_state,
 485                                                                        intel_plane);
 486                         scaler_id = &plane_state->scaler_id;
 487                 }
 488
 489                 intel_atomic_setup_scaler(scaler_state, num_scalers_need,
 490                                           intel_crtc, name, idx,
 491                                           plane_state, scaler_id);
 492         }
 493
 494         return 0;
 495 }
 496
 497 struct drm_atomic_state *
 498 intel_atomic_state_alloc(struct drm_device *dev)
 499 {
 500         struct intel_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
 501
 502         if (!state || drm_atomic_state_init(dev, &state->base) < 0) {
 503                 kfree(state);
 504                 return NULL;
 505         }
 506
 507         return &state->base;
 508 }
 509
 510 void intel_atomic_state_free(struct drm_atomic_state *_state)
 511 {
 512         struct intel_atomic_state *state = to_intel_atomic_state(_state);
 513
 514         drm_atomic_state_default_release(&state->base);
 515         kfree(state->global_objs);
 516
 517         i915_sw_fence_fini(&state->commit_ready);
 518
 519         kfree(state);
 520 }
 521
 522 void intel_atomic_state_clear(struct drm_atomic_state *s)
 523 {
 524         struct intel_atomic_state *state = to_intel_atomic_state(s);
 525
 526         drm_atomic_state_default_clear(&state->base);
 527         intel_atomic_clear_global_state(state);
 528
 529         state->dpll_set = state->modeset = false;
 530 }
 531
 532 struct intel_crtc_state *
 533 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
 534                             struct intel_crtc *crtc)
 535 {
 536         struct drm_crtc_state *crtc_state;
 537         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
 538         if (IS_ERR(crtc_state))
 539                 return ERR_CAST(crtc_state);
 540
 541         return to_intel_crtc_state(crtc_state);
 542 }