2 * Copyright © 2018 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Madhav Chauhan <madhav.chauhan@intel.com>
25 * Jani Nikula <jani.nikula@intel.com>
28 #include <drm/display/drm_dsc_helper.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_mipi_dsi.h>
33 #include "icl_dsi_regs.h"
34 #include "intel_atomic.h"
35 #include "intel_backlight.h"
36 #include "intel_combo_phy.h"
37 #include "intel_combo_phy_regs.h"
38 #include "intel_connector.h"
39 #include "intel_crtc.h"
40 #include "intel_ddi.h"
42 #include "intel_dsi.h"
43 #include "intel_dsi_vbt.h"
44 #include "intel_panel.h"
45 #include "intel_vdsc.h"
46 #include "skl_scaler.h"
47 #include "skl_universal_plane.h"
49 static int header_credits_available(struct drm_i915_private *dev_priv,
50 enum transcoder dsi_trans)
52 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
53 >> FREE_HEADER_CREDIT_SHIFT;
56 static int payload_credits_available(struct drm_i915_private *dev_priv,
57 enum transcoder dsi_trans)
59 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
60 >> FREE_PLOAD_CREDIT_SHIFT;
63 static bool wait_for_header_credits(struct drm_i915_private *dev_priv,
64 enum transcoder dsi_trans, int hdr_credit)
66 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
68 drm_err(&dev_priv->drm, "DSI header credits not released\n");
75 static bool wait_for_payload_credits(struct drm_i915_private *dev_priv,
76 enum transcoder dsi_trans, int payld_credit)
78 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
80 drm_err(&dev_priv->drm, "DSI payload credits not released\n");
87 static enum transcoder dsi_port_to_transcoder(enum port port)
90 return TRANSCODER_DSI_0;
92 return TRANSCODER_DSI_1;
95 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
97 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
98 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
99 struct mipi_dsi_device *dsi;
101 enum transcoder dsi_trans;
104 /* wait for header/payload credits to be released */
105 for_each_dsi_port(port, intel_dsi->ports) {
106 dsi_trans = dsi_port_to_transcoder(port);
107 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
108 wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT);
111 /* send nop DCS command */
112 for_each_dsi_port(port, intel_dsi->ports) {
113 dsi = intel_dsi->dsi_hosts[port]->device;
114 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
116 ret = mipi_dsi_dcs_nop(dsi);
118 drm_err(&dev_priv->drm,
119 "error sending DCS NOP command\n");
122 /* wait for header credits to be released */
123 for_each_dsi_port(port, intel_dsi->ports) {
124 dsi_trans = dsi_port_to_transcoder(port);
125 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
128 /* wait for LP TX in progress bit to be cleared */
129 for_each_dsi_port(port, intel_dsi->ports) {
130 dsi_trans = dsi_port_to_transcoder(port);
131 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
132 LPTX_IN_PROGRESS), 20))
133 drm_err(&dev_priv->drm, "LPTX bit not cleared\n");
137 static int dsi_send_pkt_payld(struct intel_dsi_host *host,
138 const struct mipi_dsi_packet *packet)
140 struct intel_dsi *intel_dsi = host->intel_dsi;
141 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
142 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
143 const u8 *data = packet->payload;
144 u32 len = packet->payload_length;
147 /* payload queue can accept *256 bytes*, check limit */
148 if (len > MAX_PLOAD_CREDIT * 4) {
149 drm_err(&i915->drm, "payload size exceeds max queue limit\n");
153 for (i = 0; i < len; i += 4) {
156 if (!wait_for_payload_credits(i915, dsi_trans, 1))
159 for (j = 0; j < min_t(u32, len - i, 4); j++)
160 tmp |= *data++ << 8 * j;
162 intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp);
168 static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
169 const struct mipi_dsi_packet *packet,
172 struct intel_dsi *intel_dsi = host->intel_dsi;
173 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
174 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
177 if (!wait_for_header_credits(dev_priv, dsi_trans, 1))
180 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans));
183 tmp |= PAYLOAD_PRESENT;
185 tmp &= ~PAYLOAD_PRESENT;
187 tmp &= ~VBLANK_FENCE;
190 tmp |= LP_DATA_TRANSFER;
192 tmp &= ~LP_DATA_TRANSFER;
194 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
195 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT);
196 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT);
197 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT);
198 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT);
199 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp);
204 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
206 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
207 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
211 mode_flags = crtc_state->mode_flags;
214 * case 1 also covers dual link
215 * In case of dual link, frame update should be set on
218 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0)
220 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1)
225 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port));
226 tmp |= DSI_FRAME_UPDATE_REQUEST;
227 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp);
230 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
232 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
233 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
238 for_each_dsi_phy(phy, intel_dsi->phys) {
240 * Program voltage swing and pre-emphasis level values as per
241 * table in BSPEC under DDI buffer programing
243 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
244 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
245 tmp |= SCALING_MODE_SEL(0x2);
246 tmp |= TAP2_DISABLE | TAP3_DISABLE;
247 tmp |= RTERM_SELECT(0x6);
248 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
250 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
251 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
252 tmp |= SCALING_MODE_SEL(0x2);
253 tmp |= TAP2_DISABLE | TAP3_DISABLE;
254 tmp |= RTERM_SELECT(0x6);
255 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
257 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
258 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
260 tmp |= SWING_SEL_UPPER(0x2);
261 tmp |= SWING_SEL_LOWER(0x2);
262 tmp |= RCOMP_SCALAR(0x98);
263 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
265 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy));
266 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
268 tmp |= SWING_SEL_UPPER(0x2);
269 tmp |= SWING_SEL_LOWER(0x2);
270 tmp |= RCOMP_SCALAR(0x98);
271 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp);
273 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy));
274 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
276 tmp |= POST_CURSOR_1(0x0);
277 tmp |= POST_CURSOR_2(0x0);
278 tmp |= CURSOR_COEFF(0x3f);
279 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp);
281 for (lane = 0; lane <= 3; lane++) {
282 /* Bspec: must not use GRP register for write */
283 tmp = intel_de_read(dev_priv,
284 ICL_PORT_TX_DW4_LN(lane, phy));
285 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
287 tmp |= POST_CURSOR_1(0x0);
288 tmp |= POST_CURSOR_2(0x0);
289 tmp |= CURSOR_COEFF(0x3f);
290 intel_de_write(dev_priv,
291 ICL_PORT_TX_DW4_LN(lane, phy), tmp);
296 static void configure_dual_link_mode(struct intel_encoder *encoder,
297 const struct intel_crtc_state *pipe_config)
299 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
300 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
303 dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1);
304 dss_ctl1 |= SPLITTER_ENABLE;
305 dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
306 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
308 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
309 const struct drm_display_mode *adjusted_mode =
310 &pipe_config->hw.adjusted_mode;
312 u16 hactive = adjusted_mode->crtc_hdisplay;
315 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
316 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
318 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
319 drm_err(&dev_priv->drm,
320 "DL buffer depth exceed max value\n");
322 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
323 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
324 dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2);
325 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK;
326 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
327 intel_de_write(dev_priv, DSS_CTL2, dss_ctl2);
330 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
333 intel_de_write(dev_priv, DSS_CTL1, dss_ctl1);
336 /* aka DSI 8X clock */
337 static int afe_clk(struct intel_encoder *encoder,
338 const struct intel_crtc_state *crtc_state)
340 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
343 if (crtc_state->dsc.compression_enable)
344 bpp = crtc_state->dsc.compressed_bpp;
346 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
348 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
351 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
352 const struct intel_crtc_state *crtc_state)
354 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
355 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
358 int theo_word_clk, act_word_clk;
359 u32 esc_clk_div_m, esc_clk_div_m_phy;
361 afe_clk_khz = afe_clk(encoder, crtc_state);
363 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
364 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK);
365 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2);
366 esc_clk_div_m = act_word_clk * 8;
367 esc_clk_div_m_phy = (act_word_clk - 1) / 2;
369 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
372 for_each_dsi_port(port, intel_dsi->ports) {
373 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port),
374 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
375 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port));
378 for_each_dsi_port(port, intel_dsi->ports) {
379 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port),
380 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
381 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port));
384 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
385 for_each_dsi_port(port, intel_dsi->ports) {
386 intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8),
387 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY);
388 intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8));
393 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
394 struct intel_dsi *intel_dsi)
398 for_each_dsi_port(port, intel_dsi->ports) {
399 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]);
400 intel_dsi->io_wakeref[port] =
401 intel_display_power_get(dev_priv,
403 POWER_DOMAIN_PORT_DDI_IO_A :
404 POWER_DOMAIN_PORT_DDI_IO_B);
408 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
410 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
411 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
415 for_each_dsi_port(port, intel_dsi->ports) {
416 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port));
417 tmp |= COMBO_PHY_MODE_DSI;
418 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp);
421 get_dsi_io_power_domains(dev_priv, intel_dsi);
424 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
426 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
427 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
430 for_each_dsi_phy(phy, intel_dsi->phys)
431 intel_combo_phy_power_up_lanes(dev_priv, phy, true,
432 intel_dsi->lane_count, false);
435 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
437 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
438 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
443 /* Step 4b(i) set loadgen select for transmit and aux lanes */
444 for_each_dsi_phy(phy, intel_dsi->phys) {
445 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy));
446 tmp &= ~LOADGEN_SELECT;
447 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp);
448 for (lane = 0; lane <= 3; lane++) {
449 tmp = intel_de_read(dev_priv,
450 ICL_PORT_TX_DW4_LN(lane, phy));
451 tmp &= ~LOADGEN_SELECT;
453 tmp |= LOADGEN_SELECT;
454 intel_de_write(dev_priv,
455 ICL_PORT_TX_DW4_LN(lane, phy), tmp);
459 /* Step 4b(ii) set latency optimization for transmit and aux lanes */
460 for_each_dsi_phy(phy, intel_dsi->phys) {
461 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy));
462 tmp &= ~FRC_LATENCY_OPTIM_MASK;
463 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
464 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp);
465 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
466 tmp &= ~FRC_LATENCY_OPTIM_MASK;
467 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
468 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
470 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
471 if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
472 tmp = intel_de_read(dev_priv,
473 ICL_PORT_PCS_DW1_AUX(phy));
474 tmp &= ~LATENCY_OPTIM_MASK;
475 tmp |= LATENCY_OPTIM_VAL(0);
476 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
479 tmp = intel_de_read(dev_priv,
480 ICL_PORT_PCS_DW1_LN(0, phy));
481 tmp &= ~LATENCY_OPTIM_MASK;
482 tmp |= LATENCY_OPTIM_VAL(0x1);
483 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy),
490 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
492 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
493 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
497 /* clear common keeper enable bit */
498 for_each_dsi_phy(phy, intel_dsi->phys) {
499 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
500 tmp &= ~COMMON_KEEPER_EN;
501 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp);
502 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy));
503 tmp &= ~COMMON_KEEPER_EN;
504 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), tmp);
508 * Set SUS Clock Config bitfield to 11b
509 * Note: loadgen select program is done
510 * as part of lane phy sequence configuration
512 for_each_dsi_phy(phy, intel_dsi->phys) {
513 tmp = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
514 tmp |= SUS_CLOCK_CONFIG;
515 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), tmp);
518 /* Clear training enable to change swing values */
519 for_each_dsi_phy(phy, intel_dsi->phys) {
520 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
521 tmp &= ~TX_TRAINING_EN;
522 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
523 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
524 tmp &= ~TX_TRAINING_EN;
525 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
528 /* Program swing and de-emphasis */
529 dsi_program_swing_and_deemphasis(encoder);
531 /* Set training enable to trigger update */
532 for_each_dsi_phy(phy, intel_dsi->phys) {
533 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
534 tmp |= TX_TRAINING_EN;
535 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
536 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
537 tmp |= TX_TRAINING_EN;
538 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
542 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
544 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
545 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
549 for_each_dsi_port(port, intel_dsi->ports) {
550 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
551 tmp |= DDI_BUF_CTL_ENABLE;
552 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp);
554 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
557 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
563 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
564 const struct intel_crtc_state *crtc_state)
566 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
567 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
572 /* Program T-INIT master registers */
573 for_each_dsi_port(port, intel_dsi->ports) {
574 tmp = intel_de_read(dev_priv, ICL_DSI_T_INIT_MASTER(port));
575 tmp &= ~DSI_T_INIT_MASTER_MASK;
576 tmp |= intel_dsi->init_count;
577 intel_de_write(dev_priv, ICL_DSI_T_INIT_MASTER(port), tmp);
580 /* Program DPHY clock lanes timings */
581 for_each_dsi_port(port, intel_dsi->ports) {
582 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port),
583 intel_dsi->dphy_reg);
585 /* shadow register inside display core */
586 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port),
587 intel_dsi->dphy_reg);
590 /* Program DPHY data lanes timings */
591 for_each_dsi_port(port, intel_dsi->ports) {
592 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port),
593 intel_dsi->dphy_data_lane_reg);
595 /* shadow register inside display core */
596 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port),
597 intel_dsi->dphy_data_lane_reg);
601 * If DSI link operating at or below an 800 MHz,
602 * TA_SURE should be override and programmed to
603 * a value '0' inside TA_PARAM_REGISTERS otherwise
604 * leave all fields at HW default values.
606 if (DISPLAY_VER(dev_priv) == 11) {
607 if (afe_clk(encoder, crtc_state) <= 800000) {
608 for_each_dsi_port(port, intel_dsi->ports) {
609 tmp = intel_de_read(dev_priv,
610 DPHY_TA_TIMING_PARAM(port));
611 tmp &= ~TA_SURE_MASK;
612 tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
613 intel_de_write(dev_priv,
614 DPHY_TA_TIMING_PARAM(port),
617 /* shadow register inside display core */
618 tmp = intel_de_read(dev_priv,
619 DSI_TA_TIMING_PARAM(port));
620 tmp &= ~TA_SURE_MASK;
621 tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
622 intel_de_write(dev_priv,
623 DSI_TA_TIMING_PARAM(port), tmp);
628 if (IS_JSL_EHL(dev_priv)) {
629 for_each_dsi_phy(phy, intel_dsi->phys) {
630 tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy));
631 tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
632 intel_de_write(dev_priv, ICL_DPHY_CHKN(phy), tmp);
637 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
639 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
640 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
644 mutex_lock(&dev_priv->dpll.lock);
645 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
646 for_each_dsi_phy(phy, intel_dsi->phys)
647 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
649 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
650 mutex_unlock(&dev_priv->dpll.lock);
653 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
655 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
656 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
660 mutex_lock(&dev_priv->dpll.lock);
661 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
662 for_each_dsi_phy(phy, intel_dsi->phys)
663 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
665 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
666 mutex_unlock(&dev_priv->dpll.lock);
669 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
671 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
672 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
673 bool clock_enabled = false;
677 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
679 for_each_dsi_phy(phy, intel_dsi->phys) {
680 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)))
681 clock_enabled = true;
684 return clock_enabled;
687 static void gen11_dsi_map_pll(struct intel_encoder *encoder,
688 const struct intel_crtc_state *crtc_state)
690 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
691 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
692 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
696 mutex_lock(&dev_priv->dpll.lock);
698 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
699 for_each_dsi_phy(phy, intel_dsi->phys) {
700 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
701 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
703 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
705 for_each_dsi_phy(phy, intel_dsi->phys) {
706 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
708 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
710 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
712 mutex_unlock(&dev_priv->dpll.lock);
716 gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
717 const struct intel_crtc_state *pipe_config)
719 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
720 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
721 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
722 enum pipe pipe = crtc->pipe;
725 enum transcoder dsi_trans;
727 for_each_dsi_port(port, intel_dsi->ports) {
728 dsi_trans = dsi_port_to_transcoder(port);
729 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
731 if (intel_dsi->eotp_pkt)
732 tmp &= ~EOTP_DISABLED;
734 tmp |= EOTP_DISABLED;
736 /* enable link calibration if freq > 1.5Gbps */
737 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
738 tmp &= ~LINK_CALIBRATION_MASK;
739 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
742 /* configure continuous clock */
743 tmp &= ~CONTINUOUS_CLK_MASK;
744 if (intel_dsi->clock_stop)
745 tmp |= CLK_ENTER_LP_AFTER_DATA;
747 tmp |= CLK_HS_CONTINUOUS;
749 /* configure buffer threshold limit to minimum */
750 tmp &= ~PIX_BUF_THRESHOLD_MASK;
751 tmp |= PIX_BUF_THRESHOLD_1_4;
753 /* set virtual channel to '0' */
754 tmp &= ~PIX_VIRT_CHAN_MASK;
755 tmp |= PIX_VIRT_CHAN(0);
757 /* program BGR transmission */
758 if (intel_dsi->bgr_enabled)
759 tmp |= BGR_TRANSMISSION;
761 /* select pixel format */
762 tmp &= ~PIX_FMT_MASK;
763 if (pipe_config->dsc.compression_enable) {
764 tmp |= PIX_FMT_COMPRESSED;
766 switch (intel_dsi->pixel_format) {
768 MISSING_CASE(intel_dsi->pixel_format);
770 case MIPI_DSI_FMT_RGB565:
771 tmp |= PIX_FMT_RGB565;
773 case MIPI_DSI_FMT_RGB666_PACKED:
774 tmp |= PIX_FMT_RGB666_PACKED;
776 case MIPI_DSI_FMT_RGB666:
777 tmp |= PIX_FMT_RGB666_LOOSE;
779 case MIPI_DSI_FMT_RGB888:
780 tmp |= PIX_FMT_RGB888;
785 if (DISPLAY_VER(dev_priv) >= 12) {
786 if (is_vid_mode(intel_dsi))
787 tmp |= BLANKING_PACKET_ENABLE;
790 /* program DSI operation mode */
791 if (is_vid_mode(intel_dsi)) {
792 tmp &= ~OP_MODE_MASK;
793 switch (intel_dsi->video_mode) {
795 MISSING_CASE(intel_dsi->video_mode);
797 case NON_BURST_SYNC_EVENTS:
798 tmp |= VIDEO_MODE_SYNC_EVENT;
800 case NON_BURST_SYNC_PULSE:
801 tmp |= VIDEO_MODE_SYNC_PULSE;
806 * FIXME: Retrieve this info from VBT.
807 * As per the spec when dsi transcoder is operating
808 * in TE GATE mode, TE comes from GPIO
809 * which is UTIL PIN for DSI 0.
810 * Also this GPIO would not be used for other
811 * purposes is an assumption.
813 tmp &= ~OP_MODE_MASK;
814 tmp |= CMD_MODE_TE_GATE;
815 tmp |= TE_SOURCE_GPIO;
818 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
821 /* enable port sync mode if dual link */
822 if (intel_dsi->dual_link) {
823 for_each_dsi_port(port, intel_dsi->ports) {
824 dsi_trans = dsi_port_to_transcoder(port);
825 tmp = intel_de_read(dev_priv,
826 TRANS_DDI_FUNC_CTL2(dsi_trans));
827 tmp |= PORT_SYNC_MODE_ENABLE;
828 intel_de_write(dev_priv,
829 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
832 /* configure stream splitting */
833 configure_dual_link_mode(encoder, pipe_config);
836 for_each_dsi_port(port, intel_dsi->ports) {
837 dsi_trans = dsi_port_to_transcoder(port);
839 /* select data lane width */
840 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
841 tmp &= ~DDI_PORT_WIDTH_MASK;
842 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
844 /* select input pipe */
845 tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
851 tmp |= TRANS_DDI_EDP_INPUT_A_ON;
854 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
857 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
860 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
864 /* enable DDI buffer */
865 tmp |= TRANS_DDI_FUNC_ENABLE;
866 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
869 /* wait for link ready */
870 for_each_dsi_port(port, intel_dsi->ports) {
871 dsi_trans = dsi_port_to_transcoder(port);
872 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) &
874 drm_err(&dev_priv->drm, "DSI link not ready\n");
879 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
880 const struct intel_crtc_state *crtc_state)
882 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
883 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
884 const struct drm_display_mode *adjusted_mode =
885 &crtc_state->hw.adjusted_mode;
887 enum transcoder dsi_trans;
888 /* horizontal timings */
889 u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
891 /* vertical timings */
892 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
893 int mul = 1, div = 1;
896 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account
897 * for slower link speed if DSC is enabled.
899 * The compression frequency ratio is the ratio between compressed and
900 * non-compressed link speeds, and simplifies down to the ratio between
901 * compressed and non-compressed bpp.
903 if (crtc_state->dsc.compression_enable) {
904 mul = crtc_state->dsc.compressed_bpp;
905 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
908 hactive = adjusted_mode->crtc_hdisplay;
910 if (is_vid_mode(intel_dsi))
911 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
913 htotal = DIV_ROUND_UP((hactive + 160) * mul, div);
915 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
916 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
917 hsync_size = hsync_end - hsync_start;
918 hback_porch = (adjusted_mode->crtc_htotal -
919 adjusted_mode->crtc_hsync_end);
920 vactive = adjusted_mode->crtc_vdisplay;
922 if (is_vid_mode(intel_dsi)) {
923 vtotal = adjusted_mode->crtc_vtotal;
925 int bpp, line_time_us, byte_clk_period_ns;
927 if (crtc_state->dsc.compression_enable)
928 bpp = crtc_state->dsc.compressed_bpp;
930 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
932 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state);
933 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);
934 vtotal = vactive + DIV_ROUND_UP(400, line_time_us);
936 vsync_start = adjusted_mode->crtc_vsync_start;
937 vsync_end = adjusted_mode->crtc_vsync_end;
938 vsync_shift = hsync_start - htotal / 2;
940 if (intel_dsi->dual_link) {
942 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
943 hactive += intel_dsi->pixel_overlap;
947 /* minimum hactive as per bspec: 256 pixels */
948 if (adjusted_mode->crtc_hdisplay < 256)
949 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n");
951 /* if RGB666 format, then hactive must be multiple of 4 pixels */
952 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
953 drm_err(&dev_priv->drm,
954 "hactive pixels are not multiple of 4\n");
956 /* program TRANS_HTOTAL register */
957 for_each_dsi_port(port, intel_dsi->ports) {
958 dsi_trans = dsi_port_to_transcoder(port);
959 intel_de_write(dev_priv, HTOTAL(dsi_trans),
960 (hactive - 1) | ((htotal - 1) << 16));
963 /* TRANS_HSYNC register to be programmed only for video mode */
964 if (is_vid_mode(intel_dsi)) {
965 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) {
966 /* BSPEC: hsync size should be atleast 16 pixels */
968 drm_err(&dev_priv->drm,
969 "hsync size < 16 pixels\n");
972 if (hback_porch < 16)
973 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n");
975 if (intel_dsi->dual_link) {
980 for_each_dsi_port(port, intel_dsi->ports) {
981 dsi_trans = dsi_port_to_transcoder(port);
982 intel_de_write(dev_priv, HSYNC(dsi_trans),
983 (hsync_start - 1) | ((hsync_end - 1) << 16));
987 /* program TRANS_VTOTAL register */
988 for_each_dsi_port(port, intel_dsi->ports) {
989 dsi_trans = dsi_port_to_transcoder(port);
991 * FIXME: Programing this by assuming progressive mode, since
992 * non-interlaced info from VBT is not saved inside
993 * struct drm_display_mode.
994 * For interlace mode: program required pixel minus 2
996 intel_de_write(dev_priv, VTOTAL(dsi_trans),
997 (vactive - 1) | ((vtotal - 1) << 16));
1000 if (vsync_end < vsync_start || vsync_end > vtotal)
1001 drm_err(&dev_priv->drm, "Invalid vsync_end value\n");
1003 if (vsync_start < vactive)
1004 drm_err(&dev_priv->drm, "vsync_start less than vactive\n");
1006 /* program TRANS_VSYNC register for video mode only */
1007 if (is_vid_mode(intel_dsi)) {
1008 for_each_dsi_port(port, intel_dsi->ports) {
1009 dsi_trans = dsi_port_to_transcoder(port);
1010 intel_de_write(dev_priv, VSYNC(dsi_trans),
1011 (vsync_start - 1) | ((vsync_end - 1) << 16));
1016 * FIXME: It has to be programmed only for video modes and interlaced
1017 * modes. Put the check condition here once interlaced
1018 * info available as described above.
1019 * program TRANS_VSYNCSHIFT register
1021 if (is_vid_mode(intel_dsi)) {
1022 for_each_dsi_port(port, intel_dsi->ports) {
1023 dsi_trans = dsi_port_to_transcoder(port);
1024 intel_de_write(dev_priv, VSYNCSHIFT(dsi_trans),
1029 /* program TRANS_VBLANK register, should be same as vtotal programmed */
1030 if (DISPLAY_VER(dev_priv) >= 12) {
1031 for_each_dsi_port(port, intel_dsi->ports) {
1032 dsi_trans = dsi_port_to_transcoder(port);
1033 intel_de_write(dev_priv, VBLANK(dsi_trans),
1034 (vactive - 1) | ((vtotal - 1) << 16));
1039 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
1041 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1042 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1044 enum transcoder dsi_trans;
1047 for_each_dsi_port(port, intel_dsi->ports) {
1048 dsi_trans = dsi_port_to_transcoder(port);
1049 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans));
1050 tmp |= PIPECONF_ENABLE;
1051 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp);
1053 /* wait for transcoder to be enabled */
1054 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),
1055 PIPECONF_STATE_ENABLE, 10))
1056 drm_err(&dev_priv->drm,
1057 "DSI transcoder not enabled\n");
1061 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
1062 const struct intel_crtc_state *crtc_state)
1064 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1065 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1067 enum transcoder dsi_trans;
1068 u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
1071 * escape clock count calculation:
1072 * BYTE_CLK_COUNT = TIME_NS/(8 * UI)
1073 * UI (nsec) = (10^6)/Bitrate
1074 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
1075 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
1077 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000;
1079 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
1081 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
1082 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
1084 for_each_dsi_port(port, intel_dsi->ports) {
1085 dsi_trans = dsi_port_to_transcoder(port);
1087 /* program hst_tx_timeout */
1088 tmp = intel_de_read(dev_priv, DSI_HSTX_TO(dsi_trans));
1089 tmp &= ~HSTX_TIMEOUT_VALUE_MASK;
1090 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout);
1091 intel_de_write(dev_priv, DSI_HSTX_TO(dsi_trans), tmp);
1093 /* FIXME: DSI_CALIB_TO */
1095 /* program lp_rx_host timeout */
1096 tmp = intel_de_read(dev_priv, DSI_LPRX_HOST_TO(dsi_trans));
1097 tmp &= ~LPRX_TIMEOUT_VALUE_MASK;
1098 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout);
1099 intel_de_write(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), tmp);
1101 /* FIXME: DSI_PWAIT_TO */
1103 /* program turn around timeout */
1104 tmp = intel_de_read(dev_priv, DSI_TA_TO(dsi_trans));
1105 tmp &= ~TA_TIMEOUT_VALUE_MASK;
1106 tmp |= TA_TIMEOUT_VALUE(ta_timeout);
1107 intel_de_write(dev_priv, DSI_TA_TO(dsi_trans), tmp);
1111 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
1114 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1115 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1119 * used as TE i/p for DSI0,
1120 * for dual link/DSI1 TE is from slave DSI1
1123 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
1126 tmp = intel_de_read(dev_priv, UTIL_PIN_CTL);
1129 tmp |= UTIL_PIN_DIRECTION_INPUT;
1130 tmp |= UTIL_PIN_ENABLE;
1132 tmp &= ~UTIL_PIN_ENABLE;
1134 intel_de_write(dev_priv, UTIL_PIN_CTL, tmp);
1138 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
1139 const struct intel_crtc_state *crtc_state)
1141 /* step 4a: power up all lanes of the DDI used by DSI */
1142 gen11_dsi_power_up_lanes(encoder);
1144 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */
1145 gen11_dsi_config_phy_lanes_sequence(encoder);
1147 /* step 4c: configure voltage swing and skew */
1148 gen11_dsi_voltage_swing_program_seq(encoder);
1150 /* enable DDI buffer */
1151 gen11_dsi_enable_ddi_buffer(encoder);
1153 /* setup D-PHY timings */
1154 gen11_dsi_setup_dphy_timings(encoder, crtc_state);
1156 /* Since transcoder is configured to take events from GPIO */
1157 gen11_dsi_config_util_pin(encoder, true);
1159 /* step 4h: setup DSI protocol timeouts */
1160 gen11_dsi_setup_timeouts(encoder, crtc_state);
1162 /* Step (4h, 4i, 4j, 4k): Configure transcoder */
1163 gen11_dsi_configure_transcoder(encoder, crtc_state);
1165 /* Step 4l: Gate DDI clocks */
1166 gen11_dsi_gate_clocks(encoder);
1169 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
1171 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1172 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1173 struct mipi_dsi_device *dsi;
1175 enum transcoder dsi_trans;
1179 /* set maximum return packet size */
1180 for_each_dsi_port(port, intel_dsi->ports) {
1181 dsi_trans = dsi_port_to_transcoder(port);
1184 * FIXME: This uses the number of DW's currently in the payload
1185 * receive queue. This is probably not what we want here.
1187 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans));
1188 tmp &= NUMBER_RX_PLOAD_DW_MASK;
1189 /* multiply "Number Rx Payload DW" by 4 to get max value */
1191 dsi = intel_dsi->dsi_hosts[port]->device;
1192 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
1194 drm_err(&dev_priv->drm,
1195 "error setting max return pkt size%d\n", tmp);
1198 /* panel power on related mipi dsi vbt sequences */
1199 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
1200 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
1201 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
1202 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
1203 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
1205 /* ensure all panel commands dispatched before enabling transcoder */
1206 wait_for_cmds_dispatched_to_panel(encoder);
1209 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state,
1210 struct intel_encoder *encoder,
1211 const struct intel_crtc_state *crtc_state,
1212 const struct drm_connector_state *conn_state)
1214 /* step2: enable IO power */
1215 gen11_dsi_enable_io_power(encoder);
1217 /* step3: enable DSI PLL */
1218 gen11_dsi_program_esc_clk_div(encoder, crtc_state);
1221 static void gen11_dsi_pre_enable(struct intel_atomic_state *state,
1222 struct intel_encoder *encoder,
1223 const struct intel_crtc_state *pipe_config,
1224 const struct drm_connector_state *conn_state)
1227 gen11_dsi_map_pll(encoder, pipe_config);
1229 /* step4: enable DSI port and DPHY */
1230 gen11_dsi_enable_port_and_phy(encoder, pipe_config);
1232 /* step5: program and powerup panel */
1233 gen11_dsi_powerup_panel(encoder);
1235 intel_dsc_dsi_pps_write(encoder, pipe_config);
1237 /* step6c: configure transcoder timings */
1238 gen11_dsi_set_transcoder_timings(encoder, pipe_config);
1242 * Wa_1409054076:icl,jsl,ehl
1243 * When pipe A is disabled and MIPI DSI is enabled on pipe B,
1244 * the AMT KVMR feature will incorrectly see pipe A as enabled.
1245 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave
1246 * it set while DSI is enabled on pipe B
1248 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder,
1249 enum pipe pipe, bool enable)
1251 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1253 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B)
1254 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
1256 enable ? IGNORE_KVMR_PIPE_A : 0);
1260 * Wa_16012360555:adl-p
1261 * SW will have to program the "LP to HS Wakeup Guardband"
1262 * to account for the repeaters on the HS Request/Ready
1263 * PPI signaling between the Display engine and the DPHY.
1265 static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
1267 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1268 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1271 if (DISPLAY_VER(i915) == 13) {
1272 for_each_dsi_port(port, intel_dsi->ports)
1273 intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
1274 TGL_DSI_CHKN_LSHS_GB_MASK,
1275 TGL_DSI_CHKN_LSHS_GB(4));
1279 static void gen11_dsi_enable(struct intel_atomic_state *state,
1280 struct intel_encoder *encoder,
1281 const struct intel_crtc_state *crtc_state,
1282 const struct drm_connector_state *conn_state)
1284 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1285 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
1287 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
1289 /* Wa_1409054076:icl,jsl,ehl */
1290 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true);
1292 /* Wa_16012360555:adl-p */
1293 adlp_set_lp_hs_wakeup_gb(encoder);
1295 /* step6d: enable dsi transcoder */
1296 gen11_dsi_enable_transcoder(encoder);
1298 /* step7: enable backlight */
1299 intel_backlight_enable(crtc_state, conn_state);
1300 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
1302 intel_crtc_vblank_on(crtc_state);
1305 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
1307 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1308 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1310 enum transcoder dsi_trans;
1313 for_each_dsi_port(port, intel_dsi->ports) {
1314 dsi_trans = dsi_port_to_transcoder(port);
1316 /* disable transcoder */
1317 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans));
1318 tmp &= ~PIPECONF_ENABLE;
1319 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp);
1321 /* wait for transcoder to be disabled */
1322 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),
1323 PIPECONF_STATE_ENABLE, 50))
1324 drm_err(&dev_priv->drm,
1325 "DSI trancoder not disabled\n");
1329 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
1331 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1333 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
1334 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1335 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1337 /* ensure cmds dispatched to panel */
1338 wait_for_cmds_dispatched_to_panel(encoder);
1341 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
1343 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1344 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1346 enum transcoder dsi_trans;
1349 /* disable periodic update mode */
1350 if (is_cmd_mode(intel_dsi)) {
1351 for_each_dsi_port(port, intel_dsi->ports) {
1352 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port));
1353 tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
1354 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp);
1358 /* put dsi link in ULPS */
1359 for_each_dsi_port(port, intel_dsi->ports) {
1360 dsi_trans = dsi_port_to_transcoder(port);
1361 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans));
1362 tmp |= LINK_ENTER_ULPS;
1363 tmp &= ~LINK_ULPS_TYPE_LP11;
1364 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp);
1366 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
1369 drm_err(&dev_priv->drm, "DSI link not in ULPS\n");
1372 /* disable ddi function */
1373 for_each_dsi_port(port, intel_dsi->ports) {
1374 dsi_trans = dsi_port_to_transcoder(port);
1375 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
1376 tmp &= ~TRANS_DDI_FUNC_ENABLE;
1377 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
1380 /* disable port sync mode if dual link */
1381 if (intel_dsi->dual_link) {
1382 for_each_dsi_port(port, intel_dsi->ports) {
1383 dsi_trans = dsi_port_to_transcoder(port);
1384 tmp = intel_de_read(dev_priv,
1385 TRANS_DDI_FUNC_CTL2(dsi_trans));
1386 tmp &= ~PORT_SYNC_MODE_ENABLE;
1387 intel_de_write(dev_priv,
1388 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
1393 static void gen11_dsi_disable_port(struct intel_encoder *encoder)
1395 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1396 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1400 gen11_dsi_ungate_clocks(encoder);
1401 for_each_dsi_port(port, intel_dsi->ports) {
1402 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
1403 tmp &= ~DDI_BUF_CTL_ENABLE;
1404 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp);
1406 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1409 drm_err(&dev_priv->drm,
1410 "DDI port:%c buffer not idle\n",
1413 gen11_dsi_gate_clocks(encoder);
1416 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
1418 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1419 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1423 for_each_dsi_port(port, intel_dsi->ports) {
1424 intel_wakeref_t wakeref;
1426 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
1427 intel_display_power_put(dev_priv,
1429 POWER_DOMAIN_PORT_DDI_IO_A :
1430 POWER_DOMAIN_PORT_DDI_IO_B,
1434 /* set mode to DDI */
1435 for_each_dsi_port(port, intel_dsi->ports) {
1436 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port));
1437 tmp &= ~COMBO_PHY_MODE_DSI;
1438 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp);
1442 static void gen11_dsi_disable(struct intel_atomic_state *state,
1443 struct intel_encoder *encoder,
1444 const struct intel_crtc_state *old_crtc_state,
1445 const struct drm_connector_state *old_conn_state)
1447 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1448 struct intel_crtc *crtc = to_intel_crtc(old_conn_state->crtc);
1450 /* step1: turn off backlight */
1451 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
1452 intel_backlight_disable(old_conn_state);
1454 /* step2d,e: disable transcoder and wait */
1455 gen11_dsi_disable_transcoder(encoder);
1457 /* Wa_1409054076:icl,jsl,ehl */
1458 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false);
1460 /* step2f,g: powerdown panel */
1461 gen11_dsi_powerdown_panel(encoder);
1463 /* step2h,i,j: deconfig trancoder */
1464 gen11_dsi_deconfigure_trancoder(encoder);
1466 /* step3: disable port */
1467 gen11_dsi_disable_port(encoder);
1469 gen11_dsi_config_util_pin(encoder, false);
1471 /* step4: disable IO power */
1472 gen11_dsi_disable_io_power(encoder);
1475 static void gen11_dsi_post_disable(struct intel_atomic_state *state,
1476 struct intel_encoder *encoder,
1477 const struct intel_crtc_state *old_crtc_state,
1478 const struct drm_connector_state *old_conn_state)
1480 intel_crtc_vblank_off(old_crtc_state);
1482 intel_dsc_disable(old_crtc_state);
1484 skl_scaler_disable(old_crtc_state);
1487 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,
1488 struct drm_display_mode *mode)
1491 return intel_dsi_mode_valid(connector, mode);
1494 static void gen11_dsi_get_timings(struct intel_encoder *encoder,
1495 struct intel_crtc_state *pipe_config)
1497 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1498 struct drm_display_mode *adjusted_mode =
1499 &pipe_config->hw.adjusted_mode;
1501 if (pipe_config->dsc.compressed_bpp) {
1502 int div = pipe_config->dsc.compressed_bpp;
1503 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1505 adjusted_mode->crtc_htotal =
1506 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
1507 adjusted_mode->crtc_hsync_start =
1508 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
1509 adjusted_mode->crtc_hsync_end =
1510 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
1513 if (intel_dsi->dual_link) {
1514 adjusted_mode->crtc_hdisplay *= 2;
1515 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1516 adjusted_mode->crtc_hdisplay -=
1517 intel_dsi->pixel_overlap;
1518 adjusted_mode->crtc_htotal *= 2;
1520 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1521 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1523 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
1524 if (intel_dsi->dual_link) {
1525 adjusted_mode->crtc_hsync_start *= 2;
1526 adjusted_mode->crtc_hsync_end *= 2;
1529 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1530 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1533 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
1535 struct drm_device *dev = intel_dsi->base.base.dev;
1536 struct drm_i915_private *dev_priv = to_i915(dev);
1537 enum transcoder dsi_trans;
1540 if (intel_dsi->ports == BIT(PORT_B))
1541 dsi_trans = TRANSCODER_DSI_1;
1543 dsi_trans = TRANSCODER_DSI_0;
1545 val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
1546 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
1549 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi,
1550 struct intel_crtc_state *pipe_config)
1552 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A)))
1553 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 |
1554 I915_MODE_FLAG_DSI_USE_TE0;
1555 else if (intel_dsi->ports == BIT(PORT_B))
1556 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1;
1558 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0;
1561 static void gen11_dsi_get_config(struct intel_encoder *encoder,
1562 struct intel_crtc_state *pipe_config)
1564 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1565 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1567 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder));
1569 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
1570 if (intel_dsi->dual_link)
1571 pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1573 gen11_dsi_get_timings(encoder, pipe_config);
1574 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1575 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
1577 /* Get the details on which TE should be enabled */
1578 if (is_cmd_mode(intel_dsi))
1579 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1581 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi))
1582 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
1585 static void gen11_dsi_sync_state(struct intel_encoder *encoder,
1586 const struct intel_crtc_state *crtc_state)
1588 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1589 struct intel_crtc *intel_crtc;
1595 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1596 pipe = intel_crtc->pipe;
1598 /* wa verify 1409054076:icl,jsl,ehl */
1599 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B &&
1600 !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
1601 drm_dbg_kms(&dev_priv->drm,
1602 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n",
1603 encoder->base.base.id,
1604 encoder->base.name);
1607 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
1608 struct intel_crtc_state *crtc_state)
1610 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1611 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1612 int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10;
1616 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc);
1620 if (crtc_state->pipe_bpp < 8 * 3)
1623 /* FIXME: split only when necessary */
1624 if (crtc_state->dsc.slice_count > 1)
1625 crtc_state->dsc.dsc_split = true;
1627 vdsc_cfg->convert_rgb = true;
1629 /* FIXME: initialize from VBT */
1630 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1632 ret = intel_dsc_compute_params(crtc_state);
1636 /* DSI specific sanity checks on the common code */
1637 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable);
1638 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422);
1639 drm_WARN_ON(&dev_priv->drm,
1640 vdsc_cfg->pic_width % vdsc_cfg->slice_width);
1641 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8);
1642 drm_WARN_ON(&dev_priv->drm,
1643 vdsc_cfg->pic_height % vdsc_cfg->slice_height);
1645 ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
1649 crtc_state->dsc.compression_enable = true;
1654 static int gen11_dsi_compute_config(struct intel_encoder *encoder,
1655 struct intel_crtc_state *pipe_config,
1656 struct drm_connector_state *conn_state)
1658 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1659 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
1661 struct intel_connector *intel_connector = intel_dsi->attached_connector;
1662 struct drm_display_mode *adjusted_mode =
1663 &pipe_config->hw.adjusted_mode;
1666 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1668 ret = intel_panel_compute_config(intel_connector, adjusted_mode);
1672 ret = intel_panel_fitting(pipe_config, conn_state);
1676 adjusted_mode->flags = 0;
1678 /* Dual link goes to trancoder DSI'0' */
1679 if (intel_dsi->ports == BIT(PORT_B))
1680 pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
1682 pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
1684 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
1685 pipe_config->pipe_bpp = 24;
1687 pipe_config->pipe_bpp = 18;
1689 pipe_config->clock_set = true;
1691 if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
1692 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n");
1694 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
1697 * In case of TE GATE cmd mode, we
1698 * receive TE from the slave if
1699 * dual link is enabled
1701 if (is_cmd_mode(intel_dsi))
1702 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1707 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
1708 struct intel_crtc_state *crtc_state)
1710 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1712 get_dsi_io_power_domains(i915,
1713 enc_to_intel_dsi(encoder));
1716 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
1719 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1720 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1721 enum transcoder dsi_trans;
1722 intel_wakeref_t wakeref;
1727 wakeref = intel_display_power_get_if_enabled(dev_priv,
1728 encoder->power_domain);
1732 for_each_dsi_port(port, intel_dsi->ports) {
1733 dsi_trans = dsi_port_to_transcoder(port);
1734 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
1735 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1736 case TRANS_DDI_EDP_INPUT_A_ON:
1739 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1742 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1745 case TRANS_DDI_EDP_INPUT_D_ONOFF:
1749 drm_err(&dev_priv->drm, "Invalid PIPE input\n");
1753 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans));
1754 ret = tmp & PIPECONF_ENABLE;
1757 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1761 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
1762 struct intel_crtc_state *crtc_state)
1764 if (crtc_state->dsc.compression_enable) {
1765 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
1766 crtc_state->uapi.mode_changed = true;
1774 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
1776 intel_encoder_destroy(encoder);
1779 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
1780 .destroy = gen11_dsi_encoder_destroy,
1783 static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
1784 .detect = intel_panel_detect,
1785 .late_register = intel_connector_register,
1786 .early_unregister = intel_connector_unregister,
1787 .destroy = intel_connector_destroy,
1788 .fill_modes = drm_helper_probe_single_connector_modes,
1789 .atomic_get_property = intel_digital_connector_atomic_get_property,
1790 .atomic_set_property = intel_digital_connector_atomic_set_property,
1791 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1792 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1795 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
1796 .get_modes = intel_dsi_get_modes,
1797 .mode_valid = gen11_dsi_mode_valid,
1798 .atomic_check = intel_digital_connector_atomic_check,
1801 static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
1802 struct mipi_dsi_device *dsi)
1807 static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
1808 struct mipi_dsi_device *dsi)
1813 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
1814 const struct mipi_dsi_msg *msg)
1816 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
1817 struct mipi_dsi_packet dsi_pkt;
1819 bool enable_lpdt = false;
1821 ret = mipi_dsi_create_packet(&dsi_pkt, msg);
1825 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1828 /* only long packet contains payload */
1829 if (mipi_dsi_packet_format_is_long(msg->type)) {
1830 ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt);
1835 /* send packet header */
1836 ret = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt);
1840 //TODO: add payload receive code if needed
1842 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
1847 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
1848 .attach = gen11_dsi_host_attach,
1849 .detach = gen11_dsi_host_detach,
1850 .transfer = gen11_dsi_host_transfer,
1853 #define ICL_PREPARE_CNT_MAX 0x7
1854 #define ICL_CLK_ZERO_CNT_MAX 0xf
1855 #define ICL_TRAIL_CNT_MAX 0x7
1856 #define ICL_TCLK_PRE_CNT_MAX 0x3
1857 #define ICL_TCLK_POST_CNT_MAX 0x7
1858 #define ICL_HS_ZERO_CNT_MAX 0xf
1859 #define ICL_EXIT_ZERO_CNT_MAX 0x7
1861 static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
1863 struct drm_device *dev = intel_dsi->base.base.dev;
1864 struct drm_i915_private *dev_priv = to_i915(dev);
1865 struct intel_connector *connector = intel_dsi->attached_connector;
1866 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1868 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1869 u32 ths_prepare_ns, tclk_trail_ns;
1871 u32 tclk_pre_cnt, tclk_post_cnt;
1873 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1875 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1876 ths_prepare_ns = max(mipi_config->ths_prepare,
1877 mipi_config->tclk_prepare);
1880 * prepare cnt in escape clocks
1881 * this field represents a hexadecimal value with a precision
1882 * of 1.2 – i.e. the most significant bit is the integer
1883 * and the least significant 2 bits are fraction bits.
1884 * so, the field can represent a range of 0.25 to 1.75
1886 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
1887 if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
1888 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n",
1890 prepare_cnt = ICL_PREPARE_CNT_MAX;
1893 /* clk zero count in escape clocks */
1894 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
1895 ths_prepare_ns, tlpx_ns);
1896 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
1897 drm_dbg_kms(&dev_priv->drm,
1898 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
1899 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
1902 /* trail cnt in escape clocks*/
1903 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
1904 if (trail_cnt > ICL_TRAIL_CNT_MAX) {
1905 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n",
1907 trail_cnt = ICL_TRAIL_CNT_MAX;
1910 /* tclk pre count in escape clocks */
1911 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
1912 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
1913 drm_dbg_kms(&dev_priv->drm,
1914 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
1915 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
1918 /* tclk post count in escape clocks */
1919 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
1920 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
1921 drm_dbg_kms(&dev_priv->drm,
1922 "tclk_post_cnt out of range (%d)\n",
1924 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
1927 /* hs zero cnt in escape clocks */
1928 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
1929 ths_prepare_ns, tlpx_ns);
1930 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
1931 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n",
1933 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
1936 /* hs exit zero cnt in escape clocks */
1937 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
1938 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
1939 drm_dbg_kms(&dev_priv->drm,
1940 "exit_zero_cnt out of range (%d)\n",
1942 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
1945 /* clock lane dphy timings */
1946 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
1947 CLK_PREPARE(prepare_cnt) |
1949 CLK_ZERO(clk_zero_cnt) |
1951 CLK_PRE(tclk_pre_cnt) |
1953 CLK_POST(tclk_post_cnt) |
1954 CLK_TRAIL_OVERRIDE |
1955 CLK_TRAIL(trail_cnt));
1957 /* data lanes dphy timings */
1958 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
1959 HS_PREPARE(prepare_cnt) |
1961 HS_ZERO(hs_zero_cnt) |
1963 HS_TRAIL(trail_cnt) |
1965 HS_EXIT(exit_zero_cnt));
1967 intel_dsi_log_params(intel_dsi);
1970 static void icl_dsi_add_properties(struct intel_connector *connector)
1972 const struct drm_display_mode *fixed_mode =
1973 intel_panel_preferred_fixed_mode(connector);
1974 u32 allowed_scalers;
1976 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) |
1977 BIT(DRM_MODE_SCALE_FULLSCREEN) |
1978 BIT(DRM_MODE_SCALE_CENTER);
1980 drm_connector_attach_scaling_mode_property(&connector->base,
1983 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1985 drm_connector_set_panel_orientation_with_quirk(&connector->base,
1986 intel_dsi_get_panel_orientation(connector),
1987 fixed_mode->hdisplay,
1988 fixed_mode->vdisplay);
1991 void icl_dsi_init(struct drm_i915_private *dev_priv)
1993 struct drm_device *dev = &dev_priv->drm;
1994 struct intel_dsi *intel_dsi;
1995 struct intel_encoder *encoder;
1996 struct intel_connector *intel_connector;
1997 struct drm_connector *connector;
2000 if (!intel_bios_is_dsi_present(dev_priv, &port))
2003 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
2007 intel_connector = intel_connector_alloc();
2008 if (!intel_connector) {
2013 encoder = &intel_dsi->base;
2014 intel_dsi->attached_connector = intel_connector;
2015 connector = &intel_connector->base;
2017 /* register DSI encoder with DRM subsystem */
2018 drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs,
2019 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
2021 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
2022 encoder->pre_enable = gen11_dsi_pre_enable;
2023 encoder->enable = gen11_dsi_enable;
2024 encoder->disable = gen11_dsi_disable;
2025 encoder->post_disable = gen11_dsi_post_disable;
2026 encoder->port = port;
2027 encoder->get_config = gen11_dsi_get_config;
2028 encoder->sync_state = gen11_dsi_sync_state;
2029 encoder->update_pipe = intel_backlight_update;
2030 encoder->compute_config = gen11_dsi_compute_config;
2031 encoder->get_hw_state = gen11_dsi_get_hw_state;
2032 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
2033 encoder->type = INTEL_OUTPUT_DSI;
2034 encoder->cloneable = 0;
2035 encoder->pipe_mask = ~0;
2036 encoder->power_domain = POWER_DOMAIN_PORT_DSI;
2037 encoder->get_power_domains = gen11_dsi_get_power_domains;
2038 encoder->disable_clock = gen11_dsi_gate_clocks;
2039 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled;
2041 /* register DSI connector with DRM subsystem */
2042 drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
2043 DRM_MODE_CONNECTOR_DSI);
2044 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
2045 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2046 connector->interlace_allowed = false;
2047 connector->doublescan_allowed = false;
2048 intel_connector->get_hw_state = intel_connector_get_hw_state;
2050 /* attach connector to encoder */
2051 intel_connector_attach_encoder(intel_connector, encoder);
2053 intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL, NULL);
2055 mutex_lock(&dev->mode_config.mutex);
2056 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
2057 mutex_unlock(&dev->mode_config.mutex);
2059 if (!intel_panel_preferred_fixed_mode(intel_connector)) {
2060 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n");
2064 intel_panel_init(intel_connector);
2066 intel_backlight_setup(intel_connector, INVALID_PIPE);
2068 if (intel_connector->panel.vbt.dsi.config->dual_link)
2069 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
2071 intel_dsi->ports = BIT(port);
2073 intel_dsi->dcs_backlight_ports = intel_connector->panel.vbt.dsi.bl_ports;
2074 intel_dsi->dcs_cabc_ports = intel_connector->panel.vbt.dsi.cabc_ports;
2076 for_each_dsi_port(port, intel_dsi->ports) {
2077 struct intel_dsi_host *host;
2079 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port);
2083 intel_dsi->dsi_hosts[port] = host;
2086 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
2087 drm_dbg_kms(&dev_priv->drm, "no device found\n");
2091 icl_dphy_param_init(intel_dsi);
2093 icl_dsi_add_properties(intel_connector);
2097 drm_connector_cleanup(connector);
2098 drm_encoder_cleanup(&encoder->base);
2100 kfree(intel_connector);