drivers/gpu/drm/i2c/tda998x_drv.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/component.h>
  19 #include <linux/hdmi.h>
  20 #include <linux/module.h>
  21 #include <linux/irq.h>
  22 #include <sound/asoundef.h>
  23
  24 #include <drm/drmP.h>
  25 #include <drm/drm_crtc_helper.h>
  26 #include <drm/drm_encoder_slave.h>
  27 #include <drm/drm_edid.h>
  28 #include <drm/drm_of.h>
  29 #include <drm/i2c/tda998x.h>
  30
  31 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
  32
  33 struct tda998x_priv {
  34         struct i2c_client *cec;
  35         struct i2c_client *hdmi;
  36         struct mutex mutex;
  37         struct delayed_work dwork;
  38         uint16_t rev;
  39         uint8_t current_page;
  40         int dpms;
  41         bool is_hdmi_sink;
  42         u8 vip_cntrl_0;
  43         u8 vip_cntrl_1;
  44         u8 vip_cntrl_2;
  45         struct tda998x_encoder_params params;
  46
  47         wait_queue_head_t wq_edid;
  48         volatile int wq_edid_wait;
  49         struct drm_encoder *encoder;
  50 };
  51
  52 #define to_tda998x_priv(x)  ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv)
  53
  54 /* The TDA9988 series of devices use a paged register scheme.. to simplify
  55  * things we encode the page # in upper bits of the register #.  To read/
  56  * write a given register, we need to make sure CURPAGE register is set
  57  * appropriately.  Which implies reads/writes are not atomic.  Fun!
  58  */
  59
  60 #define REG(page, addr) (((page) << 8) | (addr))
  61 #define REG2ADDR(reg)   ((reg) & 0xff)
  62 #define REG2PAGE(reg)   (((reg) >> 8) & 0xff)
  63
  64 #define REG_CURPAGE               0xff                /* write */
  65
  66
  67 /* Page 00h: General Control */
  68 #define REG_VERSION_LSB           REG(0x00, 0x00)     /* read */
  69 #define REG_MAIN_CNTRL0           REG(0x00, 0x01)     /* read/write */
  70 # define MAIN_CNTRL0_SR           (1 << 0)
  71 # define MAIN_CNTRL0_DECS         (1 << 1)
  72 # define MAIN_CNTRL0_DEHS         (1 << 2)
  73 # define MAIN_CNTRL0_CECS         (1 << 3)
  74 # define MAIN_CNTRL0_CEHS         (1 << 4)
  75 # define MAIN_CNTRL0_SCALER       (1 << 7)
  76 #define REG_VERSION_MSB           REG(0x00, 0x02)     /* read */
  77 #define REG_SOFTRESET             REG(0x00, 0x0a)     /* write */
  78 # define SOFTRESET_AUDIO          (1 << 0)
  79 # define SOFTRESET_I2C_MASTER     (1 << 1)
  80 #define REG_DDC_DISABLE           REG(0x00, 0x0b)     /* read/write */
  81 #define REG_CCLK_ON               REG(0x00, 0x0c)     /* read/write */
  82 #define REG_I2C_MASTER            REG(0x00, 0x0d)     /* read/write */
  83 # define I2C_MASTER_DIS_MM        (1 << 0)
  84 # define I2C_MASTER_DIS_FILT      (1 << 1)
  85 # define I2C_MASTER_APP_STRT_LAT  (1 << 2)
  86 #define REG_FEAT_POWERDOWN        REG(0x00, 0x0e)     /* read/write */
  87 # define FEAT_POWERDOWN_SPDIF     (1 << 3)
  88 #define REG_INT_FLAGS_0           REG(0x00, 0x0f)     /* read/write */
  89 #define REG_INT_FLAGS_1           REG(0x00, 0x10)     /* read/write */
  90 #define REG_INT_FLAGS_2           REG(0x00, 0x11)     /* read/write */
  91 # define INT_FLAGS_2_EDID_BLK_RD  (1 << 1)
  92 #define REG_ENA_ACLK              REG(0x00, 0x16)     /* read/write */
  93 #define REG_ENA_VP_0              REG(0x00, 0x18)     /* read/write */
  94 #define REG_ENA_VP_1              REG(0x00, 0x19)     /* read/write */
  95 #define REG_ENA_VP_2              REG(0x00, 0x1a)     /* read/write */
  96 #define REG_ENA_AP                REG(0x00, 0x1e)     /* read/write */
  97 #define REG_VIP_CNTRL_0           REG(0x00, 0x20)     /* write */
  98 # define VIP_CNTRL_0_MIRR_A       (1 << 7)
  99 # define VIP_CNTRL_0_SWAP_A(x)    (((x) & 7) << 4)
 100 # define VIP_CNTRL_0_MIRR_B       (1 << 3)
 101 # define VIP_CNTRL_0_SWAP_B(x)    (((x) & 7) << 0)
 102 #define REG_VIP_CNTRL_1           REG(0x00, 0x21)     /* write */
 103 # define VIP_CNTRL_1_MIRR_C       (1 << 7)
 104 # define VIP_CNTRL_1_SWAP_C(x)    (((x) & 7) << 4)
 105 # define VIP_CNTRL_1_MIRR_D       (1 << 3)
 106 # define VIP_CNTRL_1_SWAP_D(x)    (((x) & 7) << 0)
 107 #define REG_VIP_CNTRL_2           REG(0x00, 0x22)     /* write */
 108 # define VIP_CNTRL_2_MIRR_E       (1 << 7)
 109 # define VIP_CNTRL_2_SWAP_E(x)    (((x) & 7) << 4)
 110 # define VIP_CNTRL_2_MIRR_F       (1 << 3)
 111 # define VIP_CNTRL_2_SWAP_F(x)    (((x) & 7) << 0)
 112 #define REG_VIP_CNTRL_3           REG(0x00, 0x23)     /* write */
 113 # define VIP_CNTRL_3_X_TGL        (1 << 0)
 114 # define VIP_CNTRL_3_H_TGL        (1 << 1)
 115 # define VIP_CNTRL_3_V_TGL        (1 << 2)
 116 # define VIP_CNTRL_3_EMB          (1 << 3)
 117 # define VIP_CNTRL_3_SYNC_DE      (1 << 4)
 118 # define VIP_CNTRL_3_SYNC_HS      (1 << 5)
 119 # define VIP_CNTRL_3_DE_INT       (1 << 6)
 120 # define VIP_CNTRL_3_EDGE         (1 << 7)
 121 #define REG_VIP_CNTRL_4           REG(0x00, 0x24)     /* write */
 122 # define VIP_CNTRL_4_BLC(x)       (((x) & 3) << 0)
 123 # define VIP_CNTRL_4_BLANKIT(x)   (((x) & 3) << 2)
 124 # define VIP_CNTRL_4_CCIR656      (1 << 4)
 125 # define VIP_CNTRL_4_656_ALT      (1 << 5)
 126 # define VIP_CNTRL_4_TST_656      (1 << 6)
 127 # define VIP_CNTRL_4_TST_PAT      (1 << 7)
 128 #define REG_VIP_CNTRL_5           REG(0x00, 0x25)     /* write */
 129 # define VIP_CNTRL_5_CKCASE       (1 << 0)
 130 # define VIP_CNTRL_5_SP_CNT(x)    (((x) & 3) << 1)
 131 #define REG_MUX_AP                REG(0x00, 0x26)     /* read/write */
 132 # define MUX_AP_SELECT_I2S        0x64
 133 # define MUX_AP_SELECT_SPDIF      0x40
 134 #define REG_MUX_VP_VIP_OUT        REG(0x00, 0x27)     /* read/write */
 135 #define REG_MAT_CONTRL            REG(0x00, 0x80)     /* write */
 136 # define MAT_CONTRL_MAT_SC(x)     (((x) & 3) << 0)
 137 # define MAT_CONTRL_MAT_BP        (1 << 2)
 138 #define REG_VIDFORMAT             REG(0x00, 0xa0)     /* write */
 139 #define REG_REFPIX_MSB            REG(0x00, 0xa1)     /* write */
 140 #define REG_REFPIX_LSB            REG(0x00, 0xa2)     /* write */
 141 #define REG_REFLINE_MSB           REG(0x00, 0xa3)     /* write */
 142 #define REG_REFLINE_LSB           REG(0x00, 0xa4)     /* write */
 143 #define REG_NPIX_MSB              REG(0x00, 0xa5)     /* write */
 144 #define REG_NPIX_LSB              REG(0x00, 0xa6)     /* write */
 145 #define REG_NLINE_MSB             REG(0x00, 0xa7)     /* write */
 146 #define REG_NLINE_LSB             REG(0x00, 0xa8)     /* write */
 147 #define REG_VS_LINE_STRT_1_MSB    REG(0x00, 0xa9)     /* write */
 148 #define REG_VS_LINE_STRT_1_LSB    REG(0x00, 0xaa)     /* write */
 149 #define REG_VS_PIX_STRT_1_MSB     REG(0x00, 0xab)     /* write */
 150 #define REG_VS_PIX_STRT_1_LSB     REG(0x00, 0xac)     /* write */
 151 #define REG_VS_LINE_END_1_MSB     REG(0x00, 0xad)     /* write */
 152 #define REG_VS_LINE_END_1_LSB     REG(0x00, 0xae)     /* write */
 153 #define REG_VS_PIX_END_1_MSB      REG(0x00, 0xaf)     /* write */
 154 #define REG_VS_PIX_END_1_LSB      REG(0x00, 0xb0)     /* write */
 155 #define REG_VS_LINE_STRT_2_MSB    REG(0x00, 0xb1)     /* write */
 156 #define REG_VS_LINE_STRT_2_LSB    REG(0x00, 0xb2)     /* write */
 157 #define REG_VS_PIX_STRT_2_MSB     REG(0x00, 0xb3)     /* write */
 158 #define REG_VS_PIX_STRT_2_LSB     REG(0x00, 0xb4)     /* write */
 159 #define REG_VS_LINE_END_2_MSB     REG(0x00, 0xb5)     /* write */
 160 #define REG_VS_LINE_END_2_LSB     REG(0x00, 0xb6)     /* write */
 161 #define REG_VS_PIX_END_2_MSB      REG(0x00, 0xb7)     /* write */
 162 #define REG_VS_PIX_END_2_LSB      REG(0x00, 0xb8)     /* write */
 163 #define REG_HS_PIX_START_MSB      REG(0x00, 0xb9)     /* write */
 164 #define REG_HS_PIX_START_LSB      REG(0x00, 0xba)     /* write */
 165 #define REG_HS_PIX_STOP_MSB       REG(0x00, 0xbb)     /* write */
 166 #define REG_HS_PIX_STOP_LSB       REG(0x00, 0xbc)     /* write */
 167 #define REG_VWIN_START_1_MSB      REG(0x00, 0xbd)     /* write */
 168 #define REG_VWIN_START_1_LSB      REG(0x00, 0xbe)     /* write */
 169 #define REG_VWIN_END_1_MSB        REG(0x00, 0xbf)     /* write */
 170 #define REG_VWIN_END_1_LSB        REG(0x00, 0xc0)     /* write */
 171 #define REG_VWIN_START_2_MSB      REG(0x00, 0xc1)     /* write */
 172 #define REG_VWIN_START_2_LSB      REG(0x00, 0xc2)     /* write */
 173 #define REG_VWIN_END_2_MSB        REG(0x00, 0xc3)     /* write */
 174 #define REG_VWIN_END_2_LSB        REG(0x00, 0xc4)     /* write */
 175 #define REG_DE_START_MSB          REG(0x00, 0xc5)     /* write */
 176 #define REG_DE_START_LSB          REG(0x00, 0xc6)     /* write */
 177 #define REG_DE_STOP_MSB           REG(0x00, 0xc7)     /* write */
 178 #define REG_DE_STOP_LSB           REG(0x00, 0xc8)     /* write */
 179 #define REG_TBG_CNTRL_0           REG(0x00, 0xca)     /* write */
 180 # define TBG_CNTRL_0_TOP_TGL      (1 << 0)
 181 # define TBG_CNTRL_0_TOP_SEL      (1 << 1)
 182 # define TBG_CNTRL_0_DE_EXT       (1 << 2)
 183 # define TBG_CNTRL_0_TOP_EXT      (1 << 3)
 184 # define TBG_CNTRL_0_FRAME_DIS    (1 << 5)
 185 # define TBG_CNTRL_0_SYNC_MTHD    (1 << 6)
 186 # define TBG_CNTRL_0_SYNC_ONCE    (1 << 7)
 187 #define REG_TBG_CNTRL_1           REG(0x00, 0xcb)     /* write */
 188 # define TBG_CNTRL_1_H_TGL        (1 << 0)
 189 # define TBG_CNTRL_1_V_TGL        (1 << 1)
 190 # define TBG_CNTRL_1_TGL_EN       (1 << 2)
 191 # define TBG_CNTRL_1_X_EXT        (1 << 3)
 192 # define TBG_CNTRL_1_H_EXT        (1 << 4)
 193 # define TBG_CNTRL_1_V_EXT        (1 << 5)
 194 # define TBG_CNTRL_1_DWIN_DIS     (1 << 6)
 195 #define REG_ENABLE_SPACE          REG(0x00, 0xd6)     /* write */
 196 #define REG_HVF_CNTRL_0           REG(0x00, 0xe4)     /* write */
 197 # define HVF_CNTRL_0_SM           (1 << 7)
 198 # define HVF_CNTRL_0_RWB          (1 << 6)
 199 # define HVF_CNTRL_0_PREFIL(x)    (((x) & 3) << 2)
 200 # define HVF_CNTRL_0_INTPOL(x)    (((x) & 3) << 0)
 201 #define REG_HVF_CNTRL_1           REG(0x00, 0xe5)     /* write */
 202 # define HVF_CNTRL_1_FOR          (1 << 0)
 203 # define HVF_CNTRL_1_YUVBLK       (1 << 1)
 204 # define HVF_CNTRL_1_VQR(x)       (((x) & 3) << 2)
 205 # define HVF_CNTRL_1_PAD(x)       (((x) & 3) << 4)
 206 # define HVF_CNTRL_1_SEMI_PLANAR  (1 << 6)
 207 #define REG_RPT_CNTRL             REG(0x00, 0xf0)     /* write */
 208 #define REG_I2S_FORMAT            REG(0x00, 0xfc)     /* read/write */
 209 # define I2S_FORMAT(x)            (((x) & 3) << 0)
 210 #define REG_AIP_CLKSEL            REG(0x00, 0xfd)     /* write */
 211 # define AIP_CLKSEL_AIP_SPDIF     (0 << 3)
 212 # define AIP_CLKSEL_AIP_I2S       (1 << 3)
 213 # define AIP_CLKSEL_FS_ACLK       (0 << 0)
 214 # define AIP_CLKSEL_FS_MCLK       (1 << 0)
 215 # define AIP_CLKSEL_FS_FS64SPDIF  (2 << 0)
 216
 217 /* Page 02h: PLL settings */
 218 #define REG_PLL_SERIAL_1          REG(0x02, 0x00)     /* read/write */
 219 # define PLL_SERIAL_1_SRL_FDN     (1 << 0)
 220 # define PLL_SERIAL_1_SRL_IZ(x)   (((x) & 3) << 1)
 221 # define PLL_SERIAL_1_SRL_MAN_IZ  (1 << 6)
 222 #define REG_PLL_SERIAL_2          REG(0x02, 0x01)     /* read/write */
 223 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
 224 # define PLL_SERIAL_2_SRL_PR(x)   (((x) & 0xf) << 4)
 225 #define REG_PLL_SERIAL_3          REG(0x02, 0x02)     /* read/write */
 226 # define PLL_SERIAL_3_SRL_CCIR    (1 << 0)
 227 # define PLL_SERIAL_3_SRL_DE      (1 << 2)
 228 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
 229 #define REG_SERIALIZER            REG(0x02, 0x03)     /* read/write */
 230 #define REG_BUFFER_OUT            REG(0x02, 0x04)     /* read/write */
 231 #define REG_PLL_SCG1              REG(0x02, 0x05)     /* read/write */
 232 #define REG_PLL_SCG2              REG(0x02, 0x06)     /* read/write */
 233 #define REG_PLL_SCGN1             REG(0x02, 0x07)     /* read/write */
 234 #define REG_PLL_SCGN2             REG(0x02, 0x08)     /* read/write */
 235 #define REG_PLL_SCGR1             REG(0x02, 0x09)     /* read/write */
 236 #define REG_PLL_SCGR2             REG(0x02, 0x0a)     /* read/write */
 237 #define REG_AUDIO_DIV             REG(0x02, 0x0e)     /* read/write */
 238 # define AUDIO_DIV_SERCLK_1       0
 239 # define AUDIO_DIV_SERCLK_2       1
 240 # define AUDIO_DIV_SERCLK_4       2
 241 # define AUDIO_DIV_SERCLK_8       3
 242 # define AUDIO_DIV_SERCLK_16      4
 243 # define AUDIO_DIV_SERCLK_32      5
 244 #define REG_SEL_CLK               REG(0x02, 0x11)     /* read/write */
 245 # define SEL_CLK_SEL_CLK1         (1 << 0)
 246 # define SEL_CLK_SEL_VRF_CLK(x)   (((x) & 3) << 1)
 247 # define SEL_CLK_ENA_SC_CLK       (1 << 3)
 248 #define REG_ANA_GENERAL           REG(0x02, 0x12)     /* read/write */
 249
 250
 251 /* Page 09h: EDID Control */
 252 #define REG_EDID_DATA_0           REG(0x09, 0x00)     /* read */
 253 /* next 127 successive registers are the EDID block */
 254 #define REG_EDID_CTRL             REG(0x09, 0xfa)     /* read/write */
 255 #define REG_DDC_ADDR              REG(0x09, 0xfb)     /* read/write */
 256 #define REG_DDC_OFFS              REG(0x09, 0xfc)     /* read/write */
 257 #define REG_DDC_SEGM_ADDR         REG(0x09, 0xfd)     /* read/write */
 258 #define REG_DDC_SEGM              REG(0x09, 0xfe)     /* read/write */
 259
 260
 261 /* Page 10h: information frames and packets */
 262 #define REG_IF1_HB0               REG(0x10, 0x20)     /* read/write */
 263 #define REG_IF2_HB0               REG(0x10, 0x40)     /* read/write */
 264 #define REG_IF3_HB0               REG(0x10, 0x60)     /* read/write */
 265 #define REG_IF4_HB0               REG(0x10, 0x80)     /* read/write */
 266 #define REG_IF5_HB0               REG(0x10, 0xa0)     /* read/write */
 267
 268
 269 /* Page 11h: audio settings and content info packets */
 270 #define REG_AIP_CNTRL_0           REG(0x11, 0x00)     /* read/write */
 271 # define AIP_CNTRL_0_RST_FIFO     (1 << 0)
 272 # define AIP_CNTRL_0_SWAP         (1 << 1)
 273 # define AIP_CNTRL_0_LAYOUT       (1 << 2)
 274 # define AIP_CNTRL_0_ACR_MAN      (1 << 5)
 275 # define AIP_CNTRL_0_RST_CTS      (1 << 6)
 276 #define REG_CA_I2S                REG(0x11, 0x01)     /* read/write */
 277 # define CA_I2S_CA_I2S(x)         (((x) & 31) << 0)
 278 # define CA_I2S_HBR_CHSTAT        (1 << 6)
 279 #define REG_LATENCY_RD            REG(0x11, 0x04)     /* read/write */
 280 #define REG_ACR_CTS_0             REG(0x11, 0x05)     /* read/write */
 281 #define REG_ACR_CTS_1             REG(0x11, 0x06)     /* read/write */
 282 #define REG_ACR_CTS_2             REG(0x11, 0x07)     /* read/write */
 283 #define REG_ACR_N_0               REG(0x11, 0x08)     /* read/write */
 284 #define REG_ACR_N_1               REG(0x11, 0x09)     /* read/write */
 285 #define REG_ACR_N_2               REG(0x11, 0x0a)     /* read/write */
 286 #define REG_CTS_N                 REG(0x11, 0x0c)     /* read/write */
 287 # define CTS_N_K(x)               (((x) & 7) << 0)
 288 # define CTS_N_M(x)               (((x) & 3) << 4)
 289 #define REG_ENC_CNTRL             REG(0x11, 0x0d)     /* read/write */
 290 # define ENC_CNTRL_RST_ENC        (1 << 0)
 291 # define ENC_CNTRL_RST_SEL        (1 << 1)
 292 # define ENC_CNTRL_CTL_CODE(x)    (((x) & 3) << 2)
 293 #define REG_DIP_FLAGS             REG(0x11, 0x0e)     /* read/write */
 294 # define DIP_FLAGS_ACR            (1 << 0)
 295 # define DIP_FLAGS_GC             (1 << 1)
 296 #define REG_DIP_IF_FLAGS          REG(0x11, 0x0f)     /* read/write */
 297 # define DIP_IF_FLAGS_IF1         (1 << 1)
 298 # define DIP_IF_FLAGS_IF2         (1 << 2)
 299 # define DIP_IF_FLAGS_IF3         (1 << 3)
 300 # define DIP_IF_FLAGS_IF4         (1 << 4)
 301 # define DIP_IF_FLAGS_IF5         (1 << 5)
 302 #define REG_CH_STAT_B(x)          REG(0x11, 0x14 + (x)) /* read/write */
 303
 304
 305 /* Page 12h: HDCP and OTP */
 306 #define REG_TX3                   REG(0x12, 0x9a)     /* read/write */
 307 #define REG_TX4                   REG(0x12, 0x9b)     /* read/write */
 308 # define TX4_PD_RAM               (1 << 1)
 309 #define REG_TX33                  REG(0x12, 0xb8)     /* read/write */
 310 # define TX33_HDMI                (1 << 1)
 311
 312
 313 /* Page 13h: Gamut related metadata packets */
 314
 315
 316
 317 /* CEC registers: (not paged)
 318  */
 319 #define REG_CEC_INTSTATUS         0xee                /* read */
 320 # define CEC_INTSTATUS_CEC        (1 << 0)
 321 # define CEC_INTSTATUS_HDMI       (1 << 1)
 322 #define REG_CEC_FRO_IM_CLK_CTRL   0xfb                /* read/write */
 323 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
 324 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP   (1 << 6)
 325 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
 326 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV   (1 << 0)
 327 #define REG_CEC_RXSHPDINTENA      0xfc                /* read/write */
 328 #define REG_CEC_RXSHPDINT         0xfd                /* read */
 329 #define REG_CEC_RXSHPDLEV         0xfe                /* read */
 330 # define CEC_RXSHPDLEV_RXSENS     (1 << 0)
 331 # define CEC_RXSHPDLEV_HPD        (1 << 1)
 332
 333 #define REG_CEC_ENAMODS           0xff                /* read/write */
 334 # define CEC_ENAMODS_DIS_FRO      (1 << 6)
 335 # define CEC_ENAMODS_DIS_CCLK     (1 << 5)
 336 # define CEC_ENAMODS_EN_RXSENS    (1 << 2)
 337 # define CEC_ENAMODS_EN_HDMI      (1 << 1)
 338 # define CEC_ENAMODS_EN_CEC       (1 << 0)
 339
 340
 341 /* Device versions: */
 342 #define TDA9989N2                 0x0101
 343 #define TDA19989                  0x0201
 344 #define TDA19989N2                0x0202
 345 #define TDA19988                  0x0301
 346
 347 static void
 348 cec_write(struct tda998x_priv *priv, uint16_t addr, uint8_t val)
 349 {
 350         struct i2c_client *client = priv->cec;
 351         uint8_t buf[] = {addr, val};
 352         int ret;
 353
 354         ret = i2c_master_send(client, buf, sizeof(buf));
 355         if (ret < 0)
 356                 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
 357 }
 358
 359 static uint8_t
 360 cec_read(struct tda998x_priv *priv, uint8_t addr)
 361 {
 362         struct i2c_client *client = priv->cec;
 363         uint8_t val;
 364         int ret;
 365
 366         ret = i2c_master_send(client, &addr, sizeof(addr));
 367         if (ret < 0)
 368                 goto fail;
 369
 370         ret = i2c_master_recv(client, &val, sizeof(val));
 371         if (ret < 0)
 372                 goto fail;
 373
 374         return val;
 375
 376 fail:
 377         dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
 378         return 0;
 379 }
 380
 381 static int
 382 set_page(struct tda998x_priv *priv, uint16_t reg)
 383 {
 384         if (REG2PAGE(reg) != priv->current_page) {
 385                 struct i2c_client *client = priv->hdmi;
 386                 uint8_t buf[] = {
 387                                 REG_CURPAGE, REG2PAGE(reg)
 388                 };
 389                 int ret = i2c_master_send(client, buf, sizeof(buf));
 390                 if (ret < 0) {
 391                         dev_err(&client->dev, "%s %04x err %d\n", __func__,
 392                                         reg, ret);
 393                         return ret;
 394                 }
 395
 396                 priv->current_page = REG2PAGE(reg);
 397         }
 398         return 0;
 399 }
 400
 401 static int
 402 reg_read_range(struct tda998x_priv *priv, uint16_t reg, char *buf, int cnt)
 403 {
 404         struct i2c_client *client = priv->hdmi;
 405         uint8_t addr = REG2ADDR(reg);
 406         int ret;
 407
 408         mutex_lock(&priv->mutex);
 409         ret = set_page(priv, reg);
 410         if (ret < 0)
 411                 goto out;
 412
 413         ret = i2c_master_send(client, &addr, sizeof(addr));
 414         if (ret < 0)
 415                 goto fail;
 416
 417         ret = i2c_master_recv(client, buf, cnt);
 418         if (ret < 0)
 419                 goto fail;
 420
 421         goto out;
 422
 423 fail:
 424         dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
 425 out:
 426         mutex_unlock(&priv->mutex);
 427         return ret;
 428 }
 429
 430 static void
 431 reg_write_range(struct tda998x_priv *priv, uint16_t reg, uint8_t *p, int cnt)
 432 {
 433         struct i2c_client *client = priv->hdmi;
 434         uint8_t buf[cnt+1];
 435         int ret;
 436
 437         buf[0] = REG2ADDR(reg);
 438         memcpy(&buf[1], p, cnt);
 439
 440         mutex_lock(&priv->mutex);
 441         ret = set_page(priv, reg);
 442         if (ret < 0)
 443                 goto out;
 444
 445         ret = i2c_master_send(client, buf, cnt + 1);
 446         if (ret < 0)
 447                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 448 out:
 449         mutex_unlock(&priv->mutex);
 450 }
 451
 452 static int
 453 reg_read(struct tda998x_priv *priv, uint16_t reg)
 454 {
 455         uint8_t val = 0;
 456         int ret;
 457
 458         ret = reg_read_range(priv, reg, &val, sizeof(val));
 459         if (ret < 0)
 460                 return ret;
 461         return val;
 462 }
 463
 464 static void
 465 reg_write(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
 466 {
 467         struct i2c_client *client = priv->hdmi;
 468         uint8_t buf[] = {REG2ADDR(reg), val};
 469         int ret;
 470
 471         mutex_lock(&priv->mutex);
 472         ret = set_page(priv, reg);
 473         if (ret < 0)
 474                 goto out;
 475
 476         ret = i2c_master_send(client, buf, sizeof(buf));
 477         if (ret < 0)
 478                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 479 out:
 480         mutex_unlock(&priv->mutex);
 481 }
 482
 483 static void
 484 reg_write16(struct tda998x_priv *priv, uint16_t reg, uint16_t val)
 485 {
 486         struct i2c_client *client = priv->hdmi;
 487         uint8_t buf[] = {REG2ADDR(reg), val >> 8, val};
 488         int ret;
 489
 490         mutex_lock(&priv->mutex);
 491         ret = set_page(priv, reg);
 492         if (ret < 0)
 493                 goto out;
 494
 495         ret = i2c_master_send(client, buf, sizeof(buf));
 496         if (ret < 0)
 497                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 498 out:
 499         mutex_unlock(&priv->mutex);
 500 }
 501
 502 static void
 503 reg_set(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
 504 {
 505         int old_val;
 506
 507         old_val = reg_read(priv, reg);
 508         if (old_val >= 0)
 509                 reg_write(priv, reg, old_val | val);
 510 }
 511
 512 static void
 513 reg_clear(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
 514 {
 515         int old_val;
 516
 517         old_val = reg_read(priv, reg);
 518         if (old_val >= 0)
 519                 reg_write(priv, reg, old_val & ~val);
 520 }
 521
 522 static void
 523 tda998x_reset(struct tda998x_priv *priv)
 524 {
 525         /* reset audio and i2c master: */
 526         reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
 527         msleep(50);
 528         reg_write(priv, REG_SOFTRESET, 0);
 529         msleep(50);
 530
 531         /* reset transmitter: */
 532         reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 533         reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 534
 535         /* PLL registers common configuration */
 536         reg_write(priv, REG_PLL_SERIAL_1, 0x00);
 537         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
 538         reg_write(priv, REG_PLL_SERIAL_3, 0x00);
 539         reg_write(priv, REG_SERIALIZER,   0x00);
 540         reg_write(priv, REG_BUFFER_OUT,   0x00);
 541         reg_write(priv, REG_PLL_SCG1,     0x00);
 542         reg_write(priv, REG_AUDIO_DIV,    AUDIO_DIV_SERCLK_8);
 543         reg_write(priv, REG_SEL_CLK,      SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
 544         reg_write(priv, REG_PLL_SCGN1,    0xfa);
 545         reg_write(priv, REG_PLL_SCGN2,    0x00);
 546         reg_write(priv, REG_PLL_SCGR1,    0x5b);
 547         reg_write(priv, REG_PLL_SCGR2,    0x00);
 548         reg_write(priv, REG_PLL_SCG2,     0x10);
 549
 550         /* Write the default value MUX register */
 551         reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
 552 }
 553
 554 /* handle HDMI connect/disconnect */
 555 static void tda998x_hpd(struct work_struct *work)
 556 {
 557         struct delayed_work *dwork = to_delayed_work(work);
 558         struct tda998x_priv *priv =
 559                         container_of(dwork, struct tda998x_priv, dwork);
 560
 561         if (priv->encoder && priv->encoder->dev)
 562                 drm_kms_helper_hotplug_event(priv->encoder->dev);
 563 }
 564
 565 /*
 566  * only 2 interrupts may occur: screen plug/unplug and EDID read
 567  */
 568 static irqreturn_t tda998x_irq_thread(int irq, void *data)
 569 {
 570         struct tda998x_priv *priv = data;
 571         u8 sta, cec, lvl, flag0, flag1, flag2;
 572
 573         if (!priv)
 574                 return IRQ_HANDLED;
 575         sta = cec_read(priv, REG_CEC_INTSTATUS);
 576         cec = cec_read(priv, REG_CEC_RXSHPDINT);
 577         lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
 578         flag0 = reg_read(priv, REG_INT_FLAGS_0);
 579         flag1 = reg_read(priv, REG_INT_FLAGS_1);
 580         flag2 = reg_read(priv, REG_INT_FLAGS_2);
 581         DRM_DEBUG_DRIVER(
 582                 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
 583                 sta, cec, lvl, flag0, flag1, flag2);
 584         if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
 585                 priv->wq_edid_wait = 0;
 586                 wake_up(&priv->wq_edid);
 587         } else if (cec != 0) {                  /* HPD change */
 588                 schedule_delayed_work(&priv->dwork, HZ/10);
 589         }
 590         return IRQ_HANDLED;
 591 }
 592
 593 static uint8_t tda998x_cksum(uint8_t *buf, size_t bytes)
 594 {
 595         int sum = 0;
 596
 597         while (bytes--)
 598                 sum -= *buf++;
 599         return sum;
 600 }
 601
 602 #define HB(x) (x)
 603 #define PB(x) (HB(2) + 1 + (x))
 604
 605 static void
 606 tda998x_write_if(struct tda998x_priv *priv, uint8_t bit, uint16_t addr,
 607                  uint8_t *buf, size_t size)
 608 {
 609         buf[PB(0)] = tda998x_cksum(buf, size);
 610
 611         reg_clear(priv, REG_DIP_IF_FLAGS, bit);
 612         reg_write_range(priv, addr, buf, size);
 613         reg_set(priv, REG_DIP_IF_FLAGS, bit);
 614 }
 615
 616 static void
 617 tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p)
 618 {
 619         u8 buf[PB(HDMI_AUDIO_INFOFRAME_SIZE) + 1];
 620
 621         memset(buf, 0, sizeof(buf));
 622         buf[HB(0)] = HDMI_INFOFRAME_TYPE_AUDIO;
 623         buf[HB(1)] = 0x01;
 624         buf[HB(2)] = HDMI_AUDIO_INFOFRAME_SIZE;
 625         buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */
 626         buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */
 627         buf[PB(4)] = p->audio_frame[4];
 628         buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */
 629
 630         tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf,
 631                          sizeof(buf));
 632 }
 633
 634 static void
 635 tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
 636 {
 637         struct hdmi_avi_infoframe frame;
 638         u8 buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
 639         ssize_t len;
 640
 641         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 642
 643         frame.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
 644
 645         len = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf));
 646         if (len < 0) {
 647                 dev_err(&priv->hdmi->dev,
 648                         "hdmi_avi_infoframe_pack() failed: %zd\n", len);
 649                 return;
 650         }
 651
 652         tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf, len);
 653 }
 654
 655 static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
 656 {
 657         if (on) {
 658                 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 659                 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 660                 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 661         } else {
 662                 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 663         }
 664 }
 665
 666 static void
 667 tda998x_configure_audio(struct tda998x_priv *priv,
 668                 struct drm_display_mode *mode, struct tda998x_encoder_params *p)
 669 {
 670         uint8_t buf[6], clksel_aip, clksel_fs, cts_n, adiv;
 671         uint32_t n;
 672
 673         /* Enable audio ports */
 674         reg_write(priv, REG_ENA_AP, p->audio_cfg);
 675         reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg);
 676
 677         /* Set audio input source */
 678         switch (p->audio_format) {
 679         case AFMT_SPDIF:
 680                 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
 681                 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
 682                 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
 683                 cts_n = CTS_N_M(3) | CTS_N_K(3);
 684                 break;
 685
 686         case AFMT_I2S:
 687                 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
 688                 clksel_aip = AIP_CLKSEL_AIP_I2S;
 689                 clksel_fs = AIP_CLKSEL_FS_ACLK;
 690                 cts_n = CTS_N_M(3) | CTS_N_K(3);
 691                 break;
 692
 693         default:
 694                 BUG();
 695                 return;
 696         }
 697
 698         reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
 699         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
 700                                         AIP_CNTRL_0_ACR_MAN);   /* auto CTS */
 701         reg_write(priv, REG_CTS_N, cts_n);
 702
 703         /*
 704          * Audio input somehow depends on HDMI line rate which is
 705          * related to pixclk. Testing showed that modes with pixclk
 706          * >100MHz need a larger divider while <40MHz need the default.
 707          * There is no detailed info in the datasheet, so we just
 708          * assume 100MHz requires larger divider.
 709          */
 710         adiv = AUDIO_DIV_SERCLK_8;
 711         if (mode->clock > 100000)
 712                 adiv++;                 /* AUDIO_DIV_SERCLK_16 */
 713
 714         /* S/PDIF asks for a larger divider */
 715         if (p->audio_format == AFMT_SPDIF)
 716                 adiv++;                 /* AUDIO_DIV_SERCLK_16 or _32 */
 717
 718         reg_write(priv, REG_AUDIO_DIV, adiv);
 719
 720         /*
 721          * This is the approximate value of N, which happens to be
 722          * the recommended values for non-coherent clocks.
 723          */
 724         n = 128 * p->audio_sample_rate / 1000;
 725
 726         /* Write the CTS and N values */
 727         buf[0] = 0x44;
 728         buf[1] = 0x42;
 729         buf[2] = 0x01;
 730         buf[3] = n;
 731         buf[4] = n >> 8;
 732         buf[5] = n >> 16;
 733         reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
 734
 735         /* Set CTS clock reference */
 736         reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
 737
 738         /* Reset CTS generator */
 739         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
 740         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
 741
 742         /* Write the channel status */
 743         buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
 744         buf[1] = 0x00;
 745         buf[2] = IEC958_AES3_CON_FS_NOTID;
 746         buf[3] = IEC958_AES4_CON_ORIGFS_NOTID |
 747                         IEC958_AES4_CON_MAX_WORDLEN_24;
 748         reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
 749
 750         tda998x_audio_mute(priv, true);
 751         msleep(20);
 752         tda998x_audio_mute(priv, false);
 753
 754         /* Write the audio information packet */
 755         tda998x_write_aif(priv, p);
 756 }
 757
 758 /* DRM encoder functions */
 759
 760 static void tda998x_encoder_set_config(struct tda998x_priv *priv,
 761                                        const struct tda998x_encoder_params *p)
 762 {
 763         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
 764                             (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
 765                             VIP_CNTRL_0_SWAP_B(p->swap_b) |
 766                             (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
 767         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
 768                             (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
 769                             VIP_CNTRL_1_SWAP_D(p->swap_d) |
 770                             (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
 771         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
 772                             (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
 773                             VIP_CNTRL_2_SWAP_F(p->swap_f) |
 774                             (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
 775
 776         priv->params = *p;
 777 }
 778
 779 static void tda998x_encoder_dpms(struct tda998x_priv *priv, int mode)
 780 {
 781         /* we only care about on or off: */
 782         if (mode != DRM_MODE_DPMS_ON)
 783                 mode = DRM_MODE_DPMS_OFF;
 784
 785         if (mode == priv->dpms)
 786                 return;
 787
 788         switch (mode) {
 789         case DRM_MODE_DPMS_ON:
 790                 /* enable video ports, audio will be enabled later */
 791                 reg_write(priv, REG_ENA_VP_0, 0xff);
 792                 reg_write(priv, REG_ENA_VP_1, 0xff);
 793                 reg_write(priv, REG_ENA_VP_2, 0xff);
 794                 /* set muxing after enabling ports: */
 795                 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
 796                 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
 797                 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
 798                 break;
 799         case DRM_MODE_DPMS_OFF:
 800                 /* disable video ports */
 801                 reg_write(priv, REG_ENA_VP_0, 0x00);
 802                 reg_write(priv, REG_ENA_VP_1, 0x00);
 803                 reg_write(priv, REG_ENA_VP_2, 0x00);
 804                 break;
 805         }
 806
 807         priv->dpms = mode;
 808 }
 809
 810 static void
 811 tda998x_encoder_save(struct drm_encoder *encoder)
 812 {
 813         DBG("");
 814 }
 815
 816 static void
 817 tda998x_encoder_restore(struct drm_encoder *encoder)
 818 {
 819         DBG("");
 820 }
 821
 822 static bool
 823 tda998x_encoder_mode_fixup(struct drm_encoder *encoder,
 824                           const struct drm_display_mode *mode,
 825                           struct drm_display_mode *adjusted_mode)
 826 {
 827         return true;
 828 }
 829
 830 static int tda998x_encoder_mode_valid(struct tda998x_priv *priv,
 831                                       struct drm_display_mode *mode)
 832 {
 833         if (mode->clock > 150000)
 834                 return MODE_CLOCK_HIGH;
 835         if (mode->htotal >= BIT(13))
 836                 return MODE_BAD_HVALUE;
 837         if (mode->vtotal >= BIT(11))
 838                 return MODE_BAD_VVALUE;
 839         return MODE_OK;
 840 }
 841
 842 static void
 843 tda998x_encoder_mode_set(struct tda998x_priv *priv,
 844                          struct drm_display_mode *mode,
 845                          struct drm_display_mode *adjusted_mode)
 846 {
 847         uint16_t ref_pix, ref_line, n_pix, n_line;
 848         uint16_t hs_pix_s, hs_pix_e;
 849         uint16_t vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
 850         uint16_t vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
 851         uint16_t vwin1_line_s, vwin1_line_e;
 852         uint16_t vwin2_line_s, vwin2_line_e;
 853         uint16_t de_pix_s, de_pix_e;
 854         uint8_t reg, div, rep;
 855
 856         /*
 857          * Internally TDA998x is using ITU-R BT.656 style sync but
 858          * we get VESA style sync. TDA998x is using a reference pixel
 859          * relative to ITU to sync to the input frame and for output
 860          * sync generation. Currently, we are using reference detection
 861          * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
 862          * which is position of rising VS with coincident rising HS.
 863          *
 864          * Now there is some issues to take care of:
 865          * - HDMI data islands require sync-before-active
 866          * - TDA998x register values must be > 0 to be enabled
 867          * - REFLINE needs an additional offset of +1
 868          * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
 869          *
 870          * So we add +1 to all horizontal and vertical register values,
 871          * plus an additional +3 for REFPIX as we are using RGB input only.
 872          */
 873         n_pix        = mode->htotal;
 874         n_line       = mode->vtotal;
 875
 876         hs_pix_e     = mode->hsync_end - mode->hdisplay;
 877         hs_pix_s     = mode->hsync_start - mode->hdisplay;
 878         de_pix_e     = mode->htotal;
 879         de_pix_s     = mode->htotal - mode->hdisplay;
 880         ref_pix      = 3 + hs_pix_s;
 881
 882         /*
 883          * Attached LCD controllers may generate broken sync. Allow
 884          * those to adjust the position of the rising VS edge by adding
 885          * HSKEW to ref_pix.
 886          */
 887         if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
 888                 ref_pix += adjusted_mode->hskew;
 889
 890         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
 891                 ref_line     = 1 + mode->vsync_start - mode->vdisplay;
 892                 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
 893                 vwin1_line_e = vwin1_line_s + mode->vdisplay;
 894                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
 895                 vs1_line_s   = mode->vsync_start - mode->vdisplay;
 896                 vs1_line_e   = vs1_line_s +
 897                                mode->vsync_end - mode->vsync_start;
 898                 vwin2_line_s = vwin2_line_e = 0;
 899                 vs2_pix_s    = vs2_pix_e  = 0;
 900                 vs2_line_s   = vs2_line_e = 0;
 901         } else {
 902                 ref_line     = 1 + (mode->vsync_start - mode->vdisplay)/2;
 903                 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
 904                 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
 905                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
 906                 vs1_line_s   = (mode->vsync_start - mode->vdisplay)/2;
 907                 vs1_line_e   = vs1_line_s +
 908                                (mode->vsync_end - mode->vsync_start)/2;
 909                 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
 910                 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
 911                 vs2_pix_s    = vs2_pix_e = hs_pix_s + mode->htotal/2;
 912                 vs2_line_s   = vs1_line_s + mode->vtotal/2 ;
 913                 vs2_line_e   = vs2_line_s +
 914                                (mode->vsync_end - mode->vsync_start)/2;
 915         }
 916
 917         div = 148500 / mode->clock;
 918         if (div != 0) {
 919                 div--;
 920                 if (div > 3)
 921                         div = 3;
 922         }
 923
 924         /* mute the audio FIFO: */
 925         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 926
 927         /* set HDMI HDCP mode off: */
 928         reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
 929         reg_clear(priv, REG_TX33, TX33_HDMI);
 930         reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
 931
 932         /* no pre-filter or interpolator: */
 933         reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
 934                         HVF_CNTRL_0_INTPOL(0));
 935         reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
 936         reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
 937                         VIP_CNTRL_4_BLC(0));
 938
 939         reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
 940         reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
 941                                           PLL_SERIAL_3_SRL_DE);
 942         reg_write(priv, REG_SERIALIZER, 0);
 943         reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
 944
 945         /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
 946         rep = 0;
 947         reg_write(priv, REG_RPT_CNTRL, 0);
 948         reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
 949                         SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
 950
 951         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
 952                         PLL_SERIAL_2_SRL_PR(rep));
 953
 954         /* set color matrix bypass flag: */
 955         reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
 956                                 MAT_CONTRL_MAT_SC(1));
 957
 958         /* set BIAS tmds value: */
 959         reg_write(priv, REG_ANA_GENERAL, 0x09);
 960
 961         /*
 962          * Sync on rising HSYNC/VSYNC
 963          */
 964         reg = VIP_CNTRL_3_SYNC_HS;
 965
 966         /*
 967          * TDA19988 requires high-active sync at input stage,
 968          * so invert low-active sync provided by master encoder here
 969          */
 970         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 971                 reg |= VIP_CNTRL_3_H_TGL;
 972         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 973                 reg |= VIP_CNTRL_3_V_TGL;
 974         reg_write(priv, REG_VIP_CNTRL_3, reg);
 975
 976         reg_write(priv, REG_VIDFORMAT, 0x00);
 977         reg_write16(priv, REG_REFPIX_MSB, ref_pix);
 978         reg_write16(priv, REG_REFLINE_MSB, ref_line);
 979         reg_write16(priv, REG_NPIX_MSB, n_pix);
 980         reg_write16(priv, REG_NLINE_MSB, n_line);
 981         reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
 982         reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
 983         reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
 984         reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
 985         reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
 986         reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
 987         reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
 988         reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
 989         reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
 990         reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
 991         reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
 992         reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
 993         reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
 994         reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
 995         reg_write16(priv, REG_DE_START_MSB, de_pix_s);
 996         reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
 997
 998         if (priv->rev == TDA19988) {
 999                 /* let incoming pixels fill the active space (if any) */
1000                 reg_write(priv, REG_ENABLE_SPACE, 0x00);
1001         }
1002
1003         /*
1004          * Always generate sync polarity relative to input sync and
1005          * revert input stage toggled sync at output stage
1006          */
1007         reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1008         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1009                 reg |= TBG_CNTRL_1_H_TGL;
1010         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1011                 reg |= TBG_CNTRL_1_V_TGL;
1012         reg_write(priv, REG_TBG_CNTRL_1, reg);
1013
1014         /* must be last register set: */
1015         reg_write(priv, REG_TBG_CNTRL_0, 0);
1016
1017         /* Only setup the info frames if the sink is HDMI */
1018         if (priv->is_hdmi_sink) {
1019                 /* We need to turn HDMI HDCP stuff on to get audio through */
1020                 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1021                 reg_write(priv, REG_TBG_CNTRL_1, reg);
1022                 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1023                 reg_set(priv, REG_TX33, TX33_HDMI);
1024
1025                 tda998x_write_avi(priv, adjusted_mode);
1026
1027                 if (priv->params.audio_cfg)
1028                         tda998x_configure_audio(priv, adjusted_mode,
1029                                                 &priv->params);
1030         }
1031 }
1032
1033 static enum drm_connector_status
1034 tda998x_encoder_detect(struct tda998x_priv *priv)
1035 {
1036         uint8_t val = cec_read(priv, REG_CEC_RXSHPDLEV);
1037
1038         return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1039                         connector_status_disconnected;
1040 }
1041
1042 static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1043 {
1044         struct tda998x_priv *priv = data;
1045         uint8_t offset, segptr;
1046         int ret, i;
1047
1048         offset = (blk & 1) ? 128 : 0;
1049         segptr = blk / 2;
1050
1051         reg_write(priv, REG_DDC_ADDR, 0xa0);
1052         reg_write(priv, REG_DDC_OFFS, offset);
1053         reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1054         reg_write(priv, REG_DDC_SEGM, segptr);
1055
1056         /* enable reading EDID: */
1057         priv->wq_edid_wait = 1;
1058         reg_write(priv, REG_EDID_CTRL, 0x1);
1059
1060         /* flag must be cleared by sw: */
1061         reg_write(priv, REG_EDID_CTRL, 0x0);
1062
1063         /* wait for block read to complete: */
1064         if (priv->hdmi->irq) {
1065                 i = wait_event_timeout(priv->wq_edid,
1066                                         !priv->wq_edid_wait,
1067                                         msecs_to_jiffies(100));
1068                 if (i < 0) {
1069                         dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1070                         return i;
1071                 }
1072         } else {
1073                 for (i = 100; i > 0; i--) {
1074                         msleep(1);
1075                         ret = reg_read(priv, REG_INT_FLAGS_2);
1076                         if (ret < 0)
1077                                 return ret;
1078                         if (ret & INT_FLAGS_2_EDID_BLK_RD)
1079                                 break;
1080                 }
1081         }
1082
1083         if (i == 0) {
1084                 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1085                 return -ETIMEDOUT;
1086         }
1087
1088         ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1089         if (ret != length) {
1090                 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1091                         blk, ret);
1092                 return ret;
1093         }
1094
1095         return 0;
1096 }
1097
1098 static int
1099 tda998x_encoder_get_modes(struct tda998x_priv *priv,
1100                           struct drm_connector *connector)
1101 {
1102         struct edid *edid;
1103         int n;
1104
1105         if (priv->rev == TDA19988)
1106                 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1107
1108         edid = drm_do_get_edid(connector, read_edid_block, priv);
1109
1110         if (priv->rev == TDA19988)
1111                 reg_set(priv, REG_TX4, TX4_PD_RAM);
1112
1113         if (!edid) {
1114                 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1115                 return 0;
1116         }
1117
1118         drm_mode_connector_update_edid_property(connector, edid);
1119         n = drm_add_edid_modes(connector, edid);
1120         priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
1121         kfree(edid);
1122
1123         return n;
1124 }
1125
1126 static void tda998x_encoder_set_polling(struct tda998x_priv *priv,
1127                                         struct drm_connector *connector)
1128 {
1129         if (priv->hdmi->irq)
1130                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1131         else
1132                 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1133                         DRM_CONNECTOR_POLL_DISCONNECT;
1134 }
1135
1136 static int
1137 tda998x_encoder_set_property(struct drm_encoder *encoder,
1138                             struct drm_connector *connector,
1139                             struct drm_property *property,
1140                             uint64_t val)
1141 {
1142         DBG("");
1143         return 0;
1144 }
1145
1146 static void tda998x_destroy(struct tda998x_priv *priv)
1147 {
1148         /* disable all IRQs and free the IRQ handler */
1149         cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1150         reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1151         if (priv->hdmi->irq) {
1152                 free_irq(priv->hdmi->irq, priv);
1153                 cancel_delayed_work_sync(&priv->dwork);
1154         }
1155
1156         i2c_unregister_device(priv->cec);
1157 }
1158
1159 /* Slave encoder support */
1160
1161 static void
1162 tda998x_encoder_slave_set_config(struct drm_encoder *encoder, void *params)
1163 {
1164         tda998x_encoder_set_config(to_tda998x_priv(encoder), params);
1165 }
1166
1167 static void tda998x_encoder_slave_destroy(struct drm_encoder *encoder)
1168 {
1169         struct tda998x_priv *priv = to_tda998x_priv(encoder);
1170
1171         tda998x_destroy(priv);
1172         drm_i2c_encoder_destroy(encoder);
1173         kfree(priv);
1174 }
1175
1176 static void tda998x_encoder_slave_dpms(struct drm_encoder *encoder, int mode)
1177 {
1178         tda998x_encoder_dpms(to_tda998x_priv(encoder), mode);
1179 }
1180
1181 static int tda998x_encoder_slave_mode_valid(struct drm_encoder *encoder,
1182                                             struct drm_display_mode *mode)
1183 {
1184         return tda998x_encoder_mode_valid(to_tda998x_priv(encoder), mode);
1185 }
1186
1187 static void
1188 tda998x_encoder_slave_mode_set(struct drm_encoder *encoder,
1189                                struct drm_display_mode *mode,
1190                                struct drm_display_mode *adjusted_mode)
1191 {
1192         tda998x_encoder_mode_set(to_tda998x_priv(encoder), mode, adjusted_mode);
1193 }
1194
1195 static enum drm_connector_status
1196 tda998x_encoder_slave_detect(struct drm_encoder *encoder,
1197                              struct drm_connector *connector)
1198 {
1199         return tda998x_encoder_detect(to_tda998x_priv(encoder));
1200 }
1201
1202 static int tda998x_encoder_slave_get_modes(struct drm_encoder *encoder,
1203                                            struct drm_connector *connector)
1204 {
1205         return tda998x_encoder_get_modes(to_tda998x_priv(encoder), connector);
1206 }
1207
1208 static int
1209 tda998x_encoder_slave_create_resources(struct drm_encoder *encoder,
1210                                        struct drm_connector *connector)
1211 {
1212         tda998x_encoder_set_polling(to_tda998x_priv(encoder), connector);
1213         return 0;
1214 }
1215
1216 static struct drm_encoder_slave_funcs tda998x_encoder_slave_funcs = {
1217         .set_config = tda998x_encoder_slave_set_config,
1218         .destroy = tda998x_encoder_slave_destroy,
1219         .dpms = tda998x_encoder_slave_dpms,
1220         .save = tda998x_encoder_save,
1221         .restore = tda998x_encoder_restore,
1222         .mode_fixup = tda998x_encoder_mode_fixup,
1223         .mode_valid = tda998x_encoder_slave_mode_valid,
1224         .mode_set = tda998x_encoder_slave_mode_set,
1225         .detect = tda998x_encoder_slave_detect,
1226         .get_modes = tda998x_encoder_slave_get_modes,
1227         .create_resources = tda998x_encoder_slave_create_resources,
1228         .set_property = tda998x_encoder_set_property,
1229 };
1230
1231 /* I2C driver functions */
1232
1233 static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
1234 {
1235         struct device_node *np = client->dev.of_node;
1236         u32 video;
1237         int rev_lo, rev_hi, ret;
1238         unsigned short cec_addr;
1239
1240         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1241         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1242         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1243
1244         priv->current_page = 0xff;
1245         priv->hdmi = client;
1246         /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1247         cec_addr = 0x34 + (client->addr & 0x03);
1248         priv->cec = i2c_new_dummy(client->adapter, cec_addr);
1249         if (!priv->cec)
1250                 return -ENODEV;
1251
1252         priv->dpms = DRM_MODE_DPMS_OFF;
1253
1254         mutex_init(&priv->mutex);       /* protect the page access */
1255
1256         /* wake up the device: */
1257         cec_write(priv, REG_CEC_ENAMODS,
1258                         CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1259
1260         tda998x_reset(priv);
1261
1262         /* read version: */
1263         rev_lo = reg_read(priv, REG_VERSION_LSB);
1264         rev_hi = reg_read(priv, REG_VERSION_MSB);
1265         if (rev_lo < 0 || rev_hi < 0) {
1266                 ret = rev_lo < 0 ? rev_lo : rev_hi;
1267                 goto fail;
1268         }
1269
1270         priv->rev = rev_lo | rev_hi << 8;
1271
1272         /* mask off feature bits: */
1273         priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1274
1275         switch (priv->rev) {
1276         case TDA9989N2:
1277                 dev_info(&client->dev, "found TDA9989 n2");
1278                 break;
1279         case TDA19989:
1280                 dev_info(&client->dev, "found TDA19989");
1281                 break;
1282         case TDA19989N2:
1283                 dev_info(&client->dev, "found TDA19989 n2");
1284                 break;
1285         case TDA19988:
1286                 dev_info(&client->dev, "found TDA19988");
1287                 break;
1288         default:
1289                 dev_err(&client->dev, "found unsupported device: %04x\n",
1290                         priv->rev);
1291                 goto fail;
1292         }
1293
1294         /* after reset, enable DDC: */
1295         reg_write(priv, REG_DDC_DISABLE, 0x00);
1296
1297         /* set clock on DDC channel: */
1298         reg_write(priv, REG_TX3, 39);
1299
1300         /* if necessary, disable multi-master: */
1301         if (priv->rev == TDA19989)
1302                 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1303
1304         cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1305                         CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1306
1307         /* initialize the optional IRQ */
1308         if (client->irq) {
1309                 int irqf_trigger;
1310
1311                 /* init read EDID waitqueue and HDP work */
1312                 init_waitqueue_head(&priv->wq_edid);
1313                 INIT_DELAYED_WORK(&priv->dwork, tda998x_hpd);
1314
1315                 /* clear pending interrupts */
1316                 reg_read(priv, REG_INT_FLAGS_0);
1317                 reg_read(priv, REG_INT_FLAGS_1);
1318                 reg_read(priv, REG_INT_FLAGS_2);
1319
1320                 irqf_trigger =
1321                         irqd_get_trigger_type(irq_get_irq_data(client->irq));
1322                 ret = request_threaded_irq(client->irq, NULL,
1323                                            tda998x_irq_thread,
1324                                            irqf_trigger | IRQF_ONESHOT,
1325                                            "tda998x", priv);
1326                 if (ret) {
1327                         dev_err(&client->dev,
1328                                 "failed to request IRQ#%u: %d\n",
1329                                 client->irq, ret);
1330                         goto fail;
1331                 }
1332
1333                 /* enable HPD irq */
1334                 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1335         }
1336
1337         /* enable EDID read irq: */
1338         reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1339
1340         if (!np)
1341                 return 0;               /* non-DT */
1342
1343         /* get the optional video properties */
1344         ret = of_property_read_u32(np, "video-ports", &video);
1345         if (ret == 0) {
1346                 priv->vip_cntrl_0 = video >> 16;
1347                 priv->vip_cntrl_1 = video >> 8;
1348                 priv->vip_cntrl_2 = video;
1349         }
1350
1351         return 0;
1352
1353 fail:
1354         /* if encoder_init fails, the encoder slave is never registered,
1355          * so cleanup here:
1356          */
1357         if (priv->cec)
1358                 i2c_unregister_device(priv->cec);
1359         return -ENXIO;
1360 }
1361
1362 static int tda998x_encoder_init(struct i2c_client *client,
1363                                 struct drm_device *dev,
1364                                 struct drm_encoder_slave *encoder_slave)
1365 {
1366         struct tda998x_priv *priv;
1367         int ret;
1368
1369         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1370         if (!priv)
1371                 return -ENOMEM;
1372
1373         priv->encoder = &encoder_slave->base;
1374
1375         ret = tda998x_create(client, priv);
1376         if (ret) {
1377                 kfree(priv);
1378                 return ret;
1379         }
1380
1381         encoder_slave->slave_priv = priv;
1382         encoder_slave->slave_funcs = &tda998x_encoder_slave_funcs;
1383
1384         return 0;
1385 }
1386
1387 struct tda998x_priv2 {
1388         struct tda998x_priv base;
1389         struct drm_encoder encoder;
1390         struct drm_connector connector;
1391 };
1392
1393 #define conn_to_tda998x_priv2(x) \
1394         container_of(x, struct tda998x_priv2, connector);
1395
1396 #define enc_to_tda998x_priv2(x) \
1397         container_of(x, struct tda998x_priv2, encoder);
1398
1399 static void tda998x_encoder2_dpms(struct drm_encoder *encoder, int mode)
1400 {
1401         struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1402
1403         tda998x_encoder_dpms(&priv->base, mode);
1404 }
1405
1406 static void tda998x_encoder_prepare(struct drm_encoder *encoder)
1407 {
1408         tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_OFF);
1409 }
1410
1411 static void tda998x_encoder_commit(struct drm_encoder *encoder)
1412 {
1413         tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_ON);
1414 }
1415
1416 static void tda998x_encoder2_mode_set(struct drm_encoder *encoder,
1417                                       struct drm_display_mode *mode,
1418                                       struct drm_display_mode *adjusted_mode)
1419 {
1420         struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1421
1422         tda998x_encoder_mode_set(&priv->base, mode, adjusted_mode);
1423 }
1424
1425 static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
1426         .dpms = tda998x_encoder2_dpms,
1427         .save = tda998x_encoder_save,
1428         .restore = tda998x_encoder_restore,
1429         .mode_fixup = tda998x_encoder_mode_fixup,
1430         .prepare = tda998x_encoder_prepare,
1431         .commit = tda998x_encoder_commit,
1432         .mode_set = tda998x_encoder2_mode_set,
1433 };
1434
1435 static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1436 {
1437         struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1438
1439         tda998x_destroy(&priv->base);
1440         drm_encoder_cleanup(encoder);
1441 }
1442
1443 static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1444         .destroy = tda998x_encoder_destroy,
1445 };
1446
1447 static int tda998x_connector_get_modes(struct drm_connector *connector)
1448 {
1449         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1450
1451         return tda998x_encoder_get_modes(&priv->base, connector);
1452 }
1453
1454 static int tda998x_connector_mode_valid(struct drm_connector *connector,
1455                                         struct drm_display_mode *mode)
1456 {
1457         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1458
1459         return tda998x_encoder_mode_valid(&priv->base, mode);
1460 }
1461
1462 static struct drm_encoder *
1463 tda998x_connector_best_encoder(struct drm_connector *connector)
1464 {
1465         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1466
1467         return &priv->encoder;
1468 }
1469
1470 static
1471 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1472         .get_modes = tda998x_connector_get_modes,
1473         .mode_valid = tda998x_connector_mode_valid,
1474         .best_encoder = tda998x_connector_best_encoder,
1475 };
1476
1477 static enum drm_connector_status
1478 tda998x_connector_detect(struct drm_connector *connector, bool force)
1479 {
1480         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1481
1482         return tda998x_encoder_detect(&priv->base);
1483 }
1484
1485 static void tda998x_connector_destroy(struct drm_connector *connector)
1486 {
1487         drm_connector_unregister(connector);
1488         drm_connector_cleanup(connector);
1489 }
1490
1491 static const struct drm_connector_funcs tda998x_connector_funcs = {
1492         .dpms = drm_helper_connector_dpms,
1493         .fill_modes = drm_helper_probe_single_connector_modes,
1494         .detect = tda998x_connector_detect,
1495         .destroy = tda998x_connector_destroy,
1496 };
1497
1498 static int tda998x_bind(struct device *dev, struct device *master, void *data)
1499 {
1500         struct tda998x_encoder_params *params = dev->platform_data;
1501         struct i2c_client *client = to_i2c_client(dev);
1502         struct drm_device *drm = data;
1503         struct tda998x_priv2 *priv;
1504         uint32_t crtcs = 0;
1505         int ret;
1506
1507         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1508         if (!priv)
1509                 return -ENOMEM;
1510
1511         dev_set_drvdata(dev, priv);
1512
1513         if (dev->of_node)
1514                 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1515
1516         /* If no CRTCs were found, fall back to our old behaviour */
1517         if (crtcs == 0) {
1518                 dev_warn(dev, "Falling back to first CRTC\n");
1519                 crtcs = 1 << 0;
1520         }
1521
1522         priv->base.encoder = &priv->encoder;
1523         priv->connector.interlace_allowed = 1;
1524         priv->encoder.possible_crtcs = crtcs;
1525
1526         ret = tda998x_create(client, &priv->base);
1527         if (ret)
1528                 return ret;
1529
1530         if (!dev->of_node && params)
1531                 tda998x_encoder_set_config(&priv->base, params);
1532
1533         tda998x_encoder_set_polling(&priv->base, &priv->connector);
1534
1535         drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
1536         ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
1537                                DRM_MODE_ENCODER_TMDS);
1538         if (ret)
1539                 goto err_encoder;
1540
1541         drm_connector_helper_add(&priv->connector,
1542                                  &tda998x_connector_helper_funcs);
1543         ret = drm_connector_init(drm, &priv->connector,
1544                                  &tda998x_connector_funcs,
1545                                  DRM_MODE_CONNECTOR_HDMIA);
1546         if (ret)
1547                 goto err_connector;
1548
1549         ret = drm_connector_register(&priv->connector);
1550         if (ret)
1551                 goto err_sysfs;
1552
1553         priv->connector.encoder = &priv->encoder;
1554         drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
1555
1556         return 0;
1557
1558 err_sysfs:
1559         drm_connector_cleanup(&priv->connector);
1560 err_connector:
1561         drm_encoder_cleanup(&priv->encoder);
1562 err_encoder:
1563         tda998x_destroy(&priv->base);
1564         return ret;
1565 }
1566
1567 static void tda998x_unbind(struct device *dev, struct device *master,
1568                            void *data)
1569 {
1570         struct tda998x_priv2 *priv = dev_get_drvdata(dev);
1571
1572         drm_connector_cleanup(&priv->connector);
1573         drm_encoder_cleanup(&priv->encoder);
1574         tda998x_destroy(&priv->base);
1575 }
1576
1577 static const struct component_ops tda998x_ops = {
1578         .bind = tda998x_bind,
1579         .unbind = tda998x_unbind,
1580 };
1581
1582 static int
1583 tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1584 {
1585         return component_add(&client->dev, &tda998x_ops);
1586 }
1587
1588 static int tda998x_remove(struct i2c_client *client)
1589 {
1590         component_del(&client->dev, &tda998x_ops);
1591         return 0;
1592 }
1593
1594 #ifdef CONFIG_OF
1595 static const struct of_device_id tda998x_dt_ids[] = {
1596         { .compatible = "nxp,tda998x", },
1597         { }
1598 };
1599 MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1600 #endif
1601
1602 static struct i2c_device_id tda998x_ids[] = {
1603         { "tda998x", 0 },
1604         { }
1605 };
1606 MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1607
1608 static struct drm_i2c_encoder_driver tda998x_driver = {
1609         .i2c_driver = {
1610                 .probe = tda998x_probe,
1611                 .remove = tda998x_remove,
1612                 .driver = {
1613                         .name = "tda998x",
1614                         .of_match_table = of_match_ptr(tda998x_dt_ids),
1615                 },
1616                 .id_table = tda998x_ids,
1617         },
1618         .encoder_init = tda998x_encoder_init,
1619 };
1620
1621 /* Module initialization */
1622
1623 static int __init
1624 tda998x_init(void)
1625 {
1626         DBG("");
1627         return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver);
1628 }
1629
1630 static void __exit
1631 tda998x_exit(void)
1632 {
1633         DBG("");
1634         drm_i2c_encoder_unregister(&tda998x_driver);
1635 }
1636
1637 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1638 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1639 MODULE_LICENSE("GPL");
1640
1641 module_init(tda998x_init);
1642 module_exit(tda998x_exit);