drivers/gpu/drm/exynos/exynos_drm_fimd.c

   1 /* exynos_drm_fimd.c
   2  *
   3  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Inki Dae <inki.dae@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include <drm/drmP.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/component.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/regmap.h>
  25
  26 #include <video/of_display_timing.h>
  27 #include <video/of_videomode.h>
  28 #include <video/samsung_fimd.h>
  29 #include <drm/exynos_drm.h>
  30
  31 #include "exynos_drm_drv.h"
  32 #include "exynos_drm_fb.h"
  33 #include "exynos_drm_crtc.h"
  34 #include "exynos_drm_plane.h"
  35
  36 /*
  37  * FIMD stands for Fully Interactive Mobile Display and
  38  * as a display controller, it transfers contents drawn on memory
  39  * to a LCD Panel through Display Interfaces such as RGB or
  40  * CPU Interface.
  41  */
  42
  43 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
  44
  45 /* position control register for hardware window 0, 2 ~ 4.*/
  46 #define VIDOSD_A(win)           (VIDOSD_BASE + 0x00 + (win) * 16)
  47 #define VIDOSD_B(win)           (VIDOSD_BASE + 0x04 + (win) * 16)
  48 /*
  49  * size control register for hardware windows 0 and alpha control register
  50  * for hardware windows 1 ~ 4
  51  */
  52 #define VIDOSD_C(win)           (VIDOSD_BASE + 0x08 + (win) * 16)
  53 /* size control register for hardware windows 1 ~ 2. */
  54 #define VIDOSD_D(win)           (VIDOSD_BASE + 0x0C + (win) * 16)
  55
  56 #define VIDWnALPHA0(win)        (VIDW_ALPHA + 0x00 + (win) * 8)
  57 #define VIDWnALPHA1(win)        (VIDW_ALPHA + 0x04 + (win) * 8)
  58
  59 #define VIDWx_BUF_START(win, buf)       (VIDW_BUF_START(buf) + (win) * 8)
  60 #define VIDWx_BUF_START_S(win, buf)     (VIDW_BUF_START_S(buf) + (win) * 8)
  61 #define VIDWx_BUF_END(win, buf)         (VIDW_BUF_END(buf) + (win) * 8)
  62 #define VIDWx_BUF_SIZE(win, buf)        (VIDW_BUF_SIZE(buf) + (win) * 4)
  63
  64 /* color key control register for hardware window 1 ~ 4. */
  65 #define WKEYCON0_BASE(x)                ((WKEYCON0 + 0x140) + ((x - 1) * 8))
  66 /* color key value register for hardware window 1 ~ 4. */
  67 #define WKEYCON1_BASE(x)                ((WKEYCON1 + 0x140) + ((x - 1) * 8))
  68
  69 /* I80 trigger control register */
  70 #define TRIGCON                         0x1A4
  71 #define TRGMODE_ENABLE                  (1 << 0)
  72 #define SWTRGCMD_ENABLE                 (1 << 1)
  73 /* Exynos3250, 3472, 5260 5410, 5420 and 5422 only supported. */
  74 #define HWTRGEN_ENABLE                  (1 << 3)
  75 #define HWTRGMASK_ENABLE                (1 << 4)
  76 /* Exynos3250, 3472, 5260, 5420 and 5422 only supported. */
  77 #define HWTRIGEN_PER_ENABLE             (1 << 31)
  78
  79 /* display mode change control register except exynos4 */
  80 #define VIDOUT_CON                      0x000
  81 #define VIDOUT_CON_F_I80_LDI0           (0x2 << 8)
  82
  83 /* I80 interface control for main LDI register */
  84 #define I80IFCONFAx(x)                  (0x1B0 + (x) * 4)
  85 #define I80IFCONFBx(x)                  (0x1B8 + (x) * 4)
  86 #define LCD_CS_SETUP(x)                 ((x) << 16)
  87 #define LCD_WR_SETUP(x)                 ((x) << 12)
  88 #define LCD_WR_ACTIVE(x)                ((x) << 8)
  89 #define LCD_WR_HOLD(x)                  ((x) << 4)
  90 #define I80IFEN_ENABLE                  (1 << 0)
  91
  92 /* FIMD has totally five hardware windows. */
  93 #define WINDOWS_NR      5
  94
  95 /* HW trigger flag on i80 panel. */
  96 #define I80_HW_TRG     (1 << 1)
  97
  98 struct fimd_driver_data {
  99         unsigned int timing_base;
 100         unsigned int lcdblk_offset;
 101         unsigned int lcdblk_vt_shift;
 102         unsigned int lcdblk_bypass_shift;
 103         unsigned int lcdblk_mic_bypass_shift;
 104         unsigned int trg_type;
 105
 106         unsigned int has_shadowcon:1;
 107         unsigned int has_clksel:1;
 108         unsigned int has_limited_fmt:1;
 109         unsigned int has_vidoutcon:1;
 110         unsigned int has_vtsel:1;
 111         unsigned int has_mic_bypass:1;
 112         unsigned int has_dp_clk:1;
 113         unsigned int has_hw_trigger:1;
 114         unsigned int has_trigger_per_te:1;
 115 };
 116
 117 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
 118         .timing_base = 0x0,
 119         .has_clksel = 1,
 120         .has_limited_fmt = 1,
 121 };
 122
 123 static struct fimd_driver_data s5pv210_fimd_driver_data = {
 124         .timing_base = 0x0,
 125         .has_shadowcon = 1,
 126         .has_clksel = 1,
 127 };
 128
 129 static struct fimd_driver_data exynos3_fimd_driver_data = {
 130         .timing_base = 0x20000,
 131         .lcdblk_offset = 0x210,
 132         .lcdblk_bypass_shift = 1,
 133         .has_shadowcon = 1,
 134         .has_vidoutcon = 1,
 135 };
 136
 137 static struct fimd_driver_data exynos4_fimd_driver_data = {
 138         .timing_base = 0x0,
 139         .lcdblk_offset = 0x210,
 140         .lcdblk_vt_shift = 10,
 141         .lcdblk_bypass_shift = 1,
 142         .has_shadowcon = 1,
 143         .has_vtsel = 1,
 144 };
 145
 146 static struct fimd_driver_data exynos5_fimd_driver_data = {
 147         .timing_base = 0x20000,
 148         .lcdblk_offset = 0x214,
 149         .lcdblk_vt_shift = 24,
 150         .lcdblk_bypass_shift = 15,
 151         .has_shadowcon = 1,
 152         .has_vidoutcon = 1,
 153         .has_vtsel = 1,
 154         .has_dp_clk = 1,
 155 };
 156
 157 static struct fimd_driver_data exynos5420_fimd_driver_data = {
 158         .timing_base = 0x20000,
 159         .lcdblk_offset = 0x214,
 160         .lcdblk_vt_shift = 24,
 161         .lcdblk_bypass_shift = 15,
 162         .lcdblk_mic_bypass_shift = 11,
 163         .has_shadowcon = 1,
 164         .has_vidoutcon = 1,
 165         .has_vtsel = 1,
 166         .has_mic_bypass = 1,
 167         .has_dp_clk = 1,
 168 };
 169
 170 struct fimd_context {
 171         struct device                   *dev;
 172         struct drm_device               *drm_dev;
 173         struct exynos_drm_crtc          *crtc;
 174         struct exynos_drm_plane         planes[WINDOWS_NR];
 175         struct exynos_drm_plane_config  configs[WINDOWS_NR];
 176         struct clk                      *bus_clk;
 177         struct clk                      *lcd_clk;
 178         void __iomem                    *regs;
 179         struct regmap                   *sysreg;
 180         unsigned long                   irq_flags;
 181         u32                             vidcon0;
 182         u32                             vidcon1;
 183         u32                             vidout_con;
 184         u32                             i80ifcon;
 185         bool                            i80_if;
 186         bool                            suspended;
 187         wait_queue_head_t               wait_vsync_queue;
 188         atomic_t                        wait_vsync_event;
 189         atomic_t                        win_updated;
 190         atomic_t                        triggering;
 191         u32                             clkdiv;
 192
 193         const struct fimd_driver_data *driver_data;
 194         struct drm_encoder *encoder;
 195         struct exynos_drm_clk           dp_clk;
 196 };
 197
 198 static const struct of_device_id fimd_driver_dt_match[] = {
 199         { .compatible = "samsung,s3c6400-fimd",
 200           .data = &s3c64xx_fimd_driver_data },
 201         { .compatible = "samsung,s5pv210-fimd",
 202           .data = &s5pv210_fimd_driver_data },
 203         { .compatible = "samsung,exynos3250-fimd",
 204           .data = &exynos3_fimd_driver_data },
 205         { .compatible = "samsung,exynos4210-fimd",
 206           .data = &exynos4_fimd_driver_data },
 207         { .compatible = "samsung,exynos5250-fimd",
 208           .data = &exynos5_fimd_driver_data },
 209         { .compatible = "samsung,exynos5420-fimd",
 210           .data = &exynos5420_fimd_driver_data },
 211         {},
 212 };
 213 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
 214
 215 static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = {
 216         DRM_PLANE_TYPE_PRIMARY,
 217         DRM_PLANE_TYPE_OVERLAY,
 218         DRM_PLANE_TYPE_OVERLAY,
 219         DRM_PLANE_TYPE_OVERLAY,
 220         DRM_PLANE_TYPE_CURSOR,
 221 };
 222
 223 static const uint32_t fimd_formats[] = {
 224         DRM_FORMAT_C8,
 225         DRM_FORMAT_XRGB1555,
 226         DRM_FORMAT_RGB565,
 227         DRM_FORMAT_XRGB8888,
 228         DRM_FORMAT_ARGB8888,
 229 };
 230
 231 static const unsigned int capabilities[WINDOWS_NR] = {
 232         0,
 233         EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
 234         EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
 235         EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
 236         EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
 237 };
 238
 239 static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask,
 240                                  u32 val)
 241 {
 242         val = (val & mask) | (readl(ctx->regs + reg) & ~mask);
 243         writel(val, ctx->regs + reg);
 244 }
 245
 246 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
 247 {
 248         struct fimd_context *ctx = crtc->ctx;
 249         u32 val;
 250
 251         if (ctx->suspended)
 252                 return -EPERM;
 253
 254         if (!test_and_set_bit(0, &ctx->irq_flags)) {
 255                 val = readl(ctx->regs + VIDINTCON0);
 256
 257                 val |= VIDINTCON0_INT_ENABLE;
 258
 259                 if (ctx->i80_if) {
 260                         val |= VIDINTCON0_INT_I80IFDONE;
 261                         val |= VIDINTCON0_INT_SYSMAINCON;
 262                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 263                 } else {
 264                         val |= VIDINTCON0_INT_FRAME;
 265
 266                         val &= ~VIDINTCON0_FRAMESEL0_MASK;
 267                         val |= VIDINTCON0_FRAMESEL0_FRONTPORCH;
 268                         val &= ~VIDINTCON0_FRAMESEL1_MASK;
 269                         val |= VIDINTCON0_FRAMESEL1_NONE;
 270                 }
 271
 272                 writel(val, ctx->regs + VIDINTCON0);
 273         }
 274
 275         return 0;
 276 }
 277
 278 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
 279 {
 280         struct fimd_context *ctx = crtc->ctx;
 281         u32 val;
 282
 283         if (ctx->suspended)
 284                 return;
 285
 286         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 287                 val = readl(ctx->regs + VIDINTCON0);
 288
 289                 val &= ~VIDINTCON0_INT_ENABLE;
 290
 291                 if (ctx->i80_if) {
 292                         val &= ~VIDINTCON0_INT_I80IFDONE;
 293                         val &= ~VIDINTCON0_INT_SYSMAINCON;
 294                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 295                 } else
 296                         val &= ~VIDINTCON0_INT_FRAME;
 297
 298                 writel(val, ctx->regs + VIDINTCON0);
 299         }
 300 }
 301
 302 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
 303 {
 304         struct fimd_context *ctx = crtc->ctx;
 305
 306         if (ctx->suspended)
 307                 return;
 308
 309         atomic_set(&ctx->wait_vsync_event, 1);
 310
 311         /*
 312          * wait for FIMD to signal VSYNC interrupt or return after
 313          * timeout which is set to 50ms (refresh rate of 20).
 314          */
 315         if (!wait_event_timeout(ctx->wait_vsync_queue,
 316                                 !atomic_read(&ctx->wait_vsync_event),
 317                                 HZ/20))
 318                 DRM_DEBUG_KMS("vblank wait timed out.\n");
 319 }
 320
 321 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
 322                                         bool enable)
 323 {
 324         u32 val = readl(ctx->regs + WINCON(win));
 325
 326         if (enable)
 327                 val |= WINCONx_ENWIN;
 328         else
 329                 val &= ~WINCONx_ENWIN;
 330
 331         writel(val, ctx->regs + WINCON(win));
 332 }
 333
 334 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
 335                                                 unsigned int win,
 336                                                 bool enable)
 337 {
 338         u32 val = readl(ctx->regs + SHADOWCON);
 339
 340         if (enable)
 341                 val |= SHADOWCON_CHx_ENABLE(win);
 342         else
 343                 val &= ~SHADOWCON_CHx_ENABLE(win);
 344
 345         writel(val, ctx->regs + SHADOWCON);
 346 }
 347
 348 static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
 349 {
 350         struct fimd_context *ctx = crtc->ctx;
 351         unsigned int win, ch_enabled = 0;
 352
 353         DRM_DEBUG_KMS("%s\n", __FILE__);
 354
 355         /* Hardware is in unknown state, so ensure it gets enabled properly */
 356         pm_runtime_get_sync(ctx->dev);
 357
 358         clk_prepare_enable(ctx->bus_clk);
 359         clk_prepare_enable(ctx->lcd_clk);
 360
 361         /* Check if any channel is enabled. */
 362         for (win = 0; win < WINDOWS_NR; win++) {
 363                 u32 val = readl(ctx->regs + WINCON(win));
 364
 365                 if (val & WINCONx_ENWIN) {
 366                         fimd_enable_video_output(ctx, win, false);
 367
 368                         if (ctx->driver_data->has_shadowcon)
 369                                 fimd_enable_shadow_channel_path(ctx, win,
 370                                                                 false);
 371
 372                         ch_enabled = 1;
 373                 }
 374         }
 375
 376         /* Wait for vsync, as disable channel takes effect at next vsync */
 377         if (ch_enabled) {
 378                 ctx->suspended = false;
 379
 380                 fimd_enable_vblank(ctx->crtc);
 381                 fimd_wait_for_vblank(ctx->crtc);
 382                 fimd_disable_vblank(ctx->crtc);
 383
 384                 ctx->suspended = true;
 385         }
 386
 387         clk_disable_unprepare(ctx->lcd_clk);
 388         clk_disable_unprepare(ctx->bus_clk);
 389
 390         pm_runtime_put(ctx->dev);
 391 }
 392
 393
 394 static int fimd_atomic_check(struct exynos_drm_crtc *crtc,
 395                 struct drm_crtc_state *state)
 396 {
 397         struct drm_display_mode *mode = &state->adjusted_mode;
 398         struct fimd_context *ctx = crtc->ctx;
 399         unsigned long ideal_clk, lcd_rate;
 400         u32 clkdiv;
 401
 402         if (mode->clock == 0) {
 403                 DRM_INFO("Mode has zero clock value.\n");
 404                 return -EINVAL;
 405         }
 406
 407         ideal_clk = mode->clock * 1000;
 408
 409         if (ctx->i80_if) {
 410                 /*
 411                  * The frame done interrupt should be occurred prior to the
 412                  * next TE signal.
 413                  */
 414                 ideal_clk *= 2;
 415         }
 416
 417         lcd_rate = clk_get_rate(ctx->lcd_clk);
 418         if (2 * lcd_rate < ideal_clk) {
 419                 DRM_INFO("sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n",
 420                          lcd_rate, ideal_clk);
 421                 return -EINVAL;
 422         }
 423
 424         /* Find the clock divider value that gets us closest to ideal_clk */
 425         clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk);
 426         if (clkdiv >= 0x200) {
 427                 DRM_INFO("requested pixel clock(%lu) too low\n", ideal_clk);
 428                 return -EINVAL;
 429         }
 430
 431         ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff;
 432
 433         return 0;
 434 }
 435
 436 static void fimd_setup_trigger(struct fimd_context *ctx)
 437 {
 438         void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base;
 439         u32 trg_type = ctx->driver_data->trg_type;
 440         u32 val = readl(timing_base + TRIGCON);
 441
 442         val &= ~(TRGMODE_ENABLE);
 443
 444         if (trg_type == I80_HW_TRG) {
 445                 if (ctx->driver_data->has_hw_trigger)
 446                         val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE;
 447                 if (ctx->driver_data->has_trigger_per_te)
 448                         val |= HWTRIGEN_PER_ENABLE;
 449         } else {
 450                 val |= TRGMODE_ENABLE;
 451         }
 452
 453         writel(val, timing_base + TRIGCON);
 454 }
 455
 456 static void fimd_commit(struct exynos_drm_crtc *crtc)
 457 {
 458         struct fimd_context *ctx = crtc->ctx;
 459         struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
 460         const struct fimd_driver_data *driver_data = ctx->driver_data;
 461         void *timing_base = ctx->regs + driver_data->timing_base;
 462         u32 val;
 463
 464         if (ctx->suspended)
 465                 return;
 466
 467         /* nothing to do if we haven't set the mode yet */
 468         if (mode->htotal == 0 || mode->vtotal == 0)
 469                 return;
 470
 471         if (ctx->i80_if) {
 472                 val = ctx->i80ifcon | I80IFEN_ENABLE;
 473                 writel(val, timing_base + I80IFCONFAx(0));
 474
 475                 /* disable auto frame rate */
 476                 writel(0, timing_base + I80IFCONFBx(0));
 477
 478                 /* set video type selection to I80 interface */
 479                 if (driver_data->has_vtsel && ctx->sysreg &&
 480                                 regmap_update_bits(ctx->sysreg,
 481                                         driver_data->lcdblk_offset,
 482                                         0x3 << driver_data->lcdblk_vt_shift,
 483                                         0x1 << driver_data->lcdblk_vt_shift)) {
 484                         DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
 485                         return;
 486                 }
 487         } else {
 488                 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
 489                 u32 vidcon1;
 490
 491                 /* setup polarity values */
 492                 vidcon1 = ctx->vidcon1;
 493                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 494                         vidcon1 |= VIDCON1_INV_VSYNC;
 495                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 496                         vidcon1 |= VIDCON1_INV_HSYNC;
 497                 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
 498
 499                 /* setup vertical timing values. */
 500                 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
 501                 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
 502                 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
 503
 504                 val = VIDTCON0_VBPD(vbpd - 1) |
 505                         VIDTCON0_VFPD(vfpd - 1) |
 506                         VIDTCON0_VSPW(vsync_len - 1);
 507                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
 508
 509                 /* setup horizontal timing values.  */
 510                 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
 511                 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
 512                 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
 513
 514                 val = VIDTCON1_HBPD(hbpd - 1) |
 515                         VIDTCON1_HFPD(hfpd - 1) |
 516                         VIDTCON1_HSPW(hsync_len - 1);
 517                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
 518         }
 519
 520         if (driver_data->has_vidoutcon)
 521                 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
 522
 523         /* set bypass selection */
 524         if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
 525                                 driver_data->lcdblk_offset,
 526                                 0x1 << driver_data->lcdblk_bypass_shift,
 527                                 0x1 << driver_data->lcdblk_bypass_shift)) {
 528                 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
 529                 return;
 530         }
 531
 532         /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass
 533          * bit should be cleared.
 534          */
 535         if (driver_data->has_mic_bypass && ctx->sysreg &&
 536             regmap_update_bits(ctx->sysreg,
 537                                 driver_data->lcdblk_offset,
 538                                 0x1 << driver_data->lcdblk_mic_bypass_shift,
 539                                 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
 540                 DRM_ERROR("Failed to update sysreg for bypass mic.\n");
 541                 return;
 542         }
 543
 544         /* setup horizontal and vertical display size. */
 545         val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
 546                VIDTCON2_HOZVAL(mode->hdisplay - 1) |
 547                VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
 548                VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
 549         writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
 550
 551         fimd_setup_trigger(ctx);
 552
 553         /*
 554          * fields of register with prefix '_F' would be updated
 555          * at vsync(same as dma start)
 556          */
 557         val = ctx->vidcon0;
 558         val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 559
 560         if (ctx->driver_data->has_clksel)
 561                 val |= VIDCON0_CLKSEL_LCD;
 562
 563         if (ctx->clkdiv > 1)
 564                 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
 565
 566         writel(val, ctx->regs + VIDCON0);
 567 }
 568
 569 static void fimd_win_set_bldeq(struct fimd_context *ctx, unsigned int win,
 570                                unsigned int alpha, unsigned int pixel_alpha)
 571 {
 572         u32 mask = BLENDEQ_A_FUNC_F(0xf) | BLENDEQ_B_FUNC_F(0xf);
 573         u32 val = 0;
 574
 575         switch (pixel_alpha) {
 576         case DRM_MODE_BLEND_PIXEL_NONE:
 577         case DRM_MODE_BLEND_COVERAGE:
 578                 val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA_A);
 579                 val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
 580                 break;
 581         case DRM_MODE_BLEND_PREMULTI:
 582         default:
 583                 if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
 584                         val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA0);
 585                         val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
 586                 } else {
 587                         val |= BLENDEQ_A_FUNC_F(BLENDEQ_ONE);
 588                         val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
 589                 }
 590                 break;
 591         }
 592         fimd_set_bits(ctx, BLENDEQx(win), mask, val);
 593 }
 594
 595 static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win,
 596                                 unsigned int alpha, unsigned int pixel_alpha)
 597 {
 598         u32 win_alpha_l = (alpha >> 8) & 0xf;
 599         u32 win_alpha_h = alpha >> 12;
 600         u32 val = 0;
 601
 602         switch (pixel_alpha) {
 603         case DRM_MODE_BLEND_PIXEL_NONE:
 604                 break;
 605         case DRM_MODE_BLEND_COVERAGE:
 606         case DRM_MODE_BLEND_PREMULTI:
 607         default:
 608                 val |= WINCON1_ALPHA_SEL;
 609                 val |= WINCON1_BLD_PIX;
 610                 val |= WINCON1_ALPHA_MUL;
 611                 break;
 612         }
 613         fimd_set_bits(ctx, WINCON(win), WINCONx_BLEND_MODE_MASK, val);
 614
 615         /* OSD alpha */
 616         val = VIDISD14C_ALPHA0_R(win_alpha_h) |
 617                 VIDISD14C_ALPHA0_G(win_alpha_h) |
 618                 VIDISD14C_ALPHA0_B(win_alpha_h) |
 619                 VIDISD14C_ALPHA1_R(0x0) |
 620                 VIDISD14C_ALPHA1_G(0x0) |
 621                 VIDISD14C_ALPHA1_B(0x0);
 622         writel(val, ctx->regs + VIDOSD_C(win));
 623
 624         val = VIDW_ALPHA_R(win_alpha_l) | VIDW_ALPHA_G(win_alpha_l) |
 625                 VIDW_ALPHA_B(win_alpha_l);
 626         writel(val, ctx->regs + VIDWnALPHA0(win));
 627
 628         val = VIDW_ALPHA_R(0x0) | VIDW_ALPHA_G(0x0) |
 629                 VIDW_ALPHA_B(0x0);
 630         writel(val, ctx->regs + VIDWnALPHA1(win));
 631
 632         fimd_set_bits(ctx, BLENDCON, BLENDCON_NEW_MASK,
 633                         BLENDCON_NEW_8BIT_ALPHA_VALUE);
 634 }
 635
 636 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
 637                                 struct drm_framebuffer *fb, int width)
 638 {
 639         struct exynos_drm_plane plane = ctx->planes[win];
 640         struct exynos_drm_plane_state *state =
 641                 to_exynos_plane_state(plane.base.state);
 642         uint32_t pixel_format = fb->format->format;
 643         unsigned int alpha = state->base.alpha;
 644         u32 val = WINCONx_ENWIN;
 645         unsigned int pixel_alpha;
 646
 647         if (fb->format->has_alpha)
 648                 pixel_alpha = state->base.pixel_blend_mode;
 649         else
 650                 pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE;
 651
 652         /*
 653          * In case of s3c64xx, window 0 doesn't support alpha channel.
 654          * So the request format is ARGB8888 then change it to XRGB8888.
 655          */
 656         if (ctx->driver_data->has_limited_fmt && !win) {
 657                 if (pixel_format == DRM_FORMAT_ARGB8888)
 658                         pixel_format = DRM_FORMAT_XRGB8888;
 659         }
 660
 661         switch (pixel_format) {
 662         case DRM_FORMAT_C8:
 663                 val |= WINCON0_BPPMODE_8BPP_PALETTE;
 664                 val |= WINCONx_BURSTLEN_8WORD;
 665                 val |= WINCONx_BYTSWP;
 666                 break;
 667         case DRM_FORMAT_XRGB1555:
 668                 val |= WINCON0_BPPMODE_16BPP_1555;
 669                 val |= WINCONx_HAWSWP;
 670                 val |= WINCONx_BURSTLEN_16WORD;
 671                 break;
 672         case DRM_FORMAT_RGB565:
 673                 val |= WINCON0_BPPMODE_16BPP_565;
 674                 val |= WINCONx_HAWSWP;
 675                 val |= WINCONx_BURSTLEN_16WORD;
 676                 break;
 677         case DRM_FORMAT_XRGB8888:
 678                 val |= WINCON0_BPPMODE_24BPP_888;
 679                 val |= WINCONx_WSWP;
 680                 val |= WINCONx_BURSTLEN_16WORD;
 681                 break;
 682         case DRM_FORMAT_ARGB8888:
 683         default:
 684                 val |= WINCON1_BPPMODE_25BPP_A1888;
 685                 val |= WINCONx_WSWP;
 686                 val |= WINCONx_BURSTLEN_16WORD;
 687                 break;
 688         }
 689
 690         /*
 691          * Setting dma-burst to 16Word causes permanent tearing for very small
 692          * buffers, e.g. cursor buffer. Burst Mode switching which based on
 693          * plane size is not recommended as plane size varies alot towards the
 694          * end of the screen and rapid movement causes unstable DMA, but it is
 695          * still better to change dma-burst than displaying garbage.
 696          */
 697
 698         if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 699                 val &= ~WINCONx_BURSTLEN_MASK;
 700                 val |= WINCONx_BURSTLEN_4WORD;
 701         }
 702         fimd_set_bits(ctx, WINCON(win), ~WINCONx_BLEND_MODE_MASK, val);
 703
 704         /* hardware window 0 doesn't support alpha channel. */
 705         if (win != 0) {
 706                 fimd_win_set_bldmod(ctx, win, alpha, pixel_alpha);
 707                 fimd_win_set_bldeq(ctx, win, alpha, pixel_alpha);
 708         }
 709 }
 710
 711 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
 712 {
 713         unsigned int keycon0 = 0, keycon1 = 0;
 714
 715         keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
 716                         WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 717
 718         keycon1 = WxKEYCON1_COLVAL(0xffffffff);
 719
 720         writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
 721         writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
 722 }
 723
 724 /**
 725  * shadow_protect_win() - disable updating values from shadow registers at vsync
 726  *
 727  * @win: window to protect registers for
 728  * @protect: 1 to protect (disable updates)
 729  */
 730 static void fimd_shadow_protect_win(struct fimd_context *ctx,
 731                                     unsigned int win, bool protect)
 732 {
 733         u32 reg, bits, val;
 734
 735         /*
 736          * SHADOWCON/PRTCON register is used for enabling timing.
 737          *
 738          * for example, once only width value of a register is set,
 739          * if the dma is started then fimd hardware could malfunction so
 740          * with protect window setting, the register fields with prefix '_F'
 741          * wouldn't be updated at vsync also but updated once unprotect window
 742          * is set.
 743          */
 744
 745         if (ctx->driver_data->has_shadowcon) {
 746                 reg = SHADOWCON;
 747                 bits = SHADOWCON_WINx_PROTECT(win);
 748         } else {
 749                 reg = PRTCON;
 750                 bits = PRTCON_PROTECT;
 751         }
 752
 753         val = readl(ctx->regs + reg);
 754         if (protect)
 755                 val |= bits;
 756         else
 757                 val &= ~bits;
 758         writel(val, ctx->regs + reg);
 759 }
 760
 761 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc)
 762 {
 763         struct fimd_context *ctx = crtc->ctx;
 764         int i;
 765
 766         if (ctx->suspended)
 767                 return;
 768
 769         for (i = 0; i < WINDOWS_NR; i++)
 770                 fimd_shadow_protect_win(ctx, i, true);
 771 }
 772
 773 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc)
 774 {
 775         struct fimd_context *ctx = crtc->ctx;
 776         int i;
 777
 778         if (ctx->suspended)
 779                 return;
 780
 781         for (i = 0; i < WINDOWS_NR; i++)
 782                 fimd_shadow_protect_win(ctx, i, false);
 783
 784         exynos_crtc_handle_event(crtc);
 785 }
 786
 787 static void fimd_update_plane(struct exynos_drm_crtc *crtc,
 788                               struct exynos_drm_plane *plane)
 789 {
 790         struct exynos_drm_plane_state *state =
 791                                 to_exynos_plane_state(plane->base.state);
 792         struct fimd_context *ctx = crtc->ctx;
 793         struct drm_framebuffer *fb = state->base.fb;
 794         dma_addr_t dma_addr;
 795         unsigned long val, size, offset;
 796         unsigned int last_x, last_y, buf_offsize, line_size;
 797         unsigned int win = plane->index;
 798         unsigned int cpp = fb->format->cpp[0];
 799         unsigned int pitch = fb->pitches[0];
 800
 801         if (ctx->suspended)
 802                 return;
 803
 804         offset = state->src.x * cpp;
 805         offset += state->src.y * pitch;
 806
 807         /* buffer start address */
 808         dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
 809         val = (unsigned long)dma_addr;
 810         writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 811
 812         /* buffer end address */
 813         size = pitch * state->crtc.h;
 814         val = (unsigned long)(dma_addr + size);
 815         writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 816
 817         DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
 818                         (unsigned long)dma_addr, val, size);
 819         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 820                         state->crtc.w, state->crtc.h);
 821
 822         /* buffer size */
 823         buf_offsize = pitch - (state->crtc.w * cpp);
 824         line_size = state->crtc.w * cpp;
 825         val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
 826                 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
 827                 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
 828                 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
 829         writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
 830
 831         /* OSD position */
 832         val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
 833                 VIDOSDxA_TOPLEFT_Y(state->crtc.y) |
 834                 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) |
 835                 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y);
 836         writel(val, ctx->regs + VIDOSD_A(win));
 837
 838         last_x = state->crtc.x + state->crtc.w;
 839         if (last_x)
 840                 last_x--;
 841         last_y = state->crtc.y + state->crtc.h;
 842         if (last_y)
 843                 last_y--;
 844
 845         val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
 846                 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
 847
 848         writel(val, ctx->regs + VIDOSD_B(win));
 849
 850         DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
 851                         state->crtc.x, state->crtc.y, last_x, last_y);
 852
 853         /* OSD size */
 854         if (win != 3 && win != 4) {
 855                 u32 offset = VIDOSD_D(win);
 856                 if (win == 0)
 857                         offset = VIDOSD_C(win);
 858                 val = state->crtc.w * state->crtc.h;
 859                 writel(val, ctx->regs + offset);
 860
 861                 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
 862         }
 863
 864         fimd_win_set_pixfmt(ctx, win, fb, state->src.w);
 865
 866         /* hardware window 0 doesn't support color key. */
 867         if (win != 0)
 868                 fimd_win_set_colkey(ctx, win);
 869
 870         fimd_enable_video_output(ctx, win, true);
 871
 872         if (ctx->driver_data->has_shadowcon)
 873                 fimd_enable_shadow_channel_path(ctx, win, true);
 874
 875         if (ctx->i80_if)
 876                 atomic_set(&ctx->win_updated, 1);
 877 }
 878
 879 static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
 880                                struct exynos_drm_plane *plane)
 881 {
 882         struct fimd_context *ctx = crtc->ctx;
 883         unsigned int win = plane->index;
 884
 885         if (ctx->suspended)
 886                 return;
 887
 888         fimd_enable_video_output(ctx, win, false);
 889
 890         if (ctx->driver_data->has_shadowcon)
 891                 fimd_enable_shadow_channel_path(ctx, win, false);
 892 }
 893
 894 static void fimd_enable(struct exynos_drm_crtc *crtc)
 895 {
 896         struct fimd_context *ctx = crtc->ctx;
 897
 898         if (!ctx->suspended)
 899                 return;
 900
 901         ctx->suspended = false;
 902
 903         pm_runtime_get_sync(ctx->dev);
 904
 905         /* if vblank was enabled status, enable it again. */
 906         if (test_and_clear_bit(0, &ctx->irq_flags))
 907                 fimd_enable_vblank(ctx->crtc);
 908
 909         fimd_commit(ctx->crtc);
 910 }
 911
 912 static void fimd_disable(struct exynos_drm_crtc *crtc)
 913 {
 914         struct fimd_context *ctx = crtc->ctx;
 915         int i;
 916
 917         if (ctx->suspended)
 918                 return;
 919
 920         /*
 921          * We need to make sure that all windows are disabled before we
 922          * suspend that connector. Otherwise we might try to scan from
 923          * a destroyed buffer later.
 924          */
 925         for (i = 0; i < WINDOWS_NR; i++)
 926                 fimd_disable_plane(crtc, &ctx->planes[i]);
 927
 928         fimd_enable_vblank(crtc);
 929         fimd_wait_for_vblank(crtc);
 930         fimd_disable_vblank(crtc);
 931
 932         writel(0, ctx->regs + VIDCON0);
 933
 934         pm_runtime_put_sync(ctx->dev);
 935         ctx->suspended = true;
 936 }
 937
 938 static void fimd_trigger(struct device *dev)
 939 {
 940         struct fimd_context *ctx = dev_get_drvdata(dev);
 941         const struct fimd_driver_data *driver_data = ctx->driver_data;
 942         void *timing_base = ctx->regs + driver_data->timing_base;
 943         u32 reg;
 944
 945          /*
 946           * Skips triggering if in triggering state, because multiple triggering
 947           * requests can cause panel reset.
 948           */
 949         if (atomic_read(&ctx->triggering))
 950                 return;
 951
 952         /* Enters triggering mode */
 953         atomic_set(&ctx->triggering, 1);
 954
 955         reg = readl(timing_base + TRIGCON);
 956         reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE);
 957         writel(reg, timing_base + TRIGCON);
 958
 959         /*
 960          * Exits triggering mode if vblank is not enabled yet, because when the
 961          * VIDINTCON0 register is not set, it can not exit from triggering mode.
 962          */
 963         if (!test_bit(0, &ctx->irq_flags))
 964                 atomic_set(&ctx->triggering, 0);
 965 }
 966
 967 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
 968 {
 969         struct fimd_context *ctx = crtc->ctx;
 970         u32 trg_type = ctx->driver_data->trg_type;
 971
 972         /* Checks the crtc is detached already from encoder */
 973         if (!ctx->drm_dev)
 974                 return;
 975
 976         if (trg_type == I80_HW_TRG)
 977                 goto out;
 978
 979         /*
 980          * If there is a page flip request, triggers and handles the page flip
 981          * event so that current fb can be updated into panel GRAM.
 982          */
 983         if (atomic_add_unless(&ctx->win_updated, -1, 0))
 984                 fimd_trigger(ctx->dev);
 985
 986 out:
 987         /* Wakes up vsync event queue */
 988         if (atomic_read(&ctx->wait_vsync_event)) {
 989                 atomic_set(&ctx->wait_vsync_event, 0);
 990                 wake_up(&ctx->wait_vsync_queue);
 991         }
 992
 993         if (test_bit(0, &ctx->irq_flags))
 994                 drm_crtc_handle_vblank(&ctx->crtc->base);
 995 }
 996
 997 static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable)
 998 {
 999         struct fimd_context *ctx = container_of(clk, struct fimd_context,
1000                                                 dp_clk);
1001         u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
1002         writel(val, ctx->regs + DP_MIE_CLKCON);
1003 }
1004
1005 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
1006         .enable = fimd_enable,
1007         .disable = fimd_disable,
1008         .enable_vblank = fimd_enable_vblank,
1009         .disable_vblank = fimd_disable_vblank,
1010         .atomic_begin = fimd_atomic_begin,
1011         .update_plane = fimd_update_plane,
1012         .disable_plane = fimd_disable_plane,
1013         .atomic_flush = fimd_atomic_flush,
1014         .atomic_check = fimd_atomic_check,
1015         .te_handler = fimd_te_handler,
1016 };
1017
1018 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
1019 {
1020         struct fimd_context *ctx = (struct fimd_context *)dev_id;
1021         u32 val, clear_bit;
1022
1023         val = readl(ctx->regs + VIDINTCON1);
1024
1025         clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
1026         if (val & clear_bit)
1027                 writel(clear_bit, ctx->regs + VIDINTCON1);
1028
1029         /* check the crtc is detached already from encoder */
1030         if (!ctx->drm_dev)
1031                 goto out;
1032
1033         if (!ctx->i80_if)
1034                 drm_crtc_handle_vblank(&ctx->crtc->base);
1035
1036         if (ctx->i80_if) {
1037                 /* Exits triggering mode */
1038                 atomic_set(&ctx->triggering, 0);
1039         } else {
1040                 /* set wait vsync event to zero and wake up queue. */
1041                 if (atomic_read(&ctx->wait_vsync_event)) {
1042                         atomic_set(&ctx->wait_vsync_event, 0);
1043                         wake_up(&ctx->wait_vsync_queue);
1044                 }
1045         }
1046
1047 out:
1048         return IRQ_HANDLED;
1049 }
1050
1051 static int fimd_bind(struct device *dev, struct device *master, void *data)
1052 {
1053         struct fimd_context *ctx = dev_get_drvdata(dev);
1054         struct drm_device *drm_dev = data;
1055         struct exynos_drm_plane *exynos_plane;
1056         unsigned int i;
1057         int ret;
1058
1059         ctx->drm_dev = drm_dev;
1060
1061         for (i = 0; i < WINDOWS_NR; i++) {
1062                 ctx->configs[i].pixel_formats = fimd_formats;
1063                 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
1064                 ctx->configs[i].zpos = i;
1065                 ctx->configs[i].type = fimd_win_types[i];
1066                 ctx->configs[i].capabilities = capabilities[i];
1067                 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
1068                                         &ctx->configs[i]);
1069                 if (ret)
1070                         return ret;
1071         }
1072
1073         exynos_plane = &ctx->planes[DEFAULT_WIN];
1074         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
1075                         EXYNOS_DISPLAY_TYPE_LCD, &fimd_crtc_ops, ctx);
1076         if (IS_ERR(ctx->crtc))
1077                 return PTR_ERR(ctx->crtc);
1078
1079         if (ctx->driver_data->has_dp_clk) {
1080                 ctx->dp_clk.enable = fimd_dp_clock_enable;
1081                 ctx->crtc->pipe_clk = &ctx->dp_clk;
1082         }
1083
1084         if (ctx->encoder)
1085                 exynos_dpi_bind(drm_dev, ctx->encoder);
1086
1087         if (is_drm_iommu_supported(drm_dev))
1088                 fimd_clear_channels(ctx->crtc);
1089
1090         return exynos_drm_register_dma(drm_dev, dev);
1091 }
1092
1093 static void fimd_unbind(struct device *dev, struct device *master,
1094                         void *data)
1095 {
1096         struct fimd_context *ctx = dev_get_drvdata(dev);
1097
1098         fimd_disable(ctx->crtc);
1099
1100         exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev);
1101
1102         if (ctx->encoder)
1103                 exynos_dpi_remove(ctx->encoder);
1104 }
1105
1106 static const struct component_ops fimd_component_ops = {
1107         .bind   = fimd_bind,
1108         .unbind = fimd_unbind,
1109 };
1110
1111 static int fimd_probe(struct platform_device *pdev)
1112 {
1113         struct device *dev = &pdev->dev;
1114         struct fimd_context *ctx;
1115         struct device_node *i80_if_timings;
1116         struct resource *res;
1117         int ret;
1118
1119         if (!dev->of_node)
1120                 return -ENODEV;
1121
1122         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1123         if (!ctx)
1124                 return -ENOMEM;
1125
1126         ctx->dev = dev;
1127         ctx->suspended = true;
1128         ctx->driver_data = of_device_get_match_data(dev);
1129
1130         if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1131                 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1132         if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1133                 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1134
1135         i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1136         if (i80_if_timings) {
1137                 u32 val;
1138
1139                 ctx->i80_if = true;
1140
1141                 if (ctx->driver_data->has_vidoutcon)
1142                         ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1143                 else
1144                         ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1145                 /*
1146                  * The user manual describes that this "DSI_EN" bit is required
1147                  * to enable I80 24-bit data interface.
1148                  */
1149                 ctx->vidcon0 |= VIDCON0_DSI_EN;
1150
1151                 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1152                         val = 0;
1153                 ctx->i80ifcon = LCD_CS_SETUP(val);
1154                 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1155                         val = 0;
1156                 ctx->i80ifcon |= LCD_WR_SETUP(val);
1157                 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1158                         val = 1;
1159                 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1160                 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1161                         val = 0;
1162                 ctx->i80ifcon |= LCD_WR_HOLD(val);
1163         }
1164         of_node_put(i80_if_timings);
1165
1166         ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1167                                                         "samsung,sysreg");
1168         if (IS_ERR(ctx->sysreg)) {
1169                 dev_warn(dev, "failed to get system register.\n");
1170                 ctx->sysreg = NULL;
1171         }
1172
1173         ctx->bus_clk = devm_clk_get(dev, "fimd");
1174         if (IS_ERR(ctx->bus_clk)) {
1175                 dev_err(dev, "failed to get bus clock\n");
1176                 return PTR_ERR(ctx->bus_clk);
1177         }
1178
1179         ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1180         if (IS_ERR(ctx->lcd_clk)) {
1181                 dev_err(dev, "failed to get lcd clock\n");
1182                 return PTR_ERR(ctx->lcd_clk);
1183         }
1184
1185         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1186
1187         ctx->regs = devm_ioremap_resource(dev, res);
1188         if (IS_ERR(ctx->regs))
1189                 return PTR_ERR(ctx->regs);
1190
1191         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1192                                            ctx->i80_if ? "lcd_sys" : "vsync");
1193         if (!res) {
1194                 dev_err(dev, "irq request failed.\n");
1195                 return -ENXIO;
1196         }
1197
1198         ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1199                                                         0, "drm_fimd", ctx);
1200         if (ret) {
1201                 dev_err(dev, "irq request failed.\n");
1202                 return ret;
1203         }
1204
1205         init_waitqueue_head(&ctx->wait_vsync_queue);
1206         atomic_set(&ctx->wait_vsync_event, 0);
1207
1208         platform_set_drvdata(pdev, ctx);
1209
1210         ctx->encoder = exynos_dpi_probe(dev);
1211         if (IS_ERR(ctx->encoder))
1212                 return PTR_ERR(ctx->encoder);
1213
1214         pm_runtime_enable(dev);
1215
1216         ret = component_add(dev, &fimd_component_ops);
1217         if (ret)
1218                 goto err_disable_pm_runtime;
1219
1220         return ret;
1221
1222 err_disable_pm_runtime:
1223         pm_runtime_disable(dev);
1224
1225         return ret;
1226 }
1227
1228 static int fimd_remove(struct platform_device *pdev)
1229 {
1230         pm_runtime_disable(&pdev->dev);
1231
1232         component_del(&pdev->dev, &fimd_component_ops);
1233
1234         return 0;
1235 }
1236
1237 #ifdef CONFIG_PM
1238 static int exynos_fimd_suspend(struct device *dev)
1239 {
1240         struct fimd_context *ctx = dev_get_drvdata(dev);
1241
1242         clk_disable_unprepare(ctx->lcd_clk);
1243         clk_disable_unprepare(ctx->bus_clk);
1244
1245         return 0;
1246 }
1247
1248 static int exynos_fimd_resume(struct device *dev)
1249 {
1250         struct fimd_context *ctx = dev_get_drvdata(dev);
1251         int ret;
1252
1253         ret = clk_prepare_enable(ctx->bus_clk);
1254         if (ret < 0) {
1255                 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
1256                 return ret;
1257         }
1258
1259         ret = clk_prepare_enable(ctx->lcd_clk);
1260         if  (ret < 0) {
1261                 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
1262                 return ret;
1263         }
1264
1265         return 0;
1266 }
1267 #endif
1268
1269 static const struct dev_pm_ops exynos_fimd_pm_ops = {
1270         SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL)
1271         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1272                                 pm_runtime_force_resume)
1273 };
1274
1275 struct platform_driver fimd_driver = {
1276         .probe          = fimd_probe,
1277         .remove         = fimd_remove,
1278         .driver         = {
1279                 .name   = "exynos4-fb",
1280                 .owner  = THIS_MODULE,
1281                 .pm     = &exynos_fimd_pm_ops,
1282                 .of_match_table = fimd_driver_dt_match,
1283         },
1284 };