drivers/gpu/drm/exynos/exynos_drm_fimd.c

   1 /* exynos_drm_fimd.c
   2  *
   3  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Inki Dae <inki.dae@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include <drm/drmP.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/component.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/regmap.h>
  25
  26 #include <video/of_display_timing.h>
  27 #include <video/of_videomode.h>
  28 #include <video/samsung_fimd.h>
  29 #include <drm/exynos_drm.h>
  30
  31 #include "exynos_drm_drv.h"
  32 #include "exynos_drm_fb.h"
  33 #include "exynos_drm_crtc.h"
  34 #include "exynos_drm_plane.h"
  35
  36 /*
  37  * FIMD stands for Fully Interactive Mobile Display and
  38  * as a display controller, it transfers contents drawn on memory
  39  * to a LCD Panel through Display Interfaces such as RGB or
  40  * CPU Interface.
  41  */
  42
  43 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
  44
  45 /* position control register for hardware window 0, 2 ~ 4.*/
  46 #define VIDOSD_A(win)           (VIDOSD_BASE + 0x00 + (win) * 16)
  47 #define VIDOSD_B(win)           (VIDOSD_BASE + 0x04 + (win) * 16)
  48 /*
  49  * size control register for hardware windows 0 and alpha control register
  50  * for hardware windows 1 ~ 4
  51  */
  52 #define VIDOSD_C(win)           (VIDOSD_BASE + 0x08 + (win) * 16)
  53 /* size control register for hardware windows 1 ~ 2. */
  54 #define VIDOSD_D(win)           (VIDOSD_BASE + 0x0C + (win) * 16)
  55
  56 #define VIDWnALPHA0(win)        (VIDW_ALPHA + 0x00 + (win) * 8)
  57 #define VIDWnALPHA1(win)        (VIDW_ALPHA + 0x04 + (win) * 8)
  58
  59 #define VIDWx_BUF_START(win, buf)       (VIDW_BUF_START(buf) + (win) * 8)
  60 #define VIDWx_BUF_START_S(win, buf)     (VIDW_BUF_START_S(buf) + (win) * 8)
  61 #define VIDWx_BUF_END(win, buf)         (VIDW_BUF_END(buf) + (win) * 8)
  62 #define VIDWx_BUF_SIZE(win, buf)        (VIDW_BUF_SIZE(buf) + (win) * 4)
  63
  64 /* color key control register for hardware window 1 ~ 4. */
  65 #define WKEYCON0_BASE(x)                ((WKEYCON0 + 0x140) + ((x - 1) * 8))
  66 /* color key value register for hardware window 1 ~ 4. */
  67 #define WKEYCON1_BASE(x)                ((WKEYCON1 + 0x140) + ((x - 1) * 8))
  68
  69 /* I80 trigger control register */
  70 #define TRIGCON                         0x1A4
  71 #define TRGMODE_ENABLE                  (1 << 0)
  72 #define SWTRGCMD_ENABLE                 (1 << 1)
  73 /* Exynos3250, 3472, 5260 5410, 5420 and 5422 only supported. */
  74 #define HWTRGEN_ENABLE                  (1 << 3)
  75 #define HWTRGMASK_ENABLE                (1 << 4)
  76 /* Exynos3250, 3472, 5260, 5420 and 5422 only supported. */
  77 #define HWTRIGEN_PER_ENABLE             (1 << 31)
  78
  79 /* display mode change control register except exynos4 */
  80 #define VIDOUT_CON                      0x000
  81 #define VIDOUT_CON_F_I80_LDI0           (0x2 << 8)
  82
  83 /* I80 interface control for main LDI register */
  84 #define I80IFCONFAx(x)                  (0x1B0 + (x) * 4)
  85 #define I80IFCONFBx(x)                  (0x1B8 + (x) * 4)
  86 #define LCD_CS_SETUP(x)                 ((x) << 16)
  87 #define LCD_WR_SETUP(x)                 ((x) << 12)
  88 #define LCD_WR_ACTIVE(x)                ((x) << 8)
  89 #define LCD_WR_HOLD(x)                  ((x) << 4)
  90 #define I80IFEN_ENABLE                  (1 << 0)
  91
  92 /* FIMD has totally five hardware windows. */
  93 #define WINDOWS_NR      5
  94
  95 /* HW trigger flag on i80 panel. */
  96 #define I80_HW_TRG     (1 << 1)
  97
  98 struct fimd_driver_data {
  99         unsigned int timing_base;
 100         unsigned int lcdblk_offset;
 101         unsigned int lcdblk_vt_shift;
 102         unsigned int lcdblk_bypass_shift;
 103         unsigned int lcdblk_mic_bypass_shift;
 104         unsigned int trg_type;
 105
 106         unsigned int has_shadowcon:1;
 107         unsigned int has_clksel:1;
 108         unsigned int has_limited_fmt:1;
 109         unsigned int has_vidoutcon:1;
 110         unsigned int has_vtsel:1;
 111         unsigned int has_mic_bypass:1;
 112         unsigned int has_dp_clk:1;
 113         unsigned int has_hw_trigger:1;
 114         unsigned int has_trigger_per_te:1;
 115 };
 116
 117 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
 118         .timing_base = 0x0,
 119         .has_clksel = 1,
 120         .has_limited_fmt = 1,
 121 };
 122
 123 static struct fimd_driver_data s5pv210_fimd_driver_data = {
 124         .timing_base = 0x0,
 125         .has_shadowcon = 1,
 126         .has_clksel = 1,
 127 };
 128
 129 static struct fimd_driver_data exynos3_fimd_driver_data = {
 130         .timing_base = 0x20000,
 131         .lcdblk_offset = 0x210,
 132         .lcdblk_bypass_shift = 1,
 133         .has_shadowcon = 1,
 134         .has_vidoutcon = 1,
 135 };
 136
 137 static struct fimd_driver_data exynos4_fimd_driver_data = {
 138         .timing_base = 0x0,
 139         .lcdblk_offset = 0x210,
 140         .lcdblk_vt_shift = 10,
 141         .lcdblk_bypass_shift = 1,
 142         .has_shadowcon = 1,
 143         .has_vtsel = 1,
 144 };
 145
 146 static struct fimd_driver_data exynos5_fimd_driver_data = {
 147         .timing_base = 0x20000,
 148         .lcdblk_offset = 0x214,
 149         .lcdblk_vt_shift = 24,
 150         .lcdblk_bypass_shift = 15,
 151         .has_shadowcon = 1,
 152         .has_vidoutcon = 1,
 153         .has_vtsel = 1,
 154         .has_dp_clk = 1,
 155 };
 156
 157 static struct fimd_driver_data exynos5420_fimd_driver_data = {
 158         .timing_base = 0x20000,
 159         .lcdblk_offset = 0x214,
 160         .lcdblk_vt_shift = 24,
 161         .lcdblk_bypass_shift = 15,
 162         .lcdblk_mic_bypass_shift = 11,
 163         .has_shadowcon = 1,
 164         .has_vidoutcon = 1,
 165         .has_vtsel = 1,
 166         .has_mic_bypass = 1,
 167         .has_dp_clk = 1,
 168 };
 169
 170 struct fimd_context {
 171         struct device                   *dev;
 172         struct drm_device               *drm_dev;
 173         struct exynos_drm_crtc          *crtc;
 174         struct exynos_drm_plane         planes[WINDOWS_NR];
 175         struct exynos_drm_plane_config  configs[WINDOWS_NR];
 176         struct clk                      *bus_clk;
 177         struct clk                      *lcd_clk;
 178         void __iomem                    *regs;
 179         struct regmap                   *sysreg;
 180         unsigned long                   irq_flags;
 181         u32                             vidcon0;
 182         u32                             vidcon1;
 183         u32                             vidout_con;
 184         u32                             i80ifcon;
 185         bool                            i80_if;
 186         bool                            suspended;
 187         wait_queue_head_t               wait_vsync_queue;
 188         atomic_t                        wait_vsync_event;
 189         atomic_t                        win_updated;
 190         atomic_t                        triggering;
 191         u32                             clkdiv;
 192
 193         const struct fimd_driver_data *driver_data;
 194         struct drm_encoder *encoder;
 195         struct exynos_drm_clk           dp_clk;
 196 };
 197
 198 static const struct of_device_id fimd_driver_dt_match[] = {
 199         { .compatible = "samsung,s3c6400-fimd",
 200           .data = &s3c64xx_fimd_driver_data },
 201         { .compatible = "samsung,s5pv210-fimd",
 202           .data = &s5pv210_fimd_driver_data },
 203         { .compatible = "samsung,exynos3250-fimd",
 204           .data = &exynos3_fimd_driver_data },
 205         { .compatible = "samsung,exynos4210-fimd",
 206           .data = &exynos4_fimd_driver_data },
 207         { .compatible = "samsung,exynos5250-fimd",
 208           .data = &exynos5_fimd_driver_data },
 209         { .compatible = "samsung,exynos5420-fimd",
 210           .data = &exynos5420_fimd_driver_data },
 211         {},
 212 };
 213 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
 214
 215 static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = {
 216         DRM_PLANE_TYPE_PRIMARY,
 217         DRM_PLANE_TYPE_OVERLAY,
 218         DRM_PLANE_TYPE_OVERLAY,
 219         DRM_PLANE_TYPE_OVERLAY,
 220         DRM_PLANE_TYPE_CURSOR,
 221 };
 222
 223 static const uint32_t fimd_formats[] = {
 224         DRM_FORMAT_C8,
 225         DRM_FORMAT_XRGB1555,
 226         DRM_FORMAT_RGB565,
 227         DRM_FORMAT_XRGB8888,
 228         DRM_FORMAT_ARGB8888,
 229 };
 230
 231 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
 232 {
 233         struct fimd_context *ctx = crtc->ctx;
 234         u32 val;
 235
 236         if (ctx->suspended)
 237                 return -EPERM;
 238
 239         if (!test_and_set_bit(0, &ctx->irq_flags)) {
 240                 val = readl(ctx->regs + VIDINTCON0);
 241
 242                 val |= VIDINTCON0_INT_ENABLE;
 243
 244                 if (ctx->i80_if) {
 245                         val |= VIDINTCON0_INT_I80IFDONE;
 246                         val |= VIDINTCON0_INT_SYSMAINCON;
 247                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 248                 } else {
 249                         val |= VIDINTCON0_INT_FRAME;
 250
 251                         val &= ~VIDINTCON0_FRAMESEL0_MASK;
 252                         val |= VIDINTCON0_FRAMESEL0_FRONTPORCH;
 253                         val &= ~VIDINTCON0_FRAMESEL1_MASK;
 254                         val |= VIDINTCON0_FRAMESEL1_NONE;
 255                 }
 256
 257                 writel(val, ctx->regs + VIDINTCON0);
 258         }
 259
 260         return 0;
 261 }
 262
 263 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
 264 {
 265         struct fimd_context *ctx = crtc->ctx;
 266         u32 val;
 267
 268         if (ctx->suspended)
 269                 return;
 270
 271         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 272                 val = readl(ctx->regs + VIDINTCON0);
 273
 274                 val &= ~VIDINTCON0_INT_ENABLE;
 275
 276                 if (ctx->i80_if) {
 277                         val &= ~VIDINTCON0_INT_I80IFDONE;
 278                         val &= ~VIDINTCON0_INT_SYSMAINCON;
 279                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 280                 } else
 281                         val &= ~VIDINTCON0_INT_FRAME;
 282
 283                 writel(val, ctx->regs + VIDINTCON0);
 284         }
 285 }
 286
 287 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
 288 {
 289         struct fimd_context *ctx = crtc->ctx;
 290
 291         if (ctx->suspended)
 292                 return;
 293
 294         atomic_set(&ctx->wait_vsync_event, 1);
 295
 296         /*
 297          * wait for FIMD to signal VSYNC interrupt or return after
 298          * timeout which is set to 50ms (refresh rate of 20).
 299          */
 300         if (!wait_event_timeout(ctx->wait_vsync_queue,
 301                                 !atomic_read(&ctx->wait_vsync_event),
 302                                 HZ/20))
 303                 DRM_DEBUG_KMS("vblank wait timed out.\n");
 304 }
 305
 306 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
 307                                         bool enable)
 308 {
 309         u32 val = readl(ctx->regs + WINCON(win));
 310
 311         if (enable)
 312                 val |= WINCONx_ENWIN;
 313         else
 314                 val &= ~WINCONx_ENWIN;
 315
 316         writel(val, ctx->regs + WINCON(win));
 317 }
 318
 319 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
 320                                                 unsigned int win,
 321                                                 bool enable)
 322 {
 323         u32 val = readl(ctx->regs + SHADOWCON);
 324
 325         if (enable)
 326                 val |= SHADOWCON_CHx_ENABLE(win);
 327         else
 328                 val &= ~SHADOWCON_CHx_ENABLE(win);
 329
 330         writel(val, ctx->regs + SHADOWCON);
 331 }
 332
 333 static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
 334 {
 335         struct fimd_context *ctx = crtc->ctx;
 336         unsigned int win, ch_enabled = 0;
 337
 338         DRM_DEBUG_KMS("%s\n", __FILE__);
 339
 340         /* Hardware is in unknown state, so ensure it gets enabled properly */
 341         pm_runtime_get_sync(ctx->dev);
 342
 343         clk_prepare_enable(ctx->bus_clk);
 344         clk_prepare_enable(ctx->lcd_clk);
 345
 346         /* Check if any channel is enabled. */
 347         for (win = 0; win < WINDOWS_NR; win++) {
 348                 u32 val = readl(ctx->regs + WINCON(win));
 349
 350                 if (val & WINCONx_ENWIN) {
 351                         fimd_enable_video_output(ctx, win, false);
 352
 353                         if (ctx->driver_data->has_shadowcon)
 354                                 fimd_enable_shadow_channel_path(ctx, win,
 355                                                                 false);
 356
 357                         ch_enabled = 1;
 358                 }
 359         }
 360
 361         /* Wait for vsync, as disable channel takes effect at next vsync */
 362         if (ch_enabled) {
 363                 ctx->suspended = false;
 364
 365                 fimd_enable_vblank(ctx->crtc);
 366                 fimd_wait_for_vblank(ctx->crtc);
 367                 fimd_disable_vblank(ctx->crtc);
 368
 369                 ctx->suspended = true;
 370         }
 371
 372         clk_disable_unprepare(ctx->lcd_clk);
 373         clk_disable_unprepare(ctx->bus_clk);
 374
 375         pm_runtime_put(ctx->dev);
 376 }
 377
 378
 379 static int fimd_atomic_check(struct exynos_drm_crtc *crtc,
 380                 struct drm_crtc_state *state)
 381 {
 382         struct drm_display_mode *mode = &state->adjusted_mode;
 383         struct fimd_context *ctx = crtc->ctx;
 384         unsigned long ideal_clk, lcd_rate;
 385         u32 clkdiv;
 386
 387         if (mode->clock == 0) {
 388                 DRM_INFO("Mode has zero clock value.\n");
 389                 return -EINVAL;
 390         }
 391
 392         ideal_clk = mode->clock * 1000;
 393
 394         if (ctx->i80_if) {
 395                 /*
 396                  * The frame done interrupt should be occurred prior to the
 397                  * next TE signal.
 398                  */
 399                 ideal_clk *= 2;
 400         }
 401
 402         lcd_rate = clk_get_rate(ctx->lcd_clk);
 403         if (2 * lcd_rate < ideal_clk) {
 404                 DRM_INFO("sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n",
 405                          lcd_rate, ideal_clk);
 406                 return -EINVAL;
 407         }
 408
 409         /* Find the clock divider value that gets us closest to ideal_clk */
 410         clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk);
 411         if (clkdiv >= 0x200) {
 412                 DRM_INFO("requested pixel clock(%lu) too low\n", ideal_clk);
 413                 return -EINVAL;
 414         }
 415
 416         ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff;
 417
 418         return 0;
 419 }
 420
 421 static void fimd_setup_trigger(struct fimd_context *ctx)
 422 {
 423         void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base;
 424         u32 trg_type = ctx->driver_data->trg_type;
 425         u32 val = readl(timing_base + TRIGCON);
 426
 427         val &= ~(TRGMODE_ENABLE);
 428
 429         if (trg_type == I80_HW_TRG) {
 430                 if (ctx->driver_data->has_hw_trigger)
 431                         val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE;
 432                 if (ctx->driver_data->has_trigger_per_te)
 433                         val |= HWTRIGEN_PER_ENABLE;
 434         } else {
 435                 val |= TRGMODE_ENABLE;
 436         }
 437
 438         writel(val, timing_base + TRIGCON);
 439 }
 440
 441 static void fimd_commit(struct exynos_drm_crtc *crtc)
 442 {
 443         struct fimd_context *ctx = crtc->ctx;
 444         struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
 445         const struct fimd_driver_data *driver_data = ctx->driver_data;
 446         void *timing_base = ctx->regs + driver_data->timing_base;
 447         u32 val;
 448
 449         if (ctx->suspended)
 450                 return;
 451
 452         /* nothing to do if we haven't set the mode yet */
 453         if (mode->htotal == 0 || mode->vtotal == 0)
 454                 return;
 455
 456         if (ctx->i80_if) {
 457                 val = ctx->i80ifcon | I80IFEN_ENABLE;
 458                 writel(val, timing_base + I80IFCONFAx(0));
 459
 460                 /* disable auto frame rate */
 461                 writel(0, timing_base + I80IFCONFBx(0));
 462
 463                 /* set video type selection to I80 interface */
 464                 if (driver_data->has_vtsel && ctx->sysreg &&
 465                                 regmap_update_bits(ctx->sysreg,
 466                                         driver_data->lcdblk_offset,
 467                                         0x3 << driver_data->lcdblk_vt_shift,
 468                                         0x1 << driver_data->lcdblk_vt_shift)) {
 469                         DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
 470                         return;
 471                 }
 472         } else {
 473                 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
 474                 u32 vidcon1;
 475
 476                 /* setup polarity values */
 477                 vidcon1 = ctx->vidcon1;
 478                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 479                         vidcon1 |= VIDCON1_INV_VSYNC;
 480                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 481                         vidcon1 |= VIDCON1_INV_HSYNC;
 482                 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
 483
 484                 /* setup vertical timing values. */
 485                 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
 486                 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
 487                 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
 488
 489                 val = VIDTCON0_VBPD(vbpd - 1) |
 490                         VIDTCON0_VFPD(vfpd - 1) |
 491                         VIDTCON0_VSPW(vsync_len - 1);
 492                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
 493
 494                 /* setup horizontal timing values.  */
 495                 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
 496                 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
 497                 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
 498
 499                 val = VIDTCON1_HBPD(hbpd - 1) |
 500                         VIDTCON1_HFPD(hfpd - 1) |
 501                         VIDTCON1_HSPW(hsync_len - 1);
 502                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
 503         }
 504
 505         if (driver_data->has_vidoutcon)
 506                 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
 507
 508         /* set bypass selection */
 509         if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
 510                                 driver_data->lcdblk_offset,
 511                                 0x1 << driver_data->lcdblk_bypass_shift,
 512                                 0x1 << driver_data->lcdblk_bypass_shift)) {
 513                 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
 514                 return;
 515         }
 516
 517         /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass
 518          * bit should be cleared.
 519          */
 520         if (driver_data->has_mic_bypass && ctx->sysreg &&
 521             regmap_update_bits(ctx->sysreg,
 522                                 driver_data->lcdblk_offset,
 523                                 0x1 << driver_data->lcdblk_mic_bypass_shift,
 524                                 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
 525                 DRM_ERROR("Failed to update sysreg for bypass mic.\n");
 526                 return;
 527         }
 528
 529         /* setup horizontal and vertical display size. */
 530         val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
 531                VIDTCON2_HOZVAL(mode->hdisplay - 1) |
 532                VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
 533                VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
 534         writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
 535
 536         fimd_setup_trigger(ctx);
 537
 538         /*
 539          * fields of register with prefix '_F' would be updated
 540          * at vsync(same as dma start)
 541          */
 542         val = ctx->vidcon0;
 543         val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 544
 545         if (ctx->driver_data->has_clksel)
 546                 val |= VIDCON0_CLKSEL_LCD;
 547
 548         if (ctx->clkdiv > 1)
 549                 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
 550
 551         writel(val, ctx->regs + VIDCON0);
 552 }
 553
 554
 555 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
 556                                 uint32_t pixel_format, int width)
 557 {
 558         unsigned long val;
 559
 560         val = WINCONx_ENWIN;
 561
 562         /*
 563          * In case of s3c64xx, window 0 doesn't support alpha channel.
 564          * So the request format is ARGB8888 then change it to XRGB8888.
 565          */
 566         if (ctx->driver_data->has_limited_fmt && !win) {
 567                 if (pixel_format == DRM_FORMAT_ARGB8888)
 568                         pixel_format = DRM_FORMAT_XRGB8888;
 569         }
 570
 571         switch (pixel_format) {
 572         case DRM_FORMAT_C8:
 573                 val |= WINCON0_BPPMODE_8BPP_PALETTE;
 574                 val |= WINCONx_BURSTLEN_8WORD;
 575                 val |= WINCONx_BYTSWP;
 576                 break;
 577         case DRM_FORMAT_XRGB1555:
 578                 val |= WINCON0_BPPMODE_16BPP_1555;
 579                 val |= WINCONx_HAWSWP;
 580                 val |= WINCONx_BURSTLEN_16WORD;
 581                 break;
 582         case DRM_FORMAT_RGB565:
 583                 val |= WINCON0_BPPMODE_16BPP_565;
 584                 val |= WINCONx_HAWSWP;
 585                 val |= WINCONx_BURSTLEN_16WORD;
 586                 break;
 587         case DRM_FORMAT_XRGB8888:
 588                 val |= WINCON0_BPPMODE_24BPP_888;
 589                 val |= WINCONx_WSWP;
 590                 val |= WINCONx_BURSTLEN_16WORD;
 591                 break;
 592         case DRM_FORMAT_ARGB8888:
 593         default:
 594                 val |= WINCON1_BPPMODE_25BPP_A1888
 595                         | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
 596                 val |= WINCONx_WSWP;
 597                 val |= WINCONx_BURSTLEN_16WORD;
 598                 break;
 599         }
 600
 601         /*
 602          * Setting dma-burst to 16Word causes permanent tearing for very small
 603          * buffers, e.g. cursor buffer. Burst Mode switching which based on
 604          * plane size is not recommended as plane size varies alot towards the
 605          * end of the screen and rapid movement causes unstable DMA, but it is
 606          * still better to change dma-burst than displaying garbage.
 607          */
 608
 609         if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 610                 val &= ~WINCONx_BURSTLEN_MASK;
 611                 val |= WINCONx_BURSTLEN_4WORD;
 612         }
 613
 614         writel(val, ctx->regs + WINCON(win));
 615
 616         /* hardware window 0 doesn't support alpha channel. */
 617         if (win != 0) {
 618                 /* OSD alpha */
 619                 val = VIDISD14C_ALPHA0_R(0xf) |
 620                         VIDISD14C_ALPHA0_G(0xf) |
 621                         VIDISD14C_ALPHA0_B(0xf) |
 622                         VIDISD14C_ALPHA1_R(0xf) |
 623                         VIDISD14C_ALPHA1_G(0xf) |
 624                         VIDISD14C_ALPHA1_B(0xf);
 625
 626                 writel(val, ctx->regs + VIDOSD_C(win));
 627
 628                 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
 629                         VIDW_ALPHA_G(0xf);
 630                 writel(val, ctx->regs + VIDWnALPHA0(win));
 631                 writel(val, ctx->regs + VIDWnALPHA1(win));
 632         }
 633 }
 634
 635 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
 636 {
 637         unsigned int keycon0 = 0, keycon1 = 0;
 638
 639         keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
 640                         WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 641
 642         keycon1 = WxKEYCON1_COLVAL(0xffffffff);
 643
 644         writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
 645         writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
 646 }
 647
 648 /**
 649  * shadow_protect_win() - disable updating values from shadow registers at vsync
 650  *
 651  * @win: window to protect registers for
 652  * @protect: 1 to protect (disable updates)
 653  */
 654 static void fimd_shadow_protect_win(struct fimd_context *ctx,
 655                                     unsigned int win, bool protect)
 656 {
 657         u32 reg, bits, val;
 658
 659         /*
 660          * SHADOWCON/PRTCON register is used for enabling timing.
 661          *
 662          * for example, once only width value of a register is set,
 663          * if the dma is started then fimd hardware could malfunction so
 664          * with protect window setting, the register fields with prefix '_F'
 665          * wouldn't be updated at vsync also but updated once unprotect window
 666          * is set.
 667          */
 668
 669         if (ctx->driver_data->has_shadowcon) {
 670                 reg = SHADOWCON;
 671                 bits = SHADOWCON_WINx_PROTECT(win);
 672         } else {
 673                 reg = PRTCON;
 674                 bits = PRTCON_PROTECT;
 675         }
 676
 677         val = readl(ctx->regs + reg);
 678         if (protect)
 679                 val |= bits;
 680         else
 681                 val &= ~bits;
 682         writel(val, ctx->regs + reg);
 683 }
 684
 685 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc)
 686 {
 687         struct fimd_context *ctx = crtc->ctx;
 688         int i;
 689
 690         if (ctx->suspended)
 691                 return;
 692
 693         for (i = 0; i < WINDOWS_NR; i++)
 694                 fimd_shadow_protect_win(ctx, i, true);
 695 }
 696
 697 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc)
 698 {
 699         struct fimd_context *ctx = crtc->ctx;
 700         int i;
 701
 702         if (ctx->suspended)
 703                 return;
 704
 705         for (i = 0; i < WINDOWS_NR; i++)
 706                 fimd_shadow_protect_win(ctx, i, false);
 707
 708         exynos_crtc_handle_event(crtc);
 709 }
 710
 711 static void fimd_update_plane(struct exynos_drm_crtc *crtc,
 712                               struct exynos_drm_plane *plane)
 713 {
 714         struct exynos_drm_plane_state *state =
 715                                 to_exynos_plane_state(plane->base.state);
 716         struct fimd_context *ctx = crtc->ctx;
 717         struct drm_framebuffer *fb = state->base.fb;
 718         dma_addr_t dma_addr;
 719         unsigned long val, size, offset;
 720         unsigned int last_x, last_y, buf_offsize, line_size;
 721         unsigned int win = plane->index;
 722         unsigned int cpp = fb->format->cpp[0];
 723         unsigned int pitch = fb->pitches[0];
 724
 725         if (ctx->suspended)
 726                 return;
 727
 728         offset = state->src.x * cpp;
 729         offset += state->src.y * pitch;
 730
 731         /* buffer start address */
 732         dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
 733         val = (unsigned long)dma_addr;
 734         writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 735
 736         /* buffer end address */
 737         size = pitch * state->crtc.h;
 738         val = (unsigned long)(dma_addr + size);
 739         writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 740
 741         DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
 742                         (unsigned long)dma_addr, val, size);
 743         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 744                         state->crtc.w, state->crtc.h);
 745
 746         /* buffer size */
 747         buf_offsize = pitch - (state->crtc.w * cpp);
 748         line_size = state->crtc.w * cpp;
 749         val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
 750                 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
 751                 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
 752                 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
 753         writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
 754
 755         /* OSD position */
 756         val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
 757                 VIDOSDxA_TOPLEFT_Y(state->crtc.y) |
 758                 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) |
 759                 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y);
 760         writel(val, ctx->regs + VIDOSD_A(win));
 761
 762         last_x = state->crtc.x + state->crtc.w;
 763         if (last_x)
 764                 last_x--;
 765         last_y = state->crtc.y + state->crtc.h;
 766         if (last_y)
 767                 last_y--;
 768
 769         val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
 770                 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
 771
 772         writel(val, ctx->regs + VIDOSD_B(win));
 773
 774         DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
 775                         state->crtc.x, state->crtc.y, last_x, last_y);
 776
 777         /* OSD size */
 778         if (win != 3 && win != 4) {
 779                 u32 offset = VIDOSD_D(win);
 780                 if (win == 0)
 781                         offset = VIDOSD_C(win);
 782                 val = state->crtc.w * state->crtc.h;
 783                 writel(val, ctx->regs + offset);
 784
 785                 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
 786         }
 787
 788         fimd_win_set_pixfmt(ctx, win, fb->format->format, state->src.w);
 789
 790         /* hardware window 0 doesn't support color key. */
 791         if (win != 0)
 792                 fimd_win_set_colkey(ctx, win);
 793
 794         fimd_enable_video_output(ctx, win, true);
 795
 796         if (ctx->driver_data->has_shadowcon)
 797                 fimd_enable_shadow_channel_path(ctx, win, true);
 798
 799         if (ctx->i80_if)
 800                 atomic_set(&ctx->win_updated, 1);
 801 }
 802
 803 static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
 804                                struct exynos_drm_plane *plane)
 805 {
 806         struct fimd_context *ctx = crtc->ctx;
 807         unsigned int win = plane->index;
 808
 809         if (ctx->suspended)
 810                 return;
 811
 812         fimd_enable_video_output(ctx, win, false);
 813
 814         if (ctx->driver_data->has_shadowcon)
 815                 fimd_enable_shadow_channel_path(ctx, win, false);
 816 }
 817
 818 static void fimd_enable(struct exynos_drm_crtc *crtc)
 819 {
 820         struct fimd_context *ctx = crtc->ctx;
 821
 822         if (!ctx->suspended)
 823                 return;
 824
 825         ctx->suspended = false;
 826
 827         pm_runtime_get_sync(ctx->dev);
 828
 829         /* if vblank was enabled status, enable it again. */
 830         if (test_and_clear_bit(0, &ctx->irq_flags))
 831                 fimd_enable_vblank(ctx->crtc);
 832
 833         fimd_commit(ctx->crtc);
 834 }
 835
 836 static void fimd_disable(struct exynos_drm_crtc *crtc)
 837 {
 838         struct fimd_context *ctx = crtc->ctx;
 839         int i;
 840
 841         if (ctx->suspended)
 842                 return;
 843
 844         /*
 845          * We need to make sure that all windows are disabled before we
 846          * suspend that connector. Otherwise we might try to scan from
 847          * a destroyed buffer later.
 848          */
 849         for (i = 0; i < WINDOWS_NR; i++)
 850                 fimd_disable_plane(crtc, &ctx->planes[i]);
 851
 852         fimd_enable_vblank(crtc);
 853         fimd_wait_for_vblank(crtc);
 854         fimd_disable_vblank(crtc);
 855
 856         writel(0, ctx->regs + VIDCON0);
 857
 858         pm_runtime_put_sync(ctx->dev);
 859         ctx->suspended = true;
 860 }
 861
 862 static void fimd_trigger(struct device *dev)
 863 {
 864         struct fimd_context *ctx = dev_get_drvdata(dev);
 865         const struct fimd_driver_data *driver_data = ctx->driver_data;
 866         void *timing_base = ctx->regs + driver_data->timing_base;
 867         u32 reg;
 868
 869          /*
 870           * Skips triggering if in triggering state, because multiple triggering
 871           * requests can cause panel reset.
 872           */
 873         if (atomic_read(&ctx->triggering))
 874                 return;
 875
 876         /* Enters triggering mode */
 877         atomic_set(&ctx->triggering, 1);
 878
 879         reg = readl(timing_base + TRIGCON);
 880         reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE);
 881         writel(reg, timing_base + TRIGCON);
 882
 883         /*
 884          * Exits triggering mode if vblank is not enabled yet, because when the
 885          * VIDINTCON0 register is not set, it can not exit from triggering mode.
 886          */
 887         if (!test_bit(0, &ctx->irq_flags))
 888                 atomic_set(&ctx->triggering, 0);
 889 }
 890
 891 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
 892 {
 893         struct fimd_context *ctx = crtc->ctx;
 894         u32 trg_type = ctx->driver_data->trg_type;
 895
 896         /* Checks the crtc is detached already from encoder */
 897         if (!ctx->drm_dev)
 898                 return;
 899
 900         if (trg_type == I80_HW_TRG)
 901                 goto out;
 902
 903         /*
 904          * If there is a page flip request, triggers and handles the page flip
 905          * event so that current fb can be updated into panel GRAM.
 906          */
 907         if (atomic_add_unless(&ctx->win_updated, -1, 0))
 908                 fimd_trigger(ctx->dev);
 909
 910 out:
 911         /* Wakes up vsync event queue */
 912         if (atomic_read(&ctx->wait_vsync_event)) {
 913                 atomic_set(&ctx->wait_vsync_event, 0);
 914                 wake_up(&ctx->wait_vsync_queue);
 915         }
 916
 917         if (test_bit(0, &ctx->irq_flags))
 918                 drm_crtc_handle_vblank(&ctx->crtc->base);
 919 }
 920
 921 static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable)
 922 {
 923         struct fimd_context *ctx = container_of(clk, struct fimd_context,
 924                                                 dp_clk);
 925         u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
 926         writel(val, ctx->regs + DP_MIE_CLKCON);
 927 }
 928
 929 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
 930         .enable = fimd_enable,
 931         .disable = fimd_disable,
 932         .enable_vblank = fimd_enable_vblank,
 933         .disable_vblank = fimd_disable_vblank,
 934         .atomic_begin = fimd_atomic_begin,
 935         .update_plane = fimd_update_plane,
 936         .disable_plane = fimd_disable_plane,
 937         .atomic_flush = fimd_atomic_flush,
 938         .atomic_check = fimd_atomic_check,
 939         .te_handler = fimd_te_handler,
 940 };
 941
 942 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
 943 {
 944         struct fimd_context *ctx = (struct fimd_context *)dev_id;
 945         u32 val, clear_bit;
 946
 947         val = readl(ctx->regs + VIDINTCON1);
 948
 949         clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
 950         if (val & clear_bit)
 951                 writel(clear_bit, ctx->regs + VIDINTCON1);
 952
 953         /* check the crtc is detached already from encoder */
 954         if (!ctx->drm_dev)
 955                 goto out;
 956
 957         if (!ctx->i80_if)
 958                 drm_crtc_handle_vblank(&ctx->crtc->base);
 959
 960         if (ctx->i80_if) {
 961                 /* Exits triggering mode */
 962                 atomic_set(&ctx->triggering, 0);
 963         } else {
 964                 /* set wait vsync event to zero and wake up queue. */
 965                 if (atomic_read(&ctx->wait_vsync_event)) {
 966                         atomic_set(&ctx->wait_vsync_event, 0);
 967                         wake_up(&ctx->wait_vsync_queue);
 968                 }
 969         }
 970
 971 out:
 972         return IRQ_HANDLED;
 973 }
 974
 975 static int fimd_bind(struct device *dev, struct device *master, void *data)
 976 {
 977         struct fimd_context *ctx = dev_get_drvdata(dev);
 978         struct drm_device *drm_dev = data;
 979         struct exynos_drm_plane *exynos_plane;
 980         unsigned int i;
 981         int ret;
 982
 983         ctx->drm_dev = drm_dev;
 984
 985         for (i = 0; i < WINDOWS_NR; i++) {
 986                 ctx->configs[i].pixel_formats = fimd_formats;
 987                 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
 988                 ctx->configs[i].zpos = i;
 989                 ctx->configs[i].type = fimd_win_types[i];
 990                 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
 991                                         &ctx->configs[i]);
 992                 if (ret)
 993                         return ret;
 994         }
 995
 996         exynos_plane = &ctx->planes[DEFAULT_WIN];
 997         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 998                         EXYNOS_DISPLAY_TYPE_LCD, &fimd_crtc_ops, ctx);
 999         if (IS_ERR(ctx->crtc))
1000                 return PTR_ERR(ctx->crtc);
1001
1002         if (ctx->driver_data->has_dp_clk) {
1003                 ctx->dp_clk.enable = fimd_dp_clock_enable;
1004                 ctx->crtc->pipe_clk = &ctx->dp_clk;
1005         }
1006
1007         if (ctx->encoder)
1008                 exynos_dpi_bind(drm_dev, ctx->encoder);
1009
1010         if (is_drm_iommu_supported(drm_dev))
1011                 fimd_clear_channels(ctx->crtc);
1012
1013         return exynos_drm_register_dma(drm_dev, dev);
1014 }
1015
1016 static void fimd_unbind(struct device *dev, struct device *master,
1017                         void *data)
1018 {
1019         struct fimd_context *ctx = dev_get_drvdata(dev);
1020
1021         fimd_disable(ctx->crtc);
1022
1023         exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev);
1024
1025         if (ctx->encoder)
1026                 exynos_dpi_remove(ctx->encoder);
1027 }
1028
1029 static const struct component_ops fimd_component_ops = {
1030         .bind   = fimd_bind,
1031         .unbind = fimd_unbind,
1032 };
1033
1034 static int fimd_probe(struct platform_device *pdev)
1035 {
1036         struct device *dev = &pdev->dev;
1037         struct fimd_context *ctx;
1038         struct device_node *i80_if_timings;
1039         struct resource *res;
1040         int ret;
1041
1042         if (!dev->of_node)
1043                 return -ENODEV;
1044
1045         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1046         if (!ctx)
1047                 return -ENOMEM;
1048
1049         ctx->dev = dev;
1050         ctx->suspended = true;
1051         ctx->driver_data = of_device_get_match_data(dev);
1052
1053         if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1054                 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1055         if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1056                 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1057
1058         i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1059         if (i80_if_timings) {
1060                 u32 val;
1061
1062                 ctx->i80_if = true;
1063
1064                 if (ctx->driver_data->has_vidoutcon)
1065                         ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1066                 else
1067                         ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1068                 /*
1069                  * The user manual describes that this "DSI_EN" bit is required
1070                  * to enable I80 24-bit data interface.
1071                  */
1072                 ctx->vidcon0 |= VIDCON0_DSI_EN;
1073
1074                 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1075                         val = 0;
1076                 ctx->i80ifcon = LCD_CS_SETUP(val);
1077                 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1078                         val = 0;
1079                 ctx->i80ifcon |= LCD_WR_SETUP(val);
1080                 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1081                         val = 1;
1082                 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1083                 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1084                         val = 0;
1085                 ctx->i80ifcon |= LCD_WR_HOLD(val);
1086         }
1087         of_node_put(i80_if_timings);
1088
1089         ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1090                                                         "samsung,sysreg");
1091         if (IS_ERR(ctx->sysreg)) {
1092                 dev_warn(dev, "failed to get system register.\n");
1093                 ctx->sysreg = NULL;
1094         }
1095
1096         ctx->bus_clk = devm_clk_get(dev, "fimd");
1097         if (IS_ERR(ctx->bus_clk)) {
1098                 dev_err(dev, "failed to get bus clock\n");
1099                 return PTR_ERR(ctx->bus_clk);
1100         }
1101
1102         ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1103         if (IS_ERR(ctx->lcd_clk)) {
1104                 dev_err(dev, "failed to get lcd clock\n");
1105                 return PTR_ERR(ctx->lcd_clk);
1106         }
1107
1108         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1109
1110         ctx->regs = devm_ioremap_resource(dev, res);
1111         if (IS_ERR(ctx->regs))
1112                 return PTR_ERR(ctx->regs);
1113
1114         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1115                                            ctx->i80_if ? "lcd_sys" : "vsync");
1116         if (!res) {
1117                 dev_err(dev, "irq request failed.\n");
1118                 return -ENXIO;
1119         }
1120
1121         ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1122                                                         0, "drm_fimd", ctx);
1123         if (ret) {
1124                 dev_err(dev, "irq request failed.\n");
1125                 return ret;
1126         }
1127
1128         init_waitqueue_head(&ctx->wait_vsync_queue);
1129         atomic_set(&ctx->wait_vsync_event, 0);
1130
1131         platform_set_drvdata(pdev, ctx);
1132
1133         ctx->encoder = exynos_dpi_probe(dev);
1134         if (IS_ERR(ctx->encoder))
1135                 return PTR_ERR(ctx->encoder);
1136
1137         pm_runtime_enable(dev);
1138
1139         ret = component_add(dev, &fimd_component_ops);
1140         if (ret)
1141                 goto err_disable_pm_runtime;
1142
1143         return ret;
1144
1145 err_disable_pm_runtime:
1146         pm_runtime_disable(dev);
1147
1148         return ret;
1149 }
1150
1151 static int fimd_remove(struct platform_device *pdev)
1152 {
1153         pm_runtime_disable(&pdev->dev);
1154
1155         component_del(&pdev->dev, &fimd_component_ops);
1156
1157         return 0;
1158 }
1159
1160 #ifdef CONFIG_PM
1161 static int exynos_fimd_suspend(struct device *dev)
1162 {
1163         struct fimd_context *ctx = dev_get_drvdata(dev);
1164
1165         clk_disable_unprepare(ctx->lcd_clk);
1166         clk_disable_unprepare(ctx->bus_clk);
1167
1168         return 0;
1169 }
1170
1171 static int exynos_fimd_resume(struct device *dev)
1172 {
1173         struct fimd_context *ctx = dev_get_drvdata(dev);
1174         int ret;
1175
1176         ret = clk_prepare_enable(ctx->bus_clk);
1177         if (ret < 0) {
1178                 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
1179                 return ret;
1180         }
1181
1182         ret = clk_prepare_enable(ctx->lcd_clk);
1183         if  (ret < 0) {
1184                 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
1185                 return ret;
1186         }
1187
1188         return 0;
1189 }
1190 #endif
1191
1192 static const struct dev_pm_ops exynos_fimd_pm_ops = {
1193         SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL)
1194         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1195                                 pm_runtime_force_resume)
1196 };
1197
1198 struct platform_driver fimd_driver = {
1199         .probe          = fimd_probe,
1200         .remove         = fimd_remove,
1201         .driver         = {
1202                 .name   = "exynos4-fb",
1203                 .owner  = THIS_MODULE,
1204                 .pm     = &exynos_fimd_pm_ops,
1205                 .of_match_table = fimd_driver_dt_match,
1206         },
1207 };