1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MIPI Display Bus Interface (DBI) LCD controller support
5 * Copyright 2016 Noralf Trønnes
8 #include <linux/backlight.h>
9 #include <linux/debugfs.h>
10 #include <linux/delay.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/module.h>
13 #include <linux/regulator/consumer.h>
14 #include <linux/spi/spi.h>
16 #include <drm/drm_connector.h>
17 #include <drm/drm_damage_helper.h>
18 #include <drm/drm_drv.h>
19 #include <drm/drm_file.h>
20 #include <drm/drm_format_helper.h>
21 #include <drm/drm_fourcc.h>
22 #include <drm/drm_framebuffer.h>
23 #include <drm/drm_gem.h>
24 #include <drm/drm_gem_atomic_helper.h>
25 #include <drm/drm_gem_framebuffer_helper.h>
26 #include <drm/drm_mipi_dbi.h>
27 #include <drm/drm_modes.h>
28 #include <drm/drm_probe_helper.h>
29 #include <drm/drm_rect.h>
30 #include <video/mipi_display.h>
32 #define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */
34 #define DCS_POWER_MODE_DISPLAY BIT(2)
35 #define DCS_POWER_MODE_DISPLAY_NORMAL_MODE BIT(3)
36 #define DCS_POWER_MODE_SLEEP_MODE BIT(4)
37 #define DCS_POWER_MODE_PARTIAL_MODE BIT(5)
38 #define DCS_POWER_MODE_IDLE_MODE BIT(6)
39 #define DCS_POWER_MODE_RESERVED_MASK (BIT(0) | BIT(1) | BIT(7))
44 * This library provides helpers for MIPI Display Bus Interface (DBI)
45 * compatible display controllers.
47 * Many controllers for tiny lcd displays are MIPI compliant and can use this
48 * library. If a controller uses registers 0x2A and 0x2B to set the area to
49 * update and uses register 0x2C to write to frame memory, it is most likely
52 * Only MIPI Type 1 displays are supported since a full frame memory is needed.
54 * There are 3 MIPI DBI implementation types:
56 * A. Motorola 6800 type parallel bus
58 * B. Intel 8080 type parallel bus
60 * C. SPI type with 3 options:
62 * 1. 9-bit with the Data/Command signal as the ninth bit
63 * 2. Same as above except it's sent as 16 bits
64 * 3. 8-bit with the Data/Command signal as a separate D/CX pin
66 * Currently mipi_dbi only supports Type C options 1 and 3 with
67 * mipi_dbi_spi_init().
70 #define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \
73 DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \
75 DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\
77 DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \
80 static const u8 mipi_dbi_dcs_read_commands[] = {
81 MIPI_DCS_GET_DISPLAY_ID,
82 MIPI_DCS_GET_RED_CHANNEL,
83 MIPI_DCS_GET_GREEN_CHANNEL,
84 MIPI_DCS_GET_BLUE_CHANNEL,
85 MIPI_DCS_GET_DISPLAY_STATUS,
86 MIPI_DCS_GET_POWER_MODE,
87 MIPI_DCS_GET_ADDRESS_MODE,
88 MIPI_DCS_GET_PIXEL_FORMAT,
89 MIPI_DCS_GET_DISPLAY_MODE,
90 MIPI_DCS_GET_SIGNAL_MODE,
91 MIPI_DCS_GET_DIAGNOSTIC_RESULT,
92 MIPI_DCS_READ_MEMORY_START,
93 MIPI_DCS_READ_MEMORY_CONTINUE,
94 MIPI_DCS_GET_SCANLINE,
95 MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
96 MIPI_DCS_GET_CONTROL_DISPLAY,
97 MIPI_DCS_GET_POWER_SAVE,
98 MIPI_DCS_GET_CABC_MIN_BRIGHTNESS,
99 MIPI_DCS_READ_DDB_START,
100 MIPI_DCS_READ_DDB_CONTINUE,
104 static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd)
108 if (!dbi->read_commands)
111 for (i = 0; i < 0xff; i++) {
112 if (!dbi->read_commands[i])
114 if (cmd == dbi->read_commands[i])
122 * mipi_dbi_command_read - MIPI DCS read command
123 * @dbi: MIPI DBI structure
127 * Send MIPI DCS read command to the controller.
130 * Zero on success, negative error code on failure.
132 int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val)
134 if (!dbi->read_commands)
137 if (!mipi_dbi_command_is_read(dbi, cmd))
140 return mipi_dbi_command_buf(dbi, cmd, val, 1);
142 EXPORT_SYMBOL(mipi_dbi_command_read);
145 * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array
146 * @dbi: MIPI DBI structure
148 * @data: Parameter buffer
149 * @len: Buffer length
152 * Zero on success, negative error code on failure.
154 int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len)
159 /* SPI requires dma-safe buffers */
160 cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL);
164 mutex_lock(&dbi->cmdlock);
165 ret = dbi->command(dbi, cmdbuf, data, len);
166 mutex_unlock(&dbi->cmdlock);
172 EXPORT_SYMBOL(mipi_dbi_command_buf);
174 /* This should only be used by mipi_dbi_command() */
175 int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, const u8 *data,
181 buf = kmemdup(data, len, GFP_KERNEL);
185 ret = mipi_dbi_command_buf(dbi, cmd, buf, len);
191 EXPORT_SYMBOL(mipi_dbi_command_stackbuf);
194 * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary
195 * @dst: The destination buffer
196 * @src: The source buffer
197 * @fb: The source framebuffer
198 * @clip: Clipping rectangle of the area to be copied
199 * @swap: When true, swap MSB/LSB of 16-bit values
200 * @fmtcnv_state: Format-conversion state
203 * Zero on success, negative error code on failure.
205 int mipi_dbi_buf_copy(void *dst, struct iosys_map *src, struct drm_framebuffer *fb,
206 struct drm_rect *clip, bool swap,
207 struct drm_format_conv_state *fmtcnv_state)
209 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
210 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
211 struct iosys_map dst_map = IOSYS_MAP_INIT_VADDR(dst);
214 ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
218 switch (fb->format->format) {
219 case DRM_FORMAT_RGB565:
221 drm_fb_swab(&dst_map, NULL, src, fb, clip, !gem->import_attach,
224 drm_fb_memcpy(&dst_map, NULL, src, fb, clip);
226 case DRM_FORMAT_RGB888:
227 drm_fb_memcpy(&dst_map, NULL, src, fb, clip);
229 case DRM_FORMAT_XRGB8888:
230 switch (dbidev->pixel_format) {
231 case DRM_FORMAT_RGB565:
232 drm_fb_xrgb8888_to_rgb565(&dst_map, NULL, src, fb, clip, fmtcnv_state, swap);
234 case DRM_FORMAT_RGB888:
235 drm_fb_xrgb8888_to_rgb888(&dst_map, NULL, src, fb, clip, fmtcnv_state);
240 drm_err_once(fb->dev, "Format is not supported: %p4cc\n",
241 &fb->format->format);
245 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
249 EXPORT_SYMBOL(mipi_dbi_buf_copy);
251 static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev,
252 unsigned int xs, unsigned int xe,
253 unsigned int ys, unsigned int ye)
255 struct mipi_dbi *dbi = &dbidev->dbi;
257 xs += dbidev->left_offset;
258 xe += dbidev->left_offset;
259 ys += dbidev->top_offset;
260 ye += dbidev->top_offset;
262 mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff,
263 xs & 0xff, (xe >> 8) & 0xff, xe & 0xff);
264 mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff,
265 ys & 0xff, (ye >> 8) & 0xff, ye & 0xff);
268 static void mipi_dbi_fb_dirty(struct iosys_map *src, struct drm_framebuffer *fb,
269 struct drm_rect *rect, struct drm_format_conv_state *fmtcnv_state)
271 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
272 unsigned int height = rect->y2 - rect->y1;
273 unsigned int width = rect->x2 - rect->x1;
274 const struct drm_format_info *dst_format;
275 struct mipi_dbi *dbi = &dbidev->dbi;
276 bool swap = dbi->swap_bytes;
282 full = width == fb->width && height == fb->height;
284 DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect));
286 if (!dbi->dc || !full || swap ||
287 fb->format->format == DRM_FORMAT_XRGB8888) {
289 ret = mipi_dbi_buf_copy(tr, src, fb, rect, swap, fmtcnv_state);
293 tr = src->vaddr; /* TODO: Use mapping abstraction properly */
296 mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1,
299 if (fb->format->format == DRM_FORMAT_XRGB8888)
300 dst_format = drm_format_info(dbidev->pixel_format);
302 dst_format = fb->format;
303 len = drm_format_info_min_pitch(dst_format, 0, width) * height;
305 ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr, len);
308 drm_err_once(fb->dev, "Failed to update display %d\n", ret);
312 * mipi_dbi_pipe_mode_valid - MIPI DBI mode-valid helper
313 * @pipe: Simple display pipe
314 * @mode: The mode to test
316 * This function validates a given display mode against the MIPI DBI's hardware
317 * display. Drivers can use this as their &drm_simple_display_pipe_funcs->mode_valid
320 enum drm_mode_status mipi_dbi_pipe_mode_valid(struct drm_simple_display_pipe *pipe,
321 const struct drm_display_mode *mode)
323 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
325 return drm_crtc_helper_mode_valid_fixed(&pipe->crtc, mode, &dbidev->mode);
327 EXPORT_SYMBOL(mipi_dbi_pipe_mode_valid);
330 * mipi_dbi_pipe_update - Display pipe update helper
331 * @pipe: Simple display pipe
332 * @old_state: Old plane state
334 * This function handles framebuffer flushing and vblank events. Drivers can use
335 * this as their &drm_simple_display_pipe_funcs->update callback.
337 void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe,
338 struct drm_plane_state *old_state)
340 struct drm_plane_state *state = pipe->plane.state;
341 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(state);
342 struct drm_framebuffer *fb = state->fb;
343 struct drm_rect rect;
346 if (!pipe->crtc.state->active)
352 if (!drm_dev_enter(fb->dev, &idx))
355 if (drm_atomic_helper_damage_merged(old_state, state, &rect))
356 mipi_dbi_fb_dirty(&shadow_plane_state->data[0], fb, &rect,
357 &shadow_plane_state->fmtcnv_state);
361 EXPORT_SYMBOL(mipi_dbi_pipe_update);
364 * mipi_dbi_enable_flush - MIPI DBI enable helper
365 * @dbidev: MIPI DBI device structure
366 * @crtc_state: CRTC state
367 * @plane_state: Plane state
369 * Flushes the whole framebuffer and enables the backlight. Drivers can use this
370 * in their &drm_simple_display_pipe_funcs->enable callback.
372 * Note: Drivers which don't use mipi_dbi_pipe_update() because they have custom
373 * framebuffer flushing, can't use this function since they both use the same
376 void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev,
377 struct drm_crtc_state *crtc_state,
378 struct drm_plane_state *plane_state)
380 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
381 struct drm_framebuffer *fb = plane_state->fb;
382 struct drm_rect rect = {
390 if (!drm_dev_enter(&dbidev->drm, &idx))
393 mipi_dbi_fb_dirty(&shadow_plane_state->data[0], fb, &rect,
394 &shadow_plane_state->fmtcnv_state);
395 backlight_enable(dbidev->backlight);
399 EXPORT_SYMBOL(mipi_dbi_enable_flush);
401 static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev)
403 struct drm_device *drm = &dbidev->drm;
404 u16 height = drm->mode_config.min_height;
405 u16 width = drm->mode_config.min_width;
406 struct mipi_dbi *dbi = &dbidev->dbi;
407 size_t len = width * height * 2;
410 if (!drm_dev_enter(drm, &idx))
413 memset(dbidev->tx_buf, 0, len);
415 mipi_dbi_set_window_address(dbidev, 0, width - 1, 0, height - 1);
416 mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START,
417 (u8 *)dbidev->tx_buf, len);
423 * mipi_dbi_pipe_disable - MIPI DBI pipe disable helper
424 * @pipe: Display pipe
426 * This function disables backlight if present, if not the display memory is
427 * blanked. The regulator is disabled if in use. Drivers can use this as their
428 * &drm_simple_display_pipe_funcs->disable callback.
430 void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe)
432 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
436 if (dbidev->backlight)
437 backlight_disable(dbidev->backlight);
439 mipi_dbi_blank(dbidev);
441 if (dbidev->regulator)
442 regulator_disable(dbidev->regulator);
443 if (dbidev->io_regulator)
444 regulator_disable(dbidev->io_regulator);
446 EXPORT_SYMBOL(mipi_dbi_pipe_disable);
449 * mipi_dbi_pipe_begin_fb_access - MIPI DBI pipe begin-access helper
450 * @pipe: Display pipe
451 * @plane_state: Plane state
453 * This function implements struct &drm_simple_display_funcs.begin_fb_access.
455 * See drm_gem_begin_shadow_fb_access() for details and mipi_dbi_pipe_cleanup_fb()
459 * 0 on success, or a negative errno code otherwise.
461 int mipi_dbi_pipe_begin_fb_access(struct drm_simple_display_pipe *pipe,
462 struct drm_plane_state *plane_state)
464 return drm_gem_begin_shadow_fb_access(&pipe->plane, plane_state);
466 EXPORT_SYMBOL(mipi_dbi_pipe_begin_fb_access);
469 * mipi_dbi_pipe_end_fb_access - MIPI DBI pipe end-access helper
470 * @pipe: Display pipe
471 * @plane_state: Plane state
473 * This function implements struct &drm_simple_display_funcs.end_fb_access.
475 * See mipi_dbi_pipe_begin_fb_access().
477 void mipi_dbi_pipe_end_fb_access(struct drm_simple_display_pipe *pipe,
478 struct drm_plane_state *plane_state)
480 drm_gem_end_shadow_fb_access(&pipe->plane, plane_state);
482 EXPORT_SYMBOL(mipi_dbi_pipe_end_fb_access);
485 * mipi_dbi_pipe_reset_plane - MIPI DBI plane-reset helper
486 * @pipe: Display pipe
488 * This function implements struct &drm_simple_display_funcs.reset_plane
489 * for MIPI DBI planes.
491 void mipi_dbi_pipe_reset_plane(struct drm_simple_display_pipe *pipe)
493 drm_gem_reset_shadow_plane(&pipe->plane);
495 EXPORT_SYMBOL(mipi_dbi_pipe_reset_plane);
498 * mipi_dbi_pipe_duplicate_plane_state - duplicates MIPI DBI plane state
499 * @pipe: Display pipe
501 * This function implements struct &drm_simple_display_funcs.duplicate_plane_state
502 * for MIPI DBI planes.
504 * See drm_gem_duplicate_shadow_plane_state() for additional details.
507 * A pointer to a new plane state on success, or NULL otherwise.
509 struct drm_plane_state *mipi_dbi_pipe_duplicate_plane_state(struct drm_simple_display_pipe *pipe)
511 return drm_gem_duplicate_shadow_plane_state(&pipe->plane);
513 EXPORT_SYMBOL(mipi_dbi_pipe_duplicate_plane_state);
516 * mipi_dbi_pipe_destroy_plane_state - cleans up MIPI DBI plane state
517 * @pipe: Display pipe
518 * @plane_state: Plane state
520 * This function implements struct drm_simple_display_funcs.destroy_plane_state
521 * for MIPI DBI planes.
523 * See drm_gem_destroy_shadow_plane_state() for additional details.
525 void mipi_dbi_pipe_destroy_plane_state(struct drm_simple_display_pipe *pipe,
526 struct drm_plane_state *plane_state)
528 drm_gem_destroy_shadow_plane_state(&pipe->plane, plane_state);
530 EXPORT_SYMBOL(mipi_dbi_pipe_destroy_plane_state);
532 static int mipi_dbi_connector_get_modes(struct drm_connector *connector)
534 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(connector->dev);
536 return drm_connector_helper_get_modes_fixed(connector, &dbidev->mode);
539 static const struct drm_connector_helper_funcs mipi_dbi_connector_hfuncs = {
540 .get_modes = mipi_dbi_connector_get_modes,
543 static const struct drm_connector_funcs mipi_dbi_connector_funcs = {
544 .reset = drm_atomic_helper_connector_reset,
545 .fill_modes = drm_helper_probe_single_connector_modes,
546 .destroy = drm_connector_cleanup,
547 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
548 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
551 static int mipi_dbi_rotate_mode(struct drm_display_mode *mode,
552 unsigned int rotation)
554 if (rotation == 0 || rotation == 180) {
556 } else if (rotation == 90 || rotation == 270) {
557 swap(mode->hdisplay, mode->vdisplay);
558 swap(mode->hsync_start, mode->vsync_start);
559 swap(mode->hsync_end, mode->vsync_end);
560 swap(mode->htotal, mode->vtotal);
561 swap(mode->width_mm, mode->height_mm);
568 static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = {
569 .fb_create = drm_gem_fb_create_with_dirty,
570 .atomic_check = drm_atomic_helper_check,
571 .atomic_commit = drm_atomic_helper_commit,
574 static const uint32_t mipi_dbi_formats[] = {
580 * mipi_dbi_dev_init_with_formats - MIPI DBI device initialization with custom formats
581 * @dbidev: MIPI DBI device structure to initialize
582 * @funcs: Display pipe functions
583 * @formats: Array of supported formats (DRM_FORMAT\_\*).
584 * @format_count: Number of elements in @formats
585 * @mode: Display mode
586 * @rotation: Initial rotation in degrees Counter Clock Wise
587 * @tx_buf_size: Allocate a transmit buffer of this size.
589 * This function sets up a &drm_simple_display_pipe with a &drm_connector that
590 * has one fixed &drm_display_mode which is rotated according to @rotation.
591 * This mode is used to set the mode config min/max width/height properties.
593 * Use mipi_dbi_dev_init() if you want native RGB565 and emulated XRGB8888 format.
596 * Some of the helper functions expects RGB565 to be the default format and the
597 * transmit buffer sized to fit that.
600 * Zero on success, negative error code on failure.
602 int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev,
603 const struct drm_simple_display_pipe_funcs *funcs,
604 const uint32_t *formats, unsigned int format_count,
605 const struct drm_display_mode *mode,
606 unsigned int rotation, size_t tx_buf_size)
608 static const uint64_t modifiers[] = {
609 DRM_FORMAT_MOD_LINEAR,
610 DRM_FORMAT_MOD_INVALID
612 struct drm_device *drm = &dbidev->drm;
615 if (!dbidev->dbi.command)
618 ret = drmm_mode_config_init(drm);
622 dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL);
626 drm_mode_copy(&dbidev->mode, mode);
627 ret = mipi_dbi_rotate_mode(&dbidev->mode, rotation);
629 DRM_ERROR("Illegal rotation value %u\n", rotation);
633 drm_connector_helper_add(&dbidev->connector, &mipi_dbi_connector_hfuncs);
634 ret = drm_connector_init(drm, &dbidev->connector, &mipi_dbi_connector_funcs,
635 DRM_MODE_CONNECTOR_SPI);
639 ret = drm_simple_display_pipe_init(drm, &dbidev->pipe, funcs, formats, format_count,
640 modifiers, &dbidev->connector);
644 drm_plane_enable_fb_damage_clips(&dbidev->pipe.plane);
646 drm->mode_config.funcs = &mipi_dbi_mode_config_funcs;
647 drm->mode_config.min_width = dbidev->mode.hdisplay;
648 drm->mode_config.max_width = dbidev->mode.hdisplay;
649 drm->mode_config.min_height = dbidev->mode.vdisplay;
650 drm->mode_config.max_height = dbidev->mode.vdisplay;
651 dbidev->rotation = rotation;
652 dbidev->pixel_format = formats[0];
653 if (formats[0] == DRM_FORMAT_RGB888)
654 dbidev->dbi.write_memory_bpw = 8;
656 DRM_DEBUG_KMS("rotation = %u\n", rotation);
660 EXPORT_SYMBOL(mipi_dbi_dev_init_with_formats);
663 * mipi_dbi_dev_init - MIPI DBI device initialization
664 * @dbidev: MIPI DBI device structure to initialize
665 * @funcs: Display pipe functions
666 * @mode: Display mode
667 * @rotation: Initial rotation in degrees Counter Clock Wise
669 * This function sets up a &drm_simple_display_pipe with a &drm_connector that
670 * has one fixed &drm_display_mode which is rotated according to @rotation.
671 * This mode is used to set the mode config min/max width/height properties.
672 * Additionally &mipi_dbi.tx_buf is allocated.
674 * Supported formats: Native RGB565 and emulated XRGB8888.
677 * Zero on success, negative error code on failure.
679 int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev,
680 const struct drm_simple_display_pipe_funcs *funcs,
681 const struct drm_display_mode *mode, unsigned int rotation)
683 size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16);
685 dbidev->drm.mode_config.preferred_depth = 16;
687 return mipi_dbi_dev_init_with_formats(dbidev, funcs, mipi_dbi_formats,
688 ARRAY_SIZE(mipi_dbi_formats), mode,
691 EXPORT_SYMBOL(mipi_dbi_dev_init);
694 * mipi_dbi_hw_reset - Hardware reset of controller
695 * @dbi: MIPI DBI structure
697 * Reset controller if the &mipi_dbi->reset gpio is set.
699 void mipi_dbi_hw_reset(struct mipi_dbi *dbi)
704 gpiod_set_value_cansleep(dbi->reset, 0);
705 usleep_range(20, 1000);
706 gpiod_set_value_cansleep(dbi->reset, 1);
709 EXPORT_SYMBOL(mipi_dbi_hw_reset);
712 * mipi_dbi_display_is_on - Check if display is on
713 * @dbi: MIPI DBI structure
715 * This function checks the Power Mode register (if readable) to see if
716 * display output is turned on. This can be used to see if the bootloader
717 * has already turned on the display avoiding flicker when the pipeline is
721 * true if the display can be verified to be on, false otherwise.
723 bool mipi_dbi_display_is_on(struct mipi_dbi *dbi)
727 if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val))
730 val &= ~DCS_POWER_MODE_RESERVED_MASK;
732 /* The poweron/reset value is 08h DCS_POWER_MODE_DISPLAY_NORMAL_MODE */
733 if (val != (DCS_POWER_MODE_DISPLAY |
734 DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE))
737 DRM_DEBUG_DRIVER("Display is ON\n");
741 EXPORT_SYMBOL(mipi_dbi_display_is_on);
743 static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev *dbidev, bool cond)
745 struct device *dev = dbidev->drm.dev;
746 struct mipi_dbi *dbi = &dbidev->dbi;
749 if (dbidev->regulator) {
750 ret = regulator_enable(dbidev->regulator);
752 DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret);
757 if (dbidev->io_regulator) {
758 ret = regulator_enable(dbidev->io_regulator);
760 DRM_DEV_ERROR(dev, "Failed to enable I/O regulator (%d)\n", ret);
761 if (dbidev->regulator)
762 regulator_disable(dbidev->regulator);
767 if (cond && mipi_dbi_display_is_on(dbi))
770 mipi_dbi_hw_reset(dbi);
771 ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET);
773 DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret);
774 if (dbidev->regulator)
775 regulator_disable(dbidev->regulator);
776 if (dbidev->io_regulator)
777 regulator_disable(dbidev->io_regulator);
782 * If we did a hw reset, we know the controller is in Sleep mode and
783 * per MIPI DSC spec should wait 5ms after soft reset. If we didn't,
784 * we assume worst case and wait 120ms.
787 usleep_range(5000, 20000);
795 * mipi_dbi_poweron_reset - MIPI DBI poweron and reset
796 * @dbidev: MIPI DBI device structure
798 * This function enables the regulator if used and does a hardware and software
802 * Zero on success, or a negative error code.
804 int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev)
806 return mipi_dbi_poweron_reset_conditional(dbidev, false);
808 EXPORT_SYMBOL(mipi_dbi_poweron_reset);
811 * mipi_dbi_poweron_conditional_reset - MIPI DBI poweron and conditional reset
812 * @dbidev: MIPI DBI device structure
814 * This function enables the regulator if used and if the display is off, it
815 * does a hardware and software reset. If mipi_dbi_display_is_on() determines
816 * that the display is on, no reset is performed.
819 * Zero if the controller was reset, 1 if the display was already on, or a
820 * negative error code.
822 int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev)
824 return mipi_dbi_poweron_reset_conditional(dbidev, true);
826 EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset);
828 #if IS_ENABLED(CONFIG_SPI)
831 * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed
833 * @len: The transfer buffer length.
835 * Many controllers have a max speed of 10MHz, but can be pushed way beyond
836 * that. Increase reliability by running pixel data at max speed and the rest
837 * at 10MHz, preventing transfer glitches from messing up the init settings.
839 u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len)
842 return 0; /* use default */
844 return min_t(u32, 10000000, spi->max_speed_hz);
846 EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed);
849 * MIPI DBI Type C Option 1
851 * If the SPI controller doesn't have 9 bits per word support,
852 * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer.
853 * Pad partial blocks with MIPI_DCS_NOP (zero).
854 * This is how the D/C bit (x) is added:
866 static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc,
867 const void *buf, size_t len,
870 bool swap_bytes = (bpw == 16);
871 size_t chunk, max_chunk = dbi->tx_buf9_len;
872 struct spi_device *spi = dbi->spi;
873 struct spi_transfer tr = {
874 .tx_buf = dbi->tx_buf9,
877 struct spi_message m;
882 if (drm_debug_enabled(DRM_UT_DRIVER))
883 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
884 __func__, dc, max_chunk);
886 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
887 spi_message_init_with_transfers(&m, &tr, 1);
890 if (WARN_ON_ONCE(len != 1))
893 /* Command: pad no-op's (zeroes) at beginning of block */
899 return spi_sync(spi, &m);
902 /* max with room for adding one bit per byte */
903 max_chunk = max_chunk / 9 * 8;
904 /* but no bigger than len */
905 max_chunk = min(max_chunk, len);
907 max_chunk = max_t(size_t, 8, max_chunk & ~0x7);
912 chunk = min(len, max_chunk);
919 /* Data: pad no-op's (zeroes) at end of block */
923 for (i = 1; i < (chunk + 1); i++) {
925 *dst++ = carry | BIT(8 - i) | (val >> i);
926 carry = val << (8 - i);
929 *dst++ = carry | BIT(8 - i) | (val >> i);
930 carry = val << (8 - i);
935 for (i = 1; i < (chunk + 1); i++) {
937 *dst++ = carry | BIT(8 - i) | (val >> i);
938 carry = val << (8 - i);
946 for (i = 0; i < chunk; i += 8) {
948 *dst++ = BIT(7) | (src[1] >> 1);
949 *dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2);
950 *dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3);
951 *dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4);
952 *dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5);
953 *dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6);
954 *dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7);
955 *dst++ = (src[7] << 1) | BIT(0);
958 *dst++ = BIT(7) | (src[0] >> 1);
959 *dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2);
960 *dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3);
961 *dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4);
962 *dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5);
963 *dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6);
964 *dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7);
965 *dst++ = (src[6] << 1) | BIT(0);
974 tr.len = chunk + added;
976 ret = spi_sync(spi, &m);
984 static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc,
985 const void *buf, size_t len,
988 struct spi_device *spi = dbi->spi;
989 struct spi_transfer tr = {
992 const u16 *src16 = buf;
993 const u8 *src8 = buf;
994 struct spi_message m;
999 if (!spi_is_bpw_supported(spi, 9))
1000 return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw);
1002 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
1003 max_chunk = dbi->tx_buf9_len;
1004 dst16 = dbi->tx_buf9;
1006 if (drm_debug_enabled(DRM_UT_DRIVER))
1007 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
1008 __func__, dc, max_chunk);
1010 max_chunk = min(max_chunk / 2, len);
1012 spi_message_init_with_transfers(&m, &tr, 1);
1016 size_t chunk = min(len, max_chunk);
1020 for (i = 0; i < (chunk * 2); i += 2) {
1021 dst16[i] = *src16 >> 8;
1022 dst16[i + 1] = *src16++ & 0xFF;
1025 dst16[i + 1] |= 0x0100;
1029 for (i = 0; i < chunk; i++) {
1039 ret = spi_sync(spi, &m);
1047 static int mipi_dbi_typec1_command_read(struct mipi_dbi *dbi, u8 *cmd,
1048 u8 *data, size_t len)
1050 struct spi_device *spi = dbi->spi;
1051 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
1052 spi->max_speed_hz / 2);
1053 struct spi_transfer tr[2] = {
1055 .speed_hz = speed_hz,
1057 .tx_buf = dbi->tx_buf9,
1060 .speed_hz = speed_hz,
1066 struct spi_message m;
1073 if (!spi_is_bpw_supported(spi, 9)) {
1075 * FIXME: implement something like mipi_dbi_spi1e_transfer() but
1076 * for reads using emulation.
1079 "reading on host not supporting 9 bpw not yet implemented\n");
1084 * Turn the 8bit command into a 16bit version of the command in the
1085 * buffer. Only 9 bits of this will be used when executing the actual
1088 dst16 = dbi->tx_buf9;
1091 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
1092 ret = spi_sync(spi, &m);
1095 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
1100 static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd,
1101 u8 *parameters, size_t num)
1103 unsigned int bpw = 8;
1106 if (mipi_dbi_command_is_read(dbi, *cmd))
1107 return mipi_dbi_typec1_command_read(dbi, cmd, parameters, num);
1109 MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num);
1111 ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8);
1115 if (*cmd == MIPI_DCS_WRITE_MEMORY_START)
1116 bpw = dbi->write_memory_bpw;
1118 return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw);
1121 /* MIPI DBI Type C Option 3 */
1123 static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd,
1124 u8 *data, size_t len)
1126 struct spi_device *spi = dbi->spi;
1127 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
1128 spi->max_speed_hz / 2);
1129 struct spi_transfer tr[2] = {
1131 .speed_hz = speed_hz,
1135 .speed_hz = speed_hz,
1139 struct spi_message m;
1147 * Support non-standard 24-bit and 32-bit Nokia read commands which
1148 * start with a dummy clock, so we need to read an extra byte.
1150 if (*cmd == MIPI_DCS_GET_DISPLAY_ID ||
1151 *cmd == MIPI_DCS_GET_DISPLAY_STATUS) {
1152 if (!(len == 3 || len == 4))
1155 tr[1].len = len + 1;
1158 buf = kmalloc(tr[1].len, GFP_KERNEL);
1164 spi_bus_lock(spi->controller);
1165 gpiod_set_value_cansleep(dbi->dc, 0);
1167 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
1168 ret = spi_sync_locked(spi, &m);
1169 spi_bus_unlock(spi->controller);
1173 if (tr[1].len == len) {
1174 memcpy(data, buf, len);
1178 for (i = 0; i < len; i++)
1179 data[i] = (buf[i] << 1) | (buf[i + 1] >> 7);
1182 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
1190 static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd,
1191 u8 *par, size_t num)
1193 struct spi_device *spi = dbi->spi;
1194 unsigned int bpw = 8;
1198 if (mipi_dbi_command_is_read(dbi, *cmd))
1199 return mipi_dbi_typec3_command_read(dbi, cmd, par, num);
1201 MIPI_DBI_DEBUG_COMMAND(*cmd, par, num);
1203 spi_bus_lock(spi->controller);
1204 gpiod_set_value_cansleep(dbi->dc, 0);
1205 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1);
1206 ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1);
1207 spi_bus_unlock(spi->controller);
1211 if (*cmd == MIPI_DCS_WRITE_MEMORY_START)
1212 bpw = dbi->write_memory_bpw;
1214 spi_bus_lock(spi->controller);
1215 gpiod_set_value_cansleep(dbi->dc, 1);
1216 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
1217 ret = mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num);
1218 spi_bus_unlock(spi->controller);
1224 * mipi_dbi_spi_init - Initialize MIPI DBI SPI interface
1226 * @dbi: MIPI DBI structure to initialize
1227 * @dc: D/C gpio (optional)
1229 * This function sets &mipi_dbi->command, enables &mipi_dbi->read_commands for the
1230 * usual read commands. It should be followed by a call to mipi_dbi_dev_init() or
1231 * a driver-specific init.
1233 * If @dc is set, a Type C Option 3 interface is assumed, if not
1236 * If the command is %MIPI_DCS_WRITE_MEMORY_START and the pixel format is RGB565, endianness has
1237 * to be taken into account. The MIPI DBI serial interface is big endian and framebuffers are
1238 * assumed stored in memory as little endian (%DRM_FORMAT_BIG_ENDIAN is not supported).
1240 * This is how endianness is handled:
1242 * Option 1 (D/C as a bit): The buffer is sent on the wire byte by byte so the 16-bit buffer is
1243 * byteswapped before transfer.
1245 * Option 3 (D/C as a gpio): If the SPI controller supports 16 bits per word the buffer can be
1246 * sent as-is. If not the caller is responsible for swapping the bytes
1247 * before calling mipi_dbi_command_buf() and the buffer is sent 8 bpw.
1249 * This handling is optimised for %DRM_FORMAT_RGB565 framebuffers.
1251 * If the interface is Option 1 and the SPI controller doesn't support 9 bits per word,
1252 * the buffer is sent as 9x 8-bit words, padded with MIPI DCS no-op commands if necessary.
1255 * Zero on success, negative error code on failure.
1257 int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi,
1258 struct gpio_desc *dc)
1260 struct device *dev = &spi->dev;
1264 * Even though it's not the SPI device that does DMA (the master does),
1265 * the dma mask is necessary for the dma_alloc_wc() in the GEM code
1266 * (e.g., drm_gem_dma_create()). The dma_addr returned will be a physical
1267 * address which might be different from the bus address, but this is
1268 * not a problem since the address will not be used.
1269 * The virtual address is used in the transfer and the SPI core
1270 * re-maps it on the SPI master device using the DMA streaming API
1273 if (!dev->coherent_dma_mask) {
1274 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
1276 dev_warn(dev, "Failed to set dma mask %d\n", ret);
1282 dbi->read_commands = mipi_dbi_dcs_read_commands;
1283 dbi->write_memory_bpw = 16;
1286 dbi->command = mipi_dbi_typec3_command;
1288 if (!spi_is_bpw_supported(spi, 16)) {
1289 dbi->write_memory_bpw = 8;
1290 dbi->swap_bytes = true;
1293 dbi->command = mipi_dbi_typec1_command;
1294 dbi->tx_buf9_len = SZ_16K;
1295 dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL);
1300 mutex_init(&dbi->cmdlock);
1302 DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
1306 EXPORT_SYMBOL(mipi_dbi_spi_init);
1309 * mipi_dbi_spi_transfer - SPI transfer helper
1311 * @speed_hz: Override speed (optional)
1312 * @bpw: Bits per word
1313 * @buf: Buffer to transfer
1314 * @len: Buffer length
1316 * This SPI transfer helper breaks up the transfer of @buf into chunks which
1317 * the SPI controller driver can handle. The SPI bus must be locked when
1321 * Zero on success, negative error code on failure.
1323 int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz,
1324 u8 bpw, const void *buf, size_t len)
1326 size_t max_chunk = spi_max_transfer_size(spi);
1327 struct spi_transfer tr = {
1328 .bits_per_word = bpw,
1329 .speed_hz = speed_hz,
1331 struct spi_message m;
1335 /* In __spi_validate, there's a validation that no partial transfers
1336 * are accepted (xfer->len % w_size must be zero).
1337 * Here we align max_chunk to multiple of 2 (16bits),
1338 * to prevent transfers from being rejected.
1340 max_chunk = ALIGN_DOWN(max_chunk, 2);
1342 spi_message_init_with_transfers(&m, &tr, 1);
1345 chunk = min(len, max_chunk);
1352 ret = spi_sync_locked(spi, &m);
1359 EXPORT_SYMBOL(mipi_dbi_spi_transfer);
1361 #endif /* CONFIG_SPI */
1363 #ifdef CONFIG_DEBUG_FS
1365 static ssize_t mipi_dbi_debugfs_command_write(struct file *file,
1366 const char __user *ubuf,
1367 size_t count, loff_t *ppos)
1369 struct seq_file *m = file->private_data;
1370 struct mipi_dbi_dev *dbidev = m->private;
1371 u8 val, cmd = 0, parameters[64];
1372 char *buf, *pos, *token;
1375 if (!drm_dev_enter(&dbidev->drm, &idx))
1378 buf = memdup_user_nul(ubuf, count);
1384 /* strip trailing whitespace */
1385 for (i = count - 1; i > 0; i--)
1386 if (isspace(buf[i]))
1393 token = strsep(&pos, " ");
1399 ret = kstrtou8(token, 16, &val);
1406 parameters[i++] = val;
1414 ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i);
1421 return ret < 0 ? ret : count;
1424 static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused)
1426 struct mipi_dbi_dev *dbidev = m->private;
1427 struct mipi_dbi *dbi = &dbidev->dbi;
1432 if (!drm_dev_enter(&dbidev->drm, &idx))
1435 for (cmd = 0; cmd < 255; cmd++) {
1436 if (!mipi_dbi_command_is_read(dbi, cmd))
1440 case MIPI_DCS_READ_MEMORY_START:
1441 case MIPI_DCS_READ_MEMORY_CONTINUE:
1444 case MIPI_DCS_GET_DISPLAY_ID:
1447 case MIPI_DCS_GET_DISPLAY_STATUS:
1455 seq_printf(m, "%02x: ", cmd);
1456 ret = mipi_dbi_command_buf(dbi, cmd, val, len);
1458 seq_puts(m, "XX\n");
1461 seq_printf(m, "%*phN\n", (int)len, val);
1469 static int mipi_dbi_debugfs_command_open(struct inode *inode,
1472 return single_open(file, mipi_dbi_debugfs_command_show,
1476 static const struct file_operations mipi_dbi_debugfs_command_fops = {
1477 .owner = THIS_MODULE,
1478 .open = mipi_dbi_debugfs_command_open,
1480 .llseek = seq_lseek,
1481 .release = single_release,
1482 .write = mipi_dbi_debugfs_command_write,
1486 * mipi_dbi_debugfs_init - Create debugfs entries
1489 * This function creates a 'command' debugfs file for sending commands to the
1490 * controller or getting the read command values.
1491 * Drivers can use this as their &drm_driver->debugfs_init callback.
1494 void mipi_dbi_debugfs_init(struct drm_minor *minor)
1496 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(minor->dev);
1497 umode_t mode = S_IFREG | S_IWUSR;
1499 if (dbidev->dbi.read_commands)
1501 debugfs_create_file("command", mode, minor->debugfs_root, dbidev,
1502 &mipi_dbi_debugfs_command_fops);
1504 EXPORT_SYMBOL(mipi_dbi_debugfs_init);
1508 MODULE_DESCRIPTION("MIPI Display Bus Interface (DBI) LCD controller support");
1509 MODULE_LICENSE("GPL");