2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
31 #include <linux/bitfield.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/slab.h>
38 #include <linux/vga_switcheroo.h>
40 #include <drm/drm_displayid.h>
41 #include <drm/drm_drv.h>
42 #include <drm/drm_edid.h>
43 #include <drm/drm_encoder.h>
44 #include <drm/drm_print.h>
45 #include <drm/drm_scdc_helper.h>
47 #include "drm_crtc_internal.h"
49 #define version_greater(edid, maj, min) \
50 (((edid)->version > (maj)) || \
51 ((edid)->version == (maj) && (edid)->revision > (min)))
53 static int oui(u8 first, u8 second, u8 third)
55 return (first << 16) | (second << 8) | third;
58 #define EDID_EST_TIMINGS 16
59 #define EDID_STD_TIMINGS 8
60 #define EDID_DETAILED_TIMINGS 4
63 * EDID blocks out in the wild have a variety of bugs, try to collect
64 * them here (note that userspace may work around broken monitors first,
65 * but fixes should make their way here so that the kernel "just works"
66 * on as many displays as possible).
69 /* First detailed mode wrong, use largest 60Hz mode */
70 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
71 /* Reported 135MHz pixel clock is too high, needs adjustment */
72 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
73 /* Prefer the largest mode at 75 Hz */
74 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
75 /* Detail timing is in cm not mm */
76 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
77 /* Detailed timing descriptors have bogus size values, so just take the
78 * maximum size and use that.
80 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
81 /* use +hsync +vsync for detailed mode */
82 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
83 /* Force reduced-blanking timings for detailed modes */
84 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
86 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
88 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
90 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
92 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
93 /* Non desktop display (i.e. HMD) */
94 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
96 struct detailed_mode_closure {
97 struct drm_connector *connector;
109 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
111 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
116 static const struct edid_quirk {
119 } edid_quirk_list[] = {
121 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
123 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
125 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
126 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
128 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
129 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
131 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
132 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
134 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
135 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
137 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
138 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
140 /* Belinea 10 15 55 */
141 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
142 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
144 /* Envision Peripherals, Inc. EN-7100e */
145 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
146 /* Envision EN2028 */
147 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
149 /* Funai Electronics PM36B */
150 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
151 EDID_QUIRK_DETAILED_IN_CM),
153 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
154 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
156 /* LG Philips LCD LP154W01-A5 */
157 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
158 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
160 /* Samsung SyncMaster 205BW. Note: irony */
161 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
162 /* Samsung SyncMaster 22[5-6]BW */
163 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
164 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
166 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
167 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
169 /* ViewSonic VA2026w */
170 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
172 /* Medion MD 30217 PG */
173 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
176 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
178 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
179 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
181 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
182 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
184 /* Valve Index Headset */
185 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
186 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
187 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
188 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
189 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
190 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
203 /* HTC Vive and Vive Pro VR Headsets */
204 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
207 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
208 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
209 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
210 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
211 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
213 /* Windows Mixed Reality Headsets */
214 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('H', 'P', 'N', 0x3515, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
217 EDID_QUIRK('L', 'E', 'N', 0xb800, EDID_QUIRK_NON_DESKTOP),
218 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
219 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
221 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
223 /* Sony PlayStation VR Headset */
224 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
226 /* Sensics VR Headsets */
227 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
229 /* OSVR HDK and HDK2 VR Headsets */
230 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
234 * Autogenerated from the DMT spec.
235 * This table is copied from xfree86/modes/xf86EdidModes.c.
237 static const struct drm_display_mode drm_dmt_modes[] = {
238 /* 0x01 - 640x350@85Hz */
239 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
240 736, 832, 0, 350, 382, 385, 445, 0,
241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
242 /* 0x02 - 640x400@85Hz */
243 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
244 736, 832, 0, 400, 401, 404, 445, 0,
245 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
246 /* 0x03 - 720x400@85Hz */
247 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
248 828, 936, 0, 400, 401, 404, 446, 0,
249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
250 /* 0x04 - 640x480@60Hz */
251 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
252 752, 800, 0, 480, 490, 492, 525, 0,
253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
254 /* 0x05 - 640x480@72Hz */
255 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
256 704, 832, 0, 480, 489, 492, 520, 0,
257 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
258 /* 0x06 - 640x480@75Hz */
259 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
260 720, 840, 0, 480, 481, 484, 500, 0,
261 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
262 /* 0x07 - 640x480@85Hz */
263 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
264 752, 832, 0, 480, 481, 484, 509, 0,
265 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
266 /* 0x08 - 800x600@56Hz */
267 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
268 896, 1024, 0, 600, 601, 603, 625, 0,
269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
270 /* 0x09 - 800x600@60Hz */
271 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
272 968, 1056, 0, 600, 601, 605, 628, 0,
273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
274 /* 0x0a - 800x600@72Hz */
275 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
276 976, 1040, 0, 600, 637, 643, 666, 0,
277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
278 /* 0x0b - 800x600@75Hz */
279 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
280 896, 1056, 0, 600, 601, 604, 625, 0,
281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
282 /* 0x0c - 800x600@85Hz */
283 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
284 896, 1048, 0, 600, 601, 604, 631, 0,
285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
286 /* 0x0d - 800x600@120Hz RB */
287 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
288 880, 960, 0, 600, 603, 607, 636, 0,
289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
290 /* 0x0e - 848x480@60Hz */
291 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
292 976, 1088, 0, 480, 486, 494, 517, 0,
293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
294 /* 0x0f - 1024x768@43Hz, interlace */
295 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
296 1208, 1264, 0, 768, 768, 776, 817, 0,
297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
298 DRM_MODE_FLAG_INTERLACE) },
299 /* 0x10 - 1024x768@60Hz */
300 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
301 1184, 1344, 0, 768, 771, 777, 806, 0,
302 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
303 /* 0x11 - 1024x768@70Hz */
304 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
305 1184, 1328, 0, 768, 771, 777, 806, 0,
306 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
307 /* 0x12 - 1024x768@75Hz */
308 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
309 1136, 1312, 0, 768, 769, 772, 800, 0,
310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
311 /* 0x13 - 1024x768@85Hz */
312 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
313 1168, 1376, 0, 768, 769, 772, 808, 0,
314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
315 /* 0x14 - 1024x768@120Hz RB */
316 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
317 1104, 1184, 0, 768, 771, 775, 813, 0,
318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
319 /* 0x15 - 1152x864@75Hz */
320 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
321 1344, 1600, 0, 864, 865, 868, 900, 0,
322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
323 /* 0x55 - 1280x720@60Hz */
324 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
325 1430, 1650, 0, 720, 725, 730, 750, 0,
326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
327 /* 0x16 - 1280x768@60Hz RB */
328 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
329 1360, 1440, 0, 768, 771, 778, 790, 0,
330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
331 /* 0x17 - 1280x768@60Hz */
332 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
333 1472, 1664, 0, 768, 771, 778, 798, 0,
334 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
335 /* 0x18 - 1280x768@75Hz */
336 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
337 1488, 1696, 0, 768, 771, 778, 805, 0,
338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
339 /* 0x19 - 1280x768@85Hz */
340 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
341 1496, 1712, 0, 768, 771, 778, 809, 0,
342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
343 /* 0x1a - 1280x768@120Hz RB */
344 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
345 1360, 1440, 0, 768, 771, 778, 813, 0,
346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
347 /* 0x1b - 1280x800@60Hz RB */
348 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
349 1360, 1440, 0, 800, 803, 809, 823, 0,
350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
351 /* 0x1c - 1280x800@60Hz */
352 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
353 1480, 1680, 0, 800, 803, 809, 831, 0,
354 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
355 /* 0x1d - 1280x800@75Hz */
356 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
357 1488, 1696, 0, 800, 803, 809, 838, 0,
358 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
359 /* 0x1e - 1280x800@85Hz */
360 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
361 1496, 1712, 0, 800, 803, 809, 843, 0,
362 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
363 /* 0x1f - 1280x800@120Hz RB */
364 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
365 1360, 1440, 0, 800, 803, 809, 847, 0,
366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
367 /* 0x20 - 1280x960@60Hz */
368 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
369 1488, 1800, 0, 960, 961, 964, 1000, 0,
370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
371 /* 0x21 - 1280x960@85Hz */
372 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
373 1504, 1728, 0, 960, 961, 964, 1011, 0,
374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
375 /* 0x22 - 1280x960@120Hz RB */
376 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
377 1360, 1440, 0, 960, 963, 967, 1017, 0,
378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
379 /* 0x23 - 1280x1024@60Hz */
380 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
381 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
383 /* 0x24 - 1280x1024@75Hz */
384 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
385 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
387 /* 0x25 - 1280x1024@85Hz */
388 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
389 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
391 /* 0x26 - 1280x1024@120Hz RB */
392 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
393 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
395 /* 0x27 - 1360x768@60Hz */
396 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
397 1536, 1792, 0, 768, 771, 777, 795, 0,
398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
399 /* 0x28 - 1360x768@120Hz RB */
400 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
401 1440, 1520, 0, 768, 771, 776, 813, 0,
402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
403 /* 0x51 - 1366x768@60Hz */
404 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
405 1579, 1792, 0, 768, 771, 774, 798, 0,
406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
407 /* 0x56 - 1366x768@60Hz */
408 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
409 1436, 1500, 0, 768, 769, 772, 800, 0,
410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
411 /* 0x29 - 1400x1050@60Hz RB */
412 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
413 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
415 /* 0x2a - 1400x1050@60Hz */
416 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
417 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
418 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
419 /* 0x2b - 1400x1050@75Hz */
420 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
421 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
422 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
423 /* 0x2c - 1400x1050@85Hz */
424 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
425 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
427 /* 0x2d - 1400x1050@120Hz RB */
428 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
429 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
431 /* 0x2e - 1440x900@60Hz RB */
432 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
433 1520, 1600, 0, 900, 903, 909, 926, 0,
434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
435 /* 0x2f - 1440x900@60Hz */
436 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
437 1672, 1904, 0, 900, 903, 909, 934, 0,
438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
439 /* 0x30 - 1440x900@75Hz */
440 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
441 1688, 1936, 0, 900, 903, 909, 942, 0,
442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
443 /* 0x31 - 1440x900@85Hz */
444 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
445 1696, 1952, 0, 900, 903, 909, 948, 0,
446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
447 /* 0x32 - 1440x900@120Hz RB */
448 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
449 1520, 1600, 0, 900, 903, 909, 953, 0,
450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
451 /* 0x53 - 1600x900@60Hz */
452 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
453 1704, 1800, 0, 900, 901, 904, 1000, 0,
454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
455 /* 0x33 - 1600x1200@60Hz */
456 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
457 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
459 /* 0x34 - 1600x1200@65Hz */
460 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
461 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
463 /* 0x35 - 1600x1200@70Hz */
464 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
465 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
467 /* 0x36 - 1600x1200@75Hz */
468 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
469 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
471 /* 0x37 - 1600x1200@85Hz */
472 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
473 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
475 /* 0x38 - 1600x1200@120Hz RB */
476 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
477 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
479 /* 0x39 - 1680x1050@60Hz RB */
480 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
481 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
483 /* 0x3a - 1680x1050@60Hz */
484 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
485 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
486 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
487 /* 0x3b - 1680x1050@75Hz */
488 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
489 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
491 /* 0x3c - 1680x1050@85Hz */
492 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
493 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
495 /* 0x3d - 1680x1050@120Hz RB */
496 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
497 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
499 /* 0x3e - 1792x1344@60Hz */
500 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
501 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
502 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
503 /* 0x3f - 1792x1344@75Hz */
504 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
505 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
506 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
507 /* 0x40 - 1792x1344@120Hz RB */
508 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
509 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
511 /* 0x41 - 1856x1392@60Hz */
512 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
513 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
514 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
515 /* 0x42 - 1856x1392@75Hz */
516 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
517 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
518 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
519 /* 0x43 - 1856x1392@120Hz RB */
520 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
521 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
523 /* 0x52 - 1920x1080@60Hz */
524 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
525 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
526 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
527 /* 0x44 - 1920x1200@60Hz RB */
528 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
529 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
531 /* 0x45 - 1920x1200@60Hz */
532 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
533 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
535 /* 0x46 - 1920x1200@75Hz */
536 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
537 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
538 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
539 /* 0x47 - 1920x1200@85Hz */
540 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
541 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
543 /* 0x48 - 1920x1200@120Hz RB */
544 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
545 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
547 /* 0x49 - 1920x1440@60Hz */
548 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
549 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
550 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
551 /* 0x4a - 1920x1440@75Hz */
552 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
553 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
555 /* 0x4b - 1920x1440@120Hz RB */
556 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
557 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
558 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
559 /* 0x54 - 2048x1152@60Hz */
560 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
561 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
563 /* 0x4c - 2560x1600@60Hz RB */
564 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
565 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
567 /* 0x4d - 2560x1600@60Hz */
568 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
569 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
570 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
571 /* 0x4e - 2560x1600@75Hz */
572 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
573 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
574 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
575 /* 0x4f - 2560x1600@85Hz */
576 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
577 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
578 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
579 /* 0x50 - 2560x1600@120Hz RB */
580 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
581 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
583 /* 0x57 - 4096x2160@60Hz RB */
584 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
585 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
586 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
587 /* 0x58 - 4096x2160@59.94Hz RB */
588 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
589 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
590 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
594 * These more or less come from the DMT spec. The 720x400 modes are
595 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
596 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
597 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
600 * The DMT modes have been fact-checked; the rest are mild guesses.
602 static const struct drm_display_mode edid_est_modes[] = {
603 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
604 968, 1056, 0, 600, 601, 605, 628, 0,
605 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
606 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
607 896, 1024, 0, 600, 601, 603, 625, 0,
608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
609 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
610 720, 840, 0, 480, 481, 484, 500, 0,
611 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
612 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
613 704, 832, 0, 480, 489, 492, 520, 0,
614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
615 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
616 768, 864, 0, 480, 483, 486, 525, 0,
617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
619 752, 800, 0, 480, 490, 492, 525, 0,
620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
621 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
622 846, 900, 0, 400, 421, 423, 449, 0,
623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
624 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
625 846, 900, 0, 400, 412, 414, 449, 0,
626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
627 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
628 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
629 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
630 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
631 1136, 1312, 0, 768, 769, 772, 800, 0,
632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
633 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
634 1184, 1328, 0, 768, 771, 777, 806, 0,
635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
636 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
637 1184, 1344, 0, 768, 771, 777, 806, 0,
638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
639 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
640 1208, 1264, 0, 768, 768, 776, 817, 0,
641 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
642 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
643 928, 1152, 0, 624, 625, 628, 667, 0,
644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
645 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
646 896, 1056, 0, 600, 601, 604, 625, 0,
647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
648 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
649 976, 1040, 0, 600, 637, 643, 666, 0,
650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
651 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
652 1344, 1600, 0, 864, 865, 868, 900, 0,
653 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
663 static const struct minimode est3_modes[] = {
671 { 1024, 768, 85, 0 },
672 { 1152, 864, 75, 0 },
674 { 1280, 768, 60, 1 },
675 { 1280, 768, 60, 0 },
676 { 1280, 768, 75, 0 },
677 { 1280, 768, 85, 0 },
678 { 1280, 960, 60, 0 },
679 { 1280, 960, 85, 0 },
680 { 1280, 1024, 60, 0 },
681 { 1280, 1024, 85, 0 },
683 { 1360, 768, 60, 0 },
684 { 1440, 900, 60, 1 },
685 { 1440, 900, 60, 0 },
686 { 1440, 900, 75, 0 },
687 { 1440, 900, 85, 0 },
688 { 1400, 1050, 60, 1 },
689 { 1400, 1050, 60, 0 },
690 { 1400, 1050, 75, 0 },
692 { 1400, 1050, 85, 0 },
693 { 1680, 1050, 60, 1 },
694 { 1680, 1050, 60, 0 },
695 { 1680, 1050, 75, 0 },
696 { 1680, 1050, 85, 0 },
697 { 1600, 1200, 60, 0 },
698 { 1600, 1200, 65, 0 },
699 { 1600, 1200, 70, 0 },
701 { 1600, 1200, 75, 0 },
702 { 1600, 1200, 85, 0 },
703 { 1792, 1344, 60, 0 },
704 { 1792, 1344, 75, 0 },
705 { 1856, 1392, 60, 0 },
706 { 1856, 1392, 75, 0 },
707 { 1920, 1200, 60, 1 },
708 { 1920, 1200, 60, 0 },
710 { 1920, 1200, 75, 0 },
711 { 1920, 1200, 85, 0 },
712 { 1920, 1440, 60, 0 },
713 { 1920, 1440, 75, 0 },
716 static const struct minimode extra_modes[] = {
717 { 1024, 576, 60, 0 },
718 { 1366, 768, 60, 0 },
719 { 1600, 900, 60, 0 },
720 { 1680, 945, 60, 0 },
721 { 1920, 1080, 60, 0 },
722 { 2048, 1152, 60, 0 },
723 { 2048, 1536, 60, 0 },
727 * From CEA/CTA-861 spec.
729 * Do not access directly, instead always use cea_mode_for_vic().
731 static const struct drm_display_mode edid_cea_modes_1[] = {
732 /* 1 - 640x480@60Hz 4:3 */
733 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
734 752, 800, 0, 480, 490, 492, 525, 0,
735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
736 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
737 /* 2 - 720x480@60Hz 4:3 */
738 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
739 798, 858, 0, 480, 489, 495, 525, 0,
740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
741 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
742 /* 3 - 720x480@60Hz 16:9 */
743 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
744 798, 858, 0, 480, 489, 495, 525, 0,
745 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
746 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
747 /* 4 - 1280x720@60Hz 16:9 */
748 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
749 1430, 1650, 0, 720, 725, 730, 750, 0,
750 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
751 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
752 /* 5 - 1920x1080i@60Hz 16:9 */
753 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
754 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
755 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
756 DRM_MODE_FLAG_INTERLACE),
757 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
758 /* 6 - 720(1440)x480i@60Hz 4:3 */
759 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
760 801, 858, 0, 480, 488, 494, 525, 0,
761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
762 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
763 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
764 /* 7 - 720(1440)x480i@60Hz 16:9 */
765 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
766 801, 858, 0, 480, 488, 494, 525, 0,
767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
768 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
770 /* 8 - 720(1440)x240@60Hz 4:3 */
771 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
772 801, 858, 0, 240, 244, 247, 262, 0,
773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
774 DRM_MODE_FLAG_DBLCLK),
775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
776 /* 9 - 720(1440)x240@60Hz 16:9 */
777 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
778 801, 858, 0, 240, 244, 247, 262, 0,
779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
780 DRM_MODE_FLAG_DBLCLK),
781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
782 /* 10 - 2880x480i@60Hz 4:3 */
783 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
784 3204, 3432, 0, 480, 488, 494, 525, 0,
785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
786 DRM_MODE_FLAG_INTERLACE),
787 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
788 /* 11 - 2880x480i@60Hz 16:9 */
789 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
790 3204, 3432, 0, 480, 488, 494, 525, 0,
791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
792 DRM_MODE_FLAG_INTERLACE),
793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
794 /* 12 - 2880x240@60Hz 4:3 */
795 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
796 3204, 3432, 0, 240, 244, 247, 262, 0,
797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
798 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
799 /* 13 - 2880x240@60Hz 16:9 */
800 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
801 3204, 3432, 0, 240, 244, 247, 262, 0,
802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
803 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
804 /* 14 - 1440x480@60Hz 4:3 */
805 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
806 1596, 1716, 0, 480, 489, 495, 525, 0,
807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
808 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
809 /* 15 - 1440x480@60Hz 16:9 */
810 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
811 1596, 1716, 0, 480, 489, 495, 525, 0,
812 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
813 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
814 /* 16 - 1920x1080@60Hz 16:9 */
815 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
816 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
818 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
819 /* 17 - 720x576@50Hz 4:3 */
820 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
821 796, 864, 0, 576, 581, 586, 625, 0,
822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
823 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
824 /* 18 - 720x576@50Hz 16:9 */
825 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
826 796, 864, 0, 576, 581, 586, 625, 0,
827 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
829 /* 19 - 1280x720@50Hz 16:9 */
830 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
831 1760, 1980, 0, 720, 725, 730, 750, 0,
832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
833 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
834 /* 20 - 1920x1080i@50Hz 16:9 */
835 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
836 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
838 DRM_MODE_FLAG_INTERLACE),
839 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
840 /* 21 - 720(1440)x576i@50Hz 4:3 */
841 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
842 795, 864, 0, 576, 580, 586, 625, 0,
843 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
844 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
845 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
846 /* 22 - 720(1440)x576i@50Hz 16:9 */
847 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
848 795, 864, 0, 576, 580, 586, 625, 0,
849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
850 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
852 /* 23 - 720(1440)x288@50Hz 4:3 */
853 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
854 795, 864, 0, 288, 290, 293, 312, 0,
855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
856 DRM_MODE_FLAG_DBLCLK),
857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
858 /* 24 - 720(1440)x288@50Hz 16:9 */
859 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
860 795, 864, 0, 288, 290, 293, 312, 0,
861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
862 DRM_MODE_FLAG_DBLCLK),
863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
864 /* 25 - 2880x576i@50Hz 4:3 */
865 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
866 3180, 3456, 0, 576, 580, 586, 625, 0,
867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
868 DRM_MODE_FLAG_INTERLACE),
869 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
870 /* 26 - 2880x576i@50Hz 16:9 */
871 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
872 3180, 3456, 0, 576, 580, 586, 625, 0,
873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
874 DRM_MODE_FLAG_INTERLACE),
875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
876 /* 27 - 2880x288@50Hz 4:3 */
877 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
878 3180, 3456, 0, 288, 290, 293, 312, 0,
879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
880 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
881 /* 28 - 2880x288@50Hz 16:9 */
882 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
883 3180, 3456, 0, 288, 290, 293, 312, 0,
884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
885 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
886 /* 29 - 1440x576@50Hz 4:3 */
887 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
888 1592, 1728, 0, 576, 581, 586, 625, 0,
889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
890 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
891 /* 30 - 1440x576@50Hz 16:9 */
892 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
893 1592, 1728, 0, 576, 581, 586, 625, 0,
894 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
895 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
896 /* 31 - 1920x1080@50Hz 16:9 */
897 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
898 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
900 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
901 /* 32 - 1920x1080@24Hz 16:9 */
902 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
903 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
905 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
906 /* 33 - 1920x1080@25Hz 16:9 */
907 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
908 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
910 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
911 /* 34 - 1920x1080@30Hz 16:9 */
912 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
913 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
914 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
915 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
916 /* 35 - 2880x480@60Hz 4:3 */
917 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
918 3192, 3432, 0, 480, 489, 495, 525, 0,
919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
920 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
921 /* 36 - 2880x480@60Hz 16:9 */
922 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
923 3192, 3432, 0, 480, 489, 495, 525, 0,
924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
925 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
926 /* 37 - 2880x576@50Hz 4:3 */
927 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
928 3184, 3456, 0, 576, 581, 586, 625, 0,
929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
930 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
931 /* 38 - 2880x576@50Hz 16:9 */
932 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
933 3184, 3456, 0, 576, 581, 586, 625, 0,
934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
935 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
936 /* 39 - 1920x1080i@50Hz 16:9 */
937 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
938 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
939 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
940 DRM_MODE_FLAG_INTERLACE),
941 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
942 /* 40 - 1920x1080i@100Hz 16:9 */
943 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
944 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
945 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
946 DRM_MODE_FLAG_INTERLACE),
947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
948 /* 41 - 1280x720@100Hz 16:9 */
949 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
950 1760, 1980, 0, 720, 725, 730, 750, 0,
951 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
952 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
953 /* 42 - 720x576@100Hz 4:3 */
954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
955 796, 864, 0, 576, 581, 586, 625, 0,
956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
957 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
958 /* 43 - 720x576@100Hz 16:9 */
959 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
960 796, 864, 0, 576, 581, 586, 625, 0,
961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
962 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
963 /* 44 - 720(1440)x576i@100Hz 4:3 */
964 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
965 795, 864, 0, 576, 580, 586, 625, 0,
966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
967 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
968 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
969 /* 45 - 720(1440)x576i@100Hz 16:9 */
970 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
971 795, 864, 0, 576, 580, 586, 625, 0,
972 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
973 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
974 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
975 /* 46 - 1920x1080i@120Hz 16:9 */
976 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
977 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
978 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
979 DRM_MODE_FLAG_INTERLACE),
980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
981 /* 47 - 1280x720@120Hz 16:9 */
982 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
983 1430, 1650, 0, 720, 725, 730, 750, 0,
984 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
986 /* 48 - 720x480@120Hz 4:3 */
987 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
988 798, 858, 0, 480, 489, 495, 525, 0,
989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
990 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
991 /* 49 - 720x480@120Hz 16:9 */
992 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
993 798, 858, 0, 480, 489, 495, 525, 0,
994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
995 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
996 /* 50 - 720(1440)x480i@120Hz 4:3 */
997 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
998 801, 858, 0, 480, 488, 494, 525, 0,
999 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1000 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1001 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1002 /* 51 - 720(1440)x480i@120Hz 16:9 */
1003 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1004 801, 858, 0, 480, 488, 494, 525, 0,
1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1006 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1008 /* 52 - 720x576@200Hz 4:3 */
1009 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1010 796, 864, 0, 576, 581, 586, 625, 0,
1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1012 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1013 /* 53 - 720x576@200Hz 16:9 */
1014 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1015 796, 864, 0, 576, 581, 586, 625, 0,
1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1017 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1018 /* 54 - 720(1440)x576i@200Hz 4:3 */
1019 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1020 795, 864, 0, 576, 580, 586, 625, 0,
1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1022 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1023 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1024 /* 55 - 720(1440)x576i@200Hz 16:9 */
1025 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1026 795, 864, 0, 576, 580, 586, 625, 0,
1027 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1028 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1030 /* 56 - 720x480@240Hz 4:3 */
1031 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1032 798, 858, 0, 480, 489, 495, 525, 0,
1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1034 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1035 /* 57 - 720x480@240Hz 16:9 */
1036 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1037 798, 858, 0, 480, 489, 495, 525, 0,
1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1039 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1040 /* 58 - 720(1440)x480i@240Hz 4:3 */
1041 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1042 801, 858, 0, 480, 488, 494, 525, 0,
1043 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1044 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1045 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1046 /* 59 - 720(1440)x480i@240Hz 16:9 */
1047 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1048 801, 858, 0, 480, 488, 494, 525, 0,
1049 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1050 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1052 /* 60 - 1280x720@24Hz 16:9 */
1053 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1054 3080, 3300, 0, 720, 725, 730, 750, 0,
1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1056 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1057 /* 61 - 1280x720@25Hz 16:9 */
1058 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1059 3740, 3960, 0, 720, 725, 730, 750, 0,
1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1061 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1062 /* 62 - 1280x720@30Hz 16:9 */
1063 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1064 3080, 3300, 0, 720, 725, 730, 750, 0,
1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1066 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1067 /* 63 - 1920x1080@120Hz 16:9 */
1068 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1069 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1071 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1072 /* 64 - 1920x1080@100Hz 16:9 */
1073 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1074 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1076 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1077 /* 65 - 1280x720@24Hz 64:27 */
1078 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1079 3080, 3300, 0, 720, 725, 730, 750, 0,
1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1081 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1082 /* 66 - 1280x720@25Hz 64:27 */
1083 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1084 3740, 3960, 0, 720, 725, 730, 750, 0,
1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1086 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1087 /* 67 - 1280x720@30Hz 64:27 */
1088 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1089 3080, 3300, 0, 720, 725, 730, 750, 0,
1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1091 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1092 /* 68 - 1280x720@50Hz 64:27 */
1093 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1094 1760, 1980, 0, 720, 725, 730, 750, 0,
1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1096 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1097 /* 69 - 1280x720@60Hz 64:27 */
1098 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1099 1430, 1650, 0, 720, 725, 730, 750, 0,
1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1101 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1102 /* 70 - 1280x720@100Hz 64:27 */
1103 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1104 1760, 1980, 0, 720, 725, 730, 750, 0,
1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1106 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1107 /* 71 - 1280x720@120Hz 64:27 */
1108 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1109 1430, 1650, 0, 720, 725, 730, 750, 0,
1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1111 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1112 /* 72 - 1920x1080@24Hz 64:27 */
1113 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1114 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1116 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1117 /* 73 - 1920x1080@25Hz 64:27 */
1118 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1119 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1121 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1122 /* 74 - 1920x1080@30Hz 64:27 */
1123 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1124 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1126 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1127 /* 75 - 1920x1080@50Hz 64:27 */
1128 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1129 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1131 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1132 /* 76 - 1920x1080@60Hz 64:27 */
1133 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1134 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1136 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1137 /* 77 - 1920x1080@100Hz 64:27 */
1138 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1139 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1141 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1142 /* 78 - 1920x1080@120Hz 64:27 */
1143 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1144 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1146 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1147 /* 79 - 1680x720@24Hz 64:27 */
1148 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1149 3080, 3300, 0, 720, 725, 730, 750, 0,
1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1151 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1152 /* 80 - 1680x720@25Hz 64:27 */
1153 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1154 2948, 3168, 0, 720, 725, 730, 750, 0,
1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1156 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1157 /* 81 - 1680x720@30Hz 64:27 */
1158 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1159 2420, 2640, 0, 720, 725, 730, 750, 0,
1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1161 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1162 /* 82 - 1680x720@50Hz 64:27 */
1163 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1164 1980, 2200, 0, 720, 725, 730, 750, 0,
1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1166 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1167 /* 83 - 1680x720@60Hz 64:27 */
1168 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1169 1980, 2200, 0, 720, 725, 730, 750, 0,
1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1171 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1172 /* 84 - 1680x720@100Hz 64:27 */
1173 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1174 1780, 2000, 0, 720, 725, 730, 825, 0,
1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1176 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1177 /* 85 - 1680x720@120Hz 64:27 */
1178 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1179 1780, 2000, 0, 720, 725, 730, 825, 0,
1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1181 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1182 /* 86 - 2560x1080@24Hz 64:27 */
1183 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1184 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1186 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1187 /* 87 - 2560x1080@25Hz 64:27 */
1188 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1189 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1191 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1192 /* 88 - 2560x1080@30Hz 64:27 */
1193 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1194 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1196 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1197 /* 89 - 2560x1080@50Hz 64:27 */
1198 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1199 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1201 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1202 /* 90 - 2560x1080@60Hz 64:27 */
1203 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1204 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1206 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1207 /* 91 - 2560x1080@100Hz 64:27 */
1208 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1209 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1211 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1212 /* 92 - 2560x1080@120Hz 64:27 */
1213 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1214 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1216 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1217 /* 93 - 3840x2160@24Hz 16:9 */
1218 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1219 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1221 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1222 /* 94 - 3840x2160@25Hz 16:9 */
1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1224 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1226 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1227 /* 95 - 3840x2160@30Hz 16:9 */
1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1229 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1231 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1232 /* 96 - 3840x2160@50Hz 16:9 */
1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1234 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1236 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1237 /* 97 - 3840x2160@60Hz 16:9 */
1238 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1239 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1241 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1242 /* 98 - 4096x2160@24Hz 256:135 */
1243 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1244 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1246 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1247 /* 99 - 4096x2160@25Hz 256:135 */
1248 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1249 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1251 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1252 /* 100 - 4096x2160@30Hz 256:135 */
1253 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1254 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1256 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1257 /* 101 - 4096x2160@50Hz 256:135 */
1258 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1259 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1261 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1262 /* 102 - 4096x2160@60Hz 256:135 */
1263 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1264 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1266 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1267 /* 103 - 3840x2160@24Hz 64:27 */
1268 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1269 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1271 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1272 /* 104 - 3840x2160@25Hz 64:27 */
1273 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1274 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1276 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1277 /* 105 - 3840x2160@30Hz 64:27 */
1278 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1279 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1281 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1282 /* 106 - 3840x2160@50Hz 64:27 */
1283 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1284 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1286 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1287 /* 107 - 3840x2160@60Hz 64:27 */
1288 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1289 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1291 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1292 /* 108 - 1280x720@48Hz 16:9 */
1293 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1294 2280, 2500, 0, 720, 725, 730, 750, 0,
1295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1296 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1297 /* 109 - 1280x720@48Hz 64:27 */
1298 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1299 2280, 2500, 0, 720, 725, 730, 750, 0,
1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1301 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1302 /* 110 - 1680x720@48Hz 64:27 */
1303 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1304 2530, 2750, 0, 720, 725, 730, 750, 0,
1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1306 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1307 /* 111 - 1920x1080@48Hz 16:9 */
1308 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1309 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1311 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1312 /* 112 - 1920x1080@48Hz 64:27 */
1313 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1314 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1316 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1317 /* 113 - 2560x1080@48Hz 64:27 */
1318 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1319 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1321 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1322 /* 114 - 3840x2160@48Hz 16:9 */
1323 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1324 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1326 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1327 /* 115 - 4096x2160@48Hz 256:135 */
1328 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1329 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1331 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1332 /* 116 - 3840x2160@48Hz 64:27 */
1333 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1334 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1336 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1337 /* 117 - 3840x2160@100Hz 16:9 */
1338 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1339 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1341 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1342 /* 118 - 3840x2160@120Hz 16:9 */
1343 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1344 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1346 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1347 /* 119 - 3840x2160@100Hz 64:27 */
1348 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1349 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1351 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1352 /* 120 - 3840x2160@120Hz 64:27 */
1353 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1354 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1356 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1357 /* 121 - 5120x2160@24Hz 64:27 */
1358 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1359 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1361 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1362 /* 122 - 5120x2160@25Hz 64:27 */
1363 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1364 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1366 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1367 /* 123 - 5120x2160@30Hz 64:27 */
1368 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1369 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1371 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1372 /* 124 - 5120x2160@48Hz 64:27 */
1373 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1374 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1376 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1377 /* 125 - 5120x2160@50Hz 64:27 */
1378 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1379 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1381 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1382 /* 126 - 5120x2160@60Hz 64:27 */
1383 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1384 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1386 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1387 /* 127 - 5120x2160@100Hz 64:27 */
1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1389 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1391 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1395 * From CEA/CTA-861 spec.
1397 * Do not access directly, instead always use cea_mode_for_vic().
1399 static const struct drm_display_mode edid_cea_modes_193[] = {
1400 /* 193 - 5120x2160@120Hz 64:27 */
1401 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1402 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1405 /* 194 - 7680x4320@24Hz 16:9 */
1406 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1407 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1410 /* 195 - 7680x4320@25Hz 16:9 */
1411 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1412 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1414 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1415 /* 196 - 7680x4320@30Hz 16:9 */
1416 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1417 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1419 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1420 /* 197 - 7680x4320@48Hz 16:9 */
1421 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1422 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1424 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1425 /* 198 - 7680x4320@50Hz 16:9 */
1426 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1427 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1429 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1430 /* 199 - 7680x4320@60Hz 16:9 */
1431 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1432 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1434 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1435 /* 200 - 7680x4320@100Hz 16:9 */
1436 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1437 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1439 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1440 /* 201 - 7680x4320@120Hz 16:9 */
1441 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1442 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1444 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1445 /* 202 - 7680x4320@24Hz 64:27 */
1446 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1447 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1449 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1450 /* 203 - 7680x4320@25Hz 64:27 */
1451 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1452 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1454 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1455 /* 204 - 7680x4320@30Hz 64:27 */
1456 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1457 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1459 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1460 /* 205 - 7680x4320@48Hz 64:27 */
1461 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1462 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1464 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1465 /* 206 - 7680x4320@50Hz 64:27 */
1466 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1467 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1469 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1470 /* 207 - 7680x4320@60Hz 64:27 */
1471 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1472 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1474 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1475 /* 208 - 7680x4320@100Hz 64:27 */
1476 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1477 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1479 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1480 /* 209 - 7680x4320@120Hz 64:27 */
1481 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1482 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1484 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1485 /* 210 - 10240x4320@24Hz 64:27 */
1486 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1487 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1489 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1490 /* 211 - 10240x4320@25Hz 64:27 */
1491 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1492 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1494 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1495 /* 212 - 10240x4320@30Hz 64:27 */
1496 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1497 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1499 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1500 /* 213 - 10240x4320@48Hz 64:27 */
1501 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1502 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1504 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1505 /* 214 - 10240x4320@50Hz 64:27 */
1506 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1507 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1509 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1510 /* 215 - 10240x4320@60Hz 64:27 */
1511 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1512 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1514 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1515 /* 216 - 10240x4320@100Hz 64:27 */
1516 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1517 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1519 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1520 /* 217 - 10240x4320@120Hz 64:27 */
1521 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1522 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1524 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1525 /* 218 - 4096x2160@100Hz 256:135 */
1526 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1527 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1529 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1530 /* 219 - 4096x2160@120Hz 256:135 */
1531 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1532 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1534 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1538 * HDMI 1.4 4k modes. Index using the VIC.
1540 static const struct drm_display_mode edid_4k_modes[] = {
1541 /* 0 - dummy, VICs start at 1 */
1543 /* 1 - 3840x2160@30Hz */
1544 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1545 3840, 4016, 4104, 4400, 0,
1546 2160, 2168, 2178, 2250, 0,
1547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1548 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1549 /* 2 - 3840x2160@25Hz */
1550 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1551 3840, 4896, 4984, 5280, 0,
1552 2160, 2168, 2178, 2250, 0,
1553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1554 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1555 /* 3 - 3840x2160@24Hz */
1556 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1557 3840, 5116, 5204, 5500, 0,
1558 2160, 2168, 2178, 2250, 0,
1559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1560 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1561 /* 4 - 4096x2160@24Hz (SMPTE) */
1562 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1563 4096, 5116, 5204, 5500, 0,
1564 2160, 2168, 2178, 2250, 0,
1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1566 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1569 /*** DDC fetch and block validation ***/
1571 static const u8 edid_header[] = {
1572 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1576 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1577 * @raw_edid: pointer to raw base EDID block
1579 * Sanity check the header of the base EDID block.
1581 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1583 int drm_edid_header_is_valid(const u8 *raw_edid)
1587 for (i = 0; i < sizeof(edid_header); i++)
1588 if (raw_edid[i] == edid_header[i])
1593 EXPORT_SYMBOL(drm_edid_header_is_valid);
1595 static int edid_fixup __read_mostly = 6;
1596 module_param_named(edid_fixup, edid_fixup, int, 0400);
1597 MODULE_PARM_DESC(edid_fixup,
1598 "Minimum number of valid EDID header bytes (0-8, default 6)");
1600 static int drm_edid_block_checksum(const u8 *raw_edid)
1603 u8 csum = 0, crc = 0;
1605 for (i = 0; i < EDID_LENGTH - 1; i++)
1606 csum += raw_edid[i];
1613 static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum)
1615 if (raw_edid[EDID_LENGTH - 1] != real_checksum)
1621 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1623 if (memchr_inv(in_edid, 0, length))
1630 * drm_edid_are_equal - compare two edid blobs.
1631 * @edid1: pointer to first blob
1632 * @edid2: pointer to second blob
1633 * This helper can be used during probing to determine if
1636 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1638 int edid1_len, edid2_len;
1639 bool edid1_present = edid1 != NULL;
1640 bool edid2_present = edid2 != NULL;
1642 if (edid1_present != edid2_present)
1646 edid1_len = EDID_LENGTH * (1 + edid1->extensions);
1647 edid2_len = EDID_LENGTH * (1 + edid2->extensions);
1649 if (edid1_len != edid2_len)
1652 if (memcmp(edid1, edid2, edid1_len))
1658 EXPORT_SYMBOL(drm_edid_are_equal);
1661 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1662 * @raw_edid: pointer to raw EDID block
1663 * @block: type of block to validate (0 for base, extension otherwise)
1664 * @print_bad_edid: if true, dump bad EDID blocks to the console
1665 * @edid_corrupt: if true, the header or checksum is invalid
1667 * Validate a base or extension EDID block and optionally dump bad blocks to
1670 * Return: True if the block is valid, false otherwise.
1672 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1676 struct edid *edid = (struct edid *)raw_edid;
1678 if (WARN_ON(!raw_edid))
1681 if (edid_fixup > 8 || edid_fixup < 0)
1685 int score = drm_edid_header_is_valid(raw_edid);
1689 *edid_corrupt = false;
1690 } else if (score >= edid_fixup) {
1691 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1692 * The corrupt flag needs to be set here otherwise, the
1693 * fix-up code here will correct the problem, the
1694 * checksum is correct and the test fails
1697 *edid_corrupt = true;
1698 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1699 memcpy(raw_edid, edid_header, sizeof(edid_header));
1702 *edid_corrupt = true;
1707 csum = drm_edid_block_checksum(raw_edid);
1708 if (drm_edid_block_checksum_diff(raw_edid, csum)) {
1710 *edid_corrupt = true;
1712 /* allow CEA to slide through, switches mangle this */
1713 if (raw_edid[0] == CEA_EXT) {
1714 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1715 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1718 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1724 /* per-block-type checks */
1725 switch (raw_edid[0]) {
1727 if (edid->version != 1) {
1728 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1732 if (edid->revision > 4)
1733 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1743 if (print_bad_edid) {
1744 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1745 pr_notice("EDID block is all zeroes\n");
1747 pr_notice("Raw EDID:\n");
1748 print_hex_dump(KERN_NOTICE,
1749 " \t", DUMP_PREFIX_NONE, 16, 1,
1750 raw_edid, EDID_LENGTH, false);
1755 EXPORT_SYMBOL(drm_edid_block_valid);
1758 * drm_edid_is_valid - sanity check EDID data
1761 * Sanity-check an entire EDID record (including extensions)
1763 * Return: True if the EDID data is valid, false otherwise.
1765 bool drm_edid_is_valid(struct edid *edid)
1768 u8 *raw = (u8 *)edid;
1773 for (i = 0; i <= edid->extensions; i++)
1774 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1779 EXPORT_SYMBOL(drm_edid_is_valid);
1781 #define DDC_SEGMENT_ADDR 0x30
1783 * drm_do_probe_ddc_edid() - get EDID information via I2C
1784 * @data: I2C device adapter
1785 * @buf: EDID data buffer to be filled
1786 * @block: 128 byte EDID block to start fetching from
1787 * @len: EDID data buffer length to fetch
1789 * Try to fetch EDID information by calling I2C driver functions.
1791 * Return: 0 on success or -1 on failure.
1794 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1796 struct i2c_adapter *adapter = data;
1797 unsigned char start = block * EDID_LENGTH;
1798 unsigned char segment = block >> 1;
1799 unsigned char xfers = segment ? 3 : 2;
1800 int ret, retries = 5;
1803 * The core I2C driver will automatically retry the transfer if the
1804 * adapter reports EAGAIN. However, we find that bit-banging transfers
1805 * are susceptible to errors under a heavily loaded machine and
1806 * generate spurious NAKs and timeouts. Retrying the transfer
1807 * of the individual block a few times seems to overcome this.
1810 struct i2c_msg msgs[] = {
1812 .addr = DDC_SEGMENT_ADDR,
1830 * Avoid sending the segment addr to not upset non-compliant
1833 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1835 if (ret == -ENXIO) {
1836 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1840 } while (ret != xfers && --retries);
1842 return ret == xfers ? 0 : -1;
1845 static void connector_bad_edid(struct drm_connector *connector,
1846 u8 *edid, int num_blocks)
1852 * 0x7e in the EDID is the number of extension blocks. The EDID
1853 * is 1 (base block) + num_ext_blocks big. That means we can think
1854 * of 0x7e in the EDID of the _index_ of the last block in the
1855 * combined chunk of memory.
1857 last_block = edid[0x7e];
1859 /* Calculate real checksum for the last edid extension block data */
1860 if (last_block < num_blocks)
1861 connector->real_edid_checksum =
1862 drm_edid_block_checksum(edid + last_block * EDID_LENGTH);
1864 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
1867 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name);
1868 for (i = 0; i < num_blocks; i++) {
1869 u8 *block = edid + i * EDID_LENGTH;
1872 if (drm_edid_is_zero(block, EDID_LENGTH))
1873 sprintf(prefix, "\t[%02x] ZERO ", i);
1874 else if (!drm_edid_block_valid(block, i, false, NULL))
1875 sprintf(prefix, "\t[%02x] BAD ", i);
1877 sprintf(prefix, "\t[%02x] GOOD ", i);
1879 print_hex_dump(KERN_DEBUG,
1880 prefix, DUMP_PREFIX_NONE, 16, 1,
1881 block, EDID_LENGTH, false);
1885 /* Get override or firmware EDID */
1886 static struct edid *drm_get_override_edid(struct drm_connector *connector)
1888 struct edid *override = NULL;
1890 if (connector->override_edid)
1891 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1894 override = drm_load_edid_firmware(connector);
1896 return IS_ERR(override) ? NULL : override;
1900 * drm_add_override_edid_modes - add modes from override/firmware EDID
1901 * @connector: connector we're probing
1903 * Add modes from the override/firmware EDID, if available. Only to be used from
1904 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1905 * failed during drm_get_edid() and caused the override/firmware EDID to be
1908 * Return: The number of modes added or 0 if we couldn't find any.
1910 int drm_add_override_edid_modes(struct drm_connector *connector)
1912 struct edid *override;
1915 override = drm_get_override_edid(connector);
1917 drm_connector_update_edid_property(connector, override);
1918 num_modes = drm_add_edid_modes(connector, override);
1921 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1922 connector->base.id, connector->name, num_modes);
1927 EXPORT_SYMBOL(drm_add_override_edid_modes);
1929 static struct edid *drm_do_get_edid_base_block(struct drm_connector *connector,
1930 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1934 int *null_edid_counter = connector ? &connector->null_edid_counter : NULL;
1935 bool *edid_corrupt = connector ? &connector->edid_corrupt : NULL;
1939 edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
1943 /* base block fetch */
1944 for (i = 0; i < 4; i++) {
1945 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1947 if (drm_edid_block_valid(edid, 0, false, edid_corrupt))
1949 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1950 if (null_edid_counter)
1951 (*null_edid_counter)++;
1962 connector_bad_edid(connector, edid, 1);
1969 * drm_do_get_edid - get EDID data using a custom EDID block read function
1970 * @connector: connector we're probing
1971 * @get_edid_block: EDID block read function
1972 * @data: private data passed to the block read function
1974 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1975 * exposes a different interface to read EDID blocks this function can be used
1976 * to get EDID data using a custom block read function.
1978 * As in the general case the DDC bus is accessible by the kernel at the I2C
1979 * level, drivers must make all reasonable efforts to expose it as an I2C
1980 * adapter and use drm_get_edid() instead of abusing this function.
1982 * The EDID may be overridden using debugfs override_edid or firmware EDID
1983 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1984 * order. Having either of them bypasses actual EDID reads.
1986 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1988 struct edid *drm_do_get_edid(struct drm_connector *connector,
1989 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1993 int i, j = 0, valid_extensions = 0;
1995 struct edid *override;
1997 override = drm_get_override_edid(connector);
2001 edid = (u8 *)drm_do_get_edid_base_block(connector, get_edid_block, data);
2005 /* if there's no extensions or no connector, we're done */
2006 valid_extensions = edid[0x7e];
2007 if (valid_extensions == 0)
2008 return (struct edid *)edid;
2010 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2015 for (j = 1; j <= edid[0x7e]; j++) {
2016 u8 *block = edid + j * EDID_LENGTH;
2018 for (i = 0; i < 4; i++) {
2019 if (get_edid_block(data, block, j, EDID_LENGTH))
2021 if (drm_edid_block_valid(block, j, false, NULL))
2029 if (valid_extensions != edid[0x7e]) {
2032 connector_bad_edid(connector, edid, edid[0x7e] + 1);
2034 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
2035 edid[0x7e] = valid_extensions;
2037 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
2043 for (i = 0; i <= edid[0x7e]; i++) {
2044 u8 *block = edid + i * EDID_LENGTH;
2046 if (!drm_edid_block_valid(block, i, false, NULL))
2049 memcpy(base, block, EDID_LENGTH);
2050 base += EDID_LENGTH;
2057 return (struct edid *)edid;
2063 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2066 * drm_probe_ddc() - probe DDC presence
2067 * @adapter: I2C adapter to probe
2069 * Return: True on success, false on failure.
2072 drm_probe_ddc(struct i2c_adapter *adapter)
2076 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2078 EXPORT_SYMBOL(drm_probe_ddc);
2081 * drm_get_edid - get EDID data, if available
2082 * @connector: connector we're probing
2083 * @adapter: I2C adapter to use for DDC
2085 * Poke the given I2C channel to grab EDID data if possible. If found,
2086 * attach it to the connector.
2088 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2090 struct edid *drm_get_edid(struct drm_connector *connector,
2091 struct i2c_adapter *adapter)
2095 if (connector->force == DRM_FORCE_OFF)
2098 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2101 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
2102 drm_connector_update_edid_property(connector, edid);
2105 EXPORT_SYMBOL(drm_get_edid);
2107 static u32 edid_extract_panel_id(const struct edid *edid)
2110 * We represent the ID as a 32-bit number so it can easily be compared
2113 * NOTE that we deal with endianness differently for the top half
2114 * of this ID than for the bottom half. The bottom half (the product
2115 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2116 * that's how everyone seems to interpret it. The top half (the mfg_id)
2117 * gets stored as big endian because that makes
2118 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2119 * to write (it's easier to extract the ASCII). It doesn't really
2120 * matter, though, as long as the number here is unique.
2122 return (u32)edid->mfg_id[0] << 24 |
2123 (u32)edid->mfg_id[1] << 16 |
2124 (u32)EDID_PRODUCT_ID(edid);
2128 * drm_edid_get_panel_id - Get a panel's ID through DDC
2129 * @adapter: I2C adapter to use for DDC
2131 * This function reads the first block of the EDID of a panel and (assuming
2132 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2133 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2134 * supposed to be different for each different modem of panel.
2136 * This function is intended to be used during early probing on devices where
2137 * more than one panel might be present. Because of its intended use it must
2138 * assume that the EDID of the panel is correct, at least as far as the ID
2139 * is concerned (in other words, we don't process any overrides here).
2141 * NOTE: it's expected that this function and drm_do_get_edid() will both
2142 * be read the EDID, but there is no caching between them. Since we're only
2143 * reading the first block, hopefully this extra overhead won't be too big.
2145 * Return: A 32-bit ID that should be different for each make/model of panel.
2146 * See the functions drm_edid_encode_panel_id() and
2147 * drm_edid_decode_panel_id() for some details on the structure of this
2151 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2156 edid = drm_do_get_edid_base_block(NULL, drm_do_probe_ddc_edid, adapter);
2159 * There are no manufacturer IDs of 0, so if there is a problem reading
2160 * the EDID then we'll just return 0.
2165 panel_id = edid_extract_panel_id(edid);
2170 EXPORT_SYMBOL(drm_edid_get_panel_id);
2173 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2174 * @connector: connector we're probing
2175 * @adapter: I2C adapter to use for DDC
2177 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2178 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2179 * switch DDC to the GPU which is retrieving EDID.
2181 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2183 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2184 struct i2c_adapter *adapter)
2186 struct drm_device *dev = connector->dev;
2187 struct pci_dev *pdev = to_pci_dev(dev->dev);
2190 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2193 vga_switcheroo_lock_ddc(pdev);
2194 edid = drm_get_edid(connector, adapter);
2195 vga_switcheroo_unlock_ddc(pdev);
2199 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2202 * drm_edid_duplicate - duplicate an EDID and the extensions
2203 * @edid: EDID to duplicate
2205 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2207 struct edid *drm_edid_duplicate(const struct edid *edid)
2209 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2211 EXPORT_SYMBOL(drm_edid_duplicate);
2213 /*** EDID parsing ***/
2216 * edid_get_quirks - return quirk flags for a given EDID
2217 * @edid: EDID to process
2219 * This tells subsequent routines what fixes they need to apply.
2221 static u32 edid_get_quirks(const struct edid *edid)
2223 u32 panel_id = edid_extract_panel_id(edid);
2224 const struct edid_quirk *quirk;
2227 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2228 quirk = &edid_quirk_list[i];
2229 if (quirk->panel_id == panel_id)
2230 return quirk->quirks;
2236 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2237 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2240 * edid_fixup_preferred - set preferred modes based on quirk list
2241 * @connector: has mode list to fix up
2242 * @quirks: quirks list
2244 * Walk the mode list for @connector, clearing the preferred status
2245 * on existing modes and setting it anew for the right mode ala @quirks.
2247 static void edid_fixup_preferred(struct drm_connector *connector,
2250 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2251 int target_refresh = 0;
2252 int cur_vrefresh, preferred_vrefresh;
2254 if (list_empty(&connector->probed_modes))
2257 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2258 target_refresh = 60;
2259 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2260 target_refresh = 75;
2262 preferred_mode = list_first_entry(&connector->probed_modes,
2263 struct drm_display_mode, head);
2265 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2266 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2268 if (cur_mode == preferred_mode)
2271 /* Largest mode is preferred */
2272 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2273 preferred_mode = cur_mode;
2275 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2276 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2277 /* At a given size, try to get closest to target refresh */
2278 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2279 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2280 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2281 preferred_mode = cur_mode;
2285 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2289 mode_is_rb(const struct drm_display_mode *mode)
2291 return (mode->htotal - mode->hdisplay == 160) &&
2292 (mode->hsync_end - mode->hdisplay == 80) &&
2293 (mode->hsync_end - mode->hsync_start == 32) &&
2294 (mode->vsync_start - mode->vdisplay == 3);
2298 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2299 * @dev: Device to duplicate against
2300 * @hsize: Mode width
2301 * @vsize: Mode height
2302 * @fresh: Mode refresh rate
2303 * @rb: Mode reduced-blanking-ness
2305 * Walk the DMT mode list looking for a match for the given parameters.
2307 * Return: A newly allocated copy of the mode, or NULL if not found.
2309 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2310 int hsize, int vsize, int fresh,
2315 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2316 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2318 if (hsize != ptr->hdisplay)
2320 if (vsize != ptr->vdisplay)
2322 if (fresh != drm_mode_vrefresh(ptr))
2324 if (rb != mode_is_rb(ptr))
2327 return drm_mode_duplicate(dev, ptr);
2332 EXPORT_SYMBOL(drm_mode_find_dmt);
2334 static bool is_display_descriptor(const u8 d[18], u8 tag)
2336 return d[0] == 0x00 && d[1] == 0x00 &&
2337 d[2] == 0x00 && d[3] == tag;
2340 static bool is_detailed_timing_descriptor(const u8 d[18])
2342 return d[0] != 0x00 || d[1] != 0x00;
2345 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
2348 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2352 u8 *det_base = ext + d;
2354 if (d < 4 || d > 127)
2358 for (i = 0; i < n; i++)
2359 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2363 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2365 unsigned int i, n = min((int)ext[0x02], 6);
2366 u8 *det_base = ext + 5;
2369 return; /* unknown version */
2371 for (i = 0; i < n; i++)
2372 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2376 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
2379 struct edid *edid = (struct edid *)raw_edid;
2384 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2385 cb(&(edid->detailed_timings[i]), closure);
2387 for (i = 1; i <= raw_edid[0x7e]; i++) {
2388 u8 *ext = raw_edid + (i * EDID_LENGTH);
2392 cea_for_each_detailed_block(ext, cb, closure);
2395 vtb_for_each_detailed_block(ext, cb, closure);
2404 is_rb(struct detailed_timing *t, void *data)
2408 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2412 *(bool *)data = true;
2415 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2417 drm_monitor_supports_rb(struct edid *edid)
2419 if (edid->revision >= 4) {
2422 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2426 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2430 find_gtf2(struct detailed_timing *t, void *data)
2434 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2441 /* Secondary GTF curve kicks in above some break frequency */
2443 drm_gtf2_hbreak(struct edid *edid)
2447 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2448 return r ? (r[12] * 2) : 0;
2452 drm_gtf2_2c(struct edid *edid)
2456 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2457 return r ? r[13] : 0;
2461 drm_gtf2_m(struct edid *edid)
2465 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2466 return r ? (r[15] << 8) + r[14] : 0;
2470 drm_gtf2_k(struct edid *edid)
2474 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2475 return r ? r[16] : 0;
2479 drm_gtf2_2j(struct edid *edid)
2483 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2484 return r ? r[17] : 0;
2488 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2489 * @edid: EDID block to scan
2491 static int standard_timing_level(struct edid *edid)
2493 if (edid->revision >= 2) {
2494 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2496 if (drm_gtf2_hbreak(edid))
2498 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2505 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2506 * monitors fill with ascii space (0x20) instead.
2509 bad_std_timing(u8 a, u8 b)
2511 return (a == 0x00 && b == 0x00) ||
2512 (a == 0x01 && b == 0x01) ||
2513 (a == 0x20 && b == 0x20);
2516 static int drm_mode_hsync(const struct drm_display_mode *mode)
2518 if (mode->htotal <= 0)
2521 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
2525 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2526 * @connector: connector of for the EDID block
2527 * @edid: EDID block to scan
2528 * @t: standard timing params
2530 * Take the standard timing params (in this case width, aspect, and refresh)
2531 * and convert them into a real mode using CVT/GTF/DMT.
2533 static struct drm_display_mode *
2534 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2535 struct std_timing *t)
2537 struct drm_device *dev = connector->dev;
2538 struct drm_display_mode *m, *mode = NULL;
2541 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2542 >> EDID_TIMING_ASPECT_SHIFT;
2543 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2544 >> EDID_TIMING_VFREQ_SHIFT;
2545 int timing_level = standard_timing_level(edid);
2547 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2550 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2551 hsize = t->hsize * 8 + 248;
2552 /* vrefresh_rate = vfreq + 60 */
2553 vrefresh_rate = vfreq + 60;
2554 /* the vdisplay is calculated based on the aspect ratio */
2555 if (aspect_ratio == 0) {
2556 if (edid->revision < 3)
2559 vsize = (hsize * 10) / 16;
2560 } else if (aspect_ratio == 1)
2561 vsize = (hsize * 3) / 4;
2562 else if (aspect_ratio == 2)
2563 vsize = (hsize * 4) / 5;
2565 vsize = (hsize * 9) / 16;
2567 /* HDTV hack, part 1 */
2568 if (vrefresh_rate == 60 &&
2569 ((hsize == 1360 && vsize == 765) ||
2570 (hsize == 1368 && vsize == 769))) {
2576 * If this connector already has a mode for this size and refresh
2577 * rate (because it came from detailed or CVT info), use that
2578 * instead. This way we don't have to guess at interlace or
2581 list_for_each_entry(m, &connector->probed_modes, head)
2582 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2583 drm_mode_vrefresh(m) == vrefresh_rate)
2586 /* HDTV hack, part 2 */
2587 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2588 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2592 mode->hdisplay = 1366;
2593 mode->hsync_start = mode->hsync_start - 1;
2594 mode->hsync_end = mode->hsync_end - 1;
2598 /* check whether it can be found in default mode table */
2599 if (drm_monitor_supports_rb(edid)) {
2600 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2605 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2609 /* okay, generate it */
2610 switch (timing_level) {
2614 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2618 * This is potentially wrong if there's ever a monitor with
2619 * more than one ranges section, each claiming a different
2620 * secondary GTF curve. Please don't do that.
2622 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2625 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2626 drm_mode_destroy(dev, mode);
2627 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2628 vrefresh_rate, 0, 0,
2636 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2644 * EDID is delightfully ambiguous about how interlaced modes are to be
2645 * encoded. Our internal representation is of frame height, but some
2646 * HDTV detailed timings are encoded as field height.
2648 * The format list here is from CEA, in frame size. Technically we
2649 * should be checking refresh rate too. Whatever.
2652 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2653 struct detailed_pixel_timing *pt)
2656 static const struct {
2658 } cea_interlaced[] = {
2668 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2671 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2672 if ((mode->hdisplay == cea_interlaced[i].w) &&
2673 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2674 mode->vdisplay *= 2;
2675 mode->vsync_start *= 2;
2676 mode->vsync_end *= 2;
2682 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2686 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2687 * @dev: DRM device (needed to create new mode)
2689 * @timing: EDID detailed timing info
2690 * @quirks: quirks to apply
2692 * An EDID detailed timing block contains enough info for us to create and
2693 * return a new struct drm_display_mode.
2695 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2697 struct detailed_timing *timing,
2700 struct drm_display_mode *mode;
2701 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2702 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2703 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2704 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2705 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2706 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2707 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2708 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2709 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2711 /* ignore tiny modes */
2712 if (hactive < 64 || vactive < 64)
2715 if (pt->misc & DRM_EDID_PT_STEREO) {
2716 DRM_DEBUG_KMS("stereo mode not supported\n");
2719 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2720 DRM_DEBUG_KMS("composite sync not supported\n");
2723 /* it is incorrect if hsync/vsync width is zero */
2724 if (!hsync_pulse_width || !vsync_pulse_width) {
2725 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2726 "Wrong Hsync/Vsync pulse width\n");
2730 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2731 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2738 mode = drm_mode_create(dev);
2742 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2743 timing->pixel_clock = cpu_to_le16(1088);
2745 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2747 mode->hdisplay = hactive;
2748 mode->hsync_start = mode->hdisplay + hsync_offset;
2749 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2750 mode->htotal = mode->hdisplay + hblank;
2752 mode->vdisplay = vactive;
2753 mode->vsync_start = mode->vdisplay + vsync_offset;
2754 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2755 mode->vtotal = mode->vdisplay + vblank;
2757 /* Some EDIDs have bogus h/vtotal values */
2758 if (mode->hsync_end > mode->htotal)
2759 mode->htotal = mode->hsync_end + 1;
2760 if (mode->vsync_end > mode->vtotal)
2761 mode->vtotal = mode->vsync_end + 1;
2763 drm_mode_do_interlace_quirk(mode, pt);
2765 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2766 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2769 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2770 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2771 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2772 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2775 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2776 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2778 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2779 mode->width_mm *= 10;
2780 mode->height_mm *= 10;
2783 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2784 mode->width_mm = edid->width_cm * 10;
2785 mode->height_mm = edid->height_cm * 10;
2788 mode->type = DRM_MODE_TYPE_DRIVER;
2789 drm_mode_set_name(mode);
2795 mode_in_hsync_range(const struct drm_display_mode *mode,
2796 struct edid *edid, u8 *t)
2798 int hsync, hmin, hmax;
2801 if (edid->revision >= 4)
2802 hmin += ((t[4] & 0x04) ? 255 : 0);
2804 if (edid->revision >= 4)
2805 hmax += ((t[4] & 0x08) ? 255 : 0);
2806 hsync = drm_mode_hsync(mode);
2808 return (hsync <= hmax && hsync >= hmin);
2812 mode_in_vsync_range(const struct drm_display_mode *mode,
2813 struct edid *edid, u8 *t)
2815 int vsync, vmin, vmax;
2818 if (edid->revision >= 4)
2819 vmin += ((t[4] & 0x01) ? 255 : 0);
2821 if (edid->revision >= 4)
2822 vmax += ((t[4] & 0x02) ? 255 : 0);
2823 vsync = drm_mode_vrefresh(mode);
2825 return (vsync <= vmax && vsync >= vmin);
2829 range_pixel_clock(struct edid *edid, u8 *t)
2832 if (t[9] == 0 || t[9] == 255)
2835 /* 1.4 with CVT support gives us real precision, yay */
2836 if (edid->revision >= 4 && t[10] == 0x04)
2837 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2839 /* 1.3 is pathetic, so fuzz up a bit */
2840 return t[9] * 10000 + 5001;
2844 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2845 struct detailed_timing *timing)
2848 u8 *t = (u8 *)timing;
2850 if (!mode_in_hsync_range(mode, edid, t))
2853 if (!mode_in_vsync_range(mode, edid, t))
2856 if ((max_clock = range_pixel_clock(edid, t)))
2857 if (mode->clock > max_clock)
2860 /* 1.4 max horizontal check */
2861 if (edid->revision >= 4 && t[10] == 0x04)
2862 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2865 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2871 static bool valid_inferred_mode(const struct drm_connector *connector,
2872 const struct drm_display_mode *mode)
2874 const struct drm_display_mode *m;
2877 list_for_each_entry(m, &connector->probed_modes, head) {
2878 if (mode->hdisplay == m->hdisplay &&
2879 mode->vdisplay == m->vdisplay &&
2880 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2881 return false; /* duplicated */
2882 if (mode->hdisplay <= m->hdisplay &&
2883 mode->vdisplay <= m->vdisplay)
2890 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2891 struct detailed_timing *timing)
2894 struct drm_display_mode *newmode;
2895 struct drm_device *dev = connector->dev;
2897 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2898 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2899 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2900 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2902 drm_mode_probed_add(connector, newmode);
2911 /* fix up 1366x768 mode from 1368x768;
2912 * GFT/CVT can't express 1366 width which isn't dividable by 8
2914 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2916 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2917 mode->hdisplay = 1366;
2918 mode->hsync_start--;
2920 drm_mode_set_name(mode);
2925 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2926 struct detailed_timing *timing)
2929 struct drm_display_mode *newmode;
2930 struct drm_device *dev = connector->dev;
2932 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2933 const struct minimode *m = &extra_modes[i];
2935 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2939 drm_mode_fixup_1366x768(newmode);
2940 if (!mode_in_range(newmode, edid, timing) ||
2941 !valid_inferred_mode(connector, newmode)) {
2942 drm_mode_destroy(dev, newmode);
2946 drm_mode_probed_add(connector, newmode);
2954 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2955 struct detailed_timing *timing)
2958 struct drm_display_mode *newmode;
2959 struct drm_device *dev = connector->dev;
2960 bool rb = drm_monitor_supports_rb(edid);
2962 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2963 const struct minimode *m = &extra_modes[i];
2965 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2969 drm_mode_fixup_1366x768(newmode);
2970 if (!mode_in_range(newmode, edid, timing) ||
2971 !valid_inferred_mode(connector, newmode)) {
2972 drm_mode_destroy(dev, newmode);
2976 drm_mode_probed_add(connector, newmode);
2984 do_inferred_modes(struct detailed_timing *timing, void *c)
2986 struct detailed_mode_closure *closure = c;
2987 struct detailed_non_pixel *data = &timing->data.other_data;
2988 struct detailed_data_monitor_range *range = &data->data.range;
2990 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
2993 closure->modes += drm_dmt_modes_for_range(closure->connector,
2997 if (!version_greater(closure->edid, 1, 1))
2998 return; /* GTF not defined yet */
3000 switch (range->flags) {
3001 case 0x02: /* secondary gtf, XXX could do more */
3002 case 0x00: /* default gtf */
3003 closure->modes += drm_gtf_modes_for_range(closure->connector,
3007 case 0x04: /* cvt, only in 1.4+ */
3008 if (!version_greater(closure->edid, 1, 3))
3011 closure->modes += drm_cvt_modes_for_range(closure->connector,
3015 case 0x01: /* just the ranges, no formula */
3022 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
3024 struct detailed_mode_closure closure = {
3025 .connector = connector,
3029 if (version_greater(edid, 1, 0))
3030 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
3033 return closure.modes;
3037 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
3039 int i, j, m, modes = 0;
3040 struct drm_display_mode *mode;
3041 u8 *est = ((u8 *)timing) + 6;
3043 for (i = 0; i < 6; i++) {
3044 for (j = 7; j >= 0; j--) {
3045 m = (i * 8) + (7 - j);
3046 if (m >= ARRAY_SIZE(est3_modes))
3048 if (est[i] & (1 << j)) {
3049 mode = drm_mode_find_dmt(connector->dev,
3055 drm_mode_probed_add(connector, mode);
3066 do_established_modes(struct detailed_timing *timing, void *c)
3068 struct detailed_mode_closure *closure = c;
3070 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS))
3073 closure->modes += drm_est3_modes(closure->connector, timing);
3077 * add_established_modes - get est. modes from EDID and add them
3078 * @connector: connector to add mode(s) to
3079 * @edid: EDID block to scan
3081 * Each EDID block contains a bitmap of the supported "established modes" list
3082 * (defined above). Tease them out and add them to the global modes list.
3085 add_established_modes(struct drm_connector *connector, struct edid *edid)
3087 struct drm_device *dev = connector->dev;
3088 unsigned long est_bits = edid->established_timings.t1 |
3089 (edid->established_timings.t2 << 8) |
3090 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3092 struct detailed_mode_closure closure = {
3093 .connector = connector,
3097 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3098 if (est_bits & (1<<i)) {
3099 struct drm_display_mode *newmode;
3101 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3103 drm_mode_probed_add(connector, newmode);
3109 if (version_greater(edid, 1, 0))
3110 drm_for_each_detailed_block((u8 *)edid,
3111 do_established_modes, &closure);
3113 return modes + closure.modes;
3117 do_standard_modes(struct detailed_timing *timing, void *c)
3119 struct detailed_mode_closure *closure = c;
3120 struct detailed_non_pixel *data = &timing->data.other_data;
3121 struct drm_connector *connector = closure->connector;
3122 struct edid *edid = closure->edid;
3125 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES))
3128 for (i = 0; i < 6; i++) {
3129 struct std_timing *std = &data->data.timings[i];
3130 struct drm_display_mode *newmode;
3132 newmode = drm_mode_std(connector, edid, std);
3134 drm_mode_probed_add(connector, newmode);
3141 * add_standard_modes - get std. modes from EDID and add them
3142 * @connector: connector to add mode(s) to
3143 * @edid: EDID block to scan
3145 * Standard modes can be calculated using the appropriate standard (DMT,
3146 * GTF or CVT. Grab them from @edid and add them to the list.
3149 add_standard_modes(struct drm_connector *connector, struct edid *edid)
3152 struct detailed_mode_closure closure = {
3153 .connector = connector,
3157 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3158 struct drm_display_mode *newmode;
3160 newmode = drm_mode_std(connector, edid,
3161 &edid->standard_timings[i]);
3163 drm_mode_probed_add(connector, newmode);
3168 if (version_greater(edid, 1, 0))
3169 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
3172 /* XXX should also look for standard codes in VTB blocks */
3174 return modes + closure.modes;
3177 static int drm_cvt_modes(struct drm_connector *connector,
3178 struct detailed_timing *timing)
3180 int i, j, modes = 0;
3181 struct drm_display_mode *newmode;
3182 struct drm_device *dev = connector->dev;
3183 struct cvt_timing *cvt;
3184 const int rates[] = { 60, 85, 75, 60, 50 };
3185 const u8 empty[3] = { 0, 0, 0 };
3187 for (i = 0; i < 4; i++) {
3190 cvt = &(timing->data.other_data.data.cvt[i]);
3192 if (!memcmp(cvt->code, empty, 3))
3195 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3196 switch (cvt->code[1] & 0x0c) {
3197 /* default - because compiler doesn't see that we've enumerated all cases */
3200 width = height * 4 / 3;
3203 width = height * 16 / 9;
3206 width = height * 16 / 10;
3209 width = height * 15 / 9;
3213 for (j = 1; j < 5; j++) {
3214 if (cvt->code[2] & (1 << j)) {
3215 newmode = drm_cvt_mode(dev, width, height,
3219 drm_mode_probed_add(connector, newmode);
3230 do_cvt_mode(struct detailed_timing *timing, void *c)
3232 struct detailed_mode_closure *closure = c;
3234 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE))
3237 closure->modes += drm_cvt_modes(closure->connector, timing);
3241 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
3243 struct detailed_mode_closure closure = {
3244 .connector = connector,
3248 if (version_greater(edid, 1, 2))
3249 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
3251 /* XXX should also look for CVT codes in VTB blocks */
3253 return closure.modes;
3256 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3259 do_detailed_mode(struct detailed_timing *timing, void *c)
3261 struct detailed_mode_closure *closure = c;
3262 struct drm_display_mode *newmode;
3264 if (!is_detailed_timing_descriptor((const u8 *)timing))
3267 newmode = drm_mode_detailed(closure->connector->dev,
3268 closure->edid, timing,
3273 if (closure->preferred)
3274 newmode->type |= DRM_MODE_TYPE_PREFERRED;
3277 * Detailed modes are limited to 10kHz pixel clock resolution,
3278 * so fix up anything that looks like CEA/HDMI mode, but the clock
3279 * is just slightly off.
3281 fixup_detailed_cea_mode_clock(newmode);
3283 drm_mode_probed_add(closure->connector, newmode);
3285 closure->preferred = false;
3289 * add_detailed_modes - Add modes from detailed timings
3290 * @connector: attached connector
3291 * @edid: EDID block to scan
3292 * @quirks: quirks to apply
3295 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
3298 struct detailed_mode_closure closure = {
3299 .connector = connector,
3305 if (closure.preferred && !version_greater(edid, 1, 3))
3307 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3309 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
3311 return closure.modes;
3314 #define AUDIO_BLOCK 0x01
3315 #define VIDEO_BLOCK 0x02
3316 #define VENDOR_BLOCK 0x03
3317 #define SPEAKER_BLOCK 0x04
3318 #define HDR_STATIC_METADATA_BLOCK 0x6
3319 #define USE_EXTENDED_TAG 0x07
3320 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
3321 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
3322 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
3323 #define EDID_BASIC_AUDIO (1 << 6)
3324 #define EDID_CEA_YCRCB444 (1 << 5)
3325 #define EDID_CEA_YCRCB422 (1 << 4)
3326 #define EDID_CEA_VCDB_QS (1 << 6)
3329 * Search EDID for CEA extension block.
3331 const u8 *drm_find_edid_extension(const struct edid *edid,
3332 int ext_id, int *ext_index)
3334 const u8 *edid_ext = NULL;
3337 /* No EDID or EDID extensions */
3338 if (edid == NULL || edid->extensions == 0)
3341 /* Find CEA extension */
3342 for (i = *ext_index; i < edid->extensions; i++) {
3343 edid_ext = (const u8 *)edid + EDID_LENGTH * (i + 1);
3344 if (edid_ext[0] == ext_id)
3348 if (i >= edid->extensions)
3356 static const u8 *drm_find_cea_extension(const struct edid *edid)
3358 const struct displayid_block *block;
3359 struct displayid_iter iter;
3363 /* Look for a top level CEA extension block */
3364 /* FIXME: make callers iterate through multiple CEA ext blocks? */
3365 cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index);
3369 /* CEA blocks can also be found embedded in a DisplayID block */
3370 displayid_iter_edid_begin(edid, &iter);
3371 displayid_iter_for_each(block, &iter) {
3372 if (block->tag == DATA_BLOCK_CTA) {
3373 cea = (const u8 *)block;
3377 displayid_iter_end(&iter);
3382 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
3384 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3385 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3387 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3388 return &edid_cea_modes_1[vic - 1];
3389 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3390 return &edid_cea_modes_193[vic - 193];
3394 static u8 cea_num_vics(void)
3396 return 193 + ARRAY_SIZE(edid_cea_modes_193);
3399 static u8 cea_next_vic(u8 vic)
3401 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
3407 * Calculate the alternate clock for the CEA mode
3408 * (60Hz vs. 59.94Hz etc.)
3411 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3413 unsigned int clock = cea_mode->clock;
3415 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
3419 * edid_cea_modes contains the 59.94Hz
3420 * variant for 240 and 480 line modes,
3421 * and the 60Hz variant otherwise.
3423 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
3424 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
3426 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
3432 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3435 * For certain VICs the spec allows the vertical
3436 * front porch to vary by one or two lines.
3438 * cea_modes[] stores the variant with the shortest
3439 * vertical front porch. We can adjust the mode to
3440 * get the other variants by simply increasing the
3441 * vertical front porch length.
3443 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3444 cea_mode_for_vic(9)->vtotal != 262 ||
3445 cea_mode_for_vic(12)->vtotal != 262 ||
3446 cea_mode_for_vic(13)->vtotal != 262 ||
3447 cea_mode_for_vic(23)->vtotal != 312 ||
3448 cea_mode_for_vic(24)->vtotal != 312 ||
3449 cea_mode_for_vic(27)->vtotal != 312 ||
3450 cea_mode_for_vic(28)->vtotal != 312);
3452 if (((vic == 8 || vic == 9 ||
3453 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3454 ((vic == 23 || vic == 24 ||
3455 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3456 mode->vsync_start++;
3466 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3467 unsigned int clock_tolerance)
3469 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3472 if (!to_match->clock)
3475 if (to_match->picture_aspect_ratio)
3476 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3478 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3479 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3480 unsigned int clock1, clock2;
3482 /* Check both 60Hz and 59.94Hz */
3483 clock1 = cea_mode.clock;
3484 clock2 = cea_mode_alternate_clock(&cea_mode);
3486 if (abs(to_match->clock - clock1) > clock_tolerance &&
3487 abs(to_match->clock - clock2) > clock_tolerance)
3491 if (drm_mode_match(to_match, &cea_mode, match_flags))
3493 } while (cea_mode_alternate_timings(vic, &cea_mode));
3500 * drm_match_cea_mode - look for a CEA mode matching given mode
3501 * @to_match: display mode
3503 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3506 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3508 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3511 if (!to_match->clock)
3514 if (to_match->picture_aspect_ratio)
3515 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3517 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3518 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3519 unsigned int clock1, clock2;
3521 /* Check both 60Hz and 59.94Hz */
3522 clock1 = cea_mode.clock;
3523 clock2 = cea_mode_alternate_clock(&cea_mode);
3525 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3526 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3530 if (drm_mode_match(to_match, &cea_mode, match_flags))
3532 } while (cea_mode_alternate_timings(vic, &cea_mode));
3537 EXPORT_SYMBOL(drm_match_cea_mode);
3539 static bool drm_valid_cea_vic(u8 vic)
3541 return cea_mode_for_vic(vic) != NULL;
3544 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3546 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3549 return mode->picture_aspect_ratio;
3551 return HDMI_PICTURE_ASPECT_NONE;
3554 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3556 return edid_4k_modes[video_code].picture_aspect_ratio;
3560 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3564 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3566 return cea_mode_alternate_clock(hdmi_mode);
3569 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3570 unsigned int clock_tolerance)
3572 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3575 if (!to_match->clock)
3578 if (to_match->picture_aspect_ratio)
3579 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3581 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3582 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3583 unsigned int clock1, clock2;
3585 /* Make sure to also match alternate clocks */
3586 clock1 = hdmi_mode->clock;
3587 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3589 if (abs(to_match->clock - clock1) > clock_tolerance &&
3590 abs(to_match->clock - clock2) > clock_tolerance)
3593 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3601 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3602 * @to_match: display mode
3604 * An HDMI mode is one defined in the HDMI vendor specific block.
3606 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3608 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3610 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3613 if (!to_match->clock)
3616 if (to_match->picture_aspect_ratio)
3617 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3619 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3620 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3621 unsigned int clock1, clock2;
3623 /* Make sure to also match alternate clocks */
3624 clock1 = hdmi_mode->clock;
3625 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3627 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3628 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3629 drm_mode_match(to_match, hdmi_mode, match_flags))
3635 static bool drm_valid_hdmi_vic(u8 vic)
3637 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3641 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3643 struct drm_device *dev = connector->dev;
3644 struct drm_display_mode *mode, *tmp;
3648 /* Don't add CEA modes if the CEA extension block is missing */
3649 if (!drm_find_cea_extension(edid))
3653 * Go through all probed modes and create a new mode
3654 * with the alternate clock for certain CEA modes.
3656 list_for_each_entry(mode, &connector->probed_modes, head) {
3657 const struct drm_display_mode *cea_mode = NULL;
3658 struct drm_display_mode *newmode;
3659 u8 vic = drm_match_cea_mode(mode);
3660 unsigned int clock1, clock2;
3662 if (drm_valid_cea_vic(vic)) {
3663 cea_mode = cea_mode_for_vic(vic);
3664 clock2 = cea_mode_alternate_clock(cea_mode);
3666 vic = drm_match_hdmi_mode(mode);
3667 if (drm_valid_hdmi_vic(vic)) {
3668 cea_mode = &edid_4k_modes[vic];
3669 clock2 = hdmi_mode_alternate_clock(cea_mode);
3676 clock1 = cea_mode->clock;
3678 if (clock1 == clock2)
3681 if (mode->clock != clock1 && mode->clock != clock2)
3684 newmode = drm_mode_duplicate(dev, cea_mode);
3688 /* Carry over the stereo flags */
3689 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3692 * The current mode could be either variant. Make
3693 * sure to pick the "other" clock for the new mode.
3695 if (mode->clock != clock1)
3696 newmode->clock = clock1;
3698 newmode->clock = clock2;
3700 list_add_tail(&newmode->head, &list);
3703 list_for_each_entry_safe(mode, tmp, &list, head) {
3704 list_del(&mode->head);
3705 drm_mode_probed_add(connector, mode);
3712 static u8 svd_to_vic(u8 svd)
3714 /* 0-6 bit vic, 7th bit native mode indicator */
3715 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3721 static struct drm_display_mode *
3722 drm_display_mode_from_vic_index(struct drm_connector *connector,
3723 const u8 *video_db, u8 video_len,
3726 struct drm_device *dev = connector->dev;
3727 struct drm_display_mode *newmode;
3730 if (video_db == NULL || video_index >= video_len)
3733 /* CEA modes are numbered 1..127 */
3734 vic = svd_to_vic(video_db[video_index]);
3735 if (!drm_valid_cea_vic(vic))
3738 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3746 * do_y420vdb_modes - Parse YCBCR 420 only modes
3747 * @connector: connector corresponding to the HDMI sink
3748 * @svds: start of the data block of CEA YCBCR 420 VDB
3749 * @len: length of the CEA YCBCR 420 VDB
3751 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3752 * which contains modes which can be supported in YCBCR 420
3753 * output format only.
3755 static int do_y420vdb_modes(struct drm_connector *connector,
3756 const u8 *svds, u8 svds_len)
3759 struct drm_device *dev = connector->dev;
3760 struct drm_display_info *info = &connector->display_info;
3761 struct drm_hdmi_info *hdmi = &info->hdmi;
3763 for (i = 0; i < svds_len; i++) {
3764 u8 vic = svd_to_vic(svds[i]);
3765 struct drm_display_mode *newmode;
3767 if (!drm_valid_cea_vic(vic))
3770 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3773 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3774 drm_mode_probed_add(connector, newmode);
3779 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3784 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3785 * @connector: connector corresponding to the HDMI sink
3786 * @vic: CEA vic for the video mode to be added in the map
3788 * Makes an entry for a videomode in the YCBCR 420 bitmap
3791 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3793 u8 vic = svd_to_vic(svd);
3794 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3796 if (!drm_valid_cea_vic(vic))
3799 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3803 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
3805 * @video_code: CEA VIC of the mode
3807 * Creates a new mode matching the specified CEA VIC.
3809 * Returns: A new drm_display_mode on success or NULL on failure
3811 struct drm_display_mode *
3812 drm_display_mode_from_cea_vic(struct drm_device *dev,
3815 const struct drm_display_mode *cea_mode;
3816 struct drm_display_mode *newmode;
3818 cea_mode = cea_mode_for_vic(video_code);
3822 newmode = drm_mode_duplicate(dev, cea_mode);
3828 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
3831 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3834 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3836 for (i = 0; i < len; i++) {
3837 struct drm_display_mode *mode;
3839 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3842 * YCBCR420 capability block contains a bitmap which
3843 * gives the index of CEA modes from CEA VDB, which
3844 * can support YCBCR 420 sampling output also (apart
3845 * from RGB/YCBCR444 etc).
3846 * For example, if the bit 0 in bitmap is set,
3847 * first mode in VDB can support YCBCR420 output too.
3848 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3850 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3851 drm_add_cmdb_modes(connector, db[i]);
3853 drm_mode_probed_add(connector, mode);
3861 struct stereo_mandatory_mode {
3862 int width, height, vrefresh;
3866 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3867 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3868 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3870 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3872 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3873 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3874 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3875 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3876 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3880 stereo_match_mandatory(const struct drm_display_mode *mode,
3881 const struct stereo_mandatory_mode *stereo_mode)
3883 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3885 return mode->hdisplay == stereo_mode->width &&
3886 mode->vdisplay == stereo_mode->height &&
3887 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3888 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3891 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3893 struct drm_device *dev = connector->dev;
3894 const struct drm_display_mode *mode;
3895 struct list_head stereo_modes;
3898 INIT_LIST_HEAD(&stereo_modes);
3900 list_for_each_entry(mode, &connector->probed_modes, head) {
3901 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3902 const struct stereo_mandatory_mode *mandatory;
3903 struct drm_display_mode *new_mode;
3905 if (!stereo_match_mandatory(mode,
3906 &stereo_mandatory_modes[i]))
3909 mandatory = &stereo_mandatory_modes[i];
3910 new_mode = drm_mode_duplicate(dev, mode);
3914 new_mode->flags |= mandatory->flags;
3915 list_add_tail(&new_mode->head, &stereo_modes);
3920 list_splice_tail(&stereo_modes, &connector->probed_modes);
3925 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3927 struct drm_device *dev = connector->dev;
3928 struct drm_display_mode *newmode;
3930 if (!drm_valid_hdmi_vic(vic)) {
3931 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3935 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3939 drm_mode_probed_add(connector, newmode);
3944 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3945 const u8 *video_db, u8 video_len, u8 video_index)
3947 struct drm_display_mode *newmode;
3950 if (structure & (1 << 0)) {
3951 newmode = drm_display_mode_from_vic_index(connector, video_db,
3955 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3956 drm_mode_probed_add(connector, newmode);
3960 if (structure & (1 << 6)) {
3961 newmode = drm_display_mode_from_vic_index(connector, video_db,
3965 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3966 drm_mode_probed_add(connector, newmode);
3970 if (structure & (1 << 8)) {
3971 newmode = drm_display_mode_from_vic_index(connector, video_db,
3975 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3976 drm_mode_probed_add(connector, newmode);
3985 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3986 * @connector: connector corresponding to the HDMI sink
3987 * @db: start of the CEA vendor specific block
3988 * @len: length of the CEA block payload, ie. one can access up to db[len]
3990 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3991 * also adds the stereo 3d modes when applicable.
3994 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3995 const u8 *video_db, u8 video_len)
3997 struct drm_display_info *info = &connector->display_info;
3998 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3999 u8 vic_len, hdmi_3d_len = 0;
4006 /* no HDMI_Video_Present */
4007 if (!(db[8] & (1 << 5)))
4010 /* Latency_Fields_Present */
4011 if (db[8] & (1 << 7))
4014 /* I_Latency_Fields_Present */
4015 if (db[8] & (1 << 6))
4018 /* the declared length is not long enough for the 2 first bytes
4019 * of additional video format capabilities */
4020 if (len < (8 + offset + 2))
4025 if (db[8 + offset] & (1 << 7)) {
4026 modes += add_hdmi_mandatory_stereo_modes(connector);
4028 /* 3D_Multi_present */
4029 multi_present = (db[8 + offset] & 0x60) >> 5;
4033 vic_len = db[8 + offset] >> 5;
4034 hdmi_3d_len = db[8 + offset] & 0x1f;
4036 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4039 vic = db[9 + offset + i];
4040 modes += add_hdmi_mode(connector, vic);
4042 offset += 1 + vic_len;
4044 if (multi_present == 1)
4046 else if (multi_present == 2)
4051 if (len < (8 + offset + hdmi_3d_len - 1))
4054 if (hdmi_3d_len < multi_len)
4057 if (multi_present == 1 || multi_present == 2) {
4058 /* 3D_Structure_ALL */
4059 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4061 /* check if 3D_MASK is present */
4062 if (multi_present == 2)
4063 mask = (db[10 + offset] << 8) | db[11 + offset];
4067 for (i = 0; i < 16; i++) {
4068 if (mask & (1 << i))
4069 modes += add_3d_struct_modes(connector,
4076 offset += multi_len;
4078 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4080 struct drm_display_mode *newmode = NULL;
4081 unsigned int newflag = 0;
4082 bool detail_present;
4084 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4086 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4089 /* 2D_VIC_order_X */
4090 vic_index = db[8 + offset + i] >> 4;
4092 /* 3D_Structure_X */
4093 switch (db[8 + offset + i] & 0x0f) {
4095 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4098 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4102 if ((db[9 + offset + i] >> 4) == 1)
4103 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4108 newmode = drm_display_mode_from_vic_index(connector,
4114 newmode->flags |= newflag;
4115 drm_mode_probed_add(connector, newmode);
4126 info->has_hdmi_infoframe = true;
4131 cea_db_payload_len(const u8 *db)
4133 return db[0] & 0x1f;
4137 cea_db_extended_tag(const u8 *db)
4143 cea_db_tag(const u8 *db)
4149 cea_revision(const u8 *cea)
4152 * FIXME is this correct for the DispID variant?
4153 * The DispID spec doesn't really specify whether
4154 * this is the revision of the CEA extension or
4155 * the DispID CEA data block. And the only value
4156 * given as an example is 0.
4162 cea_db_offsets(const u8 *cea, int *start, int *end)
4164 /* DisplayID CTA extension blocks and top-level CEA EDID
4165 * block header definitions differ in the following bytes:
4166 * 1) Byte 2 of the header specifies length differently,
4167 * 2) Byte 3 is only present in the CEA top level block.
4169 * The different definitions for byte 2 follow.
4171 * DisplayID CTA extension block defines byte 2 as:
4172 * Number of payload bytes
4174 * CEA EDID block defines byte 2 as:
4175 * Byte number (decimal) within this block where the 18-byte
4176 * DTDs begin. If no non-DTD data is present in this extension
4177 * block, the value should be set to 04h (the byte after next).
4178 * If set to 00h, there are no DTDs present in this block and
4181 if (cea[0] == DATA_BLOCK_CTA) {
4183 * for_each_displayid_db() has already verified
4184 * that these stay within expected bounds.
4187 *end = *start + cea[2];
4188 } else if (cea[0] == CEA_EXT) {
4189 /* Data block offset in CEA extension block */
4194 if (*end < 4 || *end > 127)
4203 static bool cea_db_is_hdmi_vsdb(const u8 *db)
4205 if (cea_db_tag(db) != VENDOR_BLOCK)
4208 if (cea_db_payload_len(db) < 5)
4211 return oui(db[3], db[2], db[1]) == HDMI_IEEE_OUI;
4214 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
4216 if (cea_db_tag(db) != VENDOR_BLOCK)
4219 if (cea_db_payload_len(db) < 7)
4222 return oui(db[3], db[2], db[1]) == HDMI_FORUM_IEEE_OUI;
4225 static bool cea_db_is_vcdb(const u8 *db)
4227 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4230 if (cea_db_payload_len(db) != 2)
4233 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
4239 static bool cea_db_is_y420cmdb(const u8 *db)
4241 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4244 if (!cea_db_payload_len(db))
4247 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
4253 static bool cea_db_is_y420vdb(const u8 *db)
4255 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4258 if (!cea_db_payload_len(db))
4261 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
4267 #define for_each_cea_db(cea, i, start, end) \
4268 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
4270 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4273 struct drm_display_info *info = &connector->display_info;
4274 struct drm_hdmi_info *hdmi = &info->hdmi;
4275 u8 map_len = cea_db_payload_len(db) - 1;
4280 /* All CEA modes support ycbcr420 sampling also.*/
4281 hdmi->y420_cmdb_map = U64_MAX;
4282 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4287 * This map indicates which of the existing CEA block modes
4288 * from VDB can support YCBCR420 output too. So if bit=0 is
4289 * set, first mode from VDB can support YCBCR420 output too.
4290 * We will parse and keep this map, before parsing VDB itself
4291 * to avoid going through the same block again and again.
4293 * Spec is not clear about max possible size of this block.
4294 * Clamping max bitmap block size at 8 bytes. Every byte can
4295 * address 8 CEA modes, in this way this map can address
4296 * 8*8 = first 64 SVDs.
4298 if (WARN_ON_ONCE(map_len > 8))
4301 for (count = 0; count < map_len; count++)
4302 map |= (u64)db[2 + count] << (8 * count);
4305 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4307 hdmi->y420_cmdb_map = map;
4311 add_cea_modes(struct drm_connector *connector, struct edid *edid)
4313 const u8 *cea = drm_find_cea_extension(edid);
4314 const u8 *db, *hdmi = NULL, *video = NULL;
4315 u8 dbl, hdmi_len, video_len = 0;
4318 if (cea && cea_revision(cea) >= 3) {
4321 if (cea_db_offsets(cea, &start, &end))
4324 for_each_cea_db(cea, i, start, end) {
4326 dbl = cea_db_payload_len(db);
4328 if (cea_db_tag(db) == VIDEO_BLOCK) {
4331 modes += do_cea_modes(connector, video, dbl);
4332 } else if (cea_db_is_hdmi_vsdb(db)) {
4335 } else if (cea_db_is_y420vdb(db)) {
4336 const u8 *vdb420 = &db[2];
4338 /* Add 4:2:0(only) modes present in EDID */
4339 modes += do_y420vdb_modes(connector,
4347 * We parse the HDMI VSDB after having added the cea modes as we will
4348 * be patching their flags when the sink supports stereo 3D.
4351 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4357 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4359 const struct drm_display_mode *cea_mode;
4360 int clock1, clock2, clock;
4365 * allow 5kHz clock difference either way to account for
4366 * the 10kHz clock resolution limit of detailed timings.
4368 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4369 if (drm_valid_cea_vic(vic)) {
4371 cea_mode = cea_mode_for_vic(vic);
4372 clock1 = cea_mode->clock;
4373 clock2 = cea_mode_alternate_clock(cea_mode);
4375 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4376 if (drm_valid_hdmi_vic(vic)) {
4378 cea_mode = &edid_4k_modes[vic];
4379 clock1 = cea_mode->clock;
4380 clock2 = hdmi_mode_alternate_clock(cea_mode);
4386 /* pick whichever is closest */
4387 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4392 if (mode->clock == clock)
4395 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
4396 type, vic, mode->clock, clock);
4397 mode->clock = clock;
4400 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4402 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4405 if (db[1] != HDR_STATIC_METADATA_BLOCK)
4408 if (cea_db_payload_len(db) < 3)
4414 static uint8_t eotf_supported(const u8 *edid_ext)
4416 return edid_ext[2] &
4417 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4418 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
4419 BIT(HDMI_EOTF_SMPTE_ST2084) |
4420 BIT(HDMI_EOTF_BT_2100_HLG));
4423 static uint8_t hdr_metadata_type(const u8 *edid_ext)
4425 return edid_ext[3] &
4426 BIT(HDMI_STATIC_METADATA_TYPE1);
4430 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4434 len = cea_db_payload_len(db);
4436 connector->hdr_sink_metadata.hdmi_type1.eotf =
4438 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4439 hdr_metadata_type(db);
4442 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4444 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4446 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4450 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
4452 u8 len = cea_db_payload_len(db);
4454 if (len >= 6 && (db[6] & (1 << 7)))
4455 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
4457 connector->latency_present[0] = db[8] >> 7;
4458 connector->latency_present[1] = (db[8] >> 6) & 1;
4461 connector->video_latency[0] = db[9];
4463 connector->audio_latency[0] = db[10];
4465 connector->video_latency[1] = db[11];
4467 connector->audio_latency[1] = db[12];
4469 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4470 "video latency %d %d, "
4471 "audio latency %d %d\n",
4472 connector->latency_present[0],
4473 connector->latency_present[1],
4474 connector->video_latency[0],
4475 connector->video_latency[1],
4476 connector->audio_latency[0],
4477 connector->audio_latency[1]);
4481 monitor_name(struct detailed_timing *t, void *data)
4483 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME))
4486 *(u8 **)data = t->data.other_data.data.str.str;
4489 static int get_monitor_name(struct edid *edid, char name[13])
4491 char *edid_name = NULL;
4497 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4498 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4499 if (edid_name[mnl] == 0x0a)
4502 name[mnl] = edid_name[mnl];
4509 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4510 * @edid: monitor EDID information
4511 * @name: pointer to a character array to hold the name of the monitor
4512 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4515 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4523 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4524 memcpy(name, buf, name_length);
4525 name[name_length] = '\0';
4527 EXPORT_SYMBOL(drm_edid_get_monitor_name);
4529 static void clear_eld(struct drm_connector *connector)
4531 memset(connector->eld, 0, sizeof(connector->eld));
4533 connector->latency_present[0] = false;
4534 connector->latency_present[1] = false;
4535 connector->video_latency[0] = 0;
4536 connector->audio_latency[0] = 0;
4537 connector->video_latency[1] = 0;
4538 connector->audio_latency[1] = 0;
4542 * drm_edid_to_eld - build ELD from EDID
4543 * @connector: connector corresponding to the HDMI/DP sink
4544 * @edid: EDID to parse
4546 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
4547 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
4549 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
4551 uint8_t *eld = connector->eld;
4554 int total_sad_count = 0;
4558 clear_eld(connector);
4563 cea = drm_find_cea_extension(edid);
4565 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4569 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4570 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
4572 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4573 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
4575 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
4577 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4578 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4579 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4580 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
4582 if (cea_revision(cea) >= 3) {
4586 if (cea_db_offsets(cea, &start, &end)) {
4591 for_each_cea_db(cea, i, start, end) {
4593 dbl = cea_db_payload_len(db);
4595 switch (cea_db_tag(db)) {
4597 /* Audio Data Block, contains SADs */
4598 sad_count = min(dbl / 3, 15 - total_sad_count);
4600 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
4601 &db[1], sad_count * 3);
4602 total_sad_count += sad_count;
4605 /* Speaker Allocation Data Block */
4607 eld[DRM_ELD_SPEAKER] = db[1];
4610 /* HDMI Vendor-Specific Data Block */
4611 if (cea_db_is_hdmi_vsdb(db))
4612 drm_parse_hdmi_vsdb_audio(connector, db);
4619 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
4621 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4622 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4623 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4625 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4627 eld[DRM_ELD_BASELINE_ELD_LEN] =
4628 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4630 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4631 drm_eld_size(eld), total_sad_count);
4635 * drm_edid_to_sad - extracts SADs from EDID
4636 * @edid: EDID to parse
4637 * @sads: pointer that will be set to the extracted SADs
4639 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4641 * Note: The returned pointer needs to be freed using kfree().
4643 * Return: The number of found SADs or negative number on error.
4645 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4648 int i, start, end, dbl;
4651 cea = drm_find_cea_extension(edid);
4653 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4657 if (cea_revision(cea) < 3) {
4658 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4662 if (cea_db_offsets(cea, &start, &end)) {
4663 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4667 for_each_cea_db(cea, i, start, end) {
4668 const u8 *db = &cea[i];
4670 if (cea_db_tag(db) == AUDIO_BLOCK) {
4673 dbl = cea_db_payload_len(db);
4675 count = dbl / 3; /* SAD is 3B */
4676 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4679 for (j = 0; j < count; j++) {
4680 const u8 *sad = &db[1 + j * 3];
4682 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4683 (*sads)[j].channels = sad[0] & 0x7;
4684 (*sads)[j].freq = sad[1] & 0x7F;
4685 (*sads)[j].byte2 = sad[2];
4693 EXPORT_SYMBOL(drm_edid_to_sad);
4696 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4697 * @edid: EDID to parse
4698 * @sadb: pointer to the speaker block
4700 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4702 * Note: The returned pointer needs to be freed using kfree().
4704 * Return: The number of found Speaker Allocation Blocks or negative number on
4707 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4710 int i, start, end, dbl;
4713 cea = drm_find_cea_extension(edid);
4715 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4719 if (cea_revision(cea) < 3) {
4720 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4724 if (cea_db_offsets(cea, &start, &end)) {
4725 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4729 for_each_cea_db(cea, i, start, end) {
4730 const u8 *db = &cea[i];
4732 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4733 dbl = cea_db_payload_len(db);
4735 /* Speaker Allocation Data Block */
4737 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4748 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4751 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4752 * @connector: connector associated with the HDMI/DP sink
4753 * @mode: the display mode
4755 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4756 * the sink doesn't support audio or video.
4758 int drm_av_sync_delay(struct drm_connector *connector,
4759 const struct drm_display_mode *mode)
4761 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4764 if (!connector->latency_present[0])
4766 if (!connector->latency_present[1])
4769 a = connector->audio_latency[i];
4770 v = connector->video_latency[i];
4773 * HDMI/DP sink doesn't support audio or video?
4775 if (a == 255 || v == 255)
4779 * Convert raw EDID values to millisecond.
4780 * Treat unknown latency as 0ms.
4783 a = min(2 * (a - 1), 500);
4785 v = min(2 * (v - 1), 500);
4787 return max(v - a, 0);
4789 EXPORT_SYMBOL(drm_av_sync_delay);
4792 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4793 * @edid: monitor EDID information
4795 * Parse the CEA extension according to CEA-861-B.
4797 * Drivers that have added the modes parsed from EDID to drm_display_info
4798 * should use &drm_display_info.is_hdmi instead of calling this function.
4800 * Return: True if the monitor is HDMI, false if not or unknown.
4802 bool drm_detect_hdmi_monitor(struct edid *edid)
4806 int start_offset, end_offset;
4808 edid_ext = drm_find_cea_extension(edid);
4812 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4816 * Because HDMI identifier is in Vendor Specific Block,
4817 * search it from all data blocks of CEA extension.
4819 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4820 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4826 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4829 * drm_detect_monitor_audio - check monitor audio capability
4830 * @edid: EDID block to scan
4832 * Monitor should have CEA extension block.
4833 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4834 * audio' only. If there is any audio extension block and supported
4835 * audio format, assume at least 'basic audio' support, even if 'basic
4836 * audio' is not defined in EDID.
4838 * Return: True if the monitor supports audio, false otherwise.
4840 bool drm_detect_monitor_audio(struct edid *edid)
4844 bool has_audio = false;
4845 int start_offset, end_offset;
4847 edid_ext = drm_find_cea_extension(edid);
4851 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4854 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4858 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4861 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4862 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4864 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4865 DRM_DEBUG_KMS("CEA audio format %d\n",
4866 (edid_ext[i + j] >> 3) & 0xf);
4873 EXPORT_SYMBOL(drm_detect_monitor_audio);
4877 * drm_default_rgb_quant_range - default RGB quantization range
4878 * @mode: display mode
4880 * Determine the default RGB quantization range for the mode,
4881 * as specified in CEA-861.
4883 * Return: The default RGB quantization range for the mode
4885 enum hdmi_quantization_range
4886 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4888 /* All CEA modes other than VIC 1 use limited quantization range. */
4889 return drm_match_cea_mode(mode) > 1 ?
4890 HDMI_QUANTIZATION_RANGE_LIMITED :
4891 HDMI_QUANTIZATION_RANGE_FULL;
4893 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4895 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4897 struct drm_display_info *info = &connector->display_info;
4899 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4901 if (db[2] & EDID_CEA_VCDB_QS)
4902 info->rgb_quant_range_selectable = true;
4906 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
4908 switch (max_frl_rate) {
4911 *max_rate_per_lane = 3;
4915 *max_rate_per_lane = 6;
4919 *max_rate_per_lane = 6;
4923 *max_rate_per_lane = 8;
4927 *max_rate_per_lane = 10;
4931 *max_rate_per_lane = 12;
4936 *max_rate_per_lane = 0;
4940 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4944 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4946 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4947 hdmi->y420_dc_modes = dc_mask;
4950 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4953 struct drm_display_info *display = &connector->display_info;
4954 struct drm_hdmi_info *hdmi = &display->hdmi;
4956 display->has_hdmi_infoframe = true;
4958 if (hf_vsdb[6] & 0x80) {
4959 hdmi->scdc.supported = true;
4960 if (hf_vsdb[6] & 0x40)
4961 hdmi->scdc.read_request = true;
4965 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4966 * And as per the spec, three factors confirm this:
4967 * * Availability of a HF-VSDB block in EDID (check)
4968 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4969 * * SCDC support available (let's check)
4970 * Lets check it out.
4974 /* max clock is 5000 KHz times block value */
4975 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4976 struct drm_scdc *scdc = &hdmi->scdc;
4978 if (max_tmds_clock > 340000) {
4979 display->max_tmds_clock = max_tmds_clock;
4980 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4981 display->max_tmds_clock);
4984 if (scdc->supported) {
4985 scdc->scrambling.supported = true;
4987 /* Few sinks support scrambling for clocks < 340M */
4988 if ((hf_vsdb[6] & 0x8))
4989 scdc->scrambling.low_rates = true;
4995 u8 dsc_max_frl_rate;
4997 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
4999 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
5000 max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
5001 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
5002 &hdmi->max_frl_rate_per_lane);
5003 hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2;
5005 if (hdmi_dsc->v_1p2) {
5006 hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420;
5007 hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP;
5009 if (hf_vsdb[11] & DRM_EDID_DSC_16BPC)
5010 hdmi_dsc->bpc_supported = 16;
5011 else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC)
5012 hdmi_dsc->bpc_supported = 12;
5013 else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC)
5014 hdmi_dsc->bpc_supported = 10;
5016 hdmi_dsc->bpc_supported = 0;
5018 dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
5019 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
5020 &hdmi_dsc->max_frl_rate_per_lane);
5021 hdmi_dsc->total_chunk_kbytes = hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
5023 dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES;
5024 switch (dsc_max_slices) {
5026 hdmi_dsc->max_slices = 1;
5027 hdmi_dsc->clk_per_slice = 340;
5030 hdmi_dsc->max_slices = 2;
5031 hdmi_dsc->clk_per_slice = 340;
5034 hdmi_dsc->max_slices = 4;
5035 hdmi_dsc->clk_per_slice = 340;
5038 hdmi_dsc->max_slices = 8;
5039 hdmi_dsc->clk_per_slice = 340;
5042 hdmi_dsc->max_slices = 8;
5043 hdmi_dsc->clk_per_slice = 400;
5046 hdmi_dsc->max_slices = 12;
5047 hdmi_dsc->clk_per_slice = 400;
5050 hdmi_dsc->max_slices = 16;
5051 hdmi_dsc->clk_per_slice = 400;
5055 hdmi_dsc->max_slices = 0;
5056 hdmi_dsc->clk_per_slice = 0;
5061 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
5064 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
5067 struct drm_display_info *info = &connector->display_info;
5068 unsigned int dc_bpc = 0;
5070 /* HDMI supports at least 8 bpc */
5073 if (cea_db_payload_len(hdmi) < 6)
5076 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
5078 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
5079 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
5083 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
5085 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
5086 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
5090 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
5092 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
5093 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
5098 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
5103 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
5104 connector->name, dc_bpc);
5108 * Deep color support mandates RGB444 support for all video
5109 * modes and forbids YCRCB422 support for all video modes per
5112 info->color_formats = DRM_COLOR_FORMAT_RGB444;
5114 /* YCRCB444 is optional according to spec. */
5115 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
5116 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5117 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
5122 * Spec says that if any deep color mode is supported at all,
5123 * then deep color 36 bit must be supported.
5125 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
5126 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
5132 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
5134 struct drm_display_info *info = &connector->display_info;
5135 u8 len = cea_db_payload_len(db);
5137 info->is_hdmi = true;
5140 info->dvi_dual = db[6] & 1;
5142 info->max_tmds_clock = db[7] * 5000;
5144 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
5145 "max TMDS clock %d kHz\n",
5147 info->max_tmds_clock);
5149 drm_parse_hdmi_deep_color_info(connector, db);
5152 static void drm_parse_cea_ext(struct drm_connector *connector,
5153 const struct edid *edid)
5155 struct drm_display_info *info = &connector->display_info;
5159 edid_ext = drm_find_cea_extension(edid);
5163 info->cea_rev = edid_ext[1];
5165 /* The existence of a CEA block should imply RGB support */
5166 info->color_formats = DRM_COLOR_FORMAT_RGB444;
5167 if (edid_ext[3] & EDID_CEA_YCRCB444)
5168 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5169 if (edid_ext[3] & EDID_CEA_YCRCB422)
5170 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
5172 if (cea_db_offsets(edid_ext, &start, &end))
5175 for_each_cea_db(edid_ext, i, start, end) {
5176 const u8 *db = &edid_ext[i];
5178 if (cea_db_is_hdmi_vsdb(db))
5179 drm_parse_hdmi_vsdb_video(connector, db);
5180 if (cea_db_is_hdmi_forum_vsdb(db))
5181 drm_parse_hdmi_forum_vsdb(connector, db);
5182 if (cea_db_is_y420cmdb(db))
5183 drm_parse_y420cmdb_bitmap(connector, db);
5184 if (cea_db_is_vcdb(db))
5185 drm_parse_vcdb(connector, db);
5186 if (cea_db_is_hdmi_hdr_metadata_block(db))
5187 drm_parse_hdr_metadata_block(connector, db);
5192 void get_monitor_range(struct detailed_timing *timing,
5193 void *info_monitor_range)
5195 struct drm_monitor_range_info *monitor_range = info_monitor_range;
5196 const struct detailed_non_pixel *data = &timing->data.other_data;
5197 const struct detailed_data_monitor_range *range = &data->data.range;
5199 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
5203 * Check for flag range limits only. If flag == 1 then
5204 * no additional timing information provided.
5205 * Default GTF, GTF Secondary curve and CVT are not
5208 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
5211 monitor_range->min_vfreq = range->min_vfreq;
5212 monitor_range->max_vfreq = range->max_vfreq;
5216 void drm_get_monitor_range(struct drm_connector *connector,
5217 const struct edid *edid)
5219 struct drm_display_info *info = &connector->display_info;
5221 if (!version_greater(edid, 1, 1))
5224 drm_for_each_detailed_block((u8 *)edid, get_monitor_range,
5225 &info->monitor_range);
5227 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
5228 info->monitor_range.min_vfreq,
5229 info->monitor_range.max_vfreq);
5232 static void drm_parse_vesa_mso_data(struct drm_connector *connector,
5233 const struct displayid_block *block)
5235 struct displayid_vesa_vendor_specific_block *vesa =
5236 (struct displayid_vesa_vendor_specific_block *)block;
5237 struct drm_display_info *info = &connector->display_info;
5239 if (block->num_bytes < 3) {
5240 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n",
5245 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
5248 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
5249 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
5253 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
5255 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
5258 info->mso_stream_count = 0;
5261 info->mso_stream_count = 2; /* 2 or 4 links */
5264 info->mso_stream_count = 4; /* 4 links */
5268 if (!info->mso_stream_count) {
5269 info->mso_pixel_overlap = 0;
5273 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
5274 if (info->mso_pixel_overlap > 8) {
5275 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
5276 info->mso_pixel_overlap);
5277 info->mso_pixel_overlap = 8;
5280 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
5281 info->mso_stream_count, info->mso_pixel_overlap);
5284 static void drm_update_mso(struct drm_connector *connector, const struct edid *edid)
5286 const struct displayid_block *block;
5287 struct displayid_iter iter;
5289 displayid_iter_edid_begin(edid, &iter);
5290 displayid_iter_for_each(block, &iter) {
5291 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
5292 drm_parse_vesa_mso_data(connector, block);
5294 displayid_iter_end(&iter);
5297 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
5298 * all of the values which would have been set from EDID
5301 drm_reset_display_info(struct drm_connector *connector)
5303 struct drm_display_info *info = &connector->display_info;
5306 info->height_mm = 0;
5309 info->color_formats = 0;
5311 info->max_tmds_clock = 0;
5312 info->dvi_dual = false;
5313 info->is_hdmi = false;
5314 info->has_hdmi_infoframe = false;
5315 info->rgb_quant_range_selectable = false;
5316 memset(&info->hdmi, 0, sizeof(info->hdmi));
5318 info->non_desktop = 0;
5319 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
5321 info->mso_stream_count = 0;
5322 info->mso_pixel_overlap = 0;
5325 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
5327 struct drm_display_info *info = &connector->display_info;
5329 u32 quirks = edid_get_quirks(edid);
5331 drm_reset_display_info(connector);
5333 info->width_mm = edid->width_cm * 10;
5334 info->height_mm = edid->height_cm * 10;
5336 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
5338 drm_get_monitor_range(connector, edid);
5340 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
5342 if (edid->revision < 3)
5345 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
5348 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
5349 drm_parse_cea_ext(connector, edid);
5352 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
5354 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
5355 * tells us to assume 8 bpc color depth if the EDID doesn't have
5356 * extensions which tell otherwise.
5358 if (info->bpc == 0 && edid->revision == 3 &&
5359 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
5361 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
5362 connector->name, info->bpc);
5365 /* Only defined for 1.4 with digital displays */
5366 if (edid->revision < 4)
5369 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
5370 case DRM_EDID_DIGITAL_DEPTH_6:
5373 case DRM_EDID_DIGITAL_DEPTH_8:
5376 case DRM_EDID_DIGITAL_DEPTH_10:
5379 case DRM_EDID_DIGITAL_DEPTH_12:
5382 case DRM_EDID_DIGITAL_DEPTH_14:
5385 case DRM_EDID_DIGITAL_DEPTH_16:
5388 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
5394 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
5395 connector->name, info->bpc);
5397 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
5398 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5399 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
5400 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
5402 drm_update_mso(connector, edid);
5407 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
5408 struct displayid_detailed_timings_1 *timings)
5410 struct drm_display_mode *mode;
5411 unsigned pixel_clock = (timings->pixel_clock[0] |
5412 (timings->pixel_clock[1] << 8) |
5413 (timings->pixel_clock[2] << 16)) + 1;
5414 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5415 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5416 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
5417 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
5418 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
5419 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
5420 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
5421 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
5422 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
5423 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
5425 mode = drm_mode_create(dev);
5429 mode->clock = pixel_clock * 10;
5430 mode->hdisplay = hactive;
5431 mode->hsync_start = mode->hdisplay + hsync;
5432 mode->hsync_end = mode->hsync_start + hsync_width;
5433 mode->htotal = mode->hdisplay + hblank;
5435 mode->vdisplay = vactive;
5436 mode->vsync_start = mode->vdisplay + vsync;
5437 mode->vsync_end = mode->vsync_start + vsync_width;
5438 mode->vtotal = mode->vdisplay + vblank;
5441 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5442 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5443 mode->type = DRM_MODE_TYPE_DRIVER;
5445 if (timings->flags & 0x80)
5446 mode->type |= DRM_MODE_TYPE_PREFERRED;
5447 drm_mode_set_name(mode);
5452 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
5453 const struct displayid_block *block)
5455 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
5458 struct drm_display_mode *newmode;
5460 /* blocks must be multiple of 20 bytes length */
5461 if (block->num_bytes % 20)
5464 num_timings = block->num_bytes / 20;
5465 for (i = 0; i < num_timings; i++) {
5466 struct displayid_detailed_timings_1 *timings = &det->timings[i];
5468 newmode = drm_mode_displayid_detailed(connector->dev, timings);
5472 drm_mode_probed_add(connector, newmode);
5478 static int add_displayid_detailed_modes(struct drm_connector *connector,
5481 const struct displayid_block *block;
5482 struct displayid_iter iter;
5485 displayid_iter_edid_begin(edid, &iter);
5486 displayid_iter_for_each(block, &iter) {
5487 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING)
5488 num_modes += add_displayid_detailed_1_modes(connector, block);
5490 displayid_iter_end(&iter);
5496 * drm_add_edid_modes - add modes from EDID data, if available
5497 * @connector: connector we're probing
5500 * Add the specified modes to the connector's mode list. Also fills out the
5501 * &drm_display_info structure and ELD in @connector with any information which
5502 * can be derived from the edid.
5504 * Return: The number of modes added or 0 if we couldn't find any.
5506 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
5512 clear_eld(connector);
5515 if (!drm_edid_is_valid(edid)) {
5516 clear_eld(connector);
5517 drm_warn(connector->dev, "%s: EDID invalid.\n",
5522 drm_edid_to_eld(connector, edid);
5525 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5526 * To avoid multiple parsing of same block, lets parse that map
5527 * from sink info, before parsing CEA modes.
5529 quirks = drm_add_display_info(connector, edid);
5532 * EDID spec says modes should be preferred in this order:
5533 * - preferred detailed mode
5534 * - other detailed modes from base block
5535 * - detailed modes from extension blocks
5536 * - CVT 3-byte code modes
5537 * - standard timing codes
5538 * - established timing codes
5539 * - modes inferred from GTF or CVT range information
5541 * We get this pretty much right.
5543 * XXX order for additional mode types in extension blocks?
5545 num_modes += add_detailed_modes(connector, edid, quirks);
5546 num_modes += add_cvt_modes(connector, edid);
5547 num_modes += add_standard_modes(connector, edid);
5548 num_modes += add_established_modes(connector, edid);
5549 num_modes += add_cea_modes(connector, edid);
5550 num_modes += add_alternate_cea_modes(connector, edid);
5551 num_modes += add_displayid_detailed_modes(connector, edid);
5552 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
5553 num_modes += add_inferred_modes(connector, edid);
5555 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
5556 edid_fixup_preferred(connector, quirks);
5558 if (quirks & EDID_QUIRK_FORCE_6BPC)
5559 connector->display_info.bpc = 6;
5561 if (quirks & EDID_QUIRK_FORCE_8BPC)
5562 connector->display_info.bpc = 8;
5564 if (quirks & EDID_QUIRK_FORCE_10BPC)
5565 connector->display_info.bpc = 10;
5567 if (quirks & EDID_QUIRK_FORCE_12BPC)
5568 connector->display_info.bpc = 12;
5572 EXPORT_SYMBOL(drm_add_edid_modes);
5575 * drm_add_modes_noedid - add modes for the connectors without EDID
5576 * @connector: connector we're probing
5577 * @hdisplay: the horizontal display limit
5578 * @vdisplay: the vertical display limit
5580 * Add the specified modes to the connector's mode list. Only when the
5581 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5583 * Return: The number of modes added or 0 if we couldn't find any.
5585 int drm_add_modes_noedid(struct drm_connector *connector,
5586 int hdisplay, int vdisplay)
5588 int i, count, num_modes = 0;
5589 struct drm_display_mode *mode;
5590 struct drm_device *dev = connector->dev;
5592 count = ARRAY_SIZE(drm_dmt_modes);
5598 for (i = 0; i < count; i++) {
5599 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
5601 if (hdisplay && vdisplay) {
5603 * Only when two are valid, they will be used to check
5604 * whether the mode should be added to the mode list of
5607 if (ptr->hdisplay > hdisplay ||
5608 ptr->vdisplay > vdisplay)
5611 if (drm_mode_vrefresh(ptr) > 61)
5613 mode = drm_mode_duplicate(dev, ptr);
5615 drm_mode_probed_add(connector, mode);
5621 EXPORT_SYMBOL(drm_add_modes_noedid);
5624 * drm_set_preferred_mode - Sets the preferred mode of a connector
5625 * @connector: connector whose mode list should be processed
5626 * @hpref: horizontal resolution of preferred mode
5627 * @vpref: vertical resolution of preferred mode
5629 * Marks a mode as preferred if it matches the resolution specified by @hpref
5632 void drm_set_preferred_mode(struct drm_connector *connector,
5633 int hpref, int vpref)
5635 struct drm_display_mode *mode;
5637 list_for_each_entry(mode, &connector->probed_modes, head) {
5638 if (mode->hdisplay == hpref &&
5639 mode->vdisplay == vpref)
5640 mode->type |= DRM_MODE_TYPE_PREFERRED;
5643 EXPORT_SYMBOL(drm_set_preferred_mode);
5645 static bool is_hdmi2_sink(const struct drm_connector *connector)
5648 * FIXME: sil-sii8620 doesn't have a connector around when
5649 * we need one, so we have to be prepared for a NULL connector.
5654 return connector->display_info.hdmi.scdc.supported ||
5655 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
5658 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5660 return sink_eotf & BIT(output_eotf);
5664 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5665 * HDR metadata from userspace
5666 * @frame: HDMI DRM infoframe
5667 * @conn_state: Connector state containing HDR metadata
5669 * Return: 0 on success or a negative error code on failure.
5672 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5673 const struct drm_connector_state *conn_state)
5675 struct drm_connector *connector;
5676 struct hdr_output_metadata *hdr_metadata;
5679 if (!frame || !conn_state)
5682 connector = conn_state->connector;
5684 if (!conn_state->hdr_output_metadata)
5687 hdr_metadata = conn_state->hdr_output_metadata->data;
5689 if (!hdr_metadata || !connector)
5692 /* Sink EOTF is Bit map while infoframe is absolute values */
5693 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5694 connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5695 DRM_DEBUG_KMS("EOTF Not Supported\n");
5699 err = hdmi_drm_infoframe_init(frame);
5703 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5704 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5706 BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5707 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5708 BUILD_BUG_ON(sizeof(frame->white_point) !=
5709 sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5711 memcpy(&frame->display_primaries,
5712 &hdr_metadata->hdmi_metadata_type1.display_primaries,
5713 sizeof(frame->display_primaries));
5715 memcpy(&frame->white_point,
5716 &hdr_metadata->hdmi_metadata_type1.white_point,
5717 sizeof(frame->white_point));
5719 frame->max_display_mastering_luminance =
5720 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5721 frame->min_display_mastering_luminance =
5722 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5723 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5724 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5728 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5730 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
5731 const struct drm_display_mode *mode)
5733 bool has_hdmi_infoframe = connector ?
5734 connector->display_info.has_hdmi_infoframe : false;
5736 if (!has_hdmi_infoframe)
5739 /* No HDMI VIC when signalling 3D video format */
5740 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
5743 return drm_match_hdmi_mode(mode);
5746 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
5747 const struct drm_display_mode *mode)
5752 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5753 * we should send its VIC in vendor infoframes, else send the
5754 * VIC in AVI infoframes. Lets check if this mode is present in
5755 * HDMI 1.4b 4K modes
5757 if (drm_mode_hdmi_vic(connector, mode))
5760 vic = drm_match_cea_mode(mode);
5763 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5764 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5765 * have to make sure we dont break HDMI 1.4 sinks.
5767 if (!is_hdmi2_sink(connector) && vic > 64)
5774 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5775 * data from a DRM display mode
5776 * @frame: HDMI AVI infoframe
5777 * @connector: the connector
5778 * @mode: DRM display mode
5780 * Return: 0 on success or a negative error code on failure.
5783 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
5784 const struct drm_connector *connector,
5785 const struct drm_display_mode *mode)
5787 enum hdmi_picture_aspect picture_aspect;
5790 if (!frame || !mode)
5793 hdmi_avi_infoframe_init(frame);
5795 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5796 frame->pixel_repeat = 1;
5798 vic = drm_mode_cea_vic(connector, mode);
5799 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
5801 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5804 * As some drivers don't support atomic, we can't use connector state.
5805 * So just initialize the frame with default values, just the same way
5806 * as it's done with other properties here.
5808 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5812 * Populate picture aspect ratio from either
5813 * user input (if specified) or from the CEA/HDMI mode lists.
5815 picture_aspect = mode->picture_aspect_ratio;
5816 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
5818 picture_aspect = drm_get_cea_aspect_ratio(vic);
5820 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
5824 * The infoframe can't convey anything but none, 4:3
5825 * and 16:9, so if the user has asked for anything else
5826 * we can only satisfy it by specifying the right VIC.
5828 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
5830 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
5832 } else if (hdmi_vic) {
5833 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
5839 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5842 frame->video_code = vic;
5843 frame->picture_aspect = picture_aspect;
5844 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
5845 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
5849 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
5851 /* HDMI Colorspace Spec Definitions */
5852 #define FULL_COLORIMETRY_MASK 0x1FF
5853 #define NORMAL_COLORIMETRY_MASK 0x3
5854 #define EXTENDED_COLORIMETRY_MASK 0x7
5855 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5857 #define C(x) ((x) << 0)
5858 #define EC(x) ((x) << 2)
5859 #define ACE(x) ((x) << 5)
5861 #define HDMI_COLORIMETRY_NO_DATA 0x0
5862 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5863 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5864 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5865 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5866 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5867 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5868 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5869 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5870 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5871 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5872 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5873 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5875 static const u32 hdmi_colorimetry_val[] = {
5876 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5877 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5878 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5879 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5880 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5881 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5882 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5883 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5884 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5885 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5886 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5894 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
5895 * colorspace information
5896 * @frame: HDMI AVI infoframe
5897 * @conn_state: connector state
5900 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
5901 const struct drm_connector_state *conn_state)
5903 u32 colorimetry_val;
5904 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5906 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5907 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5909 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5911 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5913 * ToDo: Extend it for ACE formats as well. Modify the infoframe
5914 * structure and extend it in drivers/video/hdmi
5916 frame->extended_colorimetry = (colorimetry_val >> 2) &
5917 EXTENDED_COLORIMETRY_MASK;
5919 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5922 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5923 * quantization range information
5924 * @frame: HDMI AVI infoframe
5925 * @connector: the connector
5926 * @mode: DRM display mode
5927 * @rgb_quant_range: RGB quantization range (Q)
5930 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
5931 const struct drm_connector *connector,
5932 const struct drm_display_mode *mode,
5933 enum hdmi_quantization_range rgb_quant_range)
5935 const struct drm_display_info *info = &connector->display_info;
5939 * "A Source shall not send a non-zero Q value that does not correspond
5940 * to the default RGB Quantization Range for the transmitted Picture
5941 * unless the Sink indicates support for the Q bit in a Video
5942 * Capabilities Data Block."
5944 * HDMI 2.0 recommends sending non-zero Q when it does match the
5945 * default RGB quantization range for the mode, even when QS=0.
5947 if (info->rgb_quant_range_selectable ||
5948 rgb_quant_range == drm_default_rgb_quant_range(mode))
5949 frame->quantization_range = rgb_quant_range;
5951 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
5955 * "When transmitting any RGB colorimetry, the Source should set the
5956 * YQ-field to match the RGB Quantization Range being transmitted
5957 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5958 * set YQ=1) and the Sink shall ignore the YQ-field."
5960 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5961 * by non-zero YQ when receiving RGB. There doesn't seem to be any
5962 * good way to tell which version of CEA-861 the sink supports, so
5963 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5966 if (!is_hdmi2_sink(connector) ||
5967 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
5968 frame->ycc_quantization_range =
5969 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5971 frame->ycc_quantization_range =
5972 HDMI_YCC_QUANTIZATION_RANGE_FULL;
5974 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5977 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
5979 * @frame: HDMI AVI infoframe
5980 * @conn_state: connector state
5983 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
5984 const struct drm_connector_state *conn_state)
5986 frame->right_bar = conn_state->tv.margins.right;
5987 frame->left_bar = conn_state->tv.margins.left;
5988 frame->top_bar = conn_state->tv.margins.top;
5989 frame->bottom_bar = conn_state->tv.margins.bottom;
5991 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
5993 static enum hdmi_3d_structure
5994 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5996 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5999 case DRM_MODE_FLAG_3D_FRAME_PACKING:
6000 return HDMI_3D_STRUCTURE_FRAME_PACKING;
6001 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
6002 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
6003 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
6004 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
6005 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
6006 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
6007 case DRM_MODE_FLAG_3D_L_DEPTH:
6008 return HDMI_3D_STRUCTURE_L_DEPTH;
6009 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
6010 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
6011 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
6012 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
6013 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
6014 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
6016 return HDMI_3D_STRUCTURE_INVALID;
6021 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
6022 * data from a DRM display mode
6023 * @frame: HDMI vendor infoframe
6024 * @connector: the connector
6025 * @mode: DRM display mode
6027 * Note that there's is a need to send HDMI vendor infoframes only when using a
6028 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
6029 * function will return -EINVAL, error that can be safely ignored.
6031 * Return: 0 on success or a negative error code on failure.
6034 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
6035 const struct drm_connector *connector,
6036 const struct drm_display_mode *mode)
6039 * FIXME: sil-sii8620 doesn't have a connector around when
6040 * we need one, so we have to be prepared for a NULL connector.
6042 bool has_hdmi_infoframe = connector ?
6043 connector->display_info.has_hdmi_infoframe : false;
6046 if (!frame || !mode)
6049 if (!has_hdmi_infoframe)
6052 err = hdmi_vendor_infoframe_init(frame);
6057 * Even if it's not absolutely necessary to send the infoframe
6058 * (ie.vic==0 and s3d_struct==0) we will still send it if we
6059 * know that the sink can handle it. This is based on a
6060 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
6061 * have trouble realizing that they should switch from 3D to 2D
6062 * mode if the source simply stops sending the infoframe when
6063 * it wants to switch from 3D to 2D.
6065 frame->vic = drm_mode_hdmi_vic(connector, mode);
6066 frame->s3d_struct = s3d_structure_from_display_mode(mode);
6070 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
6072 static void drm_parse_tiled_block(struct drm_connector *connector,
6073 const struct displayid_block *block)
6075 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
6077 u8 tile_v_loc, tile_h_loc;
6078 u8 num_v_tile, num_h_tile;
6079 struct drm_tile_group *tg;
6081 w = tile->tile_size[0] | tile->tile_size[1] << 8;
6082 h = tile->tile_size[2] | tile->tile_size[3] << 8;
6084 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
6085 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
6086 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
6087 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
6089 connector->has_tile = true;
6090 if (tile->tile_cap & 0x80)
6091 connector->tile_is_single_monitor = true;
6093 connector->num_h_tile = num_h_tile + 1;
6094 connector->num_v_tile = num_v_tile + 1;
6095 connector->tile_h_loc = tile_h_loc;
6096 connector->tile_v_loc = tile_v_loc;
6097 connector->tile_h_size = w + 1;
6098 connector->tile_v_size = h + 1;
6100 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
6101 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
6102 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
6103 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
6104 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
6106 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
6108 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
6112 if (connector->tile_group != tg) {
6113 /* if we haven't got a pointer,
6114 take the reference, drop ref to old tile group */
6115 if (connector->tile_group)
6116 drm_mode_put_tile_group(connector->dev, connector->tile_group);
6117 connector->tile_group = tg;
6119 /* if same tile group, then release the ref we just took. */
6120 drm_mode_put_tile_group(connector->dev, tg);
6124 void drm_update_tile_info(struct drm_connector *connector,
6125 const struct edid *edid)
6127 const struct displayid_block *block;
6128 struct displayid_iter iter;
6130 connector->has_tile = false;
6132 displayid_iter_edid_begin(edid, &iter);
6133 displayid_iter_for_each(block, &iter) {
6134 if (block->tag == DATA_BLOCK_TILED_DISPLAY)
6135 drm_parse_tiled_block(connector, block);
6137 displayid_iter_end(&iter);
6139 if (!connector->has_tile && connector->tile_group) {
6140 drm_mode_put_tile_group(connector->dev, connector->tile_group);
6141 connector->tile_group = NULL;
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