2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
35 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_displayid.h>
41 #include "drm_crtc_internal.h"
43 #define version_greater(edid, maj, min) \
44 (((edid)->version > (maj)) || \
45 ((edid)->version == (maj) && (edid)->revision > (min)))
47 #define EDID_EST_TIMINGS 16
48 #define EDID_STD_TIMINGS 8
49 #define EDID_DETAILED_TIMINGS 4
52 * EDID blocks out in the wild have a variety of bugs, try to collect
53 * them here (note that userspace may work around broken monitors first,
54 * but fixes should make their way here so that the kernel "just works"
55 * on as many displays as possible).
58 /* First detailed mode wrong, use largest 60Hz mode */
59 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
60 /* Reported 135MHz pixel clock is too high, needs adjustment */
61 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
62 /* Prefer the largest mode at 75 Hz */
63 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
64 /* Detail timing is in cm not mm */
65 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
66 /* Detailed timing descriptors have bogus size values, so just take the
67 * maximum size and use that.
69 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
70 /* Monitor forgot to set the first detailed is preferred bit. */
71 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
72 /* use +hsync +vsync for detailed mode */
73 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
74 /* Force reduced-blanking timings for detailed modes */
75 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
77 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
79 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
81 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
83 struct detailed_mode_closure {
84 struct drm_connector *connector;
96 static const struct edid_quirk {
100 } edid_quirk_list[] = {
102 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
104 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
106 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
108 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
109 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
111 /* Belinea 10 15 55 */
112 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
113 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
115 /* Envision Peripherals, Inc. EN-7100e */
116 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
117 /* Envision EN2028 */
118 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
120 /* Funai Electronics PM36B */
121 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
122 EDID_QUIRK_DETAILED_IN_CM },
124 /* LG Philips LCD LP154W01-A5 */
125 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
126 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
128 /* Philips 107p5 CRT */
129 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
132 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
134 /* Samsung SyncMaster 205BW. Note: irony */
135 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
136 /* Samsung SyncMaster 22[5-6]BW */
137 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
138 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
140 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
141 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
143 /* ViewSonic VA2026w */
144 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
146 /* Medion MD 30217 PG */
147 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
149 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
150 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
154 * Autogenerated from the DMT spec.
155 * This table is copied from xfree86/modes/xf86EdidModes.c.
157 static const struct drm_display_mode drm_dmt_modes[] = {
158 /* 0x01 - 640x350@85Hz */
159 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
160 736, 832, 0, 350, 382, 385, 445, 0,
161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
162 /* 0x02 - 640x400@85Hz */
163 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
164 736, 832, 0, 400, 401, 404, 445, 0,
165 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
166 /* 0x03 - 720x400@85Hz */
167 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
168 828, 936, 0, 400, 401, 404, 446, 0,
169 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
170 /* 0x04 - 640x480@60Hz */
171 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
172 752, 800, 0, 480, 490, 492, 525, 0,
173 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
174 /* 0x05 - 640x480@72Hz */
175 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
176 704, 832, 0, 480, 489, 492, 520, 0,
177 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
178 /* 0x06 - 640x480@75Hz */
179 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
180 720, 840, 0, 480, 481, 484, 500, 0,
181 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
182 /* 0x07 - 640x480@85Hz */
183 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
184 752, 832, 0, 480, 481, 484, 509, 0,
185 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
186 /* 0x08 - 800x600@56Hz */
187 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
188 896, 1024, 0, 600, 601, 603, 625, 0,
189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
190 /* 0x09 - 800x600@60Hz */
191 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
192 968, 1056, 0, 600, 601, 605, 628, 0,
193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
194 /* 0x0a - 800x600@72Hz */
195 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
196 976, 1040, 0, 600, 637, 643, 666, 0,
197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
198 /* 0x0b - 800x600@75Hz */
199 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
200 896, 1056, 0, 600, 601, 604, 625, 0,
201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
202 /* 0x0c - 800x600@85Hz */
203 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
204 896, 1048, 0, 600, 601, 604, 631, 0,
205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
206 /* 0x0d - 800x600@120Hz RB */
207 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
208 880, 960, 0, 600, 603, 607, 636, 0,
209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
210 /* 0x0e - 848x480@60Hz */
211 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
212 976, 1088, 0, 480, 486, 494, 517, 0,
213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
214 /* 0x0f - 1024x768@43Hz, interlace */
215 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
216 1208, 1264, 0, 768, 768, 776, 817, 0,
217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
218 DRM_MODE_FLAG_INTERLACE) },
219 /* 0x10 - 1024x768@60Hz */
220 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
221 1184, 1344, 0, 768, 771, 777, 806, 0,
222 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
223 /* 0x11 - 1024x768@70Hz */
224 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
225 1184, 1328, 0, 768, 771, 777, 806, 0,
226 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
227 /* 0x12 - 1024x768@75Hz */
228 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
229 1136, 1312, 0, 768, 769, 772, 800, 0,
230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
231 /* 0x13 - 1024x768@85Hz */
232 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
233 1168, 1376, 0, 768, 769, 772, 808, 0,
234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
235 /* 0x14 - 1024x768@120Hz RB */
236 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
237 1104, 1184, 0, 768, 771, 775, 813, 0,
238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
239 /* 0x15 - 1152x864@75Hz */
240 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
241 1344, 1600, 0, 864, 865, 868, 900, 0,
242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
243 /* 0x55 - 1280x720@60Hz */
244 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
245 1430, 1650, 0, 720, 725, 730, 750, 0,
246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
247 /* 0x16 - 1280x768@60Hz RB */
248 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
249 1360, 1440, 0, 768, 771, 778, 790, 0,
250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
251 /* 0x17 - 1280x768@60Hz */
252 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
253 1472, 1664, 0, 768, 771, 778, 798, 0,
254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
255 /* 0x18 - 1280x768@75Hz */
256 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
257 1488, 1696, 0, 768, 771, 778, 805, 0,
258 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
259 /* 0x19 - 1280x768@85Hz */
260 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
261 1496, 1712, 0, 768, 771, 778, 809, 0,
262 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
263 /* 0x1a - 1280x768@120Hz RB */
264 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
265 1360, 1440, 0, 768, 771, 778, 813, 0,
266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
267 /* 0x1b - 1280x800@60Hz RB */
268 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
269 1360, 1440, 0, 800, 803, 809, 823, 0,
270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
271 /* 0x1c - 1280x800@60Hz */
272 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
273 1480, 1680, 0, 800, 803, 809, 831, 0,
274 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
275 /* 0x1d - 1280x800@75Hz */
276 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
277 1488, 1696, 0, 800, 803, 809, 838, 0,
278 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
279 /* 0x1e - 1280x800@85Hz */
280 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
281 1496, 1712, 0, 800, 803, 809, 843, 0,
282 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
283 /* 0x1f - 1280x800@120Hz RB */
284 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
285 1360, 1440, 0, 800, 803, 809, 847, 0,
286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
287 /* 0x20 - 1280x960@60Hz */
288 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
289 1488, 1800, 0, 960, 961, 964, 1000, 0,
290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
291 /* 0x21 - 1280x960@85Hz */
292 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
293 1504, 1728, 0, 960, 961, 964, 1011, 0,
294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
295 /* 0x22 - 1280x960@120Hz RB */
296 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
297 1360, 1440, 0, 960, 963, 967, 1017, 0,
298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
299 /* 0x23 - 1280x1024@60Hz */
300 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
301 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
303 /* 0x24 - 1280x1024@75Hz */
304 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
305 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
307 /* 0x25 - 1280x1024@85Hz */
308 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
309 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
311 /* 0x26 - 1280x1024@120Hz RB */
312 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
313 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
315 /* 0x27 - 1360x768@60Hz */
316 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
317 1536, 1792, 0, 768, 771, 777, 795, 0,
318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
319 /* 0x28 - 1360x768@120Hz RB */
320 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
321 1440, 1520, 0, 768, 771, 776, 813, 0,
322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
323 /* 0x51 - 1366x768@60Hz */
324 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
325 1579, 1792, 0, 768, 771, 774, 798, 0,
326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
327 /* 0x56 - 1366x768@60Hz */
328 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
329 1436, 1500, 0, 768, 769, 772, 800, 0,
330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
331 /* 0x29 - 1400x1050@60Hz RB */
332 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
333 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
335 /* 0x2a - 1400x1050@60Hz */
336 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
337 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
339 /* 0x2b - 1400x1050@75Hz */
340 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
341 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
343 /* 0x2c - 1400x1050@85Hz */
344 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
345 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
346 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
347 /* 0x2d - 1400x1050@120Hz RB */
348 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
349 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
351 /* 0x2e - 1440x900@60Hz RB */
352 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
353 1520, 1600, 0, 900, 903, 909, 926, 0,
354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
355 /* 0x2f - 1440x900@60Hz */
356 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
357 1672, 1904, 0, 900, 903, 909, 934, 0,
358 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
359 /* 0x30 - 1440x900@75Hz */
360 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
361 1688, 1936, 0, 900, 903, 909, 942, 0,
362 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
363 /* 0x31 - 1440x900@85Hz */
364 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
365 1696, 1952, 0, 900, 903, 909, 948, 0,
366 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
367 /* 0x32 - 1440x900@120Hz RB */
368 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
369 1520, 1600, 0, 900, 903, 909, 953, 0,
370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
371 /* 0x53 - 1600x900@60Hz */
372 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
373 1704, 1800, 0, 900, 901, 904, 1000, 0,
374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
375 /* 0x33 - 1600x1200@60Hz */
376 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
377 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
379 /* 0x34 - 1600x1200@65Hz */
380 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
381 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
383 /* 0x35 - 1600x1200@70Hz */
384 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
385 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
387 /* 0x36 - 1600x1200@75Hz */
388 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
389 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
391 /* 0x37 - 1600x1200@85Hz */
392 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
393 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
395 /* 0x38 - 1600x1200@120Hz RB */
396 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
397 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
399 /* 0x39 - 1680x1050@60Hz RB */
400 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
401 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
403 /* 0x3a - 1680x1050@60Hz */
404 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
405 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
406 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
407 /* 0x3b - 1680x1050@75Hz */
408 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
409 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
410 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
411 /* 0x3c - 1680x1050@85Hz */
412 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
413 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
414 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
415 /* 0x3d - 1680x1050@120Hz RB */
416 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
417 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
419 /* 0x3e - 1792x1344@60Hz */
420 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
421 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
422 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
423 /* 0x3f - 1792x1344@75Hz */
424 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
425 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
427 /* 0x40 - 1792x1344@120Hz RB */
428 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
429 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
431 /* 0x41 - 1856x1392@60Hz */
432 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
433 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
434 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
435 /* 0x42 - 1856x1392@75Hz */
436 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
437 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
439 /* 0x43 - 1856x1392@120Hz RB */
440 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
441 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
443 /* 0x52 - 1920x1080@60Hz */
444 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
445 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
447 /* 0x44 - 1920x1200@60Hz RB */
448 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
449 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
451 /* 0x45 - 1920x1200@60Hz */
452 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
453 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
454 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
455 /* 0x46 - 1920x1200@75Hz */
456 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
457 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
458 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
459 /* 0x47 - 1920x1200@85Hz */
460 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
461 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
462 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
463 /* 0x48 - 1920x1200@120Hz RB */
464 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
465 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
467 /* 0x49 - 1920x1440@60Hz */
468 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
469 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
470 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
471 /* 0x4a - 1920x1440@75Hz */
472 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
473 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
474 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
475 /* 0x4b - 1920x1440@120Hz RB */
476 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
477 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
479 /* 0x54 - 2048x1152@60Hz */
480 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
481 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
483 /* 0x4c - 2560x1600@60Hz RB */
484 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
485 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
487 /* 0x4d - 2560x1600@60Hz */
488 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
489 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
491 /* 0x4e - 2560x1600@75Hz */
492 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
493 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
495 /* 0x4f - 2560x1600@85Hz */
496 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
497 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
498 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
499 /* 0x50 - 2560x1600@120Hz RB */
500 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
501 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
503 /* 0x57 - 4096x2160@60Hz RB */
504 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
505 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
507 /* 0x58 - 4096x2160@59.94Hz RB */
508 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
509 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
514 * These more or less come from the DMT spec. The 720x400 modes are
515 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
516 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
517 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
520 * The DMT modes have been fact-checked; the rest are mild guesses.
522 static const struct drm_display_mode edid_est_modes[] = {
523 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
524 968, 1056, 0, 600, 601, 605, 628, 0,
525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
526 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
527 896, 1024, 0, 600, 601, 603, 625, 0,
528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
529 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
530 720, 840, 0, 480, 481, 484, 500, 0,
531 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
532 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
533 704, 832, 0, 480, 489, 492, 520, 0,
534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
535 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
536 768, 864, 0, 480, 483, 486, 525, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
538 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
539 752, 800, 0, 480, 490, 492, 525, 0,
540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
541 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
542 846, 900, 0, 400, 421, 423, 449, 0,
543 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
544 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
545 846, 900, 0, 400, 412, 414, 449, 0,
546 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
547 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
548 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
550 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
551 1136, 1312, 0, 768, 769, 772, 800, 0,
552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
553 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
554 1184, 1328, 0, 768, 771, 777, 806, 0,
555 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
556 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
557 1184, 1344, 0, 768, 771, 777, 806, 0,
558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
559 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
560 1208, 1264, 0, 768, 768, 776, 817, 0,
561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
562 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
563 928, 1152, 0, 624, 625, 628, 667, 0,
564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
565 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
566 896, 1056, 0, 600, 601, 604, 625, 0,
567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
568 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
569 976, 1040, 0, 600, 637, 643, 666, 0,
570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
571 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
572 1344, 1600, 0, 864, 865, 868, 900, 0,
573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
583 static const struct minimode est3_modes[] = {
591 { 1024, 768, 85, 0 },
592 { 1152, 864, 75, 0 },
594 { 1280, 768, 60, 1 },
595 { 1280, 768, 60, 0 },
596 { 1280, 768, 75, 0 },
597 { 1280, 768, 85, 0 },
598 { 1280, 960, 60, 0 },
599 { 1280, 960, 85, 0 },
600 { 1280, 1024, 60, 0 },
601 { 1280, 1024, 85, 0 },
603 { 1360, 768, 60, 0 },
604 { 1440, 900, 60, 1 },
605 { 1440, 900, 60, 0 },
606 { 1440, 900, 75, 0 },
607 { 1440, 900, 85, 0 },
608 { 1400, 1050, 60, 1 },
609 { 1400, 1050, 60, 0 },
610 { 1400, 1050, 75, 0 },
612 { 1400, 1050, 85, 0 },
613 { 1680, 1050, 60, 1 },
614 { 1680, 1050, 60, 0 },
615 { 1680, 1050, 75, 0 },
616 { 1680, 1050, 85, 0 },
617 { 1600, 1200, 60, 0 },
618 { 1600, 1200, 65, 0 },
619 { 1600, 1200, 70, 0 },
621 { 1600, 1200, 75, 0 },
622 { 1600, 1200, 85, 0 },
623 { 1792, 1344, 60, 0 },
624 { 1792, 1344, 75, 0 },
625 { 1856, 1392, 60, 0 },
626 { 1856, 1392, 75, 0 },
627 { 1920, 1200, 60, 1 },
628 { 1920, 1200, 60, 0 },
630 { 1920, 1200, 75, 0 },
631 { 1920, 1200, 85, 0 },
632 { 1920, 1440, 60, 0 },
633 { 1920, 1440, 75, 0 },
636 static const struct minimode extra_modes[] = {
637 { 1024, 576, 60, 0 },
638 { 1366, 768, 60, 0 },
639 { 1600, 900, 60, 0 },
640 { 1680, 945, 60, 0 },
641 { 1920, 1080, 60, 0 },
642 { 2048, 1152, 60, 0 },
643 { 2048, 1536, 60, 0 },
647 * Probably taken from CEA-861 spec.
648 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
650 * Index using the VIC.
652 static const struct drm_display_mode edid_cea_modes[] = {
653 /* 0 - dummy, VICs start at 1 */
655 /* 1 - 640x480@60Hz */
656 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
657 752, 800, 0, 480, 490, 492, 525, 0,
658 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
659 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
660 /* 2 - 720x480@60Hz */
661 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
662 798, 858, 0, 480, 489, 495, 525, 0,
663 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
664 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
665 /* 3 - 720x480@60Hz */
666 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
667 798, 858, 0, 480, 489, 495, 525, 0,
668 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
669 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
670 /* 4 - 1280x720@60Hz */
671 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
672 1430, 1650, 0, 720, 725, 730, 750, 0,
673 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
674 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
675 /* 5 - 1920x1080i@60Hz */
676 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
677 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
678 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
679 DRM_MODE_FLAG_INTERLACE),
680 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
681 /* 6 - 720(1440)x480i@60Hz */
682 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
683 801, 858, 0, 480, 488, 494, 525, 0,
684 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
685 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
686 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
687 /* 7 - 720(1440)x480i@60Hz */
688 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
689 801, 858, 0, 480, 488, 494, 525, 0,
690 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
691 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
692 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
693 /* 8 - 720(1440)x240@60Hz */
694 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
695 801, 858, 0, 240, 244, 247, 262, 0,
696 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
697 DRM_MODE_FLAG_DBLCLK),
698 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
699 /* 9 - 720(1440)x240@60Hz */
700 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
701 801, 858, 0, 240, 244, 247, 262, 0,
702 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
703 DRM_MODE_FLAG_DBLCLK),
704 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
705 /* 10 - 2880x480i@60Hz */
706 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
707 3204, 3432, 0, 480, 488, 494, 525, 0,
708 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
709 DRM_MODE_FLAG_INTERLACE),
710 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
711 /* 11 - 2880x480i@60Hz */
712 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
713 3204, 3432, 0, 480, 488, 494, 525, 0,
714 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
715 DRM_MODE_FLAG_INTERLACE),
716 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
717 /* 12 - 2880x240@60Hz */
718 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
719 3204, 3432, 0, 240, 244, 247, 262, 0,
720 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
721 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
722 /* 13 - 2880x240@60Hz */
723 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
724 3204, 3432, 0, 240, 244, 247, 262, 0,
725 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
726 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
727 /* 14 - 1440x480@60Hz */
728 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
729 1596, 1716, 0, 480, 489, 495, 525, 0,
730 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
731 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
732 /* 15 - 1440x480@60Hz */
733 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
734 1596, 1716, 0, 480, 489, 495, 525, 0,
735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
736 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
737 /* 16 - 1920x1080@60Hz */
738 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
739 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
740 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
741 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
742 /* 17 - 720x576@50Hz */
743 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
744 796, 864, 0, 576, 581, 586, 625, 0,
745 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
746 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
747 /* 18 - 720x576@50Hz */
748 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
749 796, 864, 0, 576, 581, 586, 625, 0,
750 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
751 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
752 /* 19 - 1280x720@50Hz */
753 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
754 1760, 1980, 0, 720, 725, 730, 750, 0,
755 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
756 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
757 /* 20 - 1920x1080i@50Hz */
758 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
759 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
760 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
761 DRM_MODE_FLAG_INTERLACE),
762 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
763 /* 21 - 720(1440)x576i@50Hz */
764 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
765 795, 864, 0, 576, 580, 586, 625, 0,
766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
767 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
768 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
769 /* 22 - 720(1440)x576i@50Hz */
770 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
771 795, 864, 0, 576, 580, 586, 625, 0,
772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
773 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
774 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
775 /* 23 - 720(1440)x288@50Hz */
776 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
777 795, 864, 0, 288, 290, 293, 312, 0,
778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
779 DRM_MODE_FLAG_DBLCLK),
780 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
781 /* 24 - 720(1440)x288@50Hz */
782 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
783 795, 864, 0, 288, 290, 293, 312, 0,
784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
785 DRM_MODE_FLAG_DBLCLK),
786 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
787 /* 25 - 2880x576i@50Hz */
788 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
789 3180, 3456, 0, 576, 580, 586, 625, 0,
790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
791 DRM_MODE_FLAG_INTERLACE),
792 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
793 /* 26 - 2880x576i@50Hz */
794 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
795 3180, 3456, 0, 576, 580, 586, 625, 0,
796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
797 DRM_MODE_FLAG_INTERLACE),
798 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
799 /* 27 - 2880x288@50Hz */
800 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
801 3180, 3456, 0, 288, 290, 293, 312, 0,
802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
803 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
804 /* 28 - 2880x288@50Hz */
805 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
806 3180, 3456, 0, 288, 290, 293, 312, 0,
807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
808 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
809 /* 29 - 1440x576@50Hz */
810 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
811 1592, 1728, 0, 576, 581, 586, 625, 0,
812 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
813 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
814 /* 30 - 1440x576@50Hz */
815 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
816 1592, 1728, 0, 576, 581, 586, 625, 0,
817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
818 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
819 /* 31 - 1920x1080@50Hz */
820 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
821 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
822 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
823 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
824 /* 32 - 1920x1080@24Hz */
825 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
826 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
828 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
829 /* 33 - 1920x1080@25Hz */
830 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
831 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
833 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
834 /* 34 - 1920x1080@30Hz */
835 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
836 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
838 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
839 /* 35 - 2880x480@60Hz */
840 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
841 3192, 3432, 0, 480, 489, 495, 525, 0,
842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
843 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
844 /* 36 - 2880x480@60Hz */
845 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
846 3192, 3432, 0, 480, 489, 495, 525, 0,
847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
848 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
849 /* 37 - 2880x576@50Hz */
850 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
851 3184, 3456, 0, 576, 581, 586, 625, 0,
852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
853 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
854 /* 38 - 2880x576@50Hz */
855 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
856 3184, 3456, 0, 576, 581, 586, 625, 0,
857 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
858 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
859 /* 39 - 1920x1080i@50Hz */
860 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
861 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
862 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
863 DRM_MODE_FLAG_INTERLACE),
864 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
865 /* 40 - 1920x1080i@100Hz */
866 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
867 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
868 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
869 DRM_MODE_FLAG_INTERLACE),
870 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
871 /* 41 - 1280x720@100Hz */
872 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
873 1760, 1980, 0, 720, 725, 730, 750, 0,
874 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
875 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
876 /* 42 - 720x576@100Hz */
877 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
878 796, 864, 0, 576, 581, 586, 625, 0,
879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
880 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
881 /* 43 - 720x576@100Hz */
882 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
883 796, 864, 0, 576, 581, 586, 625, 0,
884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
885 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
886 /* 44 - 720(1440)x576i@100Hz */
887 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
888 795, 864, 0, 576, 580, 586, 625, 0,
889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
890 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
891 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
892 /* 45 - 720(1440)x576i@100Hz */
893 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
894 795, 864, 0, 576, 580, 586, 625, 0,
895 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
896 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
897 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
898 /* 46 - 1920x1080i@120Hz */
899 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
900 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
902 DRM_MODE_FLAG_INTERLACE),
903 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
904 /* 47 - 1280x720@120Hz */
905 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
906 1430, 1650, 0, 720, 725, 730, 750, 0,
907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
908 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
909 /* 48 - 720x480@120Hz */
910 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
911 798, 858, 0, 480, 489, 495, 525, 0,
912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
913 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
914 /* 49 - 720x480@120Hz */
915 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
916 798, 858, 0, 480, 489, 495, 525, 0,
917 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
918 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
919 /* 50 - 720(1440)x480i@120Hz */
920 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
921 801, 858, 0, 480, 488, 494, 525, 0,
922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
923 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
924 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
925 /* 51 - 720(1440)x480i@120Hz */
926 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
927 801, 858, 0, 480, 488, 494, 525, 0,
928 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
929 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
930 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
931 /* 52 - 720x576@200Hz */
932 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
933 796, 864, 0, 576, 581, 586, 625, 0,
934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
935 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
936 /* 53 - 720x576@200Hz */
937 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
938 796, 864, 0, 576, 581, 586, 625, 0,
939 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
940 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
941 /* 54 - 720(1440)x576i@200Hz */
942 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
943 795, 864, 0, 576, 580, 586, 625, 0,
944 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
945 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
946 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
947 /* 55 - 720(1440)x576i@200Hz */
948 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
949 795, 864, 0, 576, 580, 586, 625, 0,
950 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
951 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
952 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
953 /* 56 - 720x480@240Hz */
954 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
955 798, 858, 0, 480, 489, 495, 525, 0,
956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
957 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
958 /* 57 - 720x480@240Hz */
959 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
960 798, 858, 0, 480, 489, 495, 525, 0,
961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
962 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
963 /* 58 - 720(1440)x480i@240Hz */
964 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
965 801, 858, 0, 480, 488, 494, 525, 0,
966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
967 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
968 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
969 /* 59 - 720(1440)x480i@240Hz */
970 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
971 801, 858, 0, 480, 488, 494, 525, 0,
972 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
973 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
974 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
975 /* 60 - 1280x720@24Hz */
976 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
977 3080, 3300, 0, 720, 725, 730, 750, 0,
978 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
979 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
980 /* 61 - 1280x720@25Hz */
981 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
982 3740, 3960, 0, 720, 725, 730, 750, 0,
983 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
984 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
985 /* 62 - 1280x720@30Hz */
986 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
987 3080, 3300, 0, 720, 725, 730, 750, 0,
988 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
989 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
990 /* 63 - 1920x1080@120Hz */
991 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
992 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
993 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
994 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
995 /* 64 - 1920x1080@100Hz */
996 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
997 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
998 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
999 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1003 * HDMI 1.4 4k modes. Index using the VIC.
1005 static const struct drm_display_mode edid_4k_modes[] = {
1006 /* 0 - dummy, VICs start at 1 */
1008 /* 1 - 3840x2160@30Hz */
1009 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1010 3840, 4016, 4104, 4400, 0,
1011 2160, 2168, 2178, 2250, 0,
1012 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1014 /* 2 - 3840x2160@25Hz */
1015 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1016 3840, 4896, 4984, 5280, 0,
1017 2160, 2168, 2178, 2250, 0,
1018 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1020 /* 3 - 3840x2160@24Hz */
1021 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1022 3840, 5116, 5204, 5500, 0,
1023 2160, 2168, 2178, 2250, 0,
1024 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1026 /* 4 - 4096x2160@24Hz (SMPTE) */
1027 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1028 4096, 5116, 5204, 5500, 0,
1029 2160, 2168, 2178, 2250, 0,
1030 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1034 /*** DDC fetch and block validation ***/
1036 static const u8 edid_header[] = {
1037 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1041 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1042 * @raw_edid: pointer to raw base EDID block
1044 * Sanity check the header of the base EDID block.
1046 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1048 int drm_edid_header_is_valid(const u8 *raw_edid)
1052 for (i = 0; i < sizeof(edid_header); i++)
1053 if (raw_edid[i] == edid_header[i])
1058 EXPORT_SYMBOL(drm_edid_header_is_valid);
1060 static int edid_fixup __read_mostly = 6;
1061 module_param_named(edid_fixup, edid_fixup, int, 0400);
1062 MODULE_PARM_DESC(edid_fixup,
1063 "Minimum number of valid EDID header bytes (0-8, default 6)");
1065 static void drm_get_displayid(struct drm_connector *connector,
1068 static int drm_edid_block_checksum(const u8 *raw_edid)
1072 for (i = 0; i < EDID_LENGTH; i++)
1073 csum += raw_edid[i];
1078 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1080 if (memchr_inv(in_edid, 0, length))
1087 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1088 * @raw_edid: pointer to raw EDID block
1089 * @block: type of block to validate (0 for base, extension otherwise)
1090 * @print_bad_edid: if true, dump bad EDID blocks to the console
1091 * @edid_corrupt: if true, the header or checksum is invalid
1093 * Validate a base or extension EDID block and optionally dump bad blocks to
1096 * Return: True if the block is valid, false otherwise.
1098 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1102 struct edid *edid = (struct edid *)raw_edid;
1104 if (WARN_ON(!raw_edid))
1107 if (edid_fixup > 8 || edid_fixup < 0)
1111 int score = drm_edid_header_is_valid(raw_edid);
1114 *edid_corrupt = false;
1115 } else if (score >= edid_fixup) {
1116 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1117 * The corrupt flag needs to be set here otherwise, the
1118 * fix-up code here will correct the problem, the
1119 * checksum is correct and the test fails
1122 *edid_corrupt = true;
1123 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1124 memcpy(raw_edid, edid_header, sizeof(edid_header));
1127 *edid_corrupt = true;
1132 csum = drm_edid_block_checksum(raw_edid);
1135 *edid_corrupt = true;
1137 /* allow CEA to slide through, switches mangle this */
1138 if (raw_edid[0] == CEA_EXT) {
1139 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1140 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1143 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1149 /* per-block-type checks */
1150 switch (raw_edid[0]) {
1152 if (edid->version != 1) {
1153 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1157 if (edid->revision > 4)
1158 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1168 if (print_bad_edid) {
1169 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1170 printk(KERN_NOTICE "EDID block is all zeroes\n");
1172 printk(KERN_NOTICE "Raw EDID:\n");
1173 print_hex_dump(KERN_NOTICE,
1174 " \t", DUMP_PREFIX_NONE, 16, 1,
1175 raw_edid, EDID_LENGTH, false);
1180 EXPORT_SYMBOL(drm_edid_block_valid);
1183 * drm_edid_is_valid - sanity check EDID data
1186 * Sanity-check an entire EDID record (including extensions)
1188 * Return: True if the EDID data is valid, false otherwise.
1190 bool drm_edid_is_valid(struct edid *edid)
1193 u8 *raw = (u8 *)edid;
1198 for (i = 0; i <= edid->extensions; i++)
1199 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1204 EXPORT_SYMBOL(drm_edid_is_valid);
1206 #define DDC_SEGMENT_ADDR 0x30
1208 * drm_do_probe_ddc_edid() - get EDID information via I2C
1209 * @data: I2C device adapter
1210 * @buf: EDID data buffer to be filled
1211 * @block: 128 byte EDID block to start fetching from
1212 * @len: EDID data buffer length to fetch
1214 * Try to fetch EDID information by calling I2C driver functions.
1216 * Return: 0 on success or -1 on failure.
1219 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1221 struct i2c_adapter *adapter = data;
1222 unsigned char start = block * EDID_LENGTH;
1223 unsigned char segment = block >> 1;
1224 unsigned char xfers = segment ? 3 : 2;
1225 int ret, retries = 5;
1228 * The core I2C driver will automatically retry the transfer if the
1229 * adapter reports EAGAIN. However, we find that bit-banging transfers
1230 * are susceptible to errors under a heavily loaded machine and
1231 * generate spurious NAKs and timeouts. Retrying the transfer
1232 * of the individual block a few times seems to overcome this.
1235 struct i2c_msg msgs[] = {
1237 .addr = DDC_SEGMENT_ADDR,
1255 * Avoid sending the segment addr to not upset non-compliant
1258 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1260 if (ret == -ENXIO) {
1261 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1265 } while (ret != xfers && --retries);
1267 return ret == xfers ? 0 : -1;
1270 static void connector_bad_edid(struct drm_connector *connector,
1271 u8 *edid, int num_blocks)
1275 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1278 dev_warn(connector->dev->dev,
1279 "%s: EDID is invalid:\n",
1281 for (i = 0; i < num_blocks; i++) {
1282 u8 *block = edid + i * EDID_LENGTH;
1285 if (drm_edid_is_zero(block, EDID_LENGTH))
1286 sprintf(prefix, "\t[%02x] ZERO ", i);
1287 else if (!drm_edid_block_valid(block, i, false, NULL))
1288 sprintf(prefix, "\t[%02x] BAD ", i);
1290 sprintf(prefix, "\t[%02x] GOOD ", i);
1292 print_hex_dump(KERN_WARNING,
1293 prefix, DUMP_PREFIX_NONE, 16, 1,
1294 block, EDID_LENGTH, false);
1299 * drm_do_get_edid - get EDID data using a custom EDID block read function
1300 * @connector: connector we're probing
1301 * @get_edid_block: EDID block read function
1302 * @data: private data passed to the block read function
1304 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1305 * exposes a different interface to read EDID blocks this function can be used
1306 * to get EDID data using a custom block read function.
1308 * As in the general case the DDC bus is accessible by the kernel at the I2C
1309 * level, drivers must make all reasonable efforts to expose it as an I2C
1310 * adapter and use drm_get_edid() instead of abusing this function.
1312 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1314 struct edid *drm_do_get_edid(struct drm_connector *connector,
1315 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1319 int i, j = 0, valid_extensions = 0;
1322 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1325 /* base block fetch */
1326 for (i = 0; i < 4; i++) {
1327 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1329 if (drm_edid_block_valid(edid, 0, false,
1330 &connector->edid_corrupt))
1332 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1333 connector->null_edid_counter++;
1340 /* if there's no extensions, we're done */
1341 valid_extensions = edid[0x7e];
1342 if (valid_extensions == 0)
1343 return (struct edid *)edid;
1345 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1350 for (j = 1; j <= edid[0x7e]; j++) {
1351 u8 *block = edid + j * EDID_LENGTH;
1353 for (i = 0; i < 4; i++) {
1354 if (get_edid_block(data, block, j, EDID_LENGTH))
1356 if (drm_edid_block_valid(block, j, false, NULL))
1364 if (valid_extensions != edid[0x7e]) {
1367 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1369 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1370 edid[0x7e] = valid_extensions;
1372 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1377 for (i = 0; i <= edid[0x7e]; i++) {
1378 u8 *block = edid + i * EDID_LENGTH;
1380 if (!drm_edid_block_valid(block, i, false, NULL))
1383 memcpy(base, block, EDID_LENGTH);
1384 base += EDID_LENGTH;
1391 return (struct edid *)edid;
1394 connector_bad_edid(connector, edid, 1);
1399 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1402 * drm_probe_ddc() - probe DDC presence
1403 * @adapter: I2C adapter to probe
1405 * Return: True on success, false on failure.
1408 drm_probe_ddc(struct i2c_adapter *adapter)
1412 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1414 EXPORT_SYMBOL(drm_probe_ddc);
1417 * drm_get_edid - get EDID data, if available
1418 * @connector: connector we're probing
1419 * @adapter: I2C adapter to use for DDC
1421 * Poke the given I2C channel to grab EDID data if possible. If found,
1422 * attach it to the connector.
1424 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1426 struct edid *drm_get_edid(struct drm_connector *connector,
1427 struct i2c_adapter *adapter)
1431 if (connector->force == DRM_FORCE_OFF)
1434 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1437 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1439 drm_get_displayid(connector, edid);
1442 EXPORT_SYMBOL(drm_get_edid);
1445 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1446 * @connector: connector we're probing
1447 * @adapter: I2C adapter to use for DDC
1449 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1450 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1451 * switch DDC to the GPU which is retrieving EDID.
1453 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1455 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1456 struct i2c_adapter *adapter)
1458 struct pci_dev *pdev = connector->dev->pdev;
1461 vga_switcheroo_lock_ddc(pdev);
1462 edid = drm_get_edid(connector, adapter);
1463 vga_switcheroo_unlock_ddc(pdev);
1467 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1470 * drm_edid_duplicate - duplicate an EDID and the extensions
1471 * @edid: EDID to duplicate
1473 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1475 struct edid *drm_edid_duplicate(const struct edid *edid)
1477 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1479 EXPORT_SYMBOL(drm_edid_duplicate);
1481 /*** EDID parsing ***/
1484 * edid_vendor - match a string against EDID's obfuscated vendor field
1485 * @edid: EDID to match
1486 * @vendor: vendor string
1488 * Returns true if @vendor is in @edid, false otherwise
1490 static bool edid_vendor(struct edid *edid, const char *vendor)
1492 char edid_vendor[3];
1494 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1495 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1496 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1497 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1499 return !strncmp(edid_vendor, vendor, 3);
1503 * edid_get_quirks - return quirk flags for a given EDID
1504 * @edid: EDID to process
1506 * This tells subsequent routines what fixes they need to apply.
1508 static u32 edid_get_quirks(struct edid *edid)
1510 const struct edid_quirk *quirk;
1513 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1514 quirk = &edid_quirk_list[i];
1516 if (edid_vendor(edid, quirk->vendor) &&
1517 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1518 return quirk->quirks;
1524 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1525 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1528 * edid_fixup_preferred - set preferred modes based on quirk list
1529 * @connector: has mode list to fix up
1530 * @quirks: quirks list
1532 * Walk the mode list for @connector, clearing the preferred status
1533 * on existing modes and setting it anew for the right mode ala @quirks.
1535 static void edid_fixup_preferred(struct drm_connector *connector,
1538 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1539 int target_refresh = 0;
1540 int cur_vrefresh, preferred_vrefresh;
1542 if (list_empty(&connector->probed_modes))
1545 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1546 target_refresh = 60;
1547 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1548 target_refresh = 75;
1550 preferred_mode = list_first_entry(&connector->probed_modes,
1551 struct drm_display_mode, head);
1553 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1554 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1556 if (cur_mode == preferred_mode)
1559 /* Largest mode is preferred */
1560 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1561 preferred_mode = cur_mode;
1563 cur_vrefresh = cur_mode->vrefresh ?
1564 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1565 preferred_vrefresh = preferred_mode->vrefresh ?
1566 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1567 /* At a given size, try to get closest to target refresh */
1568 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1569 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1570 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1571 preferred_mode = cur_mode;
1575 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1579 mode_is_rb(const struct drm_display_mode *mode)
1581 return (mode->htotal - mode->hdisplay == 160) &&
1582 (mode->hsync_end - mode->hdisplay == 80) &&
1583 (mode->hsync_end - mode->hsync_start == 32) &&
1584 (mode->vsync_start - mode->vdisplay == 3);
1588 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1589 * @dev: Device to duplicate against
1590 * @hsize: Mode width
1591 * @vsize: Mode height
1592 * @fresh: Mode refresh rate
1593 * @rb: Mode reduced-blanking-ness
1595 * Walk the DMT mode list looking for a match for the given parameters.
1597 * Return: A newly allocated copy of the mode, or NULL if not found.
1599 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1600 int hsize, int vsize, int fresh,
1605 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1606 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1607 if (hsize != ptr->hdisplay)
1609 if (vsize != ptr->vdisplay)
1611 if (fresh != drm_mode_vrefresh(ptr))
1613 if (rb != mode_is_rb(ptr))
1616 return drm_mode_duplicate(dev, ptr);
1621 EXPORT_SYMBOL(drm_mode_find_dmt);
1623 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1626 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1630 u8 *det_base = ext + d;
1633 for (i = 0; i < n; i++)
1634 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1638 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1640 unsigned int i, n = min((int)ext[0x02], 6);
1641 u8 *det_base = ext + 5;
1644 return; /* unknown version */
1646 for (i = 0; i < n; i++)
1647 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1651 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1654 struct edid *edid = (struct edid *)raw_edid;
1659 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1660 cb(&(edid->detailed_timings[i]), closure);
1662 for (i = 1; i <= raw_edid[0x7e]; i++) {
1663 u8 *ext = raw_edid + (i * EDID_LENGTH);
1666 cea_for_each_detailed_block(ext, cb, closure);
1669 vtb_for_each_detailed_block(ext, cb, closure);
1678 is_rb(struct detailed_timing *t, void *data)
1681 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1683 *(bool *)data = true;
1686 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1688 drm_monitor_supports_rb(struct edid *edid)
1690 if (edid->revision >= 4) {
1692 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1696 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1700 find_gtf2(struct detailed_timing *t, void *data)
1703 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1707 /* Secondary GTF curve kicks in above some break frequency */
1709 drm_gtf2_hbreak(struct edid *edid)
1712 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1713 return r ? (r[12] * 2) : 0;
1717 drm_gtf2_2c(struct edid *edid)
1720 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1721 return r ? r[13] : 0;
1725 drm_gtf2_m(struct edid *edid)
1728 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1729 return r ? (r[15] << 8) + r[14] : 0;
1733 drm_gtf2_k(struct edid *edid)
1736 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1737 return r ? r[16] : 0;
1741 drm_gtf2_2j(struct edid *edid)
1744 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1745 return r ? r[17] : 0;
1749 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1750 * @edid: EDID block to scan
1752 static int standard_timing_level(struct edid *edid)
1754 if (edid->revision >= 2) {
1755 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1757 if (drm_gtf2_hbreak(edid))
1765 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1766 * monitors fill with ascii space (0x20) instead.
1769 bad_std_timing(u8 a, u8 b)
1771 return (a == 0x00 && b == 0x00) ||
1772 (a == 0x01 && b == 0x01) ||
1773 (a == 0x20 && b == 0x20);
1777 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
1778 * @connector: connector of for the EDID block
1779 * @edid: EDID block to scan
1780 * @t: standard timing params
1782 * Take the standard timing params (in this case width, aspect, and refresh)
1783 * and convert them into a real mode using CVT/GTF/DMT.
1785 static struct drm_display_mode *
1786 drm_mode_std(struct drm_connector *connector, struct edid *edid,
1787 struct std_timing *t)
1789 struct drm_device *dev = connector->dev;
1790 struct drm_display_mode *m, *mode = NULL;
1793 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
1794 >> EDID_TIMING_ASPECT_SHIFT;
1795 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
1796 >> EDID_TIMING_VFREQ_SHIFT;
1797 int timing_level = standard_timing_level(edid);
1799 if (bad_std_timing(t->hsize, t->vfreq_aspect))
1802 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1803 hsize = t->hsize * 8 + 248;
1804 /* vrefresh_rate = vfreq + 60 */
1805 vrefresh_rate = vfreq + 60;
1806 /* the vdisplay is calculated based on the aspect ratio */
1807 if (aspect_ratio == 0) {
1808 if (edid->revision < 3)
1811 vsize = (hsize * 10) / 16;
1812 } else if (aspect_ratio == 1)
1813 vsize = (hsize * 3) / 4;
1814 else if (aspect_ratio == 2)
1815 vsize = (hsize * 4) / 5;
1817 vsize = (hsize * 9) / 16;
1819 /* HDTV hack, part 1 */
1820 if (vrefresh_rate == 60 &&
1821 ((hsize == 1360 && vsize == 765) ||
1822 (hsize == 1368 && vsize == 769))) {
1828 * If this connector already has a mode for this size and refresh
1829 * rate (because it came from detailed or CVT info), use that
1830 * instead. This way we don't have to guess at interlace or
1833 list_for_each_entry(m, &connector->probed_modes, head)
1834 if (m->hdisplay == hsize && m->vdisplay == vsize &&
1835 drm_mode_vrefresh(m) == vrefresh_rate)
1838 /* HDTV hack, part 2 */
1839 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
1840 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
1842 mode->hdisplay = 1366;
1843 mode->hsync_start = mode->hsync_start - 1;
1844 mode->hsync_end = mode->hsync_end - 1;
1848 /* check whether it can be found in default mode table */
1849 if (drm_monitor_supports_rb(edid)) {
1850 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
1855 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
1859 /* okay, generate it */
1860 switch (timing_level) {
1864 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1868 * This is potentially wrong if there's ever a monitor with
1869 * more than one ranges section, each claiming a different
1870 * secondary GTF curve. Please don't do that.
1872 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1875 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
1876 drm_mode_destroy(dev, mode);
1877 mode = drm_gtf_mode_complex(dev, hsize, vsize,
1878 vrefresh_rate, 0, 0,
1886 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
1894 * EDID is delightfully ambiguous about how interlaced modes are to be
1895 * encoded. Our internal representation is of frame height, but some
1896 * HDTV detailed timings are encoded as field height.
1898 * The format list here is from CEA, in frame size. Technically we
1899 * should be checking refresh rate too. Whatever.
1902 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
1903 struct detailed_pixel_timing *pt)
1906 static const struct {
1908 } cea_interlaced[] = {
1918 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
1921 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
1922 if ((mode->hdisplay == cea_interlaced[i].w) &&
1923 (mode->vdisplay == cea_interlaced[i].h / 2)) {
1924 mode->vdisplay *= 2;
1925 mode->vsync_start *= 2;
1926 mode->vsync_end *= 2;
1932 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1936 * drm_mode_detailed - create a new mode from an EDID detailed timing section
1937 * @dev: DRM device (needed to create new mode)
1939 * @timing: EDID detailed timing info
1940 * @quirks: quirks to apply
1942 * An EDID detailed timing block contains enough info for us to create and
1943 * return a new struct drm_display_mode.
1945 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
1947 struct detailed_timing *timing,
1950 struct drm_display_mode *mode;
1951 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
1952 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
1953 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
1954 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
1955 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
1956 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
1957 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
1958 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
1959 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
1961 /* ignore tiny modes */
1962 if (hactive < 64 || vactive < 64)
1965 if (pt->misc & DRM_EDID_PT_STEREO) {
1966 DRM_DEBUG_KMS("stereo mode not supported\n");
1969 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
1970 DRM_DEBUG_KMS("composite sync not supported\n");
1973 /* it is incorrect if hsync/vsync width is zero */
1974 if (!hsync_pulse_width || !vsync_pulse_width) {
1975 DRM_DEBUG_KMS("Incorrect Detailed timing. "
1976 "Wrong Hsync/Vsync pulse width\n");
1980 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
1981 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
1988 mode = drm_mode_create(dev);
1992 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
1993 timing->pixel_clock = cpu_to_le16(1088);
1995 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
1997 mode->hdisplay = hactive;
1998 mode->hsync_start = mode->hdisplay + hsync_offset;
1999 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2000 mode->htotal = mode->hdisplay + hblank;
2002 mode->vdisplay = vactive;
2003 mode->vsync_start = mode->vdisplay + vsync_offset;
2004 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2005 mode->vtotal = mode->vdisplay + vblank;
2007 /* Some EDIDs have bogus h/vtotal values */
2008 if (mode->hsync_end > mode->htotal)
2009 mode->htotal = mode->hsync_end + 1;
2010 if (mode->vsync_end > mode->vtotal)
2011 mode->vtotal = mode->vsync_end + 1;
2013 drm_mode_do_interlace_quirk(mode, pt);
2015 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2016 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2019 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2020 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2021 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2022 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2025 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2026 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2028 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2029 mode->width_mm *= 10;
2030 mode->height_mm *= 10;
2033 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2034 mode->width_mm = edid->width_cm * 10;
2035 mode->height_mm = edid->height_cm * 10;
2038 mode->type = DRM_MODE_TYPE_DRIVER;
2039 mode->vrefresh = drm_mode_vrefresh(mode);
2040 drm_mode_set_name(mode);
2046 mode_in_hsync_range(const struct drm_display_mode *mode,
2047 struct edid *edid, u8 *t)
2049 int hsync, hmin, hmax;
2052 if (edid->revision >= 4)
2053 hmin += ((t[4] & 0x04) ? 255 : 0);
2055 if (edid->revision >= 4)
2056 hmax += ((t[4] & 0x08) ? 255 : 0);
2057 hsync = drm_mode_hsync(mode);
2059 return (hsync <= hmax && hsync >= hmin);
2063 mode_in_vsync_range(const struct drm_display_mode *mode,
2064 struct edid *edid, u8 *t)
2066 int vsync, vmin, vmax;
2069 if (edid->revision >= 4)
2070 vmin += ((t[4] & 0x01) ? 255 : 0);
2072 if (edid->revision >= 4)
2073 vmax += ((t[4] & 0x02) ? 255 : 0);
2074 vsync = drm_mode_vrefresh(mode);
2076 return (vsync <= vmax && vsync >= vmin);
2080 range_pixel_clock(struct edid *edid, u8 *t)
2083 if (t[9] == 0 || t[9] == 255)
2086 /* 1.4 with CVT support gives us real precision, yay */
2087 if (edid->revision >= 4 && t[10] == 0x04)
2088 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2090 /* 1.3 is pathetic, so fuzz up a bit */
2091 return t[9] * 10000 + 5001;
2095 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2096 struct detailed_timing *timing)
2099 u8 *t = (u8 *)timing;
2101 if (!mode_in_hsync_range(mode, edid, t))
2104 if (!mode_in_vsync_range(mode, edid, t))
2107 if ((max_clock = range_pixel_clock(edid, t)))
2108 if (mode->clock > max_clock)
2111 /* 1.4 max horizontal check */
2112 if (edid->revision >= 4 && t[10] == 0x04)
2113 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2116 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2122 static bool valid_inferred_mode(const struct drm_connector *connector,
2123 const struct drm_display_mode *mode)
2125 const struct drm_display_mode *m;
2128 list_for_each_entry(m, &connector->probed_modes, head) {
2129 if (mode->hdisplay == m->hdisplay &&
2130 mode->vdisplay == m->vdisplay &&
2131 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2132 return false; /* duplicated */
2133 if (mode->hdisplay <= m->hdisplay &&
2134 mode->vdisplay <= m->vdisplay)
2141 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2142 struct detailed_timing *timing)
2145 struct drm_display_mode *newmode;
2146 struct drm_device *dev = connector->dev;
2148 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2149 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2150 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2151 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2153 drm_mode_probed_add(connector, newmode);
2162 /* fix up 1366x768 mode from 1368x768;
2163 * GFT/CVT can't express 1366 width which isn't dividable by 8
2165 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2167 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2168 mode->hdisplay = 1366;
2169 mode->hsync_start--;
2171 drm_mode_set_name(mode);
2176 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2177 struct detailed_timing *timing)
2180 struct drm_display_mode *newmode;
2181 struct drm_device *dev = connector->dev;
2183 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2184 const struct minimode *m = &extra_modes[i];
2185 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2189 drm_mode_fixup_1366x768(newmode);
2190 if (!mode_in_range(newmode, edid, timing) ||
2191 !valid_inferred_mode(connector, newmode)) {
2192 drm_mode_destroy(dev, newmode);
2196 drm_mode_probed_add(connector, newmode);
2204 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2205 struct detailed_timing *timing)
2208 struct drm_display_mode *newmode;
2209 struct drm_device *dev = connector->dev;
2210 bool rb = drm_monitor_supports_rb(edid);
2212 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2213 const struct minimode *m = &extra_modes[i];
2214 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2218 drm_mode_fixup_1366x768(newmode);
2219 if (!mode_in_range(newmode, edid, timing) ||
2220 !valid_inferred_mode(connector, newmode)) {
2221 drm_mode_destroy(dev, newmode);
2225 drm_mode_probed_add(connector, newmode);
2233 do_inferred_modes(struct detailed_timing *timing, void *c)
2235 struct detailed_mode_closure *closure = c;
2236 struct detailed_non_pixel *data = &timing->data.other_data;
2237 struct detailed_data_monitor_range *range = &data->data.range;
2239 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2242 closure->modes += drm_dmt_modes_for_range(closure->connector,
2246 if (!version_greater(closure->edid, 1, 1))
2247 return; /* GTF not defined yet */
2249 switch (range->flags) {
2250 case 0x02: /* secondary gtf, XXX could do more */
2251 case 0x00: /* default gtf */
2252 closure->modes += drm_gtf_modes_for_range(closure->connector,
2256 case 0x04: /* cvt, only in 1.4+ */
2257 if (!version_greater(closure->edid, 1, 3))
2260 closure->modes += drm_cvt_modes_for_range(closure->connector,
2264 case 0x01: /* just the ranges, no formula */
2271 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2273 struct detailed_mode_closure closure = {
2274 .connector = connector,
2278 if (version_greater(edid, 1, 0))
2279 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2282 return closure.modes;
2286 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2288 int i, j, m, modes = 0;
2289 struct drm_display_mode *mode;
2290 u8 *est = ((u8 *)timing) + 6;
2292 for (i = 0; i < 6; i++) {
2293 for (j = 7; j >= 0; j--) {
2294 m = (i * 8) + (7 - j);
2295 if (m >= ARRAY_SIZE(est3_modes))
2297 if (est[i] & (1 << j)) {
2298 mode = drm_mode_find_dmt(connector->dev,
2304 drm_mode_probed_add(connector, mode);
2315 do_established_modes(struct detailed_timing *timing, void *c)
2317 struct detailed_mode_closure *closure = c;
2318 struct detailed_non_pixel *data = &timing->data.other_data;
2320 if (data->type == EDID_DETAIL_EST_TIMINGS)
2321 closure->modes += drm_est3_modes(closure->connector, timing);
2325 * add_established_modes - get est. modes from EDID and add them
2326 * @connector: connector to add mode(s) to
2327 * @edid: EDID block to scan
2329 * Each EDID block contains a bitmap of the supported "established modes" list
2330 * (defined above). Tease them out and add them to the global modes list.
2333 add_established_modes(struct drm_connector *connector, struct edid *edid)
2335 struct drm_device *dev = connector->dev;
2336 unsigned long est_bits = edid->established_timings.t1 |
2337 (edid->established_timings.t2 << 8) |
2338 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2340 struct detailed_mode_closure closure = {
2341 .connector = connector,
2345 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2346 if (est_bits & (1<<i)) {
2347 struct drm_display_mode *newmode;
2348 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2350 drm_mode_probed_add(connector, newmode);
2356 if (version_greater(edid, 1, 0))
2357 drm_for_each_detailed_block((u8 *)edid,
2358 do_established_modes, &closure);
2360 return modes + closure.modes;
2364 do_standard_modes(struct detailed_timing *timing, void *c)
2366 struct detailed_mode_closure *closure = c;
2367 struct detailed_non_pixel *data = &timing->data.other_data;
2368 struct drm_connector *connector = closure->connector;
2369 struct edid *edid = closure->edid;
2371 if (data->type == EDID_DETAIL_STD_MODES) {
2373 for (i = 0; i < 6; i++) {
2374 struct std_timing *std;
2375 struct drm_display_mode *newmode;
2377 std = &data->data.timings[i];
2378 newmode = drm_mode_std(connector, edid, std);
2380 drm_mode_probed_add(connector, newmode);
2388 * add_standard_modes - get std. modes from EDID and add them
2389 * @connector: connector to add mode(s) to
2390 * @edid: EDID block to scan
2392 * Standard modes can be calculated using the appropriate standard (DMT,
2393 * GTF or CVT. Grab them from @edid and add them to the list.
2396 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2399 struct detailed_mode_closure closure = {
2400 .connector = connector,
2404 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2405 struct drm_display_mode *newmode;
2407 newmode = drm_mode_std(connector, edid,
2408 &edid->standard_timings[i]);
2410 drm_mode_probed_add(connector, newmode);
2415 if (version_greater(edid, 1, 0))
2416 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2419 /* XXX should also look for standard codes in VTB blocks */
2421 return modes + closure.modes;
2424 static int drm_cvt_modes(struct drm_connector *connector,
2425 struct detailed_timing *timing)
2427 int i, j, modes = 0;
2428 struct drm_display_mode *newmode;
2429 struct drm_device *dev = connector->dev;
2430 struct cvt_timing *cvt;
2431 const int rates[] = { 60, 85, 75, 60, 50 };
2432 const u8 empty[3] = { 0, 0, 0 };
2434 for (i = 0; i < 4; i++) {
2435 int uninitialized_var(width), height;
2436 cvt = &(timing->data.other_data.data.cvt[i]);
2438 if (!memcmp(cvt->code, empty, 3))
2441 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2442 switch (cvt->code[1] & 0x0c) {
2444 width = height * 4 / 3;
2447 width = height * 16 / 9;
2450 width = height * 16 / 10;
2453 width = height * 15 / 9;
2457 for (j = 1; j < 5; j++) {
2458 if (cvt->code[2] & (1 << j)) {
2459 newmode = drm_cvt_mode(dev, width, height,
2463 drm_mode_probed_add(connector, newmode);
2474 do_cvt_mode(struct detailed_timing *timing, void *c)
2476 struct detailed_mode_closure *closure = c;
2477 struct detailed_non_pixel *data = &timing->data.other_data;
2479 if (data->type == EDID_DETAIL_CVT_3BYTE)
2480 closure->modes += drm_cvt_modes(closure->connector, timing);
2484 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2486 struct detailed_mode_closure closure = {
2487 .connector = connector,
2491 if (version_greater(edid, 1, 2))
2492 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2494 /* XXX should also look for CVT codes in VTB blocks */
2496 return closure.modes;
2499 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2502 do_detailed_mode(struct detailed_timing *timing, void *c)
2504 struct detailed_mode_closure *closure = c;
2505 struct drm_display_mode *newmode;
2507 if (timing->pixel_clock) {
2508 newmode = drm_mode_detailed(closure->connector->dev,
2509 closure->edid, timing,
2514 if (closure->preferred)
2515 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2518 * Detailed modes are limited to 10kHz pixel clock resolution,
2519 * so fix up anything that looks like CEA/HDMI mode, but the clock
2520 * is just slightly off.
2522 fixup_detailed_cea_mode_clock(newmode);
2524 drm_mode_probed_add(closure->connector, newmode);
2526 closure->preferred = 0;
2531 * add_detailed_modes - Add modes from detailed timings
2532 * @connector: attached connector
2533 * @edid: EDID block to scan
2534 * @quirks: quirks to apply
2537 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2540 struct detailed_mode_closure closure = {
2541 .connector = connector,
2547 if (closure.preferred && !version_greater(edid, 1, 3))
2549 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2551 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2553 return closure.modes;
2556 #define AUDIO_BLOCK 0x01
2557 #define VIDEO_BLOCK 0x02
2558 #define VENDOR_BLOCK 0x03
2559 #define SPEAKER_BLOCK 0x04
2560 #define VIDEO_CAPABILITY_BLOCK 0x07
2561 #define EDID_BASIC_AUDIO (1 << 6)
2562 #define EDID_CEA_YCRCB444 (1 << 5)
2563 #define EDID_CEA_YCRCB422 (1 << 4)
2564 #define EDID_CEA_VCDB_QS (1 << 6)
2567 * Search EDID for CEA extension block.
2569 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
2571 u8 *edid_ext = NULL;
2574 /* No EDID or EDID extensions */
2575 if (edid == NULL || edid->extensions == 0)
2578 /* Find CEA extension */
2579 for (i = 0; i < edid->extensions; i++) {
2580 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2581 if (edid_ext[0] == ext_id)
2585 if (i == edid->extensions)
2591 static u8 *drm_find_cea_extension(struct edid *edid)
2593 return drm_find_edid_extension(edid, CEA_EXT);
2596 static u8 *drm_find_displayid_extension(struct edid *edid)
2598 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2602 * Calculate the alternate clock for the CEA mode
2603 * (60Hz vs. 59.94Hz etc.)
2606 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2608 unsigned int clock = cea_mode->clock;
2610 if (cea_mode->vrefresh % 6 != 0)
2614 * edid_cea_modes contains the 59.94Hz
2615 * variant for 240 and 480 line modes,
2616 * and the 60Hz variant otherwise.
2618 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2619 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2621 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2627 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2630 * For certain VICs the spec allows the vertical
2631 * front porch to vary by one or two lines.
2633 * cea_modes[] stores the variant with the shortest
2634 * vertical front porch. We can adjust the mode to
2635 * get the other variants by simply increasing the
2636 * vertical front porch length.
2638 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2639 edid_cea_modes[9].vtotal != 262 ||
2640 edid_cea_modes[12].vtotal != 262 ||
2641 edid_cea_modes[13].vtotal != 262 ||
2642 edid_cea_modes[23].vtotal != 312 ||
2643 edid_cea_modes[24].vtotal != 312 ||
2644 edid_cea_modes[27].vtotal != 312 ||
2645 edid_cea_modes[28].vtotal != 312);
2647 if (((vic == 8 || vic == 9 ||
2648 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2649 ((vic == 23 || vic == 24 ||
2650 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2651 mode->vsync_start++;
2661 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2662 unsigned int clock_tolerance)
2666 if (!to_match->clock)
2669 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2670 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2671 unsigned int clock1, clock2;
2673 /* Check both 60Hz and 59.94Hz */
2674 clock1 = cea_mode.clock;
2675 clock2 = cea_mode_alternate_clock(&cea_mode);
2677 if (abs(to_match->clock - clock1) > clock_tolerance &&
2678 abs(to_match->clock - clock2) > clock_tolerance)
2682 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2684 } while (cea_mode_alternate_timings(vic, &cea_mode));
2691 * drm_match_cea_mode - look for a CEA mode matching given mode
2692 * @to_match: display mode
2694 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2697 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2701 if (!to_match->clock)
2704 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2705 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2706 unsigned int clock1, clock2;
2708 /* Check both 60Hz and 59.94Hz */
2709 clock1 = cea_mode.clock;
2710 clock2 = cea_mode_alternate_clock(&cea_mode);
2712 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2713 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2717 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2719 } while (cea_mode_alternate_timings(vic, &cea_mode));
2724 EXPORT_SYMBOL(drm_match_cea_mode);
2726 static bool drm_valid_cea_vic(u8 vic)
2728 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2732 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2733 * the input VIC from the CEA mode list
2734 * @video_code: ID given to each of the CEA modes
2736 * Returns picture aspect ratio
2738 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2740 return edid_cea_modes[video_code].picture_aspect_ratio;
2742 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2745 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2748 * It's almost like cea_mode_alternate_clock(), we just need to add an
2749 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2753 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2755 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2756 return hdmi_mode->clock;
2758 return cea_mode_alternate_clock(hdmi_mode);
2761 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
2762 unsigned int clock_tolerance)
2766 if (!to_match->clock)
2769 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2770 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2771 unsigned int clock1, clock2;
2773 /* Make sure to also match alternate clocks */
2774 clock1 = hdmi_mode->clock;
2775 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2777 if (abs(to_match->clock - clock1) > clock_tolerance &&
2778 abs(to_match->clock - clock2) > clock_tolerance)
2781 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
2789 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2790 * @to_match: display mode
2792 * An HDMI mode is one defined in the HDMI vendor specific block.
2794 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2796 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
2800 if (!to_match->clock)
2803 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2804 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2805 unsigned int clock1, clock2;
2807 /* Make sure to also match alternate clocks */
2808 clock1 = hdmi_mode->clock;
2809 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2811 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2812 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2813 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
2819 static bool drm_valid_hdmi_vic(u8 vic)
2821 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
2825 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
2827 struct drm_device *dev = connector->dev;
2828 struct drm_display_mode *mode, *tmp;
2832 /* Don't add CEA modes if the CEA extension block is missing */
2833 if (!drm_find_cea_extension(edid))
2837 * Go through all probed modes and create a new mode
2838 * with the alternate clock for certain CEA modes.
2840 list_for_each_entry(mode, &connector->probed_modes, head) {
2841 const struct drm_display_mode *cea_mode = NULL;
2842 struct drm_display_mode *newmode;
2843 u8 vic = drm_match_cea_mode(mode);
2844 unsigned int clock1, clock2;
2846 if (drm_valid_cea_vic(vic)) {
2847 cea_mode = &edid_cea_modes[vic];
2848 clock2 = cea_mode_alternate_clock(cea_mode);
2850 vic = drm_match_hdmi_mode(mode);
2851 if (drm_valid_hdmi_vic(vic)) {
2852 cea_mode = &edid_4k_modes[vic];
2853 clock2 = hdmi_mode_alternate_clock(cea_mode);
2860 clock1 = cea_mode->clock;
2862 if (clock1 == clock2)
2865 if (mode->clock != clock1 && mode->clock != clock2)
2868 newmode = drm_mode_duplicate(dev, cea_mode);
2872 /* Carry over the stereo flags */
2873 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
2876 * The current mode could be either variant. Make
2877 * sure to pick the "other" clock for the new mode.
2879 if (mode->clock != clock1)
2880 newmode->clock = clock1;
2882 newmode->clock = clock2;
2884 list_add_tail(&newmode->head, &list);
2887 list_for_each_entry_safe(mode, tmp, &list, head) {
2888 list_del(&mode->head);
2889 drm_mode_probed_add(connector, mode);
2896 static struct drm_display_mode *
2897 drm_display_mode_from_vic_index(struct drm_connector *connector,
2898 const u8 *video_db, u8 video_len,
2901 struct drm_device *dev = connector->dev;
2902 struct drm_display_mode *newmode;
2905 if (video_db == NULL || video_index >= video_len)
2908 /* CEA modes are numbered 1..127 */
2909 vic = (video_db[video_index] & 127);
2910 if (!drm_valid_cea_vic(vic))
2913 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
2917 newmode->vrefresh = 0;
2923 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
2927 for (i = 0; i < len; i++) {
2928 struct drm_display_mode *mode;
2929 mode = drm_display_mode_from_vic_index(connector, db, len, i);
2931 drm_mode_probed_add(connector, mode);
2939 struct stereo_mandatory_mode {
2940 int width, height, vrefresh;
2944 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
2945 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2946 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
2948 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2950 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2951 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2952 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
2953 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2954 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
2958 stereo_match_mandatory(const struct drm_display_mode *mode,
2959 const struct stereo_mandatory_mode *stereo_mode)
2961 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
2963 return mode->hdisplay == stereo_mode->width &&
2964 mode->vdisplay == stereo_mode->height &&
2965 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
2966 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
2969 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
2971 struct drm_device *dev = connector->dev;
2972 const struct drm_display_mode *mode;
2973 struct list_head stereo_modes;
2976 INIT_LIST_HEAD(&stereo_modes);
2978 list_for_each_entry(mode, &connector->probed_modes, head) {
2979 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
2980 const struct stereo_mandatory_mode *mandatory;
2981 struct drm_display_mode *new_mode;
2983 if (!stereo_match_mandatory(mode,
2984 &stereo_mandatory_modes[i]))
2987 mandatory = &stereo_mandatory_modes[i];
2988 new_mode = drm_mode_duplicate(dev, mode);
2992 new_mode->flags |= mandatory->flags;
2993 list_add_tail(&new_mode->head, &stereo_modes);
2998 list_splice_tail(&stereo_modes, &connector->probed_modes);
3003 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3005 struct drm_device *dev = connector->dev;
3006 struct drm_display_mode *newmode;
3008 if (!drm_valid_hdmi_vic(vic)) {
3009 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3013 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3017 drm_mode_probed_add(connector, newmode);
3022 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3023 const u8 *video_db, u8 video_len, u8 video_index)
3025 struct drm_display_mode *newmode;
3028 if (structure & (1 << 0)) {
3029 newmode = drm_display_mode_from_vic_index(connector, video_db,
3033 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3034 drm_mode_probed_add(connector, newmode);
3038 if (structure & (1 << 6)) {
3039 newmode = drm_display_mode_from_vic_index(connector, video_db,
3043 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3044 drm_mode_probed_add(connector, newmode);
3048 if (structure & (1 << 8)) {
3049 newmode = drm_display_mode_from_vic_index(connector, video_db,
3053 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3054 drm_mode_probed_add(connector, newmode);
3063 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3064 * @connector: connector corresponding to the HDMI sink
3065 * @db: start of the CEA vendor specific block
3066 * @len: length of the CEA block payload, ie. one can access up to db[len]
3068 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3069 * also adds the stereo 3d modes when applicable.
3072 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3073 const u8 *video_db, u8 video_len)
3075 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3076 u8 vic_len, hdmi_3d_len = 0;
3083 /* no HDMI_Video_Present */
3084 if (!(db[8] & (1 << 5)))
3087 /* Latency_Fields_Present */
3088 if (db[8] & (1 << 7))
3091 /* I_Latency_Fields_Present */
3092 if (db[8] & (1 << 6))
3095 /* the declared length is not long enough for the 2 first bytes
3096 * of additional video format capabilities */
3097 if (len < (8 + offset + 2))
3102 if (db[8 + offset] & (1 << 7)) {
3103 modes += add_hdmi_mandatory_stereo_modes(connector);
3105 /* 3D_Multi_present */
3106 multi_present = (db[8 + offset] & 0x60) >> 5;
3110 vic_len = db[8 + offset] >> 5;
3111 hdmi_3d_len = db[8 + offset] & 0x1f;
3113 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3116 vic = db[9 + offset + i];
3117 modes += add_hdmi_mode(connector, vic);
3119 offset += 1 + vic_len;
3121 if (multi_present == 1)
3123 else if (multi_present == 2)
3128 if (len < (8 + offset + hdmi_3d_len - 1))
3131 if (hdmi_3d_len < multi_len)
3134 if (multi_present == 1 || multi_present == 2) {
3135 /* 3D_Structure_ALL */
3136 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3138 /* check if 3D_MASK is present */
3139 if (multi_present == 2)
3140 mask = (db[10 + offset] << 8) | db[11 + offset];
3144 for (i = 0; i < 16; i++) {
3145 if (mask & (1 << i))
3146 modes += add_3d_struct_modes(connector,
3153 offset += multi_len;
3155 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3157 struct drm_display_mode *newmode = NULL;
3158 unsigned int newflag = 0;
3159 bool detail_present;
3161 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3163 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3166 /* 2D_VIC_order_X */
3167 vic_index = db[8 + offset + i] >> 4;
3169 /* 3D_Structure_X */
3170 switch (db[8 + offset + i] & 0x0f) {
3172 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3175 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3179 if ((db[9 + offset + i] >> 4) == 1)
3180 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3185 newmode = drm_display_mode_from_vic_index(connector,
3191 newmode->flags |= newflag;
3192 drm_mode_probed_add(connector, newmode);
3206 cea_db_payload_len(const u8 *db)
3208 return db[0] & 0x1f;
3212 cea_db_tag(const u8 *db)
3218 cea_revision(const u8 *cea)
3224 cea_db_offsets(const u8 *cea, int *start, int *end)
3226 /* Data block offset in CEA extension block */
3231 if (*end < 4 || *end > 127)
3236 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3240 if (cea_db_tag(db) != VENDOR_BLOCK)
3243 if (cea_db_payload_len(db) < 5)
3246 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3248 return hdmi_id == HDMI_IEEE_OUI;
3251 #define for_each_cea_db(cea, i, start, end) \
3252 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3255 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3257 const u8 *cea = drm_find_cea_extension(edid);
3258 const u8 *db, *hdmi = NULL, *video = NULL;
3259 u8 dbl, hdmi_len, video_len = 0;
3262 if (cea && cea_revision(cea) >= 3) {
3265 if (cea_db_offsets(cea, &start, &end))
3268 for_each_cea_db(cea, i, start, end) {
3270 dbl = cea_db_payload_len(db);
3272 if (cea_db_tag(db) == VIDEO_BLOCK) {
3275 modes += do_cea_modes(connector, video, dbl);
3277 else if (cea_db_is_hdmi_vsdb(db)) {
3285 * We parse the HDMI VSDB after having added the cea modes as we will
3286 * be patching their flags when the sink supports stereo 3D.
3289 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3295 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3297 const struct drm_display_mode *cea_mode;
3298 int clock1, clock2, clock;
3303 * allow 5kHz clock difference either way to account for
3304 * the 10kHz clock resolution limit of detailed timings.
3306 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3307 if (drm_valid_cea_vic(vic)) {
3309 cea_mode = &edid_cea_modes[vic];
3310 clock1 = cea_mode->clock;
3311 clock2 = cea_mode_alternate_clock(cea_mode);
3313 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3314 if (drm_valid_hdmi_vic(vic)) {
3316 cea_mode = &edid_4k_modes[vic];
3317 clock1 = cea_mode->clock;
3318 clock2 = hdmi_mode_alternate_clock(cea_mode);
3324 /* pick whichever is closest */
3325 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3330 if (mode->clock == clock)
3333 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3334 type, vic, mode->clock, clock);
3335 mode->clock = clock;
3339 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3341 u8 len = cea_db_payload_len(db);
3344 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3346 connector->latency_present[0] = db[8] >> 7;
3347 connector->latency_present[1] = (db[8] >> 6) & 1;
3350 connector->video_latency[0] = db[9];
3352 connector->audio_latency[0] = db[10];
3354 connector->video_latency[1] = db[11];
3356 connector->audio_latency[1] = db[12];
3358 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3359 "video latency %d %d, "
3360 "audio latency %d %d\n",
3361 connector->latency_present[0],
3362 connector->latency_present[1],
3363 connector->video_latency[0],
3364 connector->video_latency[1],
3365 connector->audio_latency[0],
3366 connector->audio_latency[1]);
3370 monitor_name(struct detailed_timing *t, void *data)
3372 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3373 *(u8 **)data = t->data.other_data.data.str.str;
3376 static int get_monitor_name(struct edid *edid, char name[13])
3378 char *edid_name = NULL;
3384 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3385 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3386 if (edid_name[mnl] == 0x0a)
3389 name[mnl] = edid_name[mnl];
3396 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3397 * @edid: monitor EDID information
3398 * @name: pointer to a character array to hold the name of the monitor
3399 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3402 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3410 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3411 memcpy(name, buf, name_length);
3412 name[name_length] = '\0';
3414 EXPORT_SYMBOL(drm_edid_get_monitor_name);
3417 * drm_edid_to_eld - build ELD from EDID
3418 * @connector: connector corresponding to the HDMI/DP sink
3419 * @edid: EDID to parse
3421 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3422 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3425 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3427 uint8_t *eld = connector->eld;
3430 int total_sad_count = 0;
3434 memset(eld, 0, sizeof(connector->eld));
3436 connector->latency_present[0] = false;
3437 connector->latency_present[1] = false;
3438 connector->video_latency[0] = 0;
3439 connector->audio_latency[0] = 0;
3440 connector->video_latency[1] = 0;
3441 connector->audio_latency[1] = 0;
3446 cea = drm_find_cea_extension(edid);
3448 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3452 mnl = get_monitor_name(edid, eld + 20);
3454 eld[4] = (cea[1] << 5) | mnl;
3455 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3457 eld[0] = 2 << 3; /* ELD version: 2 */
3459 eld[16] = edid->mfg_id[0];
3460 eld[17] = edid->mfg_id[1];
3461 eld[18] = edid->prod_code[0];
3462 eld[19] = edid->prod_code[1];
3464 if (cea_revision(cea) >= 3) {
3467 if (cea_db_offsets(cea, &start, &end)) {
3472 for_each_cea_db(cea, i, start, end) {
3474 dbl = cea_db_payload_len(db);
3476 switch (cea_db_tag(db)) {
3480 /* Audio Data Block, contains SADs */
3481 sad_count = min(dbl / 3, 15 - total_sad_count);
3483 memcpy(eld + 20 + mnl + total_sad_count * 3,
3484 &db[1], sad_count * 3);
3485 total_sad_count += sad_count;
3488 /* Speaker Allocation Data Block */
3493 /* HDMI Vendor-Specific Data Block */
3494 if (cea_db_is_hdmi_vsdb(db))
3495 drm_parse_hdmi_vsdb_audio(connector, db);
3502 eld[5] |= total_sad_count << 4;
3504 eld[DRM_ELD_BASELINE_ELD_LEN] =
3505 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3507 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3508 drm_eld_size(eld), total_sad_count);
3510 EXPORT_SYMBOL(drm_edid_to_eld);
3513 * drm_edid_to_sad - extracts SADs from EDID
3514 * @edid: EDID to parse
3515 * @sads: pointer that will be set to the extracted SADs
3517 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3519 * Note: The returned pointer needs to be freed using kfree().
3521 * Return: The number of found SADs or negative number on error.
3523 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3526 int i, start, end, dbl;
3529 cea = drm_find_cea_extension(edid);
3531 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3535 if (cea_revision(cea) < 3) {
3536 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3540 if (cea_db_offsets(cea, &start, &end)) {
3541 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3545 for_each_cea_db(cea, i, start, end) {
3548 if (cea_db_tag(db) == AUDIO_BLOCK) {
3550 dbl = cea_db_payload_len(db);
3552 count = dbl / 3; /* SAD is 3B */
3553 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3556 for (j = 0; j < count; j++) {
3557 u8 *sad = &db[1 + j * 3];
3559 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3560 (*sads)[j].channels = sad[0] & 0x7;
3561 (*sads)[j].freq = sad[1] & 0x7F;
3562 (*sads)[j].byte2 = sad[2];
3570 EXPORT_SYMBOL(drm_edid_to_sad);
3573 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3574 * @edid: EDID to parse
3575 * @sadb: pointer to the speaker block
3577 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
3579 * Note: The returned pointer needs to be freed using kfree().
3581 * Return: The number of found Speaker Allocation Blocks or negative number on
3584 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3587 int i, start, end, dbl;
3590 cea = drm_find_cea_extension(edid);
3592 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3596 if (cea_revision(cea) < 3) {
3597 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3601 if (cea_db_offsets(cea, &start, &end)) {
3602 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3606 for_each_cea_db(cea, i, start, end) {
3607 const u8 *db = &cea[i];
3609 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3610 dbl = cea_db_payload_len(db);
3612 /* Speaker Allocation Data Block */
3614 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
3625 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3628 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
3629 * @connector: connector associated with the HDMI/DP sink
3630 * @mode: the display mode
3632 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3633 * the sink doesn't support audio or video.
3635 int drm_av_sync_delay(struct drm_connector *connector,
3636 const struct drm_display_mode *mode)
3638 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3641 if (!connector->latency_present[0])
3643 if (!connector->latency_present[1])
3646 a = connector->audio_latency[i];
3647 v = connector->video_latency[i];
3650 * HDMI/DP sink doesn't support audio or video?
3652 if (a == 255 || v == 255)
3656 * Convert raw EDID values to millisecond.
3657 * Treat unknown latency as 0ms.
3660 a = min(2 * (a - 1), 500);
3662 v = min(2 * (v - 1), 500);
3664 return max(v - a, 0);
3666 EXPORT_SYMBOL(drm_av_sync_delay);
3669 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
3670 * @edid: monitor EDID information
3672 * Parse the CEA extension according to CEA-861-B.
3674 * Return: True if the monitor is HDMI, false if not or unknown.
3676 bool drm_detect_hdmi_monitor(struct edid *edid)
3680 int start_offset, end_offset;
3682 edid_ext = drm_find_cea_extension(edid);
3686 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3690 * Because HDMI identifier is in Vendor Specific Block,
3691 * search it from all data blocks of CEA extension.
3693 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3694 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3700 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3703 * drm_detect_monitor_audio - check monitor audio capability
3704 * @edid: EDID block to scan
3706 * Monitor should have CEA extension block.
3707 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3708 * audio' only. If there is any audio extension block and supported
3709 * audio format, assume at least 'basic audio' support, even if 'basic
3710 * audio' is not defined in EDID.
3712 * Return: True if the monitor supports audio, false otherwise.
3714 bool drm_detect_monitor_audio(struct edid *edid)
3718 bool has_audio = false;
3719 int start_offset, end_offset;
3721 edid_ext = drm_find_cea_extension(edid);
3725 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
3728 DRM_DEBUG_KMS("Monitor has basic audio support\n");
3732 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3735 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3736 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
3738 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
3739 DRM_DEBUG_KMS("CEA audio format %d\n",
3740 (edid_ext[i + j] >> 3) & 0xf);
3747 EXPORT_SYMBOL(drm_detect_monitor_audio);
3750 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
3751 * @edid: EDID block to scan
3753 * Check whether the monitor reports the RGB quantization range selection
3754 * as supported. The AVI infoframe can then be used to inform the monitor
3755 * which quantization range (full or limited) is used.
3757 * Return: True if the RGB quantization range is selectable, false otherwise.
3759 bool drm_rgb_quant_range_selectable(struct edid *edid)
3764 edid_ext = drm_find_cea_extension(edid);
3768 if (cea_db_offsets(edid_ext, &start, &end))
3771 for_each_cea_db(edid_ext, i, start, end) {
3772 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
3773 cea_db_payload_len(&edid_ext[i]) == 2) {
3774 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
3775 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
3781 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
3784 * drm_default_rgb_quant_range - default RGB quantization range
3785 * @mode: display mode
3787 * Determine the default RGB quantization range for the mode,
3788 * as specified in CEA-861.
3790 * Return: The default RGB quantization range for the mode
3792 enum hdmi_quantization_range
3793 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
3795 /* All CEA modes other than VIC 1 use limited quantization range. */
3796 return drm_match_cea_mode(mode) > 1 ?
3797 HDMI_QUANTIZATION_RANGE_LIMITED :
3798 HDMI_QUANTIZATION_RANGE_FULL;
3800 EXPORT_SYMBOL(drm_default_rgb_quant_range);
3802 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
3805 struct drm_display_info *info = &connector->display_info;
3806 unsigned int dc_bpc = 0;
3808 /* HDMI supports at least 8 bpc */
3811 if (cea_db_payload_len(hdmi) < 6)
3814 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
3816 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
3817 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
3821 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
3823 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
3824 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
3828 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
3830 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
3831 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
3836 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
3841 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
3842 connector->name, dc_bpc);
3846 * Deep color support mandates RGB444 support for all video
3847 * modes and forbids YCRCB422 support for all video modes per
3850 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3852 /* YCRCB444 is optional according to spec. */
3853 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
3854 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3855 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
3860 * Spec says that if any deep color mode is supported at all,
3861 * then deep color 36 bit must be supported.
3863 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
3864 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
3870 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
3872 struct drm_display_info *info = &connector->display_info;
3873 u8 len = cea_db_payload_len(db);
3876 info->dvi_dual = db[6] & 1;
3878 info->max_tmds_clock = db[7] * 5000;
3880 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
3881 "max TMDS clock %d kHz\n",
3883 info->max_tmds_clock);
3885 drm_parse_hdmi_deep_color_info(connector, db);
3888 static void drm_parse_cea_ext(struct drm_connector *connector,
3891 struct drm_display_info *info = &connector->display_info;
3895 edid_ext = drm_find_cea_extension(edid);
3899 info->cea_rev = edid_ext[1];
3901 /* The existence of a CEA block should imply RGB support */
3902 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3903 if (edid_ext[3] & EDID_CEA_YCRCB444)
3904 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3905 if (edid_ext[3] & EDID_CEA_YCRCB422)
3906 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3908 if (cea_db_offsets(edid_ext, &start, &end))
3911 for_each_cea_db(edid_ext, i, start, end) {
3912 const u8 *db = &edid_ext[i];
3914 if (cea_db_is_hdmi_vsdb(db))
3915 drm_parse_hdmi_vsdb_video(connector, db);
3919 static void drm_add_display_info(struct drm_connector *connector,
3922 struct drm_display_info *info = &connector->display_info;
3924 info->width_mm = edid->width_cm * 10;
3925 info->height_mm = edid->height_cm * 10;
3927 /* driver figures it out in this case */
3929 info->color_formats = 0;
3931 info->max_tmds_clock = 0;
3932 info->dvi_dual = false;
3934 if (edid->revision < 3)
3937 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
3940 drm_parse_cea_ext(connector, edid);
3943 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
3945 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
3946 * tells us to assume 8 bpc color depth if the EDID doesn't have
3947 * extensions which tell otherwise.
3949 if ((info->bpc == 0) && (edid->revision < 4) &&
3950 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
3952 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
3953 connector->name, info->bpc);
3956 /* Only defined for 1.4 with digital displays */
3957 if (edid->revision < 4)
3960 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
3961 case DRM_EDID_DIGITAL_DEPTH_6:
3964 case DRM_EDID_DIGITAL_DEPTH_8:
3967 case DRM_EDID_DIGITAL_DEPTH_10:
3970 case DRM_EDID_DIGITAL_DEPTH_12:
3973 case DRM_EDID_DIGITAL_DEPTH_14:
3976 case DRM_EDID_DIGITAL_DEPTH_16:
3979 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
3985 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
3986 connector->name, info->bpc);
3988 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
3989 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
3990 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3991 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
3992 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3995 static int validate_displayid(u8 *displayid, int length, int idx)
3999 struct displayid_hdr *base;
4001 base = (struct displayid_hdr *)&displayid[idx];
4003 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4004 base->rev, base->bytes, base->prod_id, base->ext_count);
4006 if (base->bytes + 5 > length - idx)
4008 for (i = idx; i <= base->bytes + 5; i++) {
4009 csum += displayid[i];
4012 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4018 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4019 struct displayid_detailed_timings_1 *timings)
4021 struct drm_display_mode *mode;
4022 unsigned pixel_clock = (timings->pixel_clock[0] |
4023 (timings->pixel_clock[1] << 8) |
4024 (timings->pixel_clock[2] << 16));
4025 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4026 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4027 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4028 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4029 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4030 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4031 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4032 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4033 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4034 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4035 mode = drm_mode_create(dev);
4039 mode->clock = pixel_clock * 10;
4040 mode->hdisplay = hactive;
4041 mode->hsync_start = mode->hdisplay + hsync;
4042 mode->hsync_end = mode->hsync_start + hsync_width;
4043 mode->htotal = mode->hdisplay + hblank;
4045 mode->vdisplay = vactive;
4046 mode->vsync_start = mode->vdisplay + vsync;
4047 mode->vsync_end = mode->vsync_start + vsync_width;
4048 mode->vtotal = mode->vdisplay + vblank;
4051 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4052 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4053 mode->type = DRM_MODE_TYPE_DRIVER;
4055 if (timings->flags & 0x80)
4056 mode->type |= DRM_MODE_TYPE_PREFERRED;
4057 mode->vrefresh = drm_mode_vrefresh(mode);
4058 drm_mode_set_name(mode);
4063 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4064 struct displayid_block *block)
4066 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4069 struct drm_display_mode *newmode;
4071 /* blocks must be multiple of 20 bytes length */
4072 if (block->num_bytes % 20)
4075 num_timings = block->num_bytes / 20;
4076 for (i = 0; i < num_timings; i++) {
4077 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4079 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4083 drm_mode_probed_add(connector, newmode);
4089 static int add_displayid_detailed_modes(struct drm_connector *connector,
4095 int length = EDID_LENGTH;
4096 struct displayid_block *block;
4099 displayid = drm_find_displayid_extension(edid);
4103 ret = validate_displayid(displayid, length, idx);
4107 idx += sizeof(struct displayid_hdr);
4108 while (block = (struct displayid_block *)&displayid[idx],
4109 idx + sizeof(struct displayid_block) <= length &&
4110 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4111 block->num_bytes > 0) {
4112 idx += block->num_bytes + sizeof(struct displayid_block);
4113 switch (block->tag) {
4114 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4115 num_modes += add_displayid_detailed_1_modes(connector, block);
4123 * drm_add_edid_modes - add modes from EDID data, if available
4124 * @connector: connector we're probing
4127 * Add the specified modes to the connector's mode list. Also fills out the
4128 * &drm_display_info structure in @connector with any information which can be
4129 * derived from the edid.
4131 * Return: The number of modes added or 0 if we couldn't find any.
4133 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4141 if (!drm_edid_is_valid(edid)) {
4142 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4147 quirks = edid_get_quirks(edid);
4150 * EDID spec says modes should be preferred in this order:
4151 * - preferred detailed mode
4152 * - other detailed modes from base block
4153 * - detailed modes from extension blocks
4154 * - CVT 3-byte code modes
4155 * - standard timing codes
4156 * - established timing codes
4157 * - modes inferred from GTF or CVT range information
4159 * We get this pretty much right.
4161 * XXX order for additional mode types in extension blocks?
4163 num_modes += add_detailed_modes(connector, edid, quirks);
4164 num_modes += add_cvt_modes(connector, edid);
4165 num_modes += add_standard_modes(connector, edid);
4166 num_modes += add_established_modes(connector, edid);
4167 num_modes += add_cea_modes(connector, edid);
4168 num_modes += add_alternate_cea_modes(connector, edid);
4169 num_modes += add_displayid_detailed_modes(connector, edid);
4170 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4171 num_modes += add_inferred_modes(connector, edid);
4173 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4174 edid_fixup_preferred(connector, quirks);
4176 drm_add_display_info(connector, edid);
4178 if (quirks & EDID_QUIRK_FORCE_6BPC)
4179 connector->display_info.bpc = 6;
4181 if (quirks & EDID_QUIRK_FORCE_8BPC)
4182 connector->display_info.bpc = 8;
4184 if (quirks & EDID_QUIRK_FORCE_12BPC)
4185 connector->display_info.bpc = 12;
4189 EXPORT_SYMBOL(drm_add_edid_modes);
4192 * drm_add_modes_noedid - add modes for the connectors without EDID
4193 * @connector: connector we're probing
4194 * @hdisplay: the horizontal display limit
4195 * @vdisplay: the vertical display limit
4197 * Add the specified modes to the connector's mode list. Only when the
4198 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4200 * Return: The number of modes added or 0 if we couldn't find any.
4202 int drm_add_modes_noedid(struct drm_connector *connector,
4203 int hdisplay, int vdisplay)
4205 int i, count, num_modes = 0;
4206 struct drm_display_mode *mode;
4207 struct drm_device *dev = connector->dev;
4209 count = ARRAY_SIZE(drm_dmt_modes);
4215 for (i = 0; i < count; i++) {
4216 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4217 if (hdisplay && vdisplay) {
4219 * Only when two are valid, they will be used to check
4220 * whether the mode should be added to the mode list of
4223 if (ptr->hdisplay > hdisplay ||
4224 ptr->vdisplay > vdisplay)
4227 if (drm_mode_vrefresh(ptr) > 61)
4229 mode = drm_mode_duplicate(dev, ptr);
4231 drm_mode_probed_add(connector, mode);
4237 EXPORT_SYMBOL(drm_add_modes_noedid);
4240 * drm_set_preferred_mode - Sets the preferred mode of a connector
4241 * @connector: connector whose mode list should be processed
4242 * @hpref: horizontal resolution of preferred mode
4243 * @vpref: vertical resolution of preferred mode
4245 * Marks a mode as preferred if it matches the resolution specified by @hpref
4248 void drm_set_preferred_mode(struct drm_connector *connector,
4249 int hpref, int vpref)
4251 struct drm_display_mode *mode;
4253 list_for_each_entry(mode, &connector->probed_modes, head) {
4254 if (mode->hdisplay == hpref &&
4255 mode->vdisplay == vpref)
4256 mode->type |= DRM_MODE_TYPE_PREFERRED;
4259 EXPORT_SYMBOL(drm_set_preferred_mode);
4262 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4263 * data from a DRM display mode
4264 * @frame: HDMI AVI infoframe
4265 * @mode: DRM display mode
4267 * Return: 0 on success or a negative error code on failure.
4270 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4271 const struct drm_display_mode *mode)
4275 if (!frame || !mode)
4278 err = hdmi_avi_infoframe_init(frame);
4282 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4283 frame->pixel_repeat = 1;
4285 frame->video_code = drm_match_cea_mode(mode);
4287 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4290 * Populate picture aspect ratio from either
4291 * user input (if specified) or from the CEA mode list.
4293 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4294 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4295 frame->picture_aspect = mode->picture_aspect_ratio;
4296 else if (frame->video_code > 0)
4297 frame->picture_aspect = drm_get_cea_aspect_ratio(
4300 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4301 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4305 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4308 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4309 * quantization range information
4310 * @frame: HDMI AVI infoframe
4311 * @mode: DRM display mode
4312 * @rgb_quant_range: RGB quantization range (Q)
4313 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
4316 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
4317 const struct drm_display_mode *mode,
4318 enum hdmi_quantization_range rgb_quant_range,
4319 bool rgb_quant_range_selectable)
4323 * "A Source shall not send a non-zero Q value that does not correspond
4324 * to the default RGB Quantization Range for the transmitted Picture
4325 * unless the Sink indicates support for the Q bit in a Video
4326 * Capabilities Data Block."
4328 * HDMI 2.0 recommends sending non-zero Q when it does match the
4329 * default RGB quantization range for the mode, even when QS=0.
4331 if (rgb_quant_range_selectable ||
4332 rgb_quant_range == drm_default_rgb_quant_range(mode))
4333 frame->quantization_range = rgb_quant_range;
4335 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
4339 * "When transmitting any RGB colorimetry, the Source should set the
4340 * YQ-field to match the RGB Quantization Range being transmitted
4341 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4342 * set YQ=1) and the Sink shall ignore the YQ-field."
4344 if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
4345 frame->ycc_quantization_range =
4346 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
4348 frame->ycc_quantization_range =
4349 HDMI_YCC_QUANTIZATION_RANGE_FULL;
4351 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
4353 static enum hdmi_3d_structure
4354 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4356 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4359 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4360 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4361 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4362 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4363 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4364 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4365 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4366 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4367 case DRM_MODE_FLAG_3D_L_DEPTH:
4368 return HDMI_3D_STRUCTURE_L_DEPTH;
4369 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4370 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4371 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4372 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4373 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4374 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4376 return HDMI_3D_STRUCTURE_INVALID;
4381 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4382 * data from a DRM display mode
4383 * @frame: HDMI vendor infoframe
4384 * @mode: DRM display mode
4386 * Note that there's is a need to send HDMI vendor infoframes only when using a
4387 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4388 * function will return -EINVAL, error that can be safely ignored.
4390 * Return: 0 on success or a negative error code on failure.
4393 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4394 const struct drm_display_mode *mode)
4400 if (!frame || !mode)
4403 vic = drm_match_hdmi_mode(mode);
4404 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4406 if (!vic && !s3d_flags)
4409 if (vic && s3d_flags)
4412 err = hdmi_vendor_infoframe_init(frame);
4419 frame->s3d_struct = s3d_structure_from_display_mode(mode);
4423 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
4425 static int drm_parse_tiled_block(struct drm_connector *connector,
4426 struct displayid_block *block)
4428 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4430 u8 tile_v_loc, tile_h_loc;
4431 u8 num_v_tile, num_h_tile;
4432 struct drm_tile_group *tg;
4434 w = tile->tile_size[0] | tile->tile_size[1] << 8;
4435 h = tile->tile_size[2] | tile->tile_size[3] << 8;
4437 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4438 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
4439 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
4440 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
4442 connector->has_tile = true;
4443 if (tile->tile_cap & 0x80)
4444 connector->tile_is_single_monitor = true;
4446 connector->num_h_tile = num_h_tile + 1;
4447 connector->num_v_tile = num_v_tile + 1;
4448 connector->tile_h_loc = tile_h_loc;
4449 connector->tile_v_loc = tile_v_loc;
4450 connector->tile_h_size = w + 1;
4451 connector->tile_v_size = h + 1;
4453 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
4454 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
4455 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
4456 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
4457 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
4459 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
4461 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
4466 if (connector->tile_group != tg) {
4467 /* if we haven't got a pointer,
4468 take the reference, drop ref to old tile group */
4469 if (connector->tile_group) {
4470 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4472 connector->tile_group = tg;
4474 /* if same tile group, then release the ref we just took. */
4475 drm_mode_put_tile_group(connector->dev, tg);
4479 static int drm_parse_display_id(struct drm_connector *connector,
4480 u8 *displayid, int length,
4481 bool is_edid_extension)
4483 /* if this is an EDID extension the first byte will be 0x70 */
4485 struct displayid_block *block;
4488 if (is_edid_extension)
4491 ret = validate_displayid(displayid, length, idx);
4495 idx += sizeof(struct displayid_hdr);
4496 while (block = (struct displayid_block *)&displayid[idx],
4497 idx + sizeof(struct displayid_block) <= length &&
4498 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4499 block->num_bytes > 0) {
4500 idx += block->num_bytes + sizeof(struct displayid_block);
4501 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
4502 block->tag, block->rev, block->num_bytes);
4504 switch (block->tag) {
4505 case DATA_BLOCK_TILED_DISPLAY:
4506 ret = drm_parse_tiled_block(connector, block);
4510 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4511 /* handled in mode gathering code. */
4514 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
4521 static void drm_get_displayid(struct drm_connector *connector,
4524 void *displayid = NULL;
4526 connector->has_tile = false;
4527 displayid = drm_find_displayid_extension(edid);
4529 /* drop reference to any tile group we had */
4533 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
4536 if (!connector->has_tile)
4540 if (connector->tile_group) {
4541 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4542 connector->tile_group = NULL;
projects / linux-2.6-block.git / blob