2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
35 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_displayid.h>
41 #define version_greater(edid, maj, min) \
42 (((edid)->version > (maj)) || \
43 ((edid)->version == (maj) && (edid)->revision > (min)))
45 #define EDID_EST_TIMINGS 16
46 #define EDID_STD_TIMINGS 8
47 #define EDID_DETAILED_TIMINGS 4
50 * EDID blocks out in the wild have a variety of bugs, try to collect
51 * them here (note that userspace may work around broken monitors first,
52 * but fixes should make their way here so that the kernel "just works"
53 * on as many displays as possible).
56 /* First detailed mode wrong, use largest 60Hz mode */
57 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
58 /* Reported 135MHz pixel clock is too high, needs adjustment */
59 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
60 /* Prefer the largest mode at 75 Hz */
61 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
62 /* Detail timing is in cm not mm */
63 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
64 /* Detailed timing descriptors have bogus size values, so just take the
65 * maximum size and use that.
67 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
68 /* Monitor forgot to set the first detailed is preferred bit. */
69 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
70 /* use +hsync +vsync for detailed mode */
71 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
72 /* Force reduced-blanking timings for detailed modes */
73 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
75 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
77 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
79 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
81 struct detailed_mode_closure {
82 struct drm_connector *connector;
94 static const struct edid_quirk {
98 } edid_quirk_list[] = {
100 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
102 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
104 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
106 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
107 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
109 /* Belinea 10 15 55 */
110 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
111 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
113 /* Envision Peripherals, Inc. EN-7100e */
114 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
115 /* Envision EN2028 */
116 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
118 /* Funai Electronics PM36B */
119 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
120 EDID_QUIRK_DETAILED_IN_CM },
122 /* LG Philips LCD LP154W01-A5 */
123 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
124 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
126 /* Philips 107p5 CRT */
127 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
130 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
132 /* Samsung SyncMaster 205BW. Note: irony */
133 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
134 /* Samsung SyncMaster 22[5-6]BW */
135 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
136 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
138 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
139 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
141 /* ViewSonic VA2026w */
142 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
144 /* Medion MD 30217 PG */
145 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
147 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
148 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
152 * Autogenerated from the DMT spec.
153 * This table is copied from xfree86/modes/xf86EdidModes.c.
155 static const struct drm_display_mode drm_dmt_modes[] = {
156 /* 0x01 - 640x350@85Hz */
157 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
158 736, 832, 0, 350, 382, 385, 445, 0,
159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
160 /* 0x02 - 640x400@85Hz */
161 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
162 736, 832, 0, 400, 401, 404, 445, 0,
163 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
164 /* 0x03 - 720x400@85Hz */
165 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
166 828, 936, 0, 400, 401, 404, 446, 0,
167 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
168 /* 0x04 - 640x480@60Hz */
169 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
170 752, 800, 0, 480, 490, 492, 525, 0,
171 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
172 /* 0x05 - 640x480@72Hz */
173 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
174 704, 832, 0, 480, 489, 492, 520, 0,
175 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
176 /* 0x06 - 640x480@75Hz */
177 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
178 720, 840, 0, 480, 481, 484, 500, 0,
179 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
180 /* 0x07 - 640x480@85Hz */
181 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
182 752, 832, 0, 480, 481, 484, 509, 0,
183 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
184 /* 0x08 - 800x600@56Hz */
185 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
186 896, 1024, 0, 600, 601, 603, 625, 0,
187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
188 /* 0x09 - 800x600@60Hz */
189 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
190 968, 1056, 0, 600, 601, 605, 628, 0,
191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
192 /* 0x0a - 800x600@72Hz */
193 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
194 976, 1040, 0, 600, 637, 643, 666, 0,
195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
196 /* 0x0b - 800x600@75Hz */
197 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
198 896, 1056, 0, 600, 601, 604, 625, 0,
199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
200 /* 0x0c - 800x600@85Hz */
201 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
202 896, 1048, 0, 600, 601, 604, 631, 0,
203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
204 /* 0x0d - 800x600@120Hz RB */
205 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
206 880, 960, 0, 600, 603, 607, 636, 0,
207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
208 /* 0x0e - 848x480@60Hz */
209 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
210 976, 1088, 0, 480, 486, 494, 517, 0,
211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
212 /* 0x0f - 1024x768@43Hz, interlace */
213 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
214 1208, 1264, 0, 768, 768, 776, 817, 0,
215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
216 DRM_MODE_FLAG_INTERLACE) },
217 /* 0x10 - 1024x768@60Hz */
218 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
219 1184, 1344, 0, 768, 771, 777, 806, 0,
220 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
221 /* 0x11 - 1024x768@70Hz */
222 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
223 1184, 1328, 0, 768, 771, 777, 806, 0,
224 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
225 /* 0x12 - 1024x768@75Hz */
226 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
227 1136, 1312, 0, 768, 769, 772, 800, 0,
228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
229 /* 0x13 - 1024x768@85Hz */
230 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
231 1168, 1376, 0, 768, 769, 772, 808, 0,
232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
233 /* 0x14 - 1024x768@120Hz RB */
234 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
235 1104, 1184, 0, 768, 771, 775, 813, 0,
236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
237 /* 0x15 - 1152x864@75Hz */
238 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
239 1344, 1600, 0, 864, 865, 868, 900, 0,
240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
241 /* 0x55 - 1280x720@60Hz */
242 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
243 1430, 1650, 0, 720, 725, 730, 750, 0,
244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
245 /* 0x16 - 1280x768@60Hz RB */
246 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
247 1360, 1440, 0, 768, 771, 778, 790, 0,
248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
249 /* 0x17 - 1280x768@60Hz */
250 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
251 1472, 1664, 0, 768, 771, 778, 798, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
253 /* 0x18 - 1280x768@75Hz */
254 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
255 1488, 1696, 0, 768, 771, 778, 805, 0,
256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
257 /* 0x19 - 1280x768@85Hz */
258 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
259 1496, 1712, 0, 768, 771, 778, 809, 0,
260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
261 /* 0x1a - 1280x768@120Hz RB */
262 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
263 1360, 1440, 0, 768, 771, 778, 813, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
265 /* 0x1b - 1280x800@60Hz RB */
266 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
267 1360, 1440, 0, 800, 803, 809, 823, 0,
268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
269 /* 0x1c - 1280x800@60Hz */
270 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
271 1480, 1680, 0, 800, 803, 809, 831, 0,
272 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
273 /* 0x1d - 1280x800@75Hz */
274 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
275 1488, 1696, 0, 800, 803, 809, 838, 0,
276 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
277 /* 0x1e - 1280x800@85Hz */
278 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
279 1496, 1712, 0, 800, 803, 809, 843, 0,
280 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
281 /* 0x1f - 1280x800@120Hz RB */
282 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
283 1360, 1440, 0, 800, 803, 809, 847, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
285 /* 0x20 - 1280x960@60Hz */
286 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
287 1488, 1800, 0, 960, 961, 964, 1000, 0,
288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
289 /* 0x21 - 1280x960@85Hz */
290 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
291 1504, 1728, 0, 960, 961, 964, 1011, 0,
292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
293 /* 0x22 - 1280x960@120Hz RB */
294 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
295 1360, 1440, 0, 960, 963, 967, 1017, 0,
296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
297 /* 0x23 - 1280x1024@60Hz */
298 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
299 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
301 /* 0x24 - 1280x1024@75Hz */
302 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
303 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
305 /* 0x25 - 1280x1024@85Hz */
306 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
307 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
309 /* 0x26 - 1280x1024@120Hz RB */
310 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
311 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
313 /* 0x27 - 1360x768@60Hz */
314 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
315 1536, 1792, 0, 768, 771, 777, 795, 0,
316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
317 /* 0x28 - 1360x768@120Hz RB */
318 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
319 1440, 1520, 0, 768, 771, 776, 813, 0,
320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
321 /* 0x51 - 1366x768@60Hz */
322 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
323 1579, 1792, 0, 768, 771, 774, 798, 0,
324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
325 /* 0x56 - 1366x768@60Hz */
326 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
327 1436, 1500, 0, 768, 769, 772, 800, 0,
328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
329 /* 0x29 - 1400x1050@60Hz RB */
330 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
331 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
333 /* 0x2a - 1400x1050@60Hz */
334 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
335 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
336 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
337 /* 0x2b - 1400x1050@75Hz */
338 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
339 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
341 /* 0x2c - 1400x1050@85Hz */
342 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
343 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
345 /* 0x2d - 1400x1050@120Hz RB */
346 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
347 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
349 /* 0x2e - 1440x900@60Hz RB */
350 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
351 1520, 1600, 0, 900, 903, 909, 926, 0,
352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
353 /* 0x2f - 1440x900@60Hz */
354 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
355 1672, 1904, 0, 900, 903, 909, 934, 0,
356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
357 /* 0x30 - 1440x900@75Hz */
358 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
359 1688, 1936, 0, 900, 903, 909, 942, 0,
360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
361 /* 0x31 - 1440x900@85Hz */
362 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
363 1696, 1952, 0, 900, 903, 909, 948, 0,
364 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
365 /* 0x32 - 1440x900@120Hz RB */
366 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
367 1520, 1600, 0, 900, 903, 909, 953, 0,
368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
369 /* 0x53 - 1600x900@60Hz */
370 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
371 1704, 1800, 0, 900, 901, 904, 1000, 0,
372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
373 /* 0x33 - 1600x1200@60Hz */
374 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
375 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
377 /* 0x34 - 1600x1200@65Hz */
378 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
379 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
381 /* 0x35 - 1600x1200@70Hz */
382 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
383 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
385 /* 0x36 - 1600x1200@75Hz */
386 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
387 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
389 /* 0x37 - 1600x1200@85Hz */
390 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
391 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
393 /* 0x38 - 1600x1200@120Hz RB */
394 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
395 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
397 /* 0x39 - 1680x1050@60Hz RB */
398 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
399 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
401 /* 0x3a - 1680x1050@60Hz */
402 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
403 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
404 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
405 /* 0x3b - 1680x1050@75Hz */
406 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
407 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
409 /* 0x3c - 1680x1050@85Hz */
410 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
411 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
412 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
413 /* 0x3d - 1680x1050@120Hz RB */
414 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
415 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
417 /* 0x3e - 1792x1344@60Hz */
418 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
419 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
420 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
421 /* 0x3f - 1792x1344@75Hz */
422 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
423 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
425 /* 0x40 - 1792x1344@120Hz RB */
426 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
427 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
429 /* 0x41 - 1856x1392@60Hz */
430 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
431 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
433 /* 0x42 - 1856x1392@75Hz */
434 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
435 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
436 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
437 /* 0x43 - 1856x1392@120Hz RB */
438 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
439 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
441 /* 0x52 - 1920x1080@60Hz */
442 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
443 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
445 /* 0x44 - 1920x1200@60Hz RB */
446 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
447 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
449 /* 0x45 - 1920x1200@60Hz */
450 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
451 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
452 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
453 /* 0x46 - 1920x1200@75Hz */
454 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
455 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
457 /* 0x47 - 1920x1200@85Hz */
458 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
459 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
461 /* 0x48 - 1920x1200@120Hz RB */
462 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
463 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
465 /* 0x49 - 1920x1440@60Hz */
466 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
467 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
468 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
469 /* 0x4a - 1920x1440@75Hz */
470 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
471 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
473 /* 0x4b - 1920x1440@120Hz RB */
474 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
475 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
477 /* 0x54 - 2048x1152@60Hz */
478 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
479 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
481 /* 0x4c - 2560x1600@60Hz RB */
482 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
483 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
485 /* 0x4d - 2560x1600@60Hz */
486 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
487 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
489 /* 0x4e - 2560x1600@75Hz */
490 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
491 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
493 /* 0x4f - 2560x1600@85Hz */
494 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
495 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
497 /* 0x50 - 2560x1600@120Hz RB */
498 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
499 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
501 /* 0x57 - 4096x2160@60Hz RB */
502 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
503 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
505 /* 0x58 - 4096x2160@59.94Hz RB */
506 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
507 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
512 * These more or less come from the DMT spec. The 720x400 modes are
513 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
514 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
515 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
518 * The DMT modes have been fact-checked; the rest are mild guesses.
520 static const struct drm_display_mode edid_est_modes[] = {
521 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
522 968, 1056, 0, 600, 601, 605, 628, 0,
523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
524 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
525 896, 1024, 0, 600, 601, 603, 625, 0,
526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
527 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
528 720, 840, 0, 480, 481, 484, 500, 0,
529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
530 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
531 704, 832, 0, 480, 489, 492, 520, 0,
532 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
533 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
534 768, 864, 0, 480, 483, 486, 525, 0,
535 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
536 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
537 752, 800, 0, 480, 490, 492, 525, 0,
538 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
539 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
540 846, 900, 0, 400, 421, 423, 449, 0,
541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
542 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
543 846, 900, 0, 400, 412, 414, 449, 0,
544 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
545 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
546 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
548 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
549 1136, 1312, 0, 768, 769, 772, 800, 0,
550 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
551 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
552 1184, 1328, 0, 768, 771, 777, 806, 0,
553 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
554 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
555 1184, 1344, 0, 768, 771, 777, 806, 0,
556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
557 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
558 1208, 1264, 0, 768, 768, 776, 817, 0,
559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
560 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
561 928, 1152, 0, 624, 625, 628, 667, 0,
562 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
563 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
564 896, 1056, 0, 600, 601, 604, 625, 0,
565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
566 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
567 976, 1040, 0, 600, 637, 643, 666, 0,
568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
569 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
570 1344, 1600, 0, 864, 865, 868, 900, 0,
571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
581 static const struct minimode est3_modes[] = {
589 { 1024, 768, 85, 0 },
590 { 1152, 864, 75, 0 },
592 { 1280, 768, 60, 1 },
593 { 1280, 768, 60, 0 },
594 { 1280, 768, 75, 0 },
595 { 1280, 768, 85, 0 },
596 { 1280, 960, 60, 0 },
597 { 1280, 960, 85, 0 },
598 { 1280, 1024, 60, 0 },
599 { 1280, 1024, 85, 0 },
601 { 1360, 768, 60, 0 },
602 { 1440, 900, 60, 1 },
603 { 1440, 900, 60, 0 },
604 { 1440, 900, 75, 0 },
605 { 1440, 900, 85, 0 },
606 { 1400, 1050, 60, 1 },
607 { 1400, 1050, 60, 0 },
608 { 1400, 1050, 75, 0 },
610 { 1400, 1050, 85, 0 },
611 { 1680, 1050, 60, 1 },
612 { 1680, 1050, 60, 0 },
613 { 1680, 1050, 75, 0 },
614 { 1680, 1050, 85, 0 },
615 { 1600, 1200, 60, 0 },
616 { 1600, 1200, 65, 0 },
617 { 1600, 1200, 70, 0 },
619 { 1600, 1200, 75, 0 },
620 { 1600, 1200, 85, 0 },
621 { 1792, 1344, 60, 0 },
622 { 1792, 1344, 75, 0 },
623 { 1856, 1392, 60, 0 },
624 { 1856, 1392, 75, 0 },
625 { 1920, 1200, 60, 1 },
626 { 1920, 1200, 60, 0 },
628 { 1920, 1200, 75, 0 },
629 { 1920, 1200, 85, 0 },
630 { 1920, 1440, 60, 0 },
631 { 1920, 1440, 75, 0 },
634 static const struct minimode extra_modes[] = {
635 { 1024, 576, 60, 0 },
636 { 1366, 768, 60, 0 },
637 { 1600, 900, 60, 0 },
638 { 1680, 945, 60, 0 },
639 { 1920, 1080, 60, 0 },
640 { 2048, 1152, 60, 0 },
641 { 2048, 1536, 60, 0 },
645 * Probably taken from CEA-861 spec.
646 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
648 * Index using the VIC.
650 static const struct drm_display_mode edid_cea_modes[] = {
651 /* 0 - dummy, VICs start at 1 */
653 /* 1 - 640x480@60Hz */
654 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
655 752, 800, 0, 480, 490, 492, 525, 0,
656 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
657 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
658 /* 2 - 720x480@60Hz */
659 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
660 798, 858, 0, 480, 489, 495, 525, 0,
661 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
662 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
663 /* 3 - 720x480@60Hz */
664 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
665 798, 858, 0, 480, 489, 495, 525, 0,
666 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
667 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
668 /* 4 - 1280x720@60Hz */
669 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
670 1430, 1650, 0, 720, 725, 730, 750, 0,
671 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
672 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
673 /* 5 - 1920x1080i@60Hz */
674 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
675 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
676 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
677 DRM_MODE_FLAG_INTERLACE),
678 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
679 /* 6 - 720(1440)x480i@60Hz */
680 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
681 801, 858, 0, 480, 488, 494, 525, 0,
682 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
683 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
684 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
685 /* 7 - 720(1440)x480i@60Hz */
686 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
687 801, 858, 0, 480, 488, 494, 525, 0,
688 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
689 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
690 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
691 /* 8 - 720(1440)x240@60Hz */
692 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
693 801, 858, 0, 240, 244, 247, 262, 0,
694 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
695 DRM_MODE_FLAG_DBLCLK),
696 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
697 /* 9 - 720(1440)x240@60Hz */
698 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
699 801, 858, 0, 240, 244, 247, 262, 0,
700 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
701 DRM_MODE_FLAG_DBLCLK),
702 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
703 /* 10 - 2880x480i@60Hz */
704 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
705 3204, 3432, 0, 480, 488, 494, 525, 0,
706 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
707 DRM_MODE_FLAG_INTERLACE),
708 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
709 /* 11 - 2880x480i@60Hz */
710 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
711 3204, 3432, 0, 480, 488, 494, 525, 0,
712 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
713 DRM_MODE_FLAG_INTERLACE),
714 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
715 /* 12 - 2880x240@60Hz */
716 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
717 3204, 3432, 0, 240, 244, 247, 262, 0,
718 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
719 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
720 /* 13 - 2880x240@60Hz */
721 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
722 3204, 3432, 0, 240, 244, 247, 262, 0,
723 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
724 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
725 /* 14 - 1440x480@60Hz */
726 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
727 1596, 1716, 0, 480, 489, 495, 525, 0,
728 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
729 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
730 /* 15 - 1440x480@60Hz */
731 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
732 1596, 1716, 0, 480, 489, 495, 525, 0,
733 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
734 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
735 /* 16 - 1920x1080@60Hz */
736 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
737 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
738 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
739 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
740 /* 17 - 720x576@50Hz */
741 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
742 796, 864, 0, 576, 581, 586, 625, 0,
743 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
744 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
745 /* 18 - 720x576@50Hz */
746 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
747 796, 864, 0, 576, 581, 586, 625, 0,
748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
749 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
750 /* 19 - 1280x720@50Hz */
751 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
752 1760, 1980, 0, 720, 725, 730, 750, 0,
753 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
754 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
755 /* 20 - 1920x1080i@50Hz */
756 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
757 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
758 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
759 DRM_MODE_FLAG_INTERLACE),
760 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
761 /* 21 - 720(1440)x576i@50Hz */
762 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
763 795, 864, 0, 576, 580, 586, 625, 0,
764 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
765 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
766 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
767 /* 22 - 720(1440)x576i@50Hz */
768 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
769 795, 864, 0, 576, 580, 586, 625, 0,
770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
771 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
772 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
773 /* 23 - 720(1440)x288@50Hz */
774 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
775 795, 864, 0, 288, 290, 293, 312, 0,
776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
777 DRM_MODE_FLAG_DBLCLK),
778 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
779 /* 24 - 720(1440)x288@50Hz */
780 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
781 795, 864, 0, 288, 290, 293, 312, 0,
782 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
783 DRM_MODE_FLAG_DBLCLK),
784 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
785 /* 25 - 2880x576i@50Hz */
786 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
787 3180, 3456, 0, 576, 580, 586, 625, 0,
788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
789 DRM_MODE_FLAG_INTERLACE),
790 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
791 /* 26 - 2880x576i@50Hz */
792 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
793 3180, 3456, 0, 576, 580, 586, 625, 0,
794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
795 DRM_MODE_FLAG_INTERLACE),
796 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
797 /* 27 - 2880x288@50Hz */
798 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
799 3180, 3456, 0, 288, 290, 293, 312, 0,
800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
801 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
802 /* 28 - 2880x288@50Hz */
803 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
804 3180, 3456, 0, 288, 290, 293, 312, 0,
805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
806 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
807 /* 29 - 1440x576@50Hz */
808 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
809 1592, 1728, 0, 576, 581, 586, 625, 0,
810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
811 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
812 /* 30 - 1440x576@50Hz */
813 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
814 1592, 1728, 0, 576, 581, 586, 625, 0,
815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
816 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
817 /* 31 - 1920x1080@50Hz */
818 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
819 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
821 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
822 /* 32 - 1920x1080@24Hz */
823 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
824 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
825 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
826 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
827 /* 33 - 1920x1080@25Hz */
828 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
829 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
830 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
831 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
832 /* 34 - 1920x1080@30Hz */
833 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
834 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
836 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
837 /* 35 - 2880x480@60Hz */
838 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
839 3192, 3432, 0, 480, 489, 495, 525, 0,
840 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
841 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
842 /* 36 - 2880x480@60Hz */
843 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
844 3192, 3432, 0, 480, 489, 495, 525, 0,
845 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
846 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
847 /* 37 - 2880x576@50Hz */
848 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
849 3184, 3456, 0, 576, 581, 586, 625, 0,
850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
851 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
852 /* 38 - 2880x576@50Hz */
853 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
854 3184, 3456, 0, 576, 581, 586, 625, 0,
855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
856 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
857 /* 39 - 1920x1080i@50Hz */
858 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
859 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
860 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
861 DRM_MODE_FLAG_INTERLACE),
862 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
863 /* 40 - 1920x1080i@100Hz */
864 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
865 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
866 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
867 DRM_MODE_FLAG_INTERLACE),
868 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
869 /* 41 - 1280x720@100Hz */
870 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
871 1760, 1980, 0, 720, 725, 730, 750, 0,
872 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
873 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
874 /* 42 - 720x576@100Hz */
875 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
876 796, 864, 0, 576, 581, 586, 625, 0,
877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
878 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
879 /* 43 - 720x576@100Hz */
880 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
881 796, 864, 0, 576, 581, 586, 625, 0,
882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
883 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
884 /* 44 - 720(1440)x576i@100Hz */
885 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
886 795, 864, 0, 576, 580, 586, 625, 0,
887 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
888 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
889 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
890 /* 45 - 720(1440)x576i@100Hz */
891 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
892 795, 864, 0, 576, 580, 586, 625, 0,
893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
894 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
895 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
896 /* 46 - 1920x1080i@120Hz */
897 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
898 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
900 DRM_MODE_FLAG_INTERLACE),
901 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
902 /* 47 - 1280x720@120Hz */
903 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
904 1430, 1650, 0, 720, 725, 730, 750, 0,
905 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
906 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
907 /* 48 - 720x480@120Hz */
908 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
909 798, 858, 0, 480, 489, 495, 525, 0,
910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
911 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
912 /* 49 - 720x480@120Hz */
913 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
914 798, 858, 0, 480, 489, 495, 525, 0,
915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
916 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
917 /* 50 - 720(1440)x480i@120Hz */
918 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
919 801, 858, 0, 480, 488, 494, 525, 0,
920 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
921 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
922 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
923 /* 51 - 720(1440)x480i@120Hz */
924 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
925 801, 858, 0, 480, 488, 494, 525, 0,
926 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
927 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
928 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
929 /* 52 - 720x576@200Hz */
930 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
931 796, 864, 0, 576, 581, 586, 625, 0,
932 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
933 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
934 /* 53 - 720x576@200Hz */
935 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
936 796, 864, 0, 576, 581, 586, 625, 0,
937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
938 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
939 /* 54 - 720(1440)x576i@200Hz */
940 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
941 795, 864, 0, 576, 580, 586, 625, 0,
942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
943 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
944 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
945 /* 55 - 720(1440)x576i@200Hz */
946 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
947 795, 864, 0, 576, 580, 586, 625, 0,
948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
949 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
950 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
951 /* 56 - 720x480@240Hz */
952 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
953 798, 858, 0, 480, 489, 495, 525, 0,
954 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
955 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
956 /* 57 - 720x480@240Hz */
957 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
958 798, 858, 0, 480, 489, 495, 525, 0,
959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
960 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
961 /* 58 - 720(1440)x480i@240Hz */
962 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
963 801, 858, 0, 480, 488, 494, 525, 0,
964 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
965 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
966 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
967 /* 59 - 720(1440)x480i@240Hz */
968 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
969 801, 858, 0, 480, 488, 494, 525, 0,
970 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
971 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
972 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
973 /* 60 - 1280x720@24Hz */
974 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
975 3080, 3300, 0, 720, 725, 730, 750, 0,
976 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
977 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978 /* 61 - 1280x720@25Hz */
979 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
980 3740, 3960, 0, 720, 725, 730, 750, 0,
981 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
982 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
983 /* 62 - 1280x720@30Hz */
984 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
985 3080, 3300, 0, 720, 725, 730, 750, 0,
986 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
987 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
988 /* 63 - 1920x1080@120Hz */
989 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
990 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
991 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
992 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
993 /* 64 - 1920x1080@100Hz */
994 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
995 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
996 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
997 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1001 * HDMI 1.4 4k modes. Index using the VIC.
1003 static const struct drm_display_mode edid_4k_modes[] = {
1004 /* 0 - dummy, VICs start at 1 */
1006 /* 1 - 3840x2160@30Hz */
1007 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1008 3840, 4016, 4104, 4400, 0,
1009 2160, 2168, 2178, 2250, 0,
1010 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1012 /* 2 - 3840x2160@25Hz */
1013 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1014 3840, 4896, 4984, 5280, 0,
1015 2160, 2168, 2178, 2250, 0,
1016 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1018 /* 3 - 3840x2160@24Hz */
1019 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1020 3840, 5116, 5204, 5500, 0,
1021 2160, 2168, 2178, 2250, 0,
1022 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1024 /* 4 - 4096x2160@24Hz (SMPTE) */
1025 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1026 4096, 5116, 5204, 5500, 0,
1027 2160, 2168, 2178, 2250, 0,
1028 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1032 /*** DDC fetch and block validation ***/
1034 static const u8 edid_header[] = {
1035 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1039 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1040 * @raw_edid: pointer to raw base EDID block
1042 * Sanity check the header of the base EDID block.
1044 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1046 int drm_edid_header_is_valid(const u8 *raw_edid)
1050 for (i = 0; i < sizeof(edid_header); i++)
1051 if (raw_edid[i] == edid_header[i])
1056 EXPORT_SYMBOL(drm_edid_header_is_valid);
1058 static int edid_fixup __read_mostly = 6;
1059 module_param_named(edid_fixup, edid_fixup, int, 0400);
1060 MODULE_PARM_DESC(edid_fixup,
1061 "Minimum number of valid EDID header bytes (0-8, default 6)");
1063 static void drm_get_displayid(struct drm_connector *connector,
1066 static int drm_edid_block_checksum(const u8 *raw_edid)
1070 for (i = 0; i < EDID_LENGTH; i++)
1071 csum += raw_edid[i];
1076 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1078 if (memchr_inv(in_edid, 0, length))
1085 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1086 * @raw_edid: pointer to raw EDID block
1087 * @block: type of block to validate (0 for base, extension otherwise)
1088 * @print_bad_edid: if true, dump bad EDID blocks to the console
1089 * @edid_corrupt: if true, the header or checksum is invalid
1091 * Validate a base or extension EDID block and optionally dump bad blocks to
1094 * Return: True if the block is valid, false otherwise.
1096 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1100 struct edid *edid = (struct edid *)raw_edid;
1102 if (WARN_ON(!raw_edid))
1105 if (edid_fixup > 8 || edid_fixup < 0)
1109 int score = drm_edid_header_is_valid(raw_edid);
1112 *edid_corrupt = false;
1113 } else if (score >= edid_fixup) {
1114 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1115 * The corrupt flag needs to be set here otherwise, the
1116 * fix-up code here will correct the problem, the
1117 * checksum is correct and the test fails
1120 *edid_corrupt = true;
1121 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1122 memcpy(raw_edid, edid_header, sizeof(edid_header));
1125 *edid_corrupt = true;
1130 csum = drm_edid_block_checksum(raw_edid);
1132 if (print_bad_edid) {
1133 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
1137 *edid_corrupt = true;
1139 /* allow CEA to slide through, switches mangle this */
1140 if (raw_edid[0] != 0x02)
1144 /* per-block-type checks */
1145 switch (raw_edid[0]) {
1147 if (edid->version != 1) {
1148 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
1152 if (edid->revision > 4)
1153 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1163 if (print_bad_edid) {
1164 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1165 printk(KERN_ERR "EDID block is all zeroes\n");
1167 printk(KERN_ERR "Raw EDID:\n");
1168 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
1169 raw_edid, EDID_LENGTH, false);
1174 EXPORT_SYMBOL(drm_edid_block_valid);
1177 * drm_edid_is_valid - sanity check EDID data
1180 * Sanity-check an entire EDID record (including extensions)
1182 * Return: True if the EDID data is valid, false otherwise.
1184 bool drm_edid_is_valid(struct edid *edid)
1187 u8 *raw = (u8 *)edid;
1192 for (i = 0; i <= edid->extensions; i++)
1193 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1198 EXPORT_SYMBOL(drm_edid_is_valid);
1200 #define DDC_SEGMENT_ADDR 0x30
1202 * drm_do_probe_ddc_edid() - get EDID information via I2C
1203 * @data: I2C device adapter
1204 * @buf: EDID data buffer to be filled
1205 * @block: 128 byte EDID block to start fetching from
1206 * @len: EDID data buffer length to fetch
1208 * Try to fetch EDID information by calling I2C driver functions.
1210 * Return: 0 on success or -1 on failure.
1213 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1215 struct i2c_adapter *adapter = data;
1216 unsigned char start = block * EDID_LENGTH;
1217 unsigned char segment = block >> 1;
1218 unsigned char xfers = segment ? 3 : 2;
1219 int ret, retries = 5;
1222 * The core I2C driver will automatically retry the transfer if the
1223 * adapter reports EAGAIN. However, we find that bit-banging transfers
1224 * are susceptible to errors under a heavily loaded machine and
1225 * generate spurious NAKs and timeouts. Retrying the transfer
1226 * of the individual block a few times seems to overcome this.
1229 struct i2c_msg msgs[] = {
1231 .addr = DDC_SEGMENT_ADDR,
1249 * Avoid sending the segment addr to not upset non-compliant
1252 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1254 if (ret == -ENXIO) {
1255 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1259 } while (ret != xfers && --retries);
1261 return ret == xfers ? 0 : -1;
1264 static void connector_bad_edid(struct drm_connector *connector,
1265 u8 *edid, int num_blocks)
1269 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1272 dev_warn(connector->dev->dev,
1273 "%s: EDID is invalid:\n",
1275 for (i = 0; i < num_blocks; i++) {
1276 u8 *block = edid + i * EDID_LENGTH;
1279 if (drm_edid_is_zero(block, EDID_LENGTH))
1280 sprintf(prefix, "\t[%02x] ZERO ", i);
1281 else if (!drm_edid_block_valid(block, i, false, NULL))
1282 sprintf(prefix, "\t[%02x] BAD ", i);
1284 sprintf(prefix, "\t[%02x] GOOD ", i);
1286 print_hex_dump(KERN_WARNING,
1287 prefix, DUMP_PREFIX_NONE, 16, 1,
1288 block, EDID_LENGTH, false);
1293 * drm_do_get_edid - get EDID data using a custom EDID block read function
1294 * @connector: connector we're probing
1295 * @get_edid_block: EDID block read function
1296 * @data: private data passed to the block read function
1298 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1299 * exposes a different interface to read EDID blocks this function can be used
1300 * to get EDID data using a custom block read function.
1302 * As in the general case the DDC bus is accessible by the kernel at the I2C
1303 * level, drivers must make all reasonable efforts to expose it as an I2C
1304 * adapter and use drm_get_edid() instead of abusing this function.
1306 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1308 struct edid *drm_do_get_edid(struct drm_connector *connector,
1309 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1313 int i, j = 0, valid_extensions = 0;
1316 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1319 /* base block fetch */
1320 for (i = 0; i < 4; i++) {
1321 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1323 if (drm_edid_block_valid(edid, 0, false,
1324 &connector->edid_corrupt))
1326 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1327 connector->null_edid_counter++;
1334 /* if there's no extensions, we're done */
1335 valid_extensions = edid[0x7e];
1336 if (valid_extensions == 0)
1337 return (struct edid *)edid;
1339 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1344 for (j = 1; j <= edid[0x7e]; j++) {
1345 u8 *block = edid + j * EDID_LENGTH;
1347 for (i = 0; i < 4; i++) {
1348 if (get_edid_block(data, block, j, EDID_LENGTH))
1350 if (drm_edid_block_valid(block, j, false, NULL))
1358 if (valid_extensions != edid[0x7e]) {
1361 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1363 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1364 edid[0x7e] = valid_extensions;
1366 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1371 for (i = 0; i <= edid[0x7e]; i++) {
1372 u8 *block = edid + i * EDID_LENGTH;
1374 if (!drm_edid_block_valid(block, i, false, NULL))
1377 memcpy(base, block, EDID_LENGTH);
1378 base += EDID_LENGTH;
1385 return (struct edid *)edid;
1388 connector_bad_edid(connector, edid, 1);
1393 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1396 * drm_probe_ddc() - probe DDC presence
1397 * @adapter: I2C adapter to probe
1399 * Return: True on success, false on failure.
1402 drm_probe_ddc(struct i2c_adapter *adapter)
1406 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1408 EXPORT_SYMBOL(drm_probe_ddc);
1411 * drm_get_edid - get EDID data, if available
1412 * @connector: connector we're probing
1413 * @adapter: I2C adapter to use for DDC
1415 * Poke the given I2C channel to grab EDID data if possible. If found,
1416 * attach it to the connector.
1418 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1420 struct edid *drm_get_edid(struct drm_connector *connector,
1421 struct i2c_adapter *adapter)
1425 if (!drm_probe_ddc(adapter))
1428 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1430 drm_get_displayid(connector, edid);
1433 EXPORT_SYMBOL(drm_get_edid);
1436 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1437 * @connector: connector we're probing
1438 * @adapter: I2C adapter to use for DDC
1440 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1441 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1442 * switch DDC to the GPU which is retrieving EDID.
1444 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1446 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1447 struct i2c_adapter *adapter)
1449 struct pci_dev *pdev = connector->dev->pdev;
1452 vga_switcheroo_lock_ddc(pdev);
1453 edid = drm_get_edid(connector, adapter);
1454 vga_switcheroo_unlock_ddc(pdev);
1458 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1461 * drm_edid_duplicate - duplicate an EDID and the extensions
1462 * @edid: EDID to duplicate
1464 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1466 struct edid *drm_edid_duplicate(const struct edid *edid)
1468 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1470 EXPORT_SYMBOL(drm_edid_duplicate);
1472 /*** EDID parsing ***/
1475 * edid_vendor - match a string against EDID's obfuscated vendor field
1476 * @edid: EDID to match
1477 * @vendor: vendor string
1479 * Returns true if @vendor is in @edid, false otherwise
1481 static bool edid_vendor(struct edid *edid, const char *vendor)
1483 char edid_vendor[3];
1485 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1486 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1487 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1488 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1490 return !strncmp(edid_vendor, vendor, 3);
1494 * edid_get_quirks - return quirk flags for a given EDID
1495 * @edid: EDID to process
1497 * This tells subsequent routines what fixes they need to apply.
1499 static u32 edid_get_quirks(struct edid *edid)
1501 const struct edid_quirk *quirk;
1504 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1505 quirk = &edid_quirk_list[i];
1507 if (edid_vendor(edid, quirk->vendor) &&
1508 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1509 return quirk->quirks;
1515 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1516 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1519 * edid_fixup_preferred - set preferred modes based on quirk list
1520 * @connector: has mode list to fix up
1521 * @quirks: quirks list
1523 * Walk the mode list for @connector, clearing the preferred status
1524 * on existing modes and setting it anew for the right mode ala @quirks.
1526 static void edid_fixup_preferred(struct drm_connector *connector,
1529 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1530 int target_refresh = 0;
1531 int cur_vrefresh, preferred_vrefresh;
1533 if (list_empty(&connector->probed_modes))
1536 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1537 target_refresh = 60;
1538 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1539 target_refresh = 75;
1541 preferred_mode = list_first_entry(&connector->probed_modes,
1542 struct drm_display_mode, head);
1544 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1545 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1547 if (cur_mode == preferred_mode)
1550 /* Largest mode is preferred */
1551 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1552 preferred_mode = cur_mode;
1554 cur_vrefresh = cur_mode->vrefresh ?
1555 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1556 preferred_vrefresh = preferred_mode->vrefresh ?
1557 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1558 /* At a given size, try to get closest to target refresh */
1559 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1560 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1561 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1562 preferred_mode = cur_mode;
1566 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1570 mode_is_rb(const struct drm_display_mode *mode)
1572 return (mode->htotal - mode->hdisplay == 160) &&
1573 (mode->hsync_end - mode->hdisplay == 80) &&
1574 (mode->hsync_end - mode->hsync_start == 32) &&
1575 (mode->vsync_start - mode->vdisplay == 3);
1579 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1580 * @dev: Device to duplicate against
1581 * @hsize: Mode width
1582 * @vsize: Mode height
1583 * @fresh: Mode refresh rate
1584 * @rb: Mode reduced-blanking-ness
1586 * Walk the DMT mode list looking for a match for the given parameters.
1588 * Return: A newly allocated copy of the mode, or NULL if not found.
1590 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1591 int hsize, int vsize, int fresh,
1596 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1597 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1598 if (hsize != ptr->hdisplay)
1600 if (vsize != ptr->vdisplay)
1602 if (fresh != drm_mode_vrefresh(ptr))
1604 if (rb != mode_is_rb(ptr))
1607 return drm_mode_duplicate(dev, ptr);
1612 EXPORT_SYMBOL(drm_mode_find_dmt);
1614 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1617 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1621 u8 *det_base = ext + d;
1624 for (i = 0; i < n; i++)
1625 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1629 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1631 unsigned int i, n = min((int)ext[0x02], 6);
1632 u8 *det_base = ext + 5;
1635 return; /* unknown version */
1637 for (i = 0; i < n; i++)
1638 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1642 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1645 struct edid *edid = (struct edid *)raw_edid;
1650 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1651 cb(&(edid->detailed_timings[i]), closure);
1653 for (i = 1; i <= raw_edid[0x7e]; i++) {
1654 u8 *ext = raw_edid + (i * EDID_LENGTH);
1657 cea_for_each_detailed_block(ext, cb, closure);
1660 vtb_for_each_detailed_block(ext, cb, closure);
1669 is_rb(struct detailed_timing *t, void *data)
1672 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1674 *(bool *)data = true;
1677 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1679 drm_monitor_supports_rb(struct edid *edid)
1681 if (edid->revision >= 4) {
1683 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1687 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1691 find_gtf2(struct detailed_timing *t, void *data)
1694 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1698 /* Secondary GTF curve kicks in above some break frequency */
1700 drm_gtf2_hbreak(struct edid *edid)
1703 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1704 return r ? (r[12] * 2) : 0;
1708 drm_gtf2_2c(struct edid *edid)
1711 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1712 return r ? r[13] : 0;
1716 drm_gtf2_m(struct edid *edid)
1719 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1720 return r ? (r[15] << 8) + r[14] : 0;
1724 drm_gtf2_k(struct edid *edid)
1727 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1728 return r ? r[16] : 0;
1732 drm_gtf2_2j(struct edid *edid)
1735 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1736 return r ? r[17] : 0;
1740 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1741 * @edid: EDID block to scan
1743 static int standard_timing_level(struct edid *edid)
1745 if (edid->revision >= 2) {
1746 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1748 if (drm_gtf2_hbreak(edid))
1756 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1757 * monitors fill with ascii space (0x20) instead.
1760 bad_std_timing(u8 a, u8 b)
1762 return (a == 0x00 && b == 0x00) ||
1763 (a == 0x01 && b == 0x01) ||
1764 (a == 0x20 && b == 0x20);
1768 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
1769 * @connector: connector of for the EDID block
1770 * @edid: EDID block to scan
1771 * @t: standard timing params
1773 * Take the standard timing params (in this case width, aspect, and refresh)
1774 * and convert them into a real mode using CVT/GTF/DMT.
1776 static struct drm_display_mode *
1777 drm_mode_std(struct drm_connector *connector, struct edid *edid,
1778 struct std_timing *t)
1780 struct drm_device *dev = connector->dev;
1781 struct drm_display_mode *m, *mode = NULL;
1784 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
1785 >> EDID_TIMING_ASPECT_SHIFT;
1786 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
1787 >> EDID_TIMING_VFREQ_SHIFT;
1788 int timing_level = standard_timing_level(edid);
1790 if (bad_std_timing(t->hsize, t->vfreq_aspect))
1793 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1794 hsize = t->hsize * 8 + 248;
1795 /* vrefresh_rate = vfreq + 60 */
1796 vrefresh_rate = vfreq + 60;
1797 /* the vdisplay is calculated based on the aspect ratio */
1798 if (aspect_ratio == 0) {
1799 if (edid->revision < 3)
1802 vsize = (hsize * 10) / 16;
1803 } else if (aspect_ratio == 1)
1804 vsize = (hsize * 3) / 4;
1805 else if (aspect_ratio == 2)
1806 vsize = (hsize * 4) / 5;
1808 vsize = (hsize * 9) / 16;
1810 /* HDTV hack, part 1 */
1811 if (vrefresh_rate == 60 &&
1812 ((hsize == 1360 && vsize == 765) ||
1813 (hsize == 1368 && vsize == 769))) {
1819 * If this connector already has a mode for this size and refresh
1820 * rate (because it came from detailed or CVT info), use that
1821 * instead. This way we don't have to guess at interlace or
1824 list_for_each_entry(m, &connector->probed_modes, head)
1825 if (m->hdisplay == hsize && m->vdisplay == vsize &&
1826 drm_mode_vrefresh(m) == vrefresh_rate)
1829 /* HDTV hack, part 2 */
1830 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
1831 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
1833 mode->hdisplay = 1366;
1834 mode->hsync_start = mode->hsync_start - 1;
1835 mode->hsync_end = mode->hsync_end - 1;
1839 /* check whether it can be found in default mode table */
1840 if (drm_monitor_supports_rb(edid)) {
1841 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
1846 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
1850 /* okay, generate it */
1851 switch (timing_level) {
1855 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1859 * This is potentially wrong if there's ever a monitor with
1860 * more than one ranges section, each claiming a different
1861 * secondary GTF curve. Please don't do that.
1863 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1866 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
1867 drm_mode_destroy(dev, mode);
1868 mode = drm_gtf_mode_complex(dev, hsize, vsize,
1869 vrefresh_rate, 0, 0,
1877 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
1885 * EDID is delightfully ambiguous about how interlaced modes are to be
1886 * encoded. Our internal representation is of frame height, but some
1887 * HDTV detailed timings are encoded as field height.
1889 * The format list here is from CEA, in frame size. Technically we
1890 * should be checking refresh rate too. Whatever.
1893 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
1894 struct detailed_pixel_timing *pt)
1897 static const struct {
1899 } cea_interlaced[] = {
1909 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
1912 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
1913 if ((mode->hdisplay == cea_interlaced[i].w) &&
1914 (mode->vdisplay == cea_interlaced[i].h / 2)) {
1915 mode->vdisplay *= 2;
1916 mode->vsync_start *= 2;
1917 mode->vsync_end *= 2;
1923 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1927 * drm_mode_detailed - create a new mode from an EDID detailed timing section
1928 * @dev: DRM device (needed to create new mode)
1930 * @timing: EDID detailed timing info
1931 * @quirks: quirks to apply
1933 * An EDID detailed timing block contains enough info for us to create and
1934 * return a new struct drm_display_mode.
1936 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
1938 struct detailed_timing *timing,
1941 struct drm_display_mode *mode;
1942 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
1943 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
1944 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
1945 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
1946 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
1947 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
1948 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
1949 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
1950 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
1952 /* ignore tiny modes */
1953 if (hactive < 64 || vactive < 64)
1956 if (pt->misc & DRM_EDID_PT_STEREO) {
1957 DRM_DEBUG_KMS("stereo mode not supported\n");
1960 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
1961 DRM_DEBUG_KMS("composite sync not supported\n");
1964 /* it is incorrect if hsync/vsync width is zero */
1965 if (!hsync_pulse_width || !vsync_pulse_width) {
1966 DRM_DEBUG_KMS("Incorrect Detailed timing. "
1967 "Wrong Hsync/Vsync pulse width\n");
1971 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
1972 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
1979 mode = drm_mode_create(dev);
1983 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
1984 timing->pixel_clock = cpu_to_le16(1088);
1986 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
1988 mode->hdisplay = hactive;
1989 mode->hsync_start = mode->hdisplay + hsync_offset;
1990 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
1991 mode->htotal = mode->hdisplay + hblank;
1993 mode->vdisplay = vactive;
1994 mode->vsync_start = mode->vdisplay + vsync_offset;
1995 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
1996 mode->vtotal = mode->vdisplay + vblank;
1998 /* Some EDIDs have bogus h/vtotal values */
1999 if (mode->hsync_end > mode->htotal)
2000 mode->htotal = mode->hsync_end + 1;
2001 if (mode->vsync_end > mode->vtotal)
2002 mode->vtotal = mode->vsync_end + 1;
2004 drm_mode_do_interlace_quirk(mode, pt);
2006 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2007 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2010 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2011 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2012 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2013 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2016 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2017 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2019 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2020 mode->width_mm *= 10;
2021 mode->height_mm *= 10;
2024 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2025 mode->width_mm = edid->width_cm * 10;
2026 mode->height_mm = edid->height_cm * 10;
2029 mode->type = DRM_MODE_TYPE_DRIVER;
2030 mode->vrefresh = drm_mode_vrefresh(mode);
2031 drm_mode_set_name(mode);
2037 mode_in_hsync_range(const struct drm_display_mode *mode,
2038 struct edid *edid, u8 *t)
2040 int hsync, hmin, hmax;
2043 if (edid->revision >= 4)
2044 hmin += ((t[4] & 0x04) ? 255 : 0);
2046 if (edid->revision >= 4)
2047 hmax += ((t[4] & 0x08) ? 255 : 0);
2048 hsync = drm_mode_hsync(mode);
2050 return (hsync <= hmax && hsync >= hmin);
2054 mode_in_vsync_range(const struct drm_display_mode *mode,
2055 struct edid *edid, u8 *t)
2057 int vsync, vmin, vmax;
2060 if (edid->revision >= 4)
2061 vmin += ((t[4] & 0x01) ? 255 : 0);
2063 if (edid->revision >= 4)
2064 vmax += ((t[4] & 0x02) ? 255 : 0);
2065 vsync = drm_mode_vrefresh(mode);
2067 return (vsync <= vmax && vsync >= vmin);
2071 range_pixel_clock(struct edid *edid, u8 *t)
2074 if (t[9] == 0 || t[9] == 255)
2077 /* 1.4 with CVT support gives us real precision, yay */
2078 if (edid->revision >= 4 && t[10] == 0x04)
2079 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2081 /* 1.3 is pathetic, so fuzz up a bit */
2082 return t[9] * 10000 + 5001;
2086 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2087 struct detailed_timing *timing)
2090 u8 *t = (u8 *)timing;
2092 if (!mode_in_hsync_range(mode, edid, t))
2095 if (!mode_in_vsync_range(mode, edid, t))
2098 if ((max_clock = range_pixel_clock(edid, t)))
2099 if (mode->clock > max_clock)
2102 /* 1.4 max horizontal check */
2103 if (edid->revision >= 4 && t[10] == 0x04)
2104 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2107 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2113 static bool valid_inferred_mode(const struct drm_connector *connector,
2114 const struct drm_display_mode *mode)
2116 const struct drm_display_mode *m;
2119 list_for_each_entry(m, &connector->probed_modes, head) {
2120 if (mode->hdisplay == m->hdisplay &&
2121 mode->vdisplay == m->vdisplay &&
2122 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2123 return false; /* duplicated */
2124 if (mode->hdisplay <= m->hdisplay &&
2125 mode->vdisplay <= m->vdisplay)
2132 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2133 struct detailed_timing *timing)
2136 struct drm_display_mode *newmode;
2137 struct drm_device *dev = connector->dev;
2139 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2140 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2141 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2142 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2144 drm_mode_probed_add(connector, newmode);
2153 /* fix up 1366x768 mode from 1368x768;
2154 * GFT/CVT can't express 1366 width which isn't dividable by 8
2156 static void fixup_mode_1366x768(struct drm_display_mode *mode)
2158 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2159 mode->hdisplay = 1366;
2160 mode->hsync_start--;
2162 drm_mode_set_name(mode);
2167 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2168 struct detailed_timing *timing)
2171 struct drm_display_mode *newmode;
2172 struct drm_device *dev = connector->dev;
2174 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2175 const struct minimode *m = &extra_modes[i];
2176 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2180 fixup_mode_1366x768(newmode);
2181 if (!mode_in_range(newmode, edid, timing) ||
2182 !valid_inferred_mode(connector, newmode)) {
2183 drm_mode_destroy(dev, newmode);
2187 drm_mode_probed_add(connector, newmode);
2195 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2196 struct detailed_timing *timing)
2199 struct drm_display_mode *newmode;
2200 struct drm_device *dev = connector->dev;
2201 bool rb = drm_monitor_supports_rb(edid);
2203 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2204 const struct minimode *m = &extra_modes[i];
2205 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2209 fixup_mode_1366x768(newmode);
2210 if (!mode_in_range(newmode, edid, timing) ||
2211 !valid_inferred_mode(connector, newmode)) {
2212 drm_mode_destroy(dev, newmode);
2216 drm_mode_probed_add(connector, newmode);
2224 do_inferred_modes(struct detailed_timing *timing, void *c)
2226 struct detailed_mode_closure *closure = c;
2227 struct detailed_non_pixel *data = &timing->data.other_data;
2228 struct detailed_data_monitor_range *range = &data->data.range;
2230 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2233 closure->modes += drm_dmt_modes_for_range(closure->connector,
2237 if (!version_greater(closure->edid, 1, 1))
2238 return; /* GTF not defined yet */
2240 switch (range->flags) {
2241 case 0x02: /* secondary gtf, XXX could do more */
2242 case 0x00: /* default gtf */
2243 closure->modes += drm_gtf_modes_for_range(closure->connector,
2247 case 0x04: /* cvt, only in 1.4+ */
2248 if (!version_greater(closure->edid, 1, 3))
2251 closure->modes += drm_cvt_modes_for_range(closure->connector,
2255 case 0x01: /* just the ranges, no formula */
2262 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2264 struct detailed_mode_closure closure = {
2265 .connector = connector,
2269 if (version_greater(edid, 1, 0))
2270 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2273 return closure.modes;
2277 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2279 int i, j, m, modes = 0;
2280 struct drm_display_mode *mode;
2281 u8 *est = ((u8 *)timing) + 6;
2283 for (i = 0; i < 6; i++) {
2284 for (j = 7; j >= 0; j--) {
2285 m = (i * 8) + (7 - j);
2286 if (m >= ARRAY_SIZE(est3_modes))
2288 if (est[i] & (1 << j)) {
2289 mode = drm_mode_find_dmt(connector->dev,
2295 drm_mode_probed_add(connector, mode);
2306 do_established_modes(struct detailed_timing *timing, void *c)
2308 struct detailed_mode_closure *closure = c;
2309 struct detailed_non_pixel *data = &timing->data.other_data;
2311 if (data->type == EDID_DETAIL_EST_TIMINGS)
2312 closure->modes += drm_est3_modes(closure->connector, timing);
2316 * add_established_modes - get est. modes from EDID and add them
2317 * @connector: connector to add mode(s) to
2318 * @edid: EDID block to scan
2320 * Each EDID block contains a bitmap of the supported "established modes" list
2321 * (defined above). Tease them out and add them to the global modes list.
2324 add_established_modes(struct drm_connector *connector, struct edid *edid)
2326 struct drm_device *dev = connector->dev;
2327 unsigned long est_bits = edid->established_timings.t1 |
2328 (edid->established_timings.t2 << 8) |
2329 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2331 struct detailed_mode_closure closure = {
2332 .connector = connector,
2336 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2337 if (est_bits & (1<<i)) {
2338 struct drm_display_mode *newmode;
2339 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2341 drm_mode_probed_add(connector, newmode);
2347 if (version_greater(edid, 1, 0))
2348 drm_for_each_detailed_block((u8 *)edid,
2349 do_established_modes, &closure);
2351 return modes + closure.modes;
2355 do_standard_modes(struct detailed_timing *timing, void *c)
2357 struct detailed_mode_closure *closure = c;
2358 struct detailed_non_pixel *data = &timing->data.other_data;
2359 struct drm_connector *connector = closure->connector;
2360 struct edid *edid = closure->edid;
2362 if (data->type == EDID_DETAIL_STD_MODES) {
2364 for (i = 0; i < 6; i++) {
2365 struct std_timing *std;
2366 struct drm_display_mode *newmode;
2368 std = &data->data.timings[i];
2369 newmode = drm_mode_std(connector, edid, std);
2371 drm_mode_probed_add(connector, newmode);
2379 * add_standard_modes - get std. modes from EDID and add them
2380 * @connector: connector to add mode(s) to
2381 * @edid: EDID block to scan
2383 * Standard modes can be calculated using the appropriate standard (DMT,
2384 * GTF or CVT. Grab them from @edid and add them to the list.
2387 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2390 struct detailed_mode_closure closure = {
2391 .connector = connector,
2395 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2396 struct drm_display_mode *newmode;
2398 newmode = drm_mode_std(connector, edid,
2399 &edid->standard_timings[i]);
2401 drm_mode_probed_add(connector, newmode);
2406 if (version_greater(edid, 1, 0))
2407 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2410 /* XXX should also look for standard codes in VTB blocks */
2412 return modes + closure.modes;
2415 static int drm_cvt_modes(struct drm_connector *connector,
2416 struct detailed_timing *timing)
2418 int i, j, modes = 0;
2419 struct drm_display_mode *newmode;
2420 struct drm_device *dev = connector->dev;
2421 struct cvt_timing *cvt;
2422 const int rates[] = { 60, 85, 75, 60, 50 };
2423 const u8 empty[3] = { 0, 0, 0 };
2425 for (i = 0; i < 4; i++) {
2426 int uninitialized_var(width), height;
2427 cvt = &(timing->data.other_data.data.cvt[i]);
2429 if (!memcmp(cvt->code, empty, 3))
2432 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2433 switch (cvt->code[1] & 0x0c) {
2435 width = height * 4 / 3;
2438 width = height * 16 / 9;
2441 width = height * 16 / 10;
2444 width = height * 15 / 9;
2448 for (j = 1; j < 5; j++) {
2449 if (cvt->code[2] & (1 << j)) {
2450 newmode = drm_cvt_mode(dev, width, height,
2454 drm_mode_probed_add(connector, newmode);
2465 do_cvt_mode(struct detailed_timing *timing, void *c)
2467 struct detailed_mode_closure *closure = c;
2468 struct detailed_non_pixel *data = &timing->data.other_data;
2470 if (data->type == EDID_DETAIL_CVT_3BYTE)
2471 closure->modes += drm_cvt_modes(closure->connector, timing);
2475 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2477 struct detailed_mode_closure closure = {
2478 .connector = connector,
2482 if (version_greater(edid, 1, 2))
2483 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2485 /* XXX should also look for CVT codes in VTB blocks */
2487 return closure.modes;
2490 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2493 do_detailed_mode(struct detailed_timing *timing, void *c)
2495 struct detailed_mode_closure *closure = c;
2496 struct drm_display_mode *newmode;
2498 if (timing->pixel_clock) {
2499 newmode = drm_mode_detailed(closure->connector->dev,
2500 closure->edid, timing,
2505 if (closure->preferred)
2506 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2509 * Detailed modes are limited to 10kHz pixel clock resolution,
2510 * so fix up anything that looks like CEA/HDMI mode, but the clock
2511 * is just slightly off.
2513 fixup_detailed_cea_mode_clock(newmode);
2515 drm_mode_probed_add(closure->connector, newmode);
2517 closure->preferred = 0;
2522 * add_detailed_modes - Add modes from detailed timings
2523 * @connector: attached connector
2524 * @edid: EDID block to scan
2525 * @quirks: quirks to apply
2528 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2531 struct detailed_mode_closure closure = {
2532 .connector = connector,
2538 if (closure.preferred && !version_greater(edid, 1, 3))
2540 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2542 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2544 return closure.modes;
2547 #define AUDIO_BLOCK 0x01
2548 #define VIDEO_BLOCK 0x02
2549 #define VENDOR_BLOCK 0x03
2550 #define SPEAKER_BLOCK 0x04
2551 #define VIDEO_CAPABILITY_BLOCK 0x07
2552 #define EDID_BASIC_AUDIO (1 << 6)
2553 #define EDID_CEA_YCRCB444 (1 << 5)
2554 #define EDID_CEA_YCRCB422 (1 << 4)
2555 #define EDID_CEA_VCDB_QS (1 << 6)
2558 * Search EDID for CEA extension block.
2560 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
2562 u8 *edid_ext = NULL;
2565 /* No EDID or EDID extensions */
2566 if (edid == NULL || edid->extensions == 0)
2569 /* Find CEA extension */
2570 for (i = 0; i < edid->extensions; i++) {
2571 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2572 if (edid_ext[0] == ext_id)
2576 if (i == edid->extensions)
2582 static u8 *drm_find_cea_extension(struct edid *edid)
2584 return drm_find_edid_extension(edid, CEA_EXT);
2587 static u8 *drm_find_displayid_extension(struct edid *edid)
2589 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2593 * Calculate the alternate clock for the CEA mode
2594 * (60Hz vs. 59.94Hz etc.)
2597 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2599 unsigned int clock = cea_mode->clock;
2601 if (cea_mode->vrefresh % 6 != 0)
2605 * edid_cea_modes contains the 59.94Hz
2606 * variant for 240 and 480 line modes,
2607 * and the 60Hz variant otherwise.
2609 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2610 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2612 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2618 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2621 * For certain VICs the spec allows the vertical
2622 * front porch to vary by one or two lines.
2624 * cea_modes[] stores the variant with the shortest
2625 * vertical front porch. We can adjust the mode to
2626 * get the other variants by simply increasing the
2627 * vertical front porch length.
2629 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2630 edid_cea_modes[9].vtotal != 262 ||
2631 edid_cea_modes[12].vtotal != 262 ||
2632 edid_cea_modes[13].vtotal != 262 ||
2633 edid_cea_modes[23].vtotal != 312 ||
2634 edid_cea_modes[24].vtotal != 312 ||
2635 edid_cea_modes[27].vtotal != 312 ||
2636 edid_cea_modes[28].vtotal != 312);
2638 if (((vic == 8 || vic == 9 ||
2639 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2640 ((vic == 23 || vic == 24 ||
2641 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2642 mode->vsync_start++;
2652 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2653 unsigned int clock_tolerance)
2657 if (!to_match->clock)
2660 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2661 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2662 unsigned int clock1, clock2;
2664 /* Check both 60Hz and 59.94Hz */
2665 clock1 = cea_mode.clock;
2666 clock2 = cea_mode_alternate_clock(&cea_mode);
2668 if (abs(to_match->clock - clock1) > clock_tolerance &&
2669 abs(to_match->clock - clock2) > clock_tolerance)
2673 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2675 } while (cea_mode_alternate_timings(vic, &cea_mode));
2682 * drm_match_cea_mode - look for a CEA mode matching given mode
2683 * @to_match: display mode
2685 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2688 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2692 if (!to_match->clock)
2695 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2696 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2697 unsigned int clock1, clock2;
2699 /* Check both 60Hz and 59.94Hz */
2700 clock1 = cea_mode.clock;
2701 clock2 = cea_mode_alternate_clock(&cea_mode);
2703 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2704 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2708 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2710 } while (cea_mode_alternate_timings(vic, &cea_mode));
2715 EXPORT_SYMBOL(drm_match_cea_mode);
2717 static bool drm_valid_cea_vic(u8 vic)
2719 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2723 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2724 * the input VIC from the CEA mode list
2725 * @video_code: ID given to each of the CEA modes
2727 * Returns picture aspect ratio
2729 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2731 return edid_cea_modes[video_code].picture_aspect_ratio;
2733 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2736 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2739 * It's almost like cea_mode_alternate_clock(), we just need to add an
2740 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2744 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2746 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2747 return hdmi_mode->clock;
2749 return cea_mode_alternate_clock(hdmi_mode);
2752 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
2753 unsigned int clock_tolerance)
2757 if (!to_match->clock)
2760 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2761 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2762 unsigned int clock1, clock2;
2764 /* Make sure to also match alternate clocks */
2765 clock1 = hdmi_mode->clock;
2766 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2768 if (abs(to_match->clock - clock1) > clock_tolerance &&
2769 abs(to_match->clock - clock2) > clock_tolerance)
2772 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
2780 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2781 * @to_match: display mode
2783 * An HDMI mode is one defined in the HDMI vendor specific block.
2785 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2787 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
2791 if (!to_match->clock)
2794 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2795 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2796 unsigned int clock1, clock2;
2798 /* Make sure to also match alternate clocks */
2799 clock1 = hdmi_mode->clock;
2800 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2802 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2803 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2804 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
2810 static bool drm_valid_hdmi_vic(u8 vic)
2812 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
2816 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
2818 struct drm_device *dev = connector->dev;
2819 struct drm_display_mode *mode, *tmp;
2823 /* Don't add CEA modes if the CEA extension block is missing */
2824 if (!drm_find_cea_extension(edid))
2828 * Go through all probed modes and create a new mode
2829 * with the alternate clock for certain CEA modes.
2831 list_for_each_entry(mode, &connector->probed_modes, head) {
2832 const struct drm_display_mode *cea_mode = NULL;
2833 struct drm_display_mode *newmode;
2834 u8 vic = drm_match_cea_mode(mode);
2835 unsigned int clock1, clock2;
2837 if (drm_valid_cea_vic(vic)) {
2838 cea_mode = &edid_cea_modes[vic];
2839 clock2 = cea_mode_alternate_clock(cea_mode);
2841 vic = drm_match_hdmi_mode(mode);
2842 if (drm_valid_hdmi_vic(vic)) {
2843 cea_mode = &edid_4k_modes[vic];
2844 clock2 = hdmi_mode_alternate_clock(cea_mode);
2851 clock1 = cea_mode->clock;
2853 if (clock1 == clock2)
2856 if (mode->clock != clock1 && mode->clock != clock2)
2859 newmode = drm_mode_duplicate(dev, cea_mode);
2863 /* Carry over the stereo flags */
2864 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
2867 * The current mode could be either variant. Make
2868 * sure to pick the "other" clock for the new mode.
2870 if (mode->clock != clock1)
2871 newmode->clock = clock1;
2873 newmode->clock = clock2;
2875 list_add_tail(&newmode->head, &list);
2878 list_for_each_entry_safe(mode, tmp, &list, head) {
2879 list_del(&mode->head);
2880 drm_mode_probed_add(connector, mode);
2887 static struct drm_display_mode *
2888 drm_display_mode_from_vic_index(struct drm_connector *connector,
2889 const u8 *video_db, u8 video_len,
2892 struct drm_device *dev = connector->dev;
2893 struct drm_display_mode *newmode;
2896 if (video_db == NULL || video_index >= video_len)
2899 /* CEA modes are numbered 1..127 */
2900 vic = (video_db[video_index] & 127);
2901 if (!drm_valid_cea_vic(vic))
2904 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
2908 newmode->vrefresh = 0;
2914 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
2918 for (i = 0; i < len; i++) {
2919 struct drm_display_mode *mode;
2920 mode = drm_display_mode_from_vic_index(connector, db, len, i);
2922 drm_mode_probed_add(connector, mode);
2930 struct stereo_mandatory_mode {
2931 int width, height, vrefresh;
2935 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
2936 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2937 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
2939 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2941 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2942 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2943 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
2944 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2945 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
2949 stereo_match_mandatory(const struct drm_display_mode *mode,
2950 const struct stereo_mandatory_mode *stereo_mode)
2952 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
2954 return mode->hdisplay == stereo_mode->width &&
2955 mode->vdisplay == stereo_mode->height &&
2956 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
2957 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
2960 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
2962 struct drm_device *dev = connector->dev;
2963 const struct drm_display_mode *mode;
2964 struct list_head stereo_modes;
2967 INIT_LIST_HEAD(&stereo_modes);
2969 list_for_each_entry(mode, &connector->probed_modes, head) {
2970 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
2971 const struct stereo_mandatory_mode *mandatory;
2972 struct drm_display_mode *new_mode;
2974 if (!stereo_match_mandatory(mode,
2975 &stereo_mandatory_modes[i]))
2978 mandatory = &stereo_mandatory_modes[i];
2979 new_mode = drm_mode_duplicate(dev, mode);
2983 new_mode->flags |= mandatory->flags;
2984 list_add_tail(&new_mode->head, &stereo_modes);
2989 list_splice_tail(&stereo_modes, &connector->probed_modes);
2994 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
2996 struct drm_device *dev = connector->dev;
2997 struct drm_display_mode *newmode;
2999 if (!drm_valid_hdmi_vic(vic)) {
3000 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3004 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3008 drm_mode_probed_add(connector, newmode);
3013 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3014 const u8 *video_db, u8 video_len, u8 video_index)
3016 struct drm_display_mode *newmode;
3019 if (structure & (1 << 0)) {
3020 newmode = drm_display_mode_from_vic_index(connector, video_db,
3024 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3025 drm_mode_probed_add(connector, newmode);
3029 if (structure & (1 << 6)) {
3030 newmode = drm_display_mode_from_vic_index(connector, video_db,
3034 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3035 drm_mode_probed_add(connector, newmode);
3039 if (structure & (1 << 8)) {
3040 newmode = drm_display_mode_from_vic_index(connector, video_db,
3044 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3045 drm_mode_probed_add(connector, newmode);
3054 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3055 * @connector: connector corresponding to the HDMI sink
3056 * @db: start of the CEA vendor specific block
3057 * @len: length of the CEA block payload, ie. one can access up to db[len]
3059 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3060 * also adds the stereo 3d modes when applicable.
3063 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3064 const u8 *video_db, u8 video_len)
3066 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3067 u8 vic_len, hdmi_3d_len = 0;
3074 /* no HDMI_Video_Present */
3075 if (!(db[8] & (1 << 5)))
3078 /* Latency_Fields_Present */
3079 if (db[8] & (1 << 7))
3082 /* I_Latency_Fields_Present */
3083 if (db[8] & (1 << 6))
3086 /* the declared length is not long enough for the 2 first bytes
3087 * of additional video format capabilities */
3088 if (len < (8 + offset + 2))
3093 if (db[8 + offset] & (1 << 7)) {
3094 modes += add_hdmi_mandatory_stereo_modes(connector);
3096 /* 3D_Multi_present */
3097 multi_present = (db[8 + offset] & 0x60) >> 5;
3101 vic_len = db[8 + offset] >> 5;
3102 hdmi_3d_len = db[8 + offset] & 0x1f;
3104 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3107 vic = db[9 + offset + i];
3108 modes += add_hdmi_mode(connector, vic);
3110 offset += 1 + vic_len;
3112 if (multi_present == 1)
3114 else if (multi_present == 2)
3119 if (len < (8 + offset + hdmi_3d_len - 1))
3122 if (hdmi_3d_len < multi_len)
3125 if (multi_present == 1 || multi_present == 2) {
3126 /* 3D_Structure_ALL */
3127 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3129 /* check if 3D_MASK is present */
3130 if (multi_present == 2)
3131 mask = (db[10 + offset] << 8) | db[11 + offset];
3135 for (i = 0; i < 16; i++) {
3136 if (mask & (1 << i))
3137 modes += add_3d_struct_modes(connector,
3144 offset += multi_len;
3146 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3148 struct drm_display_mode *newmode = NULL;
3149 unsigned int newflag = 0;
3150 bool detail_present;
3152 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3154 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3157 /* 2D_VIC_order_X */
3158 vic_index = db[8 + offset + i] >> 4;
3160 /* 3D_Structure_X */
3161 switch (db[8 + offset + i] & 0x0f) {
3163 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3166 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3170 if ((db[9 + offset + i] >> 4) == 1)
3171 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3176 newmode = drm_display_mode_from_vic_index(connector,
3182 newmode->flags |= newflag;
3183 drm_mode_probed_add(connector, newmode);
3197 cea_db_payload_len(const u8 *db)
3199 return db[0] & 0x1f;
3203 cea_db_tag(const u8 *db)
3209 cea_revision(const u8 *cea)
3215 cea_db_offsets(const u8 *cea, int *start, int *end)
3217 /* Data block offset in CEA extension block */
3222 if (*end < 4 || *end > 127)
3227 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3231 if (cea_db_tag(db) != VENDOR_BLOCK)
3234 if (cea_db_payload_len(db) < 5)
3237 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3239 return hdmi_id == HDMI_IEEE_OUI;
3242 #define for_each_cea_db(cea, i, start, end) \
3243 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3246 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3248 const u8 *cea = drm_find_cea_extension(edid);
3249 const u8 *db, *hdmi = NULL, *video = NULL;
3250 u8 dbl, hdmi_len, video_len = 0;
3253 if (cea && cea_revision(cea) >= 3) {
3256 if (cea_db_offsets(cea, &start, &end))
3259 for_each_cea_db(cea, i, start, end) {
3261 dbl = cea_db_payload_len(db);
3263 if (cea_db_tag(db) == VIDEO_BLOCK) {
3266 modes += do_cea_modes(connector, video, dbl);
3268 else if (cea_db_is_hdmi_vsdb(db)) {
3276 * We parse the HDMI VSDB after having added the cea modes as we will
3277 * be patching their flags when the sink supports stereo 3D.
3280 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3286 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3288 const struct drm_display_mode *cea_mode;
3289 int clock1, clock2, clock;
3294 * allow 5kHz clock difference either way to account for
3295 * the 10kHz clock resolution limit of detailed timings.
3297 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3298 if (drm_valid_cea_vic(vic)) {
3300 cea_mode = &edid_cea_modes[vic];
3301 clock1 = cea_mode->clock;
3302 clock2 = cea_mode_alternate_clock(cea_mode);
3304 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3305 if (drm_valid_hdmi_vic(vic)) {
3307 cea_mode = &edid_4k_modes[vic];
3308 clock1 = cea_mode->clock;
3309 clock2 = hdmi_mode_alternate_clock(cea_mode);
3315 /* pick whichever is closest */
3316 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3321 if (mode->clock == clock)
3324 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3325 type, vic, mode->clock, clock);
3326 mode->clock = clock;
3330 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3332 u8 len = cea_db_payload_len(db);
3335 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3337 connector->latency_present[0] = db[8] >> 7;
3338 connector->latency_present[1] = (db[8] >> 6) & 1;
3341 connector->video_latency[0] = db[9];
3343 connector->audio_latency[0] = db[10];
3345 connector->video_latency[1] = db[11];
3347 connector->audio_latency[1] = db[12];
3349 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3350 "video latency %d %d, "
3351 "audio latency %d %d\n",
3352 connector->latency_present[0],
3353 connector->latency_present[1],
3354 connector->video_latency[0],
3355 connector->video_latency[1],
3356 connector->audio_latency[0],
3357 connector->audio_latency[1]);
3361 monitor_name(struct detailed_timing *t, void *data)
3363 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3364 *(u8 **)data = t->data.other_data.data.str.str;
3367 static int get_monitor_name(struct edid *edid, char name[13])
3369 char *edid_name = NULL;
3375 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3376 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3377 if (edid_name[mnl] == 0x0a)
3380 name[mnl] = edid_name[mnl];
3387 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3388 * @edid: monitor EDID information
3389 * @name: pointer to a character array to hold the name of the monitor
3390 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3393 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3401 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3402 memcpy(name, buf, name_length);
3403 name[name_length] = '\0';
3405 EXPORT_SYMBOL(drm_edid_get_monitor_name);
3408 * drm_edid_to_eld - build ELD from EDID
3409 * @connector: connector corresponding to the HDMI/DP sink
3410 * @edid: EDID to parse
3412 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3413 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3416 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3418 uint8_t *eld = connector->eld;
3421 int total_sad_count = 0;
3425 memset(eld, 0, sizeof(connector->eld));
3427 connector->latency_present[0] = false;
3428 connector->latency_present[1] = false;
3429 connector->video_latency[0] = 0;
3430 connector->audio_latency[0] = 0;
3431 connector->video_latency[1] = 0;
3432 connector->audio_latency[1] = 0;
3434 cea = drm_find_cea_extension(edid);
3436 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3440 mnl = get_monitor_name(edid, eld + 20);
3442 eld[4] = (cea[1] << 5) | mnl;
3443 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3445 eld[0] = 2 << 3; /* ELD version: 2 */
3447 eld[16] = edid->mfg_id[0];
3448 eld[17] = edid->mfg_id[1];
3449 eld[18] = edid->prod_code[0];
3450 eld[19] = edid->prod_code[1];
3452 if (cea_revision(cea) >= 3) {
3455 if (cea_db_offsets(cea, &start, &end)) {
3460 for_each_cea_db(cea, i, start, end) {
3462 dbl = cea_db_payload_len(db);
3464 switch (cea_db_tag(db)) {
3468 /* Audio Data Block, contains SADs */
3469 sad_count = min(dbl / 3, 15 - total_sad_count);
3471 memcpy(eld + 20 + mnl + total_sad_count * 3,
3472 &db[1], sad_count * 3);
3473 total_sad_count += sad_count;
3476 /* Speaker Allocation Data Block */
3481 /* HDMI Vendor-Specific Data Block */
3482 if (cea_db_is_hdmi_vsdb(db))
3483 drm_parse_hdmi_vsdb_audio(connector, db);
3490 eld[5] |= total_sad_count << 4;
3492 eld[DRM_ELD_BASELINE_ELD_LEN] =
3493 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3495 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3496 drm_eld_size(eld), total_sad_count);
3498 EXPORT_SYMBOL(drm_edid_to_eld);
3501 * drm_edid_to_sad - extracts SADs from EDID
3502 * @edid: EDID to parse
3503 * @sads: pointer that will be set to the extracted SADs
3505 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3507 * Note: The returned pointer needs to be freed using kfree().
3509 * Return: The number of found SADs or negative number on error.
3511 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3514 int i, start, end, dbl;
3517 cea = drm_find_cea_extension(edid);
3519 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3523 if (cea_revision(cea) < 3) {
3524 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3528 if (cea_db_offsets(cea, &start, &end)) {
3529 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3533 for_each_cea_db(cea, i, start, end) {
3536 if (cea_db_tag(db) == AUDIO_BLOCK) {
3538 dbl = cea_db_payload_len(db);
3540 count = dbl / 3; /* SAD is 3B */
3541 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3544 for (j = 0; j < count; j++) {
3545 u8 *sad = &db[1 + j * 3];
3547 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3548 (*sads)[j].channels = sad[0] & 0x7;
3549 (*sads)[j].freq = sad[1] & 0x7F;
3550 (*sads)[j].byte2 = sad[2];
3558 EXPORT_SYMBOL(drm_edid_to_sad);
3561 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3562 * @edid: EDID to parse
3563 * @sadb: pointer to the speaker block
3565 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
3567 * Note: The returned pointer needs to be freed using kfree().
3569 * Return: The number of found Speaker Allocation Blocks or negative number on
3572 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3575 int i, start, end, dbl;
3578 cea = drm_find_cea_extension(edid);
3580 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3584 if (cea_revision(cea) < 3) {
3585 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3589 if (cea_db_offsets(cea, &start, &end)) {
3590 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3594 for_each_cea_db(cea, i, start, end) {
3595 const u8 *db = &cea[i];
3597 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3598 dbl = cea_db_payload_len(db);
3600 /* Speaker Allocation Data Block */
3602 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
3613 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3616 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
3617 * @connector: connector associated with the HDMI/DP sink
3618 * @mode: the display mode
3620 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3621 * the sink doesn't support audio or video.
3623 int drm_av_sync_delay(struct drm_connector *connector,
3624 const struct drm_display_mode *mode)
3626 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3629 if (!connector->latency_present[0])
3631 if (!connector->latency_present[1])
3634 a = connector->audio_latency[i];
3635 v = connector->video_latency[i];
3638 * HDMI/DP sink doesn't support audio or video?
3640 if (a == 255 || v == 255)
3644 * Convert raw EDID values to millisecond.
3645 * Treat unknown latency as 0ms.
3648 a = min(2 * (a - 1), 500);
3650 v = min(2 * (v - 1), 500);
3652 return max(v - a, 0);
3654 EXPORT_SYMBOL(drm_av_sync_delay);
3657 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
3658 * @edid: monitor EDID information
3660 * Parse the CEA extension according to CEA-861-B.
3662 * Return: True if the monitor is HDMI, false if not or unknown.
3664 bool drm_detect_hdmi_monitor(struct edid *edid)
3668 int start_offset, end_offset;
3670 edid_ext = drm_find_cea_extension(edid);
3674 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3678 * Because HDMI identifier is in Vendor Specific Block,
3679 * search it from all data blocks of CEA extension.
3681 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3682 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3688 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3691 * drm_detect_monitor_audio - check monitor audio capability
3692 * @edid: EDID block to scan
3694 * Monitor should have CEA extension block.
3695 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3696 * audio' only. If there is any audio extension block and supported
3697 * audio format, assume at least 'basic audio' support, even if 'basic
3698 * audio' is not defined in EDID.
3700 * Return: True if the monitor supports audio, false otherwise.
3702 bool drm_detect_monitor_audio(struct edid *edid)
3706 bool has_audio = false;
3707 int start_offset, end_offset;
3709 edid_ext = drm_find_cea_extension(edid);
3713 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
3716 DRM_DEBUG_KMS("Monitor has basic audio support\n");
3720 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3723 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3724 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
3726 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
3727 DRM_DEBUG_KMS("CEA audio format %d\n",
3728 (edid_ext[i + j] >> 3) & 0xf);
3735 EXPORT_SYMBOL(drm_detect_monitor_audio);
3738 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
3739 * @edid: EDID block to scan
3741 * Check whether the monitor reports the RGB quantization range selection
3742 * as supported. The AVI infoframe can then be used to inform the monitor
3743 * which quantization range (full or limited) is used.
3745 * Return: True if the RGB quantization range is selectable, false otherwise.
3747 bool drm_rgb_quant_range_selectable(struct edid *edid)
3752 edid_ext = drm_find_cea_extension(edid);
3756 if (cea_db_offsets(edid_ext, &start, &end))
3759 for_each_cea_db(edid_ext, i, start, end) {
3760 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
3761 cea_db_payload_len(&edid_ext[i]) == 2) {
3762 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
3763 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
3769 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
3771 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
3774 struct drm_display_info *info = &connector->display_info;
3775 unsigned int dc_bpc = 0;
3777 /* HDMI supports at least 8 bpc */
3780 if (cea_db_payload_len(hdmi) < 6)
3783 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
3785 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
3786 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
3790 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
3792 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
3793 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
3797 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
3799 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
3800 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
3805 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
3810 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
3811 connector->name, dc_bpc);
3815 * Deep color support mandates RGB444 support for all video
3816 * modes and forbids YCRCB422 support for all video modes per
3819 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3821 /* YCRCB444 is optional according to spec. */
3822 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
3823 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3824 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
3829 * Spec says that if any deep color mode is supported at all,
3830 * then deep color 36 bit must be supported.
3832 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
3833 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
3839 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
3841 struct drm_display_info *info = &connector->display_info;
3842 u8 len = cea_db_payload_len(db);
3845 info->dvi_dual = db[6] & 1;
3847 info->max_tmds_clock = db[7] * 5000;
3849 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
3850 "max TMDS clock %d kHz\n",
3852 info->max_tmds_clock);
3854 drm_parse_hdmi_deep_color_info(connector, db);
3857 static void drm_parse_cea_ext(struct drm_connector *connector,
3860 struct drm_display_info *info = &connector->display_info;
3864 edid_ext = drm_find_cea_extension(edid);
3868 info->cea_rev = edid_ext[1];
3870 /* The existence of a CEA block should imply RGB support */
3871 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3872 if (edid_ext[3] & EDID_CEA_YCRCB444)
3873 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3874 if (edid_ext[3] & EDID_CEA_YCRCB422)
3875 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3877 if (cea_db_offsets(edid_ext, &start, &end))
3880 for_each_cea_db(edid_ext, i, start, end) {
3881 const u8 *db = &edid_ext[i];
3883 if (cea_db_is_hdmi_vsdb(db))
3884 drm_parse_hdmi_vsdb_video(connector, db);
3888 static void drm_add_display_info(struct drm_connector *connector,
3891 struct drm_display_info *info = &connector->display_info;
3893 info->width_mm = edid->width_cm * 10;
3894 info->height_mm = edid->height_cm * 10;
3896 /* driver figures it out in this case */
3898 info->color_formats = 0;
3900 info->max_tmds_clock = 0;
3901 info->dvi_dual = false;
3903 if (edid->revision < 3)
3906 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
3909 drm_parse_cea_ext(connector, edid);
3912 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
3914 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
3915 * tells us to assume 8 bpc color depth if the EDID doesn't have
3916 * extensions which tell otherwise.
3918 if ((info->bpc == 0) && (edid->revision < 4) &&
3919 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
3921 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
3922 connector->name, info->bpc);
3925 /* Only defined for 1.4 with digital displays */
3926 if (edid->revision < 4)
3929 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
3930 case DRM_EDID_DIGITAL_DEPTH_6:
3933 case DRM_EDID_DIGITAL_DEPTH_8:
3936 case DRM_EDID_DIGITAL_DEPTH_10:
3939 case DRM_EDID_DIGITAL_DEPTH_12:
3942 case DRM_EDID_DIGITAL_DEPTH_14:
3945 case DRM_EDID_DIGITAL_DEPTH_16:
3948 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
3954 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
3955 connector->name, info->bpc);
3957 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
3958 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
3959 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3960 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
3961 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3964 static int validate_displayid(u8 *displayid, int length, int idx)
3968 struct displayid_hdr *base;
3970 base = (struct displayid_hdr *)&displayid[idx];
3972 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
3973 base->rev, base->bytes, base->prod_id, base->ext_count);
3975 if (base->bytes + 5 > length - idx)
3977 for (i = idx; i <= base->bytes + 5; i++) {
3978 csum += displayid[i];
3981 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum);
3987 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
3988 struct displayid_detailed_timings_1 *timings)
3990 struct drm_display_mode *mode;
3991 unsigned pixel_clock = (timings->pixel_clock[0] |
3992 (timings->pixel_clock[1] << 8) |
3993 (timings->pixel_clock[2] << 16));
3994 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
3995 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
3996 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
3997 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
3998 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
3999 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4000 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4001 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4002 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4003 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4004 mode = drm_mode_create(dev);
4008 mode->clock = pixel_clock * 10;
4009 mode->hdisplay = hactive;
4010 mode->hsync_start = mode->hdisplay + hsync;
4011 mode->hsync_end = mode->hsync_start + hsync_width;
4012 mode->htotal = mode->hdisplay + hblank;
4014 mode->vdisplay = vactive;
4015 mode->vsync_start = mode->vdisplay + vsync;
4016 mode->vsync_end = mode->vsync_start + vsync_width;
4017 mode->vtotal = mode->vdisplay + vblank;
4020 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4021 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4022 mode->type = DRM_MODE_TYPE_DRIVER;
4024 if (timings->flags & 0x80)
4025 mode->type |= DRM_MODE_TYPE_PREFERRED;
4026 mode->vrefresh = drm_mode_vrefresh(mode);
4027 drm_mode_set_name(mode);
4032 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4033 struct displayid_block *block)
4035 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4038 struct drm_display_mode *newmode;
4040 /* blocks must be multiple of 20 bytes length */
4041 if (block->num_bytes % 20)
4044 num_timings = block->num_bytes / 20;
4045 for (i = 0; i < num_timings; i++) {
4046 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4048 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4052 drm_mode_probed_add(connector, newmode);
4058 static int add_displayid_detailed_modes(struct drm_connector *connector,
4064 int length = EDID_LENGTH;
4065 struct displayid_block *block;
4068 displayid = drm_find_displayid_extension(edid);
4072 ret = validate_displayid(displayid, length, idx);
4076 idx += sizeof(struct displayid_hdr);
4077 while (block = (struct displayid_block *)&displayid[idx],
4078 idx + sizeof(struct displayid_block) <= length &&
4079 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4080 block->num_bytes > 0) {
4081 idx += block->num_bytes + sizeof(struct displayid_block);
4082 switch (block->tag) {
4083 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4084 num_modes += add_displayid_detailed_1_modes(connector, block);
4092 * drm_add_edid_modes - add modes from EDID data, if available
4093 * @connector: connector we're probing
4096 * Add the specified modes to the connector's mode list. Also fills out the
4097 * &drm_display_info structure in @connector with any information which can be
4098 * derived from the edid.
4100 * Return: The number of modes added or 0 if we couldn't find any.
4102 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4110 if (!drm_edid_is_valid(edid)) {
4111 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4116 quirks = edid_get_quirks(edid);
4119 * EDID spec says modes should be preferred in this order:
4120 * - preferred detailed mode
4121 * - other detailed modes from base block
4122 * - detailed modes from extension blocks
4123 * - CVT 3-byte code modes
4124 * - standard timing codes
4125 * - established timing codes
4126 * - modes inferred from GTF or CVT range information
4128 * We get this pretty much right.
4130 * XXX order for additional mode types in extension blocks?
4132 num_modes += add_detailed_modes(connector, edid, quirks);
4133 num_modes += add_cvt_modes(connector, edid);
4134 num_modes += add_standard_modes(connector, edid);
4135 num_modes += add_established_modes(connector, edid);
4136 num_modes += add_cea_modes(connector, edid);
4137 num_modes += add_alternate_cea_modes(connector, edid);
4138 num_modes += add_displayid_detailed_modes(connector, edid);
4139 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4140 num_modes += add_inferred_modes(connector, edid);
4142 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4143 edid_fixup_preferred(connector, quirks);
4145 drm_add_display_info(connector, edid);
4147 if (quirks & EDID_QUIRK_FORCE_6BPC)
4148 connector->display_info.bpc = 6;
4150 if (quirks & EDID_QUIRK_FORCE_8BPC)
4151 connector->display_info.bpc = 8;
4153 if (quirks & EDID_QUIRK_FORCE_12BPC)
4154 connector->display_info.bpc = 12;
4158 EXPORT_SYMBOL(drm_add_edid_modes);
4161 * drm_add_modes_noedid - add modes for the connectors without EDID
4162 * @connector: connector we're probing
4163 * @hdisplay: the horizontal display limit
4164 * @vdisplay: the vertical display limit
4166 * Add the specified modes to the connector's mode list. Only when the
4167 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4169 * Return: The number of modes added or 0 if we couldn't find any.
4171 int drm_add_modes_noedid(struct drm_connector *connector,
4172 int hdisplay, int vdisplay)
4174 int i, count, num_modes = 0;
4175 struct drm_display_mode *mode;
4176 struct drm_device *dev = connector->dev;
4178 count = ARRAY_SIZE(drm_dmt_modes);
4184 for (i = 0; i < count; i++) {
4185 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4186 if (hdisplay && vdisplay) {
4188 * Only when two are valid, they will be used to check
4189 * whether the mode should be added to the mode list of
4192 if (ptr->hdisplay > hdisplay ||
4193 ptr->vdisplay > vdisplay)
4196 if (drm_mode_vrefresh(ptr) > 61)
4198 mode = drm_mode_duplicate(dev, ptr);
4200 drm_mode_probed_add(connector, mode);
4206 EXPORT_SYMBOL(drm_add_modes_noedid);
4209 * drm_set_preferred_mode - Sets the preferred mode of a connector
4210 * @connector: connector whose mode list should be processed
4211 * @hpref: horizontal resolution of preferred mode
4212 * @vpref: vertical resolution of preferred mode
4214 * Marks a mode as preferred if it matches the resolution specified by @hpref
4217 void drm_set_preferred_mode(struct drm_connector *connector,
4218 int hpref, int vpref)
4220 struct drm_display_mode *mode;
4222 list_for_each_entry(mode, &connector->probed_modes, head) {
4223 if (mode->hdisplay == hpref &&
4224 mode->vdisplay == vpref)
4225 mode->type |= DRM_MODE_TYPE_PREFERRED;
4228 EXPORT_SYMBOL(drm_set_preferred_mode);
4231 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4232 * data from a DRM display mode
4233 * @frame: HDMI AVI infoframe
4234 * @mode: DRM display mode
4236 * Return: 0 on success or a negative error code on failure.
4239 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4240 const struct drm_display_mode *mode)
4244 if (!frame || !mode)
4247 err = hdmi_avi_infoframe_init(frame);
4251 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4252 frame->pixel_repeat = 1;
4254 frame->video_code = drm_match_cea_mode(mode);
4256 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4259 * Populate picture aspect ratio from either
4260 * user input (if specified) or from the CEA mode list.
4262 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4263 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4264 frame->picture_aspect = mode->picture_aspect_ratio;
4265 else if (frame->video_code > 0)
4266 frame->picture_aspect = drm_get_cea_aspect_ratio(
4269 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4270 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4274 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4276 static enum hdmi_3d_structure
4277 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4279 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4282 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4283 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4284 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4285 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4286 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4287 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4288 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4289 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4290 case DRM_MODE_FLAG_3D_L_DEPTH:
4291 return HDMI_3D_STRUCTURE_L_DEPTH;
4292 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4293 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4294 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4295 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4296 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4297 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4299 return HDMI_3D_STRUCTURE_INVALID;
4304 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4305 * data from a DRM display mode
4306 * @frame: HDMI vendor infoframe
4307 * @mode: DRM display mode
4309 * Note that there's is a need to send HDMI vendor infoframes only when using a
4310 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4311 * function will return -EINVAL, error that can be safely ignored.
4313 * Return: 0 on success or a negative error code on failure.
4316 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4317 const struct drm_display_mode *mode)
4323 if (!frame || !mode)
4326 vic = drm_match_hdmi_mode(mode);
4327 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4329 if (!vic && !s3d_flags)
4332 if (vic && s3d_flags)
4335 err = hdmi_vendor_infoframe_init(frame);
4342 frame->s3d_struct = s3d_structure_from_display_mode(mode);
4346 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
4348 static int drm_parse_tiled_block(struct drm_connector *connector,
4349 struct displayid_block *block)
4351 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4353 u8 tile_v_loc, tile_h_loc;
4354 u8 num_v_tile, num_h_tile;
4355 struct drm_tile_group *tg;
4357 w = tile->tile_size[0] | tile->tile_size[1] << 8;
4358 h = tile->tile_size[2] | tile->tile_size[3] << 8;
4360 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4361 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
4362 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
4363 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
4365 connector->has_tile = true;
4366 if (tile->tile_cap & 0x80)
4367 connector->tile_is_single_monitor = true;
4369 connector->num_h_tile = num_h_tile + 1;
4370 connector->num_v_tile = num_v_tile + 1;
4371 connector->tile_h_loc = tile_h_loc;
4372 connector->tile_v_loc = tile_v_loc;
4373 connector->tile_h_size = w + 1;
4374 connector->tile_v_size = h + 1;
4376 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
4377 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
4378 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
4379 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
4380 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
4382 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
4384 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
4389 if (connector->tile_group != tg) {
4390 /* if we haven't got a pointer,
4391 take the reference, drop ref to old tile group */
4392 if (connector->tile_group) {
4393 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4395 connector->tile_group = tg;
4397 /* if same tile group, then release the ref we just took. */
4398 drm_mode_put_tile_group(connector->dev, tg);
4402 static int drm_parse_display_id(struct drm_connector *connector,
4403 u8 *displayid, int length,
4404 bool is_edid_extension)
4406 /* if this is an EDID extension the first byte will be 0x70 */
4408 struct displayid_block *block;
4411 if (is_edid_extension)
4414 ret = validate_displayid(displayid, length, idx);
4418 idx += sizeof(struct displayid_hdr);
4419 while (block = (struct displayid_block *)&displayid[idx],
4420 idx + sizeof(struct displayid_block) <= length &&
4421 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4422 block->num_bytes > 0) {
4423 idx += block->num_bytes + sizeof(struct displayid_block);
4424 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
4425 block->tag, block->rev, block->num_bytes);
4427 switch (block->tag) {
4428 case DATA_BLOCK_TILED_DISPLAY:
4429 ret = drm_parse_tiled_block(connector, block);
4433 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4434 /* handled in mode gathering code. */
4437 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
4444 static void drm_get_displayid(struct drm_connector *connector,
4447 void *displayid = NULL;
4449 connector->has_tile = false;
4450 displayid = drm_find_displayid_extension(edid);
4452 /* drop reference to any tile group we had */
4456 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
4459 if (!connector->has_tile)
4463 if (connector->tile_group) {
4464 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4465 connector->tile_group = NULL;
projects / linux-2.6-block.git / blob