2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
35 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_displayid.h>
40 #include <drm/drm_scdc_helper.h>
42 #include "drm_crtc_internal.h"
44 #define version_greater(edid, maj, min) \
45 (((edid)->version > (maj)) || \
46 ((edid)->version == (maj) && (edid)->revision > (min)))
48 #define EDID_EST_TIMINGS 16
49 #define EDID_STD_TIMINGS 8
50 #define EDID_DETAILED_TIMINGS 4
53 * EDID blocks out in the wild have a variety of bugs, try to collect
54 * them here (note that userspace may work around broken monitors first,
55 * but fixes should make their way here so that the kernel "just works"
56 * on as many displays as possible).
59 /* First detailed mode wrong, use largest 60Hz mode */
60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
61 /* Reported 135MHz pixel clock is too high, needs adjustment */
62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
63 /* Prefer the largest mode at 75 Hz */
64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
65 /* Detail timing is in cm not mm */
66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
67 /* Detailed timing descriptors have bogus size values, so just take the
68 * maximum size and use that.
70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
71 /* Monitor forgot to set the first detailed is preferred bit. */
72 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
73 /* use +hsync +vsync for detailed mode */
74 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
75 /* Force reduced-blanking timings for detailed modes */
76 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
78 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
80 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
82 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
84 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
85 /* Non desktop display (i.e. HMD) */
86 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
88 struct detailed_mode_closure {
89 struct drm_connector *connector;
101 static const struct edid_quirk {
105 } edid_quirk_list[] = {
107 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
109 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
111 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
116 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
117 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
119 /* Belinea 10 15 55 */
120 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
121 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
123 /* Envision Peripherals, Inc. EN-7100e */
124 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
125 /* Envision EN2028 */
126 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
128 /* Funai Electronics PM36B */
129 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
130 EDID_QUIRK_DETAILED_IN_CM },
132 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
133 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
135 /* LG Philips LCD LP154W01-A5 */
136 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
137 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
139 /* Philips 107p5 CRT */
140 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
143 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
145 /* Samsung SyncMaster 205BW. Note: irony */
146 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
147 /* Samsung SyncMaster 22[5-6]BW */
148 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
149 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
151 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
152 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
154 /* ViewSonic VA2026w */
155 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
157 /* Medion MD 30217 PG */
158 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
160 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
161 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
163 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
164 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
166 /* HTC Vive VR Headset */
167 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
169 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */
170 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
171 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
172 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
174 /* Windows Mixed Reality Headsets */
175 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
176 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
177 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
178 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
179 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
180 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
181 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
182 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
184 /* Sony PlayStation VR Headset */
185 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
189 * Autogenerated from the DMT spec.
190 * This table is copied from xfree86/modes/xf86EdidModes.c.
192 static const struct drm_display_mode drm_dmt_modes[] = {
193 /* 0x01 - 640x350@85Hz */
194 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
195 736, 832, 0, 350, 382, 385, 445, 0,
196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
197 /* 0x02 - 640x400@85Hz */
198 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
199 736, 832, 0, 400, 401, 404, 445, 0,
200 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
201 /* 0x03 - 720x400@85Hz */
202 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
203 828, 936, 0, 400, 401, 404, 446, 0,
204 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
205 /* 0x04 - 640x480@60Hz */
206 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
207 752, 800, 0, 480, 490, 492, 525, 0,
208 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
209 /* 0x05 - 640x480@72Hz */
210 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
211 704, 832, 0, 480, 489, 492, 520, 0,
212 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
213 /* 0x06 - 640x480@75Hz */
214 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
215 720, 840, 0, 480, 481, 484, 500, 0,
216 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
217 /* 0x07 - 640x480@85Hz */
218 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
219 752, 832, 0, 480, 481, 484, 509, 0,
220 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
221 /* 0x08 - 800x600@56Hz */
222 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
223 896, 1024, 0, 600, 601, 603, 625, 0,
224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
225 /* 0x09 - 800x600@60Hz */
226 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
227 968, 1056, 0, 600, 601, 605, 628, 0,
228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
229 /* 0x0a - 800x600@72Hz */
230 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
231 976, 1040, 0, 600, 637, 643, 666, 0,
232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
233 /* 0x0b - 800x600@75Hz */
234 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
235 896, 1056, 0, 600, 601, 604, 625, 0,
236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
237 /* 0x0c - 800x600@85Hz */
238 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
239 896, 1048, 0, 600, 601, 604, 631, 0,
240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
241 /* 0x0d - 800x600@120Hz RB */
242 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
243 880, 960, 0, 600, 603, 607, 636, 0,
244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
245 /* 0x0e - 848x480@60Hz */
246 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
247 976, 1088, 0, 480, 486, 494, 517, 0,
248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
249 /* 0x0f - 1024x768@43Hz, interlace */
250 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
251 1208, 1264, 0, 768, 768, 776, 817, 0,
252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
253 DRM_MODE_FLAG_INTERLACE) },
254 /* 0x10 - 1024x768@60Hz */
255 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
256 1184, 1344, 0, 768, 771, 777, 806, 0,
257 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
258 /* 0x11 - 1024x768@70Hz */
259 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
260 1184, 1328, 0, 768, 771, 777, 806, 0,
261 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
262 /* 0x12 - 1024x768@75Hz */
263 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
264 1136, 1312, 0, 768, 769, 772, 800, 0,
265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
266 /* 0x13 - 1024x768@85Hz */
267 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
268 1168, 1376, 0, 768, 769, 772, 808, 0,
269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
270 /* 0x14 - 1024x768@120Hz RB */
271 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
272 1104, 1184, 0, 768, 771, 775, 813, 0,
273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
274 /* 0x15 - 1152x864@75Hz */
275 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
276 1344, 1600, 0, 864, 865, 868, 900, 0,
277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
278 /* 0x55 - 1280x720@60Hz */
279 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
280 1430, 1650, 0, 720, 725, 730, 750, 0,
281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
282 /* 0x16 - 1280x768@60Hz RB */
283 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
284 1360, 1440, 0, 768, 771, 778, 790, 0,
285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
286 /* 0x17 - 1280x768@60Hz */
287 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
288 1472, 1664, 0, 768, 771, 778, 798, 0,
289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
290 /* 0x18 - 1280x768@75Hz */
291 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
292 1488, 1696, 0, 768, 771, 778, 805, 0,
293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
294 /* 0x19 - 1280x768@85Hz */
295 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
296 1496, 1712, 0, 768, 771, 778, 809, 0,
297 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
298 /* 0x1a - 1280x768@120Hz RB */
299 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
300 1360, 1440, 0, 768, 771, 778, 813, 0,
301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
302 /* 0x1b - 1280x800@60Hz RB */
303 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
304 1360, 1440, 0, 800, 803, 809, 823, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
306 /* 0x1c - 1280x800@60Hz */
307 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
308 1480, 1680, 0, 800, 803, 809, 831, 0,
309 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
310 /* 0x1d - 1280x800@75Hz */
311 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
312 1488, 1696, 0, 800, 803, 809, 838, 0,
313 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
314 /* 0x1e - 1280x800@85Hz */
315 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
316 1496, 1712, 0, 800, 803, 809, 843, 0,
317 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
318 /* 0x1f - 1280x800@120Hz RB */
319 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
320 1360, 1440, 0, 800, 803, 809, 847, 0,
321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
322 /* 0x20 - 1280x960@60Hz */
323 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
324 1488, 1800, 0, 960, 961, 964, 1000, 0,
325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
326 /* 0x21 - 1280x960@85Hz */
327 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
328 1504, 1728, 0, 960, 961, 964, 1011, 0,
329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
330 /* 0x22 - 1280x960@120Hz RB */
331 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
332 1360, 1440, 0, 960, 963, 967, 1017, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
334 /* 0x23 - 1280x1024@60Hz */
335 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
336 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
338 /* 0x24 - 1280x1024@75Hz */
339 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
340 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 0x25 - 1280x1024@85Hz */
343 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
344 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
346 /* 0x26 - 1280x1024@120Hz RB */
347 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
348 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
350 /* 0x27 - 1360x768@60Hz */
351 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
352 1536, 1792, 0, 768, 771, 777, 795, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
354 /* 0x28 - 1360x768@120Hz RB */
355 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
356 1440, 1520, 0, 768, 771, 776, 813, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
358 /* 0x51 - 1366x768@60Hz */
359 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
360 1579, 1792, 0, 768, 771, 774, 798, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
362 /* 0x56 - 1366x768@60Hz */
363 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
364 1436, 1500, 0, 768, 769, 772, 800, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
366 /* 0x29 - 1400x1050@60Hz RB */
367 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
368 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
370 /* 0x2a - 1400x1050@60Hz */
371 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
372 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
373 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
374 /* 0x2b - 1400x1050@75Hz */
375 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
376 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
377 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 0x2c - 1400x1050@85Hz */
379 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
380 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
381 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
382 /* 0x2d - 1400x1050@120Hz RB */
383 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
384 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
386 /* 0x2e - 1440x900@60Hz RB */
387 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
388 1520, 1600, 0, 900, 903, 909, 926, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
390 /* 0x2f - 1440x900@60Hz */
391 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
392 1672, 1904, 0, 900, 903, 909, 934, 0,
393 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x30 - 1440x900@75Hz */
395 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
396 1688, 1936, 0, 900, 903, 909, 942, 0,
397 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
398 /* 0x31 - 1440x900@85Hz */
399 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
400 1696, 1952, 0, 900, 903, 909, 948, 0,
401 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
402 /* 0x32 - 1440x900@120Hz RB */
403 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
404 1520, 1600, 0, 900, 903, 909, 953, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
406 /* 0x53 - 1600x900@60Hz */
407 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
408 1704, 1800, 0, 900, 901, 904, 1000, 0,
409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
410 /* 0x33 - 1600x1200@60Hz */
411 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
412 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 0x34 - 1600x1200@65Hz */
415 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
416 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
418 /* 0x35 - 1600x1200@70Hz */
419 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
420 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
422 /* 0x36 - 1600x1200@75Hz */
423 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
424 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 0x37 - 1600x1200@85Hz */
427 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
428 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
430 /* 0x38 - 1600x1200@120Hz RB */
431 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
432 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
434 /* 0x39 - 1680x1050@60Hz RB */
435 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
436 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
438 /* 0x3a - 1680x1050@60Hz */
439 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
440 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 0x3b - 1680x1050@75Hz */
443 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
444 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
446 /* 0x3c - 1680x1050@85Hz */
447 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
448 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
449 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
450 /* 0x3d - 1680x1050@120Hz RB */
451 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
452 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
454 /* 0x3e - 1792x1344@60Hz */
455 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
456 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
457 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 0x3f - 1792x1344@75Hz */
459 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
460 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
461 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 0x40 - 1792x1344@120Hz RB */
463 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
464 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
466 /* 0x41 - 1856x1392@60Hz */
467 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
468 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
469 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
470 /* 0x42 - 1856x1392@75Hz */
471 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
472 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 0x43 - 1856x1392@120Hz RB */
475 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
476 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
478 /* 0x52 - 1920x1080@60Hz */
479 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
480 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
482 /* 0x44 - 1920x1200@60Hz RB */
483 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
484 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
486 /* 0x45 - 1920x1200@60Hz */
487 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
488 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
490 /* 0x46 - 1920x1200@75Hz */
491 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
492 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
494 /* 0x47 - 1920x1200@85Hz */
495 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
496 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
498 /* 0x48 - 1920x1200@120Hz RB */
499 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
500 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
502 /* 0x49 - 1920x1440@60Hz */
503 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
504 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
506 /* 0x4a - 1920x1440@75Hz */
507 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
508 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
510 /* 0x4b - 1920x1440@120Hz RB */
511 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
512 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
514 /* 0x54 - 2048x1152@60Hz */
515 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
516 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
518 /* 0x4c - 2560x1600@60Hz RB */
519 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
520 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
522 /* 0x4d - 2560x1600@60Hz */
523 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
524 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
526 /* 0x4e - 2560x1600@75Hz */
527 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
528 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
530 /* 0x4f - 2560x1600@85Hz */
531 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
532 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
534 /* 0x50 - 2560x1600@120Hz RB */
535 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
536 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
538 /* 0x57 - 4096x2160@60Hz RB */
539 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
540 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
542 /* 0x58 - 4096x2160@59.94Hz RB */
543 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
544 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
549 * These more or less come from the DMT spec. The 720x400 modes are
550 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
551 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
552 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
555 * The DMT modes have been fact-checked; the rest are mild guesses.
557 static const struct drm_display_mode edid_est_modes[] = {
558 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
559 968, 1056, 0, 600, 601, 605, 628, 0,
560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
561 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
562 896, 1024, 0, 600, 601, 603, 625, 0,
563 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
564 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
565 720, 840, 0, 480, 481, 484, 500, 0,
566 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
567 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
568 704, 832, 0, 480, 489, 492, 520, 0,
569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
570 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
571 768, 864, 0, 480, 483, 486, 525, 0,
572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
573 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
574 752, 800, 0, 480, 490, 492, 525, 0,
575 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
576 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
577 846, 900, 0, 400, 421, 423, 449, 0,
578 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
579 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
580 846, 900, 0, 400, 412, 414, 449, 0,
581 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
582 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
583 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
585 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
586 1136, 1312, 0, 768, 769, 772, 800, 0,
587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
588 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
589 1184, 1328, 0, 768, 771, 777, 806, 0,
590 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
591 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
592 1184, 1344, 0, 768, 771, 777, 806, 0,
593 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
594 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
595 1208, 1264, 0, 768, 768, 776, 817, 0,
596 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
597 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
598 928, 1152, 0, 624, 625, 628, 667, 0,
599 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
600 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
601 896, 1056, 0, 600, 601, 604, 625, 0,
602 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
603 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
604 976, 1040, 0, 600, 637, 643, 666, 0,
605 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
606 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
607 1344, 1600, 0, 864, 865, 868, 900, 0,
608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
618 static const struct minimode est3_modes[] = {
626 { 1024, 768, 85, 0 },
627 { 1152, 864, 75, 0 },
629 { 1280, 768, 60, 1 },
630 { 1280, 768, 60, 0 },
631 { 1280, 768, 75, 0 },
632 { 1280, 768, 85, 0 },
633 { 1280, 960, 60, 0 },
634 { 1280, 960, 85, 0 },
635 { 1280, 1024, 60, 0 },
636 { 1280, 1024, 85, 0 },
638 { 1360, 768, 60, 0 },
639 { 1440, 900, 60, 1 },
640 { 1440, 900, 60, 0 },
641 { 1440, 900, 75, 0 },
642 { 1440, 900, 85, 0 },
643 { 1400, 1050, 60, 1 },
644 { 1400, 1050, 60, 0 },
645 { 1400, 1050, 75, 0 },
647 { 1400, 1050, 85, 0 },
648 { 1680, 1050, 60, 1 },
649 { 1680, 1050, 60, 0 },
650 { 1680, 1050, 75, 0 },
651 { 1680, 1050, 85, 0 },
652 { 1600, 1200, 60, 0 },
653 { 1600, 1200, 65, 0 },
654 { 1600, 1200, 70, 0 },
656 { 1600, 1200, 75, 0 },
657 { 1600, 1200, 85, 0 },
658 { 1792, 1344, 60, 0 },
659 { 1792, 1344, 75, 0 },
660 { 1856, 1392, 60, 0 },
661 { 1856, 1392, 75, 0 },
662 { 1920, 1200, 60, 1 },
663 { 1920, 1200, 60, 0 },
665 { 1920, 1200, 75, 0 },
666 { 1920, 1200, 85, 0 },
667 { 1920, 1440, 60, 0 },
668 { 1920, 1440, 75, 0 },
671 static const struct minimode extra_modes[] = {
672 { 1024, 576, 60, 0 },
673 { 1366, 768, 60, 0 },
674 { 1600, 900, 60, 0 },
675 { 1680, 945, 60, 0 },
676 { 1920, 1080, 60, 0 },
677 { 2048, 1152, 60, 0 },
678 { 2048, 1536, 60, 0 },
682 * Probably taken from CEA-861 spec.
683 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
685 * Index using the VIC.
687 static const struct drm_display_mode edid_cea_modes[] = {
688 /* 0 - dummy, VICs start at 1 */
690 /* 1 - 640x480@60Hz */
691 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
692 752, 800, 0, 480, 490, 492, 525, 0,
693 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
694 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
695 /* 2 - 720x480@60Hz */
696 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
697 798, 858, 0, 480, 489, 495, 525, 0,
698 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
699 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
700 /* 3 - 720x480@60Hz */
701 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
702 798, 858, 0, 480, 489, 495, 525, 0,
703 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
704 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
705 /* 4 - 1280x720@60Hz */
706 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
707 1430, 1650, 0, 720, 725, 730, 750, 0,
708 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
709 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
710 /* 5 - 1920x1080i@60Hz */
711 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
712 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
713 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
714 DRM_MODE_FLAG_INTERLACE),
715 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
716 /* 6 - 720(1440)x480i@60Hz */
717 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
718 801, 858, 0, 480, 488, 494, 525, 0,
719 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
720 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
721 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
722 /* 7 - 720(1440)x480i@60Hz */
723 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
724 801, 858, 0, 480, 488, 494, 525, 0,
725 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
726 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
727 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
728 /* 8 - 720(1440)x240@60Hz */
729 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
730 801, 858, 0, 240, 244, 247, 262, 0,
731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
732 DRM_MODE_FLAG_DBLCLK),
733 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
734 /* 9 - 720(1440)x240@60Hz */
735 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
736 801, 858, 0, 240, 244, 247, 262, 0,
737 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
738 DRM_MODE_FLAG_DBLCLK),
739 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
740 /* 10 - 2880x480i@60Hz */
741 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
742 3204, 3432, 0, 480, 488, 494, 525, 0,
743 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
744 DRM_MODE_FLAG_INTERLACE),
745 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
746 /* 11 - 2880x480i@60Hz */
747 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
748 3204, 3432, 0, 480, 488, 494, 525, 0,
749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
750 DRM_MODE_FLAG_INTERLACE),
751 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
752 /* 12 - 2880x240@60Hz */
753 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
754 3204, 3432, 0, 240, 244, 247, 262, 0,
755 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
756 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
757 /* 13 - 2880x240@60Hz */
758 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
759 3204, 3432, 0, 240, 244, 247, 262, 0,
760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
761 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
762 /* 14 - 1440x480@60Hz */
763 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
764 1596, 1716, 0, 480, 489, 495, 525, 0,
765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
766 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
767 /* 15 - 1440x480@60Hz */
768 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
769 1596, 1716, 0, 480, 489, 495, 525, 0,
770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
771 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
772 /* 16 - 1920x1080@60Hz */
773 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
774 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
775 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
776 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
777 /* 17 - 720x576@50Hz */
778 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
779 796, 864, 0, 576, 581, 586, 625, 0,
780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
781 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
782 /* 18 - 720x576@50Hz */
783 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
784 796, 864, 0, 576, 581, 586, 625, 0,
785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
786 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
787 /* 19 - 1280x720@50Hz */
788 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
789 1760, 1980, 0, 720, 725, 730, 750, 0,
790 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
791 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
792 /* 20 - 1920x1080i@50Hz */
793 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
794 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
795 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
796 DRM_MODE_FLAG_INTERLACE),
797 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
798 /* 21 - 720(1440)x576i@50Hz */
799 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
800 795, 864, 0, 576, 580, 586, 625, 0,
801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
802 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
803 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
804 /* 22 - 720(1440)x576i@50Hz */
805 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
806 795, 864, 0, 576, 580, 586, 625, 0,
807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
808 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
809 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
810 /* 23 - 720(1440)x288@50Hz */
811 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
812 795, 864, 0, 288, 290, 293, 312, 0,
813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
814 DRM_MODE_FLAG_DBLCLK),
815 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
816 /* 24 - 720(1440)x288@50Hz */
817 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
818 795, 864, 0, 288, 290, 293, 312, 0,
819 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
820 DRM_MODE_FLAG_DBLCLK),
821 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
822 /* 25 - 2880x576i@50Hz */
823 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
824 3180, 3456, 0, 576, 580, 586, 625, 0,
825 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
826 DRM_MODE_FLAG_INTERLACE),
827 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
828 /* 26 - 2880x576i@50Hz */
829 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
830 3180, 3456, 0, 576, 580, 586, 625, 0,
831 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
832 DRM_MODE_FLAG_INTERLACE),
833 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
834 /* 27 - 2880x288@50Hz */
835 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
836 3180, 3456, 0, 288, 290, 293, 312, 0,
837 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
838 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
839 /* 28 - 2880x288@50Hz */
840 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
841 3180, 3456, 0, 288, 290, 293, 312, 0,
842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
843 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
844 /* 29 - 1440x576@50Hz */
845 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
846 1592, 1728, 0, 576, 581, 586, 625, 0,
847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
848 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
849 /* 30 - 1440x576@50Hz */
850 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
851 1592, 1728, 0, 576, 581, 586, 625, 0,
852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
853 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
854 /* 31 - 1920x1080@50Hz */
855 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
856 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
857 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
858 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
859 /* 32 - 1920x1080@24Hz */
860 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
861 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
862 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
863 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
864 /* 33 - 1920x1080@25Hz */
865 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
866 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
867 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
868 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
869 /* 34 - 1920x1080@30Hz */
870 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
871 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
872 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
873 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
874 /* 35 - 2880x480@60Hz */
875 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
876 3192, 3432, 0, 480, 489, 495, 525, 0,
877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
878 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
879 /* 36 - 2880x480@60Hz */
880 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
881 3192, 3432, 0, 480, 489, 495, 525, 0,
882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
883 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
884 /* 37 - 2880x576@50Hz */
885 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
886 3184, 3456, 0, 576, 581, 586, 625, 0,
887 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
888 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
889 /* 38 - 2880x576@50Hz */
890 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
891 3184, 3456, 0, 576, 581, 586, 625, 0,
892 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
893 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
894 /* 39 - 1920x1080i@50Hz */
895 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
896 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
898 DRM_MODE_FLAG_INTERLACE),
899 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
900 /* 40 - 1920x1080i@100Hz */
901 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
902 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
903 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
904 DRM_MODE_FLAG_INTERLACE),
905 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
906 /* 41 - 1280x720@100Hz */
907 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
908 1760, 1980, 0, 720, 725, 730, 750, 0,
909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
910 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
911 /* 42 - 720x576@100Hz */
912 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
913 796, 864, 0, 576, 581, 586, 625, 0,
914 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
915 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
916 /* 43 - 720x576@100Hz */
917 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
918 796, 864, 0, 576, 581, 586, 625, 0,
919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
920 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
921 /* 44 - 720(1440)x576i@100Hz */
922 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
923 795, 864, 0, 576, 580, 586, 625, 0,
924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
925 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
926 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
927 /* 45 - 720(1440)x576i@100Hz */
928 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
929 795, 864, 0, 576, 580, 586, 625, 0,
930 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
931 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
932 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
933 /* 46 - 1920x1080i@120Hz */
934 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
935 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
936 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
937 DRM_MODE_FLAG_INTERLACE),
938 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
939 /* 47 - 1280x720@120Hz */
940 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
941 1430, 1650, 0, 720, 725, 730, 750, 0,
942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
943 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
944 /* 48 - 720x480@120Hz */
945 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
946 798, 858, 0, 480, 489, 495, 525, 0,
947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
948 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
949 /* 49 - 720x480@120Hz */
950 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
951 798, 858, 0, 480, 489, 495, 525, 0,
952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
953 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
954 /* 50 - 720(1440)x480i@120Hz */
955 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
956 801, 858, 0, 480, 488, 494, 525, 0,
957 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
958 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
959 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
960 /* 51 - 720(1440)x480i@120Hz */
961 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
962 801, 858, 0, 480, 488, 494, 525, 0,
963 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
964 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
965 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
966 /* 52 - 720x576@200Hz */
967 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
968 796, 864, 0, 576, 581, 586, 625, 0,
969 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
970 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
971 /* 53 - 720x576@200Hz */
972 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
973 796, 864, 0, 576, 581, 586, 625, 0,
974 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
975 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
976 /* 54 - 720(1440)x576i@200Hz */
977 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
978 795, 864, 0, 576, 580, 586, 625, 0,
979 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
980 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
981 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
982 /* 55 - 720(1440)x576i@200Hz */
983 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
984 795, 864, 0, 576, 580, 586, 625, 0,
985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
986 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
987 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
988 /* 56 - 720x480@240Hz */
989 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
990 798, 858, 0, 480, 489, 495, 525, 0,
991 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
992 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
993 /* 57 - 720x480@240Hz */
994 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
995 798, 858, 0, 480, 489, 495, 525, 0,
996 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
997 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
998 /* 58 - 720(1440)x480i@240Hz */
999 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1000 801, 858, 0, 480, 488, 494, 525, 0,
1001 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1002 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1003 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1004 /* 59 - 720(1440)x480i@240Hz */
1005 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1006 801, 858, 0, 480, 488, 494, 525, 0,
1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1008 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1009 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1010 /* 60 - 1280x720@24Hz */
1011 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1012 3080, 3300, 0, 720, 725, 730, 750, 0,
1013 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1014 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1015 /* 61 - 1280x720@25Hz */
1016 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1017 3740, 3960, 0, 720, 725, 730, 750, 0,
1018 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1019 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1020 /* 62 - 1280x720@30Hz */
1021 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1022 3080, 3300, 0, 720, 725, 730, 750, 0,
1023 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1024 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1025 /* 63 - 1920x1080@120Hz */
1026 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1027 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1028 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1029 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1030 /* 64 - 1920x1080@100Hz */
1031 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1032 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1033 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1034 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1035 /* 65 - 1280x720@24Hz */
1036 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1037 3080, 3300, 0, 720, 725, 730, 750, 0,
1038 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1039 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1040 /* 66 - 1280x720@25Hz */
1041 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1042 3740, 3960, 0, 720, 725, 730, 750, 0,
1043 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1044 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1045 /* 67 - 1280x720@30Hz */
1046 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1047 3080, 3300, 0, 720, 725, 730, 750, 0,
1048 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1049 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1050 /* 68 - 1280x720@50Hz */
1051 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1052 1760, 1980, 0, 720, 725, 730, 750, 0,
1053 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1054 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1055 /* 69 - 1280x720@60Hz */
1056 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1057 1430, 1650, 0, 720, 725, 730, 750, 0,
1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1059 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1060 /* 70 - 1280x720@100Hz */
1061 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1062 1760, 1980, 0, 720, 725, 730, 750, 0,
1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1064 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1065 /* 71 - 1280x720@120Hz */
1066 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1067 1430, 1650, 0, 720, 725, 730, 750, 0,
1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1069 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1070 /* 72 - 1920x1080@24Hz */
1071 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1072 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1074 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1075 /* 73 - 1920x1080@25Hz */
1076 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1077 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1079 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1080 /* 74 - 1920x1080@30Hz */
1081 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1082 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1084 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1085 /* 75 - 1920x1080@50Hz */
1086 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1087 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1089 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1090 /* 76 - 1920x1080@60Hz */
1091 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1092 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1094 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1095 /* 77 - 1920x1080@100Hz */
1096 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1097 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1099 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1100 /* 78 - 1920x1080@120Hz */
1101 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1102 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1104 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1105 /* 79 - 1680x720@24Hz */
1106 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1107 3080, 3300, 0, 720, 725, 730, 750, 0,
1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1109 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1110 /* 80 - 1680x720@25Hz */
1111 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1112 2948, 3168, 0, 720, 725, 730, 750, 0,
1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1114 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1115 /* 81 - 1680x720@30Hz */
1116 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1117 2420, 2640, 0, 720, 725, 730, 750, 0,
1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1119 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1120 /* 82 - 1680x720@50Hz */
1121 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1122 1980, 2200, 0, 720, 725, 730, 750, 0,
1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1124 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1125 /* 83 - 1680x720@60Hz */
1126 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1127 1980, 2200, 0, 720, 725, 730, 750, 0,
1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1129 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1130 /* 84 - 1680x720@100Hz */
1131 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1132 1780, 2000, 0, 720, 725, 730, 825, 0,
1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1134 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1135 /* 85 - 1680x720@120Hz */
1136 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1137 1780, 2000, 0, 720, 725, 730, 825, 0,
1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1139 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1140 /* 86 - 2560x1080@24Hz */
1141 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1142 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1144 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1145 /* 87 - 2560x1080@25Hz */
1146 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1147 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1149 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1150 /* 88 - 2560x1080@30Hz */
1151 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1152 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1154 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1155 /* 89 - 2560x1080@50Hz */
1156 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1157 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1159 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1160 /* 90 - 2560x1080@60Hz */
1161 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1162 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1164 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1165 /* 91 - 2560x1080@100Hz */
1166 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1167 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1169 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1170 /* 92 - 2560x1080@120Hz */
1171 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1172 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1174 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1175 /* 93 - 3840x2160p@24Hz 16:9 */
1176 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1177 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1179 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1180 /* 94 - 3840x2160p@25Hz 16:9 */
1181 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1182 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1184 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1185 /* 95 - 3840x2160p@30Hz 16:9 */
1186 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1187 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1189 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1190 /* 96 - 3840x2160p@50Hz 16:9 */
1191 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1192 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1194 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1195 /* 97 - 3840x2160p@60Hz 16:9 */
1196 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1197 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1199 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1200 /* 98 - 4096x2160p@24Hz 256:135 */
1201 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1202 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1204 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1205 /* 99 - 4096x2160p@25Hz 256:135 */
1206 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1207 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1209 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1210 /* 100 - 4096x2160p@30Hz 256:135 */
1211 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1212 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1214 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1215 /* 101 - 4096x2160p@50Hz 256:135 */
1216 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1217 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1219 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1220 /* 102 - 4096x2160p@60Hz 256:135 */
1221 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1222 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1224 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1225 /* 103 - 3840x2160p@24Hz 64:27 */
1226 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1227 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1229 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1230 /* 104 - 3840x2160p@25Hz 64:27 */
1231 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1232 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1234 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1235 /* 105 - 3840x2160p@30Hz 64:27 */
1236 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1237 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1239 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1240 /* 106 - 3840x2160p@50Hz 64:27 */
1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1242 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1244 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1245 /* 107 - 3840x2160p@60Hz 64:27 */
1246 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1247 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1249 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1253 * HDMI 1.4 4k modes. Index using the VIC.
1255 static const struct drm_display_mode edid_4k_modes[] = {
1256 /* 0 - dummy, VICs start at 1 */
1258 /* 1 - 3840x2160@30Hz */
1259 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1260 3840, 4016, 4104, 4400, 0,
1261 2160, 2168, 2178, 2250, 0,
1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1264 /* 2 - 3840x2160@25Hz */
1265 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1266 3840, 4896, 4984, 5280, 0,
1267 2160, 2168, 2178, 2250, 0,
1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1270 /* 3 - 3840x2160@24Hz */
1271 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1272 3840, 5116, 5204, 5500, 0,
1273 2160, 2168, 2178, 2250, 0,
1274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1276 /* 4 - 4096x2160@24Hz (SMPTE) */
1277 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1278 4096, 5116, 5204, 5500, 0,
1279 2160, 2168, 2178, 2250, 0,
1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1284 /*** DDC fetch and block validation ***/
1286 static const u8 edid_header[] = {
1287 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1291 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1292 * @raw_edid: pointer to raw base EDID block
1294 * Sanity check the header of the base EDID block.
1296 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1298 int drm_edid_header_is_valid(const u8 *raw_edid)
1302 for (i = 0; i < sizeof(edid_header); i++)
1303 if (raw_edid[i] == edid_header[i])
1308 EXPORT_SYMBOL(drm_edid_header_is_valid);
1310 static int edid_fixup __read_mostly = 6;
1311 module_param_named(edid_fixup, edid_fixup, int, 0400);
1312 MODULE_PARM_DESC(edid_fixup,
1313 "Minimum number of valid EDID header bytes (0-8, default 6)");
1315 static void drm_get_displayid(struct drm_connector *connector,
1318 static int drm_edid_block_checksum(const u8 *raw_edid)
1322 for (i = 0; i < EDID_LENGTH; i++)
1323 csum += raw_edid[i];
1328 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1330 if (memchr_inv(in_edid, 0, length))
1337 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1338 * @raw_edid: pointer to raw EDID block
1339 * @block: type of block to validate (0 for base, extension otherwise)
1340 * @print_bad_edid: if true, dump bad EDID blocks to the console
1341 * @edid_corrupt: if true, the header or checksum is invalid
1343 * Validate a base or extension EDID block and optionally dump bad blocks to
1346 * Return: True if the block is valid, false otherwise.
1348 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1352 struct edid *edid = (struct edid *)raw_edid;
1354 if (WARN_ON(!raw_edid))
1357 if (edid_fixup > 8 || edid_fixup < 0)
1361 int score = drm_edid_header_is_valid(raw_edid);
1364 *edid_corrupt = false;
1365 } else if (score >= edid_fixup) {
1366 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1367 * The corrupt flag needs to be set here otherwise, the
1368 * fix-up code here will correct the problem, the
1369 * checksum is correct and the test fails
1372 *edid_corrupt = true;
1373 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1374 memcpy(raw_edid, edid_header, sizeof(edid_header));
1377 *edid_corrupt = true;
1382 csum = drm_edid_block_checksum(raw_edid);
1385 *edid_corrupt = true;
1387 /* allow CEA to slide through, switches mangle this */
1388 if (raw_edid[0] == CEA_EXT) {
1389 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1390 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1393 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1399 /* per-block-type checks */
1400 switch (raw_edid[0]) {
1402 if (edid->version != 1) {
1403 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1407 if (edid->revision > 4)
1408 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1418 if (print_bad_edid) {
1419 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1420 pr_notice("EDID block is all zeroes\n");
1422 pr_notice("Raw EDID:\n");
1423 print_hex_dump(KERN_NOTICE,
1424 " \t", DUMP_PREFIX_NONE, 16, 1,
1425 raw_edid, EDID_LENGTH, false);
1430 EXPORT_SYMBOL(drm_edid_block_valid);
1433 * drm_edid_is_valid - sanity check EDID data
1436 * Sanity-check an entire EDID record (including extensions)
1438 * Return: True if the EDID data is valid, false otherwise.
1440 bool drm_edid_is_valid(struct edid *edid)
1443 u8 *raw = (u8 *)edid;
1448 for (i = 0; i <= edid->extensions; i++)
1449 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1454 EXPORT_SYMBOL(drm_edid_is_valid);
1456 #define DDC_SEGMENT_ADDR 0x30
1458 * drm_do_probe_ddc_edid() - get EDID information via I2C
1459 * @data: I2C device adapter
1460 * @buf: EDID data buffer to be filled
1461 * @block: 128 byte EDID block to start fetching from
1462 * @len: EDID data buffer length to fetch
1464 * Try to fetch EDID information by calling I2C driver functions.
1466 * Return: 0 on success or -1 on failure.
1469 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1471 struct i2c_adapter *adapter = data;
1472 unsigned char start = block * EDID_LENGTH;
1473 unsigned char segment = block >> 1;
1474 unsigned char xfers = segment ? 3 : 2;
1475 int ret, retries = 5;
1478 * The core I2C driver will automatically retry the transfer if the
1479 * adapter reports EAGAIN. However, we find that bit-banging transfers
1480 * are susceptible to errors under a heavily loaded machine and
1481 * generate spurious NAKs and timeouts. Retrying the transfer
1482 * of the individual block a few times seems to overcome this.
1485 struct i2c_msg msgs[] = {
1487 .addr = DDC_SEGMENT_ADDR,
1505 * Avoid sending the segment addr to not upset non-compliant
1508 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1510 if (ret == -ENXIO) {
1511 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1515 } while (ret != xfers && --retries);
1517 return ret == xfers ? 0 : -1;
1520 static void connector_bad_edid(struct drm_connector *connector,
1521 u8 *edid, int num_blocks)
1525 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1528 dev_warn(connector->dev->dev,
1529 "%s: EDID is invalid:\n",
1531 for (i = 0; i < num_blocks; i++) {
1532 u8 *block = edid + i * EDID_LENGTH;
1535 if (drm_edid_is_zero(block, EDID_LENGTH))
1536 sprintf(prefix, "\t[%02x] ZERO ", i);
1537 else if (!drm_edid_block_valid(block, i, false, NULL))
1538 sprintf(prefix, "\t[%02x] BAD ", i);
1540 sprintf(prefix, "\t[%02x] GOOD ", i);
1542 print_hex_dump(KERN_WARNING,
1543 prefix, DUMP_PREFIX_NONE, 16, 1,
1544 block, EDID_LENGTH, false);
1549 * drm_do_get_edid - get EDID data using a custom EDID block read function
1550 * @connector: connector we're probing
1551 * @get_edid_block: EDID block read function
1552 * @data: private data passed to the block read function
1554 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1555 * exposes a different interface to read EDID blocks this function can be used
1556 * to get EDID data using a custom block read function.
1558 * As in the general case the DDC bus is accessible by the kernel at the I2C
1559 * level, drivers must make all reasonable efforts to expose it as an I2C
1560 * adapter and use drm_get_edid() instead of abusing this function.
1562 * The EDID may be overridden using debugfs override_edid or firmare EDID
1563 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1564 * order. Having either of them bypasses actual EDID reads.
1566 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1568 struct edid *drm_do_get_edid(struct drm_connector *connector,
1569 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1573 int i, j = 0, valid_extensions = 0;
1575 struct edid *override = NULL;
1577 if (connector->override_edid)
1578 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1581 override = drm_load_edid_firmware(connector);
1583 if (!IS_ERR_OR_NULL(override))
1586 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1589 /* base block fetch */
1590 for (i = 0; i < 4; i++) {
1591 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1593 if (drm_edid_block_valid(edid, 0, false,
1594 &connector->edid_corrupt))
1596 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1597 connector->null_edid_counter++;
1604 /* if there's no extensions, we're done */
1605 valid_extensions = edid[0x7e];
1606 if (valid_extensions == 0)
1607 return (struct edid *)edid;
1609 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1614 for (j = 1; j <= edid[0x7e]; j++) {
1615 u8 *block = edid + j * EDID_LENGTH;
1617 for (i = 0; i < 4; i++) {
1618 if (get_edid_block(data, block, j, EDID_LENGTH))
1620 if (drm_edid_block_valid(block, j, false, NULL))
1628 if (valid_extensions != edid[0x7e]) {
1631 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1633 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1634 edid[0x7e] = valid_extensions;
1636 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1642 for (i = 0; i <= edid[0x7e]; i++) {
1643 u8 *block = edid + i * EDID_LENGTH;
1645 if (!drm_edid_block_valid(block, i, false, NULL))
1648 memcpy(base, block, EDID_LENGTH);
1649 base += EDID_LENGTH;
1656 return (struct edid *)edid;
1659 connector_bad_edid(connector, edid, 1);
1664 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1667 * drm_probe_ddc() - probe DDC presence
1668 * @adapter: I2C adapter to probe
1670 * Return: True on success, false on failure.
1673 drm_probe_ddc(struct i2c_adapter *adapter)
1677 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1679 EXPORT_SYMBOL(drm_probe_ddc);
1682 * drm_get_edid - get EDID data, if available
1683 * @connector: connector we're probing
1684 * @adapter: I2C adapter to use for DDC
1686 * Poke the given I2C channel to grab EDID data if possible. If found,
1687 * attach it to the connector.
1689 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1691 struct edid *drm_get_edid(struct drm_connector *connector,
1692 struct i2c_adapter *adapter)
1696 if (connector->force == DRM_FORCE_OFF)
1699 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1702 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1704 drm_get_displayid(connector, edid);
1707 EXPORT_SYMBOL(drm_get_edid);
1710 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1711 * @connector: connector we're probing
1712 * @adapter: I2C adapter to use for DDC
1714 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1715 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1716 * switch DDC to the GPU which is retrieving EDID.
1718 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1720 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1721 struct i2c_adapter *adapter)
1723 struct pci_dev *pdev = connector->dev->pdev;
1726 vga_switcheroo_lock_ddc(pdev);
1727 edid = drm_get_edid(connector, adapter);
1728 vga_switcheroo_unlock_ddc(pdev);
1732 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1735 * drm_edid_duplicate - duplicate an EDID and the extensions
1736 * @edid: EDID to duplicate
1738 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1740 struct edid *drm_edid_duplicate(const struct edid *edid)
1742 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1744 EXPORT_SYMBOL(drm_edid_duplicate);
1746 /*** EDID parsing ***/
1749 * edid_vendor - match a string against EDID's obfuscated vendor field
1750 * @edid: EDID to match
1751 * @vendor: vendor string
1753 * Returns true if @vendor is in @edid, false otherwise
1755 static bool edid_vendor(const struct edid *edid, const char *vendor)
1757 char edid_vendor[3];
1759 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1760 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1761 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1762 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1764 return !strncmp(edid_vendor, vendor, 3);
1768 * edid_get_quirks - return quirk flags for a given EDID
1769 * @edid: EDID to process
1771 * This tells subsequent routines what fixes they need to apply.
1773 static u32 edid_get_quirks(const struct edid *edid)
1775 const struct edid_quirk *quirk;
1778 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1779 quirk = &edid_quirk_list[i];
1781 if (edid_vendor(edid, quirk->vendor) &&
1782 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1783 return quirk->quirks;
1789 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1790 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1793 * edid_fixup_preferred - set preferred modes based on quirk list
1794 * @connector: has mode list to fix up
1795 * @quirks: quirks list
1797 * Walk the mode list for @connector, clearing the preferred status
1798 * on existing modes and setting it anew for the right mode ala @quirks.
1800 static void edid_fixup_preferred(struct drm_connector *connector,
1803 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1804 int target_refresh = 0;
1805 int cur_vrefresh, preferred_vrefresh;
1807 if (list_empty(&connector->probed_modes))
1810 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1811 target_refresh = 60;
1812 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1813 target_refresh = 75;
1815 preferred_mode = list_first_entry(&connector->probed_modes,
1816 struct drm_display_mode, head);
1818 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1819 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1821 if (cur_mode == preferred_mode)
1824 /* Largest mode is preferred */
1825 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1826 preferred_mode = cur_mode;
1828 cur_vrefresh = cur_mode->vrefresh ?
1829 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1830 preferred_vrefresh = preferred_mode->vrefresh ?
1831 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1832 /* At a given size, try to get closest to target refresh */
1833 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1834 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1835 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1836 preferred_mode = cur_mode;
1840 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1844 mode_is_rb(const struct drm_display_mode *mode)
1846 return (mode->htotal - mode->hdisplay == 160) &&
1847 (mode->hsync_end - mode->hdisplay == 80) &&
1848 (mode->hsync_end - mode->hsync_start == 32) &&
1849 (mode->vsync_start - mode->vdisplay == 3);
1853 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1854 * @dev: Device to duplicate against
1855 * @hsize: Mode width
1856 * @vsize: Mode height
1857 * @fresh: Mode refresh rate
1858 * @rb: Mode reduced-blanking-ness
1860 * Walk the DMT mode list looking for a match for the given parameters.
1862 * Return: A newly allocated copy of the mode, or NULL if not found.
1864 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1865 int hsize, int vsize, int fresh,
1870 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1871 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1872 if (hsize != ptr->hdisplay)
1874 if (vsize != ptr->vdisplay)
1876 if (fresh != drm_mode_vrefresh(ptr))
1878 if (rb != mode_is_rb(ptr))
1881 return drm_mode_duplicate(dev, ptr);
1886 EXPORT_SYMBOL(drm_mode_find_dmt);
1888 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1891 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1895 u8 *det_base = ext + d;
1898 for (i = 0; i < n; i++)
1899 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1903 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1905 unsigned int i, n = min((int)ext[0x02], 6);
1906 u8 *det_base = ext + 5;
1909 return; /* unknown version */
1911 for (i = 0; i < n; i++)
1912 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1916 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1919 struct edid *edid = (struct edid *)raw_edid;
1924 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1925 cb(&(edid->detailed_timings[i]), closure);
1927 for (i = 1; i <= raw_edid[0x7e]; i++) {
1928 u8 *ext = raw_edid + (i * EDID_LENGTH);
1931 cea_for_each_detailed_block(ext, cb, closure);
1934 vtb_for_each_detailed_block(ext, cb, closure);
1943 is_rb(struct detailed_timing *t, void *data)
1946 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1948 *(bool *)data = true;
1951 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1953 drm_monitor_supports_rb(struct edid *edid)
1955 if (edid->revision >= 4) {
1957 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1961 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1965 find_gtf2(struct detailed_timing *t, void *data)
1968 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1972 /* Secondary GTF curve kicks in above some break frequency */
1974 drm_gtf2_hbreak(struct edid *edid)
1977 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1978 return r ? (r[12] * 2) : 0;
1982 drm_gtf2_2c(struct edid *edid)
1985 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1986 return r ? r[13] : 0;
1990 drm_gtf2_m(struct edid *edid)
1993 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1994 return r ? (r[15] << 8) + r[14] : 0;
1998 drm_gtf2_k(struct edid *edid)
2001 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2002 return r ? r[16] : 0;
2006 drm_gtf2_2j(struct edid *edid)
2009 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2010 return r ? r[17] : 0;
2014 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2015 * @edid: EDID block to scan
2017 static int standard_timing_level(struct edid *edid)
2019 if (edid->revision >= 2) {
2020 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2022 if (drm_gtf2_hbreak(edid))
2030 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2031 * monitors fill with ascii space (0x20) instead.
2034 bad_std_timing(u8 a, u8 b)
2036 return (a == 0x00 && b == 0x00) ||
2037 (a == 0x01 && b == 0x01) ||
2038 (a == 0x20 && b == 0x20);
2042 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2043 * @connector: connector of for the EDID block
2044 * @edid: EDID block to scan
2045 * @t: standard timing params
2047 * Take the standard timing params (in this case width, aspect, and refresh)
2048 * and convert them into a real mode using CVT/GTF/DMT.
2050 static struct drm_display_mode *
2051 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2052 struct std_timing *t)
2054 struct drm_device *dev = connector->dev;
2055 struct drm_display_mode *m, *mode = NULL;
2058 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2059 >> EDID_TIMING_ASPECT_SHIFT;
2060 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2061 >> EDID_TIMING_VFREQ_SHIFT;
2062 int timing_level = standard_timing_level(edid);
2064 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2067 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2068 hsize = t->hsize * 8 + 248;
2069 /* vrefresh_rate = vfreq + 60 */
2070 vrefresh_rate = vfreq + 60;
2071 /* the vdisplay is calculated based on the aspect ratio */
2072 if (aspect_ratio == 0) {
2073 if (edid->revision < 3)
2076 vsize = (hsize * 10) / 16;
2077 } else if (aspect_ratio == 1)
2078 vsize = (hsize * 3) / 4;
2079 else if (aspect_ratio == 2)
2080 vsize = (hsize * 4) / 5;
2082 vsize = (hsize * 9) / 16;
2084 /* HDTV hack, part 1 */
2085 if (vrefresh_rate == 60 &&
2086 ((hsize == 1360 && vsize == 765) ||
2087 (hsize == 1368 && vsize == 769))) {
2093 * If this connector already has a mode for this size and refresh
2094 * rate (because it came from detailed or CVT info), use that
2095 * instead. This way we don't have to guess at interlace or
2098 list_for_each_entry(m, &connector->probed_modes, head)
2099 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2100 drm_mode_vrefresh(m) == vrefresh_rate)
2103 /* HDTV hack, part 2 */
2104 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2105 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2109 mode->hdisplay = 1366;
2110 mode->hsync_start = mode->hsync_start - 1;
2111 mode->hsync_end = mode->hsync_end - 1;
2115 /* check whether it can be found in default mode table */
2116 if (drm_monitor_supports_rb(edid)) {
2117 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2122 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2126 /* okay, generate it */
2127 switch (timing_level) {
2131 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2135 * This is potentially wrong if there's ever a monitor with
2136 * more than one ranges section, each claiming a different
2137 * secondary GTF curve. Please don't do that.
2139 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2142 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2143 drm_mode_destroy(dev, mode);
2144 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2145 vrefresh_rate, 0, 0,
2153 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2161 * EDID is delightfully ambiguous about how interlaced modes are to be
2162 * encoded. Our internal representation is of frame height, but some
2163 * HDTV detailed timings are encoded as field height.
2165 * The format list here is from CEA, in frame size. Technically we
2166 * should be checking refresh rate too. Whatever.
2169 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2170 struct detailed_pixel_timing *pt)
2173 static const struct {
2175 } cea_interlaced[] = {
2185 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2188 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2189 if ((mode->hdisplay == cea_interlaced[i].w) &&
2190 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2191 mode->vdisplay *= 2;
2192 mode->vsync_start *= 2;
2193 mode->vsync_end *= 2;
2199 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2203 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2204 * @dev: DRM device (needed to create new mode)
2206 * @timing: EDID detailed timing info
2207 * @quirks: quirks to apply
2209 * An EDID detailed timing block contains enough info for us to create and
2210 * return a new struct drm_display_mode.
2212 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2214 struct detailed_timing *timing,
2217 struct drm_display_mode *mode;
2218 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2219 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2220 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2221 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2222 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2223 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2224 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2225 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2226 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2228 /* ignore tiny modes */
2229 if (hactive < 64 || vactive < 64)
2232 if (pt->misc & DRM_EDID_PT_STEREO) {
2233 DRM_DEBUG_KMS("stereo mode not supported\n");
2236 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2237 DRM_DEBUG_KMS("composite sync not supported\n");
2240 /* it is incorrect if hsync/vsync width is zero */
2241 if (!hsync_pulse_width || !vsync_pulse_width) {
2242 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2243 "Wrong Hsync/Vsync pulse width\n");
2247 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2248 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2255 mode = drm_mode_create(dev);
2259 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2260 timing->pixel_clock = cpu_to_le16(1088);
2262 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2264 mode->hdisplay = hactive;
2265 mode->hsync_start = mode->hdisplay + hsync_offset;
2266 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2267 mode->htotal = mode->hdisplay + hblank;
2269 mode->vdisplay = vactive;
2270 mode->vsync_start = mode->vdisplay + vsync_offset;
2271 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2272 mode->vtotal = mode->vdisplay + vblank;
2274 /* Some EDIDs have bogus h/vtotal values */
2275 if (mode->hsync_end > mode->htotal)
2276 mode->htotal = mode->hsync_end + 1;
2277 if (mode->vsync_end > mode->vtotal)
2278 mode->vtotal = mode->vsync_end + 1;
2280 drm_mode_do_interlace_quirk(mode, pt);
2282 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2283 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2286 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2287 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2288 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2289 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2292 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2293 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2295 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2296 mode->width_mm *= 10;
2297 mode->height_mm *= 10;
2300 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2301 mode->width_mm = edid->width_cm * 10;
2302 mode->height_mm = edid->height_cm * 10;
2305 mode->type = DRM_MODE_TYPE_DRIVER;
2306 mode->vrefresh = drm_mode_vrefresh(mode);
2307 drm_mode_set_name(mode);
2313 mode_in_hsync_range(const struct drm_display_mode *mode,
2314 struct edid *edid, u8 *t)
2316 int hsync, hmin, hmax;
2319 if (edid->revision >= 4)
2320 hmin += ((t[4] & 0x04) ? 255 : 0);
2322 if (edid->revision >= 4)
2323 hmax += ((t[4] & 0x08) ? 255 : 0);
2324 hsync = drm_mode_hsync(mode);
2326 return (hsync <= hmax && hsync >= hmin);
2330 mode_in_vsync_range(const struct drm_display_mode *mode,
2331 struct edid *edid, u8 *t)
2333 int vsync, vmin, vmax;
2336 if (edid->revision >= 4)
2337 vmin += ((t[4] & 0x01) ? 255 : 0);
2339 if (edid->revision >= 4)
2340 vmax += ((t[4] & 0x02) ? 255 : 0);
2341 vsync = drm_mode_vrefresh(mode);
2343 return (vsync <= vmax && vsync >= vmin);
2347 range_pixel_clock(struct edid *edid, u8 *t)
2350 if (t[9] == 0 || t[9] == 255)
2353 /* 1.4 with CVT support gives us real precision, yay */
2354 if (edid->revision >= 4 && t[10] == 0x04)
2355 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2357 /* 1.3 is pathetic, so fuzz up a bit */
2358 return t[9] * 10000 + 5001;
2362 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2363 struct detailed_timing *timing)
2366 u8 *t = (u8 *)timing;
2368 if (!mode_in_hsync_range(mode, edid, t))
2371 if (!mode_in_vsync_range(mode, edid, t))
2374 if ((max_clock = range_pixel_clock(edid, t)))
2375 if (mode->clock > max_clock)
2378 /* 1.4 max horizontal check */
2379 if (edid->revision >= 4 && t[10] == 0x04)
2380 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2383 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2389 static bool valid_inferred_mode(const struct drm_connector *connector,
2390 const struct drm_display_mode *mode)
2392 const struct drm_display_mode *m;
2395 list_for_each_entry(m, &connector->probed_modes, head) {
2396 if (mode->hdisplay == m->hdisplay &&
2397 mode->vdisplay == m->vdisplay &&
2398 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2399 return false; /* duplicated */
2400 if (mode->hdisplay <= m->hdisplay &&
2401 mode->vdisplay <= m->vdisplay)
2408 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2409 struct detailed_timing *timing)
2412 struct drm_display_mode *newmode;
2413 struct drm_device *dev = connector->dev;
2415 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2416 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2417 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2418 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2420 drm_mode_probed_add(connector, newmode);
2429 /* fix up 1366x768 mode from 1368x768;
2430 * GFT/CVT can't express 1366 width which isn't dividable by 8
2432 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2434 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2435 mode->hdisplay = 1366;
2436 mode->hsync_start--;
2438 drm_mode_set_name(mode);
2443 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2444 struct detailed_timing *timing)
2447 struct drm_display_mode *newmode;
2448 struct drm_device *dev = connector->dev;
2450 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2451 const struct minimode *m = &extra_modes[i];
2452 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2456 drm_mode_fixup_1366x768(newmode);
2457 if (!mode_in_range(newmode, edid, timing) ||
2458 !valid_inferred_mode(connector, newmode)) {
2459 drm_mode_destroy(dev, newmode);
2463 drm_mode_probed_add(connector, newmode);
2471 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2472 struct detailed_timing *timing)
2475 struct drm_display_mode *newmode;
2476 struct drm_device *dev = connector->dev;
2477 bool rb = drm_monitor_supports_rb(edid);
2479 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2480 const struct minimode *m = &extra_modes[i];
2481 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2485 drm_mode_fixup_1366x768(newmode);
2486 if (!mode_in_range(newmode, edid, timing) ||
2487 !valid_inferred_mode(connector, newmode)) {
2488 drm_mode_destroy(dev, newmode);
2492 drm_mode_probed_add(connector, newmode);
2500 do_inferred_modes(struct detailed_timing *timing, void *c)
2502 struct detailed_mode_closure *closure = c;
2503 struct detailed_non_pixel *data = &timing->data.other_data;
2504 struct detailed_data_monitor_range *range = &data->data.range;
2506 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2509 closure->modes += drm_dmt_modes_for_range(closure->connector,
2513 if (!version_greater(closure->edid, 1, 1))
2514 return; /* GTF not defined yet */
2516 switch (range->flags) {
2517 case 0x02: /* secondary gtf, XXX could do more */
2518 case 0x00: /* default gtf */
2519 closure->modes += drm_gtf_modes_for_range(closure->connector,
2523 case 0x04: /* cvt, only in 1.4+ */
2524 if (!version_greater(closure->edid, 1, 3))
2527 closure->modes += drm_cvt_modes_for_range(closure->connector,
2531 case 0x01: /* just the ranges, no formula */
2538 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2540 struct detailed_mode_closure closure = {
2541 .connector = connector,
2545 if (version_greater(edid, 1, 0))
2546 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2549 return closure.modes;
2553 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2555 int i, j, m, modes = 0;
2556 struct drm_display_mode *mode;
2557 u8 *est = ((u8 *)timing) + 6;
2559 for (i = 0; i < 6; i++) {
2560 for (j = 7; j >= 0; j--) {
2561 m = (i * 8) + (7 - j);
2562 if (m >= ARRAY_SIZE(est3_modes))
2564 if (est[i] & (1 << j)) {
2565 mode = drm_mode_find_dmt(connector->dev,
2571 drm_mode_probed_add(connector, mode);
2582 do_established_modes(struct detailed_timing *timing, void *c)
2584 struct detailed_mode_closure *closure = c;
2585 struct detailed_non_pixel *data = &timing->data.other_data;
2587 if (data->type == EDID_DETAIL_EST_TIMINGS)
2588 closure->modes += drm_est3_modes(closure->connector, timing);
2592 * add_established_modes - get est. modes from EDID and add them
2593 * @connector: connector to add mode(s) to
2594 * @edid: EDID block to scan
2596 * Each EDID block contains a bitmap of the supported "established modes" list
2597 * (defined above). Tease them out and add them to the global modes list.
2600 add_established_modes(struct drm_connector *connector, struct edid *edid)
2602 struct drm_device *dev = connector->dev;
2603 unsigned long est_bits = edid->established_timings.t1 |
2604 (edid->established_timings.t2 << 8) |
2605 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2607 struct detailed_mode_closure closure = {
2608 .connector = connector,
2612 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2613 if (est_bits & (1<<i)) {
2614 struct drm_display_mode *newmode;
2615 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2617 drm_mode_probed_add(connector, newmode);
2623 if (version_greater(edid, 1, 0))
2624 drm_for_each_detailed_block((u8 *)edid,
2625 do_established_modes, &closure);
2627 return modes + closure.modes;
2631 do_standard_modes(struct detailed_timing *timing, void *c)
2633 struct detailed_mode_closure *closure = c;
2634 struct detailed_non_pixel *data = &timing->data.other_data;
2635 struct drm_connector *connector = closure->connector;
2636 struct edid *edid = closure->edid;
2638 if (data->type == EDID_DETAIL_STD_MODES) {
2640 for (i = 0; i < 6; i++) {
2641 struct std_timing *std;
2642 struct drm_display_mode *newmode;
2644 std = &data->data.timings[i];
2645 newmode = drm_mode_std(connector, edid, std);
2647 drm_mode_probed_add(connector, newmode);
2655 * add_standard_modes - get std. modes from EDID and add them
2656 * @connector: connector to add mode(s) to
2657 * @edid: EDID block to scan
2659 * Standard modes can be calculated using the appropriate standard (DMT,
2660 * GTF or CVT. Grab them from @edid and add them to the list.
2663 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2666 struct detailed_mode_closure closure = {
2667 .connector = connector,
2671 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2672 struct drm_display_mode *newmode;
2674 newmode = drm_mode_std(connector, edid,
2675 &edid->standard_timings[i]);
2677 drm_mode_probed_add(connector, newmode);
2682 if (version_greater(edid, 1, 0))
2683 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2686 /* XXX should also look for standard codes in VTB blocks */
2688 return modes + closure.modes;
2691 static int drm_cvt_modes(struct drm_connector *connector,
2692 struct detailed_timing *timing)
2694 int i, j, modes = 0;
2695 struct drm_display_mode *newmode;
2696 struct drm_device *dev = connector->dev;
2697 struct cvt_timing *cvt;
2698 const int rates[] = { 60, 85, 75, 60, 50 };
2699 const u8 empty[3] = { 0, 0, 0 };
2701 for (i = 0; i < 4; i++) {
2702 int uninitialized_var(width), height;
2703 cvt = &(timing->data.other_data.data.cvt[i]);
2705 if (!memcmp(cvt->code, empty, 3))
2708 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2709 switch (cvt->code[1] & 0x0c) {
2711 width = height * 4 / 3;
2714 width = height * 16 / 9;
2717 width = height * 16 / 10;
2720 width = height * 15 / 9;
2724 for (j = 1; j < 5; j++) {
2725 if (cvt->code[2] & (1 << j)) {
2726 newmode = drm_cvt_mode(dev, width, height,
2730 drm_mode_probed_add(connector, newmode);
2741 do_cvt_mode(struct detailed_timing *timing, void *c)
2743 struct detailed_mode_closure *closure = c;
2744 struct detailed_non_pixel *data = &timing->data.other_data;
2746 if (data->type == EDID_DETAIL_CVT_3BYTE)
2747 closure->modes += drm_cvt_modes(closure->connector, timing);
2751 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2753 struct detailed_mode_closure closure = {
2754 .connector = connector,
2758 if (version_greater(edid, 1, 2))
2759 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2761 /* XXX should also look for CVT codes in VTB blocks */
2763 return closure.modes;
2766 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2769 do_detailed_mode(struct detailed_timing *timing, void *c)
2771 struct detailed_mode_closure *closure = c;
2772 struct drm_display_mode *newmode;
2774 if (timing->pixel_clock) {
2775 newmode = drm_mode_detailed(closure->connector->dev,
2776 closure->edid, timing,
2781 if (closure->preferred)
2782 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2785 * Detailed modes are limited to 10kHz pixel clock resolution,
2786 * so fix up anything that looks like CEA/HDMI mode, but the clock
2787 * is just slightly off.
2789 fixup_detailed_cea_mode_clock(newmode);
2791 drm_mode_probed_add(closure->connector, newmode);
2793 closure->preferred = false;
2798 * add_detailed_modes - Add modes from detailed timings
2799 * @connector: attached connector
2800 * @edid: EDID block to scan
2801 * @quirks: quirks to apply
2804 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2807 struct detailed_mode_closure closure = {
2808 .connector = connector,
2814 if (closure.preferred && !version_greater(edid, 1, 3))
2816 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2818 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2820 return closure.modes;
2823 #define AUDIO_BLOCK 0x01
2824 #define VIDEO_BLOCK 0x02
2825 #define VENDOR_BLOCK 0x03
2826 #define SPEAKER_BLOCK 0x04
2827 #define USE_EXTENDED_TAG 0x07
2828 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2829 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
2830 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
2831 #define EDID_BASIC_AUDIO (1 << 6)
2832 #define EDID_CEA_YCRCB444 (1 << 5)
2833 #define EDID_CEA_YCRCB422 (1 << 4)
2834 #define EDID_CEA_VCDB_QS (1 << 6)
2837 * Search EDID for CEA extension block.
2839 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
2841 u8 *edid_ext = NULL;
2844 /* No EDID or EDID extensions */
2845 if (edid == NULL || edid->extensions == 0)
2848 /* Find CEA extension */
2849 for (i = 0; i < edid->extensions; i++) {
2850 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2851 if (edid_ext[0] == ext_id)
2855 if (i == edid->extensions)
2861 static u8 *drm_find_cea_extension(const struct edid *edid)
2863 return drm_find_edid_extension(edid, CEA_EXT);
2866 static u8 *drm_find_displayid_extension(const struct edid *edid)
2868 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2872 * Calculate the alternate clock for the CEA mode
2873 * (60Hz vs. 59.94Hz etc.)
2876 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2878 unsigned int clock = cea_mode->clock;
2880 if (cea_mode->vrefresh % 6 != 0)
2884 * edid_cea_modes contains the 59.94Hz
2885 * variant for 240 and 480 line modes,
2886 * and the 60Hz variant otherwise.
2888 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2889 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2891 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2897 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2900 * For certain VICs the spec allows the vertical
2901 * front porch to vary by one or two lines.
2903 * cea_modes[] stores the variant with the shortest
2904 * vertical front porch. We can adjust the mode to
2905 * get the other variants by simply increasing the
2906 * vertical front porch length.
2908 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2909 edid_cea_modes[9].vtotal != 262 ||
2910 edid_cea_modes[12].vtotal != 262 ||
2911 edid_cea_modes[13].vtotal != 262 ||
2912 edid_cea_modes[23].vtotal != 312 ||
2913 edid_cea_modes[24].vtotal != 312 ||
2914 edid_cea_modes[27].vtotal != 312 ||
2915 edid_cea_modes[28].vtotal != 312);
2917 if (((vic == 8 || vic == 9 ||
2918 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2919 ((vic == 23 || vic == 24 ||
2920 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2921 mode->vsync_start++;
2931 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2932 unsigned int clock_tolerance)
2934 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
2937 if (!to_match->clock)
2940 if (to_match->picture_aspect_ratio)
2941 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
2943 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2944 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2945 unsigned int clock1, clock2;
2947 /* Check both 60Hz and 59.94Hz */
2948 clock1 = cea_mode.clock;
2949 clock2 = cea_mode_alternate_clock(&cea_mode);
2951 if (abs(to_match->clock - clock1) > clock_tolerance &&
2952 abs(to_match->clock - clock2) > clock_tolerance)
2956 if (drm_mode_match(to_match, &cea_mode, match_flags))
2958 } while (cea_mode_alternate_timings(vic, &cea_mode));
2965 * drm_match_cea_mode - look for a CEA mode matching given mode
2966 * @to_match: display mode
2968 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2971 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2973 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
2976 if (!to_match->clock)
2979 if (to_match->picture_aspect_ratio)
2980 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
2982 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2983 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2984 unsigned int clock1, clock2;
2986 /* Check both 60Hz and 59.94Hz */
2987 clock1 = cea_mode.clock;
2988 clock2 = cea_mode_alternate_clock(&cea_mode);
2990 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2991 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2995 if (drm_mode_match(to_match, &cea_mode, match_flags))
2997 } while (cea_mode_alternate_timings(vic, &cea_mode));
3002 EXPORT_SYMBOL(drm_match_cea_mode);
3004 static bool drm_valid_cea_vic(u8 vic)
3006 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
3010 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
3011 * the input VIC from the CEA mode list
3012 * @video_code: ID given to each of the CEA modes
3014 * Returns picture aspect ratio
3016 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3018 return edid_cea_modes[video_code].picture_aspect_ratio;
3020 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
3023 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3026 * It's almost like cea_mode_alternate_clock(), we just need to add an
3027 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
3031 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3033 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3034 return hdmi_mode->clock;
3036 return cea_mode_alternate_clock(hdmi_mode);
3039 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3040 unsigned int clock_tolerance)
3042 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3045 if (!to_match->clock)
3048 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3049 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3050 unsigned int clock1, clock2;
3052 /* Make sure to also match alternate clocks */
3053 clock1 = hdmi_mode->clock;
3054 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3056 if (abs(to_match->clock - clock1) > clock_tolerance &&
3057 abs(to_match->clock - clock2) > clock_tolerance)
3060 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3068 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3069 * @to_match: display mode
3071 * An HDMI mode is one defined in the HDMI vendor specific block.
3073 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3075 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3077 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3080 if (!to_match->clock)
3083 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3084 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3085 unsigned int clock1, clock2;
3087 /* Make sure to also match alternate clocks */
3088 clock1 = hdmi_mode->clock;
3089 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3091 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3092 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3093 drm_mode_match(to_match, hdmi_mode, match_flags))
3099 static bool drm_valid_hdmi_vic(u8 vic)
3101 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3105 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3107 struct drm_device *dev = connector->dev;
3108 struct drm_display_mode *mode, *tmp;
3112 /* Don't add CEA modes if the CEA extension block is missing */
3113 if (!drm_find_cea_extension(edid))
3117 * Go through all probed modes and create a new mode
3118 * with the alternate clock for certain CEA modes.
3120 list_for_each_entry(mode, &connector->probed_modes, head) {
3121 const struct drm_display_mode *cea_mode = NULL;
3122 struct drm_display_mode *newmode;
3123 u8 vic = drm_match_cea_mode(mode);
3124 unsigned int clock1, clock2;
3126 if (drm_valid_cea_vic(vic)) {
3127 cea_mode = &edid_cea_modes[vic];
3128 clock2 = cea_mode_alternate_clock(cea_mode);
3130 vic = drm_match_hdmi_mode(mode);
3131 if (drm_valid_hdmi_vic(vic)) {
3132 cea_mode = &edid_4k_modes[vic];
3133 clock2 = hdmi_mode_alternate_clock(cea_mode);
3140 clock1 = cea_mode->clock;
3142 if (clock1 == clock2)
3145 if (mode->clock != clock1 && mode->clock != clock2)
3148 newmode = drm_mode_duplicate(dev, cea_mode);
3152 /* Carry over the stereo flags */
3153 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3156 * The current mode could be either variant. Make
3157 * sure to pick the "other" clock for the new mode.
3159 if (mode->clock != clock1)
3160 newmode->clock = clock1;
3162 newmode->clock = clock2;
3164 list_add_tail(&newmode->head, &list);
3167 list_for_each_entry_safe(mode, tmp, &list, head) {
3168 list_del(&mode->head);
3169 drm_mode_probed_add(connector, mode);
3176 static u8 svd_to_vic(u8 svd)
3178 /* 0-6 bit vic, 7th bit native mode indicator */
3179 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3185 static struct drm_display_mode *
3186 drm_display_mode_from_vic_index(struct drm_connector *connector,
3187 const u8 *video_db, u8 video_len,
3190 struct drm_device *dev = connector->dev;
3191 struct drm_display_mode *newmode;
3194 if (video_db == NULL || video_index >= video_len)
3197 /* CEA modes are numbered 1..127 */
3198 vic = svd_to_vic(video_db[video_index]);
3199 if (!drm_valid_cea_vic(vic))
3202 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3206 newmode->vrefresh = 0;
3212 * do_y420vdb_modes - Parse YCBCR 420 only modes
3213 * @connector: connector corresponding to the HDMI sink
3214 * @svds: start of the data block of CEA YCBCR 420 VDB
3215 * @len: length of the CEA YCBCR 420 VDB
3217 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3218 * which contains modes which can be supported in YCBCR 420
3219 * output format only.
3221 static int do_y420vdb_modes(struct drm_connector *connector,
3222 const u8 *svds, u8 svds_len)
3225 struct drm_device *dev = connector->dev;
3226 struct drm_display_info *info = &connector->display_info;
3227 struct drm_hdmi_info *hdmi = &info->hdmi;
3229 for (i = 0; i < svds_len; i++) {
3230 u8 vic = svd_to_vic(svds[i]);
3231 struct drm_display_mode *newmode;
3233 if (!drm_valid_cea_vic(vic))
3236 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3239 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3240 drm_mode_probed_add(connector, newmode);
3245 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3250 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3251 * @connector: connector corresponding to the HDMI sink
3252 * @vic: CEA vic for the video mode to be added in the map
3254 * Makes an entry for a videomode in the YCBCR 420 bitmap
3257 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3259 u8 vic = svd_to_vic(svd);
3260 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3262 if (!drm_valid_cea_vic(vic))
3265 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3269 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3272 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3274 for (i = 0; i < len; i++) {
3275 struct drm_display_mode *mode;
3276 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3279 * YCBCR420 capability block contains a bitmap which
3280 * gives the index of CEA modes from CEA VDB, which
3281 * can support YCBCR 420 sampling output also (apart
3282 * from RGB/YCBCR444 etc).
3283 * For example, if the bit 0 in bitmap is set,
3284 * first mode in VDB can support YCBCR420 output too.
3285 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3287 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3288 drm_add_cmdb_modes(connector, db[i]);
3290 drm_mode_probed_add(connector, mode);
3298 struct stereo_mandatory_mode {
3299 int width, height, vrefresh;
3303 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3304 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3305 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3307 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3309 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3310 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3311 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3312 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3313 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3317 stereo_match_mandatory(const struct drm_display_mode *mode,
3318 const struct stereo_mandatory_mode *stereo_mode)
3320 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3322 return mode->hdisplay == stereo_mode->width &&
3323 mode->vdisplay == stereo_mode->height &&
3324 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3325 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3328 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3330 struct drm_device *dev = connector->dev;
3331 const struct drm_display_mode *mode;
3332 struct list_head stereo_modes;
3335 INIT_LIST_HEAD(&stereo_modes);
3337 list_for_each_entry(mode, &connector->probed_modes, head) {
3338 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3339 const struct stereo_mandatory_mode *mandatory;
3340 struct drm_display_mode *new_mode;
3342 if (!stereo_match_mandatory(mode,
3343 &stereo_mandatory_modes[i]))
3346 mandatory = &stereo_mandatory_modes[i];
3347 new_mode = drm_mode_duplicate(dev, mode);
3351 new_mode->flags |= mandatory->flags;
3352 list_add_tail(&new_mode->head, &stereo_modes);
3357 list_splice_tail(&stereo_modes, &connector->probed_modes);
3362 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3364 struct drm_device *dev = connector->dev;
3365 struct drm_display_mode *newmode;
3367 if (!drm_valid_hdmi_vic(vic)) {
3368 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3372 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3376 drm_mode_probed_add(connector, newmode);
3381 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3382 const u8 *video_db, u8 video_len, u8 video_index)
3384 struct drm_display_mode *newmode;
3387 if (structure & (1 << 0)) {
3388 newmode = drm_display_mode_from_vic_index(connector, video_db,
3392 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3393 drm_mode_probed_add(connector, newmode);
3397 if (structure & (1 << 6)) {
3398 newmode = drm_display_mode_from_vic_index(connector, video_db,
3402 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3403 drm_mode_probed_add(connector, newmode);
3407 if (structure & (1 << 8)) {
3408 newmode = drm_display_mode_from_vic_index(connector, video_db,
3412 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3413 drm_mode_probed_add(connector, newmode);
3422 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3423 * @connector: connector corresponding to the HDMI sink
3424 * @db: start of the CEA vendor specific block
3425 * @len: length of the CEA block payload, ie. one can access up to db[len]
3427 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3428 * also adds the stereo 3d modes when applicable.
3431 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3432 const u8 *video_db, u8 video_len)
3434 struct drm_display_info *info = &connector->display_info;
3435 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3436 u8 vic_len, hdmi_3d_len = 0;
3443 /* no HDMI_Video_Present */
3444 if (!(db[8] & (1 << 5)))
3447 /* Latency_Fields_Present */
3448 if (db[8] & (1 << 7))
3451 /* I_Latency_Fields_Present */
3452 if (db[8] & (1 << 6))
3455 /* the declared length is not long enough for the 2 first bytes
3456 * of additional video format capabilities */
3457 if (len < (8 + offset + 2))
3462 if (db[8 + offset] & (1 << 7)) {
3463 modes += add_hdmi_mandatory_stereo_modes(connector);
3465 /* 3D_Multi_present */
3466 multi_present = (db[8 + offset] & 0x60) >> 5;
3470 vic_len = db[8 + offset] >> 5;
3471 hdmi_3d_len = db[8 + offset] & 0x1f;
3473 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3476 vic = db[9 + offset + i];
3477 modes += add_hdmi_mode(connector, vic);
3479 offset += 1 + vic_len;
3481 if (multi_present == 1)
3483 else if (multi_present == 2)
3488 if (len < (8 + offset + hdmi_3d_len - 1))
3491 if (hdmi_3d_len < multi_len)
3494 if (multi_present == 1 || multi_present == 2) {
3495 /* 3D_Structure_ALL */
3496 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3498 /* check if 3D_MASK is present */
3499 if (multi_present == 2)
3500 mask = (db[10 + offset] << 8) | db[11 + offset];
3504 for (i = 0; i < 16; i++) {
3505 if (mask & (1 << i))
3506 modes += add_3d_struct_modes(connector,
3513 offset += multi_len;
3515 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3517 struct drm_display_mode *newmode = NULL;
3518 unsigned int newflag = 0;
3519 bool detail_present;
3521 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3523 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3526 /* 2D_VIC_order_X */
3527 vic_index = db[8 + offset + i] >> 4;
3529 /* 3D_Structure_X */
3530 switch (db[8 + offset + i] & 0x0f) {
3532 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3535 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3539 if ((db[9 + offset + i] >> 4) == 1)
3540 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3545 newmode = drm_display_mode_from_vic_index(connector,
3551 newmode->flags |= newflag;
3552 drm_mode_probed_add(connector, newmode);
3563 info->has_hdmi_infoframe = true;
3568 cea_db_payload_len(const u8 *db)
3570 return db[0] & 0x1f;
3574 cea_db_extended_tag(const u8 *db)
3580 cea_db_tag(const u8 *db)
3586 cea_revision(const u8 *cea)
3592 cea_db_offsets(const u8 *cea, int *start, int *end)
3594 /* Data block offset in CEA extension block */
3599 if (*end < 4 || *end > 127)
3604 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3608 if (cea_db_tag(db) != VENDOR_BLOCK)
3611 if (cea_db_payload_len(db) < 5)
3614 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3616 return hdmi_id == HDMI_IEEE_OUI;
3619 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3623 if (cea_db_tag(db) != VENDOR_BLOCK)
3626 if (cea_db_payload_len(db) < 7)
3629 oui = db[3] << 16 | db[2] << 8 | db[1];
3631 return oui == HDMI_FORUM_IEEE_OUI;
3634 static bool cea_db_is_y420cmdb(const u8 *db)
3636 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3639 if (!cea_db_payload_len(db))
3642 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3648 static bool cea_db_is_y420vdb(const u8 *db)
3650 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3653 if (!cea_db_payload_len(db))
3656 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3662 #define for_each_cea_db(cea, i, start, end) \
3663 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3665 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3668 struct drm_display_info *info = &connector->display_info;
3669 struct drm_hdmi_info *hdmi = &info->hdmi;
3670 u8 map_len = cea_db_payload_len(db) - 1;
3675 /* All CEA modes support ycbcr420 sampling also.*/
3676 hdmi->y420_cmdb_map = U64_MAX;
3677 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3682 * This map indicates which of the existing CEA block modes
3683 * from VDB can support YCBCR420 output too. So if bit=0 is
3684 * set, first mode from VDB can support YCBCR420 output too.
3685 * We will parse and keep this map, before parsing VDB itself
3686 * to avoid going through the same block again and again.
3688 * Spec is not clear about max possible size of this block.
3689 * Clamping max bitmap block size at 8 bytes. Every byte can
3690 * address 8 CEA modes, in this way this map can address
3691 * 8*8 = first 64 SVDs.
3693 if (WARN_ON_ONCE(map_len > 8))
3696 for (count = 0; count < map_len; count++)
3697 map |= (u64)db[2 + count] << (8 * count);
3700 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3702 hdmi->y420_cmdb_map = map;
3706 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3708 const u8 *cea = drm_find_cea_extension(edid);
3709 const u8 *db, *hdmi = NULL, *video = NULL;
3710 u8 dbl, hdmi_len, video_len = 0;
3713 if (cea && cea_revision(cea) >= 3) {
3716 if (cea_db_offsets(cea, &start, &end))
3719 for_each_cea_db(cea, i, start, end) {
3721 dbl = cea_db_payload_len(db);
3723 if (cea_db_tag(db) == VIDEO_BLOCK) {
3726 modes += do_cea_modes(connector, video, dbl);
3727 } else if (cea_db_is_hdmi_vsdb(db)) {
3730 } else if (cea_db_is_y420vdb(db)) {
3731 const u8 *vdb420 = &db[2];
3733 /* Add 4:2:0(only) modes present in EDID */
3734 modes += do_y420vdb_modes(connector,
3742 * We parse the HDMI VSDB after having added the cea modes as we will
3743 * be patching their flags when the sink supports stereo 3D.
3746 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3752 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3754 const struct drm_display_mode *cea_mode;
3755 int clock1, clock2, clock;
3760 * allow 5kHz clock difference either way to account for
3761 * the 10kHz clock resolution limit of detailed timings.
3763 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3764 if (drm_valid_cea_vic(vic)) {
3766 cea_mode = &edid_cea_modes[vic];
3767 clock1 = cea_mode->clock;
3768 clock2 = cea_mode_alternate_clock(cea_mode);
3770 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3771 if (drm_valid_hdmi_vic(vic)) {
3773 cea_mode = &edid_4k_modes[vic];
3774 clock1 = cea_mode->clock;
3775 clock2 = hdmi_mode_alternate_clock(cea_mode);
3781 /* pick whichever is closest */
3782 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3787 if (mode->clock == clock)
3790 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3791 type, vic, mode->clock, clock);
3792 mode->clock = clock;
3796 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3798 u8 len = cea_db_payload_len(db);
3800 if (len >= 6 && (db[6] & (1 << 7)))
3801 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
3803 connector->latency_present[0] = db[8] >> 7;
3804 connector->latency_present[1] = (db[8] >> 6) & 1;
3807 connector->video_latency[0] = db[9];
3809 connector->audio_latency[0] = db[10];
3811 connector->video_latency[1] = db[11];
3813 connector->audio_latency[1] = db[12];
3815 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3816 "video latency %d %d, "
3817 "audio latency %d %d\n",
3818 connector->latency_present[0],
3819 connector->latency_present[1],
3820 connector->video_latency[0],
3821 connector->video_latency[1],
3822 connector->audio_latency[0],
3823 connector->audio_latency[1]);
3827 monitor_name(struct detailed_timing *t, void *data)
3829 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3830 *(u8 **)data = t->data.other_data.data.str.str;
3833 static int get_monitor_name(struct edid *edid, char name[13])
3835 char *edid_name = NULL;
3841 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3842 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3843 if (edid_name[mnl] == 0x0a)
3846 name[mnl] = edid_name[mnl];
3853 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3854 * @edid: monitor EDID information
3855 * @name: pointer to a character array to hold the name of the monitor
3856 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3859 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3867 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3868 memcpy(name, buf, name_length);
3869 name[name_length] = '\0';
3871 EXPORT_SYMBOL(drm_edid_get_monitor_name);
3873 static void clear_eld(struct drm_connector *connector)
3875 memset(connector->eld, 0, sizeof(connector->eld));
3877 connector->latency_present[0] = false;
3878 connector->latency_present[1] = false;
3879 connector->video_latency[0] = 0;
3880 connector->audio_latency[0] = 0;
3881 connector->video_latency[1] = 0;
3882 connector->audio_latency[1] = 0;
3886 * drm_edid_to_eld - build ELD from EDID
3887 * @connector: connector corresponding to the HDMI/DP sink
3888 * @edid: EDID to parse
3890 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3891 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
3893 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3895 uint8_t *eld = connector->eld;
3898 int total_sad_count = 0;
3902 clear_eld(connector);
3907 cea = drm_find_cea_extension(edid);
3909 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3913 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
3914 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
3916 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
3917 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
3919 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
3921 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
3922 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
3923 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
3924 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
3926 if (cea_revision(cea) >= 3) {
3929 if (cea_db_offsets(cea, &start, &end)) {
3934 for_each_cea_db(cea, i, start, end) {
3936 dbl = cea_db_payload_len(db);
3938 switch (cea_db_tag(db)) {
3942 /* Audio Data Block, contains SADs */
3943 sad_count = min(dbl / 3, 15 - total_sad_count);
3945 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
3946 &db[1], sad_count * 3);
3947 total_sad_count += sad_count;
3950 /* Speaker Allocation Data Block */
3952 eld[DRM_ELD_SPEAKER] = db[1];
3955 /* HDMI Vendor-Specific Data Block */
3956 if (cea_db_is_hdmi_vsdb(db))
3957 drm_parse_hdmi_vsdb_audio(connector, db);
3964 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
3966 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3967 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3968 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
3970 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
3972 eld[DRM_ELD_BASELINE_ELD_LEN] =
3973 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3975 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3976 drm_eld_size(eld), total_sad_count);
3980 * drm_edid_to_sad - extracts SADs from EDID
3981 * @edid: EDID to parse
3982 * @sads: pointer that will be set to the extracted SADs
3984 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3986 * Note: The returned pointer needs to be freed using kfree().
3988 * Return: The number of found SADs or negative number on error.
3990 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3993 int i, start, end, dbl;
3996 cea = drm_find_cea_extension(edid);
3998 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4002 if (cea_revision(cea) < 3) {
4003 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4007 if (cea_db_offsets(cea, &start, &end)) {
4008 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4012 for_each_cea_db(cea, i, start, end) {
4015 if (cea_db_tag(db) == AUDIO_BLOCK) {
4017 dbl = cea_db_payload_len(db);
4019 count = dbl / 3; /* SAD is 3B */
4020 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4023 for (j = 0; j < count; j++) {
4024 u8 *sad = &db[1 + j * 3];
4026 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4027 (*sads)[j].channels = sad[0] & 0x7;
4028 (*sads)[j].freq = sad[1] & 0x7F;
4029 (*sads)[j].byte2 = sad[2];
4037 EXPORT_SYMBOL(drm_edid_to_sad);
4040 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4041 * @edid: EDID to parse
4042 * @sadb: pointer to the speaker block
4044 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4046 * Note: The returned pointer needs to be freed using kfree().
4048 * Return: The number of found Speaker Allocation Blocks or negative number on
4051 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4054 int i, start, end, dbl;
4057 cea = drm_find_cea_extension(edid);
4059 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4063 if (cea_revision(cea) < 3) {
4064 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4068 if (cea_db_offsets(cea, &start, &end)) {
4069 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4073 for_each_cea_db(cea, i, start, end) {
4074 const u8 *db = &cea[i];
4076 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4077 dbl = cea_db_payload_len(db);
4079 /* Speaker Allocation Data Block */
4081 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4092 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4095 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4096 * @connector: connector associated with the HDMI/DP sink
4097 * @mode: the display mode
4099 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4100 * the sink doesn't support audio or video.
4102 int drm_av_sync_delay(struct drm_connector *connector,
4103 const struct drm_display_mode *mode)
4105 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4108 if (!connector->latency_present[0])
4110 if (!connector->latency_present[1])
4113 a = connector->audio_latency[i];
4114 v = connector->video_latency[i];
4117 * HDMI/DP sink doesn't support audio or video?
4119 if (a == 255 || v == 255)
4123 * Convert raw EDID values to millisecond.
4124 * Treat unknown latency as 0ms.
4127 a = min(2 * (a - 1), 500);
4129 v = min(2 * (v - 1), 500);
4131 return max(v - a, 0);
4133 EXPORT_SYMBOL(drm_av_sync_delay);
4136 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4137 * @edid: monitor EDID information
4139 * Parse the CEA extension according to CEA-861-B.
4141 * Return: True if the monitor is HDMI, false if not or unknown.
4143 bool drm_detect_hdmi_monitor(struct edid *edid)
4147 int start_offset, end_offset;
4149 edid_ext = drm_find_cea_extension(edid);
4153 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4157 * Because HDMI identifier is in Vendor Specific Block,
4158 * search it from all data blocks of CEA extension.
4160 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4161 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4167 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4170 * drm_detect_monitor_audio - check monitor audio capability
4171 * @edid: EDID block to scan
4173 * Monitor should have CEA extension block.
4174 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4175 * audio' only. If there is any audio extension block and supported
4176 * audio format, assume at least 'basic audio' support, even if 'basic
4177 * audio' is not defined in EDID.
4179 * Return: True if the monitor supports audio, false otherwise.
4181 bool drm_detect_monitor_audio(struct edid *edid)
4185 bool has_audio = false;
4186 int start_offset, end_offset;
4188 edid_ext = drm_find_cea_extension(edid);
4192 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4195 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4199 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4202 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4203 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4205 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4206 DRM_DEBUG_KMS("CEA audio format %d\n",
4207 (edid_ext[i + j] >> 3) & 0xf);
4214 EXPORT_SYMBOL(drm_detect_monitor_audio);
4217 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
4218 * @edid: EDID block to scan
4220 * Check whether the monitor reports the RGB quantization range selection
4221 * as supported. The AVI infoframe can then be used to inform the monitor
4222 * which quantization range (full or limited) is used.
4224 * Return: True if the RGB quantization range is selectable, false otherwise.
4226 bool drm_rgb_quant_range_selectable(struct edid *edid)
4231 edid_ext = drm_find_cea_extension(edid);
4235 if (cea_db_offsets(edid_ext, &start, &end))
4238 for_each_cea_db(edid_ext, i, start, end) {
4239 if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG &&
4240 cea_db_payload_len(&edid_ext[i]) == 2 &&
4241 cea_db_extended_tag(&edid_ext[i]) ==
4242 EXT_VIDEO_CAPABILITY_BLOCK) {
4243 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
4244 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
4250 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
4253 * drm_default_rgb_quant_range - default RGB quantization range
4254 * @mode: display mode
4256 * Determine the default RGB quantization range for the mode,
4257 * as specified in CEA-861.
4259 * Return: The default RGB quantization range for the mode
4261 enum hdmi_quantization_range
4262 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4264 /* All CEA modes other than VIC 1 use limited quantization range. */
4265 return drm_match_cea_mode(mode) > 1 ?
4266 HDMI_QUANTIZATION_RANGE_LIMITED :
4267 HDMI_QUANTIZATION_RANGE_FULL;
4269 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4271 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4275 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4277 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4278 hdmi->y420_dc_modes |= dc_mask;
4281 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4284 struct drm_display_info *display = &connector->display_info;
4285 struct drm_hdmi_info *hdmi = &display->hdmi;
4287 display->has_hdmi_infoframe = true;
4289 if (hf_vsdb[6] & 0x80) {
4290 hdmi->scdc.supported = true;
4291 if (hf_vsdb[6] & 0x40)
4292 hdmi->scdc.read_request = true;
4296 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4297 * And as per the spec, three factors confirm this:
4298 * * Availability of a HF-VSDB block in EDID (check)
4299 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4300 * * SCDC support available (let's check)
4301 * Lets check it out.
4305 /* max clock is 5000 KHz times block value */
4306 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4307 struct drm_scdc *scdc = &hdmi->scdc;
4309 if (max_tmds_clock > 340000) {
4310 display->max_tmds_clock = max_tmds_clock;
4311 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4312 display->max_tmds_clock);
4315 if (scdc->supported) {
4316 scdc->scrambling.supported = true;
4318 /* Few sinks support scrambling for cloks < 340M */
4319 if ((hf_vsdb[6] & 0x8))
4320 scdc->scrambling.low_rates = true;
4324 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4327 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4330 struct drm_display_info *info = &connector->display_info;
4331 unsigned int dc_bpc = 0;
4333 /* HDMI supports at least 8 bpc */
4336 if (cea_db_payload_len(hdmi) < 6)
4339 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4341 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4342 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4346 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4348 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4349 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4353 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4355 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4356 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4361 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4366 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4367 connector->name, dc_bpc);
4371 * Deep color support mandates RGB444 support for all video
4372 * modes and forbids YCRCB422 support for all video modes per
4375 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4377 /* YCRCB444 is optional according to spec. */
4378 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4379 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4380 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4385 * Spec says that if any deep color mode is supported at all,
4386 * then deep color 36 bit must be supported.
4388 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4389 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4395 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4397 struct drm_display_info *info = &connector->display_info;
4398 u8 len = cea_db_payload_len(db);
4401 info->dvi_dual = db[6] & 1;
4403 info->max_tmds_clock = db[7] * 5000;
4405 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4406 "max TMDS clock %d kHz\n",
4408 info->max_tmds_clock);
4410 drm_parse_hdmi_deep_color_info(connector, db);
4413 static void drm_parse_cea_ext(struct drm_connector *connector,
4414 const struct edid *edid)
4416 struct drm_display_info *info = &connector->display_info;
4420 edid_ext = drm_find_cea_extension(edid);
4424 info->cea_rev = edid_ext[1];
4426 /* The existence of a CEA block should imply RGB support */
4427 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4428 if (edid_ext[3] & EDID_CEA_YCRCB444)
4429 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4430 if (edid_ext[3] & EDID_CEA_YCRCB422)
4431 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4433 if (cea_db_offsets(edid_ext, &start, &end))
4436 for_each_cea_db(edid_ext, i, start, end) {
4437 const u8 *db = &edid_ext[i];
4439 if (cea_db_is_hdmi_vsdb(db))
4440 drm_parse_hdmi_vsdb_video(connector, db);
4441 if (cea_db_is_hdmi_forum_vsdb(db))
4442 drm_parse_hdmi_forum_vsdb(connector, db);
4443 if (cea_db_is_y420cmdb(db))
4444 drm_parse_y420cmdb_bitmap(connector, db);
4448 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4449 * all of the values which would have been set from EDID
4452 drm_reset_display_info(struct drm_connector *connector)
4454 struct drm_display_info *info = &connector->display_info;
4457 info->height_mm = 0;
4460 info->color_formats = 0;
4462 info->max_tmds_clock = 0;
4463 info->dvi_dual = false;
4464 info->has_hdmi_infoframe = false;
4465 memset(&info->hdmi, 0, sizeof(info->hdmi));
4467 info->non_desktop = 0;
4470 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4472 struct drm_display_info *info = &connector->display_info;
4474 u32 quirks = edid_get_quirks(edid);
4476 drm_reset_display_info(connector);
4478 info->width_mm = edid->width_cm * 10;
4479 info->height_mm = edid->height_cm * 10;
4481 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4483 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4485 if (edid->revision < 3)
4488 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4491 drm_parse_cea_ext(connector, edid);
4494 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4496 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4497 * tells us to assume 8 bpc color depth if the EDID doesn't have
4498 * extensions which tell otherwise.
4500 if ((info->bpc == 0) && (edid->revision < 4) &&
4501 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4503 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4504 connector->name, info->bpc);
4507 /* Only defined for 1.4 with digital displays */
4508 if (edid->revision < 4)
4511 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4512 case DRM_EDID_DIGITAL_DEPTH_6:
4515 case DRM_EDID_DIGITAL_DEPTH_8:
4518 case DRM_EDID_DIGITAL_DEPTH_10:
4521 case DRM_EDID_DIGITAL_DEPTH_12:
4524 case DRM_EDID_DIGITAL_DEPTH_14:
4527 case DRM_EDID_DIGITAL_DEPTH_16:
4530 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4536 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4537 connector->name, info->bpc);
4539 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4540 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4541 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4542 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4543 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4547 static int validate_displayid(u8 *displayid, int length, int idx)
4551 struct displayid_hdr *base;
4553 base = (struct displayid_hdr *)&displayid[idx];
4555 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4556 base->rev, base->bytes, base->prod_id, base->ext_count);
4558 if (base->bytes + 5 > length - idx)
4560 for (i = idx; i <= base->bytes + 5; i++) {
4561 csum += displayid[i];
4564 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4570 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4571 struct displayid_detailed_timings_1 *timings)
4573 struct drm_display_mode *mode;
4574 unsigned pixel_clock = (timings->pixel_clock[0] |
4575 (timings->pixel_clock[1] << 8) |
4576 (timings->pixel_clock[2] << 16));
4577 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4578 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4579 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4580 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4581 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4582 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4583 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4584 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4585 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4586 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4587 mode = drm_mode_create(dev);
4591 mode->clock = pixel_clock * 10;
4592 mode->hdisplay = hactive;
4593 mode->hsync_start = mode->hdisplay + hsync;
4594 mode->hsync_end = mode->hsync_start + hsync_width;
4595 mode->htotal = mode->hdisplay + hblank;
4597 mode->vdisplay = vactive;
4598 mode->vsync_start = mode->vdisplay + vsync;
4599 mode->vsync_end = mode->vsync_start + vsync_width;
4600 mode->vtotal = mode->vdisplay + vblank;
4603 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4604 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4605 mode->type = DRM_MODE_TYPE_DRIVER;
4607 if (timings->flags & 0x80)
4608 mode->type |= DRM_MODE_TYPE_PREFERRED;
4609 mode->vrefresh = drm_mode_vrefresh(mode);
4610 drm_mode_set_name(mode);
4615 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4616 struct displayid_block *block)
4618 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4621 struct drm_display_mode *newmode;
4623 /* blocks must be multiple of 20 bytes length */
4624 if (block->num_bytes % 20)
4627 num_timings = block->num_bytes / 20;
4628 for (i = 0; i < num_timings; i++) {
4629 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4631 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4635 drm_mode_probed_add(connector, newmode);
4641 static int add_displayid_detailed_modes(struct drm_connector *connector,
4647 int length = EDID_LENGTH;
4648 struct displayid_block *block;
4651 displayid = drm_find_displayid_extension(edid);
4655 ret = validate_displayid(displayid, length, idx);
4659 idx += sizeof(struct displayid_hdr);
4660 while (block = (struct displayid_block *)&displayid[idx],
4661 idx + sizeof(struct displayid_block) <= length &&
4662 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4663 block->num_bytes > 0) {
4664 idx += block->num_bytes + sizeof(struct displayid_block);
4665 switch (block->tag) {
4666 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4667 num_modes += add_displayid_detailed_1_modes(connector, block);
4675 * drm_add_edid_modes - add modes from EDID data, if available
4676 * @connector: connector we're probing
4679 * Add the specified modes to the connector's mode list. Also fills out the
4680 * &drm_display_info structure and ELD in @connector with any information which
4681 * can be derived from the edid.
4683 * Return: The number of modes added or 0 if we couldn't find any.
4685 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4691 clear_eld(connector);
4694 if (!drm_edid_is_valid(edid)) {
4695 clear_eld(connector);
4696 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4701 drm_edid_to_eld(connector, edid);
4704 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4705 * To avoid multiple parsing of same block, lets parse that map
4706 * from sink info, before parsing CEA modes.
4708 quirks = drm_add_display_info(connector, edid);
4711 * EDID spec says modes should be preferred in this order:
4712 * - preferred detailed mode
4713 * - other detailed modes from base block
4714 * - detailed modes from extension blocks
4715 * - CVT 3-byte code modes
4716 * - standard timing codes
4717 * - established timing codes
4718 * - modes inferred from GTF or CVT range information
4720 * We get this pretty much right.
4722 * XXX order for additional mode types in extension blocks?
4724 num_modes += add_detailed_modes(connector, edid, quirks);
4725 num_modes += add_cvt_modes(connector, edid);
4726 num_modes += add_standard_modes(connector, edid);
4727 num_modes += add_established_modes(connector, edid);
4728 num_modes += add_cea_modes(connector, edid);
4729 num_modes += add_alternate_cea_modes(connector, edid);
4730 num_modes += add_displayid_detailed_modes(connector, edid);
4731 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4732 num_modes += add_inferred_modes(connector, edid);
4734 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4735 edid_fixup_preferred(connector, quirks);
4737 if (quirks & EDID_QUIRK_FORCE_6BPC)
4738 connector->display_info.bpc = 6;
4740 if (quirks & EDID_QUIRK_FORCE_8BPC)
4741 connector->display_info.bpc = 8;
4743 if (quirks & EDID_QUIRK_FORCE_10BPC)
4744 connector->display_info.bpc = 10;
4746 if (quirks & EDID_QUIRK_FORCE_12BPC)
4747 connector->display_info.bpc = 12;
4751 EXPORT_SYMBOL(drm_add_edid_modes);
4754 * drm_add_modes_noedid - add modes for the connectors without EDID
4755 * @connector: connector we're probing
4756 * @hdisplay: the horizontal display limit
4757 * @vdisplay: the vertical display limit
4759 * Add the specified modes to the connector's mode list. Only when the
4760 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4762 * Return: The number of modes added or 0 if we couldn't find any.
4764 int drm_add_modes_noedid(struct drm_connector *connector,
4765 int hdisplay, int vdisplay)
4767 int i, count, num_modes = 0;
4768 struct drm_display_mode *mode;
4769 struct drm_device *dev = connector->dev;
4771 count = ARRAY_SIZE(drm_dmt_modes);
4777 for (i = 0; i < count; i++) {
4778 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4779 if (hdisplay && vdisplay) {
4781 * Only when two are valid, they will be used to check
4782 * whether the mode should be added to the mode list of
4785 if (ptr->hdisplay > hdisplay ||
4786 ptr->vdisplay > vdisplay)
4789 if (drm_mode_vrefresh(ptr) > 61)
4791 mode = drm_mode_duplicate(dev, ptr);
4793 drm_mode_probed_add(connector, mode);
4799 EXPORT_SYMBOL(drm_add_modes_noedid);
4802 * drm_set_preferred_mode - Sets the preferred mode of a connector
4803 * @connector: connector whose mode list should be processed
4804 * @hpref: horizontal resolution of preferred mode
4805 * @vpref: vertical resolution of preferred mode
4807 * Marks a mode as preferred if it matches the resolution specified by @hpref
4810 void drm_set_preferred_mode(struct drm_connector *connector,
4811 int hpref, int vpref)
4813 struct drm_display_mode *mode;
4815 list_for_each_entry(mode, &connector->probed_modes, head) {
4816 if (mode->hdisplay == hpref &&
4817 mode->vdisplay == vpref)
4818 mode->type |= DRM_MODE_TYPE_PREFERRED;
4821 EXPORT_SYMBOL(drm_set_preferred_mode);
4824 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4825 * data from a DRM display mode
4826 * @frame: HDMI AVI infoframe
4827 * @mode: DRM display mode
4828 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant
4830 * Return: 0 on success or a negative error code on failure.
4833 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4834 const struct drm_display_mode *mode,
4837 enum hdmi_picture_aspect picture_aspect;
4840 if (!frame || !mode)
4843 err = hdmi_avi_infoframe_init(frame);
4847 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4848 frame->pixel_repeat = 1;
4850 frame->video_code = drm_match_cea_mode(mode);
4853 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4854 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4855 * have to make sure we dont break HDMI 1.4 sinks.
4857 if (!is_hdmi2_sink && frame->video_code > 64)
4858 frame->video_code = 0;
4861 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
4862 * we should send its VIC in vendor infoframes, else send the
4863 * VIC in AVI infoframes. Lets check if this mode is present in
4864 * HDMI 1.4b 4K modes
4866 if (frame->video_code) {
4867 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
4868 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
4870 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
4871 frame->video_code = 0;
4874 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4877 * Populate picture aspect ratio from either
4878 * user input (if specified) or from the CEA mode list.
4880 picture_aspect = mode->picture_aspect_ratio;
4881 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE)
4882 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code);
4885 * The infoframe can't convey anything but none, 4:3
4886 * and 16:9, so if the user has asked for anything else
4887 * we can only satisfy it by specifying the right VIC.
4889 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
4890 if (picture_aspect !=
4891 drm_get_cea_aspect_ratio(frame->video_code))
4893 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4896 frame->picture_aspect = picture_aspect;
4897 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4898 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4902 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4905 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4906 * quantization range information
4907 * @frame: HDMI AVI infoframe
4908 * @mode: DRM display mode
4909 * @rgb_quant_range: RGB quantization range (Q)
4910 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
4911 * @is_hdmi2_sink: HDMI 2.0 sink, which has different default recommendations
4913 * Note that @is_hdmi2_sink can be derived by looking at the
4914 * &drm_scdc.supported flag stored in &drm_hdmi_info.scdc,
4915 * &drm_display_info.hdmi, which can be found in &drm_connector.display_info.
4918 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
4919 const struct drm_display_mode *mode,
4920 enum hdmi_quantization_range rgb_quant_range,
4921 bool rgb_quant_range_selectable,
4926 * "A Source shall not send a non-zero Q value that does not correspond
4927 * to the default RGB Quantization Range for the transmitted Picture
4928 * unless the Sink indicates support for the Q bit in a Video
4929 * Capabilities Data Block."
4931 * HDMI 2.0 recommends sending non-zero Q when it does match the
4932 * default RGB quantization range for the mode, even when QS=0.
4934 if (rgb_quant_range_selectable ||
4935 rgb_quant_range == drm_default_rgb_quant_range(mode))
4936 frame->quantization_range = rgb_quant_range;
4938 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
4942 * "When transmitting any RGB colorimetry, the Source should set the
4943 * YQ-field to match the RGB Quantization Range being transmitted
4944 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4945 * set YQ=1) and the Sink shall ignore the YQ-field."
4947 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
4948 * by non-zero YQ when receiving RGB. There doesn't seem to be any
4949 * good way to tell which version of CEA-861 the sink supports, so
4950 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
4953 if (!is_hdmi2_sink ||
4954 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
4955 frame->ycc_quantization_range =
4956 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
4958 frame->ycc_quantization_range =
4959 HDMI_YCC_QUANTIZATION_RANGE_FULL;
4961 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
4963 static enum hdmi_3d_structure
4964 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4966 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4969 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4970 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4971 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4972 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4973 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4974 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4975 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4976 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4977 case DRM_MODE_FLAG_3D_L_DEPTH:
4978 return HDMI_3D_STRUCTURE_L_DEPTH;
4979 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4980 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4981 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4982 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4983 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4984 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4986 return HDMI_3D_STRUCTURE_INVALID;
4991 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4992 * data from a DRM display mode
4993 * @frame: HDMI vendor infoframe
4994 * @connector: the connector
4995 * @mode: DRM display mode
4997 * Note that there's is a need to send HDMI vendor infoframes only when using a
4998 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4999 * function will return -EINVAL, error that can be safely ignored.
5001 * Return: 0 on success or a negative error code on failure.
5004 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5005 struct drm_connector *connector,
5006 const struct drm_display_mode *mode)
5009 * FIXME: sil-sii8620 doesn't have a connector around when
5010 * we need one, so we have to be prepared for a NULL connector.
5012 bool has_hdmi_infoframe = connector ?
5013 connector->display_info.has_hdmi_infoframe : false;
5018 if (!frame || !mode)
5021 if (!has_hdmi_infoframe)
5024 vic = drm_match_hdmi_mode(mode);
5025 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
5028 * Even if it's not absolutely necessary to send the infoframe
5029 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5030 * know that the sink can handle it. This is based on a
5031 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5032 * have trouble realizing that they shuld switch from 3D to 2D
5033 * mode if the source simply stops sending the infoframe when
5034 * it wants to switch from 3D to 2D.
5037 if (vic && s3d_flags)
5040 err = hdmi_vendor_infoframe_init(frame);
5045 frame->s3d_struct = s3d_structure_from_display_mode(mode);
5049 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5051 static int drm_parse_tiled_block(struct drm_connector *connector,
5052 struct displayid_block *block)
5054 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5056 u8 tile_v_loc, tile_h_loc;
5057 u8 num_v_tile, num_h_tile;
5058 struct drm_tile_group *tg;
5060 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5061 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5063 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5064 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5065 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5066 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5068 connector->has_tile = true;
5069 if (tile->tile_cap & 0x80)
5070 connector->tile_is_single_monitor = true;
5072 connector->num_h_tile = num_h_tile + 1;
5073 connector->num_v_tile = num_v_tile + 1;
5074 connector->tile_h_loc = tile_h_loc;
5075 connector->tile_v_loc = tile_v_loc;
5076 connector->tile_h_size = w + 1;
5077 connector->tile_v_size = h + 1;
5079 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5080 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5081 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5082 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5083 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5085 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5087 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5092 if (connector->tile_group != tg) {
5093 /* if we haven't got a pointer,
5094 take the reference, drop ref to old tile group */
5095 if (connector->tile_group) {
5096 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5098 connector->tile_group = tg;
5100 /* if same tile group, then release the ref we just took. */
5101 drm_mode_put_tile_group(connector->dev, tg);
5105 static int drm_parse_display_id(struct drm_connector *connector,
5106 u8 *displayid, int length,
5107 bool is_edid_extension)
5109 /* if this is an EDID extension the first byte will be 0x70 */
5111 struct displayid_block *block;
5114 if (is_edid_extension)
5117 ret = validate_displayid(displayid, length, idx);
5121 idx += sizeof(struct displayid_hdr);
5122 while (block = (struct displayid_block *)&displayid[idx],
5123 idx + sizeof(struct displayid_block) <= length &&
5124 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
5125 block->num_bytes > 0) {
5126 idx += block->num_bytes + sizeof(struct displayid_block);
5127 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5128 block->tag, block->rev, block->num_bytes);
5130 switch (block->tag) {
5131 case DATA_BLOCK_TILED_DISPLAY:
5132 ret = drm_parse_tiled_block(connector, block);
5136 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5137 /* handled in mode gathering code. */
5140 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5147 static void drm_get_displayid(struct drm_connector *connector,
5150 void *displayid = NULL;
5152 connector->has_tile = false;
5153 displayid = drm_find_displayid_extension(edid);
5155 /* drop reference to any tile group we had */
5159 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5162 if (!connector->has_tile)
5166 if (connector->tile_group) {
5167 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5168 connector->tile_group = NULL;
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