2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
31 #include <linux/bitfield.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/slab.h>
38 #include <linux/vga_switcheroo.h>
40 #include <drm/drm_displayid.h>
41 #include <drm/drm_drv.h>
42 #include <drm/drm_edid.h>
43 #include <drm/drm_encoder.h>
44 #include <drm/drm_print.h>
46 #include "drm_crtc_internal.h"
48 static int oui(u8 first, u8 second, u8 third)
50 return (first << 16) | (second << 8) | third;
53 #define EDID_EST_TIMINGS 16
54 #define EDID_STD_TIMINGS 8
55 #define EDID_DETAILED_TIMINGS 4
58 * EDID blocks out in the wild have a variety of bugs, try to collect
59 * them here (note that userspace may work around broken monitors first,
60 * but fixes should make their way here so that the kernel "just works"
61 * on as many displays as possible).
64 /* First detailed mode wrong, use largest 60Hz mode */
65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
66 /* Reported 135MHz pixel clock is too high, needs adjustment */
67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
68 /* Prefer the largest mode at 75 Hz */
69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
70 /* Detail timing is in cm not mm */
71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
72 /* Detailed timing descriptors have bogus size values, so just take the
73 * maximum size and use that.
75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
76 /* use +hsync +vsync for detailed mode */
77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
78 /* Force reduced-blanking timings for detailed modes */
79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
81 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
83 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
85 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
87 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
88 /* Non desktop display (i.e. HMD) */
89 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
90 /* Cap the DSC target bitrate to 15bpp */
91 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
93 #define MICROSOFT_IEEE_OUI 0xca125c
95 struct detailed_mode_closure {
96 struct drm_connector *connector;
97 const struct drm_edid *drm_edid;
107 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
109 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
114 static const struct edid_quirk {
117 } edid_quirk_list[] = {
119 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
121 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
123 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
124 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
126 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
127 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
129 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
130 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
132 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
133 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
135 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
136 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
138 /* Belinea 10 15 55 */
139 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
140 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
142 /* Envision Peripherals, Inc. EN-7100e */
143 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
144 /* Envision EN2028 */
145 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
147 /* Funai Electronics PM36B */
148 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
149 EDID_QUIRK_DETAILED_IN_CM),
152 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
155 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
157 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
158 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
160 /* LG Philips LCD LP154W01-A5 */
161 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
162 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
164 /* Samsung SyncMaster 205BW. Note: irony */
165 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
166 /* Samsung SyncMaster 22[5-6]BW */
167 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
168 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
170 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
171 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
173 /* ViewSonic VA2026w */
174 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
176 /* Medion MD 30217 PG */
177 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
180 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
182 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
183 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
185 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
186 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
188 /* Valve Index Headset */
189 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
190 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
204 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
207 /* HTC Vive and Vive Pro VR Headsets */
208 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
209 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
211 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
212 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
213 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
214 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
217 /* Windows Mixed Reality Headsets */
218 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
219 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
221 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
222 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
223 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
225 /* Sony PlayStation VR Headset */
226 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
228 /* Sensics VR Headsets */
229 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
231 /* OSVR HDK and HDK2 VR Headsets */
232 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
236 * Autogenerated from the DMT spec.
237 * This table is copied from xfree86/modes/xf86EdidModes.c.
239 static const struct drm_display_mode drm_dmt_modes[] = {
240 /* 0x01 - 640x350@85Hz */
241 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
242 736, 832, 0, 350, 382, 385, 445, 0,
243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
244 /* 0x02 - 640x400@85Hz */
245 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
246 736, 832, 0, 400, 401, 404, 445, 0,
247 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
248 /* 0x03 - 720x400@85Hz */
249 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
250 828, 936, 0, 400, 401, 404, 446, 0,
251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
252 /* 0x04 - 640x480@60Hz */
253 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
254 752, 800, 0, 480, 490, 492, 525, 0,
255 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
256 /* 0x05 - 640x480@72Hz */
257 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
258 704, 832, 0, 480, 489, 492, 520, 0,
259 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
260 /* 0x06 - 640x480@75Hz */
261 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
262 720, 840, 0, 480, 481, 484, 500, 0,
263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
264 /* 0x07 - 640x480@85Hz */
265 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
266 752, 832, 0, 480, 481, 484, 509, 0,
267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
268 /* 0x08 - 800x600@56Hz */
269 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
270 896, 1024, 0, 600, 601, 603, 625, 0,
271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
272 /* 0x09 - 800x600@60Hz */
273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
274 968, 1056, 0, 600, 601, 605, 628, 0,
275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
276 /* 0x0a - 800x600@72Hz */
277 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
278 976, 1040, 0, 600, 637, 643, 666, 0,
279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
280 /* 0x0b - 800x600@75Hz */
281 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
282 896, 1056, 0, 600, 601, 604, 625, 0,
283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
284 /* 0x0c - 800x600@85Hz */
285 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
286 896, 1048, 0, 600, 601, 604, 631, 0,
287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
288 /* 0x0d - 800x600@120Hz RB */
289 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
290 880, 960, 0, 600, 603, 607, 636, 0,
291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
292 /* 0x0e - 848x480@60Hz */
293 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
294 976, 1088, 0, 480, 486, 494, 517, 0,
295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
296 /* 0x0f - 1024x768@43Hz, interlace */
297 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
298 1208, 1264, 0, 768, 768, 776, 817, 0,
299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
300 DRM_MODE_FLAG_INTERLACE) },
301 /* 0x10 - 1024x768@60Hz */
302 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
303 1184, 1344, 0, 768, 771, 777, 806, 0,
304 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
305 /* 0x11 - 1024x768@70Hz */
306 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
307 1184, 1328, 0, 768, 771, 777, 806, 0,
308 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
309 /* 0x12 - 1024x768@75Hz */
310 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
311 1136, 1312, 0, 768, 769, 772, 800, 0,
312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
313 /* 0x13 - 1024x768@85Hz */
314 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
315 1168, 1376, 0, 768, 769, 772, 808, 0,
316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
317 /* 0x14 - 1024x768@120Hz RB */
318 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
319 1104, 1184, 0, 768, 771, 775, 813, 0,
320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
321 /* 0x15 - 1152x864@75Hz */
322 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
323 1344, 1600, 0, 864, 865, 868, 900, 0,
324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
325 /* 0x55 - 1280x720@60Hz */
326 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
327 1430, 1650, 0, 720, 725, 730, 750, 0,
328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
329 /* 0x16 - 1280x768@60Hz RB */
330 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
331 1360, 1440, 0, 768, 771, 778, 790, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
333 /* 0x17 - 1280x768@60Hz */
334 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
335 1472, 1664, 0, 768, 771, 778, 798, 0,
336 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
337 /* 0x18 - 1280x768@75Hz */
338 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
339 1488, 1696, 0, 768, 771, 778, 805, 0,
340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
341 /* 0x19 - 1280x768@85Hz */
342 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
343 1496, 1712, 0, 768, 771, 778, 809, 0,
344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
345 /* 0x1a - 1280x768@120Hz RB */
346 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
347 1360, 1440, 0, 768, 771, 778, 813, 0,
348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
349 /* 0x1b - 1280x800@60Hz RB */
350 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
351 1360, 1440, 0, 800, 803, 809, 823, 0,
352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
353 /* 0x1c - 1280x800@60Hz */
354 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
355 1480, 1680, 0, 800, 803, 809, 831, 0,
356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
357 /* 0x1d - 1280x800@75Hz */
358 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
359 1488, 1696, 0, 800, 803, 809, 838, 0,
360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
361 /* 0x1e - 1280x800@85Hz */
362 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
363 1496, 1712, 0, 800, 803, 809, 843, 0,
364 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
365 /* 0x1f - 1280x800@120Hz RB */
366 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
367 1360, 1440, 0, 800, 803, 809, 847, 0,
368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
369 /* 0x20 - 1280x960@60Hz */
370 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
371 1488, 1800, 0, 960, 961, 964, 1000, 0,
372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
373 /* 0x21 - 1280x960@85Hz */
374 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
375 1504, 1728, 0, 960, 961, 964, 1011, 0,
376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
377 /* 0x22 - 1280x960@120Hz RB */
378 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
379 1360, 1440, 0, 960, 963, 967, 1017, 0,
380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
381 /* 0x23 - 1280x1024@60Hz */
382 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
383 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
385 /* 0x24 - 1280x1024@75Hz */
386 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
387 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
389 /* 0x25 - 1280x1024@85Hz */
390 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
391 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
393 /* 0x26 - 1280x1024@120Hz RB */
394 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
395 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
397 /* 0x27 - 1360x768@60Hz */
398 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
399 1536, 1792, 0, 768, 771, 777, 795, 0,
400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
401 /* 0x28 - 1360x768@120Hz RB */
402 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
403 1440, 1520, 0, 768, 771, 776, 813, 0,
404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
405 /* 0x51 - 1366x768@60Hz */
406 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
407 1579, 1792, 0, 768, 771, 774, 798, 0,
408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
409 /* 0x56 - 1366x768@60Hz */
410 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
411 1436, 1500, 0, 768, 769, 772, 800, 0,
412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
413 /* 0x29 - 1400x1050@60Hz RB */
414 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
415 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
417 /* 0x2a - 1400x1050@60Hz */
418 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
419 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
420 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
421 /* 0x2b - 1400x1050@75Hz */
422 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
423 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
425 /* 0x2c - 1400x1050@85Hz */
426 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
427 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
429 /* 0x2d - 1400x1050@120Hz RB */
430 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
431 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
433 /* 0x2e - 1440x900@60Hz RB */
434 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
435 1520, 1600, 0, 900, 903, 909, 926, 0,
436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
437 /* 0x2f - 1440x900@60Hz */
438 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
439 1672, 1904, 0, 900, 903, 909, 934, 0,
440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
441 /* 0x30 - 1440x900@75Hz */
442 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
443 1688, 1936, 0, 900, 903, 909, 942, 0,
444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
445 /* 0x31 - 1440x900@85Hz */
446 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
447 1696, 1952, 0, 900, 903, 909, 948, 0,
448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
449 /* 0x32 - 1440x900@120Hz RB */
450 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
451 1520, 1600, 0, 900, 903, 909, 953, 0,
452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
453 /* 0x53 - 1600x900@60Hz */
454 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
455 1704, 1800, 0, 900, 901, 904, 1000, 0,
456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
457 /* 0x33 - 1600x1200@60Hz */
458 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
459 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
461 /* 0x34 - 1600x1200@65Hz */
462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
463 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
465 /* 0x35 - 1600x1200@70Hz */
466 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
467 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
469 /* 0x36 - 1600x1200@75Hz */
470 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
471 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
473 /* 0x37 - 1600x1200@85Hz */
474 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
475 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
477 /* 0x38 - 1600x1200@120Hz RB */
478 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
479 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
481 /* 0x39 - 1680x1050@60Hz RB */
482 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
483 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
485 /* 0x3a - 1680x1050@60Hz */
486 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
487 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
489 /* 0x3b - 1680x1050@75Hz */
490 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
491 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
493 /* 0x3c - 1680x1050@85Hz */
494 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
495 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
497 /* 0x3d - 1680x1050@120Hz RB */
498 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
499 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
501 /* 0x3e - 1792x1344@60Hz */
502 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
503 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
505 /* 0x3f - 1792x1344@75Hz */
506 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
507 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
509 /* 0x40 - 1792x1344@120Hz RB */
510 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
511 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
513 /* 0x41 - 1856x1392@60Hz */
514 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
515 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
516 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
517 /* 0x42 - 1856x1392@75Hz */
518 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
519 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
521 /* 0x43 - 1856x1392@120Hz RB */
522 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
523 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
525 /* 0x52 - 1920x1080@60Hz */
526 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
527 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
529 /* 0x44 - 1920x1200@60Hz RB */
530 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
531 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
533 /* 0x45 - 1920x1200@60Hz */
534 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
535 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
537 /* 0x46 - 1920x1200@75Hz */
538 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
539 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
541 /* 0x47 - 1920x1200@85Hz */
542 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
543 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
544 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
545 /* 0x48 - 1920x1200@120Hz RB */
546 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
547 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
549 /* 0x49 - 1920x1440@60Hz */
550 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
551 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
552 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
553 /* 0x4a - 1920x1440@75Hz */
554 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
555 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
557 /* 0x4b - 1920x1440@120Hz RB */
558 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
559 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
561 /* 0x54 - 2048x1152@60Hz */
562 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
563 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
565 /* 0x4c - 2560x1600@60Hz RB */
566 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
567 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
569 /* 0x4d - 2560x1600@60Hz */
570 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
571 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
573 /* 0x4e - 2560x1600@75Hz */
574 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
575 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
576 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
577 /* 0x4f - 2560x1600@85Hz */
578 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
579 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
580 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
581 /* 0x50 - 2560x1600@120Hz RB */
582 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
583 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
585 /* 0x57 - 4096x2160@60Hz RB */
586 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
587 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
589 /* 0x58 - 4096x2160@59.94Hz RB */
590 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
591 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
596 * These more or less come from the DMT spec. The 720x400 modes are
597 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
598 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
599 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
602 * The DMT modes have been fact-checked; the rest are mild guesses.
604 static const struct drm_display_mode edid_est_modes[] = {
605 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
606 968, 1056, 0, 600, 601, 605, 628, 0,
607 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
608 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
609 896, 1024, 0, 600, 601, 603, 625, 0,
610 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
611 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
612 720, 840, 0, 480, 481, 484, 500, 0,
613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
614 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
615 704, 832, 0, 480, 489, 492, 520, 0,
616 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
617 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
618 768, 864, 0, 480, 483, 486, 525, 0,
619 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
620 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
621 752, 800, 0, 480, 490, 492, 525, 0,
622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
623 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
624 846, 900, 0, 400, 421, 423, 449, 0,
625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
626 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
627 846, 900, 0, 400, 412, 414, 449, 0,
628 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
629 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
630 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
631 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
632 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
633 1136, 1312, 0, 768, 769, 772, 800, 0,
634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
635 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
636 1184, 1328, 0, 768, 771, 777, 806, 0,
637 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
638 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
639 1184, 1344, 0, 768, 771, 777, 806, 0,
640 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
641 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
642 1208, 1264, 0, 768, 768, 776, 817, 0,
643 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
644 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
645 928, 1152, 0, 624, 625, 628, 667, 0,
646 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
647 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
648 896, 1056, 0, 600, 601, 604, 625, 0,
649 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
650 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
651 976, 1040, 0, 600, 637, 643, 666, 0,
652 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
653 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
654 1344, 1600, 0, 864, 865, 868, 900, 0,
655 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
665 static const struct minimode est3_modes[] = {
673 { 1024, 768, 85, 0 },
674 { 1152, 864, 75, 0 },
676 { 1280, 768, 60, 1 },
677 { 1280, 768, 60, 0 },
678 { 1280, 768, 75, 0 },
679 { 1280, 768, 85, 0 },
680 { 1280, 960, 60, 0 },
681 { 1280, 960, 85, 0 },
682 { 1280, 1024, 60, 0 },
683 { 1280, 1024, 85, 0 },
685 { 1360, 768, 60, 0 },
686 { 1440, 900, 60, 1 },
687 { 1440, 900, 60, 0 },
688 { 1440, 900, 75, 0 },
689 { 1440, 900, 85, 0 },
690 { 1400, 1050, 60, 1 },
691 { 1400, 1050, 60, 0 },
692 { 1400, 1050, 75, 0 },
694 { 1400, 1050, 85, 0 },
695 { 1680, 1050, 60, 1 },
696 { 1680, 1050, 60, 0 },
697 { 1680, 1050, 75, 0 },
698 { 1680, 1050, 85, 0 },
699 { 1600, 1200, 60, 0 },
700 { 1600, 1200, 65, 0 },
701 { 1600, 1200, 70, 0 },
703 { 1600, 1200, 75, 0 },
704 { 1600, 1200, 85, 0 },
705 { 1792, 1344, 60, 0 },
706 { 1792, 1344, 75, 0 },
707 { 1856, 1392, 60, 0 },
708 { 1856, 1392, 75, 0 },
709 { 1920, 1200, 60, 1 },
710 { 1920, 1200, 60, 0 },
712 { 1920, 1200, 75, 0 },
713 { 1920, 1200, 85, 0 },
714 { 1920, 1440, 60, 0 },
715 { 1920, 1440, 75, 0 },
718 static const struct minimode extra_modes[] = {
719 { 1024, 576, 60, 0 },
720 { 1366, 768, 60, 0 },
721 { 1600, 900, 60, 0 },
722 { 1680, 945, 60, 0 },
723 { 1920, 1080, 60, 0 },
724 { 2048, 1152, 60, 0 },
725 { 2048, 1536, 60, 0 },
729 * From CEA/CTA-861 spec.
731 * Do not access directly, instead always use cea_mode_for_vic().
733 static const struct drm_display_mode edid_cea_modes_1[] = {
734 /* 1 - 640x480@60Hz 4:3 */
735 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
736 752, 800, 0, 480, 490, 492, 525, 0,
737 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
738 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
739 /* 2 - 720x480@60Hz 4:3 */
740 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
741 798, 858, 0, 480, 489, 495, 525, 0,
742 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
743 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
744 /* 3 - 720x480@60Hz 16:9 */
745 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
746 798, 858, 0, 480, 489, 495, 525, 0,
747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
748 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
749 /* 4 - 1280x720@60Hz 16:9 */
750 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
751 1430, 1650, 0, 720, 725, 730, 750, 0,
752 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
753 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
754 /* 5 - 1920x1080i@60Hz 16:9 */
755 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
756 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
757 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
758 DRM_MODE_FLAG_INTERLACE),
759 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
760 /* 6 - 720(1440)x480i@60Hz 4:3 */
761 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
762 801, 858, 0, 480, 488, 494, 525, 0,
763 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
764 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
765 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
766 /* 7 - 720(1440)x480i@60Hz 16:9 */
767 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
768 801, 858, 0, 480, 488, 494, 525, 0,
769 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
770 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
771 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
772 /* 8 - 720(1440)x240@60Hz 4:3 */
773 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
774 801, 858, 0, 240, 244, 247, 262, 0,
775 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
776 DRM_MODE_FLAG_DBLCLK),
777 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
778 /* 9 - 720(1440)x240@60Hz 16:9 */
779 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
780 801, 858, 0, 240, 244, 247, 262, 0,
781 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
782 DRM_MODE_FLAG_DBLCLK),
783 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
784 /* 10 - 2880x480i@60Hz 4:3 */
785 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
786 3204, 3432, 0, 480, 488, 494, 525, 0,
787 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
788 DRM_MODE_FLAG_INTERLACE),
789 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
790 /* 11 - 2880x480i@60Hz 16:9 */
791 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
792 3204, 3432, 0, 480, 488, 494, 525, 0,
793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
794 DRM_MODE_FLAG_INTERLACE),
795 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
796 /* 12 - 2880x240@60Hz 4:3 */
797 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
798 3204, 3432, 0, 240, 244, 247, 262, 0,
799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
800 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
801 /* 13 - 2880x240@60Hz 16:9 */
802 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
803 3204, 3432, 0, 240, 244, 247, 262, 0,
804 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
806 /* 14 - 1440x480@60Hz 4:3 */
807 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
808 1596, 1716, 0, 480, 489, 495, 525, 0,
809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
810 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
811 /* 15 - 1440x480@60Hz 16:9 */
812 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
813 1596, 1716, 0, 480, 489, 495, 525, 0,
814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
815 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
816 /* 16 - 1920x1080@60Hz 16:9 */
817 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
818 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
820 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
821 /* 17 - 720x576@50Hz 4:3 */
822 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
823 796, 864, 0, 576, 581, 586, 625, 0,
824 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
825 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
826 /* 18 - 720x576@50Hz 16:9 */
827 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
828 796, 864, 0, 576, 581, 586, 625, 0,
829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
830 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
831 /* 19 - 1280x720@50Hz 16:9 */
832 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
833 1760, 1980, 0, 720, 725, 730, 750, 0,
834 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
835 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
836 /* 20 - 1920x1080i@50Hz 16:9 */
837 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
838 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
839 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
840 DRM_MODE_FLAG_INTERLACE),
841 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
842 /* 21 - 720(1440)x576i@50Hz 4:3 */
843 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
844 795, 864, 0, 576, 580, 586, 625, 0,
845 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
846 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
847 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
848 /* 22 - 720(1440)x576i@50Hz 16:9 */
849 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
850 795, 864, 0, 576, 580, 586, 625, 0,
851 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
852 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
853 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
854 /* 23 - 720(1440)x288@50Hz 4:3 */
855 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
856 795, 864, 0, 288, 290, 293, 312, 0,
857 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
858 DRM_MODE_FLAG_DBLCLK),
859 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
860 /* 24 - 720(1440)x288@50Hz 16:9 */
861 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
862 795, 864, 0, 288, 290, 293, 312, 0,
863 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
864 DRM_MODE_FLAG_DBLCLK),
865 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
866 /* 25 - 2880x576i@50Hz 4:3 */
867 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
868 3180, 3456, 0, 576, 580, 586, 625, 0,
869 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
870 DRM_MODE_FLAG_INTERLACE),
871 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
872 /* 26 - 2880x576i@50Hz 16:9 */
873 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
874 3180, 3456, 0, 576, 580, 586, 625, 0,
875 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
876 DRM_MODE_FLAG_INTERLACE),
877 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
878 /* 27 - 2880x288@50Hz 4:3 */
879 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
880 3180, 3456, 0, 288, 290, 293, 312, 0,
881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
882 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
883 /* 28 - 2880x288@50Hz 16:9 */
884 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
885 3180, 3456, 0, 288, 290, 293, 312, 0,
886 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
888 /* 29 - 1440x576@50Hz 4:3 */
889 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
890 1592, 1728, 0, 576, 581, 586, 625, 0,
891 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
892 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
893 /* 30 - 1440x576@50Hz 16:9 */
894 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
895 1592, 1728, 0, 576, 581, 586, 625, 0,
896 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
897 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
898 /* 31 - 1920x1080@50Hz 16:9 */
899 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
900 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
902 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
903 /* 32 - 1920x1080@24Hz 16:9 */
904 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
905 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
906 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
907 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
908 /* 33 - 1920x1080@25Hz 16:9 */
909 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
910 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
911 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
912 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
913 /* 34 - 1920x1080@30Hz 16:9 */
914 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
915 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
916 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
917 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
918 /* 35 - 2880x480@60Hz 4:3 */
919 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
920 3192, 3432, 0, 480, 489, 495, 525, 0,
921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
922 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
923 /* 36 - 2880x480@60Hz 16:9 */
924 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
925 3192, 3432, 0, 480, 489, 495, 525, 0,
926 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
927 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
928 /* 37 - 2880x576@50Hz 4:3 */
929 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
930 3184, 3456, 0, 576, 581, 586, 625, 0,
931 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
932 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
933 /* 38 - 2880x576@50Hz 16:9 */
934 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
935 3184, 3456, 0, 576, 581, 586, 625, 0,
936 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
937 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
938 /* 39 - 1920x1080i@50Hz 16:9 */
939 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
940 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
941 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
942 DRM_MODE_FLAG_INTERLACE),
943 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
944 /* 40 - 1920x1080i@100Hz 16:9 */
945 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
946 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
947 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
948 DRM_MODE_FLAG_INTERLACE),
949 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
950 /* 41 - 1280x720@100Hz 16:9 */
951 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
952 1760, 1980, 0, 720, 725, 730, 750, 0,
953 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
954 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
955 /* 42 - 720x576@100Hz 4:3 */
956 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
957 796, 864, 0, 576, 581, 586, 625, 0,
958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
959 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
960 /* 43 - 720x576@100Hz 16:9 */
961 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
962 796, 864, 0, 576, 581, 586, 625, 0,
963 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
964 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
965 /* 44 - 720(1440)x576i@100Hz 4:3 */
966 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
967 795, 864, 0, 576, 580, 586, 625, 0,
968 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
969 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
970 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
971 /* 45 - 720(1440)x576i@100Hz 16:9 */
972 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
973 795, 864, 0, 576, 580, 586, 625, 0,
974 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
975 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
976 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
977 /* 46 - 1920x1080i@120Hz 16:9 */
978 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
979 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
980 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
981 DRM_MODE_FLAG_INTERLACE),
982 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
983 /* 47 - 1280x720@120Hz 16:9 */
984 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
985 1430, 1650, 0, 720, 725, 730, 750, 0,
986 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
987 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
988 /* 48 - 720x480@120Hz 4:3 */
989 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
990 798, 858, 0, 480, 489, 495, 525, 0,
991 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
992 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
993 /* 49 - 720x480@120Hz 16:9 */
994 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
995 798, 858, 0, 480, 489, 495, 525, 0,
996 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
997 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
998 /* 50 - 720(1440)x480i@120Hz 4:3 */
999 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1000 801, 858, 0, 480, 488, 494, 525, 0,
1001 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1002 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1003 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1004 /* 51 - 720(1440)x480i@120Hz 16:9 */
1005 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1006 801, 858, 0, 480, 488, 494, 525, 0,
1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1008 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1009 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1010 /* 52 - 720x576@200Hz 4:3 */
1011 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1012 796, 864, 0, 576, 581, 586, 625, 0,
1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1014 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1015 /* 53 - 720x576@200Hz 16:9 */
1016 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1017 796, 864, 0, 576, 581, 586, 625, 0,
1018 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1019 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1020 /* 54 - 720(1440)x576i@200Hz 4:3 */
1021 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1022 795, 864, 0, 576, 580, 586, 625, 0,
1023 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1024 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1025 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1026 /* 55 - 720(1440)x576i@200Hz 16:9 */
1027 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1028 795, 864, 0, 576, 580, 586, 625, 0,
1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1030 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1031 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1032 /* 56 - 720x480@240Hz 4:3 */
1033 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1034 798, 858, 0, 480, 489, 495, 525, 0,
1035 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1036 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1037 /* 57 - 720x480@240Hz 16:9 */
1038 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1039 798, 858, 0, 480, 489, 495, 525, 0,
1040 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1041 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1042 /* 58 - 720(1440)x480i@240Hz 4:3 */
1043 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1044 801, 858, 0, 480, 488, 494, 525, 0,
1045 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1046 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1047 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1048 /* 59 - 720(1440)x480i@240Hz 16:9 */
1049 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1050 801, 858, 0, 480, 488, 494, 525, 0,
1051 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1052 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1053 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1054 /* 60 - 1280x720@24Hz 16:9 */
1055 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1056 3080, 3300, 0, 720, 725, 730, 750, 0,
1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1058 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1059 /* 61 - 1280x720@25Hz 16:9 */
1060 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1061 3740, 3960, 0, 720, 725, 730, 750, 0,
1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1064 /* 62 - 1280x720@30Hz 16:9 */
1065 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1066 3080, 3300, 0, 720, 725, 730, 750, 0,
1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1068 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1069 /* 63 - 1920x1080@120Hz 16:9 */
1070 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1071 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1073 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1074 /* 64 - 1920x1080@100Hz 16:9 */
1075 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1076 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1078 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1079 /* 65 - 1280x720@24Hz 64:27 */
1080 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1081 3080, 3300, 0, 720, 725, 730, 750, 0,
1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1083 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1084 /* 66 - 1280x720@25Hz 64:27 */
1085 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1086 3740, 3960, 0, 720, 725, 730, 750, 0,
1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1088 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1089 /* 67 - 1280x720@30Hz 64:27 */
1090 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1091 3080, 3300, 0, 720, 725, 730, 750, 0,
1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1093 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1094 /* 68 - 1280x720@50Hz 64:27 */
1095 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1096 1760, 1980, 0, 720, 725, 730, 750, 0,
1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1098 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1099 /* 69 - 1280x720@60Hz 64:27 */
1100 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1101 1430, 1650, 0, 720, 725, 730, 750, 0,
1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1103 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1104 /* 70 - 1280x720@100Hz 64:27 */
1105 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1106 1760, 1980, 0, 720, 725, 730, 750, 0,
1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1108 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1109 /* 71 - 1280x720@120Hz 64:27 */
1110 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1111 1430, 1650, 0, 720, 725, 730, 750, 0,
1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1113 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1114 /* 72 - 1920x1080@24Hz 64:27 */
1115 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1116 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1118 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1119 /* 73 - 1920x1080@25Hz 64:27 */
1120 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1121 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1123 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1124 /* 74 - 1920x1080@30Hz 64:27 */
1125 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1126 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1128 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1129 /* 75 - 1920x1080@50Hz 64:27 */
1130 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1131 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1133 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1134 /* 76 - 1920x1080@60Hz 64:27 */
1135 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1136 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1138 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1139 /* 77 - 1920x1080@100Hz 64:27 */
1140 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1141 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1143 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1144 /* 78 - 1920x1080@120Hz 64:27 */
1145 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1146 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1148 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1149 /* 79 - 1680x720@24Hz 64:27 */
1150 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1151 3080, 3300, 0, 720, 725, 730, 750, 0,
1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1153 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1154 /* 80 - 1680x720@25Hz 64:27 */
1155 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1156 2948, 3168, 0, 720, 725, 730, 750, 0,
1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1158 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1159 /* 81 - 1680x720@30Hz 64:27 */
1160 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1161 2420, 2640, 0, 720, 725, 730, 750, 0,
1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1163 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1164 /* 82 - 1680x720@50Hz 64:27 */
1165 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1166 1980, 2200, 0, 720, 725, 730, 750, 0,
1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1168 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1169 /* 83 - 1680x720@60Hz 64:27 */
1170 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1171 1980, 2200, 0, 720, 725, 730, 750, 0,
1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1173 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1174 /* 84 - 1680x720@100Hz 64:27 */
1175 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1176 1780, 2000, 0, 720, 725, 730, 825, 0,
1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1178 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1179 /* 85 - 1680x720@120Hz 64:27 */
1180 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1181 1780, 2000, 0, 720, 725, 730, 825, 0,
1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1183 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1184 /* 86 - 2560x1080@24Hz 64:27 */
1185 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1186 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1188 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1189 /* 87 - 2560x1080@25Hz 64:27 */
1190 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1191 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1193 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1194 /* 88 - 2560x1080@30Hz 64:27 */
1195 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1196 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1198 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1199 /* 89 - 2560x1080@50Hz 64:27 */
1200 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1201 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1203 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1204 /* 90 - 2560x1080@60Hz 64:27 */
1205 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1206 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1208 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1209 /* 91 - 2560x1080@100Hz 64:27 */
1210 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1211 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1213 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1214 /* 92 - 2560x1080@120Hz 64:27 */
1215 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1216 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1218 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1219 /* 93 - 3840x2160@24Hz 16:9 */
1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1221 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1223 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1224 /* 94 - 3840x2160@25Hz 16:9 */
1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1226 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1228 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1229 /* 95 - 3840x2160@30Hz 16:9 */
1230 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1231 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1233 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1234 /* 96 - 3840x2160@50Hz 16:9 */
1235 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1236 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1238 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1239 /* 97 - 3840x2160@60Hz 16:9 */
1240 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1241 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1243 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1244 /* 98 - 4096x2160@24Hz 256:135 */
1245 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1246 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1248 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1249 /* 99 - 4096x2160@25Hz 256:135 */
1250 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1251 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1253 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1254 /* 100 - 4096x2160@30Hz 256:135 */
1255 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1256 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1258 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1259 /* 101 - 4096x2160@50Hz 256:135 */
1260 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1261 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1263 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1264 /* 102 - 4096x2160@60Hz 256:135 */
1265 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1266 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1268 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1269 /* 103 - 3840x2160@24Hz 64:27 */
1270 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1271 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1273 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1274 /* 104 - 3840x2160@25Hz 64:27 */
1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1276 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1278 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1279 /* 105 - 3840x2160@30Hz 64:27 */
1280 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1281 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1283 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1284 /* 106 - 3840x2160@50Hz 64:27 */
1285 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1286 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1288 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1289 /* 107 - 3840x2160@60Hz 64:27 */
1290 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1291 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1293 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1294 /* 108 - 1280x720@48Hz 16:9 */
1295 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1296 2280, 2500, 0, 720, 725, 730, 750, 0,
1297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1298 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1299 /* 109 - 1280x720@48Hz 64:27 */
1300 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1301 2280, 2500, 0, 720, 725, 730, 750, 0,
1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1303 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1304 /* 110 - 1680x720@48Hz 64:27 */
1305 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1306 2530, 2750, 0, 720, 725, 730, 750, 0,
1307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1308 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1309 /* 111 - 1920x1080@48Hz 16:9 */
1310 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1311 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1313 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1314 /* 112 - 1920x1080@48Hz 64:27 */
1315 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1316 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1318 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1319 /* 113 - 2560x1080@48Hz 64:27 */
1320 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1321 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1323 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1324 /* 114 - 3840x2160@48Hz 16:9 */
1325 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1326 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1328 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1329 /* 115 - 4096x2160@48Hz 256:135 */
1330 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1331 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1333 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1334 /* 116 - 3840x2160@48Hz 64:27 */
1335 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1336 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1338 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1339 /* 117 - 3840x2160@100Hz 16:9 */
1340 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1341 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1343 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1344 /* 118 - 3840x2160@120Hz 16:9 */
1345 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1346 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1348 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1349 /* 119 - 3840x2160@100Hz 64:27 */
1350 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1351 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1353 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1354 /* 120 - 3840x2160@120Hz 64:27 */
1355 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1356 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1358 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1359 /* 121 - 5120x2160@24Hz 64:27 */
1360 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1361 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1363 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1364 /* 122 - 5120x2160@25Hz 64:27 */
1365 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1366 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1368 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1369 /* 123 - 5120x2160@30Hz 64:27 */
1370 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1371 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1373 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1374 /* 124 - 5120x2160@48Hz 64:27 */
1375 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1376 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1378 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1379 /* 125 - 5120x2160@50Hz 64:27 */
1380 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1381 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1383 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1384 /* 126 - 5120x2160@60Hz 64:27 */
1385 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1386 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1388 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1389 /* 127 - 5120x2160@100Hz 64:27 */
1390 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1391 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1393 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1397 * From CEA/CTA-861 spec.
1399 * Do not access directly, instead always use cea_mode_for_vic().
1401 static const struct drm_display_mode edid_cea_modes_193[] = {
1402 /* 193 - 5120x2160@120Hz 64:27 */
1403 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1404 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1406 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1407 /* 194 - 7680x4320@24Hz 16:9 */
1408 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1409 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1411 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1412 /* 195 - 7680x4320@25Hz 16:9 */
1413 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1414 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1416 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1417 /* 196 - 7680x4320@30Hz 16:9 */
1418 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1419 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1421 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1422 /* 197 - 7680x4320@48Hz 16:9 */
1423 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1424 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1426 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1427 /* 198 - 7680x4320@50Hz 16:9 */
1428 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1429 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1431 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1432 /* 199 - 7680x4320@60Hz 16:9 */
1433 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1434 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1436 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1437 /* 200 - 7680x4320@100Hz 16:9 */
1438 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1439 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1441 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1442 /* 201 - 7680x4320@120Hz 16:9 */
1443 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1444 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1446 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1447 /* 202 - 7680x4320@24Hz 64:27 */
1448 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1449 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1451 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1452 /* 203 - 7680x4320@25Hz 64:27 */
1453 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1454 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1456 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1457 /* 204 - 7680x4320@30Hz 64:27 */
1458 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1459 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1461 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1462 /* 205 - 7680x4320@48Hz 64:27 */
1463 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1464 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1466 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1467 /* 206 - 7680x4320@50Hz 64:27 */
1468 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1469 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1471 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1472 /* 207 - 7680x4320@60Hz 64:27 */
1473 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1474 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1476 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1477 /* 208 - 7680x4320@100Hz 64:27 */
1478 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1479 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1481 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1482 /* 209 - 7680x4320@120Hz 64:27 */
1483 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1484 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1486 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1487 /* 210 - 10240x4320@24Hz 64:27 */
1488 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1489 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1491 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1492 /* 211 - 10240x4320@25Hz 64:27 */
1493 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1494 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1496 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1497 /* 212 - 10240x4320@30Hz 64:27 */
1498 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1499 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1501 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1502 /* 213 - 10240x4320@48Hz 64:27 */
1503 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1504 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1506 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1507 /* 214 - 10240x4320@50Hz 64:27 */
1508 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1509 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1511 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1512 /* 215 - 10240x4320@60Hz 64:27 */
1513 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1514 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1516 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1517 /* 216 - 10240x4320@100Hz 64:27 */
1518 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1519 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1521 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1522 /* 217 - 10240x4320@120Hz 64:27 */
1523 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1524 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1526 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1527 /* 218 - 4096x2160@100Hz 256:135 */
1528 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1529 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1531 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1532 /* 219 - 4096x2160@120Hz 256:135 */
1533 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1534 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1535 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1536 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1540 * HDMI 1.4 4k modes. Index using the VIC.
1542 static const struct drm_display_mode edid_4k_modes[] = {
1543 /* 0 - dummy, VICs start at 1 */
1545 /* 1 - 3840x2160@30Hz */
1546 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1547 3840, 4016, 4104, 4400, 0,
1548 2160, 2168, 2178, 2250, 0,
1549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1550 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1551 /* 2 - 3840x2160@25Hz */
1552 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1553 3840, 4896, 4984, 5280, 0,
1554 2160, 2168, 2178, 2250, 0,
1555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1556 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1557 /* 3 - 3840x2160@24Hz */
1558 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1559 3840, 5116, 5204, 5500, 0,
1560 2160, 2168, 2178, 2250, 0,
1561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1562 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1563 /* 4 - 4096x2160@24Hz (SMPTE) */
1564 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1565 4096, 5116, 5204, 5500, 0,
1566 2160, 2168, 2178, 2250, 0,
1567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1568 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1571 /*** DDC fetch and block validation ***/
1574 * The opaque EDID type, internal to drm_edid.c.
1577 /* Size allocated for edid */
1579 const struct edid *edid;
1582 static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1584 static int edid_hfeeodb_block_count(const struct edid *edid)
1586 int eeodb = edid_hfeeodb_extension_block_count(edid);
1588 return eeodb ? eeodb + 1 : 0;
1591 static int edid_extension_block_count(const struct edid *edid)
1593 return edid->extensions;
1596 static int edid_block_count(const struct edid *edid)
1598 return edid_extension_block_count(edid) + 1;
1601 static int edid_size_by_blocks(int num_blocks)
1603 return num_blocks * EDID_LENGTH;
1606 static int edid_size(const struct edid *edid)
1608 return edid_size_by_blocks(edid_block_count(edid));
1611 static const void *edid_block_data(const struct edid *edid, int index)
1613 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1615 return edid + index;
1618 static const void *edid_extension_block_data(const struct edid *edid, int index)
1620 return edid_block_data(edid, index + 1);
1623 /* EDID block count indicated in EDID, may exceed allocated size */
1624 static int __drm_edid_block_count(const struct drm_edid *drm_edid)
1628 /* Starting point */
1629 num_blocks = edid_block_count(drm_edid->edid);
1631 /* HF-EEODB override */
1632 if (drm_edid->size >= edid_size_by_blocks(2)) {
1636 * Note: HF-EEODB may specify a smaller extension count than the
1637 * regular one. Unlike in buffer allocation, here we can use it.
1639 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1647 /* EDID block count, limited by allocated size */
1648 static int drm_edid_block_count(const struct drm_edid *drm_edid)
1650 /* Limit by allocated size */
1651 return min(__drm_edid_block_count(drm_edid),
1652 (int)drm_edid->size / EDID_LENGTH);
1655 /* EDID extension block count, limited by allocated size */
1656 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1658 return drm_edid_block_count(drm_edid) - 1;
1661 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1663 return edid_block_data(drm_edid->edid, index);
1666 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1669 return edid_extension_block_data(drm_edid->edid, index);
1673 * Initializer helper for legacy interfaces, where we have no choice but to
1674 * trust edid size. Not for general purpose use.
1676 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1677 const struct edid *edid)
1682 memset(drm_edid, 0, sizeof(*drm_edid));
1684 drm_edid->edid = edid;
1685 drm_edid->size = edid_size(edid);
1691 * EDID base and extension block iterator.
1693 * struct drm_edid_iter iter;
1696 * drm_edid_iter_begin(drm_edid, &iter);
1697 * drm_edid_iter_for_each(block, &iter) {
1698 * // do stuff with block
1700 * drm_edid_iter_end(&iter);
1702 struct drm_edid_iter {
1703 const struct drm_edid *drm_edid;
1705 /* Current block index. */
1709 static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1710 struct drm_edid_iter *iter)
1712 memset(iter, 0, sizeof(*iter));
1714 iter->drm_edid = drm_edid;
1717 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1719 const void *block = NULL;
1721 if (!iter->drm_edid)
1724 if (iter->index < drm_edid_block_count(iter->drm_edid))
1725 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1730 #define drm_edid_iter_for_each(__block, __iter) \
1731 while (((__block) = __drm_edid_iter_next(__iter)))
1733 static void drm_edid_iter_end(struct drm_edid_iter *iter)
1735 memset(iter, 0, sizeof(*iter));
1738 static const u8 edid_header[] = {
1739 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1742 static void edid_header_fix(void *edid)
1744 memcpy(edid, edid_header, sizeof(edid_header));
1748 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1749 * @_edid: pointer to raw base EDID block
1751 * Sanity check the header of the base EDID block.
1753 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1755 int drm_edid_header_is_valid(const void *_edid)
1757 const struct edid *edid = _edid;
1760 for (i = 0; i < sizeof(edid_header); i++) {
1761 if (edid->header[i] == edid_header[i])
1767 EXPORT_SYMBOL(drm_edid_header_is_valid);
1769 static int edid_fixup __read_mostly = 6;
1770 module_param_named(edid_fixup, edid_fixup, int, 0400);
1771 MODULE_PARM_DESC(edid_fixup,
1772 "Minimum number of valid EDID header bytes (0-8, default 6)");
1774 static int edid_block_compute_checksum(const void *_block)
1776 const u8 *block = _block;
1778 u8 csum = 0, crc = 0;
1780 for (i = 0; i < EDID_LENGTH - 1; i++)
1788 static int edid_block_get_checksum(const void *_block)
1790 const struct edid *block = _block;
1792 return block->checksum;
1795 static int edid_block_tag(const void *_block)
1797 const u8 *block = _block;
1802 static bool edid_block_is_zero(const void *edid)
1804 return !memchr_inv(edid, 0, EDID_LENGTH);
1808 * drm_edid_are_equal - compare two edid blobs.
1809 * @edid1: pointer to first blob
1810 * @edid2: pointer to second blob
1811 * This helper can be used during probing to determine if
1814 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1816 int edid1_len, edid2_len;
1817 bool edid1_present = edid1 != NULL;
1818 bool edid2_present = edid2 != NULL;
1820 if (edid1_present != edid2_present)
1824 edid1_len = edid_size(edid1);
1825 edid2_len = edid_size(edid2);
1827 if (edid1_len != edid2_len)
1830 if (memcmp(edid1, edid2, edid1_len))
1836 EXPORT_SYMBOL(drm_edid_are_equal);
1838 enum edid_block_status {
1840 EDID_BLOCK_READ_FAIL,
1843 EDID_BLOCK_HEADER_CORRUPT,
1844 EDID_BLOCK_HEADER_REPAIR,
1845 EDID_BLOCK_HEADER_FIXED,
1846 EDID_BLOCK_CHECKSUM,
1850 static enum edid_block_status edid_block_check(const void *_block,
1853 const struct edid *block = _block;
1856 return EDID_BLOCK_NULL;
1858 if (is_base_block) {
1859 int score = drm_edid_header_is_valid(block);
1861 if (score < clamp(edid_fixup, 0, 8)) {
1862 if (edid_block_is_zero(block))
1863 return EDID_BLOCK_ZERO;
1865 return EDID_BLOCK_HEADER_CORRUPT;
1869 return EDID_BLOCK_HEADER_REPAIR;
1872 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1873 if (edid_block_is_zero(block))
1874 return EDID_BLOCK_ZERO;
1876 return EDID_BLOCK_CHECKSUM;
1879 if (is_base_block) {
1880 if (block->version != 1)
1881 return EDID_BLOCK_VERSION;
1884 return EDID_BLOCK_OK;
1887 static bool edid_block_status_valid(enum edid_block_status status, int tag)
1889 return status == EDID_BLOCK_OK ||
1890 status == EDID_BLOCK_HEADER_FIXED ||
1891 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1894 static bool edid_block_valid(const void *block, bool base)
1896 return edid_block_status_valid(edid_block_check(block, base),
1897 edid_block_tag(block));
1900 static void edid_block_status_print(enum edid_block_status status,
1901 const struct edid *block,
1907 case EDID_BLOCK_READ_FAIL:
1908 pr_debug("EDID block %d read failed\n", block_num);
1910 case EDID_BLOCK_NULL:
1911 pr_debug("EDID block %d pointer is NULL\n", block_num);
1913 case EDID_BLOCK_ZERO:
1914 pr_notice("EDID block %d is all zeroes\n", block_num);
1916 case EDID_BLOCK_HEADER_CORRUPT:
1917 pr_notice("EDID has corrupt header\n");
1919 case EDID_BLOCK_HEADER_REPAIR:
1920 pr_debug("EDID corrupt header needs repair\n");
1922 case EDID_BLOCK_HEADER_FIXED:
1923 pr_debug("EDID corrupt header fixed\n");
1925 case EDID_BLOCK_CHECKSUM:
1926 if (edid_block_status_valid(status, edid_block_tag(block))) {
1927 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1928 block_num, edid_block_tag(block),
1929 edid_block_compute_checksum(block));
1931 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1932 block_num, edid_block_tag(block),
1933 edid_block_compute_checksum(block));
1936 case EDID_BLOCK_VERSION:
1937 pr_notice("EDID has major version %d, instead of 1\n",
1941 WARN(1, "EDID block %d unknown edid block status code %d\n",
1947 static void edid_block_dump(const char *level, const void *block, int block_num)
1949 enum edid_block_status status;
1952 status = edid_block_check(block, block_num == 0);
1953 if (status == EDID_BLOCK_ZERO)
1954 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1955 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1956 sprintf(prefix, "\t[%02x] BAD ", block_num);
1958 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1960 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1961 block, EDID_LENGTH, false);
1965 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1966 * @_block: pointer to raw EDID block
1967 * @block_num: type of block to validate (0 for base, extension otherwise)
1968 * @print_bad_edid: if true, dump bad EDID blocks to the console
1969 * @edid_corrupt: if true, the header or checksum is invalid
1971 * Validate a base or extension EDID block and optionally dump bad blocks to
1974 * Return: True if the block is valid, false otherwise.
1976 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
1979 struct edid *block = (struct edid *)_block;
1980 enum edid_block_status status;
1981 bool is_base_block = block_num == 0;
1984 if (WARN_ON(!block))
1987 status = edid_block_check(block, is_base_block);
1988 if (status == EDID_BLOCK_HEADER_REPAIR) {
1989 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1990 edid_header_fix(block);
1992 /* Retry with fixed header, update status if that worked. */
1993 status = edid_block_check(block, is_base_block);
1994 if (status == EDID_BLOCK_OK)
1995 status = EDID_BLOCK_HEADER_FIXED;
2000 * Unknown major version isn't corrupt but we can't use it. Only
2001 * the base block can reset edid_corrupt to false.
2003 if (is_base_block &&
2004 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2005 *edid_corrupt = false;
2006 else if (status != EDID_BLOCK_OK)
2007 *edid_corrupt = true;
2010 edid_block_status_print(status, block, block_num);
2012 /* Determine whether we can use this block with this status. */
2013 valid = edid_block_status_valid(status, edid_block_tag(block));
2015 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2016 pr_notice("Raw EDID:\n");
2017 edid_block_dump(KERN_NOTICE, block, block_num);
2022 EXPORT_SYMBOL(drm_edid_block_valid);
2025 * drm_edid_is_valid - sanity check EDID data
2028 * Sanity-check an entire EDID record (including extensions)
2030 * Return: True if the EDID data is valid, false otherwise.
2032 bool drm_edid_is_valid(struct edid *edid)
2039 for (i = 0; i < edid_block_count(edid); i++) {
2040 void *block = (void *)edid_block_data(edid, i);
2042 if (!drm_edid_block_valid(block, i, true, NULL))
2048 EXPORT_SYMBOL(drm_edid_is_valid);
2051 * drm_edid_valid - sanity check EDID data
2052 * @drm_edid: EDID data
2054 * Sanity check an EDID. Cross check block count against allocated size and
2055 * checksum the blocks.
2057 * Return: True if the EDID data is valid, false otherwise.
2059 bool drm_edid_valid(const struct drm_edid *drm_edid)
2066 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2069 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2070 const void *block = drm_edid_block_data(drm_edid, i);
2072 if (!edid_block_valid(block, i == 0))
2078 EXPORT_SYMBOL(drm_edid_valid);
2080 static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2084 int i, valid_blocks = 0;
2087 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2088 * back to regular extension count here. We don't want to start
2089 * modifying the HF-EEODB extension too.
2091 for (i = 0; i < edid_block_count(edid); i++) {
2092 const void *src_block = edid_block_data(edid, i);
2094 if (edid_block_valid(src_block, i == 0)) {
2095 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2097 memmove(dst_block, src_block, EDID_LENGTH);
2102 /* We already trusted the base block to be valid here... */
2103 if (WARN_ON(!valid_blocks)) {
2108 edid->extensions = valid_blocks - 1;
2109 edid->checksum = edid_block_compute_checksum(edid);
2111 *alloc_size = edid_size_by_blocks(valid_blocks);
2113 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2120 #define DDC_SEGMENT_ADDR 0x30
2122 * drm_do_probe_ddc_edid() - get EDID information via I2C
2123 * @data: I2C device adapter
2124 * @buf: EDID data buffer to be filled
2125 * @block: 128 byte EDID block to start fetching from
2126 * @len: EDID data buffer length to fetch
2128 * Try to fetch EDID information by calling I2C driver functions.
2130 * Return: 0 on success or -1 on failure.
2133 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2135 struct i2c_adapter *adapter = data;
2136 unsigned char start = block * EDID_LENGTH;
2137 unsigned char segment = block >> 1;
2138 unsigned char xfers = segment ? 3 : 2;
2139 int ret, retries = 5;
2142 * The core I2C driver will automatically retry the transfer if the
2143 * adapter reports EAGAIN. However, we find that bit-banging transfers
2144 * are susceptible to errors under a heavily loaded machine and
2145 * generate spurious NAKs and timeouts. Retrying the transfer
2146 * of the individual block a few times seems to overcome this.
2149 struct i2c_msg msgs[] = {
2151 .addr = DDC_SEGMENT_ADDR,
2169 * Avoid sending the segment addr to not upset non-compliant
2172 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2174 if (ret == -ENXIO) {
2175 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2179 } while (ret != xfers && --retries);
2181 return ret == xfers ? 0 : -1;
2184 static void connector_bad_edid(struct drm_connector *connector,
2185 const struct edid *edid, int num_blocks)
2191 * 0x7e in the EDID is the number of extension blocks. The EDID
2192 * is 1 (base block) + num_ext_blocks big. That means we can think
2193 * of 0x7e in the EDID of the _index_ of the last block in the
2194 * combined chunk of memory.
2196 last_block = edid->extensions;
2198 /* Calculate real checksum for the last edid extension block data */
2199 if (last_block < num_blocks)
2200 connector->real_edid_checksum =
2201 edid_block_compute_checksum(edid + last_block);
2203 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2206 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2207 connector->base.id, connector->name);
2208 for (i = 0; i < num_blocks; i++)
2209 edid_block_dump(KERN_DEBUG, edid + i, i);
2212 /* Get override or firmware EDID */
2213 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
2215 const struct drm_edid *override = NULL;
2217 mutex_lock(&connector->edid_override_mutex);
2219 if (connector->edid_override)
2220 override = drm_edid_dup(connector->edid_override);
2222 mutex_unlock(&connector->edid_override_mutex);
2225 override = drm_edid_load_firmware(connector);
2227 return IS_ERR(override) ? NULL : override;
2230 /* For debugfs edid_override implementation */
2231 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2233 const struct drm_edid *drm_edid;
2235 mutex_lock(&connector->edid_override_mutex);
2237 drm_edid = connector->edid_override;
2239 seq_write(m, drm_edid->edid, drm_edid->size);
2241 mutex_unlock(&connector->edid_override_mutex);
2246 /* For debugfs edid_override implementation */
2247 int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2250 const struct drm_edid *drm_edid;
2252 drm_edid = drm_edid_alloc(edid, size);
2253 if (!drm_edid_valid(drm_edid)) {
2254 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2255 connector->base.id, connector->name);
2256 drm_edid_free(drm_edid);
2260 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2261 connector->base.id, connector->name);
2263 mutex_lock(&connector->edid_override_mutex);
2265 drm_edid_free(connector->edid_override);
2266 connector->edid_override = drm_edid;
2268 mutex_unlock(&connector->edid_override_mutex);
2273 /* For debugfs edid_override implementation */
2274 int drm_edid_override_reset(struct drm_connector *connector)
2276 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2277 connector->base.id, connector->name);
2279 mutex_lock(&connector->edid_override_mutex);
2281 drm_edid_free(connector->edid_override);
2282 connector->edid_override = NULL;
2284 mutex_unlock(&connector->edid_override_mutex);
2290 * drm_edid_override_connector_update - add modes from override/firmware EDID
2291 * @connector: connector we're probing
2293 * Add modes from the override/firmware EDID, if available. Only to be used from
2294 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2295 * failed during drm_get_edid() and caused the override/firmware EDID to be
2298 * Return: The number of modes added or 0 if we couldn't find any.
2300 int drm_edid_override_connector_update(struct drm_connector *connector)
2302 const struct drm_edid *override;
2305 override = drm_edid_override_get(connector);
2307 num_modes = drm_edid_connector_update(connector, override);
2309 drm_edid_free(override);
2311 drm_dbg_kms(connector->dev,
2312 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2313 connector->base.id, connector->name, num_modes);
2318 EXPORT_SYMBOL(drm_edid_override_connector_update);
2320 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2322 static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2323 read_block_fn read_block,
2326 enum edid_block_status status;
2327 bool is_base_block = block_num == 0;
2330 for (try = 0; try < 4; try++) {
2331 if (read_block(context, block, block_num, EDID_LENGTH))
2332 return EDID_BLOCK_READ_FAIL;
2334 status = edid_block_check(block, is_base_block);
2335 if (status == EDID_BLOCK_HEADER_REPAIR) {
2336 edid_header_fix(block);
2338 /* Retry with fixed header, update status if that worked. */
2339 status = edid_block_check(block, is_base_block);
2340 if (status == EDID_BLOCK_OK)
2341 status = EDID_BLOCK_HEADER_FIXED;
2344 if (edid_block_status_valid(status, edid_block_tag(block)))
2347 /* Fail early for unrepairable base block all zeros. */
2348 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2355 static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2356 read_block_fn read_block, void *context,
2359 enum edid_block_status status;
2360 int i, num_blocks, invalid_blocks = 0;
2361 const struct drm_edid *override;
2362 struct edid *edid, *new;
2363 size_t alloc_size = EDID_LENGTH;
2365 override = drm_edid_override_get(connector);
2367 alloc_size = override->size;
2368 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2369 drm_edid_free(override);
2375 edid = kmalloc(alloc_size, GFP_KERNEL);
2379 status = edid_block_read(edid, 0, read_block, context);
2381 edid_block_status_print(status, edid, 0);
2383 if (status == EDID_BLOCK_READ_FAIL)
2386 /* FIXME: Clarify what a corrupt EDID actually means. */
2387 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2388 connector->edid_corrupt = false;
2390 connector->edid_corrupt = true;
2392 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2393 if (status == EDID_BLOCK_ZERO)
2394 connector->null_edid_counter++;
2396 connector_bad_edid(connector, edid, 1);
2400 if (!edid_extension_block_count(edid))
2403 alloc_size = edid_size(edid);
2404 new = krealloc(edid, alloc_size, GFP_KERNEL);
2409 num_blocks = edid_block_count(edid);
2410 for (i = 1; i < num_blocks; i++) {
2411 void *block = (void *)edid_block_data(edid, i);
2413 status = edid_block_read(block, i, read_block, context);
2415 edid_block_status_print(status, block, i);
2417 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2418 if (status == EDID_BLOCK_READ_FAIL)
2421 } else if (i == 1) {
2423 * If the first EDID extension is a CTA extension, and
2424 * the first Data Block is HF-EEODB, override the
2425 * extension block count.
2427 * Note: HF-EEODB could specify a smaller extension
2428 * count too, but we can't risk allocating a smaller
2431 int eeodb = edid_hfeeodb_block_count(edid);
2433 if (eeodb > num_blocks) {
2435 alloc_size = edid_size_by_blocks(num_blocks);
2436 new = krealloc(edid, alloc_size, GFP_KERNEL);
2444 if (invalid_blocks) {
2445 connector_bad_edid(connector, edid, num_blocks);
2447 edid = edid_filter_invalid_blocks(edid, &alloc_size);
2462 * drm_do_get_edid - get EDID data using a custom EDID block read function
2463 * @connector: connector we're probing
2464 * @read_block: EDID block read function
2465 * @context: private data passed to the block read function
2467 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2468 * exposes a different interface to read EDID blocks this function can be used
2469 * to get EDID data using a custom block read function.
2471 * As in the general case the DDC bus is accessible by the kernel at the I2C
2472 * level, drivers must make all reasonable efforts to expose it as an I2C
2473 * adapter and use drm_get_edid() instead of abusing this function.
2475 * The EDID may be overridden using debugfs override_edid or firmware EDID
2476 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2477 * order. Having either of them bypasses actual EDID reads.
2479 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2481 struct edid *drm_do_get_edid(struct drm_connector *connector,
2482 read_block_fn read_block,
2485 return _drm_do_get_edid(connector, read_block, context, NULL);
2487 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2490 * drm_edid_raw - Get a pointer to the raw EDID data.
2491 * @drm_edid: drm_edid container
2493 * Get a pointer to the raw EDID data.
2495 * This is for transition only. Avoid using this like the plague.
2497 * Return: Pointer to raw EDID data.
2499 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2501 if (!drm_edid || !drm_edid->size)
2505 * Do not return pointers where relying on EDID extension count would
2506 * lead to buffer overflow.
2508 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2511 return drm_edid->edid;
2513 EXPORT_SYMBOL(drm_edid_raw);
2515 /* Allocate struct drm_edid container *without* duplicating the edid data */
2516 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2518 struct drm_edid *drm_edid;
2520 if (!edid || !size || size < EDID_LENGTH)
2523 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2525 drm_edid->edid = edid;
2526 drm_edid->size = size;
2533 * drm_edid_alloc - Allocate a new drm_edid container
2534 * @edid: Pointer to raw EDID data
2535 * @size: Size of memory allocated for EDID
2537 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2538 * the actual size that has been allocated for the data. There is no validation
2539 * of the raw EDID data against the size, but at least the EDID base block must
2540 * fit in the buffer.
2542 * The returned pointer must be freed using drm_edid_free().
2544 * Return: drm_edid container, or NULL on errors
2546 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2548 const struct drm_edid *drm_edid;
2550 if (!edid || !size || size < EDID_LENGTH)
2553 edid = kmemdup(edid, size, GFP_KERNEL);
2557 drm_edid = _drm_edid_alloc(edid, size);
2563 EXPORT_SYMBOL(drm_edid_alloc);
2566 * drm_edid_dup - Duplicate a drm_edid container
2567 * @drm_edid: EDID to duplicate
2569 * The returned pointer must be freed using drm_edid_free().
2571 * Returns: drm_edid container copy, or NULL on errors
2573 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2578 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2580 EXPORT_SYMBOL(drm_edid_dup);
2583 * drm_edid_free - Free the drm_edid container
2584 * @drm_edid: EDID to free
2586 void drm_edid_free(const struct drm_edid *drm_edid)
2591 kfree(drm_edid->edid);
2594 EXPORT_SYMBOL(drm_edid_free);
2597 * drm_probe_ddc() - probe DDC presence
2598 * @adapter: I2C adapter to probe
2600 * Return: True on success, false on failure.
2603 drm_probe_ddc(struct i2c_adapter *adapter)
2607 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2609 EXPORT_SYMBOL(drm_probe_ddc);
2612 * drm_get_edid - get EDID data, if available
2613 * @connector: connector we're probing
2614 * @adapter: I2C adapter to use for DDC
2616 * Poke the given I2C channel to grab EDID data if possible. If found,
2617 * attach it to the connector.
2619 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2621 struct edid *drm_get_edid(struct drm_connector *connector,
2622 struct i2c_adapter *adapter)
2626 if (connector->force == DRM_FORCE_OFF)
2629 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2632 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2633 drm_connector_update_edid_property(connector, edid);
2636 EXPORT_SYMBOL(drm_get_edid);
2639 * drm_edid_read_custom - Read EDID data using given EDID block read function
2640 * @connector: Connector to use
2641 * @read_block: EDID block read function
2642 * @context: Private data passed to the block read function
2644 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2645 * exposes a different interface to read EDID blocks this function can be used
2646 * to get EDID data using a custom block read function.
2648 * As in the general case the DDC bus is accessible by the kernel at the I2C
2649 * level, drivers must make all reasonable efforts to expose it as an I2C
2650 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2653 * The EDID may be overridden using debugfs override_edid or firmware EDID
2654 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2655 * order. Having either of them bypasses actual EDID reads.
2657 * The returned pointer must be freed using drm_edid_free().
2659 * Return: Pointer to EDID, or NULL if probe/read failed.
2661 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2662 read_block_fn read_block,
2665 const struct drm_edid *drm_edid;
2669 edid = _drm_do_get_edid(connector, read_block, context, &size);
2673 /* Sanity check for now */
2674 drm_WARN_ON(connector->dev, !size);
2676 drm_edid = _drm_edid_alloc(edid, size);
2682 EXPORT_SYMBOL(drm_edid_read_custom);
2685 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2686 * @connector: Connector to use
2687 * @adapter: I2C adapter to use for DDC
2689 * Read EDID using the given I2C adapter.
2691 * The EDID may be overridden using debugfs override_edid or firmware EDID
2692 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2693 * order. Having either of them bypasses actual EDID reads.
2695 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2696 * using drm_edid_read() instead of this function.
2698 * The returned pointer must be freed using drm_edid_free().
2700 * Return: Pointer to EDID, or NULL if probe/read failed.
2702 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2703 struct i2c_adapter *adapter)
2705 const struct drm_edid *drm_edid;
2707 if (connector->force == DRM_FORCE_OFF)
2710 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2713 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2715 /* Note: Do *not* call connector updates here. */
2719 EXPORT_SYMBOL(drm_edid_read_ddc);
2722 * drm_edid_read - Read EDID data using connector's I2C adapter
2723 * @connector: Connector to use
2725 * Read EDID using the connector's I2C adapter.
2727 * The EDID may be overridden using debugfs override_edid or firmware EDID
2728 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2729 * order. Having either of them bypasses actual EDID reads.
2731 * The returned pointer must be freed using drm_edid_free().
2733 * Return: Pointer to EDID, or NULL if probe/read failed.
2735 const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2737 if (drm_WARN_ON(connector->dev, !connector->ddc))
2740 return drm_edid_read_ddc(connector, connector->ddc);
2742 EXPORT_SYMBOL(drm_edid_read);
2744 static u32 edid_extract_panel_id(const struct edid *edid)
2747 * We represent the ID as a 32-bit number so it can easily be compared
2750 * NOTE that we deal with endianness differently for the top half
2751 * of this ID than for the bottom half. The bottom half (the product
2752 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2753 * that's how everyone seems to interpret it. The top half (the mfg_id)
2754 * gets stored as big endian because that makes
2755 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2756 * to write (it's easier to extract the ASCII). It doesn't really
2757 * matter, though, as long as the number here is unique.
2759 return (u32)edid->mfg_id[0] << 24 |
2760 (u32)edid->mfg_id[1] << 16 |
2761 (u32)EDID_PRODUCT_ID(edid);
2765 * drm_edid_get_panel_id - Get a panel's ID through DDC
2766 * @adapter: I2C adapter to use for DDC
2768 * This function reads the first block of the EDID of a panel and (assuming
2769 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2770 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2771 * supposed to be different for each different modem of panel.
2773 * This function is intended to be used during early probing on devices where
2774 * more than one panel might be present. Because of its intended use it must
2775 * assume that the EDID of the panel is correct, at least as far as the ID
2776 * is concerned (in other words, we don't process any overrides here).
2778 * NOTE: it's expected that this function and drm_do_get_edid() will both
2779 * be read the EDID, but there is no caching between them. Since we're only
2780 * reading the first block, hopefully this extra overhead won't be too big.
2782 * Return: A 32-bit ID that should be different for each make/model of panel.
2783 * See the functions drm_edid_encode_panel_id() and
2784 * drm_edid_decode_panel_id() for some details on the structure of this
2788 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2790 enum edid_block_status status;
2795 * There are no manufacturer IDs of 0, so if there is a problem reading
2796 * the EDID then we'll just return 0.
2799 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL);
2803 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2805 edid_block_status_print(status, base_block, 0);
2807 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2808 panel_id = edid_extract_panel_id(base_block);
2810 edid_block_dump(KERN_NOTICE, base_block, 0);
2816 EXPORT_SYMBOL(drm_edid_get_panel_id);
2819 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2820 * @connector: connector we're probing
2821 * @adapter: I2C adapter to use for DDC
2823 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2824 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2825 * switch DDC to the GPU which is retrieving EDID.
2827 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2829 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2830 struct i2c_adapter *adapter)
2832 struct drm_device *dev = connector->dev;
2833 struct pci_dev *pdev = to_pci_dev(dev->dev);
2836 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2839 vga_switcheroo_lock_ddc(pdev);
2840 edid = drm_get_edid(connector, adapter);
2841 vga_switcheroo_unlock_ddc(pdev);
2845 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2848 * drm_edid_duplicate - duplicate an EDID and the extensions
2849 * @edid: EDID to duplicate
2851 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2853 struct edid *drm_edid_duplicate(const struct edid *edid)
2855 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2857 EXPORT_SYMBOL(drm_edid_duplicate);
2859 /*** EDID parsing ***/
2862 * edid_get_quirks - return quirk flags for a given EDID
2863 * @drm_edid: EDID to process
2865 * This tells subsequent routines what fixes they need to apply.
2867 static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2869 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
2870 const struct edid_quirk *quirk;
2873 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2874 quirk = &edid_quirk_list[i];
2875 if (quirk->panel_id == panel_id)
2876 return quirk->quirks;
2882 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2883 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2886 * Walk the mode list for connector, clearing the preferred status on existing
2887 * modes and setting it anew for the right mode ala quirks.
2889 static void edid_fixup_preferred(struct drm_connector *connector)
2891 const struct drm_display_info *info = &connector->display_info;
2892 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2893 int target_refresh = 0;
2894 int cur_vrefresh, preferred_vrefresh;
2896 if (list_empty(&connector->probed_modes))
2899 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60)
2900 target_refresh = 60;
2901 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75)
2902 target_refresh = 75;
2904 preferred_mode = list_first_entry(&connector->probed_modes,
2905 struct drm_display_mode, head);
2907 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2908 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2910 if (cur_mode == preferred_mode)
2913 /* Largest mode is preferred */
2914 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2915 preferred_mode = cur_mode;
2917 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2918 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2919 /* At a given size, try to get closest to target refresh */
2920 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2921 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2922 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2923 preferred_mode = cur_mode;
2927 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2931 mode_is_rb(const struct drm_display_mode *mode)
2933 return (mode->htotal - mode->hdisplay == 160) &&
2934 (mode->hsync_end - mode->hdisplay == 80) &&
2935 (mode->hsync_end - mode->hsync_start == 32) &&
2936 (mode->vsync_start - mode->vdisplay == 3);
2940 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2941 * @dev: Device to duplicate against
2942 * @hsize: Mode width
2943 * @vsize: Mode height
2944 * @fresh: Mode refresh rate
2945 * @rb: Mode reduced-blanking-ness
2947 * Walk the DMT mode list looking for a match for the given parameters.
2949 * Return: A newly allocated copy of the mode, or NULL if not found.
2951 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2952 int hsize, int vsize, int fresh,
2957 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2958 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2960 if (hsize != ptr->hdisplay)
2962 if (vsize != ptr->vdisplay)
2964 if (fresh != drm_mode_vrefresh(ptr))
2966 if (rb != mode_is_rb(ptr))
2969 return drm_mode_duplicate(dev, ptr);
2974 EXPORT_SYMBOL(drm_mode_find_dmt);
2976 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
2978 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2979 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
2980 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
2982 return descriptor->pixel_clock == 0 &&
2983 descriptor->data.other_data.pad1 == 0 &&
2984 descriptor->data.other_data.type == type;
2987 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
2989 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2991 return descriptor->pixel_clock != 0;
2994 typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
2997 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3001 const u8 *det_base = ext + d;
3003 if (d < 4 || d > 127)
3007 for (i = 0; i < n; i++)
3008 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3012 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3014 unsigned int i, n = min((int)ext[0x02], 6);
3015 const u8 *det_base = ext + 5;
3018 return; /* unknown version */
3020 for (i = 0; i < n; i++)
3021 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3024 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3025 detailed_cb *cb, void *closure)
3027 struct drm_edid_iter edid_iter;
3034 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
3035 cb(&drm_edid->edid->detailed_timings[i], closure);
3037 drm_edid_iter_begin(drm_edid, &edid_iter);
3038 drm_edid_iter_for_each(ext, &edid_iter) {
3041 cea_for_each_detailed_block(ext, cb, closure);
3044 vtb_for_each_detailed_block(ext, cb, closure);
3050 drm_edid_iter_end(&edid_iter);
3054 is_rb(const struct detailed_timing *descriptor, void *data)
3058 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3061 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3062 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3064 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
3065 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
3069 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3071 drm_monitor_supports_rb(const struct drm_edid *drm_edid)
3073 if (drm_edid->edid->revision >= 4) {
3076 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
3080 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
3084 find_gtf2(const struct detailed_timing *descriptor, void *data)
3086 const struct detailed_timing **res = data;
3088 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3091 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3093 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
3097 /* Secondary GTF curve kicks in above some break frequency */
3099 drm_gtf2_hbreak(const struct drm_edid *drm_edid)
3101 const struct detailed_timing *descriptor = NULL;
3103 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3105 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3107 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
3111 drm_gtf2_2c(const struct drm_edid *drm_edid)
3113 const struct detailed_timing *descriptor = NULL;
3115 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3117 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
3119 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
3123 drm_gtf2_m(const struct drm_edid *drm_edid)
3125 const struct detailed_timing *descriptor = NULL;
3127 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3129 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3131 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3135 drm_gtf2_k(const struct drm_edid *drm_edid)
3137 const struct detailed_timing *descriptor = NULL;
3139 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3141 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3143 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3147 drm_gtf2_2j(const struct drm_edid *drm_edid)
3149 const struct detailed_timing *descriptor = NULL;
3151 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3153 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3155 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3159 get_timing_level(const struct detailed_timing *descriptor, void *data)
3163 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3166 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3168 switch (descriptor->data.other_data.data.range.flags) {
3169 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3172 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3175 case DRM_EDID_CVT_SUPPORT_FLAG:
3183 /* Get standard timing level (CVT/GTF/DMT). */
3184 static int standard_timing_level(const struct drm_edid *drm_edid)
3186 const struct edid *edid = drm_edid->edid;
3188 if (edid->revision >= 4) {
3190 * If the range descriptor doesn't
3191 * indicate otherwise default to CVT
3193 int ret = LEVEL_CVT;
3195 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3198 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3200 } else if (edid->revision >= 2) {
3208 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3209 * monitors fill with ascii space (0x20) instead.
3212 bad_std_timing(u8 a, u8 b)
3214 return (a == 0x00 && b == 0x00) ||
3215 (a == 0x01 && b == 0x01) ||
3216 (a == 0x20 && b == 0x20);
3219 static int drm_mode_hsync(const struct drm_display_mode *mode)
3221 if (mode->htotal <= 0)
3224 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3227 static struct drm_display_mode *
3228 drm_gtf2_mode(struct drm_device *dev,
3229 const struct drm_edid *drm_edid,
3230 int hsize, int vsize, int vrefresh_rate)
3232 struct drm_display_mode *mode;
3235 * This is potentially wrong if there's ever a monitor with
3236 * more than one ranges section, each claiming a different
3237 * secondary GTF curve. Please don't do that.
3239 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3243 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3244 drm_mode_destroy(dev, mode);
3245 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3246 vrefresh_rate, 0, 0,
3247 drm_gtf2_m(drm_edid),
3248 drm_gtf2_2c(drm_edid),
3249 drm_gtf2_k(drm_edid),
3250 drm_gtf2_2j(drm_edid));
3257 * Take the standard timing params (in this case width, aspect, and refresh)
3258 * and convert them into a real mode using CVT/GTF/DMT.
3260 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3261 const struct drm_edid *drm_edid,
3262 const struct std_timing *t)
3264 struct drm_device *dev = connector->dev;
3265 struct drm_display_mode *m, *mode = NULL;
3268 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3269 >> EDID_TIMING_ASPECT_SHIFT;
3270 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3271 >> EDID_TIMING_VFREQ_SHIFT;
3272 int timing_level = standard_timing_level(drm_edid);
3274 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3277 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3278 hsize = t->hsize * 8 + 248;
3279 /* vrefresh_rate = vfreq + 60 */
3280 vrefresh_rate = vfreq + 60;
3281 /* the vdisplay is calculated based on the aspect ratio */
3282 if (aspect_ratio == 0) {
3283 if (drm_edid->edid->revision < 3)
3286 vsize = (hsize * 10) / 16;
3287 } else if (aspect_ratio == 1)
3288 vsize = (hsize * 3) / 4;
3289 else if (aspect_ratio == 2)
3290 vsize = (hsize * 4) / 5;
3292 vsize = (hsize * 9) / 16;
3294 /* HDTV hack, part 1 */
3295 if (vrefresh_rate == 60 &&
3296 ((hsize == 1360 && vsize == 765) ||
3297 (hsize == 1368 && vsize == 769))) {
3303 * If this connector already has a mode for this size and refresh
3304 * rate (because it came from detailed or CVT info), use that
3305 * instead. This way we don't have to guess at interlace or
3308 list_for_each_entry(m, &connector->probed_modes, head)
3309 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3310 drm_mode_vrefresh(m) == vrefresh_rate)
3313 /* HDTV hack, part 2 */
3314 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3315 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3319 mode->hdisplay = 1366;
3320 mode->hsync_start = mode->hsync_start - 1;
3321 mode->hsync_end = mode->hsync_end - 1;
3325 /* check whether it can be found in default mode table */
3326 if (drm_monitor_supports_rb(drm_edid)) {
3327 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3332 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3336 /* okay, generate it */
3337 switch (timing_level) {
3341 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3344 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
3347 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3355 * EDID is delightfully ambiguous about how interlaced modes are to be
3356 * encoded. Our internal representation is of frame height, but some
3357 * HDTV detailed timings are encoded as field height.
3359 * The format list here is from CEA, in frame size. Technically we
3360 * should be checking refresh rate too. Whatever.
3363 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3364 const struct detailed_pixel_timing *pt)
3367 static const struct {
3369 } cea_interlaced[] = {
3379 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3382 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3383 if ((mode->hdisplay == cea_interlaced[i].w) &&
3384 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3385 mode->vdisplay *= 2;
3386 mode->vsync_start *= 2;
3387 mode->vsync_end *= 2;
3393 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3397 * Create a new mode from an EDID detailed timing section. An EDID detailed
3398 * timing block contains enough info for us to create and return a new struct
3401 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
3402 const struct drm_edid *drm_edid,
3403 const struct detailed_timing *timing)
3405 const struct drm_display_info *info = &connector->display_info;
3406 struct drm_device *dev = connector->dev;
3407 struct drm_display_mode *mode;
3408 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3409 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3410 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3411 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3412 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3413 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3414 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3415 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3416 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3418 /* ignore tiny modes */
3419 if (hactive < 64 || vactive < 64)
3422 if (pt->misc & DRM_EDID_PT_STEREO) {
3423 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3424 connector->base.id, connector->name);
3427 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3428 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n",
3429 connector->base.id, connector->name);
3432 /* it is incorrect if hsync/vsync width is zero */
3433 if (!hsync_pulse_width || !vsync_pulse_width) {
3434 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3435 connector->base.id, connector->name);
3439 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3440 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3447 mode = drm_mode_create(dev);
3451 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3452 mode->clock = 1088 * 10;
3454 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3456 mode->hdisplay = hactive;
3457 mode->hsync_start = mode->hdisplay + hsync_offset;
3458 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3459 mode->htotal = mode->hdisplay + hblank;
3461 mode->vdisplay = vactive;
3462 mode->vsync_start = mode->vdisplay + vsync_offset;
3463 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3464 mode->vtotal = mode->vdisplay + vblank;
3466 /* Some EDIDs have bogus h/vtotal values */
3467 if (mode->hsync_end > mode->htotal)
3468 mode->htotal = mode->hsync_end + 1;
3469 if (mode->vsync_end > mode->vtotal)
3470 mode->vtotal = mode->vsync_end + 1;
3472 drm_mode_do_interlace_quirk(mode, pt);
3474 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3475 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3477 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3478 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3479 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3480 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3484 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3485 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3487 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) {
3488 mode->width_mm *= 10;
3489 mode->height_mm *= 10;
3492 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3493 mode->width_mm = drm_edid->edid->width_cm * 10;
3494 mode->height_mm = drm_edid->edid->height_cm * 10;
3497 mode->type = DRM_MODE_TYPE_DRIVER;
3498 drm_mode_set_name(mode);
3504 mode_in_hsync_range(const struct drm_display_mode *mode,
3505 const struct edid *edid, const u8 *t)
3507 int hsync, hmin, hmax;
3510 if (edid->revision >= 4)
3511 hmin += ((t[4] & 0x04) ? 255 : 0);
3513 if (edid->revision >= 4)
3514 hmax += ((t[4] & 0x08) ? 255 : 0);
3515 hsync = drm_mode_hsync(mode);
3517 return (hsync <= hmax && hsync >= hmin);
3521 mode_in_vsync_range(const struct drm_display_mode *mode,
3522 const struct edid *edid, const u8 *t)
3524 int vsync, vmin, vmax;
3527 if (edid->revision >= 4)
3528 vmin += ((t[4] & 0x01) ? 255 : 0);
3530 if (edid->revision >= 4)
3531 vmax += ((t[4] & 0x02) ? 255 : 0);
3532 vsync = drm_mode_vrefresh(mode);
3534 return (vsync <= vmax && vsync >= vmin);
3538 range_pixel_clock(const struct edid *edid, const u8 *t)
3541 if (t[9] == 0 || t[9] == 255)
3544 /* 1.4 with CVT support gives us real precision, yay */
3545 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3546 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3548 /* 1.3 is pathetic, so fuzz up a bit */
3549 return t[9] * 10000 + 5001;
3552 static bool mode_in_range(const struct drm_display_mode *mode,
3553 const struct drm_edid *drm_edid,
3554 const struct detailed_timing *timing)
3556 const struct edid *edid = drm_edid->edid;
3558 const u8 *t = (const u8 *)timing;
3560 if (!mode_in_hsync_range(mode, edid, t))
3563 if (!mode_in_vsync_range(mode, edid, t))
3566 if ((max_clock = range_pixel_clock(edid, t)))
3567 if (mode->clock > max_clock)
3570 /* 1.4 max horizontal check */
3571 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3572 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3575 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3581 static bool valid_inferred_mode(const struct drm_connector *connector,
3582 const struct drm_display_mode *mode)
3584 const struct drm_display_mode *m;
3587 list_for_each_entry(m, &connector->probed_modes, head) {
3588 if (mode->hdisplay == m->hdisplay &&
3589 mode->vdisplay == m->vdisplay &&
3590 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3591 return false; /* duplicated */
3592 if (mode->hdisplay <= m->hdisplay &&
3593 mode->vdisplay <= m->vdisplay)
3599 static int drm_dmt_modes_for_range(struct drm_connector *connector,
3600 const struct drm_edid *drm_edid,
3601 const struct detailed_timing *timing)
3604 struct drm_display_mode *newmode;
3605 struct drm_device *dev = connector->dev;
3607 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3608 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3609 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3610 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3612 drm_mode_probed_add(connector, newmode);
3621 /* fix up 1366x768 mode from 1368x768;
3622 * GFT/CVT can't express 1366 width which isn't dividable by 8
3624 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3626 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3627 mode->hdisplay = 1366;
3628 mode->hsync_start--;
3630 drm_mode_set_name(mode);
3634 static int drm_gtf_modes_for_range(struct drm_connector *connector,
3635 const struct drm_edid *drm_edid,
3636 const struct detailed_timing *timing)
3639 struct drm_display_mode *newmode;
3640 struct drm_device *dev = connector->dev;
3642 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3643 const struct minimode *m = &extra_modes[i];
3645 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3649 drm_mode_fixup_1366x768(newmode);
3650 if (!mode_in_range(newmode, drm_edid, timing) ||
3651 !valid_inferred_mode(connector, newmode)) {
3652 drm_mode_destroy(dev, newmode);
3656 drm_mode_probed_add(connector, newmode);
3663 static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3664 const struct drm_edid *drm_edid,
3665 const struct detailed_timing *timing)
3668 struct drm_display_mode *newmode;
3669 struct drm_device *dev = connector->dev;
3671 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3672 const struct minimode *m = &extra_modes[i];
3674 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3678 drm_mode_fixup_1366x768(newmode);
3679 if (!mode_in_range(newmode, drm_edid, timing) ||
3680 !valid_inferred_mode(connector, newmode)) {
3681 drm_mode_destroy(dev, newmode);
3685 drm_mode_probed_add(connector, newmode);
3692 static int drm_cvt_modes_for_range(struct drm_connector *connector,
3693 const struct drm_edid *drm_edid,
3694 const struct detailed_timing *timing)
3697 struct drm_display_mode *newmode;
3698 struct drm_device *dev = connector->dev;
3699 bool rb = drm_monitor_supports_rb(drm_edid);
3701 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3702 const struct minimode *m = &extra_modes[i];
3704 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3708 drm_mode_fixup_1366x768(newmode);
3709 if (!mode_in_range(newmode, drm_edid, timing) ||
3710 !valid_inferred_mode(connector, newmode)) {
3711 drm_mode_destroy(dev, newmode);
3715 drm_mode_probed_add(connector, newmode);
3723 do_inferred_modes(const struct detailed_timing *timing, void *c)
3725 struct detailed_mode_closure *closure = c;
3726 const struct detailed_non_pixel *data = &timing->data.other_data;
3727 const struct detailed_data_monitor_range *range = &data->data.range;
3729 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3732 closure->modes += drm_dmt_modes_for_range(closure->connector,
3736 if (closure->drm_edid->edid->revision < 2)
3737 return; /* GTF not defined yet */
3739 switch (range->flags) {
3740 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3741 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3745 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3746 closure->modes += drm_gtf_modes_for_range(closure->connector,
3750 case DRM_EDID_CVT_SUPPORT_FLAG:
3751 if (closure->drm_edid->edid->revision < 4)
3754 closure->modes += drm_cvt_modes_for_range(closure->connector,
3758 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
3764 static int add_inferred_modes(struct drm_connector *connector,
3765 const struct drm_edid *drm_edid)
3767 struct detailed_mode_closure closure = {
3768 .connector = connector,
3769 .drm_edid = drm_edid,
3772 if (drm_edid->edid->revision >= 1)
3773 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3775 return closure.modes;
3779 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3781 int i, j, m, modes = 0;
3782 struct drm_display_mode *mode;
3783 const u8 *est = ((const u8 *)timing) + 6;
3785 for (i = 0; i < 6; i++) {
3786 for (j = 7; j >= 0; j--) {
3787 m = (i * 8) + (7 - j);
3788 if (m >= ARRAY_SIZE(est3_modes))
3790 if (est[i] & (1 << j)) {
3791 mode = drm_mode_find_dmt(connector->dev,
3797 drm_mode_probed_add(connector, mode);
3808 do_established_modes(const struct detailed_timing *timing, void *c)
3810 struct detailed_mode_closure *closure = c;
3812 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3815 closure->modes += drm_est3_modes(closure->connector, timing);
3819 * Get established modes from EDID and add them. Each EDID block contains a
3820 * bitmap of the supported "established modes" list (defined above). Tease them
3821 * out and add them to the global modes list.
3823 static int add_established_modes(struct drm_connector *connector,
3824 const struct drm_edid *drm_edid)
3826 struct drm_device *dev = connector->dev;
3827 const struct edid *edid = drm_edid->edid;
3828 unsigned long est_bits = edid->established_timings.t1 |
3829 (edid->established_timings.t2 << 8) |
3830 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3832 struct detailed_mode_closure closure = {
3833 .connector = connector,
3834 .drm_edid = drm_edid,
3837 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3838 if (est_bits & (1<<i)) {
3839 struct drm_display_mode *newmode;
3841 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3843 drm_mode_probed_add(connector, newmode);
3849 if (edid->revision >= 1)
3850 drm_for_each_detailed_block(drm_edid, do_established_modes,
3853 return modes + closure.modes;
3857 do_standard_modes(const struct detailed_timing *timing, void *c)
3859 struct detailed_mode_closure *closure = c;
3860 const struct detailed_non_pixel *data = &timing->data.other_data;
3861 struct drm_connector *connector = closure->connector;
3864 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3867 for (i = 0; i < 6; i++) {
3868 const struct std_timing *std = &data->data.timings[i];
3869 struct drm_display_mode *newmode;
3871 newmode = drm_mode_std(connector, closure->drm_edid, std);
3873 drm_mode_probed_add(connector, newmode);
3880 * Get standard modes from EDID and add them. Standard modes can be calculated
3881 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3882 * add them to the list.
3884 static int add_standard_modes(struct drm_connector *connector,
3885 const struct drm_edid *drm_edid)
3888 struct detailed_mode_closure closure = {
3889 .connector = connector,
3890 .drm_edid = drm_edid,
3893 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3894 struct drm_display_mode *newmode;
3896 newmode = drm_mode_std(connector, drm_edid,
3897 &drm_edid->edid->standard_timings[i]);
3899 drm_mode_probed_add(connector, newmode);
3904 if (drm_edid->edid->revision >= 1)
3905 drm_for_each_detailed_block(drm_edid, do_standard_modes,
3908 /* XXX should also look for standard codes in VTB blocks */
3910 return modes + closure.modes;
3913 static int drm_cvt_modes(struct drm_connector *connector,
3914 const struct detailed_timing *timing)
3916 int i, j, modes = 0;
3917 struct drm_display_mode *newmode;
3918 struct drm_device *dev = connector->dev;
3919 const struct cvt_timing *cvt;
3920 const int rates[] = { 60, 85, 75, 60, 50 };
3921 const u8 empty[3] = { 0, 0, 0 };
3923 for (i = 0; i < 4; i++) {
3926 cvt = &(timing->data.other_data.data.cvt[i]);
3928 if (!memcmp(cvt->code, empty, 3))
3931 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3932 switch (cvt->code[1] & 0x0c) {
3933 /* default - because compiler doesn't see that we've enumerated all cases */
3936 width = height * 4 / 3;
3939 width = height * 16 / 9;
3942 width = height * 16 / 10;
3945 width = height * 15 / 9;
3949 for (j = 1; j < 5; j++) {
3950 if (cvt->code[2] & (1 << j)) {
3951 newmode = drm_cvt_mode(dev, width, height,
3955 drm_mode_probed_add(connector, newmode);
3966 do_cvt_mode(const struct detailed_timing *timing, void *c)
3968 struct detailed_mode_closure *closure = c;
3970 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
3973 closure->modes += drm_cvt_modes(closure->connector, timing);
3977 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
3979 struct detailed_mode_closure closure = {
3980 .connector = connector,
3981 .drm_edid = drm_edid,
3984 if (drm_edid->edid->revision >= 3)
3985 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
3987 /* XXX should also look for CVT codes in VTB blocks */
3989 return closure.modes;
3992 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
3993 struct drm_display_mode *mode);
3996 do_detailed_mode(const struct detailed_timing *timing, void *c)
3998 struct detailed_mode_closure *closure = c;
3999 struct drm_display_mode *newmode;
4001 if (!is_detailed_timing_descriptor(timing))
4004 newmode = drm_mode_detailed(closure->connector,
4005 closure->drm_edid, timing);
4009 if (closure->preferred)
4010 newmode->type |= DRM_MODE_TYPE_PREFERRED;
4013 * Detailed modes are limited to 10kHz pixel clock resolution,
4014 * so fix up anything that looks like CEA/HDMI mode, but the clock
4015 * is just slightly off.
4017 fixup_detailed_cea_mode_clock(closure->connector, newmode);
4019 drm_mode_probed_add(closure->connector, newmode);
4021 closure->preferred = false;
4025 * add_detailed_modes - Add modes from detailed timings
4026 * @connector: attached connector
4027 * @drm_edid: EDID block to scan
4029 static int add_detailed_modes(struct drm_connector *connector,
4030 const struct drm_edid *drm_edid)
4032 struct detailed_mode_closure closure = {
4033 .connector = connector,
4034 .drm_edid = drm_edid,
4037 if (drm_edid->edid->revision >= 4)
4038 closure.preferred = true; /* first detailed timing is always preferred */
4041 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
4043 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
4045 return closure.modes;
4048 /* CTA-861-H Table 60 - CTA Tag Codes */
4049 #define CTA_DB_AUDIO 1
4050 #define CTA_DB_VIDEO 2
4051 #define CTA_DB_VENDOR 3
4052 #define CTA_DB_SPEAKER 4
4053 #define CTA_DB_EXTENDED_TAG 7
4055 /* CTA-861-H Table 62 - CTA Extended Tag Codes */
4056 #define CTA_EXT_DB_VIDEO_CAP 0
4057 #define CTA_EXT_DB_VENDOR 1
4058 #define CTA_EXT_DB_HDR_STATIC_METADATA 6
4059 #define CTA_EXT_DB_420_VIDEO_DATA 14
4060 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
4061 #define CTA_EXT_DB_HF_EEODB 0x78
4062 #define CTA_EXT_DB_HF_SCDB 0x79
4064 #define EDID_BASIC_AUDIO (1 << 6)
4065 #define EDID_CEA_YCRCB444 (1 << 5)
4066 #define EDID_CEA_YCRCB422 (1 << 4)
4067 #define EDID_CEA_VCDB_QS (1 << 6)
4070 * Search EDID for CEA extension block.
4072 * FIXME: Prefer not returning pointers to raw EDID data.
4074 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
4075 int ext_id, int *ext_index)
4077 const u8 *edid_ext = NULL;
4080 /* No EDID or EDID extensions */
4081 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
4084 /* Find CEA extension */
4085 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4086 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4087 if (edid_block_tag(edid_ext) == ext_id)
4091 if (i >= drm_edid_extension_block_count(drm_edid))
4099 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
4100 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
4102 const struct displayid_block *block;
4103 struct displayid_iter iter;
4107 /* Look for a top level CEA extension block */
4108 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
4111 /* CEA blocks can also be found embedded in a DisplayID block */
4112 displayid_iter_edid_begin(drm_edid, &iter);
4113 displayid_iter_for_each(block, &iter) {
4114 if (block->tag == DATA_BLOCK_CTA) {
4119 displayid_iter_end(&iter);
4124 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
4126 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4127 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4129 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4130 return &edid_cea_modes_1[vic - 1];
4131 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4132 return &edid_cea_modes_193[vic - 193];
4136 static u8 cea_num_vics(void)
4138 return 193 + ARRAY_SIZE(edid_cea_modes_193);
4141 static u8 cea_next_vic(u8 vic)
4143 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
4149 * Calculate the alternate clock for the CEA mode
4150 * (60Hz vs. 59.94Hz etc.)
4153 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4155 unsigned int clock = cea_mode->clock;
4157 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
4161 * edid_cea_modes contains the 59.94Hz
4162 * variant for 240 and 480 line modes,
4163 * and the 60Hz variant otherwise.
4165 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
4166 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4168 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4174 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4177 * For certain VICs the spec allows the vertical
4178 * front porch to vary by one or two lines.
4180 * cea_modes[] stores the variant with the shortest
4181 * vertical front porch. We can adjust the mode to
4182 * get the other variants by simply increasing the
4183 * vertical front porch length.
4185 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4186 cea_mode_for_vic(9)->vtotal != 262 ||
4187 cea_mode_for_vic(12)->vtotal != 262 ||
4188 cea_mode_for_vic(13)->vtotal != 262 ||
4189 cea_mode_for_vic(23)->vtotal != 312 ||
4190 cea_mode_for_vic(24)->vtotal != 312 ||
4191 cea_mode_for_vic(27)->vtotal != 312 ||
4192 cea_mode_for_vic(28)->vtotal != 312);
4194 if (((vic == 8 || vic == 9 ||
4195 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4196 ((vic == 23 || vic == 24 ||
4197 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4198 mode->vsync_start++;
4208 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4209 unsigned int clock_tolerance)
4211 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4214 if (!to_match->clock)
4217 if (to_match->picture_aspect_ratio)
4218 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4220 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4221 struct drm_display_mode cea_mode;
4222 unsigned int clock1, clock2;
4224 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4226 /* Check both 60Hz and 59.94Hz */
4227 clock1 = cea_mode.clock;
4228 clock2 = cea_mode_alternate_clock(&cea_mode);
4230 if (abs(to_match->clock - clock1) > clock_tolerance &&
4231 abs(to_match->clock - clock2) > clock_tolerance)
4235 if (drm_mode_match(to_match, &cea_mode, match_flags))
4237 } while (cea_mode_alternate_timings(vic, &cea_mode));
4244 * drm_match_cea_mode - look for a CEA mode matching given mode
4245 * @to_match: display mode
4247 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4250 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4252 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4255 if (!to_match->clock)
4258 if (to_match->picture_aspect_ratio)
4259 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4261 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4262 struct drm_display_mode cea_mode;
4263 unsigned int clock1, clock2;
4265 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4267 /* Check both 60Hz and 59.94Hz */
4268 clock1 = cea_mode.clock;
4269 clock2 = cea_mode_alternate_clock(&cea_mode);
4271 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4272 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4276 if (drm_mode_match(to_match, &cea_mode, match_flags))
4278 } while (cea_mode_alternate_timings(vic, &cea_mode));
4283 EXPORT_SYMBOL(drm_match_cea_mode);
4285 static bool drm_valid_cea_vic(u8 vic)
4287 return cea_mode_for_vic(vic) != NULL;
4290 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4292 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4295 return mode->picture_aspect_ratio;
4297 return HDMI_PICTURE_ASPECT_NONE;
4300 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4302 return edid_4k_modes[video_code].picture_aspect_ratio;
4306 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4310 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4312 return cea_mode_alternate_clock(hdmi_mode);
4315 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4316 unsigned int clock_tolerance)
4318 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4321 if (!to_match->clock)
4324 if (to_match->picture_aspect_ratio)
4325 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4327 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4328 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4329 unsigned int clock1, clock2;
4331 /* Make sure to also match alternate clocks */
4332 clock1 = hdmi_mode->clock;
4333 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4335 if (abs(to_match->clock - clock1) > clock_tolerance &&
4336 abs(to_match->clock - clock2) > clock_tolerance)
4339 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4347 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4348 * @to_match: display mode
4350 * An HDMI mode is one defined in the HDMI vendor specific block.
4352 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4354 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4356 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4359 if (!to_match->clock)
4362 if (to_match->picture_aspect_ratio)
4363 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4365 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4366 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4367 unsigned int clock1, clock2;
4369 /* Make sure to also match alternate clocks */
4370 clock1 = hdmi_mode->clock;
4371 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4373 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4374 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4375 drm_mode_match(to_match, hdmi_mode, match_flags))
4381 static bool drm_valid_hdmi_vic(u8 vic)
4383 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4386 static int add_alternate_cea_modes(struct drm_connector *connector,
4387 const struct drm_edid *drm_edid)
4389 struct drm_device *dev = connector->dev;
4390 struct drm_display_mode *mode, *tmp;
4394 /* Don't add CTA modes if the CTA extension block is missing */
4395 if (!drm_edid_has_cta_extension(drm_edid))
4399 * Go through all probed modes and create a new mode
4400 * with the alternate clock for certain CEA modes.
4402 list_for_each_entry(mode, &connector->probed_modes, head) {
4403 const struct drm_display_mode *cea_mode = NULL;
4404 struct drm_display_mode *newmode;
4405 u8 vic = drm_match_cea_mode(mode);
4406 unsigned int clock1, clock2;
4408 if (drm_valid_cea_vic(vic)) {
4409 cea_mode = cea_mode_for_vic(vic);
4410 clock2 = cea_mode_alternate_clock(cea_mode);
4412 vic = drm_match_hdmi_mode(mode);
4413 if (drm_valid_hdmi_vic(vic)) {
4414 cea_mode = &edid_4k_modes[vic];
4415 clock2 = hdmi_mode_alternate_clock(cea_mode);
4422 clock1 = cea_mode->clock;
4424 if (clock1 == clock2)
4427 if (mode->clock != clock1 && mode->clock != clock2)
4430 newmode = drm_mode_duplicate(dev, cea_mode);
4434 /* Carry over the stereo flags */
4435 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4438 * The current mode could be either variant. Make
4439 * sure to pick the "other" clock for the new mode.
4441 if (mode->clock != clock1)
4442 newmode->clock = clock1;
4444 newmode->clock = clock2;
4446 list_add_tail(&newmode->head, &list);
4449 list_for_each_entry_safe(mode, tmp, &list, head) {
4450 list_del(&mode->head);
4451 drm_mode_probed_add(connector, mode);
4458 static u8 svd_to_vic(u8 svd)
4460 /* 0-6 bit vic, 7th bit native mode indicator */
4461 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4468 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in
4469 * the EDID, or NULL on errors.
4471 static struct drm_display_mode *
4472 drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index)
4474 const struct drm_display_info *info = &connector->display_info;
4475 struct drm_device *dev = connector->dev;
4477 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index])
4480 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]);
4484 * do_y420vdb_modes - Parse YCBCR 420 only modes
4485 * @connector: connector corresponding to the HDMI sink
4486 * @svds: start of the data block of CEA YCBCR 420 VDB
4487 * @len: length of the CEA YCBCR 420 VDB
4489 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4490 * which contains modes which can be supported in YCBCR 420
4491 * output format only.
4493 static int do_y420vdb_modes(struct drm_connector *connector,
4494 const u8 *svds, u8 svds_len)
4496 struct drm_device *dev = connector->dev;
4499 for (i = 0; i < svds_len; i++) {
4500 u8 vic = svd_to_vic(svds[i]);
4501 struct drm_display_mode *newmode;
4503 if (!drm_valid_cea_vic(vic))
4506 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4509 drm_mode_probed_add(connector, newmode);
4517 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4519 * @video_code: CEA VIC of the mode
4521 * Creates a new mode matching the specified CEA VIC.
4523 * Returns: A new drm_display_mode on success or NULL on failure
4525 struct drm_display_mode *
4526 drm_display_mode_from_cea_vic(struct drm_device *dev,
4529 const struct drm_display_mode *cea_mode;
4530 struct drm_display_mode *newmode;
4532 cea_mode = cea_mode_for_vic(video_code);
4536 newmode = drm_mode_duplicate(dev, cea_mode);
4542 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4544 /* Add modes based on VICs parsed in parse_cta_vdb() */
4545 static int add_cta_vdb_modes(struct drm_connector *connector)
4547 const struct drm_display_info *info = &connector->display_info;
4553 for (i = 0; i < info->vics_len; i++) {
4554 struct drm_display_mode *mode;
4556 mode = drm_display_mode_from_vic_index(connector, i);
4558 drm_mode_probed_add(connector, mode);
4566 struct stereo_mandatory_mode {
4567 int width, height, vrefresh;
4571 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4572 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4573 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4575 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4577 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4578 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4579 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4580 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4581 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4585 stereo_match_mandatory(const struct drm_display_mode *mode,
4586 const struct stereo_mandatory_mode *stereo_mode)
4588 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4590 return mode->hdisplay == stereo_mode->width &&
4591 mode->vdisplay == stereo_mode->height &&
4592 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4593 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4596 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4598 struct drm_device *dev = connector->dev;
4599 const struct drm_display_mode *mode;
4600 struct list_head stereo_modes;
4603 INIT_LIST_HEAD(&stereo_modes);
4605 list_for_each_entry(mode, &connector->probed_modes, head) {
4606 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4607 const struct stereo_mandatory_mode *mandatory;
4608 struct drm_display_mode *new_mode;
4610 if (!stereo_match_mandatory(mode,
4611 &stereo_mandatory_modes[i]))
4614 mandatory = &stereo_mandatory_modes[i];
4615 new_mode = drm_mode_duplicate(dev, mode);
4619 new_mode->flags |= mandatory->flags;
4620 list_add_tail(&new_mode->head, &stereo_modes);
4625 list_splice_tail(&stereo_modes, &connector->probed_modes);
4630 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4632 struct drm_device *dev = connector->dev;
4633 struct drm_display_mode *newmode;
4635 if (!drm_valid_hdmi_vic(vic)) {
4636 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4637 connector->base.id, connector->name, vic);
4641 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4645 drm_mode_probed_add(connector, newmode);
4650 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4653 struct drm_display_mode *newmode;
4656 if (structure & (1 << 0)) {
4657 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4659 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4660 drm_mode_probed_add(connector, newmode);
4664 if (structure & (1 << 6)) {
4665 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4667 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4668 drm_mode_probed_add(connector, newmode);
4672 if (structure & (1 << 8)) {
4673 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4675 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4676 drm_mode_probed_add(connector, newmode);
4684 static bool hdmi_vsdb_latency_present(const u8 *db)
4686 return db[8] & BIT(7);
4689 static bool hdmi_vsdb_i_latency_present(const u8 *db)
4691 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6);
4694 static int hdmi_vsdb_latency_length(const u8 *db)
4696 if (hdmi_vsdb_i_latency_present(db))
4698 else if (hdmi_vsdb_latency_present(db))
4705 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4706 * @connector: connector corresponding to the HDMI sink
4707 * @db: start of the CEA vendor specific block
4708 * @len: length of the CEA block payload, ie. one can access up to db[len]
4710 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4711 * also adds the stereo 3d modes when applicable.
4714 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
4716 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4717 u8 vic_len, hdmi_3d_len = 0;
4724 /* no HDMI_Video_Present */
4725 if (!(db[8] & (1 << 5)))
4728 offset += hdmi_vsdb_latency_length(db);
4730 /* the declared length is not long enough for the 2 first bytes
4731 * of additional video format capabilities */
4732 if (len < (8 + offset + 2))
4737 if (db[8 + offset] & (1 << 7)) {
4738 modes += add_hdmi_mandatory_stereo_modes(connector);
4740 /* 3D_Multi_present */
4741 multi_present = (db[8 + offset] & 0x60) >> 5;
4745 vic_len = db[8 + offset] >> 5;
4746 hdmi_3d_len = db[8 + offset] & 0x1f;
4748 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4751 vic = db[9 + offset + i];
4752 modes += add_hdmi_mode(connector, vic);
4754 offset += 1 + vic_len;
4756 if (multi_present == 1)
4758 else if (multi_present == 2)
4763 if (len < (8 + offset + hdmi_3d_len - 1))
4766 if (hdmi_3d_len < multi_len)
4769 if (multi_present == 1 || multi_present == 2) {
4770 /* 3D_Structure_ALL */
4771 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4773 /* check if 3D_MASK is present */
4774 if (multi_present == 2)
4775 mask = (db[10 + offset] << 8) | db[11 + offset];
4779 for (i = 0; i < 16; i++) {
4780 if (mask & (1 << i))
4781 modes += add_3d_struct_modes(connector,
4786 offset += multi_len;
4788 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4790 struct drm_display_mode *newmode = NULL;
4791 unsigned int newflag = 0;
4792 bool detail_present;
4794 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4796 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4799 /* 2D_VIC_order_X */
4800 vic_index = db[8 + offset + i] >> 4;
4802 /* 3D_Structure_X */
4803 switch (db[8 + offset + i] & 0x0f) {
4805 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4808 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4812 if ((db[9 + offset + i] >> 4) == 1)
4813 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4818 newmode = drm_display_mode_from_vic_index(connector,
4822 newmode->flags |= newflag;
4823 drm_mode_probed_add(connector, newmode);
4837 cea_revision(const u8 *cea)
4840 * FIXME is this correct for the DispID variant?
4841 * The DispID spec doesn't really specify whether
4842 * this is the revision of the CEA extension or
4843 * the DispID CEA data block. And the only value
4844 * given as an example is 0.
4850 * CTA Data Block iterator.
4852 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4855 * struct cea_db *db:
4856 * struct cea_db_iter iter;
4858 * cea_db_iter_edid_begin(edid, &iter);
4859 * cea_db_iter_for_each(db, &iter) {
4860 * // do stuff with db
4862 * cea_db_iter_end(&iter);
4864 struct cea_db_iter {
4865 struct drm_edid_iter edid_iter;
4866 struct displayid_iter displayid_iter;
4868 /* Current Data Block Collection. */
4869 const u8 *collection;
4871 /* Current Data Block index in current collection. */
4874 /* End index in current collection. */
4878 /* CTA-861-H section 7.4 CTA Data BLock Collection */
4884 static int cea_db_tag(const struct cea_db *db)
4886 return db->tag_length >> 5;
4889 static int cea_db_payload_len(const void *_db)
4891 /* FIXME: Transition to passing struct cea_db * everywhere. */
4892 const struct cea_db *db = _db;
4894 return db->tag_length & 0x1f;
4897 static const void *cea_db_data(const struct cea_db *db)
4902 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4904 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4905 cea_db_payload_len(db) >= 1 &&
4909 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4911 const u8 *data = cea_db_data(db);
4913 return cea_db_tag(db) == CTA_DB_VENDOR &&
4914 cea_db_payload_len(db) >= 3 &&
4915 oui(data[2], data[1], data[0]) == vendor_oui;
4918 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4919 struct cea_db_iter *iter)
4921 memset(iter, 0, sizeof(*iter));
4923 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
4924 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
4927 static const struct cea_db *
4928 __cea_db_iter_current_block(const struct cea_db_iter *iter)
4930 const struct cea_db *db;
4932 if (!iter->collection)
4935 db = (const struct cea_db *)&iter->collection[iter->index];
4937 if (iter->index + sizeof(*db) <= iter->end &&
4938 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4946 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4948 static int cea_db_collection_size(const u8 *cta)
4952 if (d < 4 || d > 127)
4960 * - VESA E-EDID v1.4
4961 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4963 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
4967 drm_edid_iter_for_each(ext, &iter->edid_iter) {
4970 /* Only support CTA Extension revision 3+ */
4971 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
4974 size = cea_db_collection_size(ext);
4979 iter->end = iter->index + size;
4989 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
4990 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
4992 * Note that the above do not specify any connection between DisplayID Data
4993 * Block revision and CTA Extension versions.
4995 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
4997 const struct displayid_block *block;
4999 displayid_iter_for_each(block, &iter->displayid_iter) {
5000 if (block->tag != DATA_BLOCK_CTA)
5004 * The displayid iterator has already verified the block bounds
5005 * in displayid_iter_block().
5007 iter->index = sizeof(*block);
5008 iter->end = iter->index + block->num_bytes;
5016 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5018 const struct cea_db *db;
5020 if (iter->collection) {
5021 /* Current collection should always be valid. */
5022 db = __cea_db_iter_current_block(iter);
5024 iter->collection = NULL;
5028 /* Next block in CTA Data Block Collection */
5029 iter->index += sizeof(*db) + cea_db_payload_len(db);
5031 db = __cea_db_iter_current_block(iter);
5038 * Find the next CTA Data Block Collection. First iterate all
5039 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5041 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5042 * Extension, it's recommended that DisplayID extensions are
5043 * exposed after all of the CTA Extensions.
5045 iter->collection = __cea_db_iter_edid_next(iter);
5046 if (!iter->collection)
5047 iter->collection = __cea_db_iter_displayid_next(iter);
5049 if (!iter->collection)
5052 db = __cea_db_iter_current_block(iter);
5058 #define cea_db_iter_for_each(__db, __iter) \
5059 while (((__db) = __cea_db_iter_next(__iter)))
5061 static void cea_db_iter_end(struct cea_db_iter *iter)
5063 displayid_iter_end(&iter->displayid_iter);
5064 drm_edid_iter_end(&iter->edid_iter);
5066 memset(iter, 0, sizeof(*iter));
5069 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
5071 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5072 cea_db_payload_len(db) >= 5;
5075 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
5077 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5078 cea_db_payload_len(db) >= 7;
5081 static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5083 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5084 cea_db_payload_len(db) >= 2;
5087 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
5089 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5090 cea_db_payload_len(db) == 21;
5093 static bool cea_db_is_vcdb(const struct cea_db *db)
5095 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5096 cea_db_payload_len(db) == 2;
5099 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
5101 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5102 cea_db_payload_len(db) >= 7;
5105 static bool cea_db_is_y420cmdb(const struct cea_db *db)
5107 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
5110 static bool cea_db_is_y420vdb(const struct cea_db *db)
5112 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5115 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
5117 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5118 cea_db_payload_len(db) >= 3;
5122 * Get the HF-EEODB override extension block count from EDID.
5124 * The passed in EDID may be partially read, as long as it has at least two
5125 * blocks (base block and one extension block) if EDID extension count is > 0.
5127 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5128 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5129 * iterators instead.
5132 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5134 static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5138 /* No extensions according to base block, no HF-EEODB. */
5139 if (!edid_extension_block_count(edid))
5142 /* HF-EEODB is always in the first EDID extension block only */
5143 cta = edid_extension_block_data(edid, 0);
5144 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5147 /* Need to have the data block collection, and at least 3 bytes. */
5148 if (cea_db_collection_size(cta) < 3)
5152 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5153 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5154 * through 6 of Block 1 of the E-EDID.
5156 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5163 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB)
5165 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB,
5166 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444
5167 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can
5168 * support YCBCR420 output too.
5170 static void parse_cta_y420cmdb(struct drm_connector *connector,
5171 const struct cea_db *db, u64 *y420cmdb_map)
5173 struct drm_display_info *info = &connector->display_info;
5174 int i, map_len = cea_db_payload_len(db) - 1;
5175 const u8 *data = cea_db_data(db) + 1;
5179 /* All CEA modes support ycbcr420 sampling also.*/
5185 * This map indicates which of the existing CEA block modes
5186 * from VDB can support YCBCR420 output too. So if bit=0 is
5187 * set, first mode from VDB can support YCBCR420 output too.
5188 * We will parse and keep this map, before parsing VDB itself
5189 * to avoid going through the same block again and again.
5191 * Spec is not clear about max possible size of this block.
5192 * Clamping max bitmap block size at 8 bytes. Every byte can
5193 * address 8 CEA modes, in this way this map can address
5194 * 8*8 = first 64 SVDs.
5196 if (WARN_ON_ONCE(map_len > 8))
5199 for (i = 0; i < map_len; i++)
5200 map |= (u64)data[i] << (8 * i);
5204 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5206 *y420cmdb_map = map;
5209 static int add_cea_modes(struct drm_connector *connector,
5210 const struct drm_edid *drm_edid)
5212 const struct cea_db *db;
5213 struct cea_db_iter iter;
5216 /* CTA VDB block VICs parsed earlier */
5217 modes = add_cta_vdb_modes(connector);
5219 cea_db_iter_edid_begin(drm_edid, &iter);
5220 cea_db_iter_for_each(db, &iter) {
5221 if (cea_db_is_hdmi_vsdb(db)) {
5222 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db,
5223 cea_db_payload_len(db));
5224 } else if (cea_db_is_y420vdb(db)) {
5225 const u8 *vdb420 = cea_db_data(db) + 1;
5227 /* Add 4:2:0(only) modes present in EDID */
5228 modes += do_y420vdb_modes(connector, vdb420,
5229 cea_db_payload_len(db) - 1);
5232 cea_db_iter_end(&iter);
5237 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5238 struct drm_display_mode *mode)
5240 const struct drm_display_mode *cea_mode;
5241 int clock1, clock2, clock;
5246 * allow 5kHz clock difference either way to account for
5247 * the 10kHz clock resolution limit of detailed timings.
5249 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5250 if (drm_valid_cea_vic(vic)) {
5252 cea_mode = cea_mode_for_vic(vic);
5253 clock1 = cea_mode->clock;
5254 clock2 = cea_mode_alternate_clock(cea_mode);
5256 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5257 if (drm_valid_hdmi_vic(vic)) {
5259 cea_mode = &edid_4k_modes[vic];
5260 clock1 = cea_mode->clock;
5261 clock2 = hdmi_mode_alternate_clock(cea_mode);
5267 /* pick whichever is closest */
5268 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5273 if (mode->clock == clock)
5276 drm_dbg_kms(connector->dev,
5277 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5278 connector->base.id, connector->name,
5279 type, vic, mode->clock, clock);
5280 mode->clock = clock;
5283 static void drm_calculate_luminance_range(struct drm_connector *connector)
5285 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5286 struct drm_luminance_range_info *luminance_range =
5287 &connector->display_info.luminance_range;
5288 static const u8 pre_computed_values[] = {
5289 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5290 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5292 u32 max_avg, min_cll, max, min, q, r;
5294 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5297 max_avg = hdr_metadata->max_fall;
5298 min_cll = hdr_metadata->min_cll;
5301 * From the specification (CTA-861-G), for calculating the maximum
5302 * luminance we need to use:
5303 * Luminance = 50*2**(CV/32)
5304 * Where CV is a one-byte value.
5305 * For calculating this expression we may need float point precision;
5306 * to avoid this complexity level, we take advantage that CV is divided
5307 * by a constant. From the Euclids division algorithm, we know that CV
5308 * can be written as: CV = 32*q + r. Next, we replace CV in the
5309 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5310 * need to pre-compute the value of r/32. For pre-computing the values
5311 * We just used the following Ruby line:
5312 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5313 * The results of the above expressions can be verified at
5314 * pre_computed_values.
5318 max = (1 << q) * pre_computed_values[r];
5320 /* min luminance: maxLum * (CV/255)^2 / 100 */
5321 q = DIV_ROUND_CLOSEST(min_cll, 255);
5322 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5324 luminance_range->min_luminance = min;
5325 luminance_range->max_luminance = max;
5328 static uint8_t eotf_supported(const u8 *edid_ext)
5330 return edid_ext[2] &
5331 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5332 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5333 BIT(HDMI_EOTF_SMPTE_ST2084) |
5334 BIT(HDMI_EOTF_BT_2100_HLG));
5337 static uint8_t hdr_metadata_type(const u8 *edid_ext)
5339 return edid_ext[3] &
5340 BIT(HDMI_STATIC_METADATA_TYPE1);
5344 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5348 len = cea_db_payload_len(db);
5350 connector->hdr_sink_metadata.hdmi_type1.eotf =
5352 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5353 hdr_metadata_type(db);
5356 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5358 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5360 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5362 /* Calculate only when all values are available */
5363 drm_calculate_luminance_range(connector);
5367 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
5369 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5371 u8 len = cea_db_payload_len(db);
5373 if (len >= 6 && (db[6] & (1 << 7)))
5374 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5376 if (len >= 10 && hdmi_vsdb_latency_present(db)) {
5377 connector->latency_present[0] = true;
5378 connector->video_latency[0] = db[9];
5379 connector->audio_latency[0] = db[10];
5382 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) {
5383 connector->latency_present[1] = true;
5384 connector->video_latency[1] = db[11];
5385 connector->audio_latency[1] = db[12];
5388 drm_dbg_kms(connector->dev,
5389 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5390 connector->base.id, connector->name,
5391 connector->latency_present[0], connector->latency_present[1],
5392 connector->video_latency[0], connector->video_latency[1],
5393 connector->audio_latency[0], connector->audio_latency[1]);
5397 monitor_name(const struct detailed_timing *timing, void *data)
5399 const char **res = data;
5401 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5404 *res = timing->data.other_data.data.str.str;
5407 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5409 const char *edid_name = NULL;
5412 if (!drm_edid || !name)
5415 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5416 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5417 if (edid_name[mnl] == 0x0a)
5420 name[mnl] = edid_name[mnl];
5427 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5428 * @edid: monitor EDID information
5429 * @name: pointer to a character array to hold the name of the monitor
5430 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5433 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5435 int name_length = 0;
5442 struct drm_edid drm_edid = {
5444 .size = edid_size(edid),
5447 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5448 memcpy(name, buf, name_length);
5451 name[name_length] = '\0';
5453 EXPORT_SYMBOL(drm_edid_get_monitor_name);
5455 static void clear_eld(struct drm_connector *connector)
5457 memset(connector->eld, 0, sizeof(connector->eld));
5459 connector->latency_present[0] = false;
5460 connector->latency_present[1] = false;
5461 connector->video_latency[0] = 0;
5462 connector->audio_latency[0] = 0;
5463 connector->video_latency[1] = 0;
5464 connector->audio_latency[1] = 0;
5468 * drm_edid_to_eld - build ELD from EDID
5469 * @connector: connector corresponding to the HDMI/DP sink
5470 * @drm_edid: EDID to parse
5472 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5473 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5475 static void drm_edid_to_eld(struct drm_connector *connector,
5476 const struct drm_edid *drm_edid)
5478 const struct drm_display_info *info = &connector->display_info;
5479 const struct cea_db *db;
5480 struct cea_db_iter iter;
5481 uint8_t *eld = connector->eld;
5482 int total_sad_count = 0;
5488 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5489 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5490 connector->base.id, connector->name,
5491 &eld[DRM_ELD_MONITOR_NAME_STRING]);
5493 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5494 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5496 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5498 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5499 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5500 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5501 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5503 cea_db_iter_edid_begin(drm_edid, &iter);
5504 cea_db_iter_for_each(db, &iter) {
5505 const u8 *data = cea_db_data(db);
5506 int len = cea_db_payload_len(db);
5509 switch (cea_db_tag(db)) {
5511 /* Audio Data Block, contains SADs */
5512 sad_count = min(len / 3, 15 - total_sad_count);
5514 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5515 data, sad_count * 3);
5516 total_sad_count += sad_count;
5518 case CTA_DB_SPEAKER:
5519 /* Speaker Allocation Data Block */
5521 eld[DRM_ELD_SPEAKER] = data[0];
5524 /* HDMI Vendor-Specific Data Block */
5525 if (cea_db_is_hdmi_vsdb(db))
5526 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5532 cea_db_iter_end(&iter);
5534 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5536 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5537 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5538 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5540 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5542 eld[DRM_ELD_BASELINE_ELD_LEN] =
5543 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5545 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5546 connector->base.id, connector->name,
5547 drm_eld_size(eld), total_sad_count);
5550 static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5551 struct cea_sad **sads)
5553 const struct cea_db *db;
5554 struct cea_db_iter iter;
5557 cea_db_iter_edid_begin(drm_edid, &iter);
5558 cea_db_iter_for_each(db, &iter) {
5559 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5562 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5563 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
5566 for (j = 0; j < count; j++) {
5567 const u8 *sad = &db->data[j * 3];
5569 (*sads)[j].format = (sad[0] & 0x78) >> 3;
5570 (*sads)[j].channels = sad[0] & 0x7;
5571 (*sads)[j].freq = sad[1] & 0x7F;
5572 (*sads)[j].byte2 = sad[2];
5577 cea_db_iter_end(&iter);
5579 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5585 * drm_edid_to_sad - extracts SADs from EDID
5586 * @edid: EDID to parse
5587 * @sads: pointer that will be set to the extracted SADs
5589 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5591 * Note: The returned pointer needs to be freed using kfree().
5593 * Return: The number of found SADs or negative number on error.
5595 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5597 struct drm_edid drm_edid;
5599 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5601 EXPORT_SYMBOL(drm_edid_to_sad);
5603 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5606 const struct cea_db *db;
5607 struct cea_db_iter iter;
5610 cea_db_iter_edid_begin(drm_edid, &iter);
5611 cea_db_iter_for_each(db, &iter) {
5612 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5613 cea_db_payload_len(db) == 3) {
5614 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5618 count = cea_db_payload_len(db);
5622 cea_db_iter_end(&iter);
5624 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5630 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5631 * @edid: EDID to parse
5632 * @sadb: pointer to the speaker block
5634 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5636 * Note: The returned pointer needs to be freed using kfree().
5638 * Return: The number of found Speaker Allocation Blocks or negative number on
5641 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5643 struct drm_edid drm_edid;
5645 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5648 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5651 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5652 * @connector: connector associated with the HDMI/DP sink
5653 * @mode: the display mode
5655 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5656 * the sink doesn't support audio or video.
5658 int drm_av_sync_delay(struct drm_connector *connector,
5659 const struct drm_display_mode *mode)
5661 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5664 if (!connector->latency_present[0])
5666 if (!connector->latency_present[1])
5669 a = connector->audio_latency[i];
5670 v = connector->video_latency[i];
5673 * HDMI/DP sink doesn't support audio or video?
5675 if (a == 255 || v == 255)
5679 * Convert raw EDID values to millisecond.
5680 * Treat unknown latency as 0ms.
5683 a = min(2 * (a - 1), 500);
5685 v = min(2 * (v - 1), 500);
5687 return max(v - a, 0);
5689 EXPORT_SYMBOL(drm_av_sync_delay);
5691 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5693 const struct cea_db *db;
5694 struct cea_db_iter iter;
5698 * Because HDMI identifier is in Vendor Specific Block,
5699 * search it from all data blocks of CEA extension.
5701 cea_db_iter_edid_begin(drm_edid, &iter);
5702 cea_db_iter_for_each(db, &iter) {
5703 if (cea_db_is_hdmi_vsdb(db)) {
5708 cea_db_iter_end(&iter);
5714 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5715 * @edid: monitor EDID information
5717 * Parse the CEA extension according to CEA-861-B.
5719 * Drivers that have added the modes parsed from EDID to drm_display_info
5720 * should use &drm_display_info.is_hdmi instead of calling this function.
5722 * Return: True if the monitor is HDMI, false if not or unknown.
5724 bool drm_detect_hdmi_monitor(const struct edid *edid)
5726 struct drm_edid drm_edid;
5728 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5730 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5732 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5734 struct drm_edid_iter edid_iter;
5735 const struct cea_db *db;
5736 struct cea_db_iter iter;
5738 bool has_audio = false;
5740 drm_edid_iter_begin(drm_edid, &edid_iter);
5741 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5742 if (edid_ext[0] == CEA_EXT) {
5743 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5748 drm_edid_iter_end(&edid_iter);
5751 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5755 cea_db_iter_edid_begin(drm_edid, &iter);
5756 cea_db_iter_for_each(db, &iter) {
5757 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5758 const u8 *data = cea_db_data(db);
5761 for (i = 0; i < cea_db_payload_len(db); i += 3)
5762 DRM_DEBUG_KMS("CEA audio format %d\n",
5763 (data[i] >> 3) & 0xf);
5768 cea_db_iter_end(&iter);
5775 * drm_detect_monitor_audio - check monitor audio capability
5776 * @edid: EDID block to scan
5778 * Monitor should have CEA extension block.
5779 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5780 * audio' only. If there is any audio extension block and supported
5781 * audio format, assume at least 'basic audio' support, even if 'basic
5782 * audio' is not defined in EDID.
5784 * Return: True if the monitor supports audio, false otherwise.
5786 bool drm_detect_monitor_audio(const struct edid *edid)
5788 struct drm_edid drm_edid;
5790 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5792 EXPORT_SYMBOL(drm_detect_monitor_audio);
5796 * drm_default_rgb_quant_range - default RGB quantization range
5797 * @mode: display mode
5799 * Determine the default RGB quantization range for the mode,
5800 * as specified in CEA-861.
5802 * Return: The default RGB quantization range for the mode
5804 enum hdmi_quantization_range
5805 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5807 /* All CEA modes other than VIC 1 use limited quantization range. */
5808 return drm_match_cea_mode(mode) > 1 ?
5809 HDMI_QUANTIZATION_RANGE_LIMITED :
5810 HDMI_QUANTIZATION_RANGE_FULL;
5812 EXPORT_SYMBOL(drm_default_rgb_quant_range);
5814 /* CTA-861 Video Data Block (CTA VDB) */
5815 static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db)
5817 struct drm_display_info *info = &connector->display_info;
5818 int i, vic_index, len = cea_db_payload_len(db);
5819 const u8 *svds = cea_db_data(db);
5825 /* Gracefully handle multiple VDBs, however unlikely that is */
5826 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL);
5830 vic_index = info->vics_len;
5831 info->vics_len += len;
5834 for (i = 0; i < len; i++) {
5835 u8 vic = svd_to_vic(svds[i]);
5837 if (!drm_valid_cea_vic(vic))
5840 info->vics[vic_index++] = vic;
5845 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB.
5847 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed
5848 * using the VICs themselves.
5850 static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map)
5852 struct drm_display_info *info = &connector->display_info;
5853 struct drm_hdmi_info *hdmi = &info->hdmi;
5854 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map));
5856 for (i = 0; i < len; i++) {
5857 u8 vic = info->vics[i];
5859 if (vic && y420cmdb_map & BIT_ULL(i))
5860 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
5864 static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)
5866 const struct drm_display_info *info = &connector->display_info;
5869 if (!vic || !info->vics)
5872 for (i = 0; i < info->vics_len; i++) {
5873 if (info->vics[i] == vic)
5880 /* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */
5881 static void parse_cta_y420vdb(struct drm_connector *connector,
5882 const struct cea_db *db)
5884 struct drm_display_info *info = &connector->display_info;
5885 struct drm_hdmi_info *hdmi = &info->hdmi;
5886 const u8 *svds = cea_db_data(db) + 1;
5889 for (i = 0; i < cea_db_payload_len(db) - 1; i++) {
5890 u8 vic = svd_to_vic(svds[i]);
5892 if (!drm_valid_cea_vic(vic))
5895 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
5896 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5900 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5902 struct drm_display_info *info = &connector->display_info;
5904 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
5905 connector->base.id, connector->name, db[2]);
5907 if (db[2] & EDID_CEA_VCDB_QS)
5908 info->rgb_quant_range_selectable = true;
5912 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5914 switch (max_frl_rate) {
5917 *max_rate_per_lane = 3;
5921 *max_rate_per_lane = 6;
5925 *max_rate_per_lane = 6;
5929 *max_rate_per_lane = 8;
5933 *max_rate_per_lane = 10;
5937 *max_rate_per_lane = 12;
5942 *max_rate_per_lane = 0;
5946 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5950 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5952 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
5953 hdmi->y420_dc_modes = dc_mask;
5956 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
5959 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
5961 if (!hdmi_dsc->v_1p2)
5964 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
5965 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
5967 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
5968 hdmi_dsc->bpc_supported = 16;
5969 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
5970 hdmi_dsc->bpc_supported = 12;
5971 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
5972 hdmi_dsc->bpc_supported = 10;
5974 /* Supports min 8 BPC if DSC 1.2 is supported*/
5975 hdmi_dsc->bpc_supported = 8;
5977 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
5979 u8 dsc_max_frl_rate;
5981 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
5982 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
5983 &hdmi_dsc->max_frl_rate_per_lane);
5985 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
5987 switch (dsc_max_slices) {
5989 hdmi_dsc->max_slices = 1;
5990 hdmi_dsc->clk_per_slice = 340;
5993 hdmi_dsc->max_slices = 2;
5994 hdmi_dsc->clk_per_slice = 340;
5997 hdmi_dsc->max_slices = 4;
5998 hdmi_dsc->clk_per_slice = 340;
6001 hdmi_dsc->max_slices = 8;
6002 hdmi_dsc->clk_per_slice = 340;
6005 hdmi_dsc->max_slices = 8;
6006 hdmi_dsc->clk_per_slice = 400;
6009 hdmi_dsc->max_slices = 12;
6010 hdmi_dsc->clk_per_slice = 400;
6013 hdmi_dsc->max_slices = 16;
6014 hdmi_dsc->clk_per_slice = 400;
6018 hdmi_dsc->max_slices = 0;
6019 hdmi_dsc->clk_per_slice = 0;
6023 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
6024 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
6027 /* Sink Capability Data Structure */
6028 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
6031 struct drm_display_info *info = &connector->display_info;
6032 struct drm_hdmi_info *hdmi = &info->hdmi;
6033 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
6034 int max_tmds_clock = 0;
6035 u8 max_frl_rate = 0;
6036 bool dsc_support = false;
6038 info->has_hdmi_infoframe = true;
6040 if (hf_scds[6] & 0x80) {
6041 hdmi->scdc.supported = true;
6042 if (hf_scds[6] & 0x40)
6043 hdmi->scdc.read_request = true;
6047 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6048 * And as per the spec, three factors confirm this:
6049 * * Availability of a HF-VSDB block in EDID (check)
6050 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6051 * * SCDC support available (let's check)
6052 * Lets check it out.
6056 struct drm_scdc *scdc = &hdmi->scdc;
6058 /* max clock is 5000 KHz times block value */
6059 max_tmds_clock = hf_scds[5] * 5000;
6061 if (max_tmds_clock > 340000) {
6062 info->max_tmds_clock = max_tmds_clock;
6065 if (scdc->supported) {
6066 scdc->scrambling.supported = true;
6068 /* Few sinks support scrambling for clocks < 340M */
6069 if ((hf_scds[6] & 0x8))
6070 scdc->scrambling.low_rates = true;
6075 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
6076 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6077 &hdmi->max_frl_rate_per_lane);
6080 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
6082 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
6083 drm_parse_dsc_info(hdmi_dsc, hf_scds);
6087 drm_dbg_kms(connector->dev,
6088 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6089 connector->base.id, connector->name,
6090 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
6093 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6096 struct drm_display_info *info = &connector->display_info;
6097 unsigned int dc_bpc = 0;
6099 /* HDMI supports at least 8 bpc */
6102 if (cea_db_payload_len(hdmi) < 6)
6105 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6107 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
6108 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6109 connector->base.id, connector->name);
6112 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6114 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
6115 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6116 connector->base.id, connector->name);
6119 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6121 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
6122 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6123 connector->base.id, connector->name);
6127 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6128 connector->base.id, connector->name);
6132 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6133 connector->base.id, connector->name, dc_bpc);
6136 /* YCRCB444 is optional according to spec. */
6137 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
6138 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
6139 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6140 connector->base.id, connector->name);
6144 * Spec says that if any deep color mode is supported at all,
6145 * then deep color 36 bit must be supported.
6147 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
6148 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6149 connector->base.id, connector->name);
6153 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
6155 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6157 struct drm_display_info *info = &connector->display_info;
6158 u8 len = cea_db_payload_len(db);
6160 info->is_hdmi = true;
6163 info->dvi_dual = db[6] & 1;
6165 info->max_tmds_clock = db[7] * 5000;
6168 * Try to infer whether the sink supports HDMI infoframes.
6170 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink
6171 * supports infoframes if HDMI_Video_present is set.
6173 if (len >= 8 && db[8] & BIT(5))
6174 info->has_hdmi_infoframe = true;
6176 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6177 connector->base.id, connector->name,
6178 info->dvi_dual, info->max_tmds_clock);
6180 drm_parse_hdmi_deep_color_info(connector, db);
6184 * See EDID extension for head-mounted and specialized monitors, specified at:
6185 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6187 static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6190 struct drm_display_info *info = &connector->display_info;
6192 bool desktop_usage = db[5] & BIT(6);
6194 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6195 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6196 info->non_desktop = true;
6198 drm_dbg_kms(connector->dev,
6199 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6200 connector->base.id, connector->name, version, db[5]);
6203 static void drm_parse_cea_ext(struct drm_connector *connector,
6204 const struct drm_edid *drm_edid)
6206 struct drm_display_info *info = &connector->display_info;
6207 struct drm_edid_iter edid_iter;
6208 const struct cea_db *db;
6209 struct cea_db_iter iter;
6211 u64 y420cmdb_map = 0;
6213 drm_edid_iter_begin(drm_edid, &edid_iter);
6214 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6215 if (edid_ext[0] != CEA_EXT)
6219 info->cea_rev = edid_ext[1];
6221 if (info->cea_rev != edid_ext[1])
6222 drm_dbg_kms(connector->dev,
6223 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6224 connector->base.id, connector->name,
6225 info->cea_rev, edid_ext[1]);
6227 /* The existence of a CTA extension should imply RGB support */
6228 info->color_formats = DRM_COLOR_FORMAT_RGB444;
6229 if (edid_ext[3] & EDID_CEA_YCRCB444)
6230 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6231 if (edid_ext[3] & EDID_CEA_YCRCB422)
6232 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6234 drm_edid_iter_end(&edid_iter);
6236 cea_db_iter_edid_begin(drm_edid, &iter);
6237 cea_db_iter_for_each(db, &iter) {
6238 /* FIXME: convert parsers to use struct cea_db */
6239 const u8 *data = (const u8 *)db;
6241 if (cea_db_is_hdmi_vsdb(db))
6242 drm_parse_hdmi_vsdb_video(connector, data);
6243 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6244 cea_db_is_hdmi_forum_scdb(db))
6245 drm_parse_hdmi_forum_scds(connector, data);
6246 else if (cea_db_is_microsoft_vsdb(db))
6247 drm_parse_microsoft_vsdb(connector, data);
6248 else if (cea_db_is_y420cmdb(db))
6249 parse_cta_y420cmdb(connector, db, &y420cmdb_map);
6250 else if (cea_db_is_y420vdb(db))
6251 parse_cta_y420vdb(connector, db);
6252 else if (cea_db_is_vcdb(db))
6253 drm_parse_vcdb(connector, data);
6254 else if (cea_db_is_hdmi_hdr_metadata_block(db))
6255 drm_parse_hdr_metadata_block(connector, data);
6256 else if (cea_db_tag(db) == CTA_DB_VIDEO)
6257 parse_cta_vdb(connector, db);
6259 cea_db_iter_end(&iter);
6262 update_cta_y420cmdb(connector, y420cmdb_map);
6266 void get_monitor_range(const struct detailed_timing *timing, void *c)
6268 struct detailed_mode_closure *closure = c;
6269 struct drm_display_info *info = &closure->connector->display_info;
6270 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
6271 const struct detailed_non_pixel *data = &timing->data.other_data;
6272 const struct detailed_data_monitor_range *range = &data->data.range;
6273 const struct edid *edid = closure->drm_edid->edid;
6275 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
6279 * These limits are used to determine the VRR refresh
6280 * rate range. Only the "range limits only" variant
6281 * of the range descriptor seems to guarantee that
6282 * any and all timings are accepted by the sink, as
6283 * opposed to just timings conforming to the indicated
6284 * formula (GTF/GTF2/CVT). Thus other variants of the
6285 * range descriptor are not accepted here.
6287 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6290 monitor_range->min_vfreq = range->min_vfreq;
6291 monitor_range->max_vfreq = range->max_vfreq;
6293 if (edid->revision >= 4) {
6294 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6295 monitor_range->min_vfreq += 255;
6296 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6297 monitor_range->max_vfreq += 255;
6301 static void drm_get_monitor_range(struct drm_connector *connector,
6302 const struct drm_edid *drm_edid)
6304 const struct drm_display_info *info = &connector->display_info;
6305 struct detailed_mode_closure closure = {
6306 .connector = connector,
6307 .drm_edid = drm_edid,
6310 if (drm_edid->edid->revision < 4)
6313 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
6316 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6318 drm_dbg_kms(connector->dev,
6319 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6320 connector->base.id, connector->name,
6321 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
6324 static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6325 const struct displayid_block *block)
6327 struct displayid_vesa_vendor_specific_block *vesa =
6328 (struct displayid_vesa_vendor_specific_block *)block;
6329 struct drm_display_info *info = &connector->display_info;
6331 if (block->num_bytes < 3) {
6332 drm_dbg_kms(connector->dev,
6333 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6334 connector->base.id, connector->name, block->num_bytes);
6338 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6341 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6342 drm_dbg_kms(connector->dev,
6343 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6344 connector->base.id, connector->name);
6348 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6350 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6351 connector->base.id, connector->name);
6354 info->mso_stream_count = 0;
6357 info->mso_stream_count = 2; /* 2 or 4 links */
6360 info->mso_stream_count = 4; /* 4 links */
6364 if (!info->mso_stream_count) {
6365 info->mso_pixel_overlap = 0;
6369 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6370 if (info->mso_pixel_overlap > 8) {
6371 drm_dbg_kms(connector->dev,
6372 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6373 connector->base.id, connector->name,
6374 info->mso_pixel_overlap);
6375 info->mso_pixel_overlap = 8;
6378 drm_dbg_kms(connector->dev,
6379 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6380 connector->base.id, connector->name,
6381 info->mso_stream_count, info->mso_pixel_overlap);
6384 static void drm_update_mso(struct drm_connector *connector,
6385 const struct drm_edid *drm_edid)
6387 const struct displayid_block *block;
6388 struct displayid_iter iter;
6390 displayid_iter_edid_begin(drm_edid, &iter);
6391 displayid_iter_for_each(block, &iter) {
6392 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6393 drm_parse_vesa_mso_data(connector, block);
6395 displayid_iter_end(&iter);
6398 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6399 * all of the values which would have been set from EDID
6401 static void drm_reset_display_info(struct drm_connector *connector)
6403 struct drm_display_info *info = &connector->display_info;
6406 info->height_mm = 0;
6409 info->color_formats = 0;
6411 info->max_tmds_clock = 0;
6412 info->dvi_dual = false;
6413 info->is_hdmi = false;
6414 info->has_hdmi_infoframe = false;
6415 info->rgb_quant_range_selectable = false;
6416 memset(&info->hdmi, 0, sizeof(info->hdmi));
6418 info->edid_hdmi_rgb444_dc_modes = 0;
6419 info->edid_hdmi_ycbcr444_dc_modes = 0;
6421 info->non_desktop = 0;
6422 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6423 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
6425 info->mso_stream_count = 0;
6426 info->mso_pixel_overlap = 0;
6427 info->max_dsc_bpp = 0;
6436 static void update_display_info(struct drm_connector *connector,
6437 const struct drm_edid *drm_edid)
6439 struct drm_display_info *info = &connector->display_info;
6440 const struct edid *edid;
6442 drm_reset_display_info(connector);
6443 clear_eld(connector);
6448 edid = drm_edid->edid;
6450 info->quirks = edid_get_quirks(drm_edid);
6452 info->width_mm = edid->width_cm * 10;
6453 info->height_mm = edid->height_cm * 10;
6455 drm_get_monitor_range(connector, drm_edid);
6457 if (edid->revision < 3)
6460 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
6463 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6464 drm_parse_cea_ext(connector, drm_edid);
6467 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6469 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6470 * tells us to assume 8 bpc color depth if the EDID doesn't have
6471 * extensions which tell otherwise.
6473 if (info->bpc == 0 && edid->revision == 3 &&
6474 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6476 drm_dbg_kms(connector->dev,
6477 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6478 connector->base.id, connector->name, info->bpc);
6481 /* Only defined for 1.4 with digital displays */
6482 if (edid->revision < 4)
6485 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6486 case DRM_EDID_DIGITAL_DEPTH_6:
6489 case DRM_EDID_DIGITAL_DEPTH_8:
6492 case DRM_EDID_DIGITAL_DEPTH_10:
6495 case DRM_EDID_DIGITAL_DEPTH_12:
6498 case DRM_EDID_DIGITAL_DEPTH_14:
6501 case DRM_EDID_DIGITAL_DEPTH_16:
6504 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6510 drm_dbg_kms(connector->dev,
6511 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6512 connector->base.id, connector->name, info->bpc);
6514 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6515 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6516 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6517 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6519 drm_update_mso(connector, drm_edid);
6522 if (info->quirks & EDID_QUIRK_NON_DESKTOP) {
6523 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6524 connector->base.id, connector->name,
6525 info->non_desktop ? " (redundant quirk)" : "");
6526 info->non_desktop = true;
6529 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP)
6530 info->max_dsc_bpp = 15;
6532 if (info->quirks & EDID_QUIRK_FORCE_6BPC)
6535 if (info->quirks & EDID_QUIRK_FORCE_8BPC)
6538 if (info->quirks & EDID_QUIRK_FORCE_10BPC)
6541 if (info->quirks & EDID_QUIRK_FORCE_12BPC)
6544 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */
6545 drm_edid_to_eld(connector, drm_edid);
6548 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6549 struct displayid_detailed_timings_1 *timings,
6552 struct drm_display_mode *mode;
6553 unsigned pixel_clock = (timings->pixel_clock[0] |
6554 (timings->pixel_clock[1] << 8) |
6555 (timings->pixel_clock[2] << 16)) + 1;
6556 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6557 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6558 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6559 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6560 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6561 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6562 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6563 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6564 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6565 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6567 mode = drm_mode_create(dev);
6571 /* resolution is kHz for type VII, and 10 kHz for type I */
6572 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6573 mode->hdisplay = hactive;
6574 mode->hsync_start = mode->hdisplay + hsync;
6575 mode->hsync_end = mode->hsync_start + hsync_width;
6576 mode->htotal = mode->hdisplay + hblank;
6578 mode->vdisplay = vactive;
6579 mode->vsync_start = mode->vdisplay + vsync;
6580 mode->vsync_end = mode->vsync_start + vsync_width;
6581 mode->vtotal = mode->vdisplay + vblank;
6584 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6585 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6586 mode->type = DRM_MODE_TYPE_DRIVER;
6588 if (timings->flags & 0x80)
6589 mode->type |= DRM_MODE_TYPE_PREFERRED;
6590 drm_mode_set_name(mode);
6595 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6596 const struct displayid_block *block)
6598 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6601 struct drm_display_mode *newmode;
6603 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6604 /* blocks must be multiple of 20 bytes length */
6605 if (block->num_bytes % 20)
6608 num_timings = block->num_bytes / 20;
6609 for (i = 0; i < num_timings; i++) {
6610 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6612 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6616 drm_mode_probed_add(connector, newmode);
6622 static int add_displayid_detailed_modes(struct drm_connector *connector,
6623 const struct drm_edid *drm_edid)
6625 const struct displayid_block *block;
6626 struct displayid_iter iter;
6629 displayid_iter_edid_begin(drm_edid, &iter);
6630 displayid_iter_for_each(block, &iter) {
6631 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6632 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6633 num_modes += add_displayid_detailed_1_modes(connector, block);
6635 displayid_iter_end(&iter);
6640 static int _drm_edid_connector_add_modes(struct drm_connector *connector,
6641 const struct drm_edid *drm_edid)
6643 const struct drm_display_info *info = &connector->display_info;
6650 * EDID spec says modes should be preferred in this order:
6651 * - preferred detailed mode
6652 * - other detailed modes from base block
6653 * - detailed modes from extension blocks
6654 * - CVT 3-byte code modes
6655 * - standard timing codes
6656 * - established timing codes
6657 * - modes inferred from GTF or CVT range information
6659 * We get this pretty much right.
6661 * XXX order for additional mode types in extension blocks?
6663 num_modes += add_detailed_modes(connector, drm_edid);
6664 num_modes += add_cvt_modes(connector, drm_edid);
6665 num_modes += add_standard_modes(connector, drm_edid);
6666 num_modes += add_established_modes(connector, drm_edid);
6667 num_modes += add_cea_modes(connector, drm_edid);
6668 num_modes += add_alternate_cea_modes(connector, drm_edid);
6669 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6670 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
6671 num_modes += add_inferred_modes(connector, drm_edid);
6673 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6674 edid_fixup_preferred(connector);
6679 static void _drm_update_tile_info(struct drm_connector *connector,
6680 const struct drm_edid *drm_edid);
6682 static int _drm_edid_connector_property_update(struct drm_connector *connector,
6683 const struct drm_edid *drm_edid)
6685 struct drm_device *dev = connector->dev;
6688 if (connector->edid_blob_ptr) {
6689 const struct edid *old_edid = connector->edid_blob_ptr->data;
6692 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
6693 connector->epoch_counter++;
6694 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6695 connector->base.id, connector->name,
6696 connector->epoch_counter);
6701 ret = drm_property_replace_global_blob(dev,
6702 &connector->edid_blob_ptr,
6703 drm_edid ? drm_edid->size : 0,
6704 drm_edid ? drm_edid->edid : NULL,
6706 dev->mode_config.edid_property);
6708 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6709 connector->base.id, connector->name, ret);
6713 ret = drm_object_property_set_value(&connector->base,
6714 dev->mode_config.non_desktop_property,
6715 connector->display_info.non_desktop);
6717 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6718 connector->base.id, connector->name, ret);
6722 ret = drm_connector_set_tile_property(connector);
6724 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6725 connector->base.id, connector->name, ret);
6734 * drm_edid_connector_update - Update connector information from EDID
6735 * @connector: Connector
6738 * Update the connector display info, ELD, HDR metadata, relevant properties,
6739 * etc. from the passed in EDID.
6741 * If EDID is NULL, reset the information.
6743 * Must be called before calling drm_edid_connector_add_modes().
6745 * Return: 0 on success, negative error on errors.
6747 int drm_edid_connector_update(struct drm_connector *connector,
6748 const struct drm_edid *drm_edid)
6750 update_display_info(connector, drm_edid);
6752 _drm_update_tile_info(connector, drm_edid);
6754 return _drm_edid_connector_property_update(connector, drm_edid);
6756 EXPORT_SYMBOL(drm_edid_connector_update);
6759 * drm_edid_connector_add_modes - Update probed modes from the EDID property
6760 * @connector: Connector
6762 * Add the modes from the previously updated EDID property to the connector
6763 * probed modes list.
6765 * drm_edid_connector_update() must have been called before this to update the
6768 * Return: The number of modes added, or 0 if we couldn't find any.
6770 int drm_edid_connector_add_modes(struct drm_connector *connector)
6772 const struct drm_edid *drm_edid = NULL;
6775 if (connector->edid_blob_ptr)
6776 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data,
6777 connector->edid_blob_ptr->length);
6779 count = _drm_edid_connector_add_modes(connector, drm_edid);
6781 drm_edid_free(drm_edid);
6785 EXPORT_SYMBOL(drm_edid_connector_add_modes);
6788 * drm_connector_update_edid_property - update the edid property of a connector
6789 * @connector: drm connector
6790 * @edid: new value of the edid property
6792 * This function creates a new blob modeset object and assigns its id to the
6793 * connector's edid property.
6794 * Since we also parse tile information from EDID's displayID block, we also
6795 * set the connector's tile property here. See drm_connector_set_tile_property()
6798 * This function is deprecated. Use drm_edid_connector_update() instead.
6801 * Zero on success, negative errno on failure.
6803 int drm_connector_update_edid_property(struct drm_connector *connector,
6804 const struct edid *edid)
6806 struct drm_edid drm_edid;
6808 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid));
6810 EXPORT_SYMBOL(drm_connector_update_edid_property);
6813 * drm_add_edid_modes - add modes from EDID data, if available
6814 * @connector: connector we're probing
6817 * Add the specified modes to the connector's mode list. Also fills out the
6818 * &drm_display_info structure and ELD in @connector with any information which
6819 * can be derived from the edid.
6821 * This function is deprecated. Use drm_edid_connector_add_modes() instead.
6823 * Return: The number of modes added or 0 if we couldn't find any.
6825 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6827 struct drm_edid _drm_edid;
6828 const struct drm_edid *drm_edid;
6830 if (edid && !drm_edid_is_valid(edid)) {
6831 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
6832 connector->base.id, connector->name);
6836 drm_edid = drm_edid_legacy_init(&_drm_edid, edid);
6838 update_display_info(connector, drm_edid);
6840 return _drm_edid_connector_add_modes(connector, drm_edid);
6842 EXPORT_SYMBOL(drm_add_edid_modes);
6845 * drm_add_modes_noedid - add modes for the connectors without EDID
6846 * @connector: connector we're probing
6847 * @hdisplay: the horizontal display limit
6848 * @vdisplay: the vertical display limit
6850 * Add the specified modes to the connector's mode list. Only when the
6851 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6853 * Return: The number of modes added or 0 if we couldn't find any.
6855 int drm_add_modes_noedid(struct drm_connector *connector,
6856 int hdisplay, int vdisplay)
6858 int i, count, num_modes = 0;
6859 struct drm_display_mode *mode;
6860 struct drm_device *dev = connector->dev;
6862 count = ARRAY_SIZE(drm_dmt_modes);
6868 for (i = 0; i < count; i++) {
6869 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
6871 if (hdisplay && vdisplay) {
6873 * Only when two are valid, they will be used to check
6874 * whether the mode should be added to the mode list of
6877 if (ptr->hdisplay > hdisplay ||
6878 ptr->vdisplay > vdisplay)
6881 if (drm_mode_vrefresh(ptr) > 61)
6883 mode = drm_mode_duplicate(dev, ptr);
6885 drm_mode_probed_add(connector, mode);
6891 EXPORT_SYMBOL(drm_add_modes_noedid);
6894 * drm_set_preferred_mode - Sets the preferred mode of a connector
6895 * @connector: connector whose mode list should be processed
6896 * @hpref: horizontal resolution of preferred mode
6897 * @vpref: vertical resolution of preferred mode
6899 * Marks a mode as preferred if it matches the resolution specified by @hpref
6902 void drm_set_preferred_mode(struct drm_connector *connector,
6903 int hpref, int vpref)
6905 struct drm_display_mode *mode;
6907 list_for_each_entry(mode, &connector->probed_modes, head) {
6908 if (mode->hdisplay == hpref &&
6909 mode->vdisplay == vpref)
6910 mode->type |= DRM_MODE_TYPE_PREFERRED;
6913 EXPORT_SYMBOL(drm_set_preferred_mode);
6915 static bool is_hdmi2_sink(const struct drm_connector *connector)
6918 * FIXME: sil-sii8620 doesn't have a connector around when
6919 * we need one, so we have to be prepared for a NULL connector.
6924 return connector->display_info.hdmi.scdc.supported ||
6925 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
6928 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
6929 const struct drm_display_mode *mode)
6931 bool has_hdmi_infoframe = connector ?
6932 connector->display_info.has_hdmi_infoframe : false;
6934 if (!has_hdmi_infoframe)
6937 /* No HDMI VIC when signalling 3D video format */
6938 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
6941 return drm_match_hdmi_mode(mode);
6944 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
6945 const struct drm_display_mode *mode)
6948 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
6949 * we should send its VIC in vendor infoframes, else send the
6950 * VIC in AVI infoframes. Lets check if this mode is present in
6951 * HDMI 1.4b 4K modes
6953 if (drm_mode_hdmi_vic(connector, mode))
6956 return drm_match_cea_mode(mode);
6960 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
6961 * conform to HDMI 1.4.
6963 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
6964 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
6966 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI
6969 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
6971 if (!is_hdmi2_sink(connector) && vic > 64 &&
6972 !cta_vdb_has_vic(connector, vic))
6979 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
6980 * data from a DRM display mode
6981 * @frame: HDMI AVI infoframe
6982 * @connector: the connector
6983 * @mode: DRM display mode
6985 * Return: 0 on success or a negative error code on failure.
6988 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
6989 const struct drm_connector *connector,
6990 const struct drm_display_mode *mode)
6992 enum hdmi_picture_aspect picture_aspect;
6995 if (!frame || !mode)
6998 hdmi_avi_infoframe_init(frame);
7000 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
7001 frame->pixel_repeat = 1;
7003 vic = drm_mode_cea_vic(connector, mode);
7004 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
7006 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7009 * As some drivers don't support atomic, we can't use connector state.
7010 * So just initialize the frame with default values, just the same way
7011 * as it's done with other properties here.
7013 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
7017 * Populate picture aspect ratio from either
7018 * user input (if specified) or from the CEA/HDMI mode lists.
7020 picture_aspect = mode->picture_aspect_ratio;
7021 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
7023 picture_aspect = drm_get_cea_aspect_ratio(vic);
7025 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
7029 * The infoframe can't convey anything but none, 4:3
7030 * and 16:9, so if the user has asked for anything else
7031 * we can only satisfy it by specifying the right VIC.
7033 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
7035 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
7037 } else if (hdmi_vic) {
7038 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
7044 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7047 frame->video_code = vic_for_avi_infoframe(connector, vic);
7048 frame->picture_aspect = picture_aspect;
7049 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
7050 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
7054 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
7057 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
7058 * quantization range information
7059 * @frame: HDMI AVI infoframe
7060 * @connector: the connector
7061 * @mode: DRM display mode
7062 * @rgb_quant_range: RGB quantization range (Q)
7065 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
7066 const struct drm_connector *connector,
7067 const struct drm_display_mode *mode,
7068 enum hdmi_quantization_range rgb_quant_range)
7070 const struct drm_display_info *info = &connector->display_info;
7074 * "A Source shall not send a non-zero Q value that does not correspond
7075 * to the default RGB Quantization Range for the transmitted Picture
7076 * unless the Sink indicates support for the Q bit in a Video
7077 * Capabilities Data Block."
7079 * HDMI 2.0 recommends sending non-zero Q when it does match the
7080 * default RGB quantization range for the mode, even when QS=0.
7082 if (info->rgb_quant_range_selectable ||
7083 rgb_quant_range == drm_default_rgb_quant_range(mode))
7084 frame->quantization_range = rgb_quant_range;
7086 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
7090 * "When transmitting any RGB colorimetry, the Source should set the
7091 * YQ-field to match the RGB Quantization Range being transmitted
7092 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7093 * set YQ=1) and the Sink shall ignore the YQ-field."
7095 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7096 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7097 * good way to tell which version of CEA-861 the sink supports, so
7098 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
7101 if (!is_hdmi2_sink(connector) ||
7102 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
7103 frame->ycc_quantization_range =
7104 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7106 frame->ycc_quantization_range =
7107 HDMI_YCC_QUANTIZATION_RANGE_FULL;
7109 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7111 static enum hdmi_3d_structure
7112 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7114 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7117 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7118 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7119 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7120 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7121 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7122 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7123 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7124 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7125 case DRM_MODE_FLAG_3D_L_DEPTH:
7126 return HDMI_3D_STRUCTURE_L_DEPTH;
7127 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7128 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7129 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7130 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7131 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7132 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7134 return HDMI_3D_STRUCTURE_INVALID;
7139 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7140 * data from a DRM display mode
7141 * @frame: HDMI vendor infoframe
7142 * @connector: the connector
7143 * @mode: DRM display mode
7145 * Note that there's is a need to send HDMI vendor infoframes only when using a
7146 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7147 * function will return -EINVAL, error that can be safely ignored.
7149 * Return: 0 on success or a negative error code on failure.
7152 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
7153 const struct drm_connector *connector,
7154 const struct drm_display_mode *mode)
7157 * FIXME: sil-sii8620 doesn't have a connector around when
7158 * we need one, so we have to be prepared for a NULL connector.
7160 bool has_hdmi_infoframe = connector ?
7161 connector->display_info.has_hdmi_infoframe : false;
7164 if (!frame || !mode)
7167 if (!has_hdmi_infoframe)
7170 err = hdmi_vendor_infoframe_init(frame);
7175 * Even if it's not absolutely necessary to send the infoframe
7176 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7177 * know that the sink can handle it. This is based on a
7178 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
7179 * have trouble realizing that they should switch from 3D to 2D
7180 * mode if the source simply stops sending the infoframe when
7181 * it wants to switch from 3D to 2D.
7183 frame->vic = drm_mode_hdmi_vic(connector, mode);
7184 frame->s3d_struct = s3d_structure_from_display_mode(mode);
7188 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
7190 static void drm_parse_tiled_block(struct drm_connector *connector,
7191 const struct displayid_block *block)
7193 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
7195 u8 tile_v_loc, tile_h_loc;
7196 u8 num_v_tile, num_h_tile;
7197 struct drm_tile_group *tg;
7199 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7200 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7202 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7203 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7204 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7205 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7207 connector->has_tile = true;
7208 if (tile->tile_cap & 0x80)
7209 connector->tile_is_single_monitor = true;
7211 connector->num_h_tile = num_h_tile + 1;
7212 connector->num_v_tile = num_v_tile + 1;
7213 connector->tile_h_loc = tile_h_loc;
7214 connector->tile_v_loc = tile_v_loc;
7215 connector->tile_h_size = w + 1;
7216 connector->tile_v_size = h + 1;
7218 drm_dbg_kms(connector->dev,
7219 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7220 connector->base.id, connector->name,
7222 connector->tile_h_size, connector->tile_v_size,
7223 connector->num_h_tile, connector->num_v_tile,
7224 connector->tile_h_loc, connector->tile_v_loc,
7225 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
7227 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
7229 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
7233 if (connector->tile_group != tg) {
7234 /* if we haven't got a pointer,
7235 take the reference, drop ref to old tile group */
7236 if (connector->tile_group)
7237 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7238 connector->tile_group = tg;
7240 /* if same tile group, then release the ref we just took. */
7241 drm_mode_put_tile_group(connector->dev, tg);
7245 static void _drm_update_tile_info(struct drm_connector *connector,
7246 const struct drm_edid *drm_edid)
7248 const struct displayid_block *block;
7249 struct displayid_iter iter;
7251 connector->has_tile = false;
7253 displayid_iter_edid_begin(drm_edid, &iter);
7254 displayid_iter_for_each(block, &iter) {
7255 if (block->tag == DATA_BLOCK_TILED_DISPLAY)
7256 drm_parse_tiled_block(connector, block);
7258 displayid_iter_end(&iter);
7260 if (!connector->has_tile && connector->tile_group) {
7261 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7262 connector->tile_group = NULL;
projects / linux-2.6-block.git / blob