2 * Copyright © 2009 Keith Packard
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
23 #include <linux/delay.h>
24 #include <linux/errno.h>
25 #include <linux/i2c.h>
26 #include <linux/init.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/sched.h>
30 #include <linux/seq_file.h>
32 #include <drm/drm_dp_helper.h>
33 #include <drm/drm_print.h>
34 #include <drm/drm_vblank.h>
35 #include <drm/drm_dp_mst_helper.h>
37 #include "drm_crtc_helper_internal.h"
42 * These functions contain some common logic and helpers at various abstraction
43 * levels to deal with Display Port sink devices and related things like DP aux
44 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
48 /* Helpers for DP link training */
49 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
51 return link_status[r - DP_LANE0_1_STATUS];
54 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
57 int i = DP_LANE0_1_STATUS + (lane >> 1);
58 int s = (lane & 1) * 4;
59 u8 l = dp_link_status(link_status, i);
61 return (l >> s) & 0xf;
64 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
71 lane_align = dp_link_status(link_status,
72 DP_LANE_ALIGN_STATUS_UPDATED);
73 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
75 for (lane = 0; lane < lane_count; lane++) {
76 lane_status = dp_get_lane_status(link_status, lane);
77 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
82 EXPORT_SYMBOL(drm_dp_channel_eq_ok);
84 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
90 for (lane = 0; lane < lane_count; lane++) {
91 lane_status = dp_get_lane_status(link_status, lane);
92 if ((lane_status & DP_LANE_CR_DONE) == 0)
97 EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
99 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
102 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
103 int s = ((lane & 1) ?
104 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
105 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
106 u8 l = dp_link_status(link_status, i);
108 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
110 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
112 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
115 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
116 int s = ((lane & 1) ?
117 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
118 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
119 u8 l = dp_link_status(link_status, i);
121 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
123 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
125 u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
128 unsigned int offset = DP_ADJUST_REQUEST_POST_CURSOR2;
129 u8 value = dp_link_status(link_status, offset);
131 return (value >> (lane << 1)) & 0x3;
133 EXPORT_SYMBOL(drm_dp_get_adjust_request_post_cursor);
135 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
137 unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
138 DP_TRAINING_AUX_RD_MASK;
141 DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
144 if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
147 rd_interval *= 4 * USEC_PER_MSEC;
149 usleep_range(rd_interval, rd_interval * 2);
151 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
153 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
155 unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
156 DP_TRAINING_AUX_RD_MASK;
159 DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
162 if (rd_interval == 0)
165 rd_interval *= 4 * USEC_PER_MSEC;
167 usleep_range(rd_interval, rd_interval * 2);
169 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
171 u8 drm_dp_link_rate_to_bw_code(int link_rate)
173 /* Spec says link_bw = link_rate / 0.27Gbps */
174 return link_rate / 27000;
176 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
178 int drm_dp_bw_code_to_link_rate(u8 link_bw)
180 /* Spec says link_rate = link_bw * 0.27Gbps */
181 return link_bw * 27000;
183 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
185 #define AUX_RETRY_INTERVAL 500 /* us */
188 drm_dp_dump_access(const struct drm_dp_aux *aux,
189 u8 request, uint offset, void *buffer, int ret)
191 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
194 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
195 aux->name, offset, arrow, ret, min(ret, 20), buffer);
197 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d)\n",
198 aux->name, offset, arrow, ret);
204 * The DisplayPort AUX channel is an abstraction to allow generic, driver-
205 * independent access to AUX functionality. Drivers can take advantage of
206 * this by filling in the fields of the drm_dp_aux structure.
208 * Transactions are described using a hardware-independent drm_dp_aux_msg
209 * structure, which is passed into a driver's .transfer() implementation.
210 * Both native and I2C-over-AUX transactions are supported.
213 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
214 unsigned int offset, void *buffer, size_t size)
216 struct drm_dp_aux_msg msg;
217 unsigned int retry, native_reply;
218 int err = 0, ret = 0;
220 memset(&msg, 0, sizeof(msg));
221 msg.address = offset;
222 msg.request = request;
226 mutex_lock(&aux->hw_mutex);
229 * The specification doesn't give any recommendation on how often to
230 * retry native transactions. We used to retry 7 times like for
231 * aux i2c transactions but real world devices this wasn't
232 * sufficient, bump to 32 which makes Dell 4k monitors happier.
234 for (retry = 0; retry < 32; retry++) {
235 if (ret != 0 && ret != -ETIMEDOUT) {
236 usleep_range(AUX_RETRY_INTERVAL,
237 AUX_RETRY_INTERVAL + 100);
240 ret = aux->transfer(aux, &msg);
242 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
243 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
253 * We want the error we return to be the error we received on
254 * the first transaction, since we may get a different error the
261 DRM_DEBUG_KMS("%s: Too many retries, giving up. First error: %d\n",
266 mutex_unlock(&aux->hw_mutex);
271 * drm_dp_dpcd_read() - read a series of bytes from the DPCD
272 * @aux: DisplayPort AUX channel (SST or MST)
273 * @offset: address of the (first) register to read
274 * @buffer: buffer to store the register values
275 * @size: number of bytes in @buffer
277 * Returns the number of bytes transferred on success, or a negative error
278 * code on failure. -EIO is returned if the request was NAKed by the sink or
279 * if the retry count was exceeded. If not all bytes were transferred, this
280 * function returns -EPROTO. Errors from the underlying AUX channel transfer
281 * function, with the exception of -EBUSY (which causes the transaction to
282 * be retried), are propagated to the caller.
284 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
285 void *buffer, size_t size)
290 * HP ZR24w corrupts the first DPCD access after entering power save
291 * mode. Eg. on a read, the entire buffer will be filled with the same
292 * byte. Do a throw away read to avoid corrupting anything we care
293 * about. Afterwards things will work correctly until the monitor
294 * gets woken up and subsequently re-enters power save mode.
296 * The user pressing any button on the monitor is enough to wake it
297 * up, so there is no particularly good place to do the workaround.
298 * We just have to do it before any DPCD access and hope that the
299 * monitor doesn't power down exactly after the throw away read.
301 if (!aux->is_remote) {
302 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV,
309 ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size);
311 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset,
315 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
318 EXPORT_SYMBOL(drm_dp_dpcd_read);
321 * drm_dp_dpcd_write() - write a series of bytes to the DPCD
322 * @aux: DisplayPort AUX channel (SST or MST)
323 * @offset: address of the (first) register to write
324 * @buffer: buffer containing the values to write
325 * @size: number of bytes in @buffer
327 * Returns the number of bytes transferred on success, or a negative error
328 * code on failure. -EIO is returned if the request was NAKed by the sink or
329 * if the retry count was exceeded. If not all bytes were transferred, this
330 * function returns -EPROTO. Errors from the underlying AUX channel transfer
331 * function, with the exception of -EBUSY (which causes the transaction to
332 * be retried), are propagated to the caller.
334 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
335 void *buffer, size_t size)
340 ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size);
342 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset,
345 drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
348 EXPORT_SYMBOL(drm_dp_dpcd_write);
351 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
352 * @aux: DisplayPort AUX channel
353 * @status: buffer to store the link status in (must be at least 6 bytes)
355 * Returns the number of bytes transferred on success or a negative error
358 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
359 u8 status[DP_LINK_STATUS_SIZE])
361 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
362 DP_LINK_STATUS_SIZE);
364 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
367 * drm_dp_send_real_edid_checksum() - send back real edid checksum value
368 * @aux: DisplayPort AUX channel
369 * @real_edid_checksum: real edid checksum for the last block
374 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
375 u8 real_edid_checksum)
377 u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
379 if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
380 &auto_test_req, 1) < 1) {
381 DRM_ERROR("%s: DPCD failed read at register 0x%x\n",
382 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
385 auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
387 if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) {
388 DRM_ERROR("%s: DPCD failed read at register 0x%x\n",
389 aux->name, DP_TEST_REQUEST);
392 link_edid_read &= DP_TEST_LINK_EDID_READ;
394 if (!auto_test_req || !link_edid_read) {
395 DRM_DEBUG_KMS("%s: Source DUT does not support TEST_EDID_READ\n",
400 if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
401 &auto_test_req, 1) < 1) {
402 DRM_ERROR("%s: DPCD failed write at register 0x%x\n",
403 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
407 /* send back checksum for the last edid extension block data */
408 if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM,
409 &real_edid_checksum, 1) < 1) {
410 DRM_ERROR("%s: DPCD failed write at register 0x%x\n",
411 aux->name, DP_TEST_EDID_CHECKSUM);
415 test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
416 if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) {
417 DRM_ERROR("%s: DPCD failed write at register 0x%x\n",
418 aux->name, DP_TEST_RESPONSE);
424 EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
427 * drm_dp_downstream_max_clock() - extract branch device max
428 * pixel rate for legacy VGA
429 * converter or max TMDS clock
431 * @dpcd: DisplayPort configuration data
432 * @port_cap: port capabilities
434 * Returns max clock in kHz on success or 0 if max clock not defined
436 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
437 const u8 port_cap[4])
439 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
440 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
441 DP_DETAILED_CAP_INFO_AVAILABLE;
443 if (!detailed_cap_info)
447 case DP_DS_PORT_TYPE_VGA:
448 return port_cap[1] * 8 * 1000;
449 case DP_DS_PORT_TYPE_DVI:
450 case DP_DS_PORT_TYPE_HDMI:
451 case DP_DS_PORT_TYPE_DP_DUALMODE:
452 return port_cap[1] * 2500;
457 EXPORT_SYMBOL(drm_dp_downstream_max_clock);
460 * drm_dp_downstream_max_bpc() - extract branch device max
462 * @dpcd: DisplayPort configuration data
463 * @port_cap: port capabilities
465 * Returns max bpc on success or 0 if max bpc not defined
467 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
468 const u8 port_cap[4])
470 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
471 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
472 DP_DETAILED_CAP_INFO_AVAILABLE;
475 if (!detailed_cap_info)
479 case DP_DS_PORT_TYPE_VGA:
480 case DP_DS_PORT_TYPE_DVI:
481 case DP_DS_PORT_TYPE_HDMI:
482 case DP_DS_PORT_TYPE_DP_DUALMODE:
483 bpc = port_cap[2] & DP_DS_MAX_BPC_MASK;
500 EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
503 * drm_dp_downstream_id() - identify branch device
504 * @aux: DisplayPort AUX channel
505 * @id: DisplayPort branch device id
507 * Returns branch device id on success or NULL on failure
509 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
511 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
513 EXPORT_SYMBOL(drm_dp_downstream_id);
516 * drm_dp_downstream_debug() - debug DP branch devices
517 * @m: pointer for debugfs file
518 * @dpcd: DisplayPort configuration data
519 * @port_cap: port capabilities
520 * @aux: DisplayPort AUX channel
523 void drm_dp_downstream_debug(struct seq_file *m,
524 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
525 const u8 port_cap[4], struct drm_dp_aux *aux)
527 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
528 DP_DETAILED_CAP_INFO_AVAILABLE;
534 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
535 bool branch_device = drm_dp_is_branch(dpcd);
537 seq_printf(m, "\tDP branch device present: %s\n",
538 branch_device ? "yes" : "no");
544 case DP_DS_PORT_TYPE_DP:
545 seq_puts(m, "\t\tType: DisplayPort\n");
547 case DP_DS_PORT_TYPE_VGA:
548 seq_puts(m, "\t\tType: VGA\n");
550 case DP_DS_PORT_TYPE_DVI:
551 seq_puts(m, "\t\tType: DVI\n");
553 case DP_DS_PORT_TYPE_HDMI:
554 seq_puts(m, "\t\tType: HDMI\n");
556 case DP_DS_PORT_TYPE_NON_EDID:
557 seq_puts(m, "\t\tType: others without EDID support\n");
559 case DP_DS_PORT_TYPE_DP_DUALMODE:
560 seq_puts(m, "\t\tType: DP++\n");
562 case DP_DS_PORT_TYPE_WIRELESS:
563 seq_puts(m, "\t\tType: Wireless\n");
566 seq_puts(m, "\t\tType: N/A\n");
569 memset(id, 0, sizeof(id));
570 drm_dp_downstream_id(aux, id);
571 seq_printf(m, "\t\tID: %s\n", id);
573 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1);
575 seq_printf(m, "\t\tHW: %d.%d\n",
576 (rev[0] & 0xf0) >> 4, rev[0] & 0xf);
578 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2);
580 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
582 if (detailed_cap_info) {
583 clk = drm_dp_downstream_max_clock(dpcd, port_cap);
586 if (type == DP_DS_PORT_TYPE_VGA)
587 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
589 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);
592 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap);
595 seq_printf(m, "\t\tMax bpc: %d\n", bpc);
598 EXPORT_SYMBOL(drm_dp_downstream_debug);
601 * I2C-over-AUX implementation
604 static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
606 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
607 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
608 I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
612 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
615 * In case of i2c defer or short i2c ack reply to a write,
616 * we need to switch to WRITE_STATUS_UPDATE to drain the
617 * rest of the message
619 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
620 msg->request &= DP_AUX_I2C_MOT;
621 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
625 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
626 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
627 #define AUX_STOP_LEN 4
628 #define AUX_CMD_LEN 4
629 #define AUX_ADDRESS_LEN 20
630 #define AUX_REPLY_PAD_LEN 4
631 #define AUX_LENGTH_LEN 8
634 * Calculate the duration of the AUX request/reply in usec. Gives the
635 * "best" case estimate, ie. successful while as short as possible.
637 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
639 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
640 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
642 if ((msg->request & DP_AUX_I2C_READ) == 0)
643 len += msg->size * 8;
648 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
650 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
651 AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
654 * For read we expect what was asked. For writes there will
655 * be 0 or 1 data bytes. Assume 0 for the "best" case.
657 if (msg->request & DP_AUX_I2C_READ)
658 len += msg->size * 8;
663 #define I2C_START_LEN 1
664 #define I2C_STOP_LEN 1
665 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
666 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
669 * Calculate the length of the i2c transfer in usec, assuming
670 * the i2c bus speed is as specified. Gives the the "worst"
671 * case estimate, ie. successful while as long as possible.
672 * Doesn't account the the "MOT" bit, and instead assumes each
673 * message includes a START, ADDRESS and STOP. Neither does it
674 * account for additional random variables such as clock stretching.
676 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
679 /* AUX bitrate is 1MHz, i2c bitrate as specified */
680 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
681 msg->size * I2C_DATA_LEN +
682 I2C_STOP_LEN) * 1000, i2c_speed_khz);
686 * Deterine how many retries should be attempted to successfully transfer
687 * the specified message, based on the estimated durations of the
688 * i2c and AUX transfers.
690 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
693 int aux_time_us = drm_dp_aux_req_duration(msg) +
694 drm_dp_aux_reply_duration(msg);
695 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
697 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
701 * FIXME currently assumes 10 kHz as some real world devices seem
702 * to require it. We should query/set the speed via DPCD if supported.
704 static int dp_aux_i2c_speed_khz __read_mostly = 10;
705 module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
706 MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
707 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
710 * Transfer a single I2C-over-AUX message and handle various error conditions,
711 * retrying the transaction as appropriate. It is assumed that the
712 * &drm_dp_aux.transfer function does not modify anything in the msg other than the
715 * Returns bytes transferred on success, or a negative error code on failure.
717 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
719 unsigned int retry, defer_i2c;
722 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
723 * is required to retry at least seven times upon receiving AUX_DEFER
724 * before giving up the AUX transaction.
726 * We also try to account for the i2c bus speed.
728 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
730 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
731 ret = aux->transfer(aux, msg);
737 * While timeouts can be errors, they're usually normal
738 * behavior (for instance, when a driver tries to
739 * communicate with a non-existant DisplayPort device).
740 * Avoid spamming the kernel log with timeout errors.
742 if (ret == -ETIMEDOUT)
743 DRM_DEBUG_KMS_RATELIMITED("%s: transaction timed out\n",
746 DRM_DEBUG_KMS("%s: transaction failed: %d\n",
752 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
753 case DP_AUX_NATIVE_REPLY_ACK:
755 * For I2C-over-AUX transactions this isn't enough, we
756 * need to check for the I2C ACK reply.
760 case DP_AUX_NATIVE_REPLY_NACK:
761 DRM_DEBUG_KMS("%s: native nack (result=%d, size=%zu)\n",
762 aux->name, ret, msg->size);
765 case DP_AUX_NATIVE_REPLY_DEFER:
766 DRM_DEBUG_KMS("%s: native defer\n", aux->name);
768 * We could check for I2C bit rate capabilities and if
769 * available adjust this interval. We could also be
770 * more careful with DP-to-legacy adapters where a
771 * long legacy cable may force very low I2C bit rates.
773 * For now just defer for long enough to hopefully be
774 * safe for all use-cases.
776 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
780 DRM_ERROR("%s: invalid native reply %#04x\n",
781 aux->name, msg->reply);
785 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
786 case DP_AUX_I2C_REPLY_ACK:
788 * Both native ACK and I2C ACK replies received. We
789 * can assume the transfer was successful.
791 if (ret != msg->size)
792 drm_dp_i2c_msg_write_status_update(msg);
795 case DP_AUX_I2C_REPLY_NACK:
796 DRM_DEBUG_KMS("%s: I2C nack (result=%d, size=%zu)\n",
797 aux->name, ret, msg->size);
798 aux->i2c_nack_count++;
801 case DP_AUX_I2C_REPLY_DEFER:
802 DRM_DEBUG_KMS("%s: I2C defer\n", aux->name);
803 /* DP Compliance Test 4.2.2.5 Requirement:
804 * Must have at least 7 retries for I2C defers on the
805 * transaction to pass this test
807 aux->i2c_defer_count++;
810 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
811 drm_dp_i2c_msg_write_status_update(msg);
816 DRM_ERROR("%s: invalid I2C reply %#04x\n",
817 aux->name, msg->reply);
822 DRM_DEBUG_KMS("%s: Too many retries, giving up\n", aux->name);
826 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
827 const struct i2c_msg *i2c_msg)
829 msg->request = (i2c_msg->flags & I2C_M_RD) ?
830 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
831 if (!(i2c_msg->flags & I2C_M_STOP))
832 msg->request |= DP_AUX_I2C_MOT;
836 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
838 * Returns an error code on failure, or a recommended transfer size on success.
840 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
842 int err, ret = orig_msg->size;
843 struct drm_dp_aux_msg msg = *orig_msg;
845 while (msg.size > 0) {
846 err = drm_dp_i2c_do_msg(aux, &msg);
848 return err == 0 ? -EPROTO : err;
850 if (err < msg.size && err < ret) {
851 DRM_DEBUG_KMS("%s: Partial I2C reply: requested %zu bytes got %d bytes\n",
852 aux->name, msg.size, err);
864 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
865 * packets to be as large as possible. If not, the I2C transactions never
866 * succeed. Hence the default is maximum.
868 static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
869 module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
870 MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
871 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
873 static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
876 struct drm_dp_aux *aux = adapter->algo_data;
878 unsigned transfer_size;
879 struct drm_dp_aux_msg msg;
882 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
884 memset(&msg, 0, sizeof(msg));
886 for (i = 0; i < num; i++) {
887 msg.address = msgs[i].addr;
888 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
889 /* Send a bare address packet to start the transaction.
890 * Zero sized messages specify an address only (bare
891 * address) transaction.
895 err = drm_dp_i2c_do_msg(aux, &msg);
898 * Reset msg.request in case in case it got
899 * changed into a WRITE_STATUS_UPDATE.
901 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
905 /* We want each transaction to be as large as possible, but
906 * we'll go to smaller sizes if the hardware gives us a
909 transfer_size = dp_aux_i2c_transfer_size;
910 for (j = 0; j < msgs[i].len; j += msg.size) {
911 msg.buffer = msgs[i].buf + j;
912 msg.size = min(transfer_size, msgs[i].len - j);
914 err = drm_dp_i2c_drain_msg(aux, &msg);
917 * Reset msg.request in case in case it got
918 * changed into a WRITE_STATUS_UPDATE.
920 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
931 /* Send a bare address packet to close out the transaction.
932 * Zero sized messages specify an address only (bare
933 * address) transaction.
935 msg.request &= ~DP_AUX_I2C_MOT;
938 (void)drm_dp_i2c_do_msg(aux, &msg);
943 static const struct i2c_algorithm drm_dp_i2c_algo = {
944 .functionality = drm_dp_i2c_functionality,
945 .master_xfer = drm_dp_i2c_xfer,
948 static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
950 return container_of(i2c, struct drm_dp_aux, ddc);
953 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
955 mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
958 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
960 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
963 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
965 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex);
968 static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
969 .lock_bus = lock_bus,
970 .trylock_bus = trylock_bus,
971 .unlock_bus = unlock_bus,
974 static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
979 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
983 WARN_ON(!(buf & DP_TEST_SINK_START));
985 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf);
989 count = buf & DP_TEST_COUNT_MASK;
990 if (count == aux->crc_count)
991 return -EAGAIN; /* No CRC yet */
993 aux->crc_count = count;
996 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes
997 * per component (RGB or CrYCb).
999 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6);
1006 static void drm_dp_aux_crc_work(struct work_struct *work)
1008 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,
1010 struct drm_crtc *crtc;
1015 if (WARN_ON(!aux->crtc))
1019 while (crtc->crc.opened) {
1020 drm_crtc_wait_one_vblank(crtc);
1021 if (!crtc->crc.opened)
1024 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1025 if (ret == -EAGAIN) {
1026 usleep_range(1000, 2000);
1027 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1030 if (ret == -EAGAIN) {
1031 DRM_DEBUG_KMS("%s: Get CRC failed after retrying: %d\n",
1035 DRM_DEBUG_KMS("%s: Failed to get a CRC: %d\n",
1040 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
1041 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
1042 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
1043 drm_crtc_add_crc_entry(crtc, false, 0, crcs);
1048 * drm_dp_remote_aux_init() - minimally initialise a remote aux channel
1049 * @aux: DisplayPort AUX channel
1051 * Used for remote aux channel in general. Merely initialize the crc work
1054 void drm_dp_remote_aux_init(struct drm_dp_aux *aux)
1056 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
1058 EXPORT_SYMBOL(drm_dp_remote_aux_init);
1061 * drm_dp_aux_init() - minimally initialise an aux channel
1062 * @aux: DisplayPort AUX channel
1064 * If you need to use the drm_dp_aux's i2c adapter prior to registering it
1065 * with the outside world, call drm_dp_aux_init() first. You must still
1066 * call drm_dp_aux_register() once the connector has been registered to
1067 * allow userspace access to the auxiliary DP channel.
1069 void drm_dp_aux_init(struct drm_dp_aux *aux)
1071 mutex_init(&aux->hw_mutex);
1072 mutex_init(&aux->cec.lock);
1073 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
1075 aux->ddc.algo = &drm_dp_i2c_algo;
1076 aux->ddc.algo_data = aux;
1077 aux->ddc.retries = 3;
1079 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
1081 EXPORT_SYMBOL(drm_dp_aux_init);
1084 * drm_dp_aux_register() - initialise and register aux channel
1085 * @aux: DisplayPort AUX channel
1087 * Automatically calls drm_dp_aux_init() if this hasn't been done yet.
1088 * This should only be called when the underlying &struct drm_connector is
1089 * initialiazed already. Therefore the best place to call this is from
1090 * &drm_connector_funcs.late_register. Not that drivers which don't follow this
1091 * will Oops when CONFIG_DRM_DP_AUX_CHARDEV is enabled.
1093 * Drivers which need to use the aux channel before that point (e.g. at driver
1094 * load time, before drm_dev_register() has been called) need to call
1095 * drm_dp_aux_init().
1097 * Returns 0 on success or a negative error code on failure.
1099 int drm_dp_aux_register(struct drm_dp_aux *aux)
1104 drm_dp_aux_init(aux);
1106 aux->ddc.class = I2C_CLASS_DDC;
1107 aux->ddc.owner = THIS_MODULE;
1108 aux->ddc.dev.parent = aux->dev;
1110 strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
1111 sizeof(aux->ddc.name));
1113 ret = drm_dp_aux_register_devnode(aux);
1117 ret = i2c_add_adapter(&aux->ddc);
1119 drm_dp_aux_unregister_devnode(aux);
1125 EXPORT_SYMBOL(drm_dp_aux_register);
1128 * drm_dp_aux_unregister() - unregister an AUX adapter
1129 * @aux: DisplayPort AUX channel
1131 void drm_dp_aux_unregister(struct drm_dp_aux *aux)
1133 drm_dp_aux_unregister_devnode(aux);
1134 i2c_del_adapter(&aux->ddc);
1136 EXPORT_SYMBOL(drm_dp_aux_unregister);
1138 #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
1141 * drm_dp_psr_setup_time() - PSR setup in time usec
1142 * @psr_cap: PSR capabilities from DPCD
1145 * PSR setup time for the panel in microseconds, negative
1146 * error code on failure.
1148 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
1150 static const u16 psr_setup_time_us[] = {
1151 PSR_SETUP_TIME(330),
1152 PSR_SETUP_TIME(275),
1153 PSR_SETUP_TIME(220),
1154 PSR_SETUP_TIME(165),
1155 PSR_SETUP_TIME(110),
1161 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
1162 if (i >= ARRAY_SIZE(psr_setup_time_us))
1165 return psr_setup_time_us[i];
1167 EXPORT_SYMBOL(drm_dp_psr_setup_time);
1169 #undef PSR_SETUP_TIME
1172 * drm_dp_start_crc() - start capture of frame CRCs
1173 * @aux: DisplayPort AUX channel
1174 * @crtc: CRTC displaying the frames whose CRCs are to be captured
1176 * Returns 0 on success or a negative error code on failure.
1178 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
1183 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1187 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START);
1193 schedule_work(&aux->crc_work);
1197 EXPORT_SYMBOL(drm_dp_start_crc);
1200 * drm_dp_stop_crc() - stop capture of frame CRCs
1201 * @aux: DisplayPort AUX channel
1203 * Returns 0 on success or a negative error code on failure.
1205 int drm_dp_stop_crc(struct drm_dp_aux *aux)
1210 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1214 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START);
1218 flush_work(&aux->crc_work);
1223 EXPORT_SYMBOL(drm_dp_stop_crc);
1232 #define OUI(first, second, third) { (first), (second), (third) }
1233 #define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
1234 { (first), (second), (third), (fourth), (fifth), (sixth) }
1236 #define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0)
1238 static const struct dpcd_quirk dpcd_quirk_list[] = {
1239 /* Analogix 7737 needs reduced M and N at HBR2 link rates */
1240 { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
1241 /* LG LP140WF6-SPM1 eDP panel */
1242 { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
1243 /* Apple panels need some additional handling to support PSR */
1244 { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
1245 /* CH7511 seems to leave SINK_COUNT zeroed */
1246 { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
1247 /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
1248 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
1249 /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
1250 { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
1256 * Get a bit mask of DPCD quirks for the sink/branch device identified by
1257 * ident. The quirk data is shared but it's up to the drivers to act on the
1260 * For now, only the OUI (first three bytes) is used, but this may be extended
1261 * to device identification string and hardware/firmware revisions later.
1264 drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
1266 const struct dpcd_quirk *quirk;
1269 u8 any_device[] = DEVICE_ID_ANY;
1271 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
1272 quirk = &dpcd_quirk_list[i];
1274 if (quirk->is_branch != is_branch)
1277 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
1280 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 &&
1281 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0)
1284 quirks |= quirk->quirks;
1290 #undef DEVICE_ID_ANY
1299 #define MFG(first, second) { (first), (second) }
1300 #define PROD_ID(first, second) { (first), (second) }
1303 * Some devices have unreliable OUIDs where they don't set the device ID
1304 * correctly, and as a result we need to use the EDID for finding additional
1305 * DP quirks in such cases.
1307 static const struct edid_quirk edid_quirk_list[] = {
1308 /* Optional 4K AMOLED panel in the ThinkPad X1 Extreme 2nd Generation
1309 * only supports DPCD backlight controls
1311 { MFG(0x4c, 0x83), PROD_ID(0x41, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
1313 * Some Dell CML 2020 systems have panels support both AUX and PWM
1314 * backlight control, and some only support AUX backlight control. All
1315 * said panels start up in AUX mode by default, and we don't have any
1316 * support for disabling HDR mode on these panels which would be
1317 * required to switch to PWM backlight control mode (plus, I'm not
1318 * even sure we want PWM backlight controls over DPCD backlight
1319 * controls anyway...). Until we have a better way of detecting these,
1320 * force DPCD backlight mode on all of them.
1322 { MFG(0x06, 0xaf), PROD_ID(0x9b, 0x32), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
1323 { MFG(0x06, 0xaf), PROD_ID(0xeb, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
1324 { MFG(0x4d, 0x10), PROD_ID(0xc7, 0x14), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
1325 { MFG(0x4d, 0x10), PROD_ID(0xe6, 0x14), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
1326 { MFG(0x4c, 0x83), PROD_ID(0x47, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
1333 * drm_dp_get_edid_quirks() - Check the EDID of a DP device to find additional
1334 * DP-specific quirks
1335 * @edid: The EDID to check
1337 * While OUIDs are meant to be used to recognize a DisplayPort device, a lot
1338 * of manufacturers don't seem to like following standards and neglect to fill
1339 * the dev-ID in, making it impossible to only use OUIDs for determining
1340 * quirks in some cases. This function can be used to check the EDID and look
1341 * up any additional DP quirks. The bits returned by this function correspond
1342 * to the quirk bits in &drm_dp_quirk.
1344 * Returns: a bitmask of quirks, if any. The driver can check this using
1345 * drm_dp_has_quirk().
1347 u32 drm_dp_get_edid_quirks(const struct edid *edid)
1349 const struct edid_quirk *quirk;
1356 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1357 quirk = &edid_quirk_list[i];
1358 if (memcmp(quirk->mfg_id, edid->mfg_id,
1359 sizeof(edid->mfg_id)) == 0 &&
1360 memcmp(quirk->prod_id, edid->prod_code,
1361 sizeof(edid->prod_code)) == 0)
1362 quirks |= quirk->quirks;
1365 DRM_DEBUG_KMS("DP sink: EDID mfg %*phD prod-ID %*phD quirks: 0x%04x\n",
1366 (int)sizeof(edid->mfg_id), edid->mfg_id,
1367 (int)sizeof(edid->prod_code), edid->prod_code, quirks);
1371 EXPORT_SYMBOL(drm_dp_get_edid_quirks);
1374 * drm_dp_read_desc - read sink/branch descriptor from DPCD
1375 * @aux: DisplayPort AUX channel
1376 * @desc: Device descriptor to fill from DPCD
1377 * @is_branch: true for branch devices, false for sink devices
1379 * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
1382 * Returns 0 on success or a negative error code on failure.
1384 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
1387 struct drm_dp_dpcd_ident *ident = &desc->ident;
1388 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
1389 int ret, dev_id_len;
1391 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
1395 desc->quirks = drm_dp_get_quirks(ident, is_branch);
1397 dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
1399 DRM_DEBUG_KMS("%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
1400 aux->name, is_branch ? "branch" : "sink",
1401 (int)sizeof(ident->oui), ident->oui,
1402 dev_id_len, ident->device_id,
1403 ident->hw_rev >> 4, ident->hw_rev & 0xf,
1404 ident->sw_major_rev, ident->sw_minor_rev,
1409 EXPORT_SYMBOL(drm_dp_read_desc);
1412 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
1413 * supported by the DSC sink.
1414 * @dsc_dpcd: DSC capabilities from DPCD
1415 * @is_edp: true if its eDP, false for DP
1417 * Read the slice capabilities DPCD register from DSC sink to get
1418 * the maximum slice count supported. This is used to populate
1419 * the DSC parameters in the &struct drm_dsc_config by the driver.
1420 * Driver creates an infoframe using these parameters to populate
1421 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
1422 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
1425 * Maximum slice count supported by DSC sink or 0 its invalid
1427 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
1430 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
1433 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */
1434 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
1436 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
1438 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
1441 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
1442 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
1444 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
1446 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
1448 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
1450 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
1452 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
1454 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
1456 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
1458 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
1460 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
1462 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
1468 EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
1471 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
1472 * @dsc_dpcd: DSC capabilities from DPCD
1474 * Read the DSC DPCD register to parse the line buffer depth in bits which is
1475 * number of bits of precision within the decoder line buffer supported by
1476 * the DSC sink. This is used to populate the DSC parameters in the
1477 * &struct drm_dsc_config by the driver.
1478 * Driver creates an infoframe using these parameters to populate
1479 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
1480 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
1483 * Line buffer depth supported by DSC panel or 0 its invalid
1485 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1487 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];
1489 switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
1490 case DP_DSC_LINE_BUF_BIT_DEPTH_9:
1492 case DP_DSC_LINE_BUF_BIT_DEPTH_10:
1494 case DP_DSC_LINE_BUF_BIT_DEPTH_11:
1496 case DP_DSC_LINE_BUF_BIT_DEPTH_12:
1498 case DP_DSC_LINE_BUF_BIT_DEPTH_13:
1500 case DP_DSC_LINE_BUF_BIT_DEPTH_14:
1502 case DP_DSC_LINE_BUF_BIT_DEPTH_15:
1504 case DP_DSC_LINE_BUF_BIT_DEPTH_16:
1506 case DP_DSC_LINE_BUF_BIT_DEPTH_8:
1512 EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
1515 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
1516 * values supported by the DSC sink.
1517 * @dsc_dpcd: DSC capabilities from DPCD
1518 * @dsc_bpc: An array to be filled by this helper with supported
1521 * Read the DSC DPCD from the sink device to parse the supported bits per
1522 * component values. This is used to populate the DSC parameters
1523 * in the &struct drm_dsc_config by the driver.
1524 * Driver creates an infoframe using these parameters to populate
1525 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
1526 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
1529 * Number of input BPC values parsed from the DPCD
1531 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
1535 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
1537 if (color_depth & DP_DSC_12_BPC)
1538 dsc_bpc[num_bpc++] = 12;
1539 if (color_depth & DP_DSC_10_BPC)
1540 dsc_bpc[num_bpc++] = 10;
1541 if (color_depth & DP_DSC_8_BPC)
1542 dsc_bpc[num_bpc++] = 8;
1546 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
1549 * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
1550 * @aux: DisplayPort AUX channel
1551 * @data: DP phy compliance test parameters.
1553 * Returns 0 on success or a negative error code on failure.
1555 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
1556 struct drm_dp_phy_test_params *data)
1561 err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
1564 data->link_rate = drm_dp_bw_code_to_link_rate(rate);
1566 err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
1569 data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
1571 if (lanes & DP_ENHANCED_FRAME_CAP)
1572 data->enhanced_frame_cap = true;
1574 err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
1578 switch (data->phy_pattern) {
1579 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
1580 err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
1581 &data->custom80, sizeof(data->custom80));
1586 case DP_PHY_TEST_PATTERN_CP2520:
1587 err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
1589 sizeof(data->hbr2_reset));
1596 EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
1599 * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
1600 * @aux: DisplayPort AUX channel
1601 * @data: DP phy compliance test parameters.
1602 * @dp_rev: DP revision to use for compliance testing
1604 * Returns 0 on success or a negative error code on failure.
1606 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
1607 struct drm_dp_phy_test_params *data, u8 dp_rev)
1613 link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
1614 link_config[1] = data->num_lanes;
1615 if (data->enhanced_frame_cap)
1616 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
1617 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
1621 test_pattern = data->phy_pattern;
1622 if (dp_rev < 0x12) {
1623 test_pattern = (test_pattern << 2) &
1624 DP_LINK_QUAL_PATTERN_11_MASK;
1625 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
1630 for (i = 0; i < data->num_lanes; i++) {
1631 err = drm_dp_dpcd_writeb(aux,
1632 DP_LINK_QUAL_LANE0_SET + i,
1641 EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
1643 static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
1645 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
1648 switch (pixelformat) {
1649 case DP_PIXELFORMAT_RGB:
1651 case DP_PIXELFORMAT_YUV444:
1653 case DP_PIXELFORMAT_YUV422:
1655 case DP_PIXELFORMAT_YUV420:
1657 case DP_PIXELFORMAT_Y_ONLY:
1659 case DP_PIXELFORMAT_RAW:
1666 static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
1667 enum dp_colorimetry colorimetry)
1669 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
1672 switch (colorimetry) {
1673 case DP_COLORIMETRY_DEFAULT:
1674 switch (pixelformat) {
1675 case DP_PIXELFORMAT_RGB:
1677 case DP_PIXELFORMAT_YUV444:
1678 case DP_PIXELFORMAT_YUV422:
1679 case DP_PIXELFORMAT_YUV420:
1681 case DP_PIXELFORMAT_Y_ONLY:
1682 return "DICOM PS3.14";
1683 case DP_PIXELFORMAT_RAW:
1684 return "Custom Color Profile";
1688 case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
1689 switch (pixelformat) {
1690 case DP_PIXELFORMAT_RGB:
1691 return "Wide Fixed";
1692 case DP_PIXELFORMAT_YUV444:
1693 case DP_PIXELFORMAT_YUV422:
1694 case DP_PIXELFORMAT_YUV420:
1699 case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
1700 switch (pixelformat) {
1701 case DP_PIXELFORMAT_RGB:
1702 return "Wide Float";
1703 case DP_PIXELFORMAT_YUV444:
1704 case DP_PIXELFORMAT_YUV422:
1705 case DP_PIXELFORMAT_YUV420:
1710 case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
1711 switch (pixelformat) {
1712 case DP_PIXELFORMAT_RGB:
1714 case DP_PIXELFORMAT_YUV444:
1715 case DP_PIXELFORMAT_YUV422:
1716 case DP_PIXELFORMAT_YUV420:
1721 case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
1722 switch (pixelformat) {
1723 case DP_PIXELFORMAT_RGB:
1725 case DP_PIXELFORMAT_YUV444:
1726 case DP_PIXELFORMAT_YUV422:
1727 case DP_PIXELFORMAT_YUV420:
1732 case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
1733 switch (pixelformat) {
1734 case DP_PIXELFORMAT_RGB:
1735 return "Custom Profile";
1736 case DP_PIXELFORMAT_YUV444:
1737 case DP_PIXELFORMAT_YUV422:
1738 case DP_PIXELFORMAT_YUV420:
1743 case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
1744 switch (pixelformat) {
1745 case DP_PIXELFORMAT_RGB:
1746 return "BT.2020 RGB";
1747 case DP_PIXELFORMAT_YUV444:
1748 case DP_PIXELFORMAT_YUV422:
1749 case DP_PIXELFORMAT_YUV420:
1750 return "BT.2020 CYCC";
1754 case DP_COLORIMETRY_BT2020_YCC:
1755 switch (pixelformat) {
1756 case DP_PIXELFORMAT_YUV444:
1757 case DP_PIXELFORMAT_YUV422:
1758 case DP_PIXELFORMAT_YUV420:
1759 return "BT.2020 YCC";
1768 static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
1770 switch (dynamic_range) {
1771 case DP_DYNAMIC_RANGE_VESA:
1772 return "VESA range";
1773 case DP_DYNAMIC_RANGE_CTA:
1780 static const char *dp_content_type_get_name(enum dp_content_type content_type)
1782 switch (content_type) {
1783 case DP_CONTENT_TYPE_NOT_DEFINED:
1784 return "Not defined";
1785 case DP_CONTENT_TYPE_GRAPHICS:
1787 case DP_CONTENT_TYPE_PHOTO:
1789 case DP_CONTENT_TYPE_VIDEO:
1791 case DP_CONTENT_TYPE_GAME:
1798 void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
1799 const struct drm_dp_vsc_sdp *vsc)
1801 #define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
1802 DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
1803 vsc->revision, vsc->length);
1804 DP_SDP_LOG(" pixelformat: %s\n",
1805 dp_pixelformat_get_name(vsc->pixelformat));
1806 DP_SDP_LOG(" colorimetry: %s\n",
1807 dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry));
1808 DP_SDP_LOG(" bpc: %u\n", vsc->bpc);
1809 DP_SDP_LOG(" dynamic range: %s\n",
1810 dp_dynamic_range_get_name(vsc->dynamic_range));
1811 DP_SDP_LOG(" content type: %s\n",
1812 dp_content_type_get_name(vsc->content_type));
1815 EXPORT_SYMBOL(drm_dp_vsc_sdp_log);