1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2011 Freescale Semiconductor, Inc.
9 /* Identification Registers */
10 #define HDMI_DESIGN_ID 0x0000
11 #define HDMI_REVISION_ID 0x0001
12 #define HDMI_PRODUCT_ID0 0x0002
13 #define HDMI_PRODUCT_ID1 0x0003
14 #define HDMI_CONFIG0_ID 0x0004
15 #define HDMI_CONFIG1_ID 0x0005
16 #define HDMI_CONFIG2_ID 0x0006
17 #define HDMI_CONFIG3_ID 0x0007
19 /* Interrupt Registers */
20 #define HDMI_IH_FC_STAT0 0x0100
21 #define HDMI_IH_FC_STAT1 0x0101
22 #define HDMI_IH_FC_STAT2 0x0102
23 #define HDMI_IH_AS_STAT0 0x0103
24 #define HDMI_IH_PHY_STAT0 0x0104
25 #define HDMI_IH_I2CM_STAT0 0x0105
26 #define HDMI_IH_CEC_STAT0 0x0106
27 #define HDMI_IH_VP_STAT0 0x0107
28 #define HDMI_IH_I2CMPHY_STAT0 0x0108
29 #define HDMI_IH_AHBDMAAUD_STAT0 0x0109
31 #define HDMI_IH_MUTE_FC_STAT0 0x0180
32 #define HDMI_IH_MUTE_FC_STAT1 0x0181
33 #define HDMI_IH_MUTE_FC_STAT2 0x0182
34 #define HDMI_IH_MUTE_AS_STAT0 0x0183
35 #define HDMI_IH_MUTE_PHY_STAT0 0x0184
36 #define HDMI_IH_MUTE_I2CM_STAT0 0x0185
37 #define HDMI_IH_MUTE_CEC_STAT0 0x0186
38 #define HDMI_IH_MUTE_VP_STAT0 0x0187
39 #define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188
40 #define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189
41 #define HDMI_IH_MUTE 0x01FF
43 /* Video Sample Registers */
44 #define HDMI_TX_INVID0 0x0200
45 #define HDMI_TX_INSTUFFING 0x0201
46 #define HDMI_TX_GYDATA0 0x0202
47 #define HDMI_TX_GYDATA1 0x0203
48 #define HDMI_TX_RCRDATA0 0x0204
49 #define HDMI_TX_RCRDATA1 0x0205
50 #define HDMI_TX_BCBDATA0 0x0206
51 #define HDMI_TX_BCBDATA1 0x0207
53 /* Video Packetizer Registers */
54 #define HDMI_VP_STATUS 0x0800
55 #define HDMI_VP_PR_CD 0x0801
56 #define HDMI_VP_STUFF 0x0802
57 #define HDMI_VP_REMAP 0x0803
58 #define HDMI_VP_CONF 0x0804
59 #define HDMI_VP_STAT 0x0805
60 #define HDMI_VP_INT 0x0806
61 #define HDMI_VP_MASK 0x0807
62 #define HDMI_VP_POL 0x0808
64 /* Frame Composer Registers */
65 #define HDMI_FC_INVIDCONF 0x1000
66 #define HDMI_FC_INHACTV0 0x1001
67 #define HDMI_FC_INHACTV1 0x1002
68 #define HDMI_FC_INHBLANK0 0x1003
69 #define HDMI_FC_INHBLANK1 0x1004
70 #define HDMI_FC_INVACTV0 0x1005
71 #define HDMI_FC_INVACTV1 0x1006
72 #define HDMI_FC_INVBLANK 0x1007
73 #define HDMI_FC_HSYNCINDELAY0 0x1008
74 #define HDMI_FC_HSYNCINDELAY1 0x1009
75 #define HDMI_FC_HSYNCINWIDTH0 0x100A
76 #define HDMI_FC_HSYNCINWIDTH1 0x100B
77 #define HDMI_FC_VSYNCINDELAY 0x100C
78 #define HDMI_FC_VSYNCINWIDTH 0x100D
79 #define HDMI_FC_INFREQ0 0x100E
80 #define HDMI_FC_INFREQ1 0x100F
81 #define HDMI_FC_INFREQ2 0x1010
82 #define HDMI_FC_CTRLDUR 0x1011
83 #define HDMI_FC_EXCTRLDUR 0x1012
84 #define HDMI_FC_EXCTRLSPAC 0x1013
85 #define HDMI_FC_CH0PREAM 0x1014
86 #define HDMI_FC_CH1PREAM 0x1015
87 #define HDMI_FC_CH2PREAM 0x1016
88 #define HDMI_FC_AVICONF3 0x1017
89 #define HDMI_FC_GCP 0x1018
90 #define HDMI_FC_AVICONF0 0x1019
91 #define HDMI_FC_AVICONF1 0x101A
92 #define HDMI_FC_AVICONF2 0x101B
93 #define HDMI_FC_AVIVID 0x101C
94 #define HDMI_FC_AVIETB0 0x101D
95 #define HDMI_FC_AVIETB1 0x101E
96 #define HDMI_FC_AVISBB0 0x101F
97 #define HDMI_FC_AVISBB1 0x1020
98 #define HDMI_FC_AVIELB0 0x1021
99 #define HDMI_FC_AVIELB1 0x1022
100 #define HDMI_FC_AVISRB0 0x1023
101 #define HDMI_FC_AVISRB1 0x1024
102 #define HDMI_FC_AUDICONF0 0x1025
103 #define HDMI_FC_AUDICONF1 0x1026
104 #define HDMI_FC_AUDICONF2 0x1027
105 #define HDMI_FC_AUDICONF3 0x1028
106 #define HDMI_FC_VSDIEEEID0 0x1029
107 #define HDMI_FC_VSDSIZE 0x102A
108 #define HDMI_FC_VSDIEEEID1 0x1030
109 #define HDMI_FC_VSDIEEEID2 0x1031
110 #define HDMI_FC_VSDPAYLOAD0 0x1032
111 #define HDMI_FC_VSDPAYLOAD1 0x1033
112 #define HDMI_FC_VSDPAYLOAD2 0x1034
113 #define HDMI_FC_VSDPAYLOAD3 0x1035
114 #define HDMI_FC_VSDPAYLOAD4 0x1036
115 #define HDMI_FC_VSDPAYLOAD5 0x1037
116 #define HDMI_FC_VSDPAYLOAD6 0x1038
117 #define HDMI_FC_VSDPAYLOAD7 0x1039
118 #define HDMI_FC_VSDPAYLOAD8 0x103A
119 #define HDMI_FC_VSDPAYLOAD9 0x103B
120 #define HDMI_FC_VSDPAYLOAD10 0x103C
121 #define HDMI_FC_VSDPAYLOAD11 0x103D
122 #define HDMI_FC_VSDPAYLOAD12 0x103E
123 #define HDMI_FC_VSDPAYLOAD13 0x103F
124 #define HDMI_FC_VSDPAYLOAD14 0x1040
125 #define HDMI_FC_VSDPAYLOAD15 0x1041
126 #define HDMI_FC_VSDPAYLOAD16 0x1042
127 #define HDMI_FC_VSDPAYLOAD17 0x1043
128 #define HDMI_FC_VSDPAYLOAD18 0x1044
129 #define HDMI_FC_VSDPAYLOAD19 0x1045
130 #define HDMI_FC_VSDPAYLOAD20 0x1046
131 #define HDMI_FC_VSDPAYLOAD21 0x1047
132 #define HDMI_FC_VSDPAYLOAD22 0x1048
133 #define HDMI_FC_VSDPAYLOAD23 0x1049
134 #define HDMI_FC_SPDVENDORNAME0 0x104A
135 #define HDMI_FC_SPDVENDORNAME1 0x104B
136 #define HDMI_FC_SPDVENDORNAME2 0x104C
137 #define HDMI_FC_SPDVENDORNAME3 0x104D
138 #define HDMI_FC_SPDVENDORNAME4 0x104E
139 #define HDMI_FC_SPDVENDORNAME5 0x104F
140 #define HDMI_FC_SPDVENDORNAME6 0x1050
141 #define HDMI_FC_SPDVENDORNAME7 0x1051
142 #define HDMI_FC_SDPPRODUCTNAME0 0x1052
143 #define HDMI_FC_SDPPRODUCTNAME1 0x1053
144 #define HDMI_FC_SDPPRODUCTNAME2 0x1054
145 #define HDMI_FC_SDPPRODUCTNAME3 0x1055
146 #define HDMI_FC_SDPPRODUCTNAME4 0x1056
147 #define HDMI_FC_SDPPRODUCTNAME5 0x1057
148 #define HDMI_FC_SDPPRODUCTNAME6 0x1058
149 #define HDMI_FC_SDPPRODUCTNAME7 0x1059
150 #define HDMI_FC_SDPPRODUCTNAME8 0x105A
151 #define HDMI_FC_SDPPRODUCTNAME9 0x105B
152 #define HDMI_FC_SDPPRODUCTNAME10 0x105C
153 #define HDMI_FC_SDPPRODUCTNAME11 0x105D
154 #define HDMI_FC_SDPPRODUCTNAME12 0x105E
155 #define HDMI_FC_SDPPRODUCTNAME13 0x105F
156 #define HDMI_FC_SDPPRODUCTNAME14 0x1060
157 #define HDMI_FC_SPDPRODUCTNAME15 0x1061
158 #define HDMI_FC_SPDDEVICEINF 0x1062
159 #define HDMI_FC_AUDSCONF 0x1063
160 #define HDMI_FC_AUDSSTAT 0x1064
161 #define HDMI_FC_AUDSCHNLS7 0x106e
162 #define HDMI_FC_AUDSCHNLS8 0x106f
163 #define HDMI_FC_DATACH0FILL 0x1070
164 #define HDMI_FC_DATACH1FILL 0x1071
165 #define HDMI_FC_DATACH2FILL 0x1072
166 #define HDMI_FC_CTRLQHIGH 0x1073
167 #define HDMI_FC_CTRLQLOW 0x1074
168 #define HDMI_FC_ACP0 0x1075
169 #define HDMI_FC_ACP28 0x1076
170 #define HDMI_FC_ACP27 0x1077
171 #define HDMI_FC_ACP26 0x1078
172 #define HDMI_FC_ACP25 0x1079
173 #define HDMI_FC_ACP24 0x107A
174 #define HDMI_FC_ACP23 0x107B
175 #define HDMI_FC_ACP22 0x107C
176 #define HDMI_FC_ACP21 0x107D
177 #define HDMI_FC_ACP20 0x107E
178 #define HDMI_FC_ACP19 0x107F
179 #define HDMI_FC_ACP18 0x1080
180 #define HDMI_FC_ACP17 0x1081
181 #define HDMI_FC_ACP16 0x1082
182 #define HDMI_FC_ACP15 0x1083
183 #define HDMI_FC_ACP14 0x1084
184 #define HDMI_FC_ACP13 0x1085
185 #define HDMI_FC_ACP12 0x1086
186 #define HDMI_FC_ACP11 0x1087
187 #define HDMI_FC_ACP10 0x1088
188 #define HDMI_FC_ACP9 0x1089
189 #define HDMI_FC_ACP8 0x108A
190 #define HDMI_FC_ACP7 0x108B
191 #define HDMI_FC_ACP6 0x108C
192 #define HDMI_FC_ACP5 0x108D
193 #define HDMI_FC_ACP4 0x108E
194 #define HDMI_FC_ACP3 0x108F
195 #define HDMI_FC_ACP2 0x1090
196 #define HDMI_FC_ACP1 0x1091
197 #define HDMI_FC_ISCR1_0 0x1092
198 #define HDMI_FC_ISCR1_16 0x1093
199 #define HDMI_FC_ISCR1_15 0x1094
200 #define HDMI_FC_ISCR1_14 0x1095
201 #define HDMI_FC_ISCR1_13 0x1096
202 #define HDMI_FC_ISCR1_12 0x1097
203 #define HDMI_FC_ISCR1_11 0x1098
204 #define HDMI_FC_ISCR1_10 0x1099
205 #define HDMI_FC_ISCR1_9 0x109A
206 #define HDMI_FC_ISCR1_8 0x109B
207 #define HDMI_FC_ISCR1_7 0x109C
208 #define HDMI_FC_ISCR1_6 0x109D
209 #define HDMI_FC_ISCR1_5 0x109E
210 #define HDMI_FC_ISCR1_4 0x109F
211 #define HDMI_FC_ISCR1_3 0x10A0
212 #define HDMI_FC_ISCR1_2 0x10A1
213 #define HDMI_FC_ISCR1_1 0x10A2
214 #define HDMI_FC_ISCR2_15 0x10A3
215 #define HDMI_FC_ISCR2_14 0x10A4
216 #define HDMI_FC_ISCR2_13 0x10A5
217 #define HDMI_FC_ISCR2_12 0x10A6
218 #define HDMI_FC_ISCR2_11 0x10A7
219 #define HDMI_FC_ISCR2_10 0x10A8
220 #define HDMI_FC_ISCR2_9 0x10A9
221 #define HDMI_FC_ISCR2_8 0x10AA
222 #define HDMI_FC_ISCR2_7 0x10AB
223 #define HDMI_FC_ISCR2_6 0x10AC
224 #define HDMI_FC_ISCR2_5 0x10AD
225 #define HDMI_FC_ISCR2_4 0x10AE
226 #define HDMI_FC_ISCR2_3 0x10AF
227 #define HDMI_FC_ISCR2_2 0x10B0
228 #define HDMI_FC_ISCR2_1 0x10B1
229 #define HDMI_FC_ISCR2_0 0x10B2
230 #define HDMI_FC_DATAUTO0 0x10B3
231 #define HDMI_FC_DATAUTO1 0x10B4
232 #define HDMI_FC_DATAUTO2 0x10B5
233 #define HDMI_FC_DATMAN 0x10B6
234 #define HDMI_FC_DATAUTO3 0x10B7
235 #define HDMI_FC_RDRB0 0x10B8
236 #define HDMI_FC_RDRB1 0x10B9
237 #define HDMI_FC_RDRB2 0x10BA
238 #define HDMI_FC_RDRB3 0x10BB
239 #define HDMI_FC_RDRB4 0x10BC
240 #define HDMI_FC_RDRB5 0x10BD
241 #define HDMI_FC_RDRB6 0x10BE
242 #define HDMI_FC_RDRB7 0x10BF
243 #define HDMI_FC_STAT0 0x10D0
244 #define HDMI_FC_INT0 0x10D1
245 #define HDMI_FC_MASK0 0x10D2
246 #define HDMI_FC_POL0 0x10D3
247 #define HDMI_FC_STAT1 0x10D4
248 #define HDMI_FC_INT1 0x10D5
249 #define HDMI_FC_MASK1 0x10D6
250 #define HDMI_FC_POL1 0x10D7
251 #define HDMI_FC_STAT2 0x10D8
252 #define HDMI_FC_INT2 0x10D9
253 #define HDMI_FC_MASK2 0x10DA
254 #define HDMI_FC_POL2 0x10DB
255 #define HDMI_FC_PRCONF 0x10E0
256 #define HDMI_FC_SCRAMBLER_CTRL 0x10E1
258 #define HDMI_FC_GMD_STAT 0x1100
259 #define HDMI_FC_GMD_EN 0x1101
260 #define HDMI_FC_GMD_UP 0x1102
261 #define HDMI_FC_GMD_CONF 0x1103
262 #define HDMI_FC_GMD_HB 0x1104
263 #define HDMI_FC_GMD_PB0 0x1105
264 #define HDMI_FC_GMD_PB1 0x1106
265 #define HDMI_FC_GMD_PB2 0x1107
266 #define HDMI_FC_GMD_PB3 0x1108
267 #define HDMI_FC_GMD_PB4 0x1109
268 #define HDMI_FC_GMD_PB5 0x110A
269 #define HDMI_FC_GMD_PB6 0x110B
270 #define HDMI_FC_GMD_PB7 0x110C
271 #define HDMI_FC_GMD_PB8 0x110D
272 #define HDMI_FC_GMD_PB9 0x110E
273 #define HDMI_FC_GMD_PB10 0x110F
274 #define HDMI_FC_GMD_PB11 0x1110
275 #define HDMI_FC_GMD_PB12 0x1111
276 #define HDMI_FC_GMD_PB13 0x1112
277 #define HDMI_FC_GMD_PB14 0x1113
278 #define HDMI_FC_GMD_PB15 0x1114
279 #define HDMI_FC_GMD_PB16 0x1115
280 #define HDMI_FC_GMD_PB17 0x1116
281 #define HDMI_FC_GMD_PB18 0x1117
282 #define HDMI_FC_GMD_PB19 0x1118
283 #define HDMI_FC_GMD_PB20 0x1119
284 #define HDMI_FC_GMD_PB21 0x111A
285 #define HDMI_FC_GMD_PB22 0x111B
286 #define HDMI_FC_GMD_PB23 0x111C
287 #define HDMI_FC_GMD_PB24 0x111D
288 #define HDMI_FC_GMD_PB25 0x111E
289 #define HDMI_FC_GMD_PB26 0x111F
290 #define HDMI_FC_GMD_PB27 0x1120
292 #define HDMI_FC_DBGFORCE 0x1200
293 #define HDMI_FC_DBGAUD0CH0 0x1201
294 #define HDMI_FC_DBGAUD1CH0 0x1202
295 #define HDMI_FC_DBGAUD2CH0 0x1203
296 #define HDMI_FC_DBGAUD0CH1 0x1204
297 #define HDMI_FC_DBGAUD1CH1 0x1205
298 #define HDMI_FC_DBGAUD2CH1 0x1206
299 #define HDMI_FC_DBGAUD0CH2 0x1207
300 #define HDMI_FC_DBGAUD1CH2 0x1208
301 #define HDMI_FC_DBGAUD2CH2 0x1209
302 #define HDMI_FC_DBGAUD0CH3 0x120A
303 #define HDMI_FC_DBGAUD1CH3 0x120B
304 #define HDMI_FC_DBGAUD2CH3 0x120C
305 #define HDMI_FC_DBGAUD0CH4 0x120D
306 #define HDMI_FC_DBGAUD1CH4 0x120E
307 #define HDMI_FC_DBGAUD2CH4 0x120F
308 #define HDMI_FC_DBGAUD0CH5 0x1210
309 #define HDMI_FC_DBGAUD1CH5 0x1211
310 #define HDMI_FC_DBGAUD2CH5 0x1212
311 #define HDMI_FC_DBGAUD0CH6 0x1213
312 #define HDMI_FC_DBGAUD1CH6 0x1214
313 #define HDMI_FC_DBGAUD2CH6 0x1215
314 #define HDMI_FC_DBGAUD0CH7 0x1216
315 #define HDMI_FC_DBGAUD1CH7 0x1217
316 #define HDMI_FC_DBGAUD2CH7 0x1218
317 #define HDMI_FC_DBGTMDS0 0x1219
318 #define HDMI_FC_DBGTMDS1 0x121A
319 #define HDMI_FC_DBGTMDS2 0x121B
321 /* HDMI Source PHY Registers */
322 #define HDMI_PHY_CONF0 0x3000
323 #define HDMI_PHY_TST0 0x3001
324 #define HDMI_PHY_TST1 0x3002
325 #define HDMI_PHY_TST2 0x3003
326 #define HDMI_PHY_STAT0 0x3004
327 #define HDMI_PHY_INT0 0x3005
328 #define HDMI_PHY_MASK0 0x3006
329 #define HDMI_PHY_POL0 0x3007
331 /* HDMI Master PHY Registers */
332 #define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020
333 #define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021
334 #define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022
335 #define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023
336 #define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024
337 #define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025
338 #define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026
339 #define HDMI_PHY_I2CM_INT_ADDR 0x3027
340 #define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028
341 #define HDMI_PHY_I2CM_DIV_ADDR 0x3029
342 #define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a
343 #define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b
344 #define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c
345 #define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d
346 #define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e
347 #define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f
348 #define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030
349 #define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031
350 #define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032
352 /* Audio Sampler Registers */
353 #define HDMI_AUD_CONF0 0x3100
354 #define HDMI_AUD_CONF1 0x3101
355 #define HDMI_AUD_INT 0x3102
356 #define HDMI_AUD_CONF2 0x3103
357 #define HDMI_AUD_N1 0x3200
358 #define HDMI_AUD_N2 0x3201
359 #define HDMI_AUD_N3 0x3202
360 #define HDMI_AUD_CTS1 0x3203
361 #define HDMI_AUD_CTS2 0x3204
362 #define HDMI_AUD_CTS3 0x3205
363 #define HDMI_AUD_INPUTCLKFS 0x3206
364 #define HDMI_AUD_SPDIFINT 0x3302
365 #define HDMI_AUD_CONF0_HBR 0x3400
366 #define HDMI_AUD_HBR_STATUS 0x3401
367 #define HDMI_AUD_HBR_INT 0x3402
368 #define HDMI_AUD_HBR_POL 0x3403
369 #define HDMI_AUD_HBR_MASK 0x3404
372 * Generic Parallel Audio Interface Registers
373 * Not used as GPAUD interface is not enabled in hw
375 #define HDMI_GP_CONF0 0x3500
376 #define HDMI_GP_CONF1 0x3501
377 #define HDMI_GP_CONF2 0x3502
378 #define HDMI_GP_STAT 0x3503
379 #define HDMI_GP_INT 0x3504
380 #define HDMI_GP_MASK 0x3505
381 #define HDMI_GP_POL 0x3506
383 /* Audio DMA Registers */
384 #define HDMI_AHB_DMA_CONF0 0x3600
385 #define HDMI_AHB_DMA_START 0x3601
386 #define HDMI_AHB_DMA_STOP 0x3602
387 #define HDMI_AHB_DMA_THRSLD 0x3603
388 #define HDMI_AHB_DMA_STRADDR0 0x3604
389 #define HDMI_AHB_DMA_STRADDR1 0x3605
390 #define HDMI_AHB_DMA_STRADDR2 0x3606
391 #define HDMI_AHB_DMA_STRADDR3 0x3607
392 #define HDMI_AHB_DMA_STPADDR0 0x3608
393 #define HDMI_AHB_DMA_STPADDR1 0x3609
394 #define HDMI_AHB_DMA_STPADDR2 0x360a
395 #define HDMI_AHB_DMA_STPADDR3 0x360b
396 #define HDMI_AHB_DMA_BSTADDR0 0x360c
397 #define HDMI_AHB_DMA_BSTADDR1 0x360d
398 #define HDMI_AHB_DMA_BSTADDR2 0x360e
399 #define HDMI_AHB_DMA_BSTADDR3 0x360f
400 #define HDMI_AHB_DMA_MBLENGTH0 0x3610
401 #define HDMI_AHB_DMA_MBLENGTH1 0x3611
402 #define HDMI_AHB_DMA_STAT 0x3612
403 #define HDMI_AHB_DMA_INT 0x3613
404 #define HDMI_AHB_DMA_MASK 0x3614
405 #define HDMI_AHB_DMA_POL 0x3615
406 #define HDMI_AHB_DMA_CONF1 0x3616
407 #define HDMI_AHB_DMA_BUFFSTAT 0x3617
408 #define HDMI_AHB_DMA_BUFFINT 0x3618
409 #define HDMI_AHB_DMA_BUFFMASK 0x3619
410 #define HDMI_AHB_DMA_BUFFPOL 0x361a
412 /* Main Controller Registers */
413 #define HDMI_MC_SFRDIV 0x4000
414 #define HDMI_MC_CLKDIS 0x4001
415 #define HDMI_MC_SWRSTZ 0x4002
416 #define HDMI_MC_OPCTRL 0x4003
417 #define HDMI_MC_FLOWCTRL 0x4004
418 #define HDMI_MC_PHYRSTZ 0x4005
419 #define HDMI_MC_LOCKONCLOCK 0x4006
420 #define HDMI_MC_HEACPHY_RST 0x4007
422 /* Color Space Converter Registers */
423 #define HDMI_CSC_CFG 0x4100
424 #define HDMI_CSC_SCALE 0x4101
425 #define HDMI_CSC_COEF_A1_MSB 0x4102
426 #define HDMI_CSC_COEF_A1_LSB 0x4103
427 #define HDMI_CSC_COEF_A2_MSB 0x4104
428 #define HDMI_CSC_COEF_A2_LSB 0x4105
429 #define HDMI_CSC_COEF_A3_MSB 0x4106
430 #define HDMI_CSC_COEF_A3_LSB 0x4107
431 #define HDMI_CSC_COEF_A4_MSB 0x4108
432 #define HDMI_CSC_COEF_A4_LSB 0x4109
433 #define HDMI_CSC_COEF_B1_MSB 0x410A
434 #define HDMI_CSC_COEF_B1_LSB 0x410B
435 #define HDMI_CSC_COEF_B2_MSB 0x410C
436 #define HDMI_CSC_COEF_B2_LSB 0x410D
437 #define HDMI_CSC_COEF_B3_MSB 0x410E
438 #define HDMI_CSC_COEF_B3_LSB 0x410F
439 #define HDMI_CSC_COEF_B4_MSB 0x4110
440 #define HDMI_CSC_COEF_B4_LSB 0x4111
441 #define HDMI_CSC_COEF_C1_MSB 0x4112
442 #define HDMI_CSC_COEF_C1_LSB 0x4113
443 #define HDMI_CSC_COEF_C2_MSB 0x4114
444 #define HDMI_CSC_COEF_C2_LSB 0x4115
445 #define HDMI_CSC_COEF_C3_MSB 0x4116
446 #define HDMI_CSC_COEF_C3_LSB 0x4117
447 #define HDMI_CSC_COEF_C4_MSB 0x4118
448 #define HDMI_CSC_COEF_C4_LSB 0x4119
450 /* HDCP Encryption Engine Registers */
451 #define HDMI_A_HDCPCFG0 0x5000
452 #define HDMI_A_HDCPCFG1 0x5001
453 #define HDMI_A_HDCPOBS0 0x5002
454 #define HDMI_A_HDCPOBS1 0x5003
455 #define HDMI_A_HDCPOBS2 0x5004
456 #define HDMI_A_HDCPOBS3 0x5005
457 #define HDMI_A_APIINTCLR 0x5006
458 #define HDMI_A_APIINTSTAT 0x5007
459 #define HDMI_A_APIINTMSK 0x5008
460 #define HDMI_A_VIDPOLCFG 0x5009
461 #define HDMI_A_OESSWCFG 0x500A
462 #define HDMI_A_TIMER1SETUP0 0x500B
463 #define HDMI_A_TIMER1SETUP1 0x500C
464 #define HDMI_A_TIMER2SETUP0 0x500D
465 #define HDMI_A_TIMER2SETUP1 0x500E
466 #define HDMI_A_100MSCFG 0x500F
467 #define HDMI_A_2SCFG0 0x5010
468 #define HDMI_A_2SCFG1 0x5011
469 #define HDMI_A_5SCFG0 0x5012
470 #define HDMI_A_5SCFG1 0x5013
471 #define HDMI_A_SRMVERLSB 0x5014
472 #define HDMI_A_SRMVERMSB 0x5015
473 #define HDMI_A_SRMCTRL 0x5016
474 #define HDMI_A_SFRSETUP 0x5017
475 #define HDMI_A_I2CHSETUP 0x5018
476 #define HDMI_A_INTSETUP 0x5019
477 #define HDMI_A_PRESETUP 0x501A
478 #define HDMI_A_SRM_BASE 0x5020
480 /* I2C Master Registers (E-DDC) */
481 #define HDMI_I2CM_SLAVE 0x7E00
482 #define HDMI_I2CM_ADDRESS 0x7E01
483 #define HDMI_I2CM_DATAO 0x7E02
484 #define HDMI_I2CM_DATAI 0x7E03
485 #define HDMI_I2CM_OPERATION 0x7E04
486 #define HDMI_I2CM_INT 0x7E05
487 #define HDMI_I2CM_CTLINT 0x7E06
488 #define HDMI_I2CM_DIV 0x7E07
489 #define HDMI_I2CM_SEGADDR 0x7E08
490 #define HDMI_I2CM_SOFTRSTZ 0x7E09
491 #define HDMI_I2CM_SEGPTR 0x7E0A
492 #define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B
493 #define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C
494 #define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D
495 #define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E
496 #define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F
497 #define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10
498 #define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11
499 #define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12
502 /* PRODUCT_ID0 field values */
503 HDMI_PRODUCT_ID0_HDMI_TX = 0xa0,
505 /* PRODUCT_ID1 field values */
506 HDMI_PRODUCT_ID1_HDCP = 0xc0,
507 HDMI_PRODUCT_ID1_HDMI_RX = 0x02,
508 HDMI_PRODUCT_ID1_HDMI_TX = 0x01,
510 /* CONFIG0_ID field values */
511 HDMI_CONFIG0_I2S = 0x10,
512 HDMI_CONFIG0_CEC = 0x02,
514 /* CONFIG1_ID field values */
515 HDMI_CONFIG1_AHB = 0x01,
517 /* CONFIG3_ID field values */
518 HDMI_CONFIG3_AHBAUDDMA = 0x02,
519 HDMI_CONFIG3_GPAUD = 0x01,
521 /* IH_FC_INT2 field values */
522 HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03,
523 HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
524 HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
526 /* IH_FC_STAT2 field values */
527 HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03,
528 HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
529 HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
531 /* IH_PHY_STAT0 field values */
532 HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20,
533 HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10,
534 HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8,
535 HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4,
536 HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2,
537 HDMI_IH_PHY_STAT0_HPD = 0x1,
539 /* IH_I2CM_STAT0 and IH_MUTE_I2CM_STAT0 field values */
540 HDMI_IH_I2CM_STAT0_DONE = 0x2,
541 HDMI_IH_I2CM_STAT0_ERROR = 0x1,
543 /* IH_MUTE_I2CMPHY_STAT0 field values */
544 HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2,
545 HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1,
547 /* IH_AHBDMAAUD_STAT0 field values */
548 HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
549 HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
550 HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08,
551 HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04,
552 HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
553 HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
555 /* IH_MUTE_FC_STAT2 field values */
556 HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03,
557 HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
558 HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
560 /* IH_MUTE_AHBDMAAUD_STAT0 field values */
561 HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20,
562 HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10,
563 HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08,
564 HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04,
565 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
566 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
568 /* IH_MUTE field values */
569 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
570 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
572 /* TX_INVID0 field values */
573 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80,
574 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80,
575 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
576 HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F,
577 HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
579 /* TX_INSTUFFING field values */
580 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4,
581 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
582 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0,
583 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2,
584 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
585 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0,
586 HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1,
587 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
588 HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0,
590 /* VP_PR_CD field values */
591 HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0,
592 HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
593 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F,
594 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
596 /* VP_STUFF field values */
597 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
598 HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
599 HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10,
600 HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4,
601 HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8,
602 HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3,
603 HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
604 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
605 HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0,
606 HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
607 HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
608 HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0,
609 HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
610 HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
611 HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0,
613 /* VP_CONF field values */
614 HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
615 HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
616 HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00,
617 HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
618 HDMI_VP_CONF_PP_EN_ENABLE = 0x20,
619 HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
620 HDMI_VP_CONF_PR_EN_MASK = 0x10,
621 HDMI_VP_CONF_PR_EN_ENABLE = 0x10,
622 HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
623 HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
624 HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8,
625 HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
626 HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
627 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
628 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0,
629 HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
630 HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
631 HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1,
632 HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0,
634 /* VP_REMAP field values */
635 HDMI_VP_REMAP_MASK = 0x3,
636 HDMI_VP_REMAP_YCC422_24bit = 0x2,
637 HDMI_VP_REMAP_YCC422_20bit = 0x1,
638 HDMI_VP_REMAP_YCC422_16bit = 0x0,
640 /* FC_INVIDCONF field values */
641 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
642 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
643 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
644 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
645 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
646 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
647 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
648 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
649 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
650 HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
651 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
652 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
653 HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
654 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
655 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
656 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
657 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
658 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
659 HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
660 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
661 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
663 /* FC_AUDICONF0 field values */
664 HDMI_FC_AUDICONF0_CC_OFFSET = 4,
665 HDMI_FC_AUDICONF0_CC_MASK = 0x70,
666 HDMI_FC_AUDICONF0_CT_OFFSET = 0,
667 HDMI_FC_AUDICONF0_CT_MASK = 0xF,
669 /* FC_AUDICONF1 field values */
670 HDMI_FC_AUDICONF1_SS_OFFSET = 3,
671 HDMI_FC_AUDICONF1_SS_MASK = 0x18,
672 HDMI_FC_AUDICONF1_SF_OFFSET = 0,
673 HDMI_FC_AUDICONF1_SF_MASK = 0x7,
675 /* FC_AUDICONF3 field values */
676 HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5,
677 HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60,
678 HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4,
679 HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10,
680 HDMI_FC_AUDICONF3_LSV_OFFSET = 0,
681 HDMI_FC_AUDICONF3_LSV_MASK = 0xF,
683 /* FC_AUDSCHNLS0 field values */
684 HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4,
685 HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30,
686 HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0,
687 HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01,
689 /* FC_AUDSCHNLS3-6 field values */
690 HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0,
691 HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f,
692 HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4,
693 HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0,
694 HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0,
695 HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f,
696 HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4,
697 HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0,
699 HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0,
700 HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f,
701 HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4,
702 HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0,
703 HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0,
704 HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f,
705 HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4,
706 HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0,
708 /* HDMI_FC_AUDSCHNLS7 field values */
709 HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
710 HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
712 /* HDMI_FC_AUDSCHNLS8 field values */
713 HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
714 HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
715 HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
716 HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
718 /* FC_AUDSCONF field values */
719 HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
720 HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4,
721 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1,
722 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0,
723 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1,
724 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0,
726 /* FC_STAT2 field values */
727 HDMI_FC_STAT2_OVERFLOW_MASK = 0x03,
728 HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
729 HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
731 /* FC_INT2 field values */
732 HDMI_FC_INT2_OVERFLOW_MASK = 0x03,
733 HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
734 HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
736 /* FC_MASK2 field values */
737 HDMI_FC_MASK2_OVERFLOW_MASK = 0x03,
738 HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02,
739 HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01,
741 /* FC_PRCONF field values */
742 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0,
743 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4,
744 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F,
745 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
747 /* FC_AVICONF0-FC_AVICONF3 field values */
748 HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
749 HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
750 HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
751 HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
752 HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
753 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
754 HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
755 HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C,
756 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
757 HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
758 HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
759 HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C,
760 HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
761 HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
762 HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
763 HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
765 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F,
766 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
767 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
768 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A,
769 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B,
770 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
771 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
772 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
773 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
774 HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0,
775 HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
776 HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
777 HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
778 HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0,
780 HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
781 HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
782 HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
783 HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
784 HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03,
785 HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C,
786 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
787 HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
788 HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
789 HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
790 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
791 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
792 HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
793 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
794 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
795 HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
796 HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
797 HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
799 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
800 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
801 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
802 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
803 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
804 HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C,
805 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
806 HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
808 /* FC_DBGFORCE field values */
809 HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
810 HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
812 /* FC_DATAUTO0 field values */
813 HDMI_FC_DATAUTO0_VSD_MASK = 0x08,
814 HDMI_FC_DATAUTO0_VSD_OFFSET = 3,
816 /* PHY_CONF0 field values */
817 HDMI_PHY_CONF0_PDZ_MASK = 0x80,
818 HDMI_PHY_CONF0_PDZ_OFFSET = 7,
819 HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
820 HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
821 HDMI_PHY_CONF0_SVSRET_MASK = 0x20,
822 HDMI_PHY_CONF0_SVSRET_OFFSET = 5,
823 HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
824 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
825 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
826 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
827 HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4,
828 HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2,
829 HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
830 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
831 HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
832 HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
834 /* PHY_TST0 field values */
835 HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
836 HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
837 HDMI_PHY_TST0_TSTEN_MASK = 0x10,
838 HDMI_PHY_TST0_TSTEN_OFFSET = 4,
839 HDMI_PHY_TST0_TSTCLK_MASK = 0x1,
840 HDMI_PHY_TST0_TSTCLK_OFFSET = 0,
842 /* PHY_STAT0 field values */
843 HDMI_PHY_RX_SENSE3 = 0x80,
844 HDMI_PHY_RX_SENSE2 = 0x40,
845 HDMI_PHY_RX_SENSE1 = 0x20,
846 HDMI_PHY_RX_SENSE0 = 0x10,
848 HDMI_PHY_TX_PHY_LOCK = 0x01,
850 /* PHY_I2CM_SLAVE_ADDR field values */
851 HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
852 HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
854 /* PHY_I2CM_OPERATION_ADDR field values */
855 HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
856 HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1,
858 /* HDMI_PHY_I2CM_INT_ADDR */
859 HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
860 HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04,
862 /* HDMI_PHY_I2CM_CTLINT_ADDR */
863 HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
864 HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40,
865 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
866 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04,
868 /* AUD_CONF0 field values */
869 HDMI_AUD_CONF0_SW_RESET = 0x80,
870 HDMI_AUD_CONF0_I2S_SELECT = 0x20,
871 HDMI_AUD_CONF0_I2S_EN3 = 0x08,
872 HDMI_AUD_CONF0_I2S_EN2 = 0x04,
873 HDMI_AUD_CONF0_I2S_EN1 = 0x02,
874 HDMI_AUD_CONF0_I2S_EN0 = 0x01,
876 /* AUD_CONF1 field values */
877 HDMI_AUD_CONF1_MODE_I2S = 0x00,
878 HDMI_AUD_CONF1_MODE_RIGHT_J = 0x20,
879 HDMI_AUD_CONF1_MODE_LEFT_J = 0x40,
880 HDMI_AUD_CONF1_MODE_BURST_1 = 0x60,
881 HDMI_AUD_CONF1_MODE_BURST_2 = 0x80,
882 HDMI_AUD_CONF1_WIDTH_16 = 0x10,
883 HDMI_AUD_CONF1_WIDTH_24 = 0x18,
885 /* AUD_CTS3 field values */
886 HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
887 HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
888 HDMI_AUD_CTS3_N_SHIFT_1 = 0,
889 HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
890 HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
891 HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
892 HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
893 HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
894 /* note that the CTS3 MANUAL bit has been removed
895 from our part. Can't set it, will read as 0. */
896 HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
897 HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
899 /* HDMI_AUD_INPUTCLKFS field values */
900 HDMI_AUD_INPUTCLKFS_128FS = 0,
901 HDMI_AUD_INPUTCLKFS_256FS = 1,
902 HDMI_AUD_INPUTCLKFS_512FS = 2,
903 HDMI_AUD_INPUTCLKFS_64FS = 4,
905 /* AHB_DMA_CONF0 field values */
906 HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7,
907 HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80,
908 HDMI_AHB_DMA_CONF0_HBR = 0x10,
909 HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3,
910 HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08,
911 HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1,
912 HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06,
913 HDMI_AHB_DMA_CONF0_INCR4 = 0x0,
914 HDMI_AHB_DMA_CONF0_INCR8 = 0x2,
915 HDMI_AHB_DMA_CONF0_INCR16 = 0x4,
916 HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1,
918 /* HDMI_AHB_DMA_START field values */
919 HDMI_AHB_DMA_START_START_OFFSET = 0,
920 HDMI_AHB_DMA_START_START_MASK = 0x01,
922 /* HDMI_AHB_DMA_STOP field values */
923 HDMI_AHB_DMA_STOP_STOP_OFFSET = 0,
924 HDMI_AHB_DMA_STOP_STOP_MASK = 0x01,
926 /* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */
927 HDMI_AHB_DMA_DONE = 0x80,
928 HDMI_AHB_DMA_RETRY_SPLIT = 0x40,
929 HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20,
930 HDMI_AHB_DMA_ERROR = 0x10,
931 HDMI_AHB_DMA_FIFO_THREMPTY = 0x04,
932 HDMI_AHB_DMA_FIFO_FULL = 0x02,
933 HDMI_AHB_DMA_FIFO_EMPTY = 0x01,
935 /* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT,AHB_DMA_BUFFMASK,AHB_DMA_BUFFPOL values */
936 HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02,
937 HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01,
939 /* MC_CLKDIS field values */
940 HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
941 HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
942 HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
943 HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
944 HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
945 HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
946 HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
948 /* MC_SWRSTZ field values */
949 HDMI_MC_SWRSTZ_I2SSWRST_REQ = 0x08,
950 HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
952 /* MC_FLOWCTRL field values */
953 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1,
954 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
955 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
957 /* MC_PHYRSTZ field values */
958 HDMI_MC_PHYRSTZ_PHYRSTZ = 0x01,
960 /* MC_HEACPHY_RST field values */
961 HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
962 HDMI_MC_HEACPHY_RST_DEASSERT = 0x0,
964 /* CSC_CFG field values */
965 HDMI_CSC_CFG_INTMODE_MASK = 0x30,
966 HDMI_CSC_CFG_INTMODE_OFFSET = 4,
967 HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
968 HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
969 HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
970 HDMI_CSC_CFG_DECMODE_MASK = 0x3,
971 HDMI_CSC_CFG_DECMODE_OFFSET = 0,
972 HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
973 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
974 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
975 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
977 /* CSC_SCALE field values */
978 HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
979 HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
980 HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
981 HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
982 HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
983 HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
985 /* A_HDCPCFG0 field values */
986 HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80,
987 HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80,
988 HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00,
989 HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40,
990 HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40,
991 HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00,
992 HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20,
993 HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20,
994 HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00,
995 HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10,
996 HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10,
997 HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00,
998 HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8,
999 HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8,
1000 HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0,
1001 HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4,
1002 HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4,
1003 HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0,
1004 HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2,
1005 HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2,
1006 HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0,
1007 HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1,
1008 HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1,
1009 HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0,
1011 /* A_HDCPCFG1 field values */
1012 HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8,
1013 HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8,
1014 HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0,
1015 HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4,
1016 HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4,
1017 HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0,
1018 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2,
1019 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2,
1020 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0,
1021 HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1,
1022 HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0,
1024 /* A_VIDPOLCFG field values */
1025 HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60,
1026 HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5,
1027 HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10,
1028 HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10,
1029 HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0,
1030 HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8,
1031 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8,
1032 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0,
1033 HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2,
1034 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2,
1035 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0,
1037 /* I2CM_OPERATION field values */
1038 HDMI_I2CM_OPERATION_WRITE = 0x10,
1039 HDMI_I2CM_OPERATION_READ_EXT = 0x2,
1040 HDMI_I2CM_OPERATION_READ = 0x1,
1042 /* I2CM_INT field values */
1043 HDMI_I2CM_INT_DONE_POL = 0x8,
1044 HDMI_I2CM_INT_DONE_MASK = 0x4,
1046 /* I2CM_CTLINT field values */
1047 HDMI_I2CM_CTLINT_NAC_POL = 0x80,
1048 HDMI_I2CM_CTLINT_NAC_MASK = 0x40,
1049 HDMI_I2CM_CTLINT_ARB_POL = 0x8,
1050 HDMI_I2CM_CTLINT_ARB_MASK = 0x4,
1054 * HDMI 3D TX PHY registers
1056 #define HDMI_3D_TX_PHY_PWRCTRL 0x00
1057 #define HDMI_3D_TX_PHY_SERDIVCTRL 0x01
1058 #define HDMI_3D_TX_PHY_SERCKCTRL 0x02
1059 #define HDMI_3D_TX_PHY_SERCKKILLCTRL 0x03
1060 #define HDMI_3D_TX_PHY_TXRESCTRL 0x04
1061 #define HDMI_3D_TX_PHY_CKCALCTRL 0x05
1062 #define HDMI_3D_TX_PHY_CPCE_CTRL 0x06
1063 #define HDMI_3D_TX_PHY_TXCLKMEASCTRL 0x07
1064 #define HDMI_3D_TX_PHY_TXMEASCTRL 0x08
1065 #define HDMI_3D_TX_PHY_CKSYMTXCTRL 0x09
1066 #define HDMI_3D_TX_PHY_CMPSEQCTRL 0x0a
1067 #define HDMI_3D_TX_PHY_CMPPWRCTRL 0x0b
1068 #define HDMI_3D_TX_PHY_CMPMODECTRL 0x0c
1069 #define HDMI_3D_TX_PHY_MEASCTRL 0x0d
1070 #define HDMI_3D_TX_PHY_VLEVCTRL 0x0e
1071 #define HDMI_3D_TX_PHY_D2ACTRL 0x0f
1072 #define HDMI_3D_TX_PHY_CURRCTRL 0x10
1073 #define HDMI_3D_TX_PHY_DRVANACTRL 0x11
1074 #define HDMI_3D_TX_PHY_PLLMEASCTRL 0x12
1075 #define HDMI_3D_TX_PHY_PLLPHBYCTRL 0x13
1076 #define HDMI_3D_TX_PHY_GRP_CTRL 0x14
1077 #define HDMI_3D_TX_PHY_GMPCTRL 0x15
1078 #define HDMI_3D_TX_PHY_MPLLMEASCTRL 0x16
1079 #define HDMI_3D_TX_PHY_MSM_CTRL 0x17
1080 #define HDMI_3D_TX_PHY_SCRPB_STATUS 0x18
1081 #define HDMI_3D_TX_PHY_TXTERM 0x19
1082 #define HDMI_3D_TX_PHY_PTRPT_ENBL 0x1a
1083 #define HDMI_3D_TX_PHY_PATTERNGEN 0x1b
1084 #define HDMI_3D_TX_PHY_SDCAP_MODE 0x1c
1085 #define HDMI_3D_TX_PHY_SCOPEMODE 0x1d
1086 #define HDMI_3D_TX_PHY_DIGTXMODE 0x1e
1087 #define HDMI_3D_TX_PHY_STR_STATUS 0x1f
1088 #define HDMI_3D_TX_PHY_SCOPECNT0 0x20
1089 #define HDMI_3D_TX_PHY_SCOPECNT1 0x21
1090 #define HDMI_3D_TX_PHY_SCOPECNT2 0x22
1091 #define HDMI_3D_TX_PHY_SCOPECNTCLK 0x23
1092 #define HDMI_3D_TX_PHY_SCOPESAMPLE 0x24
1093 #define HDMI_3D_TX_PHY_SCOPECNTMSB01 0x25
1094 #define HDMI_3D_TX_PHY_SCOPECNTMSB2CK 0x26
1096 /* HDMI_3D_TX_PHY_CKCALCTRL values */
1097 #define HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE BIT(15)
1099 /* HDMI_3D_TX_PHY_MSM_CTRL values */
1100 #define HDMI_3D_TX_PHY_MSM_CTRL_MPLL_PH_SEL_CK BIT(13)
1101 #define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_CLK_REF_MPLL (0 << 1)
1102 #define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_OFF (1 << 1)
1103 #define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_PCLK (2 << 1)
1104 #define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK (3 << 1)
1105 #define HDMI_3D_TX_PHY_MSM_CTRL_SCOPE_CK_SEL BIT(0)
1107 /* HDMI_3D_TX_PHY_PTRPT_ENBL values */
1108 #define HDMI_3D_TX_PHY_PTRPT_ENBL_OVERRIDE BIT(15)
1109 #define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT2 BIT(8)
1110 #define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT1 BIT(7)
1111 #define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT0 BIT(6)
1112 #define HDMI_3D_TX_PHY_PTRPT_ENBL_CK_REF_ENB BIT(5)
1113 #define HDMI_3D_TX_PHY_PTRPT_ENBL_RCAL_ENB BIT(4)
1114 #define HDMI_3D_TX_PHY_PTRPT_ENBL_TX_CLK_ALIGN_ENB BIT(3)
1115 #define HDMI_3D_TX_PHY_PTRPT_ENBL_TX_READY BIT(2)
1116 #define HDMI_3D_TX_PHY_PTRPT_ENBL_CKO_WORD_ENB BIT(1)
1117 #define HDMI_3D_TX_PHY_PTRPT_ENBL_REFCLK_ENB BIT(0)
1119 #endif /* __DW_HDMI_H__ */
projects / linux-2.6-block.git / blob