1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright(c) 2016, Analogix Semiconductor.
5 * Based on anx7808 driver obtained from chromeos with copyright:
6 * Copyright(c) 2013, Google Inc.
8 #include <linux/delay.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/i2c.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of_irq.h>
16 #include <linux/of_platform.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/types.h>
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_bridge.h>
23 #include <drm/drm_crtc.h>
24 #include <drm/drm_dp_helper.h>
25 #include <drm/drm_edid.h>
26 #include <drm/drm_print.h>
27 #include <drm/drm_probe_helper.h>
29 #include "analogix-anx78xx.h"
31 #define I2C_NUM_ADDRESSES 5
32 #define I2C_IDX_TX_P0 0
33 #define I2C_IDX_TX_P1 1
34 #define I2C_IDX_TX_P2 2
35 #define I2C_IDX_RX_P0 3
36 #define I2C_IDX_RX_P1 4
38 #define XTAL_CLK 270 /* 27M */
39 #define AUX_CH_BUFFER_SIZE 16
40 #define AUX_WAIT_TIMEOUT_MS 15
42 static const u8 anx78xx_i2c_addresses[] = {
43 [I2C_IDX_TX_P0] = TX_P0,
44 [I2C_IDX_TX_P1] = TX_P1,
45 [I2C_IDX_TX_P2] = TX_P2,
46 [I2C_IDX_RX_P0] = RX_P0,
47 [I2C_IDX_RX_P1] = RX_P1,
50 struct anx78xx_platform_data {
51 struct regulator *dvdd10;
52 struct gpio_desc *gpiod_hpd;
53 struct gpio_desc *gpiod_pd;
54 struct gpio_desc *gpiod_reset;
61 struct drm_dp_aux aux;
62 struct drm_bridge bridge;
63 struct i2c_client *client;
65 struct drm_connector connector;
66 struct drm_dp_link link;
67 struct anx78xx_platform_data pdata;
71 * I2C Slave addresses of ANX7814 are mapped as TX_P0, TX_P1, TX_P2,
74 struct i2c_client *i2c_dummy[I2C_NUM_ADDRESSES];
75 struct regmap *map[I2C_NUM_ADDRESSES];
78 u8 dpcd[DP_RECEIVER_CAP_SIZE];
83 static inline struct anx78xx *connector_to_anx78xx(struct drm_connector *c)
85 return container_of(c, struct anx78xx, connector);
88 static inline struct anx78xx *bridge_to_anx78xx(struct drm_bridge *bridge)
90 return container_of(bridge, struct anx78xx, bridge);
93 static int anx78xx_set_bits(struct regmap *map, u8 reg, u8 mask)
95 return regmap_update_bits(map, reg, mask, mask);
98 static int anx78xx_clear_bits(struct regmap *map, u8 reg, u8 mask)
100 return regmap_update_bits(map, reg, mask, 0);
103 static bool anx78xx_aux_op_finished(struct anx78xx *anx78xx)
108 err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,
113 return (value & SP_AUX_EN) == 0;
116 static int anx78xx_aux_wait(struct anx78xx *anx78xx)
118 unsigned long timeout;
122 timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
124 while (!anx78xx_aux_op_finished(anx78xx)) {
125 if (time_after(jiffies, timeout)) {
126 if (!anx78xx_aux_op_finished(anx78xx)) {
127 DRM_ERROR("Timed out waiting AUX to finish\n");
134 usleep_range(1000, 2000);
137 /* Read the AUX channel access status */
138 err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_CH_STATUS_REG,
141 DRM_ERROR("Failed to read from AUX channel: %d\n", err);
145 if (status & SP_AUX_STATUS) {
146 DRM_ERROR("Failed to wait for AUX channel (status: %02x)\n",
154 static int anx78xx_aux_address(struct anx78xx *anx78xx, unsigned int addr)
158 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_7_0_REG,
163 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_15_8_REG,
164 (addr & 0xff00) >> 8);
169 * DP AUX CH Address Register #2, only update bits[3:0]
171 * [3:0] AUX_ADDR[19:16], Register control AUX CH address.
173 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0],
174 SP_AUX_ADDR_19_16_REG,
175 SP_AUX_ADDR_19_16_MASK,
176 (addr & 0xf0000) >> 16);
184 static ssize_t anx78xx_aux_transfer(struct drm_dp_aux *aux,
185 struct drm_dp_aux_msg *msg)
187 struct anx78xx *anx78xx = container_of(aux, struct anx78xx, aux);
188 u8 ctrl1 = msg->request;
189 u8 ctrl2 = SP_AUX_EN;
190 u8 *buffer = msg->buffer;
193 /* The DP AUX transmit and receive buffer has 16 bytes. */
194 if (WARN_ON(msg->size > AUX_CH_BUFFER_SIZE))
197 /* Zero-sized messages specify address-only transactions. */
199 ctrl2 |= SP_ADDR_ONLY;
200 else /* For non-zero-sized set the length field. */
201 ctrl1 |= (msg->size - 1) << SP_AUX_LENGTH_SHIFT;
203 if ((msg->request & DP_AUX_I2C_READ) == 0) {
204 /* When WRITE | MOT write values to data buffer */
205 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P0],
206 SP_DP_BUF_DATA0_REG, buffer,
212 /* Write address and request */
213 err = anx78xx_aux_address(anx78xx, msg->address);
217 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL1_REG,
222 /* Start transaction */
223 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0],
224 SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY |
229 err = anx78xx_aux_wait(anx78xx);
233 msg->reply = DP_AUX_I2C_REPLY_ACK;
235 if ((msg->size > 0) && (msg->request & DP_AUX_I2C_READ)) {
236 /* Read values from data buffer */
237 err = regmap_bulk_read(anx78xx->map[I2C_IDX_TX_P0],
238 SP_DP_BUF_DATA0_REG, buffer,
244 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
245 SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY);
252 static int anx78xx_set_hpd(struct anx78xx *anx78xx)
256 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
257 SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
261 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
269 static int anx78xx_clear_hpd(struct anx78xx *anx78xx)
273 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
278 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
279 SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
286 static const struct reg_sequence tmds_phy_initialization[] = {
287 { SP_TMDS_CTRL_BASE + 1, 0x90 },
288 { SP_TMDS_CTRL_BASE + 2, 0xa9 },
289 { SP_TMDS_CTRL_BASE + 6, 0x92 },
290 { SP_TMDS_CTRL_BASE + 7, 0x80 },
291 { SP_TMDS_CTRL_BASE + 20, 0xf2 },
292 { SP_TMDS_CTRL_BASE + 22, 0xc4 },
293 { SP_TMDS_CTRL_BASE + 23, 0x18 },
296 static int anx78xx_rx_initialization(struct anx78xx *anx78xx)
300 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
301 SP_AUD_MUTE | SP_VID_MUTE);
305 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_CHIP_CTRL_REG,
306 SP_MAN_HDMI5V_DET | SP_PLLLOCK_CKDT_EN |
311 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
312 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
313 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
317 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
318 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
319 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
323 /* Sync detect change, GP set mute */
324 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
325 SP_AUD_EXCEPTION_ENABLE_BASE + 1, BIT(5) |
330 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
331 SP_AUD_EXCEPTION_ENABLE_BASE + 3,
336 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_AUDVID_CTRL_REG,
337 SP_AVC_EN | SP_AAC_OE | SP_AAC_EN);
341 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
342 SP_SYSTEM_POWER_DOWN1_REG, SP_PWDN_CTRL);
346 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
347 SP_VID_DATA_RANGE_CTRL_REG, SP_R2Y_INPUT_LIMIT);
351 /* Enable DDC stretch */
352 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
353 SP_DP_EXTRA_I2C_DEV_ADDR_REG, SP_I2C_EXTRA_ADDR);
357 /* TMDS phy initialization */
358 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_RX_P0],
359 tmds_phy_initialization,
360 ARRAY_SIZE(tmds_phy_initialization));
364 err = anx78xx_clear_hpd(anx78xx);
371 static const u8 dp_tx_output_precise_tune_bits[20] = {
372 0x01, 0x03, 0x07, 0x7f, 0x71, 0x6b, 0x7f,
373 0x73, 0x7f, 0x7f, 0x00, 0x00, 0x00, 0x00,
374 0x0c, 0x42, 0x1e, 0x3e, 0x72, 0x7e,
377 static int anx78xx_link_phy_initialization(struct anx78xx *anx78xx)
382 * REVISIT : It is writing to a RESERVED bits in Analog Control 0
385 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_ANALOG_CTRL0_REG,
391 * Write DP TX output emphasis precise tune bits.
393 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P1],
394 SP_DP_TX_LT_CTRL0_REG,
395 dp_tx_output_precise_tune_bits,
396 ARRAY_SIZE(dp_tx_output_precise_tune_bits));
404 static int anx78xx_xtal_clk_sel(struct anx78xx *anx78xx)
409 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P2],
410 SP_ANALOG_DEBUG2_REG,
411 SP_XTAL_FRQ | SP_FORCE_SW_OFF_BYPASS,
416 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL3_REG,
417 XTAL_CLK & SP_WAIT_COUNTER_7_0_MASK);
421 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL4_REG,
422 ((XTAL_CLK & 0xff00) >> 2) | (XTAL_CLK / 10));
426 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
427 SP_I2C_GEN_10US_TIMER0_REG, XTAL_CLK & 0xff);
431 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
432 SP_I2C_GEN_10US_TIMER1_REG,
433 (XTAL_CLK & 0xff00) >> 8);
437 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_MISC_CTRL_REG,
442 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
443 SP_HDMI_US_TIMER_CTRL_REG,
448 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0],
449 SP_HDMI_US_TIMER_CTRL_REG,
450 (value & SP_MS_TIMER_MARGIN_10_8_MASK) |
451 ((((XTAL_CLK / 10) >> 1) - 2) << 3));
458 static const struct reg_sequence otp_key_protect[] = {
459 { SP_OTP_KEY_PROTECT1_REG, SP_OTP_PSW1 },
460 { SP_OTP_KEY_PROTECT2_REG, SP_OTP_PSW2 },
461 { SP_OTP_KEY_PROTECT3_REG, SP_OTP_PSW3 },
464 static int anx78xx_tx_initialization(struct anx78xx *anx78xx)
468 /* Set terminal resistor to 50 ohm */
469 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,
474 /* Enable aux double diff output */
475 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
476 SP_DP_AUX_CH_CTRL2_REG, 0x08);
480 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
481 SP_DP_HDCP_CTRL_REG, SP_AUTO_EN |
486 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_TX_P0],
488 ARRAY_SIZE(otp_key_protect));
492 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
493 SP_HDCP_KEY_COMMAND_REG, SP_DISABLE_SYNC_HDCP);
497 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL8_REG,
503 * DP HDCP auto authentication wait timer (when downstream starts to
504 * auth, DP side will wait for this period then do auth automatically)
506 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_HDCP_AUTO_TIMER_REG,
511 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
512 SP_DP_HDCP_CTRL_REG, SP_LINK_POLLING);
516 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
517 SP_DP_LINK_DEBUG_CTRL_REG, SP_M_VID_DEBUG);
521 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2],
522 SP_ANALOG_DEBUG2_REG, SP_POWERON_TIME_1P5MS);
526 err = anx78xx_xtal_clk_sel(anx78xx);
530 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_DEFER_CTRL_REG,
531 SP_DEFER_CTRL_EN | 0x0c);
535 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
536 SP_DP_POLLING_CTRL_REG,
537 SP_AUTO_POLLING_DISABLE);
542 * Short the link integrity check timer to speed up bstatus
543 * polling for HDCP CTS item 1A-07
545 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
546 SP_HDCP_LINK_CHECK_TIMER_REG, 0x1d);
550 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
551 SP_DP_MISC_CTRL_REG, SP_EQ_TRAINING_LOOP);
555 /* Power down the main link by default */
556 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
557 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
561 err = anx78xx_link_phy_initialization(anx78xx);
565 /* Gen m_clk with downspreading */
566 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
567 SP_DP_M_CALCULATION_CTRL_REG, SP_M_GEN_CLK_SEL);
574 static int anx78xx_enable_interrupts(struct anx78xx *anx78xx)
579 * BIT0: INT pin assertion polarity: 1 = assert high
580 * BIT1: INT pin output type: 0 = push/pull
582 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_INT_CTRL_REG, 0x01);
586 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
587 SP_COMMON_INT_MASK4_REG, SP_HPD_LOST | SP_HPD_PLUG);
591 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_MASK1_REG,
596 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_MASK1_REG,
597 SP_CKDT_CHG | SP_SCDT_CHG);
604 static void anx78xx_poweron(struct anx78xx *anx78xx)
606 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
609 if (WARN_ON(anx78xx->powered))
613 err = regulator_enable(pdata->dvdd10);
615 DRM_ERROR("Failed to enable DVDD10 regulator: %d\n",
620 usleep_range(1000, 2000);
623 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
624 usleep_range(1000, 2000);
626 gpiod_set_value_cansleep(pdata->gpiod_pd, 0);
627 usleep_range(1000, 2000);
629 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
631 /* Power on registers module */
632 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
633 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
634 anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
635 SP_REGISTER_PD | SP_TOTAL_PD);
637 anx78xx->powered = true;
640 static void anx78xx_poweroff(struct anx78xx *anx78xx)
642 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
645 if (WARN_ON(!anx78xx->powered))
648 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
649 usleep_range(1000, 2000);
651 gpiod_set_value_cansleep(pdata->gpiod_pd, 1);
652 usleep_range(1000, 2000);
655 err = regulator_disable(pdata->dvdd10);
657 DRM_ERROR("Failed to disable DVDD10 regulator: %d\n",
662 usleep_range(1000, 2000);
665 anx78xx->powered = false;
668 static int anx78xx_start(struct anx78xx *anx78xx)
672 /* Power on all modules */
673 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
674 SP_POWERDOWN_CTRL_REG,
675 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD |
678 err = anx78xx_enable_interrupts(anx78xx);
680 DRM_ERROR("Failed to enable interrupts: %d\n", err);
684 err = anx78xx_rx_initialization(anx78xx);
686 DRM_ERROR("Failed receiver initialization: %d\n", err);
690 err = anx78xx_tx_initialization(anx78xx);
692 DRM_ERROR("Failed transmitter initialization: %d\n", err);
697 * This delay seems to help keep the hardware in a good state. Without
698 * it, there are times where it fails silently.
700 usleep_range(10000, 15000);
705 DRM_ERROR("Failed SlimPort transmitter initialization: %d\n", err);
706 anx78xx_poweroff(anx78xx);
711 static int anx78xx_init_pdata(struct anx78xx *anx78xx)
713 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
714 struct device *dev = &anx78xx->client->dev;
716 /* 1.0V digital core power regulator */
717 pdata->dvdd10 = devm_regulator_get(dev, "dvdd10");
718 if (IS_ERR(pdata->dvdd10)) {
719 DRM_ERROR("DVDD10 regulator not found\n");
720 return PTR_ERR(pdata->dvdd10);
724 pdata->gpiod_hpd = devm_gpiod_get(dev, "hpd", GPIOD_IN);
725 if (IS_ERR(pdata->gpiod_hpd))
726 return PTR_ERR(pdata->gpiod_hpd);
728 /* GPIO for chip power down */
729 pdata->gpiod_pd = devm_gpiod_get(dev, "pd", GPIOD_OUT_HIGH);
730 if (IS_ERR(pdata->gpiod_pd))
731 return PTR_ERR(pdata->gpiod_pd);
733 /* GPIO for chip reset */
734 pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
736 return PTR_ERR_OR_ZERO(pdata->gpiod_reset);
739 static int anx78xx_dp_link_training(struct anx78xx *anx78xx)
744 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
749 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
750 SP_POWERDOWN_CTRL_REG,
755 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_MAX_LINK_RATE, &dp_bw);
760 case DP_LINK_BW_1_62:
766 DRM_DEBUG_KMS("DP bandwidth (%#02x) not supported\n", dp_bw);
770 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
775 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
776 SP_VID_CTRL1_REG, SP_VIDEO_EN);
781 err = drm_dp_dpcd_read(&anx78xx->aux, DP_DPCD_REV,
782 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE);
784 DRM_ERROR("Failed to read DPCD: %d\n", err);
788 /* Clear channel x SERDES power down */
789 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
790 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
794 /* Check link capabilities */
795 err = drm_dp_link_probe(&anx78xx->aux, &anx78xx->link);
797 DRM_ERROR("Failed to probe link capabilities: %d\n", err);
801 /* Power up the sink */
802 err = drm_dp_link_power_up(&anx78xx->aux, &anx78xx->link);
804 DRM_ERROR("Failed to power up DisplayPort link: %d\n", err);
808 /* Possibly enable downspread on the sink */
809 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
810 SP_DP_DOWNSPREAD_CTRL1_REG, 0);
814 if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {
815 DRM_DEBUG("Enable downspread on the sink\n");
817 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
818 SP_DP_DOWNSPREAD_CTRL1_REG, 8);
822 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL,
827 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL, 0);
832 /* Set the lane count and the link rate on the sink */
833 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd))
834 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
835 SP_DP_SYSTEM_CTRL_BASE + 4,
838 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
839 SP_DP_SYSTEM_CTRL_BASE + 4,
844 value = drm_dp_link_rate_to_bw_code(anx78xx->link.rate);
845 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
846 SP_DP_MAIN_LINK_BW_SET_REG, value);
850 err = drm_dp_link_configure(&anx78xx->aux, &anx78xx->link);
852 DRM_ERROR("Failed to configure DisplayPort link: %d\n", err);
856 /* Start training on the source */
857 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_LT_CTRL_REG,
865 static int anx78xx_config_dp_output(struct anx78xx *anx78xx)
869 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
874 /* Enable DP output */
875 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
883 static int anx78xx_send_video_infoframe(struct anx78xx *anx78xx,
884 struct hdmi_avi_infoframe *frame)
886 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
889 err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));
891 DRM_ERROR("Failed to pack AVI infoframe: %d\n", err);
895 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
896 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
900 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P2],
901 SP_INFOFRAME_AVI_DB1_REG, buffer,
906 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
907 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_UD);
911 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
912 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
919 static int anx78xx_get_downstream_info(struct anx78xx *anx78xx)
924 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SINK_COUNT, &value);
926 DRM_ERROR("Get sink count failed %d\n", err);
930 if (!DP_GET_SINK_COUNT(value)) {
931 DRM_ERROR("Downstream disconnected\n");
938 static int anx78xx_get_modes(struct drm_connector *connector)
940 struct anx78xx *anx78xx = connector_to_anx78xx(connector);
941 int err, num_modes = 0;
943 if (WARN_ON(!anx78xx->powered))
947 return drm_add_edid_modes(connector, anx78xx->edid);
949 mutex_lock(&anx78xx->lock);
951 err = anx78xx_get_downstream_info(anx78xx);
953 DRM_ERROR("Failed to get downstream info: %d\n", err);
957 anx78xx->edid = drm_get_edid(connector, &anx78xx->aux.ddc);
958 if (!anx78xx->edid) {
959 DRM_ERROR("Failed to read EDID\n");
963 err = drm_connector_update_edid_property(connector,
966 DRM_ERROR("Failed to update EDID property: %d\n", err);
970 num_modes = drm_add_edid_modes(connector, anx78xx->edid);
973 mutex_unlock(&anx78xx->lock);
978 static const struct drm_connector_helper_funcs anx78xx_connector_helper_funcs = {
979 .get_modes = anx78xx_get_modes,
982 static enum drm_connector_status anx78xx_detect(struct drm_connector *connector,
985 struct anx78xx *anx78xx = connector_to_anx78xx(connector);
987 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
988 return connector_status_disconnected;
990 return connector_status_connected;
993 static const struct drm_connector_funcs anx78xx_connector_funcs = {
994 .fill_modes = drm_helper_probe_single_connector_modes,
995 .detect = anx78xx_detect,
996 .destroy = drm_connector_cleanup,
997 .reset = drm_atomic_helper_connector_reset,
998 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
999 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1002 static int anx78xx_bridge_attach(struct drm_bridge *bridge)
1004 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1007 if (!bridge->encoder) {
1008 DRM_ERROR("Parent encoder object not found");
1012 /* Register aux channel */
1013 anx78xx->aux.name = "DP-AUX";
1014 anx78xx->aux.dev = &anx78xx->client->dev;
1015 anx78xx->aux.transfer = anx78xx_aux_transfer;
1017 err = drm_dp_aux_register(&anx78xx->aux);
1019 DRM_ERROR("Failed to register aux channel: %d\n", err);
1023 err = drm_connector_init(bridge->dev, &anx78xx->connector,
1024 &anx78xx_connector_funcs,
1025 DRM_MODE_CONNECTOR_DisplayPort);
1027 DRM_ERROR("Failed to initialize connector: %d\n", err);
1031 drm_connector_helper_add(&anx78xx->connector,
1032 &anx78xx_connector_helper_funcs);
1034 err = drm_connector_register(&anx78xx->connector);
1036 DRM_ERROR("Failed to register connector: %d\n", err);
1040 anx78xx->connector.polled = DRM_CONNECTOR_POLL_HPD;
1042 err = drm_connector_attach_encoder(&anx78xx->connector,
1045 DRM_ERROR("Failed to link up connector to encoder: %d\n", err);
1052 static enum drm_mode_status
1053 anx78xx_bridge_mode_valid(struct drm_bridge *bridge,
1054 const struct drm_display_mode *mode)
1056 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1057 return MODE_NO_INTERLACE;
1059 /* Max 1200p at 5.4 Ghz, one lane */
1060 if (mode->clock > 154000)
1061 return MODE_CLOCK_HIGH;
1066 static void anx78xx_bridge_disable(struct drm_bridge *bridge)
1068 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1070 /* Power off all modules except configuration registers access */
1071 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
1072 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
1075 static void anx78xx_bridge_mode_set(struct drm_bridge *bridge,
1076 const struct drm_display_mode *mode,
1077 const struct drm_display_mode *adjusted_mode)
1079 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1080 struct hdmi_avi_infoframe frame;
1083 if (WARN_ON(!anx78xx->powered))
1086 mutex_lock(&anx78xx->lock);
1088 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
1089 &anx78xx->connector,
1092 DRM_ERROR("Failed to setup AVI infoframe: %d\n", err);
1096 err = anx78xx_send_video_infoframe(anx78xx, &frame);
1098 DRM_ERROR("Failed to send AVI infoframe: %d\n", err);
1101 mutex_unlock(&anx78xx->lock);
1104 static void anx78xx_bridge_enable(struct drm_bridge *bridge)
1106 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1109 err = anx78xx_start(anx78xx);
1111 DRM_ERROR("Failed to initialize: %d\n", err);
1115 err = anx78xx_set_hpd(anx78xx);
1117 DRM_ERROR("Failed to set HPD: %d\n", err);
1120 static const struct drm_bridge_funcs anx78xx_bridge_funcs = {
1121 .attach = anx78xx_bridge_attach,
1122 .mode_valid = anx78xx_bridge_mode_valid,
1123 .disable = anx78xx_bridge_disable,
1124 .mode_set = anx78xx_bridge_mode_set,
1125 .enable = anx78xx_bridge_enable,
1128 static irqreturn_t anx78xx_hpd_threaded_handler(int irq, void *data)
1130 struct anx78xx *anx78xx = data;
1133 if (anx78xx->powered)
1136 mutex_lock(&anx78xx->lock);
1138 /* Cable is pulled, power on the chip */
1139 anx78xx_poweron(anx78xx);
1141 err = anx78xx_enable_interrupts(anx78xx);
1143 DRM_ERROR("Failed to enable interrupts: %d\n", err);
1145 mutex_unlock(&anx78xx->lock);
1150 static int anx78xx_handle_dp_int_1(struct anx78xx *anx78xx, u8 irq)
1154 DRM_DEBUG_KMS("Handle DP interrupt 1: %02x\n", irq);
1156 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1161 if (irq & SP_TRAINING_FINISH) {
1162 DRM_DEBUG_KMS("IRQ: hardware link training finished\n");
1163 err = anx78xx_config_dp_output(anx78xx);
1169 static bool anx78xx_handle_common_int_4(struct anx78xx *anx78xx, u8 irq)
1174 DRM_DEBUG_KMS("Handle common interrupt 4: %02x\n", irq);
1176 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
1177 SP_COMMON_INT_STATUS4_REG, irq);
1179 DRM_ERROR("Failed to write SP_COMMON_INT_STATUS4 %d\n", err);
1183 if (irq & SP_HPD_LOST) {
1184 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable is pulled out\n");
1186 anx78xx_poweroff(anx78xx);
1187 /* Free cached EDID */
1188 kfree(anx78xx->edid);
1189 anx78xx->edid = NULL;
1190 } else if (irq & SP_HPD_PLUG) {
1191 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable plug\n");
1198 static void anx78xx_handle_hdmi_int_1(struct anx78xx *anx78xx, u8 irq)
1203 DRM_DEBUG_KMS("Handle HDMI interrupt 1: %02x\n", irq);
1205 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1208 DRM_ERROR("Write HDMI int 1 failed: %d\n", err);
1212 if ((irq & SP_CKDT_CHG) || (irq & SP_SCDT_CHG)) {
1213 DRM_DEBUG_KMS("IRQ: HDMI input detected\n");
1215 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
1216 SP_SYSTEM_STATUS_REG, &value);
1218 DRM_ERROR("Read system status reg failed: %d\n", err);
1222 if (!(value & SP_TMDS_CLOCK_DET)) {
1223 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI clock ***\n");
1227 if (!(value & SP_TMDS_DE_DET)) {
1228 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI signal ***\n");
1232 err = anx78xx_dp_link_training(anx78xx);
1234 DRM_ERROR("Failed to start link training: %d\n", err);
1238 static irqreturn_t anx78xx_intp_threaded_handler(int unused, void *data)
1240 struct anx78xx *anx78xx = data;
1245 mutex_lock(&anx78xx->lock);
1247 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1250 DRM_ERROR("Failed to read DP interrupt 1 status: %d\n", err);
1255 anx78xx_handle_dp_int_1(anx78xx, irq);
1257 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2],
1258 SP_COMMON_INT_STATUS4_REG, &irq);
1260 DRM_ERROR("Failed to read common interrupt 4 status: %d\n",
1266 event = anx78xx_handle_common_int_4(anx78xx, irq);
1268 /* Make sure we are still powered after handle HPD events */
1269 if (!anx78xx->powered)
1272 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1275 DRM_ERROR("Failed to read HDMI int 1 status: %d\n", err);
1280 anx78xx_handle_hdmi_int_1(anx78xx, irq);
1283 mutex_unlock(&anx78xx->lock);
1286 drm_helper_hpd_irq_event(anx78xx->connector.dev);
1291 static void unregister_i2c_dummy_clients(struct anx78xx *anx78xx)
1295 for (i = 0; i < ARRAY_SIZE(anx78xx->i2c_dummy); i++)
1296 i2c_unregister_device(anx78xx->i2c_dummy[i]);
1299 static const struct regmap_config anx78xx_regmap_config = {
1304 static const u16 anx78xx_chipid_list[] = {
1310 static int anx78xx_i2c_probe(struct i2c_client *client,
1311 const struct i2c_device_id *id)
1313 struct anx78xx *anx78xx;
1314 struct anx78xx_platform_data *pdata;
1315 unsigned int i, idl, idh, version;
1319 anx78xx = devm_kzalloc(&client->dev, sizeof(*anx78xx), GFP_KERNEL);
1323 pdata = &anx78xx->pdata;
1325 mutex_init(&anx78xx->lock);
1327 #if IS_ENABLED(CONFIG_OF)
1328 anx78xx->bridge.of_node = client->dev.of_node;
1331 anx78xx->client = client;
1332 i2c_set_clientdata(client, anx78xx);
1334 err = anx78xx_init_pdata(anx78xx);
1336 DRM_ERROR("Failed to initialize pdata: %d\n", err);
1340 pdata->hpd_irq = gpiod_to_irq(pdata->gpiod_hpd);
1341 if (pdata->hpd_irq < 0) {
1342 DRM_ERROR("Failed to get HPD IRQ: %d\n", pdata->hpd_irq);
1346 pdata->intp_irq = client->irq;
1347 if (!pdata->intp_irq) {
1348 DRM_ERROR("Failed to get CABLE_DET and INTP IRQ\n");
1352 /* Map slave addresses of ANX7814 */
1353 for (i = 0; i < I2C_NUM_ADDRESSES; i++) {
1354 anx78xx->i2c_dummy[i] = i2c_new_dummy(client->adapter,
1355 anx78xx_i2c_addresses[i] >> 1);
1356 if (!anx78xx->i2c_dummy[i]) {
1358 DRM_ERROR("Failed to reserve I2C bus %02x\n",
1359 anx78xx_i2c_addresses[i]);
1360 goto err_unregister_i2c;
1363 anx78xx->map[i] = devm_regmap_init_i2c(anx78xx->i2c_dummy[i],
1364 &anx78xx_regmap_config);
1365 if (IS_ERR(anx78xx->map[i])) {
1366 err = PTR_ERR(anx78xx->map[i]);
1367 DRM_ERROR("Failed regmap initialization %02x\n",
1368 anx78xx_i2c_addresses[i]);
1369 goto err_unregister_i2c;
1373 /* Look for supported chip ID */
1374 anx78xx_poweron(anx78xx);
1376 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDL_REG,
1381 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDH_REG,
1386 anx78xx->chipid = (u8)idl | ((u8)idh << 8);
1388 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_VERSION_REG,
1393 for (i = 0; i < ARRAY_SIZE(anx78xx_chipid_list); i++) {
1394 if (anx78xx->chipid == anx78xx_chipid_list[i]) {
1395 DRM_INFO("Found ANX%x (ver. %d) SlimPort Transmitter\n",
1396 anx78xx->chipid, version);
1403 DRM_ERROR("ANX%x (ver. %d) not supported by this driver\n",
1404 anx78xx->chipid, version);
1409 err = devm_request_threaded_irq(&client->dev, pdata->hpd_irq, NULL,
1410 anx78xx_hpd_threaded_handler,
1411 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1412 "anx78xx-hpd", anx78xx);
1414 DRM_ERROR("Failed to request CABLE_DET threaded IRQ: %d\n",
1419 err = devm_request_threaded_irq(&client->dev, pdata->intp_irq, NULL,
1420 anx78xx_intp_threaded_handler,
1421 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1422 "anx78xx-intp", anx78xx);
1424 DRM_ERROR("Failed to request INTP threaded IRQ: %d\n", err);
1428 anx78xx->bridge.funcs = &anx78xx_bridge_funcs;
1430 drm_bridge_add(&anx78xx->bridge);
1432 /* If cable is pulled out, just poweroff and wait for HPD event */
1433 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
1434 anx78xx_poweroff(anx78xx);
1439 anx78xx_poweroff(anx78xx);
1442 unregister_i2c_dummy_clients(anx78xx);
1446 static int anx78xx_i2c_remove(struct i2c_client *client)
1448 struct anx78xx *anx78xx = i2c_get_clientdata(client);
1450 drm_bridge_remove(&anx78xx->bridge);
1452 unregister_i2c_dummy_clients(anx78xx);
1454 kfree(anx78xx->edid);
1459 static const struct i2c_device_id anx78xx_id[] = {
1463 MODULE_DEVICE_TABLE(i2c, anx78xx_id);
1465 #if IS_ENABLED(CONFIG_OF)
1466 static const struct of_device_id anx78xx_match_table[] = {
1467 { .compatible = "analogix,anx7814", },
1470 MODULE_DEVICE_TABLE(of, anx78xx_match_table);
1473 static struct i2c_driver anx78xx_driver = {
1476 .of_match_table = of_match_ptr(anx78xx_match_table),
1478 .probe = anx78xx_i2c_probe,
1479 .remove = anx78xx_i2c_remove,
1480 .id_table = anx78xx_id,
1482 module_i2c_driver(anx78xx_driver);
1484 MODULE_DESCRIPTION("ANX78xx SlimPort Transmitter driver");
1485 MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
1486 MODULE_LICENSE("GPL v2");