2 * Copyright (C) 2012 Russell King
3 * Rewritten from the dovefb driver, and Armada510 manuals.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <drm/drm_plane_helper.h>
11 #include "armada_crtc.h"
12 #include "armada_drm.h"
13 #include "armada_fb.h"
14 #include "armada_gem.h"
15 #include "armada_hw.h"
16 #include <drm/armada_drm.h>
17 #include "armada_ioctlP.h"
19 struct armada_plane_properties {
23 #define K2R(val) (((val) >> 0) & 0xff)
24 #define K2G(val) (((val) >> 8) & 0xff)
25 #define K2B(val) (((val) >> 16) & 0xff)
29 uint32_t colorkey_mode;
33 struct drm_plane base;
35 struct drm_framebuffer *old_fb;
41 struct armada_vbl_event update;
42 struct armada_regs regs[13];
43 wait_queue_head_t wait;
45 struct armada_plane_properties prop;
47 #define drm_to_armada_plane(p) container_of(p, struct armada_plane, base)
51 armada_ovl_update_attr(struct armada_plane_properties *prop,
52 struct armada_crtc *dcrtc)
54 writel_relaxed(prop->colorkey_yr, dcrtc->base + LCD_SPU_COLORKEY_Y);
55 writel_relaxed(prop->colorkey_ug, dcrtc->base + LCD_SPU_COLORKEY_U);
56 writel_relaxed(prop->colorkey_vb, dcrtc->base + LCD_SPU_COLORKEY_V);
58 writel_relaxed(prop->brightness << 16 | prop->contrast,
59 dcrtc->base + LCD_SPU_CONTRAST);
60 /* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */
61 writel_relaxed(prop->saturation << 16,
62 dcrtc->base + LCD_SPU_SATURATION);
63 writel_relaxed(0x00002000, dcrtc->base + LCD_SPU_CBSH_HUE);
65 spin_lock_irq(&dcrtc->irq_lock);
66 armada_updatel(prop->colorkey_mode | CFG_ALPHAM_GRA,
67 CFG_CKMODE_MASK | CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
68 dcrtc->base + LCD_SPU_DMA_CTRL1);
70 armada_updatel(ADV_GRACOLORKEY, 0, dcrtc->base + LCD_SPU_ADV_REG);
71 spin_unlock_irq(&dcrtc->irq_lock);
74 /* === Plane support === */
75 static void armada_plane_vbl(struct armada_crtc *dcrtc, void *data)
77 struct armada_plane *dplane = data;
78 struct drm_framebuffer *fb;
80 armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs);
82 spin_lock(&dplane->lock);
84 dplane->old_fb = NULL;
85 spin_unlock(&dplane->lock);
88 armada_drm_queue_unref_work(dcrtc->crtc.dev, fb);
90 wake_up(&dplane->vbl.wait);
94 armada_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
95 struct drm_framebuffer *fb,
96 int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
97 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h)
99 struct armada_plane *dplane = drm_to_armada_plane(plane);
100 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
101 struct drm_rect src = {
107 struct drm_rect dest = {
110 .x2 = crtc_x + crtc_w,
111 .y2 = crtc_y + crtc_h,
113 const struct drm_rect clip = {
114 .x2 = crtc->mode.hdisplay,
115 .y2 = crtc->mode.vdisplay,
122 ret = drm_plane_helper_check_update(plane, crtc, fb, &src, &dest, &clip,
123 0, INT_MAX, true, false, &visible);
127 ctrl0 = CFG_DMA_FMT(drm_fb_to_armada_fb(fb)->fmt) |
128 CFG_DMA_MOD(drm_fb_to_armada_fb(fb)->mod) |
129 CFG_CBSH_ENA | CFG_DMA_HSMOOTH | CFG_DMA_ENA;
131 /* Does the position/size result in nothing to display? */
133 ctrl0 &= ~CFG_DMA_ENA;
136 dcrtc->plane = plane;
137 armada_ovl_update_attr(&dplane->prop, dcrtc);
140 /* FIXME: overlay on an interlaced display */
141 /* Just updating the position/size? */
142 if (plane->fb == fb && dplane->ctrl0 == ctrl0) {
143 val = (drm_rect_height(&src) & 0xffff0000) |
144 drm_rect_width(&src) >> 16;
145 dplane->src_hw = val;
146 writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_HPXL_VLN);
148 val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest);
149 dplane->dst_hw = val;
150 writel_relaxed(val, dcrtc->base + LCD_SPU_DZM_HPXL_VLN);
152 val = dest.y1 << 16 | dest.x1;
153 dplane->dst_yx = val;
154 writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_OVSA_HPXL_VLN);
157 } else if (~dplane->ctrl0 & ctrl0 & CFG_DMA_ENA) {
158 /* Power up the Y/U/V FIFOs on ENA 0->1 transitions */
159 armada_updatel(0, CFG_PDWN16x66 | CFG_PDWN32x66,
160 dcrtc->base + LCD_SPU_SRAM_PARA1);
163 wait_event_timeout(dplane->vbl.wait,
164 list_empty(&dplane->vbl.update.node),
167 if (plane->fb != fb) {
168 struct armada_gem_object *obj = drm_fb_obj(fb);
169 uint32_t addr[3], pixel_format;
170 int i, num_planes, hsub;
173 * Take a reference on the new framebuffer - we want to
174 * hold on to it while the hardware is displaying it.
176 drm_framebuffer_reference(fb);
179 struct drm_framebuffer *older_fb;
181 spin_lock_irq(&dplane->lock);
182 older_fb = dplane->old_fb;
183 dplane->old_fb = plane->fb;
184 spin_unlock_irq(&dplane->lock);
186 armada_drm_queue_unref_work(dcrtc->crtc.dev,
190 src_y = src.y1 >> 16;
191 src_x = src.x1 >> 16;
193 pixel_format = fb->pixel_format;
194 hsub = drm_format_horz_chroma_subsampling(pixel_format);
195 num_planes = drm_format_num_planes(pixel_format);
198 * Annoyingly, shifting a YUYV-format image by one pixel
199 * causes the U/V planes to toggle. Toggle the UV swap.
200 * (Unfortunately, this causes momentary colour flickering.)
202 if (src_x & (hsub - 1) && num_planes == 1)
203 ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV);
205 for (i = 0; i < num_planes; i++)
206 addr[i] = obj->dev_addr + fb->offsets[i] +
207 src_y * fb->pitches[i] +
208 src_x * drm_format_plane_cpp(pixel_format, i);
209 for (; i < ARRAY_SIZE(addr); i++)
212 armada_reg_queue_set(dplane->vbl.regs, idx, addr[0],
213 LCD_SPU_DMA_START_ADDR_Y0);
214 armada_reg_queue_set(dplane->vbl.regs, idx, addr[1],
215 LCD_SPU_DMA_START_ADDR_U0);
216 armada_reg_queue_set(dplane->vbl.regs, idx, addr[2],
217 LCD_SPU_DMA_START_ADDR_V0);
218 armada_reg_queue_set(dplane->vbl.regs, idx, addr[0],
219 LCD_SPU_DMA_START_ADDR_Y1);
220 armada_reg_queue_set(dplane->vbl.regs, idx, addr[1],
221 LCD_SPU_DMA_START_ADDR_U1);
222 armada_reg_queue_set(dplane->vbl.regs, idx, addr[2],
223 LCD_SPU_DMA_START_ADDR_V1);
225 val = fb->pitches[0] << 16 | fb->pitches[0];
226 armada_reg_queue_set(dplane->vbl.regs, idx, val,
227 LCD_SPU_DMA_PITCH_YC);
228 val = fb->pitches[1] << 16 | fb->pitches[2];
229 armada_reg_queue_set(dplane->vbl.regs, idx, val,
230 LCD_SPU_DMA_PITCH_UV);
233 val = (drm_rect_height(&src) & 0xffff0000) | drm_rect_width(&src) >> 16;
234 if (dplane->src_hw != val) {
235 dplane->src_hw = val;
236 armada_reg_queue_set(dplane->vbl.regs, idx, val,
237 LCD_SPU_DMA_HPXL_VLN);
240 val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest);
241 if (dplane->dst_hw != val) {
242 dplane->dst_hw = val;
243 armada_reg_queue_set(dplane->vbl.regs, idx, val,
244 LCD_SPU_DZM_HPXL_VLN);
247 val = dest.y1 << 16 | dest.x1;
248 if (dplane->dst_yx != val) {
249 dplane->dst_yx = val;
250 armada_reg_queue_set(dplane->vbl.regs, idx, val,
251 LCD_SPU_DMA_OVSA_HPXL_VLN);
254 if (dplane->ctrl0 != ctrl0) {
255 dplane->ctrl0 = ctrl0;
256 armada_reg_queue_mod(dplane->vbl.regs, idx, ctrl0,
257 CFG_CBSH_ENA | CFG_DMAFORMAT | CFG_DMA_FTOGGLE |
258 CFG_DMA_HSMOOTH | CFG_DMA_TSTMODE |
259 CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | CFG_SWAPYU |
260 CFG_YUV2RGB) | CFG_DMA_ENA,
264 armada_reg_queue_end(dplane->vbl.regs, idx);
265 armada_drm_vbl_event_add(dcrtc, &dplane->vbl.update);
270 static int armada_plane_disable(struct drm_plane *plane)
272 struct armada_plane *dplane = drm_to_armada_plane(plane);
273 struct drm_framebuffer *fb;
274 struct armada_crtc *dcrtc;
276 if (!dplane->base.crtc)
279 dcrtc = drm_to_armada_crtc(dplane->base.crtc);
282 spin_lock_irq(&dcrtc->irq_lock);
283 armada_drm_vbl_event_remove(dcrtc, &dplane->vbl.update);
284 armada_updatel(0, CFG_DMA_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
286 spin_unlock_irq(&dcrtc->irq_lock);
288 /* Power down the Y/U/V FIFOs */
289 armada_updatel(CFG_PDWN16x66 | CFG_PDWN32x66, 0,
290 dcrtc->base + LCD_SPU_SRAM_PARA1);
293 drm_framebuffer_unreference(plane->fb);
295 spin_lock_irq(&dplane->lock);
297 dplane->old_fb = NULL;
298 spin_unlock_irq(&dplane->lock);
300 drm_framebuffer_unreference(fb);
305 static void armada_plane_destroy(struct drm_plane *plane)
307 struct armada_plane *dplane = drm_to_armada_plane(plane);
309 drm_plane_cleanup(plane);
314 static int armada_plane_set_property(struct drm_plane *plane,
315 struct drm_property *property, uint64_t val)
317 struct armada_private *priv = plane->dev->dev_private;
318 struct armada_plane *dplane = drm_to_armada_plane(plane);
319 bool update_attr = false;
321 if (property == priv->colorkey_prop) {
322 #define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8)
323 dplane->prop.colorkey_yr = CCC(K2R(val));
324 dplane->prop.colorkey_ug = CCC(K2G(val));
325 dplane->prop.colorkey_vb = CCC(K2B(val));
328 } else if (property == priv->colorkey_min_prop) {
329 dplane->prop.colorkey_yr &= ~0x00ff0000;
330 dplane->prop.colorkey_yr |= K2R(val) << 16;
331 dplane->prop.colorkey_ug &= ~0x00ff0000;
332 dplane->prop.colorkey_ug |= K2G(val) << 16;
333 dplane->prop.colorkey_vb &= ~0x00ff0000;
334 dplane->prop.colorkey_vb |= K2B(val) << 16;
336 } else if (property == priv->colorkey_max_prop) {
337 dplane->prop.colorkey_yr &= ~0xff000000;
338 dplane->prop.colorkey_yr |= K2R(val) << 24;
339 dplane->prop.colorkey_ug &= ~0xff000000;
340 dplane->prop.colorkey_ug |= K2G(val) << 24;
341 dplane->prop.colorkey_vb &= ~0xff000000;
342 dplane->prop.colorkey_vb |= K2B(val) << 24;
344 } else if (property == priv->colorkey_val_prop) {
345 dplane->prop.colorkey_yr &= ~0x0000ff00;
346 dplane->prop.colorkey_yr |= K2R(val) << 8;
347 dplane->prop.colorkey_ug &= ~0x0000ff00;
348 dplane->prop.colorkey_ug |= K2G(val) << 8;
349 dplane->prop.colorkey_vb &= ~0x0000ff00;
350 dplane->prop.colorkey_vb |= K2B(val) << 8;
352 } else if (property == priv->colorkey_alpha_prop) {
353 dplane->prop.colorkey_yr &= ~0x000000ff;
354 dplane->prop.colorkey_yr |= K2R(val);
355 dplane->prop.colorkey_ug &= ~0x000000ff;
356 dplane->prop.colorkey_ug |= K2G(val);
357 dplane->prop.colorkey_vb &= ~0x000000ff;
358 dplane->prop.colorkey_vb |= K2B(val);
360 } else if (property == priv->colorkey_mode_prop) {
361 dplane->prop.colorkey_mode &= ~CFG_CKMODE_MASK;
362 dplane->prop.colorkey_mode |= CFG_CKMODE(val);
364 } else if (property == priv->brightness_prop) {
365 dplane->prop.brightness = val - 256;
367 } else if (property == priv->contrast_prop) {
368 dplane->prop.contrast = val;
370 } else if (property == priv->saturation_prop) {
371 dplane->prop.saturation = val;
375 if (update_attr && dplane->base.crtc)
376 armada_ovl_update_attr(&dplane->prop,
377 drm_to_armada_crtc(dplane->base.crtc));
382 static const struct drm_plane_funcs armada_plane_funcs = {
383 .update_plane = armada_plane_update,
384 .disable_plane = armada_plane_disable,
385 .destroy = armada_plane_destroy,
386 .set_property = armada_plane_set_property,
389 static const uint32_t armada_formats[] = {
410 static struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = {
411 { CKMODE_DISABLE, "disabled" },
412 { CKMODE_Y, "Y component" },
413 { CKMODE_U, "U component" },
414 { CKMODE_V, "V component" },
415 { CKMODE_RGB, "RGB" },
416 { CKMODE_R, "R component" },
417 { CKMODE_G, "G component" },
418 { CKMODE_B, "B component" },
421 static int armada_overlay_create_properties(struct drm_device *dev)
423 struct armada_private *priv = dev->dev_private;
425 if (priv->colorkey_prop)
428 priv->colorkey_prop = drm_property_create_range(dev, 0,
429 "colorkey", 0, 0xffffff);
430 priv->colorkey_min_prop = drm_property_create_range(dev, 0,
431 "colorkey_min", 0, 0xffffff);
432 priv->colorkey_max_prop = drm_property_create_range(dev, 0,
433 "colorkey_max", 0, 0xffffff);
434 priv->colorkey_val_prop = drm_property_create_range(dev, 0,
435 "colorkey_val", 0, 0xffffff);
436 priv->colorkey_alpha_prop = drm_property_create_range(dev, 0,
437 "colorkey_alpha", 0, 0xffffff);
438 priv->colorkey_mode_prop = drm_property_create_enum(dev, 0,
440 armada_drm_colorkey_enum_list,
441 ARRAY_SIZE(armada_drm_colorkey_enum_list));
442 priv->brightness_prop = drm_property_create_range(dev, 0,
443 "brightness", 0, 256 + 255);
444 priv->contrast_prop = drm_property_create_range(dev, 0,
445 "contrast", 0, 0x7fff);
446 priv->saturation_prop = drm_property_create_range(dev, 0,
447 "saturation", 0, 0x7fff);
449 if (!priv->colorkey_prop)
455 int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
457 struct armada_private *priv = dev->dev_private;
458 struct drm_mode_object *mobj;
459 struct armada_plane *dplane;
462 ret = armada_overlay_create_properties(dev);
466 dplane = kzalloc(sizeof(*dplane), GFP_KERNEL);
470 spin_lock_init(&dplane->lock);
471 init_waitqueue_head(&dplane->vbl.wait);
472 armada_drm_vbl_event_init(&dplane->vbl.update, armada_plane_vbl,
475 drm_plane_init(dev, &dplane->base, crtcs, &armada_plane_funcs,
476 armada_formats, ARRAY_SIZE(armada_formats), false);
478 dplane->prop.colorkey_yr = 0xfefefe00;
479 dplane->prop.colorkey_ug = 0x01010100;
480 dplane->prop.colorkey_vb = 0x01010100;
481 dplane->prop.colorkey_mode = CFG_CKMODE(CKMODE_RGB);
482 dplane->prop.brightness = 0;
483 dplane->prop.contrast = 0x4000;
484 dplane->prop.saturation = 0x4000;
486 mobj = &dplane->base.base;
487 drm_object_attach_property(mobj, priv->colorkey_prop,
489 drm_object_attach_property(mobj, priv->colorkey_min_prop,
491 drm_object_attach_property(mobj, priv->colorkey_max_prop,
493 drm_object_attach_property(mobj, priv->colorkey_val_prop,
495 drm_object_attach_property(mobj, priv->colorkey_alpha_prop,
497 drm_object_attach_property(mobj, priv->colorkey_mode_prop,
499 drm_object_attach_property(mobj, priv->brightness_prop, 256);
500 drm_object_attach_property(mobj, priv->contrast_prop,
501 dplane->prop.contrast);
502 drm_object_attach_property(mobj, priv->saturation_prop,
503 dplane->prop.saturation);