drivers/gpu/drm/arm/malidp_drv.c

   1 /*
   2  * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
   3  * Author: Liviu Dudau <Liviu.Dudau@arm.com>
   4  *
   5  * This program is free software and is provided to you under the terms of the
   6  * GNU General Public License version 2 as published by the Free Software
   7  * Foundation, and any use by you of this program is subject to the terms
   8  * of such GNU licence.
   9  *
  10  * ARM Mali DP500/DP550/DP650 KMS/DRM driver
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/console.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_graph.h>
  19 #include <linux/of_reserved_mem.h>
  20 #include <linux/pm_runtime.h>
  21
  22 #include <drm/drmP.h>
  23 #include <drm/drm_atomic.h>
  24 #include <drm/drm_atomic_helper.h>
  25 #include <drm/drm_crtc.h>
  26 #include <drm/drm_crtc_helper.h>
  27 #include <drm/drm_fb_cma_helper.h>
  28 #include <drm/drm_gem_cma_helper.h>
  29 #include <drm/drm_gem_framebuffer_helper.h>
  30 #include <drm/drm_modeset_helper.h>
  31 #include <drm/drm_of.h>
  32
  33 #include "malidp_drv.h"
  34 #include "malidp_regs.h"
  35 #include "malidp_hw.h"
  36
  37 #define MALIDP_CONF_VALID_TIMEOUT       250
  38
  39 static void malidp_write_gamma_table(struct malidp_hw_device *hwdev,
  40                                      u32 data[MALIDP_COEFFTAB_NUM_COEFFS])
  41 {
  42         int i;
  43         /* Update all channels with a single gamma curve. */
  44         const u32 gamma_write_mask = GENMASK(18, 16);
  45         /*
  46          * Always write an entire table, so the address field in
  47          * DE_COEFFTAB_ADDR is 0 and we can use the gamma_write_mask bitmask
  48          * directly.
  49          */
  50         malidp_hw_write(hwdev, gamma_write_mask,
  51                         hwdev->hw->map.coeffs_base + MALIDP_COEF_TABLE_ADDR);
  52         for (i = 0; i < MALIDP_COEFFTAB_NUM_COEFFS; ++i)
  53                 malidp_hw_write(hwdev, data[i],
  54                                 hwdev->hw->map.coeffs_base +
  55                                 MALIDP_COEF_TABLE_DATA);
  56 }
  57
  58 static void malidp_atomic_commit_update_gamma(struct drm_crtc *crtc,
  59                                               struct drm_crtc_state *old_state)
  60 {
  61         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  62         struct malidp_hw_device *hwdev = malidp->dev;
  63
  64         if (!crtc->state->color_mgmt_changed)
  65                 return;
  66
  67         if (!crtc->state->gamma_lut) {
  68                 malidp_hw_clearbits(hwdev,
  69                                     MALIDP_DISP_FUNC_GAMMA,
  70                                     MALIDP_DE_DISPLAY_FUNC);
  71         } else {
  72                 struct malidp_crtc_state *mc =
  73                         to_malidp_crtc_state(crtc->state);
  74
  75                 if (!old_state->gamma_lut || (crtc->state->gamma_lut->base.id !=
  76                                               old_state->gamma_lut->base.id))
  77                         malidp_write_gamma_table(hwdev, mc->gamma_coeffs);
  78
  79                 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_GAMMA,
  80                                   MALIDP_DE_DISPLAY_FUNC);
  81         }
  82 }
  83
  84 static
  85 void malidp_atomic_commit_update_coloradj(struct drm_crtc *crtc,
  86                                           struct drm_crtc_state *old_state)
  87 {
  88         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  89         struct malidp_hw_device *hwdev = malidp->dev;
  90         int i;
  91
  92         if (!crtc->state->color_mgmt_changed)
  93                 return;
  94
  95         if (!crtc->state->ctm) {
  96                 malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_CADJ,
  97                                     MALIDP_DE_DISPLAY_FUNC);
  98         } else {
  99                 struct malidp_crtc_state *mc =
 100                         to_malidp_crtc_state(crtc->state);
 101
 102                 if (!old_state->ctm || (crtc->state->ctm->base.id !=
 103                                         old_state->ctm->base.id))
 104                         for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; ++i)
 105                                 malidp_hw_write(hwdev,
 106                                                 mc->coloradj_coeffs[i],
 107                                                 hwdev->hw->map.coeffs_base +
 108                                                 MALIDP_COLOR_ADJ_COEF + 4 * i);
 109
 110                 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_CADJ,
 111                                   MALIDP_DE_DISPLAY_FUNC);
 112         }
 113 }
 114
 115 static void malidp_atomic_commit_se_config(struct drm_crtc *crtc,
 116                                            struct drm_crtc_state *old_state)
 117 {
 118         struct malidp_crtc_state *cs = to_malidp_crtc_state(crtc->state);
 119         struct malidp_crtc_state *old_cs = to_malidp_crtc_state(old_state);
 120         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 121         struct malidp_hw_device *hwdev = malidp->dev;
 122         struct malidp_se_config *s = &cs->scaler_config;
 123         struct malidp_se_config *old_s = &old_cs->scaler_config;
 124         u32 se_control = hwdev->hw->map.se_base +
 125                          ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ?
 126                          0x10 : 0xC);
 127         u32 layer_control = se_control + MALIDP_SE_LAYER_CONTROL;
 128         u32 scr = se_control + MALIDP_SE_SCALING_CONTROL;
 129         u32 val;
 130
 131         /* Set SE_CONTROL */
 132         if (!s->scale_enable) {
 133                 val = malidp_hw_read(hwdev, se_control);
 134                 val &= ~MALIDP_SE_SCALING_EN;
 135                 malidp_hw_write(hwdev, val, se_control);
 136                 return;
 137         }
 138
 139         hwdev->hw->se_set_scaling_coeffs(hwdev, s, old_s);
 140         val = malidp_hw_read(hwdev, se_control);
 141         val |= MALIDP_SE_SCALING_EN | MALIDP_SE_ALPHA_EN;
 142
 143         val &= ~MALIDP_SE_ENH(MALIDP_SE_ENH_MASK);
 144         val |= s->enhancer_enable ? MALIDP_SE_ENH(3) : 0;
 145
 146         val |= MALIDP_SE_RGBO_IF_EN;
 147         malidp_hw_write(hwdev, val, se_control);
 148
 149         /* Set IN_SIZE & OUT_SIZE. */
 150         val = MALIDP_SE_SET_V_SIZE(s->input_h) |
 151               MALIDP_SE_SET_H_SIZE(s->input_w);
 152         malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_IN_SIZE);
 153         val = MALIDP_SE_SET_V_SIZE(s->output_h) |
 154               MALIDP_SE_SET_H_SIZE(s->output_w);
 155         malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_OUT_SIZE);
 156
 157         /* Set phase regs. */
 158         malidp_hw_write(hwdev, s->h_init_phase, scr + MALIDP_SE_H_INIT_PH);
 159         malidp_hw_write(hwdev, s->h_delta_phase, scr + MALIDP_SE_H_DELTA_PH);
 160         malidp_hw_write(hwdev, s->v_init_phase, scr + MALIDP_SE_V_INIT_PH);
 161         malidp_hw_write(hwdev, s->v_delta_phase, scr + MALIDP_SE_V_DELTA_PH);
 162 }
 163
 164 /*
 165  * set the "config valid" bit and wait until the hardware acts on it
 166  */
 167 static int malidp_set_and_wait_config_valid(struct drm_device *drm)
 168 {
 169         struct malidp_drm *malidp = drm->dev_private;
 170         struct malidp_hw_device *hwdev = malidp->dev;
 171         int ret;
 172
 173         atomic_set(&malidp->config_valid, 0);
 174         hwdev->hw->set_config_valid(hwdev);
 175         /* don't wait for config_valid flag if we are in config mode */
 176         if (hwdev->hw->in_config_mode(hwdev))
 177                 return 0;
 178
 179         ret = wait_event_interruptible_timeout(malidp->wq,
 180                         atomic_read(&malidp->config_valid) == 1,
 181                         msecs_to_jiffies(MALIDP_CONF_VALID_TIMEOUT));
 182
 183         return (ret > 0) ? 0 : -ETIMEDOUT;
 184 }
 185
 186 static void malidp_output_poll_changed(struct drm_device *drm)
 187 {
 188         struct malidp_drm *malidp = drm->dev_private;
 189
 190         drm_fbdev_cma_hotplug_event(malidp->fbdev);
 191 }
 192
 193 static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state)
 194 {
 195         struct drm_pending_vblank_event *event;
 196         struct drm_device *drm = state->dev;
 197         struct malidp_drm *malidp = drm->dev_private;
 198
 199         if (malidp->crtc.enabled) {
 200                 /* only set config_valid if the CRTC is enabled */
 201                 if (malidp_set_and_wait_config_valid(drm))
 202                         DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n");
 203         }
 204
 205         event = malidp->crtc.state->event;
 206         if (event) {
 207                 malidp->crtc.state->event = NULL;
 208
 209                 spin_lock_irq(&drm->event_lock);
 210                 if (drm_crtc_vblank_get(&malidp->crtc) == 0)
 211                         drm_crtc_arm_vblank_event(&malidp->crtc, event);
 212                 else
 213                         drm_crtc_send_vblank_event(&malidp->crtc, event);
 214                 spin_unlock_irq(&drm->event_lock);
 215         }
 216         drm_atomic_helper_commit_hw_done(state);
 217 }
 218
 219 static void malidp_atomic_commit_tail(struct drm_atomic_state *state)
 220 {
 221         struct drm_device *drm = state->dev;
 222         struct drm_crtc *crtc;
 223         struct drm_crtc_state *old_crtc_state;
 224         int i;
 225
 226         pm_runtime_get_sync(drm->dev);
 227
 228         drm_atomic_helper_commit_modeset_disables(drm, state);
 229
 230         for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
 231                 malidp_atomic_commit_update_gamma(crtc, old_crtc_state);
 232                 malidp_atomic_commit_update_coloradj(crtc, old_crtc_state);
 233                 malidp_atomic_commit_se_config(crtc, old_crtc_state);
 234         }
 235
 236         drm_atomic_helper_commit_planes(drm, state, 0);
 237
 238         drm_atomic_helper_commit_modeset_enables(drm, state);
 239
 240         malidp_atomic_commit_hw_done(state);
 241
 242         drm_atomic_helper_wait_for_vblanks(drm, state);
 243
 244         pm_runtime_put(drm->dev);
 245
 246         drm_atomic_helper_cleanup_planes(drm, state);
 247 }
 248
 249 static const struct drm_mode_config_helper_funcs malidp_mode_config_helpers = {
 250         .atomic_commit_tail = malidp_atomic_commit_tail,
 251 };
 252
 253 static const struct drm_mode_config_funcs malidp_mode_config_funcs = {
 254         .fb_create = drm_gem_fb_create,
 255         .output_poll_changed = malidp_output_poll_changed,
 256         .atomic_check = drm_atomic_helper_check,
 257         .atomic_commit = drm_atomic_helper_commit,
 258 };
 259
 260 static int malidp_init(struct drm_device *drm)
 261 {
 262         int ret;
 263         struct malidp_drm *malidp = drm->dev_private;
 264         struct malidp_hw_device *hwdev = malidp->dev;
 265
 266         drm_mode_config_init(drm);
 267
 268         drm->mode_config.min_width = hwdev->min_line_size;
 269         drm->mode_config.min_height = hwdev->min_line_size;
 270         drm->mode_config.max_width = hwdev->max_line_size;
 271         drm->mode_config.max_height = hwdev->max_line_size;
 272         drm->mode_config.funcs = &malidp_mode_config_funcs;
 273         drm->mode_config.helper_private = &malidp_mode_config_helpers;
 274
 275         ret = malidp_crtc_init(drm);
 276         if (ret) {
 277                 drm_mode_config_cleanup(drm);
 278                 return ret;
 279         }
 280
 281         return 0;
 282 }
 283
 284 static void malidp_fini(struct drm_device *drm)
 285 {
 286         malidp_de_planes_destroy(drm);
 287         drm_mode_config_cleanup(drm);
 288 }
 289
 290 static int malidp_irq_init(struct platform_device *pdev)
 291 {
 292         int irq_de, irq_se, ret = 0;
 293         struct drm_device *drm = dev_get_drvdata(&pdev->dev);
 294
 295         /* fetch the interrupts from DT */
 296         irq_de = platform_get_irq_byname(pdev, "DE");
 297         if (irq_de < 0) {
 298                 DRM_ERROR("no 'DE' IRQ specified!\n");
 299                 return irq_de;
 300         }
 301         irq_se = platform_get_irq_byname(pdev, "SE");
 302         if (irq_se < 0) {
 303                 DRM_ERROR("no 'SE' IRQ specified!\n");
 304                 return irq_se;
 305         }
 306
 307         ret = malidp_de_irq_init(drm, irq_de);
 308         if (ret)
 309                 return ret;
 310
 311         ret = malidp_se_irq_init(drm, irq_se);
 312         if (ret) {
 313                 malidp_de_irq_fini(drm);
 314                 return ret;
 315         }
 316
 317         return 0;
 318 }
 319
 320 static void malidp_lastclose(struct drm_device *drm)
 321 {
 322         struct malidp_drm *malidp = drm->dev_private;
 323
 324         drm_fbdev_cma_restore_mode(malidp->fbdev);
 325 }
 326
 327 DEFINE_DRM_GEM_CMA_FOPS(fops);
 328
 329 static struct drm_driver malidp_driver = {
 330         .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC |
 331                            DRIVER_PRIME,
 332         .lastclose = malidp_lastclose,
 333         .gem_free_object_unlocked = drm_gem_cma_free_object,
 334         .gem_vm_ops = &drm_gem_cma_vm_ops,
 335         .dumb_create = drm_gem_cma_dumb_create,
 336         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 337         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 338         .gem_prime_export = drm_gem_prime_export,
 339         .gem_prime_import = drm_gem_prime_import,
 340         .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
 341         .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
 342         .gem_prime_vmap = drm_gem_cma_prime_vmap,
 343         .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
 344         .gem_prime_mmap = drm_gem_cma_prime_mmap,
 345         .fops = &fops,
 346         .name = "mali-dp",
 347         .desc = "ARM Mali Display Processor driver",
 348         .date = "20160106",
 349         .major = 1,
 350         .minor = 0,
 351 };
 352
 353 static const struct of_device_id  malidp_drm_of_match[] = {
 354         {
 355                 .compatible = "arm,mali-dp500",
 356                 .data = &malidp_device[MALIDP_500]
 357         },
 358         {
 359                 .compatible = "arm,mali-dp550",
 360                 .data = &malidp_device[MALIDP_550]
 361         },
 362         {
 363                 .compatible = "arm,mali-dp650",
 364                 .data = &malidp_device[MALIDP_650]
 365         },
 366         {},
 367 };
 368 MODULE_DEVICE_TABLE(of, malidp_drm_of_match);
 369
 370 static bool malidp_is_compatible_hw_id(struct malidp_hw_device *hwdev,
 371                                        const struct of_device_id *dev_id)
 372 {
 373         u32 core_id;
 374         const char *compatstr_dp500 = "arm,mali-dp500";
 375         bool is_dp500;
 376         bool dt_is_dp500;
 377
 378         /*
 379          * The DP500 CORE_ID register is in a different location, so check it
 380          * first. If the product id field matches, then this is DP500, otherwise
 381          * check the DP550/650 CORE_ID register.
 382          */
 383         core_id = malidp_hw_read(hwdev, MALIDP500_DC_BASE + MALIDP_DE_CORE_ID);
 384         /* Offset 0x18 will never read 0x500 on products other than DP500. */
 385         is_dp500 = (MALIDP_PRODUCT_ID(core_id) == 0x500);
 386         dt_is_dp500 = strnstr(dev_id->compatible, compatstr_dp500,
 387                               sizeof(dev_id->compatible)) != NULL;
 388         if (is_dp500 != dt_is_dp500) {
 389                 DRM_ERROR("Device-tree expects %s, but hardware %s DP500.\n",
 390                           dev_id->compatible, is_dp500 ? "is" : "is not");
 391                 return false;
 392         } else if (!dt_is_dp500) {
 393                 u16 product_id;
 394                 char buf[32];
 395
 396                 core_id = malidp_hw_read(hwdev,
 397                                          MALIDP550_DC_BASE + MALIDP_DE_CORE_ID);
 398                 product_id = MALIDP_PRODUCT_ID(core_id);
 399                 snprintf(buf, sizeof(buf), "arm,mali-dp%X", product_id);
 400                 if (!strnstr(dev_id->compatible, buf,
 401                              sizeof(dev_id->compatible))) {
 402                         DRM_ERROR("Device-tree expects %s, but hardware is DP%03X.\n",
 403                                   dev_id->compatible, product_id);
 404                         return false;
 405                 }
 406         }
 407         return true;
 408 }
 409
 410 static bool malidp_has_sufficient_address_space(const struct resource *res,
 411                                                 const struct of_device_id *dev_id)
 412 {
 413         resource_size_t res_size = resource_size(res);
 414         const char *compatstr_dp500 = "arm,mali-dp500";
 415
 416         if (!strnstr(dev_id->compatible, compatstr_dp500,
 417                      sizeof(dev_id->compatible)))
 418                 return res_size >= MALIDP550_ADDR_SPACE_SIZE;
 419         else if (res_size < MALIDP500_ADDR_SPACE_SIZE)
 420                 return false;
 421         return true;
 422 }
 423
 424 static ssize_t core_id_show(struct device *dev, struct device_attribute *attr,
 425                             char *buf)
 426 {
 427         struct drm_device *drm = dev_get_drvdata(dev);
 428         struct malidp_drm *malidp = drm->dev_private;
 429
 430         return snprintf(buf, PAGE_SIZE, "%08x\n", malidp->core_id);
 431 }
 432
 433 DEVICE_ATTR_RO(core_id);
 434
 435 static int malidp_init_sysfs(struct device *dev)
 436 {
 437         int ret = device_create_file(dev, &dev_attr_core_id);
 438
 439         if (ret)
 440                 DRM_ERROR("failed to create device file for core_id\n");
 441
 442         return ret;
 443 }
 444
 445 static void malidp_fini_sysfs(struct device *dev)
 446 {
 447         device_remove_file(dev, &dev_attr_core_id);
 448 }
 449
 450 #define MAX_OUTPUT_CHANNELS     3
 451
 452 static int malidp_runtime_pm_suspend(struct device *dev)
 453 {
 454         struct drm_device *drm = dev_get_drvdata(dev);
 455         struct malidp_drm *malidp = drm->dev_private;
 456         struct malidp_hw_device *hwdev = malidp->dev;
 457
 458         /* we can only suspend if the hardware is in config mode */
 459         WARN_ON(!hwdev->hw->in_config_mode(hwdev));
 460
 461         hwdev->pm_suspended = true;
 462         clk_disable_unprepare(hwdev->mclk);
 463         clk_disable_unprepare(hwdev->aclk);
 464         clk_disable_unprepare(hwdev->pclk);
 465
 466         return 0;
 467 }
 468
 469 static int malidp_runtime_pm_resume(struct device *dev)
 470 {
 471         struct drm_device *drm = dev_get_drvdata(dev);
 472         struct malidp_drm *malidp = drm->dev_private;
 473         struct malidp_hw_device *hwdev = malidp->dev;
 474
 475         clk_prepare_enable(hwdev->pclk);
 476         clk_prepare_enable(hwdev->aclk);
 477         clk_prepare_enable(hwdev->mclk);
 478         hwdev->pm_suspended = false;
 479
 480         return 0;
 481 }
 482
 483 static int malidp_bind(struct device *dev)
 484 {
 485         struct resource *res;
 486         struct drm_device *drm;
 487         struct malidp_drm *malidp;
 488         struct malidp_hw_device *hwdev;
 489         struct platform_device *pdev = to_platform_device(dev);
 490         struct of_device_id const *dev_id;
 491         /* number of lines for the R, G and B output */
 492         u8 output_width[MAX_OUTPUT_CHANNELS];
 493         int ret = 0, i;
 494         u32 version, out_depth = 0;
 495
 496         malidp = devm_kzalloc(dev, sizeof(*malidp), GFP_KERNEL);
 497         if (!malidp)
 498                 return -ENOMEM;
 499
 500         hwdev = devm_kzalloc(dev, sizeof(*hwdev), GFP_KERNEL);
 501         if (!hwdev)
 502                 return -ENOMEM;
 503
 504         hwdev->hw = (struct malidp_hw *)of_device_get_match_data(dev);
 505         malidp->dev = hwdev;
 506
 507         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 508         hwdev->regs = devm_ioremap_resource(dev, res);
 509         if (IS_ERR(hwdev->regs))
 510                 return PTR_ERR(hwdev->regs);
 511
 512         hwdev->pclk = devm_clk_get(dev, "pclk");
 513         if (IS_ERR(hwdev->pclk))
 514                 return PTR_ERR(hwdev->pclk);
 515
 516         hwdev->aclk = devm_clk_get(dev, "aclk");
 517         if (IS_ERR(hwdev->aclk))
 518                 return PTR_ERR(hwdev->aclk);
 519
 520         hwdev->mclk = devm_clk_get(dev, "mclk");
 521         if (IS_ERR(hwdev->mclk))
 522                 return PTR_ERR(hwdev->mclk);
 523
 524         hwdev->pxlclk = devm_clk_get(dev, "pxlclk");
 525         if (IS_ERR(hwdev->pxlclk))
 526                 return PTR_ERR(hwdev->pxlclk);
 527
 528         /* Get the optional framebuffer memory resource */
 529         ret = of_reserved_mem_device_init(dev);
 530         if (ret && ret != -ENODEV)
 531                 return ret;
 532
 533         drm = drm_dev_alloc(&malidp_driver, dev);
 534         if (IS_ERR(drm)) {
 535                 ret = PTR_ERR(drm);
 536                 goto alloc_fail;
 537         }
 538
 539         drm->dev_private = malidp;
 540         dev_set_drvdata(dev, drm);
 541
 542         /* Enable power management */
 543         pm_runtime_enable(dev);
 544
 545         /* Resume device to enable the clocks */
 546         if (pm_runtime_enabled(dev))
 547                 pm_runtime_get_sync(dev);
 548         else
 549                 malidp_runtime_pm_resume(dev);
 550
 551         dev_id = of_match_device(malidp_drm_of_match, dev);
 552         if (!dev_id) {
 553                 ret = -EINVAL;
 554                 goto query_hw_fail;
 555         }
 556
 557         if (!malidp_has_sufficient_address_space(res, dev_id)) {
 558                 DRM_ERROR("Insufficient address space in device-tree.\n");
 559                 ret = -EINVAL;
 560                 goto query_hw_fail;
 561         }
 562
 563         if (!malidp_is_compatible_hw_id(hwdev, dev_id)) {
 564                 ret = -EINVAL;
 565                 goto query_hw_fail;
 566         }
 567
 568         ret = hwdev->hw->query_hw(hwdev);
 569         if (ret) {
 570                 DRM_ERROR("Invalid HW configuration\n");
 571                 goto query_hw_fail;
 572         }
 573
 574         version = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_DE_CORE_ID);
 575         DRM_INFO("found ARM Mali-DP%3x version r%dp%d\n", version >> 16,
 576                  (version >> 12) & 0xf, (version >> 8) & 0xf);
 577
 578         malidp->core_id = version;
 579
 580         /* set the number of lines used for output of RGB data */
 581         ret = of_property_read_u8_array(dev->of_node,
 582                                         "arm,malidp-output-port-lines",
 583                                         output_width, MAX_OUTPUT_CHANNELS);
 584         if (ret)
 585                 goto query_hw_fail;
 586
 587         for (i = 0; i < MAX_OUTPUT_CHANNELS; i++)
 588                 out_depth = (out_depth << 8) | (output_width[i] & 0xf);
 589         malidp_hw_write(hwdev, out_depth, hwdev->hw->map.out_depth_base);
 590
 591         atomic_set(&malidp->config_valid, 0);
 592         init_waitqueue_head(&malidp->wq);
 593
 594         ret = malidp_init(drm);
 595         if (ret < 0)
 596                 goto query_hw_fail;
 597
 598         ret = malidp_init_sysfs(dev);
 599         if (ret)
 600                 goto init_fail;
 601
 602         /* Set the CRTC's port so that the encoder component can find it */
 603         malidp->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
 604
 605         ret = component_bind_all(dev, drm);
 606         if (ret) {
 607                 DRM_ERROR("Failed to bind all components\n");
 608                 goto bind_fail;
 609         }
 610
 611         ret = malidp_irq_init(pdev);
 612         if (ret < 0)
 613                 goto irq_init_fail;
 614
 615         drm->irq_enabled = true;
 616
 617         ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
 618         if (ret < 0) {
 619                 DRM_ERROR("failed to initialise vblank\n");
 620                 goto vblank_fail;
 621         }
 622         pm_runtime_put(dev);
 623
 624         drm_mode_config_reset(drm);
 625
 626         malidp->fbdev = drm_fbdev_cma_init(drm, 32,
 627                                            drm->mode_config.num_connector);
 628
 629         if (IS_ERR(malidp->fbdev)) {
 630                 ret = PTR_ERR(malidp->fbdev);
 631                 malidp->fbdev = NULL;
 632                 goto fbdev_fail;
 633         }
 634
 635         drm_kms_helper_poll_init(drm);
 636
 637         ret = drm_dev_register(drm, 0);
 638         if (ret)
 639                 goto register_fail;
 640
 641         return 0;
 642
 643 register_fail:
 644         if (malidp->fbdev) {
 645                 drm_fbdev_cma_fini(malidp->fbdev);
 646                 malidp->fbdev = NULL;
 647         }
 648         drm_kms_helper_poll_fini(drm);
 649 fbdev_fail:
 650         pm_runtime_get_sync(dev);
 651 vblank_fail:
 652         malidp_se_irq_fini(drm);
 653         malidp_de_irq_fini(drm);
 654         drm->irq_enabled = false;
 655 irq_init_fail:
 656         component_unbind_all(dev, drm);
 657 bind_fail:
 658         of_node_put(malidp->crtc.port);
 659         malidp->crtc.port = NULL;
 660 init_fail:
 661         malidp_fini_sysfs(dev);
 662         malidp_fini(drm);
 663 query_hw_fail:
 664         pm_runtime_put(dev);
 665         if (pm_runtime_enabled(dev))
 666                 pm_runtime_disable(dev);
 667         else
 668                 malidp_runtime_pm_suspend(dev);
 669         drm->dev_private = NULL;
 670         dev_set_drvdata(dev, NULL);
 671         drm_dev_put(drm);
 672 alloc_fail:
 673         of_reserved_mem_device_release(dev);
 674
 675         return ret;
 676 }
 677
 678 static void malidp_unbind(struct device *dev)
 679 {
 680         struct drm_device *drm = dev_get_drvdata(dev);
 681         struct malidp_drm *malidp = drm->dev_private;
 682
 683         drm_dev_unregister(drm);
 684         if (malidp->fbdev) {
 685                 drm_fbdev_cma_fini(malidp->fbdev);
 686                 malidp->fbdev = NULL;
 687         }
 688         drm_kms_helper_poll_fini(drm);
 689         pm_runtime_get_sync(dev);
 690         malidp_se_irq_fini(drm);
 691         malidp_de_irq_fini(drm);
 692         component_unbind_all(dev, drm);
 693         of_node_put(malidp->crtc.port);
 694         malidp->crtc.port = NULL;
 695         malidp_fini_sysfs(dev);
 696         malidp_fini(drm);
 697         pm_runtime_put(dev);
 698         if (pm_runtime_enabled(dev))
 699                 pm_runtime_disable(dev);
 700         else
 701                 malidp_runtime_pm_suspend(dev);
 702         drm->dev_private = NULL;
 703         dev_set_drvdata(dev, NULL);
 704         drm_dev_put(drm);
 705         of_reserved_mem_device_release(dev);
 706 }
 707
 708 static const struct component_master_ops malidp_master_ops = {
 709         .bind = malidp_bind,
 710         .unbind = malidp_unbind,
 711 };
 712
 713 static int malidp_compare_dev(struct device *dev, void *data)
 714 {
 715         struct device_node *np = data;
 716
 717         return dev->of_node == np;
 718 }
 719
 720 static int malidp_platform_probe(struct platform_device *pdev)
 721 {
 722         struct device_node *port;
 723         struct component_match *match = NULL;
 724
 725         if (!pdev->dev.of_node)
 726                 return -ENODEV;
 727
 728         /* there is only one output port inside each device, find it */
 729         port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
 730         if (!port)
 731                 return -ENODEV;
 732
 733         drm_of_component_match_add(&pdev->dev, &match, malidp_compare_dev,
 734                                    port);
 735         of_node_put(port);
 736         return component_master_add_with_match(&pdev->dev, &malidp_master_ops,
 737                                                match);
 738 }
 739
 740 static int malidp_platform_remove(struct platform_device *pdev)
 741 {
 742         component_master_del(&pdev->dev, &malidp_master_ops);
 743         return 0;
 744 }
 745
 746 static int __maybe_unused malidp_pm_suspend(struct device *dev)
 747 {
 748         struct drm_device *drm = dev_get_drvdata(dev);
 749
 750         return drm_mode_config_helper_suspend(drm);
 751 }
 752
 753 static int __maybe_unused malidp_pm_resume(struct device *dev)
 754 {
 755         struct drm_device *drm = dev_get_drvdata(dev);
 756
 757         drm_mode_config_helper_resume(drm);
 758
 759         return 0;
 760 }
 761
 762 static const struct dev_pm_ops malidp_pm_ops = {
 763         SET_SYSTEM_SLEEP_PM_OPS(malidp_pm_suspend, malidp_pm_resume) \
 764         SET_RUNTIME_PM_OPS(malidp_runtime_pm_suspend, malidp_runtime_pm_resume, NULL)
 765 };
 766
 767 static struct platform_driver malidp_platform_driver = {
 768         .probe          = malidp_platform_probe,
 769         .remove         = malidp_platform_remove,
 770         .driver = {
 771                 .name = "mali-dp",
 772                 .pm = &malidp_pm_ops,
 773                 .of_match_table = malidp_drm_of_match,
 774         },
 775 };
 776
 777 module_platform_driver(malidp_platform_driver);
 778
 779 MODULE_AUTHOR("Liviu Dudau <Liviu.Dudau@arm.com>");
 780 MODULE_DESCRIPTION("ARM Mali DP DRM driver");
 781 MODULE_LICENSE("GPL v2");