drivers/gpu/drm/amd/powerplay/vega20_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "atomfirmware.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "smu_v11_0.h"
  31 #include "smu11_driver_if.h"
  32 #include "soc15_common.h"
  33 #include "atom.h"
  34 #include "power_state.h"
  35 #include "vega20_ppt.h"
  36 #include "vega20_pptable.h"
  37 #include "vega20_ppsmc.h"
  38 #include "nbio/nbio_7_4_sh_mask.h"
  39
  40 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  41 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  42
  43 #define MSG_MAP(msg, index) \
  44         [SMU_MSG_##msg] = index
  45
  46 static int vega20_message_map[SMU_MSG_MAX_COUNT] = {
  47         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
  48         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
  49         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
  50         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow),
  51         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  52         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures),
  53         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures),
  54         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow),
  55         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh),
  56         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow),
  57         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh),
  58         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetEnabledSmuFeaturesLow),
  59         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  60         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask),
  61         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit),
  62         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
  63         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
  64         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh),
  65         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow),
  66         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
  67         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
  68         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable),
  69         MSG_MAP(UseBackupPPTable,               PPSMC_MSG_UseBackupPPTable),
  70         MSG_MAP(RunBtc,                         PPSMC_MSG_RunBtc),
  71         MSG_MAP(RequestI2CBus,                  PPSMC_MSG_RequestI2CBus),
  72         MSG_MAP(ReleaseI2CBus,                  PPSMC_MSG_ReleaseI2CBus),
  73         MSG_MAP(SetFloorSocVoltage,             PPSMC_MSG_SetFloorSocVoltage),
  74         MSG_MAP(SoftReset,                      PPSMC_MSG_SoftReset),
  75         MSG_MAP(StartBacoMonitor,               PPSMC_MSG_StartBacoMonitor),
  76         MSG_MAP(CancelBacoMonitor,              PPSMC_MSG_CancelBacoMonitor),
  77         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco),
  78         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq),
  79         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq),
  80         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq),
  81         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq),
  82         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq),
  83         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq),
  84         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex),
  85         MSG_MAP(GetDpmClockFreq,                PPSMC_MSG_GetDpmClockFreq),
  86         MSG_MAP(GetSsVoltageByDpm,              PPSMC_MSG_GetSsVoltageByDpm),
  87         MSG_MAP(SetMemoryChannelConfig,         PPSMC_MSG_SetMemoryChannelConfig),
  88         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode),
  89         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh),
  90         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow),
  91         MSG_MAP(SetMinLinkDpmByIndex,           PPSMC_MSG_SetMinLinkDpmByIndex),
  92         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters),
  93         MSG_MAP(OverDriveSetPercentage,         PPSMC_MSG_OverDriveSetPercentage),
  94         MSG_MAP(SetMinDeepSleepDcefclk,         PPSMC_MSG_SetMinDeepSleepDcefclk),
  95         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt),
  96         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource),
  97         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch),
  98         MSG_MAP(SetUclkDownHyst,                PPSMC_MSG_SetUclkDownHyst),
  99         MSG_MAP(GetCurrentRpm,                  PPSMC_MSG_GetCurrentRpm),
 100         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
 101         MSG_MAP(SetTjMax,                       PPSMC_MSG_SetTjMax),
 102         MSG_MAP(SetFanTemperatureTarget,        PPSMC_MSG_SetFanTemperatureTarget),
 103         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload),
 104         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh),
 105         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow),
 106         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize),
 107         MSG_MAP(SetFanMaxRpm,                   PPSMC_MSG_SetFanMaxRpm),
 108         MSG_MAP(SetFanMinPwm,                   PPSMC_MSG_SetFanMinPwm),
 109         MSG_MAP(ConfigureGfxDidt,               PPSMC_MSG_ConfigureGfxDidt),
 110         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_NumOfDisplays),
 111         MSG_MAP(RemoveMargins,                  PPSMC_MSG_RemoveMargins),
 112         MSG_MAP(ReadSerialNumTop32,             PPSMC_MSG_ReadSerialNumTop32),
 113         MSG_MAP(ReadSerialNumBottom32,          PPSMC_MSG_ReadSerialNumBottom32),
 114         MSG_MAP(SetSystemVirtualDramAddrHigh,   PPSMC_MSG_SetSystemVirtualDramAddrHigh),
 115         MSG_MAP(SetSystemVirtualDramAddrLow,    PPSMC_MSG_SetSystemVirtualDramAddrLow),
 116         MSG_MAP(WaflTest,                       PPSMC_MSG_WaflTest),
 117         MSG_MAP(SetFclkGfxClkRatio,             PPSMC_MSG_SetFclkGfxClkRatio),
 118         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff),
 119         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff),
 120         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit),
 121         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq),
 122         MSG_MAP(GetDebugData,                   PPSMC_MSG_GetDebugData),
 123         MSG_MAP(SetXgmiMode,                    PPSMC_MSG_SetXgmiMode),
 124         MSG_MAP(RunAfllBtc,                     PPSMC_MSG_RunAfllBtc),
 125         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco),
 126         MSG_MAP(PrepareMp1ForReset,             PPSMC_MSG_PrepareMp1ForReset),
 127         MSG_MAP(PrepareMp1ForShutdown,          PPSMC_MSG_PrepareMp1ForShutdown),
 128         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm),
 129         MSG_MAP(GetAVFSVoltageByDpm,            PPSMC_MSG_GetAVFSVoltageByDpm),
 130 };
 131
 132 static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 133 {
 134         int val;
 135         if (index > SMU_MSG_MAX_COUNT)
 136                 return -EINVAL;
 137
 138         val = vega20_message_map[index];
 139         if (val > PPSMC_Message_Count)
 140                 return -EINVAL;
 141
 142         return val;
 143 }
 144
 145 static int vega20_allocate_dpm_context(struct smu_context *smu)
 146 {
 147         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 148
 149         if (smu_dpm->dpm_context)
 150                 return -EINVAL;
 151
 152         smu_dpm->dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
 153                                        GFP_KERNEL);
 154         if (!smu_dpm->dpm_context)
 155                 return -ENOMEM;
 156
 157         if (smu_dpm->golden_dpm_context)
 158                 return -EINVAL;
 159
 160         smu_dpm->golden_dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
 161                                               GFP_KERNEL);
 162         if (!smu_dpm->golden_dpm_context)
 163                 return -ENOMEM;
 164
 165         smu_dpm->dpm_context_size = sizeof(struct vega20_dpm_table);
 166
 167         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 168                                        GFP_KERNEL);
 169         if (!smu_dpm->dpm_current_power_state)
 170                 return -ENOMEM;
 171
 172         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 173                                        GFP_KERNEL);
 174         if (!smu_dpm->dpm_request_power_state)
 175                 return -ENOMEM;
 176
 177         return 0;
 178 }
 179
 180 static int vega20_setup_od8_information(struct smu_context *smu)
 181 {
 182         ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
 183         struct smu_table_context *table_context = &smu->smu_table;
 184
 185         uint32_t od_feature_count, od_feature_array_size,
 186                  od_setting_count, od_setting_array_size;
 187
 188         if (!table_context->power_play_table)
 189                 return -EINVAL;
 190
 191         powerplay_table = table_context->power_play_table;
 192
 193         if (powerplay_table->OverDrive8Table.ucODTableRevision == 1) {
 194                 /* Setup correct ODFeatureCount, and store ODFeatureArray from
 195                  * powerplay table to od_feature_capabilities */
 196                 od_feature_count =
 197                         (le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount) >
 198                          ATOM_VEGA20_ODFEATURE_COUNT) ?
 199                         ATOM_VEGA20_ODFEATURE_COUNT :
 200                         le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount);
 201
 202                 od_feature_array_size = sizeof(uint8_t) * od_feature_count;
 203
 204                 if (table_context->od_feature_capabilities)
 205                         return -EINVAL;
 206
 207                 table_context->od_feature_capabilities = kzalloc(od_feature_array_size, GFP_KERNEL);
 208                 if (!table_context->od_feature_capabilities)
 209                         return -ENOMEM;
 210
 211                 memcpy(table_context->od_feature_capabilities,
 212                        &powerplay_table->OverDrive8Table.ODFeatureCapabilities,
 213                        od_feature_array_size);
 214
 215                 /* Setup correct ODSettingCount, and store ODSettingArray from
 216                  * powerplay table to od_settings_max and od_setting_min */
 217                 od_setting_count =
 218                         (le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount) >
 219                          ATOM_VEGA20_ODSETTING_COUNT) ?
 220                         ATOM_VEGA20_ODSETTING_COUNT :
 221                         le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount);
 222
 223                 od_setting_array_size = sizeof(uint32_t) * od_setting_count;
 224
 225                 if (table_context->od_settings_max)
 226                         return -EINVAL;
 227
 228                 table_context->od_settings_max = kzalloc(od_setting_array_size, GFP_KERNEL);
 229
 230                 if (!table_context->od_settings_max) {
 231                         kfree(table_context->od_feature_capabilities);
 232                         table_context->od_feature_capabilities = NULL;
 233                         return -ENOMEM;
 234                 }
 235
 236                 memcpy(table_context->od_settings_max,
 237                        &powerplay_table->OverDrive8Table.ODSettingsMax,
 238                        od_setting_array_size);
 239
 240                 if (table_context->od_settings_min)
 241                         return -EINVAL;
 242
 243                 table_context->od_settings_min = kzalloc(od_setting_array_size, GFP_KERNEL);
 244
 245                 if (!table_context->od_settings_min) {
 246                         kfree(table_context->od_feature_capabilities);
 247                         table_context->od_feature_capabilities = NULL;
 248                         kfree(table_context->od_settings_max);
 249                         table_context->od_settings_max = NULL;
 250                         return -ENOMEM;
 251                 }
 252
 253                 memcpy(table_context->od_settings_min,
 254                        &powerplay_table->OverDrive8Table.ODSettingsMin,
 255                        od_setting_array_size);
 256         }
 257
 258         return 0;
 259 }
 260
 261 static int vega20_store_powerplay_table(struct smu_context *smu)
 262 {
 263         ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
 264         struct smu_table_context *table_context = &smu->smu_table;
 265         int ret;
 266
 267         if (!table_context->power_play_table)
 268                 return -EINVAL;
 269
 270         powerplay_table = table_context->power_play_table;
 271
 272         memcpy(table_context->driver_pptable, &powerplay_table->smcPPTable,
 273                sizeof(PPTable_t));
 274
 275         table_context->software_shutdown_temp = powerplay_table->usSoftwareShutdownTemp;
 276         table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
 277         table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
 278
 279         ret = vega20_setup_od8_information(smu);
 280
 281         return ret;
 282 }
 283
 284 static int vega20_append_powerplay_table(struct smu_context *smu)
 285 {
 286         struct smu_table_context *table_context = &smu->smu_table;
 287         PPTable_t *smc_pptable = table_context->driver_pptable;
 288         struct atom_smc_dpm_info_v4_4 *smc_dpm_table;
 289         int index, i, ret;
 290
 291         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 292                                            smc_dpm_info);
 293
 294         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 295                                       (uint8_t **)&smc_dpm_table);
 296         if (ret)
 297                 return ret;
 298
 299         smc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx;
 300         smc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc;
 301
 302         smc_pptable->VddGfxVrMapping = smc_dpm_table->vddgfxvrmapping;
 303         smc_pptable->VddSocVrMapping = smc_dpm_table->vddsocvrmapping;
 304         smc_pptable->VddMem0VrMapping = smc_dpm_table->vddmem0vrmapping;
 305         smc_pptable->VddMem1VrMapping = smc_dpm_table->vddmem1vrmapping;
 306
 307         smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->gfxulvphasesheddingmask;
 308         smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->soculvphasesheddingmask;
 309         smc_pptable->ExternalSensorPresent = smc_dpm_table->externalsensorpresent;
 310
 311         smc_pptable->GfxMaxCurrent = smc_dpm_table->gfxmaxcurrent;
 312         smc_pptable->GfxOffset = smc_dpm_table->gfxoffset;
 313         smc_pptable->Padding_TelemetryGfx = smc_dpm_table->padding_telemetrygfx;
 314
 315         smc_pptable->SocMaxCurrent = smc_dpm_table->socmaxcurrent;
 316         smc_pptable->SocOffset = smc_dpm_table->socoffset;
 317         smc_pptable->Padding_TelemetrySoc = smc_dpm_table->padding_telemetrysoc;
 318
 319         smc_pptable->Mem0MaxCurrent = smc_dpm_table->mem0maxcurrent;
 320         smc_pptable->Mem0Offset = smc_dpm_table->mem0offset;
 321         smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->padding_telemetrymem0;
 322
 323         smc_pptable->Mem1MaxCurrent = smc_dpm_table->mem1maxcurrent;
 324         smc_pptable->Mem1Offset = smc_dpm_table->mem1offset;
 325         smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->padding_telemetrymem1;
 326
 327         smc_pptable->AcDcGpio = smc_dpm_table->acdcgpio;
 328         smc_pptable->AcDcPolarity = smc_dpm_table->acdcpolarity;
 329         smc_pptable->VR0HotGpio = smc_dpm_table->vr0hotgpio;
 330         smc_pptable->VR0HotPolarity = smc_dpm_table->vr0hotpolarity;
 331
 332         smc_pptable->VR1HotGpio = smc_dpm_table->vr1hotgpio;
 333         smc_pptable->VR1HotPolarity = smc_dpm_table->vr1hotpolarity;
 334         smc_pptable->Padding1 = smc_dpm_table->padding1;
 335         smc_pptable->Padding2 = smc_dpm_table->padding2;
 336
 337         smc_pptable->LedPin0 = smc_dpm_table->ledpin0;
 338         smc_pptable->LedPin1 = smc_dpm_table->ledpin1;
 339         smc_pptable->LedPin2 = smc_dpm_table->ledpin2;
 340
 341         smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->pllgfxclkspreadenabled;
 342         smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->pllgfxclkspreadpercent;
 343         smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->pllgfxclkspreadfreq;
 344
 345         smc_pptable->UclkSpreadEnabled = 0;
 346         smc_pptable->UclkSpreadPercent = smc_dpm_table->uclkspreadpercent;
 347         smc_pptable->UclkSpreadFreq = smc_dpm_table->uclkspreadfreq;
 348
 349         smc_pptable->FclkSpreadEnabled = smc_dpm_table->fclkspreadenabled;
 350         smc_pptable->FclkSpreadPercent = smc_dpm_table->fclkspreadpercent;
 351         smc_pptable->FclkSpreadFreq = smc_dpm_table->fclkspreadfreq;
 352
 353         smc_pptable->FllGfxclkSpreadEnabled = smc_dpm_table->fllgfxclkspreadenabled;
 354         smc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent;
 355         smc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq;
 356
 357         for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
 358                 smc_pptable->I2cControllers[i].Enabled =
 359                         smc_dpm_table->i2ccontrollers[i].enabled;
 360                 smc_pptable->I2cControllers[i].SlaveAddress =
 361                         smc_dpm_table->i2ccontrollers[i].slaveaddress;
 362                 smc_pptable->I2cControllers[i].ControllerPort =
 363                         smc_dpm_table->i2ccontrollers[i].controllerport;
 364                 smc_pptable->I2cControllers[i].ThermalThrottler =
 365                         smc_dpm_table->i2ccontrollers[i].thermalthrottler;
 366                 smc_pptable->I2cControllers[i].I2cProtocol =
 367                         smc_dpm_table->i2ccontrollers[i].i2cprotocol;
 368                 smc_pptable->I2cControllers[i].I2cSpeed =
 369                         smc_dpm_table->i2ccontrollers[i].i2cspeed;
 370         }
 371
 372         return 0;
 373 }
 374
 375 static int vega20_check_powerplay_table(struct smu_context *smu)
 376 {
 377         ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
 378         struct smu_table_context *table_context = &smu->smu_table;
 379
 380         powerplay_table = table_context->power_play_table;
 381
 382         if (powerplay_table->sHeader.format_revision < ATOM_VEGA20_TABLE_REVISION_VEGA20) {
 383                 pr_err("Unsupported PPTable format!");
 384                 return -EINVAL;
 385         }
 386
 387         if (!powerplay_table->sHeader.structuresize) {
 388                 pr_err("Invalid PowerPlay Table!");
 389                 return -EINVAL;
 390         }
 391
 392         return 0;
 393 }
 394
 395 static int vega20_run_btc_afll(struct smu_context *smu)
 396 {
 397         return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
 398 }
 399
 400 static int
 401 vega20_get_unallowed_feature_mask(struct smu_context *smu,
 402                                   uint32_t *feature_mask, uint32_t num)
 403 {
 404         if (num > 2)
 405                 return -EINVAL;
 406
 407         feature_mask[0] = 0xE0041C00;
 408         feature_mask[1] = 0xFFFFFFFE; /* bit32~bit63 is Unsupported */
 409
 410         return 0;
 411 }
 412
 413 static enum
 414 amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
 415 {
 416         enum amd_pm_state_type pm_type;
 417         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 418
 419         if (!smu_dpm_ctx->dpm_context ||
 420             !smu_dpm_ctx->dpm_current_power_state)
 421                 return -EINVAL;
 422
 423         mutex_lock(&(smu->mutex));
 424         switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
 425         case SMU_STATE_UI_LABEL_BATTERY:
 426                 pm_type = POWER_STATE_TYPE_BATTERY;
 427                 break;
 428         case SMU_STATE_UI_LABEL_BALLANCED:
 429                 pm_type = POWER_STATE_TYPE_BALANCED;
 430                 break;
 431         case SMU_STATE_UI_LABEL_PERFORMANCE:
 432                 pm_type = POWER_STATE_TYPE_PERFORMANCE;
 433                 break;
 434         default:
 435                 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
 436                         pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
 437                 else
 438                         pm_type = POWER_STATE_TYPE_DEFAULT;
 439                 break;
 440         }
 441         mutex_unlock(&(smu->mutex));
 442
 443         return pm_type;
 444 }
 445
 446 static int
 447 vega20_set_single_dpm_table(struct smu_context *smu,
 448                             struct vega20_single_dpm_table *single_dpm_table,
 449                             PPCLK_e clk_id)
 450 {
 451         int ret = 0;
 452         uint32_t i, num_of_levels, clk;
 453
 454         ret = smu_send_smc_msg_with_param(smu,
 455                         SMU_MSG_GetDpmFreqByIndex,
 456                         (clk_id << 16 | 0xFF));
 457         if (ret) {
 458                 pr_err("[GetNumOfDpmLevel] failed to get dpm levels!");
 459                 return ret;
 460         }
 461
 462         smu_read_smc_arg(smu, &num_of_levels);
 463         if (!num_of_levels) {
 464                 pr_err("[GetNumOfDpmLevel] number of clk levels is invalid!");
 465                 return -EINVAL;
 466         }
 467
 468         single_dpm_table->count = num_of_levels;
 469
 470         for (i = 0; i < num_of_levels; i++) {
 471                 ret = smu_send_smc_msg_with_param(smu,
 472                                 SMU_MSG_GetDpmFreqByIndex,
 473                                 (clk_id << 16 | i));
 474                 if (ret) {
 475                         pr_err("[GetDpmFreqByIndex] failed to get dpm freq by index!");
 476                         return ret;
 477                 }
 478                 smu_read_smc_arg(smu, &clk);
 479                 if (!clk) {
 480                         pr_err("[GetDpmFreqByIndex] clk value is invalid!");
 481                         return -EINVAL;
 482                 }
 483                 single_dpm_table->dpm_levels[i].value = clk;
 484                 single_dpm_table->dpm_levels[i].enabled = true;
 485         }
 486         return 0;
 487 }
 488
 489 static void vega20_init_single_dpm_state(struct vega20_dpm_state *dpm_state)
 490 {
 491         dpm_state->soft_min_level = 0x0;
 492         dpm_state->soft_max_level = 0xffff;
 493         dpm_state->hard_min_level = 0x0;
 494         dpm_state->hard_max_level = 0xffff;
 495 }
 496
 497 static int vega20_set_default_dpm_table(struct smu_context *smu)
 498 {
 499         int ret;
 500
 501         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 502         struct vega20_dpm_table *dpm_table = NULL;
 503         struct vega20_single_dpm_table *single_dpm_table;
 504
 505         dpm_table = smu_dpm->dpm_context;
 506
 507         /* socclk */
 508         single_dpm_table = &(dpm_table->soc_table);
 509
 510         if (smu_feature_is_enabled(smu, FEATURE_DPM_SOCCLK_BIT)) {
 511                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 512                                                   PPCLK_SOCCLK);
 513                 if (ret) {
 514                         pr_err("[SetupDefaultDpmTable] failed to get socclk dpm levels!");
 515                         return ret;
 516                 }
 517         } else {
 518                 single_dpm_table->count = 1;
 519                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 520         }
 521         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 522
 523         /* gfxclk */
 524         single_dpm_table = &(dpm_table->gfx_table);
 525
 526         if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT)) {
 527                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 528                                                   PPCLK_GFXCLK);
 529                 if (ret) {
 530                         pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
 531                         return ret;
 532                 }
 533         } else {
 534                 single_dpm_table->count = 1;
 535                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 536         }
 537         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 538
 539         /* memclk */
 540         single_dpm_table = &(dpm_table->mem_table);
 541
 542         if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
 543                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 544                                                   PPCLK_UCLK);
 545                 if (ret) {
 546                         pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
 547                         return ret;
 548                 }
 549         } else {
 550                 single_dpm_table->count = 1;
 551                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 552         }
 553         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 554
 555         /* eclk */
 556         single_dpm_table = &(dpm_table->eclk_table);
 557
 558         if (smu_feature_is_enabled(smu, FEATURE_DPM_VCE_BIT)) {
 559                 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_ECLK);
 560                 if (ret) {
 561                         pr_err("[SetupDefaultDpmTable] failed to get eclk dpm levels!");
 562                         return ret;
 563                 }
 564         } else {
 565                 single_dpm_table->count = 1;
 566                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.eclk / 100;
 567         }
 568         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 569
 570         /* vclk */
 571         single_dpm_table = &(dpm_table->vclk_table);
 572
 573         if (smu_feature_is_enabled(smu, FEATURE_DPM_UVD_BIT)) {
 574                 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_VCLK);
 575                 if (ret) {
 576                         pr_err("[SetupDefaultDpmTable] failed to get vclk dpm levels!");
 577                         return ret;
 578                 }
 579         } else {
 580                 single_dpm_table->count = 1;
 581                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
 582         }
 583         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 584
 585         /* dclk */
 586         single_dpm_table = &(dpm_table->dclk_table);
 587
 588         if (smu_feature_is_enabled(smu, FEATURE_DPM_UVD_BIT)) {
 589                 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_DCLK);
 590                 if (ret) {
 591                         pr_err("[SetupDefaultDpmTable] failed to get dclk dpm levels!");
 592                         return ret;
 593                 }
 594         } else {
 595                 single_dpm_table->count = 1;
 596                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
 597         }
 598         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 599
 600         /* dcefclk */
 601         single_dpm_table = &(dpm_table->dcef_table);
 602
 603         if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT)) {
 604                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 605                                                   PPCLK_DCEFCLK);
 606                 if (ret) {
 607                         pr_err("[SetupDefaultDpmTable] failed to get dcefclk dpm levels!");
 608                         return ret;
 609                 }
 610         } else {
 611                 single_dpm_table->count = 1;
 612                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 613         }
 614         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 615
 616         /* pixclk */
 617         single_dpm_table = &(dpm_table->pixel_table);
 618
 619         if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT)) {
 620                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 621                                                   PPCLK_PIXCLK);
 622                 if (ret) {
 623                         pr_err("[SetupDefaultDpmTable] failed to get pixclk dpm levels!");
 624                         return ret;
 625                 }
 626         } else {
 627                 single_dpm_table->count = 0;
 628         }
 629         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 630
 631         /* dispclk */
 632         single_dpm_table = &(dpm_table->display_table);
 633
 634         if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT)) {
 635                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 636                                                   PPCLK_DISPCLK);
 637                 if (ret) {
 638                         pr_err("[SetupDefaultDpmTable] failed to get dispclk dpm levels!");
 639                         return ret;
 640                 }
 641         } else {
 642                 single_dpm_table->count = 0;
 643         }
 644         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 645
 646         /* phyclk */
 647         single_dpm_table = &(dpm_table->phy_table);
 648
 649         if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT)) {
 650                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 651                                                   PPCLK_PHYCLK);
 652                 if (ret) {
 653                         pr_err("[SetupDefaultDpmTable] failed to get phyclk dpm levels!");
 654                         return ret;
 655                 }
 656         } else {
 657                 single_dpm_table->count = 0;
 658         }
 659         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 660
 661         /* fclk */
 662         single_dpm_table = &(dpm_table->fclk_table);
 663
 664         if (smu_feature_is_enabled(smu,FEATURE_DPM_FCLK_BIT)) {
 665                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 666                                                   PPCLK_FCLK);
 667                 if (ret) {
 668                         pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
 669                         return ret;
 670                 }
 671         } else {
 672                 single_dpm_table->count = 0;
 673         }
 674         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 675
 676         memcpy(smu_dpm->golden_dpm_context, dpm_table,
 677                sizeof(struct vega20_dpm_table));
 678
 679         return 0;
 680 }
 681
 682 static int vega20_populate_umd_state_clk(struct smu_context *smu)
 683 {
 684         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 685         struct vega20_dpm_table *dpm_table = NULL;
 686         struct vega20_single_dpm_table *gfx_table = NULL;
 687         struct vega20_single_dpm_table *mem_table = NULL;
 688
 689         dpm_table = smu_dpm->dpm_context;
 690         gfx_table = &(dpm_table->gfx_table);
 691         mem_table = &(dpm_table->mem_table);
 692
 693         smu->pstate_sclk = gfx_table->dpm_levels[0].value;
 694         smu->pstate_mclk = mem_table->dpm_levels[0].value;
 695
 696         if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
 697             mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
 698                 smu->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
 699                 smu->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
 700         }
 701
 702         smu->pstate_sclk = smu->pstate_sclk * 100;
 703         smu->pstate_mclk = smu->pstate_mclk * 100;
 704
 705         return 0;
 706 }
 707
 708 static int vega20_get_clk_table(struct smu_context *smu,
 709                         struct pp_clock_levels_with_latency *clocks,
 710                         struct vega20_single_dpm_table *dpm_table)
 711 {
 712         int i, count;
 713
 714         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 715         clocks->num_levels = count;
 716
 717         for (i = 0; i < count; i++) {
 718                 clocks->data[i].clocks_in_khz =
 719                         dpm_table->dpm_levels[i].value * 1000;
 720                 clocks->data[i].latency_in_us = 0;
 721         }
 722
 723         return 0;
 724 }
 725
 726 static int vega20_print_clk_levels(struct smu_context *smu,
 727                         enum pp_clock_type type, char *buf)
 728 {
 729         int i, now, size = 0;
 730         int ret = 0;
 731         uint32_t gen_speed, lane_width;
 732         struct amdgpu_device *adev = smu->adev;
 733         struct pp_clock_levels_with_latency clocks;
 734         struct vega20_single_dpm_table *single_dpm_table;
 735         struct smu_table_context *table_context = &smu->smu_table;
 736         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 737         struct vega20_dpm_table *dpm_table = NULL;
 738         struct vega20_od8_settings *od8_settings =
 739                 (struct vega20_od8_settings *)table_context->od8_settings;
 740         OverDriveTable_t *od_table =
 741                 (OverDriveTable_t *)(table_context->overdrive_table);
 742         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 743
 744         dpm_table = smu_dpm->dpm_context;
 745
 746         switch (type) {
 747         case PP_SCLK:
 748                 ret = smu_get_current_clk_freq(smu, PPCLK_GFXCLK, &now);
 749                 if (ret) {
 750                         pr_err("Attempt to get current gfx clk Failed!");
 751                         return ret;
 752                 }
 753
 754                 single_dpm_table = &(dpm_table->gfx_table);
 755                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
 756                 if (ret) {
 757                         pr_err("Attempt to get gfx clk levels Failed!");
 758                         return ret;
 759                 }
 760
 761                 for (i = 0; i < clocks.num_levels; i++)
 762                         size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 763                                         clocks.data[i].clocks_in_khz / 1000,
 764                                         (clocks.data[i].clocks_in_khz == now * 10)
 765                                         ? "*" : "");
 766                 break;
 767
 768         case PP_MCLK:
 769                 ret = smu_get_current_clk_freq(smu, PPCLK_UCLK, &now);
 770                 if (ret) {
 771                         pr_err("Attempt to get current mclk Failed!");
 772                         return ret;
 773                 }
 774
 775                 single_dpm_table = &(dpm_table->mem_table);
 776                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
 777                 if (ret) {
 778                         pr_err("Attempt to get memory clk levels Failed!");
 779                         return ret;
 780                 }
 781
 782                 for (i = 0; i < clocks.num_levels; i++)
 783                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 784                                 i, clocks.data[i].clocks_in_khz / 1000,
 785                                 (clocks.data[i].clocks_in_khz == now * 10)
 786                                 ? "*" : "");
 787                 break;
 788
 789         case PP_SOCCLK:
 790                 ret = smu_get_current_clk_freq(smu, PPCLK_SOCCLK, &now);
 791                 if (ret) {
 792                         pr_err("Attempt to get current socclk Failed!");
 793                         return ret;
 794                 }
 795
 796                 single_dpm_table = &(dpm_table->soc_table);
 797                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
 798                 if (ret) {
 799                         pr_err("Attempt to get socclk levels Failed!");
 800                         return ret;
 801                 }
 802
 803                 for (i = 0; i < clocks.num_levels; i++)
 804                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 805                                 i, clocks.data[i].clocks_in_khz / 1000,
 806                                 (clocks.data[i].clocks_in_khz == now * 10)
 807                                 ? "*" : "");
 808                 break;
 809
 810         case PP_FCLK:
 811                 ret = smu_get_current_clk_freq(smu, PPCLK_FCLK, &now);
 812                 if (ret) {
 813                         pr_err("Attempt to get current fclk Failed!");
 814                         return ret;
 815                 }
 816
 817                 single_dpm_table = &(dpm_table->fclk_table);
 818                 for (i = 0; i < single_dpm_table->count; i++)
 819                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 820                                 i, single_dpm_table->dpm_levels[i].value,
 821                                 (single_dpm_table->dpm_levels[i].value == now / 100)
 822                                 ? "*" : "");
 823                 break;
 824
 825         case PP_DCEFCLK:
 826                 ret = smu_get_current_clk_freq(smu, PPCLK_DCEFCLK, &now);
 827                 if (ret) {
 828                         pr_err("Attempt to get current dcefclk Failed!");
 829                         return ret;
 830                 }
 831
 832                 single_dpm_table = &(dpm_table->dcef_table);
 833                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
 834                 if (ret) {
 835                         pr_err("Attempt to get dcefclk levels Failed!");
 836                         return ret;
 837                 }
 838
 839                 for (i = 0; i < clocks.num_levels; i++)
 840                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 841                                 i, clocks.data[i].clocks_in_khz / 1000,
 842                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
 843                 break;
 844
 845         case PP_PCIE:
 846                 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
 847                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
 848                         >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
 849                 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
 850                               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
 851                         >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
 852                 for (i = 0; i < NUM_LINK_LEVELS; i++)
 853                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 854                                         (pptable->PcieGenSpeed[i] == 0) ? "2.5GT/s," :
 855                                         (pptable->PcieGenSpeed[i] == 1) ? "5.0GT/s," :
 856                                         (pptable->PcieGenSpeed[i] == 2) ? "8.0GT/s," :
 857                                         (pptable->PcieGenSpeed[i] == 3) ? "16.0GT/s," : "",
 858                                         (pptable->PcieLaneCount[i] == 1) ? "x1" :
 859                                         (pptable->PcieLaneCount[i] == 2) ? "x2" :
 860                                         (pptable->PcieLaneCount[i] == 3) ? "x4" :
 861                                         (pptable->PcieLaneCount[i] == 4) ? "x8" :
 862                                         (pptable->PcieLaneCount[i] == 5) ? "x12" :
 863                                         (pptable->PcieLaneCount[i] == 6) ? "x16" : "",
 864                                         pptable->LclkFreq[i],
 865                                         (gen_speed == pptable->PcieGenSpeed[i]) &&
 866                                         (lane_width == pptable->PcieLaneCount[i]) ?
 867                                         "*" : "");
 868                 break;
 869
 870         case OD_SCLK:
 871                 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
 872                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
 873                         size = sprintf(buf, "%s:\n", "OD_SCLK");
 874                         size += sprintf(buf + size, "0: %10uMhz\n",
 875                                         od_table->GfxclkFmin);
 876                         size += sprintf(buf + size, "1: %10uMhz\n",
 877                                         od_table->GfxclkFmax);
 878                 }
 879
 880                 break;
 881
 882         case OD_MCLK:
 883                 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
 884                         size = sprintf(buf, "%s:\n", "OD_MCLK");
 885                         size += sprintf(buf + size, "1: %10uMhz\n",
 886                                          od_table->UclkFmax);
 887                 }
 888
 889                 break;
 890
 891         case OD_VDDC_CURVE:
 892                 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
 893                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
 894                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
 895                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
 896                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
 897                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
 898                         size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
 899                         size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
 900                                         od_table->GfxclkFreq1,
 901                                         od_table->GfxclkVolt1 / VOLTAGE_SCALE);
 902                         size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
 903                                         od_table->GfxclkFreq2,
 904                                         od_table->GfxclkVolt2 / VOLTAGE_SCALE);
 905                         size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
 906                                         od_table->GfxclkFreq3,
 907                                         od_table->GfxclkVolt3 / VOLTAGE_SCALE);
 908                 }
 909
 910                 break;
 911
 912         case OD_RANGE:
 913                 size = sprintf(buf, "%s:\n", "OD_RANGE");
 914
 915                 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
 916                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
 917                         size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
 918                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
 919                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
 920                 }
 921
 922                 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
 923                         single_dpm_table = &(dpm_table->mem_table);
 924                         ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
 925                         if (ret) {
 926                                 pr_err("Attempt to get memory clk levels Failed!");
 927                                 return ret;
 928                         }
 929
 930                         size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
 931                                         clocks.data[0].clocks_in_khz / 1000,
 932                                         od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
 933                 }
 934
 935                 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
 936                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
 937                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
 938                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
 939                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
 940                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
 941                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
 942                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].min_value,
 943                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].max_value);
 944                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
 945                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
 946                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
 947                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
 948                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].min_value,
 949                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].max_value);
 950                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
 951                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
 952                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
 953                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
 954                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].min_value,
 955                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].max_value);
 956                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
 957                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
 958                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
 959                 }
 960
 961                 break;
 962
 963         default:
 964                 break;
 965         }
 966         return size;
 967 }
 968
 969 static int vega20_upload_dpm_level(struct smu_context *smu, bool max,
 970                                    uint32_t feature_mask)
 971 {
 972         struct vega20_dpm_table *dpm_table;
 973         struct vega20_single_dpm_table *single_dpm_table;
 974         uint32_t freq;
 975         int ret = 0;
 976
 977         dpm_table = smu->smu_dpm.dpm_context;
 978
 979         if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT) &&
 980             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 981                 single_dpm_table = &(dpm_table->gfx_table);
 982                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 983                         single_dpm_table->dpm_state.soft_min_level;
 984                 ret = smu_send_smc_msg_with_param(smu,
 985                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 986                         (PPCLK_GFXCLK << 16) | (freq & 0xffff));
 987                 if (ret) {
 988                         pr_err("Failed to set soft %s gfxclk !\n",
 989                                                 max ? "max" : "min");
 990                         return ret;
 991                 }
 992         }
 993
 994         if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT) &&
 995             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 996                 single_dpm_table = &(dpm_table->mem_table);
 997                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 998                         single_dpm_table->dpm_state.soft_min_level;
 999                 ret = smu_send_smc_msg_with_param(smu,
1000                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1001                         (PPCLK_UCLK << 16) | (freq & 0xffff));
1002                 if (ret) {
1003                         pr_err("Failed to set soft %s memclk !\n",
1004                                                 max ? "max" : "min");
1005                         return ret;
1006                 }
1007         }
1008
1009         if (smu_feature_is_enabled(smu, FEATURE_DPM_SOCCLK_BIT) &&
1010             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1011                 single_dpm_table = &(dpm_table->soc_table);
1012                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1013                         single_dpm_table->dpm_state.soft_min_level;
1014                 ret = smu_send_smc_msg_with_param(smu,
1015                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1016                         (PPCLK_SOCCLK << 16) | (freq & 0xffff));
1017                 if (ret) {
1018                         pr_err("Failed to set soft %s socclk !\n",
1019                                                 max ? "max" : "min");
1020                         return ret;
1021                 }
1022         }
1023
1024         if (smu_feature_is_enabled(smu, FEATURE_DPM_FCLK_BIT) &&
1025             (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1026                 single_dpm_table = &(dpm_table->fclk_table);
1027                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1028                         single_dpm_table->dpm_state.soft_min_level;
1029                 ret = smu_send_smc_msg_with_param(smu,
1030                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1031                         (PPCLK_FCLK << 16) | (freq & 0xffff));
1032                 if (ret) {
1033                         pr_err("Failed to set soft %s fclk !\n",
1034                                                 max ? "max" : "min");
1035                         return ret;
1036                 }
1037         }
1038
1039         if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT) &&
1040             (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
1041                 single_dpm_table = &(dpm_table->dcef_table);
1042                 freq = single_dpm_table->dpm_state.hard_min_level;
1043                 if (!max) {
1044                         ret = smu_send_smc_msg_with_param(smu,
1045                                 SMU_MSG_SetHardMinByFreq,
1046                                 (PPCLK_DCEFCLK << 16) | (freq & 0xffff));
1047                         if (ret) {
1048                                 pr_err("Failed to set hard min dcefclk !\n");
1049                                 return ret;
1050                         }
1051                 }
1052         }
1053
1054         return ret;
1055 }
1056
1057 static int vega20_force_clk_levels(struct smu_context *smu,
1058                         enum pp_clock_type type, uint32_t mask)
1059 {
1060         struct vega20_dpm_table *dpm_table;
1061         struct vega20_single_dpm_table *single_dpm_table;
1062         uint32_t soft_min_level, soft_max_level, hard_min_level;
1063         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1064         int ret = 0;
1065
1066         if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1067                 pr_info("force clock level is for dpm manual mode only.\n");
1068                 return -EINVAL;
1069         }
1070
1071         mutex_lock(&(smu->mutex));
1072
1073         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1074         soft_max_level = mask ? (fls(mask) - 1) : 0;
1075
1076         dpm_table = smu->smu_dpm.dpm_context;
1077
1078         switch (type) {
1079         case PP_SCLK:
1080                 single_dpm_table = &(dpm_table->gfx_table);
1081
1082                 if (soft_max_level >= single_dpm_table->count) {
1083                         pr_err("Clock level specified %d is over max allowed %d\n",
1084                                         soft_max_level, single_dpm_table->count - 1);
1085                         ret = -EINVAL;
1086                         break;
1087                 }
1088
1089                 single_dpm_table->dpm_state.soft_min_level =
1090                         single_dpm_table->dpm_levels[soft_min_level].value;
1091                 single_dpm_table->dpm_state.soft_max_level =
1092                         single_dpm_table->dpm_levels[soft_max_level].value;
1093
1094                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1095                 if (ret) {
1096                         pr_err("Failed to upload boot level to lowest!\n");
1097                         break;
1098                 }
1099
1100                 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1101                 if (ret)
1102                         pr_err("Failed to upload dpm max level to highest!\n");
1103
1104                 break;
1105
1106         case PP_MCLK:
1107                 single_dpm_table = &(dpm_table->mem_table);
1108
1109                 if (soft_max_level >= single_dpm_table->count) {
1110                         pr_err("Clock level specified %d is over max allowed %d\n",
1111                                         soft_max_level, single_dpm_table->count - 1);
1112                         ret = -EINVAL;
1113                         break;
1114                 }
1115
1116                 single_dpm_table->dpm_state.soft_min_level =
1117                         single_dpm_table->dpm_levels[soft_min_level].value;
1118                 single_dpm_table->dpm_state.soft_max_level =
1119                         single_dpm_table->dpm_levels[soft_max_level].value;
1120
1121                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
1122                 if (ret) {
1123                         pr_err("Failed to upload boot level to lowest!\n");
1124                         break;
1125                 }
1126
1127                 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
1128                 if (ret)
1129                         pr_err("Failed to upload dpm max level to highest!\n");
1130
1131                 break;
1132
1133         case PP_SOCCLK:
1134                 single_dpm_table = &(dpm_table->soc_table);
1135
1136                 if (soft_max_level >= single_dpm_table->count) {
1137                         pr_err("Clock level specified %d is over max allowed %d\n",
1138                                         soft_max_level, single_dpm_table->count - 1);
1139                         ret = -EINVAL;
1140                         break;
1141                 }
1142
1143                 single_dpm_table->dpm_state.soft_min_level =
1144                         single_dpm_table->dpm_levels[soft_min_level].value;
1145                 single_dpm_table->dpm_state.soft_max_level =
1146                         single_dpm_table->dpm_levels[soft_max_level].value;
1147
1148                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
1149                 if (ret) {
1150                         pr_err("Failed to upload boot level to lowest!\n");
1151                         break;
1152                 }
1153
1154                 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
1155                 if (ret)
1156                         pr_err("Failed to upload dpm max level to highest!\n");
1157
1158                 break;
1159
1160         case PP_FCLK:
1161                 single_dpm_table = &(dpm_table->fclk_table);
1162
1163                 if (soft_max_level >= single_dpm_table->count) {
1164                         pr_err("Clock level specified %d is over max allowed %d\n",
1165                                         soft_max_level, single_dpm_table->count - 1);
1166                         ret = -EINVAL;
1167                         break;
1168                 }
1169
1170                 single_dpm_table->dpm_state.soft_min_level =
1171                         single_dpm_table->dpm_levels[soft_min_level].value;
1172                 single_dpm_table->dpm_state.soft_max_level =
1173                         single_dpm_table->dpm_levels[soft_max_level].value;
1174
1175                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
1176                 if (ret) {
1177                         pr_err("Failed to upload boot level to lowest!\n");
1178                         break;
1179                 }
1180
1181                 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
1182                 if (ret)
1183                         pr_err("Failed to upload dpm max level to highest!\n");
1184
1185                 break;
1186
1187         case PP_DCEFCLK:
1188                 hard_min_level = soft_min_level;
1189                 single_dpm_table = &(dpm_table->dcef_table);
1190
1191                 if (hard_min_level >= single_dpm_table->count) {
1192                         pr_err("Clock level specified %d is over max allowed %d\n",
1193                                         hard_min_level, single_dpm_table->count - 1);
1194                         ret = -EINVAL;
1195                         break;
1196                 }
1197
1198                 single_dpm_table->dpm_state.hard_min_level =
1199                         single_dpm_table->dpm_levels[hard_min_level].value;
1200
1201                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_DCEFCLK_MASK);
1202                 if (ret)
1203                         pr_err("Failed to upload boot level to lowest!\n");
1204
1205                 break;
1206
1207         case PP_PCIE:
1208                 if (soft_min_level >= NUM_LINK_LEVELS ||
1209                     soft_max_level >= NUM_LINK_LEVELS)
1210                         return -EINVAL;
1211
1212                 ret = smu_send_smc_msg_with_param(smu,
1213                                 SMU_MSG_SetMinLinkDpmByIndex, soft_min_level);
1214                 if (ret)
1215                         pr_err("Failed to set min link dpm level!\n");
1216
1217                 break;
1218
1219         default:
1220                 break;
1221         }
1222
1223         mutex_unlock(&(smu->mutex));
1224         return ret;
1225 }
1226
1227 static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
1228                                                  enum amd_pp_clock_type type,
1229                                                  struct pp_clock_levels_with_latency *clocks)
1230 {
1231         int ret;
1232         struct vega20_single_dpm_table *single_dpm_table;
1233         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1234         struct vega20_dpm_table *dpm_table = NULL;
1235
1236         dpm_table = smu_dpm->dpm_context;
1237
1238         mutex_lock(&smu->mutex);
1239
1240         switch (type) {
1241         case amd_pp_sys_clock:
1242                 single_dpm_table = &(dpm_table->gfx_table);
1243                 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1244                 break;
1245         case amd_pp_mem_clock:
1246                 single_dpm_table = &(dpm_table->mem_table);
1247                 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1248                 break;
1249         case amd_pp_dcef_clock:
1250                 single_dpm_table = &(dpm_table->dcef_table);
1251                 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1252                 break;
1253         case amd_pp_soc_clock:
1254                 single_dpm_table = &(dpm_table->soc_table);
1255                 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1256                 break;
1257         default:
1258                 ret = -EINVAL;
1259         }
1260
1261         mutex_unlock(&smu->mutex);
1262         return ret;
1263 }
1264
1265 static int vega20_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
1266                                                      uint32_t *voltage,
1267                                                      uint32_t freq)
1268 {
1269         int ret;
1270
1271         ret = smu_send_smc_msg_with_param(smu,
1272                         SMU_MSG_GetAVFSVoltageByDpm,
1273                         ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1274         if (ret) {
1275                 pr_err("[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
1276                 return ret;
1277         }
1278
1279         smu_read_smc_arg(smu, voltage);
1280         *voltage = *voltage / VOLTAGE_SCALE;
1281
1282         return 0;
1283 }
1284
1285 static int vega20_set_default_od8_setttings(struct smu_context *smu)
1286 {
1287         struct smu_table_context *table_context = &smu->smu_table;
1288         OverDriveTable_t *od_table = (OverDriveTable_t *)(table_context->overdrive_table);
1289         struct vega20_od8_settings *od8_settings = NULL;
1290         PPTable_t *smc_pptable = table_context->driver_pptable;
1291         int i, ret;
1292
1293         if (table_context->od8_settings)
1294                 return -EINVAL;
1295
1296         table_context->od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL);
1297
1298         if (!table_context->od8_settings)
1299                 return -ENOMEM;
1300
1301         memset(table_context->od8_settings, 0, sizeof(struct vega20_od8_settings));
1302         od8_settings = (struct vega20_od8_settings *)table_context->od8_settings;
1303
1304         if (smu_feature_is_enabled(smu, FEATURE_DPM_SOCCLK_BIT)) {
1305                 if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
1306                     table_context->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
1307                     table_context->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
1308                     (table_context->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
1309                      table_context->od_settings_min[OD8_SETTING_GFXCLK_FMIN])) {
1310                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1311                                 OD8_GFXCLK_LIMITS;
1312                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1313                                 OD8_GFXCLK_LIMITS;
1314                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1315                                 od_table->GfxclkFmin;
1316                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1317                                 od_table->GfxclkFmax;
1318                 }
1319
1320                 if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
1321                     (table_context->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
1322                      smc_pptable->MinVoltageGfx / VOLTAGE_SCALE) &&
1323                     (table_context->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
1324                      smc_pptable->MaxVoltageGfx / VOLTAGE_SCALE) &&
1325                     (table_context->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] <=
1326                      table_context->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3])) {
1327                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1328                                 OD8_GFXCLK_CURVE;
1329                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1330                                 OD8_GFXCLK_CURVE;
1331                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1332                                 OD8_GFXCLK_CURVE;
1333                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1334                                 OD8_GFXCLK_CURVE;
1335                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1336                                 OD8_GFXCLK_CURVE;
1337                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1338                                 OD8_GFXCLK_CURVE;
1339
1340                         od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1341                         od_table->GfxclkFreq2 = (od_table->GfxclkFmin + od_table->GfxclkFmax) / 2;
1342                         od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1343                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1344                                 od_table->GfxclkFreq1;
1345                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1346                                 od_table->GfxclkFreq2;
1347                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1348                                 od_table->GfxclkFreq3;
1349
1350                         ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1351                                 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value,
1352                                 od_table->GfxclkFreq1);
1353                         if (ret)
1354                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0;
1355                         od_table->GfxclkVolt1 =
1356                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1357                                 * VOLTAGE_SCALE;
1358                         ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1359                                 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value,
1360                                 od_table->GfxclkFreq2);
1361                         if (ret)
1362                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0;
1363                         od_table->GfxclkVolt2 =
1364                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1365                                 * VOLTAGE_SCALE;
1366                         ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1367                                 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value,
1368                                 od_table->GfxclkFreq3);
1369                         if (ret)
1370                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0;
1371                         od_table->GfxclkVolt3 =
1372                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1373                                 * VOLTAGE_SCALE;
1374                 }
1375         }
1376
1377         if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
1378                 if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
1379                     table_context->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
1380                     table_context->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
1381                     (table_context->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
1382                      table_context->od_settings_min[OD8_SETTING_UCLK_FMAX])) {
1383                         od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id =
1384                                 OD8_UCLK_MAX;
1385                         od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1386                                 od_table->UclkFmax;
1387                 }
1388         }
1389
1390         if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
1391             table_context->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1392             table_context->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
1393             table_context->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1394             table_context->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100) {
1395                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id =
1396                         OD8_POWER_LIMIT;
1397                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1398                         od_table->OverDrivePct;
1399         }
1400
1401         if (smu_feature_is_enabled(smu, FEATURE_FAN_CONTROL_BIT)) {
1402                 if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
1403                     table_context->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1404                     table_context->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1405                     (table_context->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
1406                      table_context->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT])) {
1407                         od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1408                                 OD8_ACOUSTIC_LIMIT_SCLK;
1409                         od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1410                                 od_table->FanMaximumRpm;
1411                 }
1412
1413                 if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
1414                     table_context->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1415                     table_context->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1416                     (table_context->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
1417                      table_context->od_settings_min[OD8_SETTING_FAN_MIN_SPEED])) {
1418                         od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1419                                 OD8_FAN_SPEED_MIN;
1420                         od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1421                                 od_table->FanMinimumPwm * smc_pptable->FanMaximumRpm / 100;
1422                 }
1423         }
1424
1425         if (smu_feature_is_enabled(smu, FEATURE_THERMAL_BIT)) {
1426                 if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
1427                     table_context->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1428                     table_context->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1429                     (table_context->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
1430                      table_context->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP])) {
1431                         od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1432                                 OD8_TEMPERATURE_FAN;
1433                         od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1434                                 od_table->FanTargetTemperature;
1435                 }
1436
1437                 if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
1438                     table_context->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1439                     table_context->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1440                     (table_context->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
1441                      table_context->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX])) {
1442                         od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1443                                 OD8_TEMPERATURE_SYSTEM;
1444                         od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1445                                 od_table->MaxOpTemp;
1446                 }
1447         }
1448
1449         for (i = 0; i < OD8_SETTING_COUNT; i++) {
1450                 if (od8_settings->od8_settings_array[i].feature_id) {
1451                         od8_settings->od8_settings_array[i].min_value =
1452                                 table_context->od_settings_min[i];
1453                         od8_settings->od8_settings_array[i].max_value =
1454                                 table_context->od_settings_max[i];
1455                         od8_settings->od8_settings_array[i].current_value =
1456                                 od8_settings->od8_settings_array[i].default_value;
1457                 } else {
1458                         od8_settings->od8_settings_array[i].min_value = 0;
1459                         od8_settings->od8_settings_array[i].max_value = 0;
1460                         od8_settings->od8_settings_array[i].current_value = 0;
1461                 }
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int vega20_get_od_percentage(struct smu_context *smu,
1468                                     enum pp_clock_type type)
1469 {
1470         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1471         struct vega20_dpm_table *dpm_table = NULL;
1472         struct vega20_dpm_table *golden_table = NULL;
1473         struct vega20_single_dpm_table *single_dpm_table;
1474         struct vega20_single_dpm_table *golden_dpm_table;
1475         int value, golden_value;
1476
1477         dpm_table = smu_dpm->dpm_context;
1478         golden_table = smu_dpm->golden_dpm_context;
1479
1480         switch (type) {
1481         case OD_SCLK:
1482                 single_dpm_table = &(dpm_table->gfx_table);
1483                 golden_dpm_table = &(golden_table->gfx_table);
1484                 break;
1485         case OD_MCLK:
1486                 single_dpm_table = &(dpm_table->mem_table);
1487                 golden_dpm_table = &(golden_table->mem_table);
1488                 break;
1489         default:
1490                 return -EINVAL;
1491                 break;
1492         }
1493
1494         value = single_dpm_table->dpm_levels[single_dpm_table->count - 1].value;
1495         golden_value = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
1496
1497         value -= golden_value;
1498         value = DIV_ROUND_UP(value * 100, golden_value);
1499
1500         return value;
1501 }
1502
1503 static int
1504 vega20_get_profiling_clk_mask(struct smu_context *smu,
1505                               enum amd_dpm_forced_level level,
1506                               uint32_t *sclk_mask,
1507                               uint32_t *mclk_mask,
1508                               uint32_t *soc_mask)
1509 {
1510         struct vega20_dpm_table *dpm_table = (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
1511         struct vega20_single_dpm_table *gfx_dpm_table;
1512         struct vega20_single_dpm_table *mem_dpm_table;
1513         struct vega20_single_dpm_table *soc_dpm_table;
1514
1515         if (!smu->smu_dpm.dpm_context)
1516                 return -EINVAL;
1517
1518         gfx_dpm_table = &dpm_table->gfx_table;
1519         mem_dpm_table = &dpm_table->mem_table;
1520         soc_dpm_table = &dpm_table->soc_table;
1521
1522         *sclk_mask = 0;
1523         *mclk_mask = 0;
1524         *soc_mask  = 0;
1525
1526         if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1527             mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
1528             soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
1529                 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
1530                 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
1531                 *soc_mask  = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
1532         }
1533
1534         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1535                 *sclk_mask = 0;
1536         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1537                 *mclk_mask = 0;
1538         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1539                 *sclk_mask = gfx_dpm_table->count - 1;
1540                 *mclk_mask = mem_dpm_table->count - 1;
1541                 *soc_mask  = soc_dpm_table->count - 1;
1542         }
1543
1544         return 0;
1545 }
1546
1547 static int
1548 vega20_set_uclk_to_highest_dpm_level(struct smu_context *smu,
1549                                      struct vega20_single_dpm_table *dpm_table)
1550 {
1551         int ret = 0;
1552         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1553         if (!smu_dpm_ctx->dpm_context)
1554                 return -EINVAL;
1555
1556         if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
1557                 if (dpm_table->count <= 0) {
1558                         pr_err("[%s] Dpm table has no entry!", __func__);
1559                                 return -EINVAL;
1560                 }
1561
1562                 if (dpm_table->count > NUM_UCLK_DPM_LEVELS) {
1563                         pr_err("[%s] Dpm table has too many entries!", __func__);
1564                                 return -EINVAL;
1565                 }
1566
1567                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1568                 ret = smu_send_smc_msg_with_param(smu,
1569                                 SMU_MSG_SetHardMinByFreq,
1570                                 (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level);
1571                 if (ret) {
1572                         pr_err("[%s] Set hard min uclk failed!", __func__);
1573                                 return ret;
1574                 }
1575         }
1576
1577         return ret;
1578 }
1579
1580 static int vega20_pre_display_config_changed(struct smu_context *smu)
1581 {
1582         int ret = 0;
1583         struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
1584
1585         if (!smu->smu_dpm.dpm_context)
1586                 return -EINVAL;
1587
1588         smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
1589         ret = vega20_set_uclk_to_highest_dpm_level(smu,
1590                                                    &dpm_table->mem_table);
1591         if (ret)
1592                 pr_err("Failed to set uclk to highest dpm level");
1593         return ret;
1594 }
1595
1596 static int vega20_display_config_changed(struct smu_context *smu)
1597 {
1598         int ret = 0;
1599
1600         if (!smu->funcs)
1601                 return -EINVAL;
1602
1603         if (!smu->smu_dpm.dpm_context ||
1604             !smu->smu_table.tables ||
1605             !smu->smu_table.tables[TABLE_WATERMARKS].cpu_addr)
1606                 return -EINVAL;
1607
1608         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1609             !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1610                 ret = smu->funcs->write_watermarks_table(smu);
1611                 if (ret) {
1612                         pr_err("Failed to update WMTABLE!");
1613                         return ret;
1614                 }
1615                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1616         }
1617
1618         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1619             smu_feature_is_supported(smu, FEATURE_DPM_DCEFCLK_BIT) &&
1620             smu_feature_is_supported(smu, FEATURE_DPM_SOCCLK_BIT)) {
1621                 smu_send_smc_msg_with_param(smu,
1622                                             SMU_MSG_NumOfDisplays,
1623                                             smu->display_config->num_display);
1624         }
1625
1626         return ret;
1627 }
1628
1629 static int vega20_apply_clocks_adjust_rules(struct smu_context *smu)
1630 {
1631         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1632         struct vega20_dpm_table *dpm_ctx = (struct vega20_dpm_table *)(smu_dpm_ctx->dpm_context);
1633         struct vega20_single_dpm_table *dpm_table;
1634         bool vblank_too_short = false;
1635         bool disable_mclk_switching;
1636         uint32_t i, latency;
1637
1638         disable_mclk_switching = ((1 < smu->display_config->num_display) &&
1639                                   !smu->display_config->multi_monitor_in_sync) || vblank_too_short;
1640         latency = smu->display_config->dce_tolerable_mclk_in_active_latency;
1641
1642         /* gfxclk */
1643         dpm_table = &(dpm_ctx->gfx_table);
1644         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
1645         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1646         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
1647         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1648
1649                 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
1650                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
1651                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
1652                 }
1653
1654                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1655                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
1656                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
1657                 }
1658
1659                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1660                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1661                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1662                 }
1663
1664         /* memclk */
1665         dpm_table = &(dpm_ctx->mem_table);
1666         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
1667         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1668         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
1669         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1670
1671                 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
1672                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
1673                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
1674                 }
1675
1676                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1677                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
1678                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
1679                 }
1680
1681                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1682                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1683                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1684                 }
1685
1686         /* honour DAL's UCLK Hardmin */
1687         if (dpm_table->dpm_state.hard_min_level < (smu->display_config->min_mem_set_clock / 100))
1688                 dpm_table->dpm_state.hard_min_level = smu->display_config->min_mem_set_clock / 100;
1689
1690         /* Hardmin is dependent on displayconfig */
1691         if (disable_mclk_switching) {
1692                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1693                 for (i = 0; i < smu_dpm_ctx->mclk_latency_table->count - 1; i++) {
1694                         if (smu_dpm_ctx->mclk_latency_table->entries[i].latency <= latency) {
1695                                 if (dpm_table->dpm_levels[i].value >= (smu->display_config->min_mem_set_clock / 100)) {
1696                                         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
1697                                         break;
1698                                 }
1699                         }
1700                 }
1701         }
1702
1703         if (smu->display_config->nb_pstate_switch_disable)
1704                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1705
1706         /* vclk */
1707         dpm_table = &(dpm_ctx->vclk_table);
1708         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
1709         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1710         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
1711         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1712
1713                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
1714                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
1715                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
1716                 }
1717
1718                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1719                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1720                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1721                 }
1722
1723         /* dclk */
1724         dpm_table = &(dpm_ctx->dclk_table);
1725         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
1726         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1727         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
1728         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1729
1730                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
1731                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
1732                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
1733                 }
1734
1735                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1736                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1737                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1738                 }
1739
1740         /* socclk */
1741         dpm_table = &(dpm_ctx->soc_table);
1742         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
1743         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1744         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
1745         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1746
1747                 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
1748                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
1749                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
1750                 }
1751
1752                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1753                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1754                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1755                 }
1756
1757         /* eclk */
1758         dpm_table = &(dpm_ctx->eclk_table);
1759         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
1760         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1761         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
1762         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1763
1764                 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
1765                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
1766                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
1767                 }
1768
1769                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1770                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1771                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1772                 }
1773         return 0;
1774 }
1775
1776 static int
1777 vega20_notify_smc_dispaly_config(struct smu_context *smu)
1778 {
1779         struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
1780         struct vega20_single_dpm_table *memtable = &dpm_table->mem_table;
1781         struct smu_clocks min_clocks = {0};
1782         struct pp_display_clock_request clock_req;
1783         int ret = 0;
1784
1785         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1786         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1787         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1788
1789         if (smu_feature_is_supported(smu, FEATURE_DPM_DCEFCLK_BIT)) {
1790                 clock_req.clock_type = amd_pp_dcef_clock;
1791                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1792                 if (!smu->funcs->display_clock_voltage_request(smu, &clock_req)) {
1793                         if (smu_feature_is_supported(smu, FEATURE_DS_DCEFCLK_BIT)) {
1794                                 ret = smu_send_smc_msg_with_param(smu,
1795                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1796                                                                   min_clocks.dcef_clock_in_sr/100);
1797                                 if (ret) {
1798                                         pr_err("Attempt to set divider for DCEFCLK Failed!");
1799                                         return ret;
1800                                 }
1801                         }
1802                 } else {
1803                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1804                 }
1805         }
1806
1807         if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
1808                 memtable->dpm_state.hard_min_level = min_clocks.memory_clock/100;
1809                 ret = smu_send_smc_msg_with_param(smu,
1810                                                   SMU_MSG_SetHardMinByFreq,
1811                                                   (PPCLK_UCLK << 16) | memtable->dpm_state.hard_min_level);
1812                 if (ret) {
1813                         pr_err("[%s] Set hard min uclk failed!", __func__);
1814                         return ret;
1815                 }
1816         }
1817
1818         return 0;
1819 }
1820
1821 static uint32_t vega20_find_lowest_dpm_level(struct vega20_single_dpm_table *table)
1822 {
1823         uint32_t i;
1824
1825         for (i = 0; i < table->count; i++) {
1826                 if (table->dpm_levels[i].enabled)
1827                         break;
1828         }
1829         if (i >= table->count) {
1830                 i = 0;
1831                 table->dpm_levels[i].enabled = true;
1832         }
1833
1834         return i;
1835 }
1836
1837 static uint32_t vega20_find_highest_dpm_level(struct vega20_single_dpm_table *table)
1838 {
1839         int i = 0;
1840
1841         if (!table) {
1842                 pr_err("[%s] DPM Table does not exist!", __func__);
1843                 return 0;
1844         }
1845         if (table->count <= 0) {
1846                 pr_err("[%s] DPM Table has no entry!", __func__);
1847                 return 0;
1848         }
1849         if (table->count > MAX_REGULAR_DPM_NUMBER) {
1850                 pr_err("[%s] DPM Table has too many entries!", __func__);
1851                 return MAX_REGULAR_DPM_NUMBER - 1;
1852         }
1853
1854         for (i = table->count - 1; i >= 0; i--) {
1855                 if (table->dpm_levels[i].enabled)
1856                         break;
1857         }
1858         if (i < 0) {
1859                 i = 0;
1860                 table->dpm_levels[i].enabled = true;
1861         }
1862
1863         return i;
1864 }
1865
1866 static int vega20_force_dpm_limit_value(struct smu_context *smu, bool highest)
1867 {
1868         uint32_t soft_level;
1869         int ret = 0;
1870         struct vega20_dpm_table *dpm_table =
1871                 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
1872
1873         if (highest)
1874                 soft_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
1875         else
1876                 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
1877
1878         dpm_table->gfx_table.dpm_state.soft_min_level =
1879                 dpm_table->gfx_table.dpm_state.soft_max_level =
1880                 dpm_table->gfx_table.dpm_levels[soft_level].value;
1881
1882         if (highest)
1883                 soft_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
1884         else
1885                 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
1886
1887         dpm_table->mem_table.dpm_state.soft_min_level =
1888                 dpm_table->mem_table.dpm_state.soft_max_level =
1889                 dpm_table->mem_table.dpm_levels[soft_level].value;
1890
1891         if (highest)
1892                 soft_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
1893         else
1894                 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
1895
1896         dpm_table->soc_table.dpm_state.soft_min_level =
1897                 dpm_table->soc_table.dpm_state.soft_max_level =
1898                 dpm_table->soc_table.dpm_levels[soft_level].value;
1899
1900         ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
1901         if (ret) {
1902                 pr_err("Failed to upload boot level to %s!\n",
1903                                 highest ? "highest" : "lowest");
1904                 return ret;
1905         }
1906
1907         ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
1908         if (ret) {
1909                 pr_err("Failed to upload dpm max level to %s!\n!",
1910                                 highest ? "highest" : "lowest");
1911                 return ret;
1912         }
1913
1914         return ret;
1915 }
1916
1917 static int vega20_unforce_dpm_levels(struct smu_context *smu)
1918 {
1919         uint32_t soft_min_level, soft_max_level;
1920         int ret = 0;
1921         struct vega20_dpm_table *dpm_table =
1922                 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
1923
1924         soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
1925         soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
1926         dpm_table->gfx_table.dpm_state.soft_min_level =
1927                 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
1928         dpm_table->gfx_table.dpm_state.soft_max_level =
1929                 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
1930
1931         soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
1932         soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
1933         dpm_table->mem_table.dpm_state.soft_min_level =
1934                 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
1935         dpm_table->mem_table.dpm_state.soft_max_level =
1936                 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
1937
1938         soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
1939         soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
1940         dpm_table->soc_table.dpm_state.soft_min_level =
1941                 dpm_table->soc_table.dpm_levels[soft_min_level].value;
1942         dpm_table->soc_table.dpm_state.soft_max_level =
1943                 dpm_table->soc_table.dpm_levels[soft_max_level].value;
1944
1945         ret = smu_upload_dpm_level(smu, false, 0xFFFFFFFF);
1946         if (ret) {
1947                 pr_err("Failed to upload DPM Bootup Levels!");
1948                 return ret;
1949         }
1950
1951         ret = smu_upload_dpm_level(smu, true, 0xFFFFFFFF);
1952         if (ret) {
1953                 pr_err("Failed to upload DPM Max Levels!");
1954                 return ret;
1955         }
1956
1957         return ret;
1958 }
1959
1960 static enum amd_dpm_forced_level vega20_get_performance_level(struct smu_context *smu)
1961 {
1962         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1963         if (!smu_dpm_ctx->dpm_context)
1964                 return -EINVAL;
1965
1966         if (smu_dpm_ctx->dpm_level != smu_dpm_ctx->saved_dpm_level) {
1967                 mutex_lock(&(smu->mutex));
1968                 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1969                 mutex_unlock(&(smu->mutex));
1970         }
1971         return smu_dpm_ctx->dpm_level;
1972 }
1973
1974 static int
1975 vega20_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1976 {
1977         int ret = 0;
1978         int i;
1979         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1980
1981         if (!smu_dpm_ctx->dpm_context)
1982                 return -EINVAL;
1983
1984         for (i = 0; i < smu->adev->num_ip_blocks; i++) {
1985                 if (smu->adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)
1986                         break;
1987         }
1988
1989         mutex_lock(&smu->mutex);
1990
1991         smu->adev->ip_blocks[i].version->funcs->enable_umd_pstate(smu, &level);
1992         ret = smu_handle_task(smu, level,
1993                               AMD_PP_TASK_READJUST_POWER_STATE);
1994
1995         mutex_unlock(&smu->mutex);
1996
1997         return ret;
1998 }
1999
2000 static int vega20_update_specified_od8_value(struct smu_context *smu,
2001                                              uint32_t index,
2002                                              uint32_t value)
2003 {
2004         struct smu_table_context *table_context = &smu->smu_table;
2005         OverDriveTable_t *od_table =
2006                 (OverDriveTable_t *)(table_context->overdrive_table);
2007         struct vega20_od8_settings *od8_settings =
2008                 (struct vega20_od8_settings *)table_context->od8_settings;
2009
2010         switch (index) {
2011         case OD8_SETTING_GFXCLK_FMIN:
2012                 od_table->GfxclkFmin = (uint16_t)value;
2013                 break;
2014
2015         case OD8_SETTING_GFXCLK_FMAX:
2016                 if (value < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].min_value ||
2017                     value > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value)
2018                         return -EINVAL;
2019                 od_table->GfxclkFmax = (uint16_t)value;
2020                 break;
2021
2022         case OD8_SETTING_GFXCLK_FREQ1:
2023                 od_table->GfxclkFreq1 = (uint16_t)value;
2024                 break;
2025
2026         case OD8_SETTING_GFXCLK_VOLTAGE1:
2027                 od_table->GfxclkVolt1 = (uint16_t)value;
2028                 break;
2029
2030         case OD8_SETTING_GFXCLK_FREQ2:
2031                 od_table->GfxclkFreq2 = (uint16_t)value;
2032                 break;
2033
2034         case OD8_SETTING_GFXCLK_VOLTAGE2:
2035                 od_table->GfxclkVolt2 = (uint16_t)value;
2036                 break;
2037
2038         case OD8_SETTING_GFXCLK_FREQ3:
2039                 od_table->GfxclkFreq3 = (uint16_t)value;
2040                 break;
2041
2042         case OD8_SETTING_GFXCLK_VOLTAGE3:
2043                 od_table->GfxclkVolt3 = (uint16_t)value;
2044                 break;
2045
2046         case OD8_SETTING_UCLK_FMAX:
2047                 if (value < od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].min_value ||
2048                     value > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value)
2049                         return -EINVAL;
2050                 od_table->UclkFmax = (uint16_t)value;
2051                 break;
2052
2053         case OD8_SETTING_POWER_PERCENTAGE:
2054                 od_table->OverDrivePct = (int16_t)value;
2055                 break;
2056
2057         case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
2058                 od_table->FanMaximumRpm = (uint16_t)value;
2059                 break;
2060
2061         case OD8_SETTING_FAN_MIN_SPEED:
2062                 od_table->FanMinimumPwm = (uint16_t)value;
2063                 break;
2064
2065         case OD8_SETTING_FAN_TARGET_TEMP:
2066                 od_table->FanTargetTemperature = (uint16_t)value;
2067                 break;
2068
2069         case OD8_SETTING_OPERATING_TEMP_MAX:
2070                 od_table->MaxOpTemp = (uint16_t)value;
2071                 break;
2072         }
2073
2074         return 0;
2075 }
2076
2077 static int vega20_set_od_percentage(struct smu_context *smu,
2078                                     enum pp_clock_type type,
2079                                     uint32_t value)
2080 {
2081         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2082         struct vega20_dpm_table *dpm_table = NULL;
2083         struct vega20_dpm_table *golden_table = NULL;
2084         struct vega20_single_dpm_table *single_dpm_table;
2085         struct vega20_single_dpm_table *golden_dpm_table;
2086         uint32_t od_clk, index;
2087         int ret = 0;
2088         int feature_enabled;
2089         PPCLK_e clk_id;
2090
2091         mutex_lock(&(smu->mutex));
2092
2093         dpm_table = smu_dpm->dpm_context;
2094         golden_table = smu_dpm->golden_dpm_context;
2095
2096         switch (type) {
2097         case OD_SCLK:
2098                 single_dpm_table = &(dpm_table->gfx_table);
2099                 golden_dpm_table = &(golden_table->gfx_table);
2100                 feature_enabled = smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT);
2101                 clk_id = PPCLK_GFXCLK;
2102                 index = OD8_SETTING_GFXCLK_FMAX;
2103                 break;
2104         case OD_MCLK:
2105                 single_dpm_table = &(dpm_table->mem_table);
2106                 golden_dpm_table = &(golden_table->mem_table);
2107                 feature_enabled = smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT);
2108                 clk_id = PPCLK_UCLK;
2109                 index = OD8_SETTING_UCLK_FMAX;
2110                 break;
2111         default:
2112                 ret = -EINVAL;
2113                 break;
2114         }
2115
2116         if (ret)
2117                 goto set_od_failed;
2118
2119         od_clk = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value * value;
2120         od_clk /= 100;
2121         od_clk += golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
2122
2123         ret = smu_update_od8_settings(smu, index, od_clk);
2124         if (ret) {
2125                 pr_err("[Setoverdrive] failed to set od clk!\n");
2126                 goto set_od_failed;
2127         }
2128
2129         if (feature_enabled) {
2130                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2131                                                   clk_id);
2132                 if (ret) {
2133                         pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2134                         goto set_od_failed;
2135                 }
2136         } else {
2137                 single_dpm_table->count = 1;
2138                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2139         }
2140
2141         ret = smu_handle_task(smu, smu_dpm->dpm_level,
2142                               AMD_PP_TASK_READJUST_POWER_STATE);
2143
2144 set_od_failed:
2145         mutex_unlock(&(smu->mutex));
2146
2147         return ret;
2148 }
2149
2150 static int vega20_odn_edit_dpm_table(struct smu_context *smu,
2151                                      enum PP_OD_DPM_TABLE_COMMAND type,
2152                                      long *input, uint32_t size)
2153 {
2154         struct smu_table_context *table_context = &smu->smu_table;
2155         OverDriveTable_t *od_table =
2156                 (OverDriveTable_t *)(table_context->overdrive_table);
2157         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2158         struct vega20_dpm_table *dpm_table = NULL;
2159         struct vega20_single_dpm_table *single_dpm_table;
2160         struct vega20_od8_settings *od8_settings =
2161                 (struct vega20_od8_settings *)table_context->od8_settings;
2162         struct pp_clock_levels_with_latency clocks;
2163         int32_t input_index, input_clk, input_vol, i;
2164         int od8_id;
2165         int ret = 0;
2166
2167         dpm_table = smu_dpm->dpm_context;
2168
2169         if (!input) {
2170                 pr_warn("NULL user input for clock and voltage\n");
2171                 return -EINVAL;
2172         }
2173
2174         switch (type) {
2175         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2176                 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2177                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2178                         pr_info("Sclk min/max frequency overdrive not supported\n");
2179                         return -EOPNOTSUPP;
2180                 }
2181
2182                 for (i = 0; i < size; i += 2) {
2183                         if (i + 2 > size) {
2184                                 pr_info("invalid number of input parameters %d\n", size);
2185                                 return -EINVAL;
2186                         }
2187
2188                         input_index = input[i];
2189                         input_clk = input[i + 1];
2190
2191                         if (input_index != 0 && input_index != 1) {
2192                                 pr_info("Invalid index %d\n", input_index);
2193                                 pr_info("Support min/max sclk frequency settingonly which index by 0/1\n");
2194                                 return -EINVAL;
2195                         }
2196
2197                         if (input_clk < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value ||
2198                             input_clk > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value) {
2199                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2200                                         input_clk,
2201                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
2202                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
2203                                 return -EINVAL;
2204                         }
2205
2206                         if (input_index == 0 && od_table->GfxclkFmin != input_clk) {
2207                                 od_table->GfxclkFmin = input_clk;
2208                                 table_context->od_gfxclk_update = true;
2209                         } else if (input_index == 1 && od_table->GfxclkFmax != input_clk) {
2210                                 od_table->GfxclkFmax = input_clk;
2211                                 table_context->od_gfxclk_update = true;
2212                         }
2213                 }
2214
2215                 break;
2216
2217         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2218                 if (!od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
2219                         pr_info("Mclk max frequency overdrive not supported\n");
2220                         return -EOPNOTSUPP;
2221                 }
2222
2223                 single_dpm_table = &(dpm_table->mem_table);
2224                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
2225                 if (ret) {
2226                         pr_err("Attempt to get memory clk levels Failed!");
2227                         return ret;
2228                 }
2229
2230                 for (i = 0; i < size; i += 2) {
2231                         if (i + 2 > size) {
2232                                 pr_info("invalid number of input parameters %d\n",
2233                                          size);
2234                                 return -EINVAL;
2235                         }
2236
2237                         input_index = input[i];
2238                         input_clk = input[i + 1];
2239
2240                         if (input_index != 1) {
2241                                 pr_info("Invalid index %d\n", input_index);
2242                                 pr_info("Support max Mclk frequency setting only which index by 1\n");
2243                                 return -EINVAL;
2244                         }
2245
2246                         if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2247                             input_clk > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value) {
2248                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2249                                         input_clk,
2250                                         clocks.data[0].clocks_in_khz / 1000,
2251                                         od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
2252                                 return -EINVAL;
2253                         }
2254
2255                         if (input_index == 1 && od_table->UclkFmax != input_clk) {
2256                                 table_context->od_gfxclk_update = true;
2257                                 od_table->UclkFmax = input_clk;
2258                         }
2259                 }
2260
2261                 break;
2262
2263         case PP_OD_EDIT_VDDC_CURVE:
2264                 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2265                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2266                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2267                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2268                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2269                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2270                         pr_info("Voltage curve calibrate not supported\n");
2271                         return -EOPNOTSUPP;
2272                 }
2273
2274                 for (i = 0; i < size; i += 3) {
2275                         if (i + 3 > size) {
2276                                 pr_info("invalid number of input parameters %d\n",
2277                                         size);
2278                                 return -EINVAL;
2279                         }
2280
2281                         input_index = input[i];
2282                         input_clk = input[i + 1];
2283                         input_vol = input[i + 2];
2284
2285                         if (input_index > 2) {
2286                                 pr_info("Setting for point %d is not supported\n",
2287                                         input_index + 1);
2288                                 pr_info("Three supported points index by 0, 1, 2\n");
2289                                 return -EINVAL;
2290                         }
2291
2292                         od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2293                         if (input_clk < od8_settings->od8_settings_array[od8_id].min_value ||
2294                             input_clk > od8_settings->od8_settings_array[od8_id].max_value) {
2295                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2296                                         input_clk,
2297                                         od8_settings->od8_settings_array[od8_id].min_value,
2298                                         od8_settings->od8_settings_array[od8_id].max_value);
2299                                 return -EINVAL;
2300                         }
2301
2302                         od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2303                         if (input_vol < od8_settings->od8_settings_array[od8_id].min_value ||
2304                             input_vol > od8_settings->od8_settings_array[od8_id].max_value) {
2305                                 pr_info("clock voltage %d is not within allowed range [%d- %d]\n",
2306                                         input_vol,
2307                                         od8_settings->od8_settings_array[od8_id].min_value,
2308                                         od8_settings->od8_settings_array[od8_id].max_value);
2309                                 return -EINVAL;
2310                         }
2311
2312                         switch (input_index) {
2313                         case 0:
2314                                 od_table->GfxclkFreq1 = input_clk;
2315                                 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2316                                 break;
2317                         case 1:
2318                                 od_table->GfxclkFreq2 = input_clk;
2319                                 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2320                                 break;
2321                         case 2:
2322                                 od_table->GfxclkFreq3 = input_clk;
2323                                 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2324                                 break;
2325                         }
2326                 }
2327
2328                 break;
2329
2330         case PP_OD_RESTORE_DEFAULT_TABLE:
2331                 ret = smu_update_table(smu, TABLE_OVERDRIVE, table_context->overdrive_table, false);
2332                 if (ret) {
2333                         pr_err("Failed to export over drive table!\n");
2334                         return ret;
2335                 }
2336
2337                 break;
2338
2339         case PP_OD_COMMIT_DPM_TABLE:
2340                 ret = smu_update_table(smu, TABLE_OVERDRIVE, table_context->overdrive_table, true);
2341                 if (ret) {
2342                         pr_err("Failed to import over drive table!\n");
2343                         return ret;
2344                 }
2345
2346                 /* retrieve updated gfxclk table */
2347                 if (table_context->od_gfxclk_update) {
2348                         table_context->od_gfxclk_update = false;
2349                         single_dpm_table = &(dpm_table->gfx_table);
2350
2351                         if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT)) {
2352                                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2353                                                                   PPCLK_GFXCLK);
2354                                 if (ret) {
2355                                         pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2356                                         return ret;
2357                                 }
2358                         } else {
2359                                 single_dpm_table->count = 1;
2360                                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2361                         }
2362                 }
2363
2364                 break;
2365
2366         default:
2367                 return -EINVAL;
2368         }
2369
2370         if (type == PP_OD_COMMIT_DPM_TABLE) {
2371                 mutex_lock(&(smu->mutex));
2372                 ret = smu_handle_task(smu, smu_dpm->dpm_level,
2373                                       AMD_PP_TASK_READJUST_POWER_STATE);
2374                 mutex_unlock(&(smu->mutex));
2375         }
2376
2377         return ret;
2378 }
2379
2380 static const struct pptable_funcs vega20_ppt_funcs = {
2381         .alloc_dpm_context = vega20_allocate_dpm_context,
2382         .store_powerplay_table = vega20_store_powerplay_table,
2383         .check_powerplay_table = vega20_check_powerplay_table,
2384         .append_powerplay_table = vega20_append_powerplay_table,
2385         .get_smu_msg_index = vega20_get_smu_msg_index,
2386         .run_afll_btc = vega20_run_btc_afll,
2387         .get_unallowed_feature_mask = vega20_get_unallowed_feature_mask,
2388         .get_current_power_state = vega20_get_current_power_state,
2389         .set_default_dpm_table = vega20_set_default_dpm_table,
2390         .set_power_state = NULL,
2391         .populate_umd_state_clk = vega20_populate_umd_state_clk,
2392         .print_clk_levels = vega20_print_clk_levels,
2393         .force_clk_levels = vega20_force_clk_levels,
2394         .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
2395         .set_default_od8_settings = vega20_set_default_od8_setttings,
2396         .get_od_percentage = vega20_get_od_percentage,
2397         .get_performance_level = vega20_get_performance_level,
2398         .force_performance_level = vega20_force_performance_level,
2399         .update_specified_od8_value = vega20_update_specified_od8_value,
2400         .set_od_percentage = vega20_set_od_percentage,
2401         .od_edit_dpm_table = vega20_odn_edit_dpm_table,
2402         .pre_display_config_changed = vega20_pre_display_config_changed,
2403         .display_config_changed = vega20_display_config_changed,
2404         .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
2405         .notify_smc_dispaly_config = vega20_notify_smc_dispaly_config,
2406         .force_dpm_limit_value = vega20_force_dpm_limit_value,
2407         .unforce_dpm_levels = vega20_unforce_dpm_levels,
2408         .upload_dpm_level = vega20_upload_dpm_level,
2409         .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
2410 };
2411
2412 void vega20_set_ppt_funcs(struct smu_context *smu)
2413 {
2414         smu->ppt_funcs = &vega20_ppt_funcs;
2415 }