2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Author: Huang Rui <ray.huang@amd.com>
26 #include <linux/types.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/gfp.h>
32 #include "iceland_smumgr.h"
36 #include "cgs_common.h"
38 #include "smu7_dyn_defaults.h"
39 #include "smu7_hwmgr.h"
40 #include "hardwaremanager.h"
41 #include "ppatomctrl.h"
43 #include "pppcielanes.h"
44 #include "pp_endian.h"
45 #include "processpptables.h"
48 #include "smu/smu_7_1_1_d.h"
49 #include "smu/smu_7_1_1_sh_mask.h"
50 #include "smu71_discrete.h"
52 #include "smu_ucode_xfer_vi.h"
53 #include "gmc/gmc_8_1_d.h"
54 #include "gmc/gmc_8_1_sh_mask.h"
55 #include "bif/bif_5_0_d.h"
56 #include "bif/bif_5_0_sh_mask.h"
57 #include "dce/dce_10_0_d.h"
58 #include "dce/dce_10_0_sh_mask.h"
61 #define ICELAND_SMC_SIZE 0x20000
63 #define VOLTAGE_SCALE 4
64 #define POWERTUNE_DEFAULT_SET_MAX 1
65 #define VOLTAGE_VID_OFFSET_SCALE1 625
66 #define VOLTAGE_VID_OFFSET_SCALE2 100
67 #define MC_CG_ARB_FREQ_F1 0x0b
68 #define VDDC_VDDCI_DELTA 200
70 #define DEVICE_ID_VI_ICELAND_M_6900 0x6900
71 #define DEVICE_ID_VI_ICELAND_M_6901 0x6901
72 #define DEVICE_ID_VI_ICELAND_M_6902 0x6902
73 #define DEVICE_ID_VI_ICELAND_M_6903 0x6903
75 static const struct iceland_pt_defaults defaults_iceland = {
77 * sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc,
78 * TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT
80 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
81 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
82 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
86 static const struct iceland_pt_defaults defaults_icelandxt = {
88 * sviLoadLIneEn, SviLoadLineVddC,
89 * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
90 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac,
93 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0,
94 { 0xA7, 0x0, 0x0, 0xB5, 0x0, 0x0, 0x9F, 0x0, 0x0, 0xD6, 0x0, 0x0, 0xD7, 0x0, 0x0},
95 { 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0}
99 static const struct iceland_pt_defaults defaults_icelandpro = {
101 * sviLoadLIneEn, SviLoadLineVddC,
102 * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
103 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac,
106 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0,
107 { 0xB7, 0x0, 0x0, 0xC3, 0x0, 0x0, 0xB5, 0x0, 0x0, 0xEA, 0x0, 0x0, 0xE6, 0x0, 0x0},
108 { 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0}
111 static int iceland_start_smc(struct pp_hwmgr *hwmgr)
113 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
114 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
119 static void iceland_reset_smc(struct pp_hwmgr *hwmgr)
121 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
122 SMC_SYSCON_RESET_CNTL,
127 static void iceland_stop_smc_clock(struct pp_hwmgr *hwmgr)
129 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
130 SMC_SYSCON_CLOCK_CNTL_0,
134 static void iceland_start_smc_clock(struct pp_hwmgr *hwmgr)
136 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
137 SMC_SYSCON_CLOCK_CNTL_0,
141 static int iceland_smu_start_smc(struct pp_hwmgr *hwmgr)
143 /* set smc instruct start point at 0x0 */
144 smu7_program_jump_on_start(hwmgr);
146 /* enable smc clock */
147 iceland_start_smc_clock(hwmgr);
149 /* de-assert reset */
150 iceland_start_smc(hwmgr);
152 PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
153 INTERRUPTS_ENABLED, 1);
159 static int iceland_upload_smc_firmware_data(struct pp_hwmgr *hwmgr,
160 uint32_t length, const uint8_t *src,
161 uint32_t limit, uint32_t start_addr)
163 uint32_t byte_count = length;
166 PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
168 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
169 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
171 while (byte_count >= 4) {
172 data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
173 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
178 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
180 PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL);
186 static int iceland_smu_upload_firmware_image(struct pp_hwmgr *hwmgr)
189 struct cgs_firmware_info info = {0};
191 if (hwmgr == NULL || hwmgr->device == NULL)
194 /* load SMC firmware */
195 cgs_get_firmware_info(hwmgr->device,
196 smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
198 if (info.image_size & 3) {
199 pr_err("[ powerplay ] SMC ucode is not 4 bytes aligned\n");
203 if (info.image_size > ICELAND_SMC_SIZE) {
204 pr_err("[ powerplay ] SMC address is beyond the SMC RAM area\n");
207 hwmgr->smu_version = info.version;
208 /* wait for smc boot up */
209 PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
210 RCU_UC_EVENTS, boot_seq_done, 0);
212 /* clear firmware interrupt enable flag */
213 val = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
214 ixSMC_SYSCON_MISC_CNTL);
215 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
216 ixSMC_SYSCON_MISC_CNTL, val | 1);
219 iceland_stop_smc_clock(hwmgr);
222 iceland_reset_smc(hwmgr);
223 iceland_upload_smc_firmware_data(hwmgr, info.image_size,
224 (uint8_t *)info.kptr, ICELAND_SMC_SIZE,
225 info.ucode_start_address);
230 static int iceland_request_smu_load_specific_fw(struct pp_hwmgr *hwmgr,
231 uint32_t firmwareType)
236 static int iceland_start_smu(struct pp_hwmgr *hwmgr)
240 result = iceland_smu_upload_firmware_image(hwmgr);
243 result = iceland_smu_start_smc(hwmgr);
247 if (!smu7_is_smc_ram_running(hwmgr)) {
248 pr_info("smu not running, upload firmware again \n");
249 result = iceland_smu_upload_firmware_image(hwmgr);
253 result = iceland_smu_start_smc(hwmgr);
258 result = smu7_request_smu_load_fw(hwmgr);
263 static int iceland_smu_init(struct pp_hwmgr *hwmgr)
266 struct iceland_smumgr *iceland_priv = NULL;
268 iceland_priv = kzalloc(sizeof(struct iceland_smumgr), GFP_KERNEL);
270 if (iceland_priv == NULL)
273 hwmgr->smu_backend = iceland_priv;
275 if (smu7_init(hwmgr))
278 for (i = 0; i < SMU71_MAX_LEVELS_GRAPHICS; i++)
279 iceland_priv->activity_target[i] = 30;
285 static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
287 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
288 struct cgs_system_info sys_info = {0};
291 sys_info.size = sizeof(struct cgs_system_info);
292 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
293 cgs_query_system_info(hwmgr->device, &sys_info);
294 dev_id = (uint32_t)sys_info.value;
297 case DEVICE_ID_VI_ICELAND_M_6900:
298 case DEVICE_ID_VI_ICELAND_M_6903:
299 smu_data->power_tune_defaults = &defaults_icelandxt;
302 case DEVICE_ID_VI_ICELAND_M_6901:
303 case DEVICE_ID_VI_ICELAND_M_6902:
304 smu_data->power_tune_defaults = &defaults_icelandpro;
307 smu_data->power_tune_defaults = &defaults_iceland;
308 pr_warn("Unknown V.I. Device ID.\n");
314 static int iceland_populate_svi_load_line(struct pp_hwmgr *hwmgr)
316 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
317 const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
319 smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
320 smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddc;
321 smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
322 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
327 static int iceland_populate_tdc_limit(struct pp_hwmgr *hwmgr)
330 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
331 const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
333 tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256);
334 smu_data->power_tune_table.TDC_VDDC_PkgLimit =
335 CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
336 smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
337 defaults->tdc_vddc_throttle_release_limit_perc;
338 smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt;
343 static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
345 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
346 const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
349 if (smu7_read_smc_sram_dword(hwmgr,
351 offsetof(SMU71_Discrete_PmFuses, TdcWaterfallCtl),
352 (uint32_t *)&temp, SMC_RAM_END))
353 PP_ASSERT_WITH_CODE(false,
354 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
357 smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl;
362 static int iceland_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
367 static int iceland_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
370 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
372 /* Currently not used. Set all to zero. */
373 for (i = 0; i < 8; i++)
374 smu_data->power_tune_table.GnbLPML[i] = 0;
379 static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
381 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
382 uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
383 uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
384 struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table;
386 HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
387 LoSidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
389 smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
390 CONVERT_FROM_HOST_TO_SMC_US(HiSidd);
391 smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
392 CONVERT_FROM_HOST_TO_SMC_US(LoSidd);
397 static int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr)
400 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
401 uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;
402 uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;
404 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,
405 "The CAC Leakage table does not exist!", return -EINVAL);
406 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,
407 "There should never be more than 8 entries for BapmVddcVid!!!", return -EINVAL);
408 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,
409 "CACLeakageTable->count and VddcDependencyOnSCLk->count not equal", return -EINVAL);
411 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) {
412 for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) {
413 lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1);
414 hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2);
417 PP_ASSERT_WITH_CODE(false, "Iceland should always support EVV", return -EINVAL);
423 static int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr)
426 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
427 uint8_t *vid = smu_data->power_tune_table.VddCVid;
428 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
430 PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8,
431 "There should never be more than 8 entries for VddcVid!!!",
434 for (i = 0; i < (int)data->vddc_voltage_table.count; i++) {
435 vid[i] = convert_to_vid(data->vddc_voltage_table.entries[i].value);
443 static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr)
445 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
446 uint32_t pm_fuse_table_offset;
448 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
449 PHM_PlatformCaps_PowerContainment)) {
450 if (smu7_read_smc_sram_dword(hwmgr,
451 SMU71_FIRMWARE_HEADER_LOCATION +
452 offsetof(SMU71_Firmware_Header, PmFuseTable),
453 &pm_fuse_table_offset, SMC_RAM_END))
454 PP_ASSERT_WITH_CODE(false,
455 "Attempt to get pm_fuse_table_offset Failed!",
459 if (iceland_populate_bapm_vddc_vid_sidd(hwmgr))
460 PP_ASSERT_WITH_CODE(false,
461 "Attempt to populate bapm vddc vid Failed!",
465 if (iceland_populate_vddc_vid(hwmgr))
466 PP_ASSERT_WITH_CODE(false,
467 "Attempt to populate vddc vid Failed!",
471 if (iceland_populate_svi_load_line(hwmgr))
472 PP_ASSERT_WITH_CODE(false,
473 "Attempt to populate SviLoadLine Failed!",
476 if (iceland_populate_tdc_limit(hwmgr))
477 PP_ASSERT_WITH_CODE(false,
478 "Attempt to populate TDCLimit Failed!", return -EINVAL);
480 if (iceland_populate_dw8(hwmgr, pm_fuse_table_offset))
481 PP_ASSERT_WITH_CODE(false,
482 "Attempt to populate TdcWaterfallCtl, "
483 "LPMLTemperature Min and Max Failed!",
487 if (0 != iceland_populate_temperature_scaler(hwmgr))
488 PP_ASSERT_WITH_CODE(false,
489 "Attempt to populate LPMLTemperatureScaler Failed!",
493 if (iceland_populate_gnb_lpml(hwmgr))
494 PP_ASSERT_WITH_CODE(false,
495 "Attempt to populate GnbLPML Failed!",
499 if (iceland_populate_bapm_vddc_base_leakage_sidd(hwmgr))
500 PP_ASSERT_WITH_CODE(false,
501 "Attempt to populate BapmVddCBaseLeakage Hi and Lo Sidd Failed!",
504 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
505 (uint8_t *)&smu_data->power_tune_table,
506 sizeof(struct SMU71_Discrete_PmFuses), SMC_RAM_END))
507 PP_ASSERT_WITH_CODE(false,
508 "Attempt to download PmFuseTable Failed!",
514 static int iceland_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
515 struct phm_clock_voltage_dependency_table *allowed_clock_voltage_table,
516 uint32_t clock, uint32_t *vol)
520 /* clock - voltage dependency table is empty table */
521 if (allowed_clock_voltage_table->count == 0)
524 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
525 /* find first sclk bigger than request */
526 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
527 *vol = allowed_clock_voltage_table->entries[i].v;
532 /* sclk is bigger than max sclk in the dependence table */
533 *vol = allowed_clock_voltage_table->entries[i - 1].v;
538 static int iceland_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr,
539 pp_atomctrl_voltage_table_entry *tab, uint16_t *hi,
543 bool vol_found = false;
544 *hi = tab->value * VOLTAGE_SCALE;
545 *lo = tab->value * VOLTAGE_SCALE;
547 /* SCLK/VDDC Dependency Table has to exist. */
548 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk,
549 "The SCLK/VDDC Dependency Table does not exist.",
552 if (NULL == hwmgr->dyn_state.cac_leakage_table) {
553 pr_warn("CAC Leakage Table does not exist, using vddc.\n");
558 * Since voltage in the sclk/vddc dependency table is not
559 * necessarily in ascending order because of ELB voltage
560 * patching, loop through entire list to find exact voltage.
562 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
563 if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
565 if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
566 *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
567 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE);
569 pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum index from CAC table.\n");
570 *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
571 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
578 * If voltage is not found in the first pass, loop again to
579 * find the best match, equal or higher value.
582 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
583 if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
585 if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
586 *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
587 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE;
589 pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using maximum index from CAC table.");
590 *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
591 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
598 pr_warn("Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc.\n");
604 static int iceland_populate_smc_voltage_table(struct pp_hwmgr *hwmgr,
605 pp_atomctrl_voltage_table_entry *tab,
606 SMU71_Discrete_VoltageLevel *smc_voltage_tab)
610 result = iceland_get_std_voltage_value_sidd(hwmgr, tab,
611 &smc_voltage_tab->StdVoltageHiSidd,
612 &smc_voltage_tab->StdVoltageLoSidd);
614 smc_voltage_tab->StdVoltageHiSidd = tab->value * VOLTAGE_SCALE;
615 smc_voltage_tab->StdVoltageLoSidd = tab->value * VOLTAGE_SCALE;
618 smc_voltage_tab->Voltage = PP_HOST_TO_SMC_US(tab->value * VOLTAGE_SCALE);
619 CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd);
620 CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd);
625 static int iceland_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
626 SMU71_Discrete_DpmTable *table)
630 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
632 table->VddcLevelCount = data->vddc_voltage_table.count;
633 for (count = 0; count < table->VddcLevelCount; count++) {
634 result = iceland_populate_smc_voltage_table(hwmgr,
635 &(data->vddc_voltage_table.entries[count]),
636 &(table->VddcLevel[count]));
637 PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL);
639 /* GPIO voltage control */
640 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control)
641 table->VddcLevel[count].Smio |= data->vddc_voltage_table.entries[count].smio_low;
642 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control)
643 table->VddcLevel[count].Smio = 0;
646 CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
651 static int iceland_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
652 SMU71_Discrete_DpmTable *table)
654 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
658 table->VddciLevelCount = data->vddci_voltage_table.count;
660 for (count = 0; count < table->VddciLevelCount; count++) {
661 result = iceland_populate_smc_voltage_table(hwmgr,
662 &(data->vddci_voltage_table.entries[count]),
663 &(table->VddciLevel[count]));
664 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL);
665 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
666 table->VddciLevel[count].Smio |= data->vddci_voltage_table.entries[count].smio_low;
668 table->VddciLevel[count].Smio |= 0;
671 CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
676 static int iceland_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
677 SMU71_Discrete_DpmTable *table)
679 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
683 table->MvddLevelCount = data->mvdd_voltage_table.count;
685 for (count = 0; count < table->VddciLevelCount; count++) {
686 result = iceland_populate_smc_voltage_table(hwmgr,
687 &(data->mvdd_voltage_table.entries[count]),
688 &table->MvddLevel[count]);
689 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL);
690 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control)
691 table->MvddLevel[count].Smio |= data->mvdd_voltage_table.entries[count].smio_low;
693 table->MvddLevel[count].Smio |= 0;
696 CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
702 static int iceland_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
703 SMU71_Discrete_DpmTable *table)
707 result = iceland_populate_smc_vddc_table(hwmgr, table);
708 PP_ASSERT_WITH_CODE(0 == result,
709 "can not populate VDDC voltage table to SMC", return -EINVAL);
711 result = iceland_populate_smc_vdd_ci_table(hwmgr, table);
712 PP_ASSERT_WITH_CODE(0 == result,
713 "can not populate VDDCI voltage table to SMC", return -EINVAL);
715 result = iceland_populate_smc_mvdd_table(hwmgr, table);
716 PP_ASSERT_WITH_CODE(0 == result,
717 "can not populate MVDD voltage table to SMC", return -EINVAL);
722 static int iceland_populate_ulv_level(struct pp_hwmgr *hwmgr,
723 struct SMU71_Discrete_Ulv *state)
725 uint32_t voltage_response_time, ulv_voltage;
727 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
729 state->CcPwrDynRm = 0;
730 state->CcPwrDynRm1 = 0;
732 result = pp_tables_get_response_times(hwmgr, &voltage_response_time, &ulv_voltage);
733 PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;);
735 if (ulv_voltage == 0) {
736 data->ulv_supported = false;
740 if (data->voltage_control != SMU7_VOLTAGE_CONTROL_BY_SVID2) {
741 /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
742 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
743 state->VddcOffset = 0;
745 /* used in SMIO Mode. not implemented for now. this is backup only for CI. */
746 state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage);
748 /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
749 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
750 state->VddcOffsetVid = 0;
751 else /* used in SVI2 Mode */
752 state->VddcOffsetVid = (uint8_t)(
753 (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage)
754 * VOLTAGE_VID_OFFSET_SCALE2
755 / VOLTAGE_VID_OFFSET_SCALE1);
757 state->VddcPhase = 1;
759 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
760 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
761 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
766 static int iceland_populate_ulv_state(struct pp_hwmgr *hwmgr,
767 SMU71_Discrete_Ulv *ulv_level)
769 return iceland_populate_ulv_level(hwmgr, ulv_level);
772 static int iceland_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU71_Discrete_DpmTable *table)
774 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
775 struct smu7_dpm_table *dpm_table = &data->dpm_table;
776 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
779 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
780 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
781 table->LinkLevel[i].PcieGenSpeed =
782 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
783 table->LinkLevel[i].PcieLaneCount =
784 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
785 table->LinkLevel[i].EnabledForActivity =
787 table->LinkLevel[i].SPC =
788 (uint8_t)(data->pcie_spc_cap & 0xff);
789 table->LinkLevel[i].DownThreshold =
790 PP_HOST_TO_SMC_UL(5);
791 table->LinkLevel[i].UpThreshold =
792 PP_HOST_TO_SMC_UL(30);
795 smu_data->smc_state_table.LinkLevelCount =
796 (uint8_t)dpm_table->pcie_speed_table.count;
797 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
798 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
803 static int iceland_calculate_sclk_params(struct pp_hwmgr *hwmgr,
804 uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk)
806 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
807 pp_atomctrl_clock_dividers_vi dividers;
808 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
809 uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
810 uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
811 uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
812 uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
813 uint32_t reference_clock;
814 uint32_t reference_divider;
818 /* get the engine clock dividers for this clock value*/
819 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs);
821 PP_ASSERT_WITH_CODE(result == 0,
822 "Error retrieving Engine Clock dividers from VBIOS.", return result);
824 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
825 reference_clock = atomctrl_get_reference_clock(hwmgr);
827 reference_divider = 1 + dividers.uc_pll_ref_div;
829 /* low 14 bits is fraction and high 12 bits is divider*/
830 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
832 /* SPLL_FUNC_CNTL setup*/
833 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
834 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
835 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
836 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
838 /* SPLL_FUNC_CNTL_3 setup*/
839 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
840 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
842 /* set to use fractional accumulation*/
843 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
844 CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
846 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
847 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
848 pp_atomctrl_internal_ss_info ss_info;
850 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
851 if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
853 * ss_info.speed_spectrum_percentage -- in unit of 0.01%
854 * ss_info.speed_spectrum_rate -- in unit of khz
856 /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
857 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
859 /* clkv = 2 * D * fbdiv / NS */
860 uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
862 cg_spll_spread_spectrum =
863 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
864 cg_spll_spread_spectrum =
865 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
866 cg_spll_spread_spectrum_2 =
867 PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
871 sclk->SclkFrequency = engine_clock;
872 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
873 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
874 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
875 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
876 sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
881 static int iceland_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr,
882 const struct phm_phase_shedding_limits_table *pl,
883 uint32_t sclk, uint32_t *p_shed)
887 /* use the minimum phase shedding */
890 for (i = 0; i < pl->count; i++) {
891 if (sclk < pl->entries[i].Sclk) {
899 static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
900 uint32_t engine_clock,
901 uint16_t sclk_activity_level_threshold,
902 SMU71_Discrete_GraphicsLevel *graphic_level)
905 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
907 result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
909 /* populate graphics levels*/
910 result = iceland_get_dependency_volt_by_clk(hwmgr,
911 hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock,
912 &graphic_level->MinVddc);
913 PP_ASSERT_WITH_CODE((0 == result),
914 "can not find VDDC voltage value for VDDC engine clock dependency table", return result);
916 /* SCLK frequency in units of 10KHz*/
917 graphic_level->SclkFrequency = engine_clock;
918 graphic_level->MinVddcPhases = 1;
920 if (data->vddc_phase_shed_control)
921 iceland_populate_phase_value_based_on_sclk(hwmgr,
922 hwmgr->dyn_state.vddc_phase_shed_limits_table,
924 &graphic_level->MinVddcPhases);
926 /* Indicates maximum activity level for this performance level. 50% for now*/
927 graphic_level->ActivityLevel = sclk_activity_level_threshold;
929 graphic_level->CcPwrDynRm = 0;
930 graphic_level->CcPwrDynRm1 = 0;
931 /* this level can be used if activity is high enough.*/
932 graphic_level->EnabledForActivity = 0;
933 /* this level can be used for throttling.*/
934 graphic_level->EnabledForThrottle = 1;
935 graphic_level->UpHyst = 0;
936 graphic_level->DownHyst = 100;
937 graphic_level->VoltageDownHyst = 0;
938 graphic_level->PowerThrottle = 0;
940 data->display_timing.min_clock_in_sr =
941 hwmgr->display_config.min_core_set_clock_in_sr;
943 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
944 PHM_PlatformCaps_SclkDeepSleep))
945 graphic_level->DeepSleepDivId =
946 smu7_get_sleep_divider_id_from_clock(engine_clock,
947 data->display_timing.min_clock_in_sr);
949 /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
950 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
953 graphic_level->MinVddc = PP_HOST_TO_SMC_UL(graphic_level->MinVddc * VOLTAGE_SCALE);
954 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);
955 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
956 CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
957 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
958 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
959 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
960 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
961 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
962 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
968 static int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
970 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
971 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
972 struct smu7_dpm_table *dpm_table = &data->dpm_table;
973 uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start +
974 offsetof(SMU71_Discrete_DpmTable, GraphicsLevel);
976 uint32_t level_array_size = sizeof(SMU71_Discrete_GraphicsLevel) *
977 SMU71_MAX_LEVELS_GRAPHICS;
979 SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
982 uint8_t highest_pcie_level_enabled = 0;
983 uint8_t lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0;
987 memset(levels, 0x00, level_array_size);
989 for (i = 0; i < dpm_table->sclk_table.count; i++) {
990 result = iceland_populate_single_graphic_level(hwmgr,
991 dpm_table->sclk_table.dpm_levels[i].value,
992 (uint16_t)smu_data->activity_target[i],
993 &(smu_data->smc_state_table.GraphicsLevel[i]));
997 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
999 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
1002 /* Only enable level 0 for now. */
1003 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1005 /* set highest level watermark to high */
1006 if (dpm_table->sclk_table.count > 1)
1007 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
1008 PPSMC_DISPLAY_WATERMARK_HIGH;
1010 smu_data->smc_state_table.GraphicsDpmLevelCount =
1011 (uint8_t)dpm_table->sclk_table.count;
1012 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1013 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1015 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1016 (1 << (highest_pcie_level_enabled + 1))) != 0) {
1017 highest_pcie_level_enabled++;
1020 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1021 (1 << lowest_pcie_level_enabled)) == 0) {
1022 lowest_pcie_level_enabled++;
1025 while ((count < highest_pcie_level_enabled) &&
1026 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1027 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0)) {
1031 mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
1032 (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
1035 /* set pcieDpmLevel to highest_pcie_level_enabled*/
1036 for (i = 2; i < dpm_table->sclk_table.count; i++) {
1037 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
1040 /* set pcieDpmLevel to lowest_pcie_level_enabled*/
1041 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
1043 /* set pcieDpmLevel to mid_pcie_level_enabled*/
1044 smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
1046 /* level count will send to smc once at init smc table and never change*/
1047 result = smu7_copy_bytes_to_smc(hwmgr, level_array_adress,
1048 (uint8_t *)levels, (uint32_t)level_array_size,
1054 static int iceland_calculate_mclk_params(
1055 struct pp_hwmgr *hwmgr,
1056 uint32_t memory_clock,
1057 SMU71_Discrete_MemoryLevel *mclk,
1062 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1064 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
1065 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
1066 uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
1067 uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
1068 uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
1069 uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
1070 uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
1071 uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;
1072 uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
1074 pp_atomctrl_memory_clock_param mpll_param;
1077 result = atomctrl_get_memory_pll_dividers_si(hwmgr,
1078 memory_clock, &mpll_param, strobe_mode);
1079 PP_ASSERT_WITH_CODE(0 == result,
1080 "Error retrieving Memory Clock Parameters from VBIOS.", return result);
1082 /* MPLL_FUNC_CNTL setup*/
1083 mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
1085 /* MPLL_FUNC_CNTL_1 setup*/
1086 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1087 MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
1088 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1089 MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
1090 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1091 MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
1093 /* MPLL_AD_FUNC_CNTL setup*/
1094 mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
1095 MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1097 if (data->is_memory_gddr5) {
1098 /* MPLL_DQ_FUNC_CNTL setup*/
1099 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1100 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
1101 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1102 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1105 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1106 PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
1108 ************************************
1109 Fref = Reference Frequency
1110 NF = Feedback divider ratio
1111 NR = Reference divider ratio
1112 Fnom = Nominal VCO output frequency = Fref * NF / NR
1114 D = Percentage down-spread / 2
1115 Fint = Reference input frequency to PFD = Fref / NR
1116 NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
1117 CLKS = NS - 1 = ISS_STEP_NUM[11:0]
1118 NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
1119 CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
1120 *************************************
1122 pp_atomctrl_internal_ss_info ss_info;
1125 uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
1127 /* for GDDR5 for all modes and DDR3 */
1128 if (1 == mpll_param.qdr)
1129 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
1131 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
1133 /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
1134 tmp = (freq_nom / reference_clock);
1137 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
1138 /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
1139 /* ss.Info.speed_spectrum_rate -- in unit of khz */
1140 /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
1141 /* = reference_clock * 5 / speed_spectrum_rate */
1142 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
1144 /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
1145 /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
1147 (uint32_t)((((131 * ss_info.speed_spectrum_percentage *
1148 ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
1150 mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
1151 mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
1155 /* MCLK_PWRMGT_CNTL setup */
1156 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1157 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
1158 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1159 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
1160 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1161 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
1164 /* Save the result data to outpupt memory level structure */
1165 mclk->MclkFrequency = memory_clock;
1166 mclk->MpllFuncCntl = mpll_func_cntl;
1167 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
1168 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
1169 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
1170 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
1171 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
1172 mclk->DllCntl = dll_cntl;
1173 mclk->MpllSs1 = mpll_ss1;
1174 mclk->MpllSs2 = mpll_ss2;
1179 static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock,
1182 uint8_t mc_para_index;
1185 if (memory_clock < 12500) {
1186 mc_para_index = 0x00;
1187 } else if (memory_clock > 47500) {
1188 mc_para_index = 0x0f;
1190 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
1193 if (memory_clock < 65000) {
1194 mc_para_index = 0x00;
1195 } else if (memory_clock > 135000) {
1196 mc_para_index = 0x0f;
1198 mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
1202 return mc_para_index;
1205 static uint8_t iceland_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
1207 uint8_t mc_para_index;
1209 if (memory_clock < 10000) {
1211 } else if (memory_clock >= 80000) {
1212 mc_para_index = 0x0f;
1214 mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
1217 return mc_para_index;
1220 static int iceland_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl,
1221 uint32_t memory_clock, uint32_t *p_shed)
1227 for (i = 0; i < pl->count; i++) {
1228 if (memory_clock < pl->entries[i].Mclk) {
1237 static int iceland_populate_single_memory_level(
1238 struct pp_hwmgr *hwmgr,
1239 uint32_t memory_clock,
1240 SMU71_Discrete_MemoryLevel *memory_level
1243 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1246 struct cgs_display_info info = {0};
1247 uint32_t mclk_edc_wr_enable_threshold = 40000;
1248 uint32_t mclk_edc_enable_threshold = 40000;
1249 uint32_t mclk_strobe_mode_threshold = 40000;
1251 if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) {
1252 result = iceland_get_dependency_volt_by_clk(hwmgr,
1253 hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc);
1254 PP_ASSERT_WITH_CODE((0 == result),
1255 "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
1258 if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE) {
1259 memory_level->MinVddci = memory_level->MinVddc;
1260 } else if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {
1261 result = iceland_get_dependency_volt_by_clk(hwmgr,
1262 hwmgr->dyn_state.vddci_dependency_on_mclk,
1264 &memory_level->MinVddci);
1265 PP_ASSERT_WITH_CODE((0 == result),
1266 "can not find MinVddci voltage value from memory VDDCI voltage dependency table", return result);
1269 memory_level->MinVddcPhases = 1;
1271 if (data->vddc_phase_shed_control) {
1272 iceland_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table,
1273 memory_clock, &memory_level->MinVddcPhases);
1276 memory_level->EnabledForThrottle = 1;
1277 memory_level->EnabledForActivity = 0;
1278 memory_level->UpHyst = 0;
1279 memory_level->DownHyst = 100;
1280 memory_level->VoltageDownHyst = 0;
1282 /* Indicates maximum activity level for this performance level.*/
1283 memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1284 memory_level->StutterEnable = 0;
1285 memory_level->StrobeEnable = 0;
1286 memory_level->EdcReadEnable = 0;
1287 memory_level->EdcWriteEnable = 0;
1288 memory_level->RttEnable = 0;
1290 /* default set to low watermark. Highest level will be set to high later.*/
1291 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1293 cgs_get_active_displays_info(hwmgr->device, &info);
1294 data->display_timing.num_existing_displays = info.display_count;
1296 /* stutter mode not support on iceland */
1298 /* decide strobe mode*/
1299 memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) &&
1300 (memory_clock <= mclk_strobe_mode_threshold);
1302 /* decide EDC mode and memory clock ratio*/
1303 if (data->is_memory_gddr5) {
1304 memory_level->StrobeRatio = iceland_get_mclk_frequency_ratio(memory_clock,
1305 memory_level->StrobeEnable);
1307 if ((mclk_edc_enable_threshold != 0) &&
1308 (memory_clock > mclk_edc_enable_threshold)) {
1309 memory_level->EdcReadEnable = 1;
1312 if ((mclk_edc_wr_enable_threshold != 0) &&
1313 (memory_clock > mclk_edc_wr_enable_threshold)) {
1314 memory_level->EdcWriteEnable = 1;
1317 if (memory_level->StrobeEnable) {
1318 if (iceland_get_mclk_frequency_ratio(memory_clock, 1) >=
1319 ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf))
1320 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
1322 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
1324 dll_state_on = data->dll_default_on;
1326 memory_level->StrobeRatio =
1327 iceland_get_ddr3_mclk_frequency_ratio(memory_clock);
1328 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
1331 result = iceland_calculate_mclk_params(hwmgr,
1332 memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
1335 memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE);
1336 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases);
1337 memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE);
1338 memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE);
1339 /* MCLK frequency in units of 10KHz*/
1340 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
1341 /* Indicates maximum activity level for this performance level.*/
1342 CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
1343 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
1344 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
1345 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
1346 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
1347 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
1348 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
1349 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
1350 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
1351 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
1357 static int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1359 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1360 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1361 struct smu7_dpm_table *dpm_table = &data->dpm_table;
1364 /* populate MCLK dpm table to SMU7 */
1365 uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, MemoryLevel);
1366 uint32_t level_array_size = sizeof(SMU71_Discrete_MemoryLevel) * SMU71_MAX_LEVELS_MEMORY;
1367 SMU71_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel;
1370 memset(levels, 0x00, level_array_size);
1372 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1373 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1374 "can not populate memory level as memory clock is zero", return -EINVAL);
1375 result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
1376 &(smu_data->smc_state_table.MemoryLevel[i]));
1382 /* Only enable level 0 for now.*/
1383 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
1386 * in order to prevent MC activity from stutter mode to push DPM up.
1387 * the UVD change complements this by putting the MCLK in a higher state
1388 * by default such that we are not effected by up threshold or and MCLK DPM latency.
1390 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
1391 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
1393 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
1394 data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1395 /* set highest level watermark to high*/
1396 smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1398 /* level count will send to smc once at init smc table and never change*/
1399 result = smu7_copy_bytes_to_smc(hwmgr,
1400 level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size,
1406 static int iceland_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk,
1407 SMU71_Discrete_VoltageLevel *voltage)
1409 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1413 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1414 /* find mvdd value which clock is more than request */
1415 for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) {
1416 if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) {
1417 /* Always round to higher voltage. */
1418 voltage->Voltage = data->mvdd_voltage_table.entries[i].value;
1423 PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count,
1424 "MVDD Voltage is outside the supported range.", return -EINVAL);
1433 static int iceland_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1434 SMU71_Discrete_DpmTable *table)
1437 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1438 struct pp_atomctrl_clock_dividers_vi dividers;
1439 uint32_t vddc_phase_shed_control = 0;
1441 SMU71_Discrete_VoltageLevel voltage_level;
1442 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1443 uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
1444 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
1445 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
1448 /* The ACPI state should not do DPM on DC (or ever).*/
1449 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1451 if (data->acpi_vddc)
1452 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);
1454 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);
1456 table->ACPILevel.MinVddcPhases = vddc_phase_shed_control ? 0 : 1;
1457 /* assign zero for now*/
1458 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
1460 /* get the engine clock dividers for this clock value*/
1461 result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
1462 table->ACPILevel.SclkFrequency, ÷rs);
1464 PP_ASSERT_WITH_CODE(result == 0,
1465 "Error retrieving Engine Clock dividers from VBIOS.", return result);
1467 /* divider ID for required SCLK*/
1468 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1469 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1470 table->ACPILevel.DeepSleepDivId = 0;
1472 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
1473 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0);
1474 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
1475 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1);
1476 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2,
1477 CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4);
1479 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
1480 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
1481 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1482 table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
1483 table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
1484 table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
1485 table->ACPILevel.CcPwrDynRm = 0;
1486 table->ACPILevel.CcPwrDynRm1 = 0;
1489 /* For various features to be enabled/disabled while this level is active.*/
1490 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1491 /* SCLK frequency in units of 10KHz*/
1492 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
1493 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
1494 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
1495 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
1496 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
1497 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
1498 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
1499 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1500 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1502 /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
1503 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
1504 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
1506 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
1507 table->MemoryACPILevel.MinVddci = table->MemoryACPILevel.MinVddc;
1509 if (data->acpi_vddci != 0)
1510 table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE);
1512 table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE);
1515 if (0 == iceland_populate_mvdd_value(hwmgr, 0, &voltage_level))
1516 table->MemoryACPILevel.MinMvdd =
1517 PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
1519 table->MemoryACPILevel.MinMvdd = 0;
1521 /* Force reset on DLL*/
1522 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1523 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
1524 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1525 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
1527 /* Disable DLL in ACPIState*/
1528 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1529 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
1530 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1531 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
1533 /* Enable DLL bypass signal*/
1534 dll_cntl = PHM_SET_FIELD(dll_cntl,
1535 DLL_CNTL, MRDCK0_BYPASS, 0);
1536 dll_cntl = PHM_SET_FIELD(dll_cntl,
1537 DLL_CNTL, MRDCK1_BYPASS, 0);
1539 table->MemoryACPILevel.DllCntl =
1540 PP_HOST_TO_SMC_UL(dll_cntl);
1541 table->MemoryACPILevel.MclkPwrmgtCntl =
1542 PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
1543 table->MemoryACPILevel.MpllAdFuncCntl =
1544 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
1545 table->MemoryACPILevel.MpllDqFuncCntl =
1546 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
1547 table->MemoryACPILevel.MpllFuncCntl =
1548 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
1549 table->MemoryACPILevel.MpllFuncCntl_1 =
1550 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
1551 table->MemoryACPILevel.MpllFuncCntl_2 =
1552 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
1553 table->MemoryACPILevel.MpllSs1 =
1554 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
1555 table->MemoryACPILevel.MpllSs2 =
1556 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
1558 table->MemoryACPILevel.EnabledForThrottle = 0;
1559 table->MemoryACPILevel.EnabledForActivity = 0;
1560 table->MemoryACPILevel.UpHyst = 0;
1561 table->MemoryACPILevel.DownHyst = 100;
1562 table->MemoryACPILevel.VoltageDownHyst = 0;
1563 /* Indicates maximum activity level for this performance level.*/
1564 table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1566 table->MemoryACPILevel.StutterEnable = 0;
1567 table->MemoryACPILevel.StrobeEnable = 0;
1568 table->MemoryACPILevel.EdcReadEnable = 0;
1569 table->MemoryACPILevel.EdcWriteEnable = 0;
1570 table->MemoryACPILevel.RttEnable = 0;
1575 static int iceland_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1576 SMU71_Discrete_DpmTable *table)
1581 static int iceland_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1582 SMU71_Discrete_DpmTable *table)
1587 static int iceland_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
1588 SMU71_Discrete_DpmTable *table)
1593 static int iceland_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1594 SMU71_Discrete_DpmTable *table)
1599 static int iceland_populate_memory_timing_parameters(
1600 struct pp_hwmgr *hwmgr,
1601 uint32_t engine_clock,
1602 uint32_t memory_clock,
1603 struct SMU71_Discrete_MCArbDramTimingTableEntry *arb_regs
1606 uint32_t dramTiming;
1607 uint32_t dramTiming2;
1611 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1612 engine_clock, memory_clock);
1614 PP_ASSERT_WITH_CODE(result == 0,
1615 "Error calling VBIOS to set DRAM_TIMING.", return result);
1617 dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1618 dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1619 burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1621 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);
1622 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
1623 arb_regs->McArbBurstTime = (uint8_t)burstTime;
1628 static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1630 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1631 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1633 SMU71_Discrete_MCArbDramTimingTable arb_regs;
1636 memset(&arb_regs, 0x00, sizeof(SMU71_Discrete_MCArbDramTimingTable));
1638 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1639 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1640 result = iceland_populate_memory_timing_parameters
1641 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
1642 data->dpm_table.mclk_table.dpm_levels[j].value,
1643 &arb_regs.entries[i][j]);
1652 result = smu7_copy_bytes_to_smc(
1654 smu_data->smu7_data.arb_table_start,
1655 (uint8_t *)&arb_regs,
1656 sizeof(SMU71_Discrete_MCArbDramTimingTable),
1664 static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1665 SMU71_Discrete_DpmTable *table)
1668 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1669 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1670 table->GraphicsBootLevel = 0;
1671 table->MemoryBootLevel = 0;
1673 /* find boot level from dpm table*/
1674 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1675 data->vbios_boot_state.sclk_bootup_value,
1676 (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));
1679 smu_data->smc_state_table.GraphicsBootLevel = 0;
1680 pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n");
1684 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1685 data->vbios_boot_state.mclk_bootup_value,
1686 (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));
1689 smu_data->smc_state_table.MemoryBootLevel = 0;
1690 pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n");
1694 table->BootVddc = data->vbios_boot_state.vddc_bootup_value;
1695 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
1696 table->BootVddci = table->BootVddc;
1698 table->BootVddci = data->vbios_boot_state.vddci_bootup_value;
1700 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
1705 static int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
1706 SMU71_Discrete_MCRegisters *mc_reg_table)
1708 const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)hwmgr->smu_backend;
1712 for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) {
1713 if (smu_data->mc_reg_table.validflag & 1<<j) {
1714 PP_ASSERT_WITH_CODE(i < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE,
1715 "Index of mc_reg_table->address[] array out of boundary", return -EINVAL);
1716 mc_reg_table->address[i].s0 =
1717 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
1718 mc_reg_table->address[i].s1 =
1719 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
1724 mc_reg_table->last = (uint8_t)i;
1729 /*convert register values from driver to SMC format */
1730 static void iceland_convert_mc_registers(
1731 const struct iceland_mc_reg_entry *entry,
1732 SMU71_Discrete_MCRegisterSet *data,
1733 uint32_t num_entries, uint32_t valid_flag)
1737 for (i = 0, j = 0; j < num_entries; j++) {
1738 if (valid_flag & 1<<j) {
1739 data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]);
1745 static int iceland_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr *hwmgr,
1746 const uint32_t memory_clock,
1747 SMU71_Discrete_MCRegisterSet *mc_reg_table_data
1750 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1753 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
1755 smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) {
1760 if ((i == smu_data->mc_reg_table.num_entries) && (i > 0))
1763 iceland_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i],
1764 mc_reg_table_data, smu_data->mc_reg_table.last,
1765 smu_data->mc_reg_table.validflag);
1770 static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
1771 SMU71_Discrete_MCRegisters *mc_regs)
1774 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1778 for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
1779 res = iceland_convert_mc_reg_table_entry_to_smc(
1781 data->dpm_table.mclk_table.dpm_levels[i].value,
1792 static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
1794 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1795 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1799 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
1803 memset(&smu_data->mc_regs, 0, sizeof(SMU71_Discrete_MCRegisters));
1805 result = iceland_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
1811 address = smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]);
1813 return smu7_copy_bytes_to_smc(hwmgr, address,
1814 (uint8_t *)&smu_data->mc_regs.data[0],
1815 sizeof(SMU71_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
1819 static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
1822 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1824 memset(&smu_data->mc_regs, 0x00, sizeof(SMU71_Discrete_MCRegisters));
1825 result = iceland_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
1826 PP_ASSERT_WITH_CODE(0 == result,
1827 "Failed to initialize MCRegTable for the MC register addresses!", return result;);
1829 result = iceland_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
1830 PP_ASSERT_WITH_CODE(0 == result,
1831 "Failed to initialize MCRegTable for driver state!", return result;);
1833 return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
1834 (uint8_t *)&smu_data->mc_regs, sizeof(SMU71_Discrete_MCRegisters), SMC_RAM_END);
1837 static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
1839 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1840 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1841 uint8_t count, level;
1843 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count);
1845 for (level = 0; level < count; level++) {
1846 if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk
1847 >= data->vbios_boot_state.sclk_bootup_value) {
1848 smu_data->smc_state_table.GraphicsBootLevel = level;
1853 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count);
1855 for (level = 0; level < count; level++) {
1856 if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk
1857 >= data->vbios_boot_state.mclk_bootup_value) {
1858 smu_data->smc_state_table.MemoryBootLevel = level;
1866 static int iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
1868 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1869 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1870 const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
1871 SMU71_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
1872 struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table;
1873 struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table;
1874 const uint16_t *def1, *def2;
1879 * TDP number of fraction bits are changed from 8 to 7 for Iceland
1880 * as requested by SMC team
1883 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256));
1884 dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usConfigurableTDP * 256));
1887 dpm_table->DTETjOffset = 0;
1889 dpm_table->GpuTjMax = (uint8_t)(data->thermal_temp_setting.temperature_high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES);
1890 dpm_table->GpuTjHyst = 8;
1892 dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base;
1894 /* The following are for new Iceland Multi-input fan/thermal control */
1896 dpm_table->PPM_PkgPwrLimit = (uint16_t)ppm->dgpu_tdp * 256 / 1000;
1897 dpm_table->PPM_TemperatureLimit = (uint16_t)ppm->tj_max * 256;
1899 dpm_table->PPM_PkgPwrLimit = 0;
1900 dpm_table->PPM_TemperatureLimit = 0;
1903 CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_PkgPwrLimit);
1904 CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_TemperatureLimit);
1906 dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);
1907 def1 = defaults->bapmti_r;
1908 def2 = defaults->bapmti_rc;
1910 for (i = 0; i < SMU71_DTE_ITERATIONS; i++) {
1911 for (j = 0; j < SMU71_DTE_SOURCES; j++) {
1912 for (k = 0; k < SMU71_DTE_SINKS; k++) {
1913 dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*def1);
1914 dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*def2);
1924 static int iceland_populate_smc_svi2_config(struct pp_hwmgr *hwmgr,
1925 SMU71_Discrete_DpmTable *tab)
1927 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1929 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control)
1930 tab->SVI2Enable |= VDDC_ON_SVI2;
1932 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1933 tab->SVI2Enable |= VDDCI_ON_SVI2;
1935 tab->MergedVddci = 1;
1937 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control)
1938 tab->SVI2Enable |= MVDD_ON_SVI2;
1940 PP_ASSERT_WITH_CODE(tab->SVI2Enable != (VDDC_ON_SVI2 | VDDCI_ON_SVI2 | MVDD_ON_SVI2) &&
1941 (tab->SVI2Enable & VDDC_ON_SVI2), "SVI2 domain configuration is incorrect!", return -EINVAL);
1946 static int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
1949 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1950 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1951 SMU71_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1954 iceland_initialize_power_tune_defaults(hwmgr);
1955 memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table));
1957 if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control) {
1958 iceland_populate_smc_voltage_tables(hwmgr, table);
1961 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1962 PHM_PlatformCaps_AutomaticDCTransition))
1963 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1966 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1967 PHM_PlatformCaps_StepVddc))
1968 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1970 if (data->is_memory_gddr5)
1971 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1974 if (data->ulv_supported) {
1975 result = iceland_populate_ulv_state(hwmgr, &(smu_data->ulv_setting));
1976 PP_ASSERT_WITH_CODE(0 == result,
1977 "Failed to initialize ULV state!", return result;);
1979 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1980 ixCG_ULV_PARAMETER, 0x40035);
1983 result = iceland_populate_smc_link_level(hwmgr, table);
1984 PP_ASSERT_WITH_CODE(0 == result,
1985 "Failed to initialize Link Level!", return result;);
1987 result = iceland_populate_all_graphic_levels(hwmgr);
1988 PP_ASSERT_WITH_CODE(0 == result,
1989 "Failed to initialize Graphics Level!", return result;);
1991 result = iceland_populate_all_memory_levels(hwmgr);
1992 PP_ASSERT_WITH_CODE(0 == result,
1993 "Failed to initialize Memory Level!", return result;);
1995 result = iceland_populate_smc_acpi_level(hwmgr, table);
1996 PP_ASSERT_WITH_CODE(0 == result,
1997 "Failed to initialize ACPI Level!", return result;);
1999 result = iceland_populate_smc_vce_level(hwmgr, table);
2000 PP_ASSERT_WITH_CODE(0 == result,
2001 "Failed to initialize VCE Level!", return result;);
2003 result = iceland_populate_smc_acp_level(hwmgr, table);
2004 PP_ASSERT_WITH_CODE(0 == result,
2005 "Failed to initialize ACP Level!", return result;);
2007 result = iceland_populate_smc_samu_level(hwmgr, table);
2008 PP_ASSERT_WITH_CODE(0 == result,
2009 "Failed to initialize SAMU Level!", return result;);
2011 /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
2012 /* need to populate the ARB settings for the initial state. */
2013 result = iceland_program_memory_timing_parameters(hwmgr);
2014 PP_ASSERT_WITH_CODE(0 == result,
2015 "Failed to Write ARB settings for the initial state.", return result;);
2017 result = iceland_populate_smc_uvd_level(hwmgr, table);
2018 PP_ASSERT_WITH_CODE(0 == result,
2019 "Failed to initialize UVD Level!", return result;);
2021 table->GraphicsBootLevel = 0;
2022 table->MemoryBootLevel = 0;
2024 result = iceland_populate_smc_boot_level(hwmgr, table);
2025 PP_ASSERT_WITH_CODE(0 == result,
2026 "Failed to initialize Boot Level!", return result;);
2028 result = iceland_populate_smc_initial_state(hwmgr);
2029 PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result);
2031 result = iceland_populate_bapm_parameters_in_dpm_table(hwmgr);
2032 PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result);
2034 table->GraphicsVoltageChangeEnable = 1;
2035 table->GraphicsThermThrottleEnable = 1;
2036 table->GraphicsInterval = 1;
2037 table->VoltageInterval = 1;
2038 table->ThermalInterval = 1;
2040 table->TemperatureLimitHigh =
2041 (data->thermal_temp_setting.temperature_high *
2042 SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2043 table->TemperatureLimitLow =
2044 (data->thermal_temp_setting.temperature_low *
2045 SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2047 table->MemoryVoltageChangeEnable = 1;
2048 table->MemoryInterval = 1;
2049 table->VoltageResponseTime = 0;
2050 table->PhaseResponseTime = 0;
2051 table->MemoryThermThrottleEnable = 1;
2052 table->PCIeBootLinkLevel = 0;
2053 table->PCIeGenInterval = 1;
2055 result = iceland_populate_smc_svi2_config(hwmgr, table);
2056 PP_ASSERT_WITH_CODE(0 == result,
2057 "Failed to populate SVI2 setting!", return result);
2059 table->ThermGpio = 17;
2060 table->SclkStepSize = 0x4000;
2062 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2063 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid);
2064 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase);
2065 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid);
2066 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskMvddVid);
2067 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2068 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2069 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2070 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2071 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2073 table->BootVddc = PP_HOST_TO_SMC_US(table->BootVddc * VOLTAGE_SCALE);
2074 table->BootVddci = PP_HOST_TO_SMC_US(table->BootVddci * VOLTAGE_SCALE);
2075 table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);
2077 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2078 result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.dpm_table_start +
2079 offsetof(SMU71_Discrete_DpmTable, SystemFlags),
2080 (uint8_t *)&(table->SystemFlags),
2081 sizeof(SMU71_Discrete_DpmTable)-3 * sizeof(SMU71_PIDController),
2084 PP_ASSERT_WITH_CODE(0 == result,
2085 "Failed to upload dpm data to SMC memory!", return result;);
2087 /* Upload all ulv setting to SMC memory.(dpm level, dpm level count etc) */
2088 result = smu7_copy_bytes_to_smc(hwmgr,
2089 smu_data->smu7_data.ulv_setting_starts,
2090 (uint8_t *)&(smu_data->ulv_setting),
2091 sizeof(SMU71_Discrete_Ulv),
2095 result = iceland_populate_initial_mc_reg_table(hwmgr);
2096 PP_ASSERT_WITH_CODE((0 == result),
2097 "Failed to populate initialize MC Reg table!", return result);
2099 result = iceland_populate_pm_fuses(hwmgr);
2100 PP_ASSERT_WITH_CODE(0 == result,
2101 "Failed to populate PM fuses to SMC memory!", return result);
2106 int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2108 struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
2109 SMU71_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
2111 uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
2112 uint16_t fdo_min, slope1, slope2;
2113 uint32_t reference_clock;
2117 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl))
2120 if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2121 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2122 PHM_PlatformCaps_MicrocodeFanControl);
2126 if (0 == smu7_data->fan_table_start) {
2127 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
2131 duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100);
2134 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
2138 tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
2139 do_div(tmp64, 10000);
2140 fdo_min = (uint16_t)tmp64;
2142 t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
2143 t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
2145 pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
2146 pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
2148 slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
2149 slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
2151 fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
2152 fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
2153 fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
2155 fan_table.Slope1 = cpu_to_be16(slope1);
2156 fan_table.Slope2 = cpu_to_be16(slope2);
2158 fan_table.FdoMin = cpu_to_be16(fdo_min);
2160 fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
2162 fan_table.HystUp = cpu_to_be16(1);
2164 fan_table.HystSlope = cpu_to_be16(1);
2166 fan_table.TempRespLim = cpu_to_be16(5);
2168 reference_clock = smu7_get_xclk(hwmgr);
2170 fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
2172 fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
2174 fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
2176 /* fan_table.FanControl_GL_Flag = 1; */
2178 res = smu7_copy_bytes_to_smc(hwmgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
2184 static int iceland_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2186 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2188 if (data->need_update_smu7_dpm_table &
2189 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
2190 return iceland_program_memory_timing_parameters(hwmgr);
2195 static int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2197 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2198 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
2201 uint32_t low_sclk_interrupt_threshold = 0;
2203 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2204 PHM_PlatformCaps_SclkThrottleLowNotification)
2205 && (data->low_sclk_interrupt_threshold != 0)) {
2206 low_sclk_interrupt_threshold =
2207 data->low_sclk_interrupt_threshold;
2209 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2211 result = smu7_copy_bytes_to_smc(
2213 smu_data->smu7_data.dpm_table_start +
2214 offsetof(SMU71_Discrete_DpmTable,
2215 LowSclkInterruptThreshold),
2216 (uint8_t *)&low_sclk_interrupt_threshold,
2221 result = iceland_update_and_upload_mc_reg_table(hwmgr);
2223 PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result);
2225 result = iceland_program_mem_timing_parameters(hwmgr);
2226 PP_ASSERT_WITH_CODE((result == 0),
2227 "Failed to program memory timing parameters!",
2233 static uint32_t iceland_get_offsetof(uint32_t type, uint32_t member)
2236 case SMU_SoftRegisters:
2238 case HandshakeDisables:
2239 return offsetof(SMU71_SoftRegisters, HandshakeDisables);
2240 case VoltageChangeTimeout:
2241 return offsetof(SMU71_SoftRegisters, VoltageChangeTimeout);
2242 case AverageGraphicsActivity:
2243 return offsetof(SMU71_SoftRegisters, AverageGraphicsActivity);
2245 return offsetof(SMU71_SoftRegisters, PreVBlankGap);
2247 return offsetof(SMU71_SoftRegisters, VBlankTimeout);
2248 case UcodeLoadStatus:
2249 return offsetof(SMU71_SoftRegisters, UcodeLoadStatus);
2250 case DRAM_LOG_ADDR_H:
2251 return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_H);
2252 case DRAM_LOG_ADDR_L:
2253 return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_L);
2254 case DRAM_LOG_PHY_ADDR_H:
2255 return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2256 case DRAM_LOG_PHY_ADDR_L:
2257 return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2258 case DRAM_LOG_BUFF_SIZE:
2259 return offsetof(SMU71_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2261 case SMU_Discrete_DpmTable:
2263 case LowSclkInterruptThreshold:
2264 return offsetof(SMU71_Discrete_DpmTable, LowSclkInterruptThreshold);
2267 pr_warn("can't get the offset of type %x member %x\n", type, member);
2271 static uint32_t iceland_get_mac_definition(uint32_t value)
2274 case SMU_MAX_LEVELS_GRAPHICS:
2275 return SMU71_MAX_LEVELS_GRAPHICS;
2276 case SMU_MAX_LEVELS_MEMORY:
2277 return SMU71_MAX_LEVELS_MEMORY;
2278 case SMU_MAX_LEVELS_LINK:
2279 return SMU71_MAX_LEVELS_LINK;
2280 case SMU_MAX_ENTRIES_SMIO:
2281 return SMU71_MAX_ENTRIES_SMIO;
2282 case SMU_MAX_LEVELS_VDDC:
2283 return SMU71_MAX_LEVELS_VDDC;
2284 case SMU_MAX_LEVELS_VDDCI:
2285 return SMU71_MAX_LEVELS_VDDCI;
2286 case SMU_MAX_LEVELS_MVDD:
2287 return SMU71_MAX_LEVELS_MVDD;
2290 pr_warn("can't get the mac of %x\n", value);
2294 static int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
2296 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2297 struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
2303 result = smu7_read_smc_sram_dword(hwmgr,
2304 SMU71_FIRMWARE_HEADER_LOCATION +
2305 offsetof(SMU71_Firmware_Header, DpmTable),
2309 smu7_data->dpm_table_start = tmp;
2312 error |= (0 != result);
2314 result = smu7_read_smc_sram_dword(hwmgr,
2315 SMU71_FIRMWARE_HEADER_LOCATION +
2316 offsetof(SMU71_Firmware_Header, SoftRegisters),
2320 data->soft_regs_start = tmp;
2321 smu7_data->soft_regs_start = tmp;
2324 error |= (0 != result);
2327 result = smu7_read_smc_sram_dword(hwmgr,
2328 SMU71_FIRMWARE_HEADER_LOCATION +
2329 offsetof(SMU71_Firmware_Header, mcRegisterTable),
2333 smu7_data->mc_reg_table_start = tmp;
2336 result = smu7_read_smc_sram_dword(hwmgr,
2337 SMU71_FIRMWARE_HEADER_LOCATION +
2338 offsetof(SMU71_Firmware_Header, FanTable),
2342 smu7_data->fan_table_start = tmp;
2345 error |= (0 != result);
2347 result = smu7_read_smc_sram_dword(hwmgr,
2348 SMU71_FIRMWARE_HEADER_LOCATION +
2349 offsetof(SMU71_Firmware_Header, mcArbDramTimingTable),
2353 smu7_data->arb_table_start = tmp;
2356 error |= (0 != result);
2359 result = smu7_read_smc_sram_dword(hwmgr,
2360 SMU71_FIRMWARE_HEADER_LOCATION +
2361 offsetof(SMU71_Firmware_Header, Version),
2365 hwmgr->microcode_version_info.SMC = tmp;
2368 error |= (0 != result);
2370 result = smu7_read_smc_sram_dword(hwmgr,
2371 SMU71_FIRMWARE_HEADER_LOCATION +
2372 offsetof(SMU71_Firmware_Header, UlvSettings),
2376 smu7_data->ulv_setting_starts = tmp;
2379 error |= (0 != result);
2381 return error ? 1 : 0;
2384 /*---------------------------MC----------------------------*/
2386 static uint8_t iceland_get_memory_modile_index(struct pp_hwmgr *hwmgr)
2388 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
2391 static bool iceland_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg)
2396 case mmMC_SEQ_RAS_TIMING:
2397 *out_reg = mmMC_SEQ_RAS_TIMING_LP;
2400 case mmMC_SEQ_DLL_STBY:
2401 *out_reg = mmMC_SEQ_DLL_STBY_LP;
2404 case mmMC_SEQ_G5PDX_CMD0:
2405 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
2408 case mmMC_SEQ_G5PDX_CMD1:
2409 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
2412 case mmMC_SEQ_G5PDX_CTRL:
2413 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
2416 case mmMC_SEQ_CAS_TIMING:
2417 *out_reg = mmMC_SEQ_CAS_TIMING_LP;
2420 case mmMC_SEQ_MISC_TIMING:
2421 *out_reg = mmMC_SEQ_MISC_TIMING_LP;
2424 case mmMC_SEQ_MISC_TIMING2:
2425 *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
2428 case mmMC_SEQ_PMG_DVS_CMD:
2429 *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
2432 case mmMC_SEQ_PMG_DVS_CTL:
2433 *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
2436 case mmMC_SEQ_RD_CTL_D0:
2437 *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
2440 case mmMC_SEQ_RD_CTL_D1:
2441 *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
2444 case mmMC_SEQ_WR_CTL_D0:
2445 *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
2448 case mmMC_SEQ_WR_CTL_D1:
2449 *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
2452 case mmMC_PMG_CMD_EMRS:
2453 *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
2456 case mmMC_PMG_CMD_MRS:
2457 *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
2460 case mmMC_PMG_CMD_MRS1:
2461 *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
2464 case mmMC_SEQ_PMG_TIMING:
2465 *out_reg = mmMC_SEQ_PMG_TIMING_LP;
2468 case mmMC_PMG_CMD_MRS2:
2469 *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
2472 case mmMC_SEQ_WR_CTL_2:
2473 *out_reg = mmMC_SEQ_WR_CTL_2_LP;
2484 static int iceland_set_s0_mc_reg_index(struct iceland_mc_reg_table *table)
2489 for (i = 0; i < table->last; i++) {
2490 table->mc_reg_address[i].s0 =
2491 iceland_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
2492 ? address : table->mc_reg_address[i].s1;
2497 static int iceland_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
2498 struct iceland_mc_reg_table *ni_table)
2502 PP_ASSERT_WITH_CODE((table->last <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2503 "Invalid VramInfo table.", return -EINVAL);
2504 PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
2505 "Invalid VramInfo table.", return -EINVAL);
2507 for (i = 0; i < table->last; i++) {
2508 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
2510 ni_table->last = table->last;
2512 for (i = 0; i < table->num_entries; i++) {
2513 ni_table->mc_reg_table_entry[i].mclk_max =
2514 table->mc_reg_table_entry[i].mclk_max;
2515 for (j = 0; j < table->last; j++) {
2516 ni_table->mc_reg_table_entry[i].mc_data[j] =
2517 table->mc_reg_table_entry[i].mc_data[j];
2521 ni_table->num_entries = table->num_entries;
2526 static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr,
2527 struct iceland_mc_reg_table *table)
2531 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2533 for (i = 0, j = table->last; i < table->last; i++) {
2534 PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2535 "Invalid VramInfo table.", return -EINVAL);
2537 switch (table->mc_reg_address[i].s1) {
2539 case mmMC_SEQ_MISC1:
2540 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
2541 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
2542 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
2543 for (k = 0; k < table->num_entries; k++) {
2544 table->mc_reg_table_entry[k].mc_data[j] =
2545 ((temp_reg & 0xffff0000)) |
2546 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
2550 PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2551 "Invalid VramInfo table.", return -EINVAL);
2552 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
2553 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
2554 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
2555 for (k = 0; k < table->num_entries; k++) {
2556 table->mc_reg_table_entry[k].mc_data[j] =
2557 (temp_reg & 0xffff0000) |
2558 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
2560 if (!data->is_memory_gddr5) {
2561 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
2566 if (!data->is_memory_gddr5) {
2567 PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2568 "Invalid VramInfo table.", return -EINVAL);
2569 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
2570 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
2571 for (k = 0; k < table->num_entries; k++) {
2572 table->mc_reg_table_entry[k].mc_data[j] =
2573 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
2580 case mmMC_SEQ_RESERVE_M:
2581 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
2582 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
2583 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
2584 for (k = 0; k < table->num_entries; k++) {
2585 table->mc_reg_table_entry[k].mc_data[j] =
2586 (temp_reg & 0xffff0000) |
2587 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
2603 static int iceland_set_valid_flag(struct iceland_mc_reg_table *table)
2606 for (i = 0; i < table->last; i++) {
2607 for (j = 1; j < table->num_entries; j++) {
2608 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
2609 table->mc_reg_table_entry[j].mc_data[i]) {
2610 table->validflag |= (1<<i);
2619 static int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
2622 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
2623 pp_atomctrl_mc_reg_table *table;
2624 struct iceland_mc_reg_table *ni_table = &smu_data->mc_reg_table;
2625 uint8_t module_index = iceland_get_memory_modile_index(hwmgr);
2627 table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
2632 /* Program additional LP registers that are no longer programmed by VBIOS */
2633 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
2634 cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
2635 cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
2636 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
2637 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
2638 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
2639 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
2640 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
2641 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
2642 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
2643 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
2644 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
2645 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
2646 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
2647 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
2648 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
2649 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
2650 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
2651 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
2652 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
2654 memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
2656 result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
2659 result = iceland_copy_vbios_smc_reg_table(table, ni_table);
2662 iceland_set_s0_mc_reg_index(ni_table);
2663 result = iceland_set_mc_special_registers(hwmgr, ni_table);
2667 iceland_set_valid_flag(ni_table);
2674 static bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr)
2676 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
2677 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
2681 const struct pp_smumgr_func iceland_smu_funcs = {
2682 .smu_init = &iceland_smu_init,
2683 .smu_fini = &smu7_smu_fini,
2684 .start_smu = &iceland_start_smu,
2685 .check_fw_load_finish = &smu7_check_fw_load_finish,
2686 .request_smu_load_fw = &smu7_reload_firmware,
2687 .request_smu_load_specific_fw = &iceland_request_smu_load_specific_fw,
2688 .send_msg_to_smc = &smu7_send_msg_to_smc,
2689 .send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
2690 .download_pptable_settings = NULL,
2691 .upload_pptable_settings = NULL,
2692 .get_offsetof = iceland_get_offsetof,
2693 .process_firmware_header = iceland_process_firmware_header,
2694 .init_smc_table = iceland_init_smc_table,
2695 .update_sclk_threshold = iceland_update_sclk_threshold,
2696 .thermal_setup_fan_table = iceland_thermal_setup_fan_table,
2697 .populate_all_graphic_levels = iceland_populate_all_graphic_levels,
2698 .populate_all_memory_levels = iceland_populate_all_memory_levels,
2699 .get_mac_definition = iceland_get_mac_definition,
2700 .initialize_mc_reg_table = iceland_initialize_mc_reg_table,
2701 .is_dpm_running = iceland_is_dpm_running,