drivers/gpu/drm/amd/powerplay/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26
  27 #include "pp_debug.h"
  28 #include "amdgpu.h"
  29 #include "amdgpu_smu.h"
  30 #include "atomfirmware.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "smu_v11_0.h"
  33 #include "soc15_common.h"
  34 #include "atom.h"
  35 #include "vega20_ppt.h"
  36 #include "navi10_ppt.h"
  37
  38 #include "asic_reg/thm/thm_11_0_2_offset.h"
  39 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  40 #include "asic_reg/mp/mp_11_0_offset.h"
  41 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  42 #include "asic_reg/nbio/nbio_7_4_offset.h"
  43 #include "asic_reg/nbio/nbio_7_4_sh_mask.h"
  44 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  45 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  46
  47 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
  48 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  49
  50 #define SMU11_VOLTAGE_SCALE 4
  51
  52 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
  53                                               uint16_t msg)
  54 {
  55         struct amdgpu_device *adev = smu->adev;
  56         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  57         return 0;
  58 }
  59
  60 static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
  61 {
  62         struct amdgpu_device *adev = smu->adev;
  63
  64         *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  65         return 0;
  66 }
  67
  68 static int smu_v11_0_wait_for_response(struct smu_context *smu)
  69 {
  70         struct amdgpu_device *adev = smu->adev;
  71         uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
  72
  73         for (i = 0; i < timeout; i++) {
  74                 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  75                 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
  76                         break;
  77                 udelay(1);
  78         }
  79
  80         /* timeout means wrong logic */
  81         if (i == timeout)
  82                 return -ETIME;
  83
  84         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
  85 }
  86
  87 static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
  88 {
  89         struct amdgpu_device *adev = smu->adev;
  90         int ret = 0, index = 0;
  91
  92         index = smu_msg_get_index(smu, msg);
  93         if (index < 0)
  94                 return index;
  95
  96         smu_v11_0_wait_for_response(smu);
  97
  98         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
  99
 100         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 101
 102         ret = smu_v11_0_wait_for_response(smu);
 103
 104         if (ret)
 105                 pr_err("Failed to send message 0x%x, response 0x%x\n", index,
 106                        ret);
 107
 108         return ret;
 109
 110 }
 111
 112 static int
 113 smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
 114                               uint32_t param)
 115 {
 116
 117         struct amdgpu_device *adev = smu->adev;
 118         int ret = 0, index = 0;
 119
 120         index = smu_msg_get_index(smu, msg);
 121         if (index < 0)
 122                 return index;
 123
 124         ret = smu_v11_0_wait_for_response(smu);
 125         if (ret)
 126                 pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
 127                        index, ret, param);
 128
 129         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 130
 131         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
 132
 133         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 134
 135         ret = smu_v11_0_wait_for_response(smu);
 136         if (ret)
 137                 pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
 138                        index, ret, param);
 139
 140         return ret;
 141 }
 142
 143 static int smu_v11_0_init_microcode(struct smu_context *smu)
 144 {
 145         struct amdgpu_device *adev = smu->adev;
 146         const char *chip_name;
 147         char fw_name[30];
 148         int err = 0;
 149         const struct smc_firmware_header_v1_0 *hdr;
 150         const struct common_firmware_header *header;
 151         struct amdgpu_firmware_info *ucode = NULL;
 152
 153         switch (adev->asic_type) {
 154         case CHIP_VEGA20:
 155                 chip_name = "vega20";
 156                 break;
 157         case CHIP_NAVI10:
 158                 chip_name = "navi10";
 159                 break;
 160         default:
 161                 BUG();
 162         }
 163
 164         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 165
 166         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 167         if (err)
 168                 goto out;
 169         err = amdgpu_ucode_validate(adev->pm.fw);
 170         if (err)
 171                 goto out;
 172
 173         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 174         amdgpu_ucode_print_smc_hdr(&hdr->header);
 175         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 176
 177         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 178                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 179                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 180                 ucode->fw = adev->pm.fw;
 181                 header = (const struct common_firmware_header *)ucode->fw->data;
 182                 adev->firmware.fw_size +=
 183                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 184         }
 185
 186 out:
 187         if (err) {
 188                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 189                           fw_name);
 190                 release_firmware(adev->pm.fw);
 191                 adev->pm.fw = NULL;
 192         }
 193         return err;
 194 }
 195
 196 static int smu_v11_0_load_microcode(struct smu_context *smu)
 197 {
 198         struct amdgpu_device *adev = smu->adev;
 199         const uint32_t *src;
 200         const struct smc_firmware_header_v1_0 *hdr;
 201         uint32_t addr_start = MP1_SRAM;
 202         uint32_t i;
 203         uint32_t mp1_fw_flags;
 204
 205         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 206         src = (const uint32_t *)(adev->pm.fw->data +
 207                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 208
 209         for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
 210                 WREG32_PCIE(addr_start, src[i]);
 211                 addr_start += 4;
 212         }
 213
 214         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 215                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 216         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 217                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 218
 219         for (i = 0; i < adev->usec_timeout; i++) {
 220                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 221                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 222                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 223                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 224                         break;
 225                 udelay(1);
 226         }
 227
 228         if (i == adev->usec_timeout)
 229                 return -ETIME;
 230
 231         return 0;
 232 }
 233
 234 static int smu_v11_0_check_fw_status(struct smu_context *smu)
 235 {
 236         struct amdgpu_device *adev = smu->adev;
 237         uint32_t mp1_fw_flags;
 238
 239         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 240                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 241
 242         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 243             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 244                 return 0;
 245
 246         return -EIO;
 247 }
 248
 249 static int smu_v11_0_check_fw_version(struct smu_context *smu)
 250 {
 251         uint32_t if_version = 0xff, smu_version = 0xff;
 252         uint16_t smu_major;
 253         uint8_t smu_minor, smu_debug;
 254         int ret = 0;
 255
 256         ret = smu_get_smc_version(smu, &if_version, &smu_version);
 257         if (ret)
 258                 return ret;
 259
 260         smu_major = (smu_version >> 16) & 0xffff;
 261         smu_minor = (smu_version >> 8) & 0xff;
 262         smu_debug = (smu_version >> 0) & 0xff;
 263
 264         /*
 265          * 1. if_version mismatch is not critical as our fw is designed
 266          * to be backward compatible.
 267          * 2. New fw usually brings some optimizations. But that's visible
 268          * only on the paired driver.
 269          * Considering above, we just leave user a warning message instead
 270          * of halt driver loading.
 271          */
 272         if (if_version != smu->smc_if_version) {
 273                 pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 274                         "smu fw version = 0x%08x (%d.%d.%d)\n",
 275                         smu->smc_if_version, if_version,
 276                         smu_version, smu_major, smu_minor, smu_debug);
 277                 pr_warn("SMU driver if version not matched\n");
 278         }
 279
 280         return ret;
 281 }
 282
 283 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 284 {
 285         struct amdgpu_device *adev = smu->adev;
 286         uint32_t ppt_offset_bytes;
 287         const struct smc_firmware_header_v2_0 *v2;
 288
 289         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 290
 291         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 292         *size = le32_to_cpu(v2->ppt_size_bytes);
 293         *table = (uint8_t *)v2 + ppt_offset_bytes;
 294
 295         return 0;
 296 }
 297
 298 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table, uint32_t *size, uint32_t pptable_id)
 299 {
 300         struct amdgpu_device *adev = smu->adev;
 301         const struct smc_firmware_header_v2_1 *v2_1;
 302         struct smc_soft_pptable_entry *entries;
 303         uint32_t pptable_count = 0;
 304         int i = 0;
 305
 306         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 307         entries = (struct smc_soft_pptable_entry *)
 308                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 309         pptable_count = le32_to_cpu(v2_1->pptable_count);
 310         for (i = 0; i < pptable_count; i++) {
 311                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 312                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 313                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 314                         break;
 315                 }
 316         }
 317
 318         if (i == pptable_count)
 319                 return -EINVAL;
 320
 321         return 0;
 322 }
 323
 324 static int smu_v11_0_setup_pptable(struct smu_context *smu)
 325 {
 326         struct amdgpu_device *adev = smu->adev;
 327         const struct smc_firmware_header_v1_0 *hdr;
 328         int ret, index;
 329         uint32_t size;
 330         uint8_t frev, crev;
 331         void *table;
 332         uint16_t version_major, version_minor;
 333
 334         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 335         version_major = le16_to_cpu(hdr->header.header_version_major);
 336         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 337         if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 338                 switch (version_minor) {
 339                 case 0:
 340                         ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 341                         break;
 342                 case 1:
 343                         ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 344                                                          smu->smu_table.boot_values.pp_table_id);
 345                         break;
 346                 default:
 347                         ret = -EINVAL;
 348                         break;
 349                 }
 350                 if (ret)
 351                         return ret;
 352
 353         } else {
 354                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 355                                                     powerplayinfo);
 356
 357                 ret = smu_get_atom_data_table(smu, index, (uint16_t *)&size, &frev, &crev,
 358                                               (uint8_t **)&table);
 359                 if (ret)
 360                         return ret;
 361         }
 362
 363         if (!smu->smu_table.power_play_table)
 364                 smu->smu_table.power_play_table = table;
 365         if (!smu->smu_table.power_play_table_size)
 366                 smu->smu_table.power_play_table_size = size;
 367
 368         return 0;
 369 }
 370
 371 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
 372 {
 373         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 374
 375         if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
 376                 return -EINVAL;
 377
 378         return smu_alloc_dpm_context(smu);
 379 }
 380
 381 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
 382 {
 383         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 384
 385         if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
 386                 return -EINVAL;
 387
 388         kfree(smu_dpm->dpm_context);
 389         kfree(smu_dpm->golden_dpm_context);
 390         kfree(smu_dpm->dpm_current_power_state);
 391         kfree(smu_dpm->dpm_request_power_state);
 392         smu_dpm->dpm_context = NULL;
 393         smu_dpm->golden_dpm_context = NULL;
 394         smu_dpm->dpm_context_size = 0;
 395         smu_dpm->dpm_current_power_state = NULL;
 396         smu_dpm->dpm_request_power_state = NULL;
 397
 398         return 0;
 399 }
 400
 401 static int smu_v11_0_init_smc_tables(struct smu_context *smu)
 402 {
 403         struct smu_table_context *smu_table = &smu->smu_table;
 404         struct smu_table *tables = NULL;
 405         int ret = 0;
 406
 407         if (smu_table->tables || smu_table->table_count == 0)
 408                 return -EINVAL;
 409
 410         tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
 411                          GFP_KERNEL);
 412         if (!tables)
 413                 return -ENOMEM;
 414
 415         smu_table->tables = tables;
 416
 417         ret = smu_tables_init(smu, tables);
 418         if (ret)
 419                 return ret;
 420
 421         ret = smu_v11_0_init_dpm_context(smu);
 422         if (ret)
 423                 return ret;
 424
 425         return 0;
 426 }
 427
 428 static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 429 {
 430         struct smu_table_context *smu_table = &smu->smu_table;
 431         int ret = 0;
 432
 433         if (!smu_table->tables || smu_table->table_count == 0)
 434                 return -EINVAL;
 435
 436         kfree(smu_table->tables);
 437         kfree(smu_table->metrics_table);
 438         smu_table->tables = NULL;
 439         smu_table->table_count = 0;
 440         smu_table->metrics_table = NULL;
 441         smu_table->metrics_time = 0;
 442
 443         ret = smu_v11_0_fini_dpm_context(smu);
 444         if (ret)
 445                 return ret;
 446         return 0;
 447 }
 448
 449 static int smu_v11_0_init_power(struct smu_context *smu)
 450 {
 451         struct smu_power_context *smu_power = &smu->smu_power;
 452
 453         if (!smu->pm_enabled)
 454                 return 0;
 455         if (smu_power->power_context || smu_power->power_context_size != 0)
 456                 return -EINVAL;
 457
 458         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 459                                            GFP_KERNEL);
 460         if (!smu_power->power_context)
 461                 return -ENOMEM;
 462         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 463
 464         return 0;
 465 }
 466
 467 static int smu_v11_0_fini_power(struct smu_context *smu)
 468 {
 469         struct smu_power_context *smu_power = &smu->smu_power;
 470
 471         if (!smu->pm_enabled)
 472                 return 0;
 473         if (!smu_power->power_context || smu_power->power_context_size == 0)
 474                 return -EINVAL;
 475
 476         kfree(smu_power->power_context);
 477         smu_power->power_context = NULL;
 478         smu_power->power_context_size = 0;
 479
 480         return 0;
 481 }
 482
 483 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 484 {
 485         int ret, index;
 486         uint16_t size;
 487         uint8_t frev, crev;
 488         struct atom_common_table_header *header;
 489         struct atom_firmware_info_v3_3 *v_3_3;
 490         struct atom_firmware_info_v3_1 *v_3_1;
 491
 492         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 493                                             firmwareinfo);
 494
 495         ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
 496                                       (uint8_t **)&header);
 497         if (ret)
 498                 return ret;
 499
 500         if (header->format_revision != 3) {
 501                 pr_err("unknown atom_firmware_info version! for smu11\n");
 502                 return -EINVAL;
 503         }
 504
 505         switch (header->content_revision) {
 506         case 0:
 507         case 1:
 508         case 2:
 509                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 510                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 511                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 512                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 513                 smu->smu_table.boot_values.socclk = 0;
 514                 smu->smu_table.boot_values.dcefclk = 0;
 515                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 516                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 517                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 518                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 519                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 520                 smu->smu_table.boot_values.pp_table_id = 0;
 521                 break;
 522         case 3:
 523         default:
 524                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 525                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 526                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 527                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 528                 smu->smu_table.boot_values.socclk = 0;
 529                 smu->smu_table.boot_values.dcefclk = 0;
 530                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 531                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 532                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 533                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 534                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 535                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 536         }
 537
 538         return 0;
 539 }
 540
 541 static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 542 {
 543         int ret, index;
 544         struct amdgpu_device *adev = smu->adev;
 545         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 546         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 547
 548         input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
 549         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 550         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 551                                             getsmuclockinfo);
 552
 553         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 554                                         (uint32_t *)&input);
 555         if (ret)
 556                 return -EINVAL;
 557
 558         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 559         smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 560
 561         memset(&input, 0, sizeof(input));
 562         input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
 563         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 564         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 565                                             getsmuclockinfo);
 566
 567         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 568                                         (uint32_t *)&input);
 569         if (ret)
 570                 return -EINVAL;
 571
 572         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 573         smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 574
 575         memset(&input, 0, sizeof(input));
 576         input.clk_id = SMU11_SYSPLL0_ECLK_ID;
 577         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 578         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 579                                             getsmuclockinfo);
 580
 581         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 582                                         (uint32_t *)&input);
 583         if (ret)
 584                 return -EINVAL;
 585
 586         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 587         smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 588
 589         memset(&input, 0, sizeof(input));
 590         input.clk_id = SMU11_SYSPLL0_VCLK_ID;
 591         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 592         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 593                                             getsmuclockinfo);
 594
 595         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 596                                         (uint32_t *)&input);
 597         if (ret)
 598                 return -EINVAL;
 599
 600         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 601         smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 602
 603         memset(&input, 0, sizeof(input));
 604         input.clk_id = SMU11_SYSPLL0_DCLK_ID;
 605         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 606         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 607                                             getsmuclockinfo);
 608
 609         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 610                                         (uint32_t *)&input);
 611         if (ret)
 612                 return -EINVAL;
 613
 614         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 615         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 616
 617         return 0;
 618 }
 619
 620 static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 621 {
 622         struct smu_table_context *smu_table = &smu->smu_table;
 623         struct smu_table *memory_pool = &smu_table->memory_pool;
 624         int ret = 0;
 625         uint64_t address;
 626         uint32_t address_low, address_high;
 627
 628         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 629                 return ret;
 630
 631         address = (uintptr_t)memory_pool->cpu_addr;
 632         address_high = (uint32_t)upper_32_bits(address);
 633         address_low  = (uint32_t)lower_32_bits(address);
 634
 635         ret = smu_send_smc_msg_with_param(smu,
 636                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 637                                           address_high);
 638         if (ret)
 639                 return ret;
 640         ret = smu_send_smc_msg_with_param(smu,
 641                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 642                                           address_low);
 643         if (ret)
 644                 return ret;
 645
 646         address = memory_pool->mc_address;
 647         address_high = (uint32_t)upper_32_bits(address);
 648         address_low  = (uint32_t)lower_32_bits(address);
 649
 650         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 651                                           address_high);
 652         if (ret)
 653                 return ret;
 654         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 655                                           address_low);
 656         if (ret)
 657                 return ret;
 658         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 659                                           (uint32_t)memory_pool->size);
 660         if (ret)
 661                 return ret;
 662
 663         return ret;
 664 }
 665
 666 static int smu_v11_0_check_pptable(struct smu_context *smu)
 667 {
 668         int ret;
 669
 670         ret = smu_check_powerplay_table(smu);
 671         return ret;
 672 }
 673
 674 static int smu_v11_0_parse_pptable(struct smu_context *smu)
 675 {
 676         int ret;
 677
 678         struct smu_table_context *table_context = &smu->smu_table;
 679         struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
 680
 681         if (table_context->driver_pptable)
 682                 return -EINVAL;
 683
 684         table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
 685
 686         if (!table_context->driver_pptable)
 687                 return -ENOMEM;
 688
 689         ret = smu_store_powerplay_table(smu);
 690         if (ret)
 691                 return -EINVAL;
 692
 693         ret = smu_append_powerplay_table(smu);
 694
 695         return ret;
 696 }
 697
 698 static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
 699 {
 700         int ret;
 701
 702         ret = smu_set_default_dpm_table(smu);
 703
 704         return ret;
 705 }
 706
 707 static int smu_v11_0_write_pptable(struct smu_context *smu)
 708 {
 709         struct smu_table_context *table_context = &smu->smu_table;
 710         int ret = 0;
 711
 712         ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0,
 713                                table_context->driver_pptable, true);
 714
 715         return ret;
 716 }
 717
 718 static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
 719 {
 720         int ret = 0;
 721         struct smu_table_context *smu_table = &smu->smu_table;
 722         struct smu_table *table = NULL;
 723
 724         table = &smu_table->tables[SMU_TABLE_WATERMARKS];
 725         if (!table)
 726                 return -EINVAL;
 727
 728         if (!table->cpu_addr)
 729                 return -EINVAL;
 730
 731         ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
 732                                 true);
 733
 734         return ret;
 735 }
 736
 737 static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 738 {
 739         int ret;
 740
 741         ret = smu_send_smc_msg_with_param(smu,
 742                                           SMU_MSG_SetMinDeepSleepDcefclk, clk);
 743         if (ret)
 744                 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
 745
 746         return ret;
 747 }
 748
 749 static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
 750 {
 751         struct smu_table_context *table_context = &smu->smu_table;
 752
 753         if (!smu->pm_enabled)
 754                 return 0;
 755         if (!table_context)
 756                 return -EINVAL;
 757
 758         return smu_set_deep_sleep_dcefclk(smu,
 759                                           table_context->boot_values.dcefclk / 100);
 760 }
 761
 762 static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 763 {
 764         int ret = 0;
 765         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 766
 767         if (tool_table->mc_address) {
 768                 ret = smu_send_smc_msg_with_param(smu,
 769                                 SMU_MSG_SetToolsDramAddrHigh,
 770                                 upper_32_bits(tool_table->mc_address));
 771                 if (!ret)
 772                         ret = smu_send_smc_msg_with_param(smu,
 773                                 SMU_MSG_SetToolsDramAddrLow,
 774                                 lower_32_bits(tool_table->mc_address));
 775         }
 776
 777         return ret;
 778 }
 779
 780 static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 781 {
 782         int ret = 0;
 783
 784         if (!smu->pm_enabled)
 785                 return ret;
 786
 787         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count);
 788         return ret;
 789 }
 790
 791 static int smu_v11_0_update_feature_enable_state(struct smu_context *smu, uint32_t feature_id, bool enabled)
 792 {
 793         uint32_t feature_low = 0, feature_high = 0;
 794         int ret = 0;
 795
 796         if (!smu->pm_enabled)
 797                 return ret;
 798         if (feature_id >= 0 && feature_id < 31)
 799                 feature_low = (1 << feature_id);
 800         else if (feature_id > 31 && feature_id < 63)
 801                 feature_high = (1 << feature_id);
 802         else
 803                 return -EINVAL;
 804
 805         if (enabled) {
 806                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
 807                                                   feature_low);
 808                 if (ret)
 809                         return ret;
 810                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
 811                                                   feature_high);
 812                 if (ret)
 813                         return ret;
 814
 815         } else {
 816                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
 817                                                   feature_low);
 818                 if (ret)
 819                         return ret;
 820                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
 821                                                   feature_high);
 822                 if (ret)
 823                         return ret;
 824
 825         }
 826
 827         return ret;
 828 }
 829
 830 static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 831 {
 832         struct smu_feature *feature = &smu->smu_feature;
 833         int ret = 0;
 834         uint32_t feature_mask[2];
 835
 836         mutex_lock(&feature->mutex);
 837         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 838                 goto failed;
 839
 840         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 841
 842         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 843                                           feature_mask[1]);
 844         if (ret)
 845                 goto failed;
 846
 847         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 848                                           feature_mask[0]);
 849         if (ret)
 850                 goto failed;
 851
 852 failed:
 853         mutex_unlock(&feature->mutex);
 854         return ret;
 855 }
 856
 857 static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 858                                       uint32_t *feature_mask, uint32_t num)
 859 {
 860         uint32_t feature_mask_high = 0, feature_mask_low = 0;
 861         int ret = 0;
 862
 863         if (!feature_mask || num < 2)
 864                 return -EINVAL;
 865
 866         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
 867         if (ret)
 868                 return ret;
 869         ret = smu_read_smc_arg(smu, &feature_mask_high);
 870         if (ret)
 871                 return ret;
 872
 873         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
 874         if (ret)
 875                 return ret;
 876         ret = smu_read_smc_arg(smu, &feature_mask_low);
 877         if (ret)
 878                 return ret;
 879
 880         feature_mask[0] = feature_mask_low;
 881         feature_mask[1] = feature_mask_high;
 882
 883         return ret;
 884 }
 885
 886 static int smu_v11_0_system_features_control(struct smu_context *smu,
 887                                              bool en)
 888 {
 889         struct smu_feature *feature = &smu->smu_feature;
 890         uint32_t feature_mask[2];
 891         int ret = 0;
 892
 893         if (smu->pm_enabled) {
 894                 ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 895                                              SMU_MSG_DisableAllSmuFeatures));
 896                 if (ret)
 897                         return ret;
 898         }
 899
 900         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 901         if (ret)
 902                 return ret;
 903
 904         bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 905                     feature->feature_num);
 906         bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 907                     feature->feature_num);
 908
 909         return ret;
 910 }
 911
 912 static int smu_v11_0_notify_display_change(struct smu_context *smu)
 913 {
 914         int ret = 0;
 915
 916         if (!smu->pm_enabled)
 917                 return ret;
 918         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 919             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 920                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
 921
 922         return ret;
 923 }
 924
 925 static int
 926 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 927                                     enum smu_clk_type clock_select)
 928 {
 929         int ret = 0;
 930
 931         if (!smu->pm_enabled)
 932                 return ret;
 933         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 934                                           smu_clk_get_index(smu, clock_select) << 16);
 935         if (ret) {
 936                 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 937                 return ret;
 938         }
 939
 940         ret = smu_read_smc_arg(smu, clock);
 941         if (ret)
 942                 return ret;
 943
 944         if (*clock != 0)
 945                 return 0;
 946
 947         /* if DC limit is zero, return AC limit */
 948         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 949                                           smu_clk_get_index(smu, clock_select) << 16);
 950         if (ret) {
 951                 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 952                 return ret;
 953         }
 954
 955         ret = smu_read_smc_arg(smu, clock);
 956
 957         return ret;
 958 }
 959
 960 static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 961 {
 962         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 963         int ret = 0;
 964
 965         max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
 966                                          GFP_KERNEL);
 967         smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 968
 969         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 970         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 971         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 972         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 973         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 974         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 975
 976         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 977                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 978                                                           &(max_sustainable_clocks->uclock),
 979                                                           SMU_UCLK);
 980                 if (ret) {
 981                         pr_err("[%s] failed to get max UCLK from SMC!",
 982                                __func__);
 983                         return ret;
 984                 }
 985         }
 986
 987         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 988                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 989                                                           &(max_sustainable_clocks->soc_clock),
 990                                                           SMU_SOCCLK);
 991                 if (ret) {
 992                         pr_err("[%s] failed to get max SOCCLK from SMC!",
 993                                __func__);
 994                         return ret;
 995                 }
 996         }
 997
 998         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 999                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1000                                                           &(max_sustainable_clocks->dcef_clock),
1001                                                           SMU_DCEFCLK);
1002                 if (ret) {
1003                         pr_err("[%s] failed to get max DCEFCLK from SMC!",
1004                                __func__);
1005                         return ret;
1006                 }
1007
1008                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1009                                                           &(max_sustainable_clocks->display_clock),
1010                                                           SMU_DISPCLK);
1011                 if (ret) {
1012                         pr_err("[%s] failed to get max DISPCLK from SMC!",
1013                                __func__);
1014                         return ret;
1015                 }
1016                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1017                                                           &(max_sustainable_clocks->phy_clock),
1018                                                           SMU_PHYCLK);
1019                 if (ret) {
1020                         pr_err("[%s] failed to get max PHYCLK from SMC!",
1021                                __func__);
1022                         return ret;
1023                 }
1024                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1025                                                           &(max_sustainable_clocks->pixel_clock),
1026                                                           SMU_PIXCLK);
1027                 if (ret) {
1028                         pr_err("[%s] failed to get max PIXCLK from SMC!",
1029                                __func__);
1030                         return ret;
1031                 }
1032         }
1033
1034         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1035                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1036
1037         return 0;
1038 }
1039
1040 static int smu_v11_0_get_power_limit(struct smu_context *smu,
1041                                      uint32_t *limit,
1042                                      bool get_default)
1043 {
1044         int ret = 0;
1045
1046         if (get_default) {
1047                 mutex_lock(&smu->mutex);
1048                 *limit = smu->default_power_limit;
1049                 if (smu->od_enabled) {
1050                         *limit *= (100 + smu->smu_table.TDPODLimit);
1051                         *limit /= 100;
1052                 }
1053                 mutex_unlock(&smu->mutex);
1054         } else {
1055                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1056                         smu_power_get_index(smu, SMU_POWER_SOURCE_AC) << 16);
1057                 if (ret) {
1058                         pr_err("[%s] get PPT limit failed!", __func__);
1059                         return ret;
1060                 }
1061                 smu_read_smc_arg(smu, limit);
1062                 smu->power_limit = *limit;
1063         }
1064
1065         return ret;
1066 }
1067
1068 static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1069 {
1070         uint32_t max_power_limit;
1071         int ret = 0;
1072
1073         if (n == 0)
1074                 n = smu->default_power_limit;
1075
1076         max_power_limit = smu->default_power_limit;
1077
1078         if (smu->od_enabled) {
1079                 max_power_limit *= (100 + smu->smu_table.TDPODLimit);
1080                 max_power_limit /= 100;
1081         }
1082
1083         if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1084                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1085         if (ret) {
1086                 pr_err("[%s] Set power limit Failed!", __func__);
1087                 return ret;
1088         }
1089
1090         return ret;
1091 }
1092
1093 static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1094                                           enum smu_clk_type clk_id,
1095                                           uint32_t *value)
1096 {
1097         int ret = 0;
1098         uint32_t freq = 0;
1099
1100         if (clk_id >= SMU_CLK_COUNT || !value)
1101                 return -EINVAL;
1102
1103         /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
1104         if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) == 0)
1105                 ret =  smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
1106         else {
1107                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1108                                                   (smu_clk_get_index(smu, clk_id) << 16));
1109                 if (ret)
1110                         return ret;
1111
1112                 ret = smu_read_smc_arg(smu, &freq);
1113                 if (ret)
1114                         return ret;
1115         }
1116
1117         freq *= 100;
1118         *value = freq;
1119
1120         return ret;
1121 }
1122
1123 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1124                                        struct smu_temperature_range *range)
1125 {
1126         struct amdgpu_device *adev = smu->adev;
1127         int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
1128         int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
1129         uint32_t val;
1130
1131         if (!range)
1132                 return -EINVAL;
1133
1134         if (low < range->min)
1135                 low = range->min;
1136         if (high > range->max)
1137                 high = range->max;
1138
1139         low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, range->min);
1140         high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, range->max);
1141
1142         if (low > high)
1143                 return -EINVAL;
1144
1145         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1146         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1147         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1148         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1149         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1150         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1151         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1152         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1153
1154         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1155
1156         return 0;
1157 }
1158
1159 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1160 {
1161         struct amdgpu_device *adev = smu->adev;
1162         uint32_t val = 0;
1163
1164         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1165         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1166         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1167
1168         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1169
1170         return 0;
1171 }
1172
1173 static int smu_v11_0_start_thermal_control(struct smu_context *smu)
1174 {
1175         int ret = 0;
1176         struct smu_temperature_range range = {
1177                 TEMP_RANGE_MIN,
1178                 TEMP_RANGE_MAX,
1179                 TEMP_RANGE_MAX,
1180                 TEMP_RANGE_MIN,
1181                 TEMP_RANGE_MAX,
1182                 TEMP_RANGE_MAX,
1183                 TEMP_RANGE_MIN,
1184                 TEMP_RANGE_MAX,
1185                 TEMP_RANGE_MAX};
1186         struct amdgpu_device *adev = smu->adev;
1187
1188         if (!smu->pm_enabled)
1189                 return ret;
1190
1191         ret = smu_get_thermal_temperature_range(smu, &range);
1192         if (ret)
1193                 return ret;
1194
1195         if (smu->smu_table.thermal_controller_type) {
1196                 ret = smu_v11_0_set_thermal_range(smu, &range);
1197                 if (ret)
1198                         return ret;
1199
1200                 ret = smu_v11_0_enable_thermal_alert(smu);
1201                 if (ret)
1202                         return ret;
1203
1204                 ret = smu_set_thermal_fan_table(smu);
1205                 if (ret)
1206                         return ret;
1207         }
1208
1209         adev->pm.dpm.thermal.min_temp = range.min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1210         adev->pm.dpm.thermal.max_temp = range.max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1211         adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1212         adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1213         adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1214         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1215         adev->pm.dpm.thermal.min_mem_temp = range.mem_min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1216         adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1217         adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1218         adev->pm.dpm.thermal.min_temp = range.min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1219         adev->pm.dpm.thermal.max_temp = range.max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1220
1221         return ret;
1222 }
1223
1224 static uint16_t convert_to_vddc(uint8_t vid)
1225 {
1226         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1227 }
1228
1229 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1230 {
1231         struct amdgpu_device *adev = smu->adev;
1232         uint32_t vdd = 0, val_vid = 0;
1233
1234         if (!value)
1235                 return -EINVAL;
1236         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1237                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1238                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1239
1240         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1241
1242         *value = vdd;
1243
1244         return 0;
1245
1246 }
1247
1248 static int smu_v11_0_read_sensor(struct smu_context *smu,
1249                                  enum amd_pp_sensors sensor,
1250                                  void *data, uint32_t *size)
1251 {
1252         int ret = 0;
1253         switch (sensor) {
1254         case AMDGPU_PP_SENSOR_GFX_MCLK:
1255                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1256                 *size = 4;
1257                 break;
1258         case AMDGPU_PP_SENSOR_GFX_SCLK:
1259                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1260                 *size = 4;
1261                 break;
1262         case AMDGPU_PP_SENSOR_VDDGFX:
1263                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1264                 *size = 4;
1265                 break;
1266         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1267                 *(uint32_t *)data = 0;
1268                 *size = 4;
1269                 break;
1270         default:
1271                 ret = smu_common_read_sensor(smu, sensor, data, size);
1272                 break;
1273         }
1274
1275         /* try get sensor data by asic */
1276         if (ret)
1277                 ret = smu_asic_read_sensor(smu, sensor, data, size);
1278
1279         if (ret)
1280                 *size = 0;
1281
1282         return ret;
1283 }
1284
1285 static int
1286 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1287                                         struct pp_display_clock_request
1288                                         *clock_req)
1289 {
1290         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1291         int ret = 0;
1292         enum smu_clk_type clk_select = 0;
1293         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1294
1295         if (!smu->pm_enabled)
1296                 return -EINVAL;
1297
1298         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1299                 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1300                 switch (clk_type) {
1301                 case amd_pp_dcef_clock:
1302                         clk_select = SMU_DCEFCLK;
1303                         break;
1304                 case amd_pp_disp_clock:
1305                         clk_select = SMU_DISPCLK;
1306                         break;
1307                 case amd_pp_pixel_clock:
1308                         clk_select = SMU_PIXCLK;
1309                         break;
1310                 case amd_pp_phy_clock:
1311                         clk_select = SMU_PHYCLK;
1312                         break;
1313                 case amd_pp_mem_clock:
1314                         clk_select = SMU_UCLK;
1315                         break;
1316                 default:
1317                         pr_info("[%s] Invalid Clock Type!", __func__);
1318                         ret = -EINVAL;
1319                         break;
1320                 }
1321
1322                 if (ret)
1323                         goto failed;
1324
1325                 mutex_lock(&smu->mutex);
1326                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1327                         (smu_clk_get_index(smu, clk_select) << 16) | clk_freq);
1328                 mutex_unlock(&smu->mutex);
1329         }
1330
1331 failed:
1332         return ret;
1333 }
1334
1335 static int
1336 smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
1337                                           dm_pp_wm_sets_with_clock_ranges_soc15
1338                                           *clock_ranges)
1339 {
1340         int ret = 0;
1341         struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
1342         void *table = watermarks->cpu_addr;
1343
1344         if (!smu->disable_watermark &&
1345             smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1346             smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1347                 smu_set_watermarks_table(smu, table, clock_ranges);
1348                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1349                 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1350         }
1351
1352         return ret;
1353 }
1354
1355 static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1356 {
1357         int ret = 0;
1358         struct amdgpu_device *adev = smu->adev;
1359
1360         switch (adev->asic_type) {
1361         case CHIP_VEGA20:
1362                 break;
1363         case CHIP_NAVI10:
1364                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1365                         return 0;
1366                 mutex_lock(&smu->mutex);
1367                 if (enable)
1368                         ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
1369                 else
1370                         ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
1371                 mutex_unlock(&smu->mutex);
1372                 break;
1373         default:
1374                 break;
1375         }
1376
1377         return ret;
1378 }
1379
1380 static uint32_t
1381 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1382 {
1383         if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1384                 return AMD_FAN_CTRL_MANUAL;
1385         else
1386                 return AMD_FAN_CTRL_AUTO;
1387 }
1388
1389 static int
1390 smu_v11_0_smc_fan_control(struct smu_context *smu, bool start)
1391 {
1392         int ret = 0;
1393
1394         if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1395                 return 0;
1396
1397         ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start);
1398         if (ret)
1399                 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1400                        __func__, (start ? "Start" : "Stop"));
1401
1402         return ret;
1403 }
1404
1405 static int
1406 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1407 {
1408         struct amdgpu_device *adev = smu->adev;
1409
1410         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1411                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1412                                    CG_FDO_CTRL2, TMIN, 0));
1413         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1414                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1415                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1416
1417         return 0;
1418 }
1419
1420 static int
1421 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1422 {
1423         struct amdgpu_device *adev = smu->adev;
1424         uint32_t duty100;
1425         uint32_t duty;
1426         uint64_t tmp64;
1427         bool stop = 0;
1428
1429         if (speed > 100)
1430                 speed = 100;
1431
1432         if (smu_v11_0_smc_fan_control(smu, stop))
1433                 return -EINVAL;
1434         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1435                                 CG_FDO_CTRL1, FMAX_DUTY100);
1436         if (!duty100)
1437                 return -EINVAL;
1438
1439         tmp64 = (uint64_t)speed * duty100;
1440         do_div(tmp64, 100);
1441         duty = (uint32_t)tmp64;
1442
1443         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1444                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1445                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1446
1447         return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1448 }
1449
1450 static int
1451 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1452                                uint32_t mode)
1453 {
1454         int ret = 0;
1455         bool start = 1;
1456         bool stop  = 0;
1457
1458         switch (mode) {
1459         case AMD_FAN_CTRL_NONE:
1460                 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1461                 break;
1462         case AMD_FAN_CTRL_MANUAL:
1463                 ret = smu_v11_0_smc_fan_control(smu, stop);
1464                 break;
1465         case AMD_FAN_CTRL_AUTO:
1466                 ret = smu_v11_0_smc_fan_control(smu, start);
1467                 break;
1468         default:
1469                 break;
1470         }
1471
1472         if (ret) {
1473                 pr_err("[%s]Set fan control mode failed!", __func__);
1474                 return -EINVAL;
1475         }
1476
1477         return ret;
1478 }
1479
1480 static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1481                                        uint32_t speed)
1482 {
1483         struct amdgpu_device *adev = smu->adev;
1484         int ret;
1485         uint32_t tach_period, crystal_clock_freq;
1486         bool stop = 0;
1487
1488         if (!speed)
1489                 return -EINVAL;
1490
1491         mutex_lock(&(smu->mutex));
1492         ret = smu_v11_0_smc_fan_control(smu, stop);
1493         if (ret)
1494                 goto set_fan_speed_rpm_failed;
1495
1496         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1497         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1498         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1499                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1500                                    CG_TACH_CTRL, TARGET_PERIOD,
1501                                    tach_period));
1502
1503         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1504
1505 set_fan_speed_rpm_failed:
1506         mutex_unlock(&(smu->mutex));
1507         return ret;
1508 }
1509
1510 #define XGMI_STATE_D0 1
1511 #define XGMI_STATE_D3 0
1512
1513 static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1514                                      uint32_t pstate)
1515 {
1516         int ret = 0;
1517         mutex_lock(&(smu->mutex));
1518         ret = smu_send_smc_msg_with_param(smu,
1519                                           SMU_MSG_SetXgmiMode,
1520                                           pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
1521         mutex_unlock(&(smu->mutex));
1522         return ret;
1523 }
1524
1525 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1526 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1527
1528 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1529                                  struct amdgpu_irq_src *source,
1530                                  struct amdgpu_iv_entry *entry)
1531 {
1532         uint32_t client_id = entry->client_id;
1533         uint32_t src_id = entry->src_id;
1534
1535         if (client_id == SOC15_IH_CLIENTID_THM) {
1536                 switch (src_id) {
1537                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1538                         pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
1539                                 PCI_BUS_NUM(adev->pdev->devfn),
1540                                 PCI_SLOT(adev->pdev->devfn),
1541                                 PCI_FUNC(adev->pdev->devfn));
1542                 break;
1543                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1544                         pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
1545                                 PCI_BUS_NUM(adev->pdev->devfn),
1546                                 PCI_SLOT(adev->pdev->devfn),
1547                                 PCI_FUNC(adev->pdev->devfn));
1548                 break;
1549                 default:
1550                         pr_warn("GPU under temperature range unknown src id (%d), detected on PCIe %d:%d.%d!\n",
1551                                 src_id,
1552                                 PCI_BUS_NUM(adev->pdev->devfn),
1553                                 PCI_SLOT(adev->pdev->devfn),
1554                                 PCI_FUNC(adev->pdev->devfn));
1555                 break;
1556
1557                 }
1558         }
1559
1560         return 0;
1561 }
1562
1563 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1564 {
1565         .process = smu_v11_0_irq_process,
1566 };
1567
1568 static int smu_v11_0_register_irq_handler(struct smu_context *smu)
1569 {
1570         struct amdgpu_device *adev = smu->adev;
1571         struct amdgpu_irq_src *irq_src = smu->irq_source;
1572         int ret = 0;
1573
1574         /* already register */
1575         if (irq_src)
1576                 return 0;
1577
1578         irq_src = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
1579         if (!irq_src)
1580                 return -ENOMEM;
1581         smu->irq_source = irq_src;
1582
1583         irq_src->funcs = &smu_v11_0_irq_funcs;
1584
1585         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1586                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1587                                 irq_src);
1588         if (ret)
1589                 return ret;
1590
1591         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1592                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1593                                 irq_src);
1594         if (ret)
1595                 return ret;
1596
1597         return ret;
1598 }
1599
1600 static int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1601                 struct pp_smu_nv_clock_table *max_clocks)
1602 {
1603         struct smu_table_context *table_context = &smu->smu_table;
1604         struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1605
1606         if (!max_clocks || !table_context->max_sustainable_clocks)
1607                 return -EINVAL;
1608
1609         sustainable_clocks = table_context->max_sustainable_clocks;
1610
1611         max_clocks->dcfClockInKhz =
1612                         (unsigned int) sustainable_clocks->dcef_clock * 1000;
1613         max_clocks->displayClockInKhz =
1614                         (unsigned int) sustainable_clocks->display_clock * 1000;
1615         max_clocks->phyClockInKhz =
1616                         (unsigned int) sustainable_clocks->phy_clock * 1000;
1617         max_clocks->pixelClockInKhz =
1618                         (unsigned int) sustainable_clocks->pixel_clock * 1000;
1619         max_clocks->uClockInKhz =
1620                         (unsigned int) sustainable_clocks->uclock * 1000;
1621         max_clocks->socClockInKhz =
1622                         (unsigned int) sustainable_clocks->soc_clock * 1000;
1623         max_clocks->dscClockInKhz = 0;
1624         max_clocks->dppClockInKhz = 0;
1625         max_clocks->fabricClockInKhz = 0;
1626
1627         return 0;
1628 }
1629
1630 static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1631 {
1632         int ret = 0;
1633
1634         mutex_lock(&smu->mutex);
1635         ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
1636         mutex_unlock(&smu->mutex);
1637
1638         return ret;
1639 }
1640
1641 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1642 {
1643         return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq);
1644 }
1645
1646 static bool smu_v11_0_baco_is_support(struct smu_context *smu)
1647 {
1648         struct amdgpu_device *adev = smu->adev;
1649         struct smu_baco_context *smu_baco = &smu->smu_baco;
1650         uint32_t val;
1651         bool baco_support;
1652
1653         mutex_lock(&smu_baco->mutex);
1654         baco_support = smu_baco->platform_support;
1655         mutex_unlock(&smu_baco->mutex);
1656
1657         if (!baco_support)
1658                 return false;
1659
1660         if (!smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1661                 return false;
1662
1663         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1664         if (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
1665                 return true;
1666
1667         return false;
1668 }
1669
1670 static enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1671 {
1672         struct smu_baco_context *smu_baco = &smu->smu_baco;
1673         enum smu_baco_state baco_state = SMU_BACO_STATE_EXIT;
1674
1675         mutex_lock(&smu_baco->mutex);
1676         baco_state = smu_baco->state;
1677         mutex_unlock(&smu_baco->mutex);
1678
1679         return baco_state;
1680 }
1681
1682 static int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1683 {
1684
1685         struct smu_baco_context *smu_baco = &smu->smu_baco;
1686         int ret = 0;
1687
1688         if (smu_v11_0_baco_get_state(smu) == state)
1689                 return 0;
1690
1691         mutex_lock(&smu_baco->mutex);
1692
1693         if (state == SMU_BACO_STATE_ENTER)
1694                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, BACO_SEQ_BACO);
1695         else
1696                 ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
1697         if (ret)
1698                 goto out;
1699
1700         smu_baco->state = state;
1701 out:
1702         mutex_unlock(&smu_baco->mutex);
1703         return ret;
1704 }
1705
1706 static int smu_v11_0_baco_reset(struct smu_context *smu)
1707 {
1708         int ret = 0;
1709
1710         ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1711         if (ret)
1712                 return ret;
1713
1714         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1715         if (ret)
1716                 return ret;
1717
1718         msleep(10);
1719
1720         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1721         if (ret)
1722                 return ret;
1723
1724         return ret;
1725 }
1726
1727 static const struct smu_funcs smu_v11_0_funcs = {
1728         .init_microcode = smu_v11_0_init_microcode,
1729         .load_microcode = smu_v11_0_load_microcode,
1730         .check_fw_status = smu_v11_0_check_fw_status,
1731         .check_fw_version = smu_v11_0_check_fw_version,
1732         .send_smc_msg = smu_v11_0_send_msg,
1733         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
1734         .read_smc_arg = smu_v11_0_read_arg,
1735         .setup_pptable = smu_v11_0_setup_pptable,
1736         .init_smc_tables = smu_v11_0_init_smc_tables,
1737         .fini_smc_tables = smu_v11_0_fini_smc_tables,
1738         .init_power = smu_v11_0_init_power,
1739         .fini_power = smu_v11_0_fini_power,
1740         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
1741         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
1742         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
1743         .check_pptable = smu_v11_0_check_pptable,
1744         .parse_pptable = smu_v11_0_parse_pptable,
1745         .populate_smc_pptable = smu_v11_0_populate_smc_pptable,
1746         .write_pptable = smu_v11_0_write_pptable,
1747         .write_watermarks_table = smu_v11_0_write_watermarks_table,
1748         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
1749         .set_tool_table_location = smu_v11_0_set_tool_table_location,
1750         .init_display_count = smu_v11_0_init_display_count,
1751         .set_allowed_mask = smu_v11_0_set_allowed_mask,
1752         .get_enabled_mask = smu_v11_0_get_enabled_mask,
1753         .system_features_control = smu_v11_0_system_features_control,
1754         .update_feature_enable_state = smu_v11_0_update_feature_enable_state,
1755         .notify_display_change = smu_v11_0_notify_display_change,
1756         .get_power_limit = smu_v11_0_get_power_limit,
1757         .set_power_limit = smu_v11_0_set_power_limit,
1758         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
1759         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
1760         .start_thermal_control = smu_v11_0_start_thermal_control,
1761         .read_sensor = smu_v11_0_read_sensor,
1762         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
1763         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
1764         .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
1765         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
1766         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
1767         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
1768         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
1769         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
1770         .gfx_off_control = smu_v11_0_gfx_off_control,
1771         .register_irq_handler = smu_v11_0_register_irq_handler,
1772         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
1773         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
1774         .baco_is_support = smu_v11_0_baco_is_support,
1775         .baco_get_state = smu_v11_0_baco_get_state,
1776         .baco_set_state = smu_v11_0_baco_set_state,
1777         .baco_reset = smu_v11_0_baco_reset,
1778 };
1779
1780 void smu_v11_0_set_smu_funcs(struct smu_context *smu)
1781 {
1782         struct amdgpu_device *adev = smu->adev;
1783
1784         smu->funcs = &smu_v11_0_funcs;
1785         switch (adev->asic_type) {
1786         case CHIP_VEGA20:
1787                 vega20_set_ppt_funcs(smu);
1788                 break;
1789         case CHIP_NAVI10:
1790                 navi10_set_ppt_funcs(smu);
1791                 break;
1792         default:
1793                 pr_warn("Unknown asic for smu11\n");
1794         }
1795 }