drivers/gpu/drm/amd/powerplay/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26
  27 #define SMU_11_0_PARTIAL_PPTABLE
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_smu.h"
  31 #include "smu_internal.h"
  32 #include "atomfirmware.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "smu_v11_0.h"
  35 #include "smu_v11_0_pptable.h"
  36 #include "soc15_common.h"
  37 #include "atom.h"
  38 #include "amd_pcie.h"
  39 #include "amdgpu_ras.h"
  40
  41 #include "asic_reg/thm/thm_11_0_2_offset.h"
  42 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  43 #include "asic_reg/mp/mp_11_0_offset.h"
  44 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  45 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  46 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  47
  48 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
  49 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
  50 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  51 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
  52 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
  53
  54 #define SMU11_VOLTAGE_SCALE 4
  55
  56 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
  57                                               uint16_t msg)
  58 {
  59         struct amdgpu_device *adev = smu->adev;
  60         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  61         return 0;
  62 }
  63
  64 static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
  65 {
  66         struct amdgpu_device *adev = smu->adev;
  67
  68         *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  69         return 0;
  70 }
  71
  72 static int smu_v11_0_wait_for_response(struct smu_context *smu)
  73 {
  74         struct amdgpu_device *adev = smu->adev;
  75         uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
  76
  77         for (i = 0; i < timeout; i++) {
  78                 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  79                 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
  80                         return cur_value == 0x1 ? 0 : -EIO;
  81
  82                 udelay(1);
  83         }
  84
  85         /* timeout means wrong logic */
  86         return -ETIME;
  87 }
  88
  89 int
  90 smu_v11_0_send_msg_with_param(struct smu_context *smu,
  91                               enum smu_message_type msg,
  92                               uint32_t param,
  93                               uint32_t *read_arg)
  94 {
  95         struct amdgpu_device *adev = smu->adev;
  96         int ret = 0, index = 0;
  97
  98         index = smu_msg_get_index(smu, msg);
  99         if (index < 0)
 100                 return index;
 101
 102         mutex_lock(&smu->message_lock);
 103         ret = smu_v11_0_wait_for_response(smu);
 104         if (ret) {
 105                 pr_err("Msg issuing pre-check failed and "
 106                        "SMU may be not in the right state!\n");
 107                 goto out;
 108         }
 109
 110         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 111
 112         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
 113
 114         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 115
 116         ret = smu_v11_0_wait_for_response(smu);
 117         if (ret) {
 118                 pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
 119                        smu_get_message_name(smu, msg), index, param, ret);
 120                 goto out;
 121         }
 122         if (read_arg) {
 123                 ret = smu_v11_0_read_arg(smu, read_arg);
 124                 if (ret) {
 125                         pr_err("failed to read message arg: %10s (%d) \tparam: 0x%08x response %#x\n",
 126                                smu_get_message_name(smu, msg), index, param, ret);
 127                         goto out;
 128                 }
 129         }
 130 out:
 131         mutex_unlock(&smu->message_lock);
 132         return ret;
 133 }
 134
 135 int smu_v11_0_init_microcode(struct smu_context *smu)
 136 {
 137         struct amdgpu_device *adev = smu->adev;
 138         const char *chip_name;
 139         char fw_name[30];
 140         int err = 0;
 141         const struct smc_firmware_header_v1_0 *hdr;
 142         const struct common_firmware_header *header;
 143         struct amdgpu_firmware_info *ucode = NULL;
 144
 145         switch (adev->asic_type) {
 146         case CHIP_VEGA20:
 147                 chip_name = "vega20";
 148                 break;
 149         case CHIP_ARCTURUS:
 150                 chip_name = "arcturus";
 151                 break;
 152         case CHIP_NAVI10:
 153                 chip_name = "navi10";
 154                 break;
 155         case CHIP_NAVI14:
 156                 chip_name = "navi14";
 157                 break;
 158         case CHIP_NAVI12:
 159                 chip_name = "navi12";
 160                 break;
 161         default:
 162                 BUG();
 163         }
 164
 165         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 166
 167         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 168         if (err)
 169                 goto out;
 170         err = amdgpu_ucode_validate(adev->pm.fw);
 171         if (err)
 172                 goto out;
 173
 174         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 175         amdgpu_ucode_print_smc_hdr(&hdr->header);
 176         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 177
 178         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 179                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 180                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 181                 ucode->fw = adev->pm.fw;
 182                 header = (const struct common_firmware_header *)ucode->fw->data;
 183                 adev->firmware.fw_size +=
 184                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 185         }
 186
 187 out:
 188         if (err) {
 189                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 190                           fw_name);
 191                 release_firmware(adev->pm.fw);
 192                 adev->pm.fw = NULL;
 193         }
 194         return err;
 195 }
 196
 197 int smu_v11_0_load_microcode(struct smu_context *smu)
 198 {
 199         struct amdgpu_device *adev = smu->adev;
 200         const uint32_t *src;
 201         const struct smc_firmware_header_v1_0 *hdr;
 202         uint32_t addr_start = MP1_SRAM;
 203         uint32_t i;
 204         uint32_t smc_fw_size;
 205         uint32_t mp1_fw_flags;
 206
 207         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 208         src = (const uint32_t *)(adev->pm.fw->data +
 209                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 210         smc_fw_size = hdr->header.ucode_size_bytes;
 211
 212         for (i = 1; i < smc_fw_size/4 - 1; i++) {
 213                 WREG32_PCIE(addr_start, src[i]);
 214                 addr_start += 4;
 215         }
 216
 217         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 218                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 219         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 220                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 221
 222         for (i = 0; i < adev->usec_timeout; i++) {
 223                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 224                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 225                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 226                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 227                         break;
 228                 udelay(1);
 229         }
 230
 231         if (i == adev->usec_timeout)
 232                 return -ETIME;
 233
 234         return 0;
 235 }
 236
 237 int smu_v11_0_check_fw_status(struct smu_context *smu)
 238 {
 239         struct amdgpu_device *adev = smu->adev;
 240         uint32_t mp1_fw_flags;
 241
 242         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 243                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 244
 245         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 246             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 247                 return 0;
 248
 249         return -EIO;
 250 }
 251
 252 int smu_v11_0_check_fw_version(struct smu_context *smu)
 253 {
 254         uint32_t if_version = 0xff, smu_version = 0xff;
 255         uint16_t smu_major;
 256         uint8_t smu_minor, smu_debug;
 257         int ret = 0;
 258
 259         ret = smu_get_smc_version(smu, &if_version, &smu_version);
 260         if (ret)
 261                 return ret;
 262
 263         smu_major = (smu_version >> 16) & 0xffff;
 264         smu_minor = (smu_version >> 8) & 0xff;
 265         smu_debug = (smu_version >> 0) & 0xff;
 266
 267         switch (smu->adev->asic_type) {
 268         case CHIP_VEGA20:
 269                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VG20;
 270                 break;
 271         case CHIP_ARCTURUS:
 272                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
 273                 break;
 274         case CHIP_NAVI10:
 275                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
 276                 break;
 277         case CHIP_NAVI12:
 278                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
 279                 break;
 280         case CHIP_NAVI14:
 281                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
 282                 break;
 283         default:
 284                 pr_err("smu unsupported asic type:%d.\n", smu->adev->asic_type);
 285                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
 286                 break;
 287         }
 288
 289         /*
 290          * 1. if_version mismatch is not critical as our fw is designed
 291          * to be backward compatible.
 292          * 2. New fw usually brings some optimizations. But that's visible
 293          * only on the paired driver.
 294          * Considering above, we just leave user a warning message instead
 295          * of halt driver loading.
 296          */
 297         if (if_version != smu->smc_driver_if_version) {
 298                 pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 299                         "smu fw version = 0x%08x (%d.%d.%d)\n",
 300                         smu->smc_driver_if_version, if_version,
 301                         smu_version, smu_major, smu_minor, smu_debug);
 302                 pr_warn("SMU driver if version not matched\n");
 303         }
 304
 305         return ret;
 306 }
 307
 308 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 309 {
 310         struct amdgpu_device *adev = smu->adev;
 311         uint32_t ppt_offset_bytes;
 312         const struct smc_firmware_header_v2_0 *v2;
 313
 314         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 315
 316         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 317         *size = le32_to_cpu(v2->ppt_size_bytes);
 318         *table = (uint8_t *)v2 + ppt_offset_bytes;
 319
 320         return 0;
 321 }
 322
 323 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 324                                       uint32_t *size, uint32_t pptable_id)
 325 {
 326         struct amdgpu_device *adev = smu->adev;
 327         const struct smc_firmware_header_v2_1 *v2_1;
 328         struct smc_soft_pptable_entry *entries;
 329         uint32_t pptable_count = 0;
 330         int i = 0;
 331
 332         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 333         entries = (struct smc_soft_pptable_entry *)
 334                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 335         pptable_count = le32_to_cpu(v2_1->pptable_count);
 336         for (i = 0; i < pptable_count; i++) {
 337                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 338                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 339                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 340                         break;
 341                 }
 342         }
 343
 344         if (i == pptable_count)
 345                 return -EINVAL;
 346
 347         return 0;
 348 }
 349
 350 int smu_v11_0_setup_pptable(struct smu_context *smu)
 351 {
 352         struct amdgpu_device *adev = smu->adev;
 353         const struct smc_firmware_header_v1_0 *hdr;
 354         int ret, index;
 355         uint32_t size = 0;
 356         uint16_t atom_table_size;
 357         uint8_t frev, crev;
 358         void *table;
 359         uint16_t version_major, version_minor;
 360
 361         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 362         version_major = le16_to_cpu(hdr->header.header_version_major);
 363         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 364         if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 365                 pr_info("use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
 366                 switch (version_minor) {
 367                 case 0:
 368                         ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 369                         break;
 370                 case 1:
 371                         ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 372                                                          smu->smu_table.boot_values.pp_table_id);
 373                         break;
 374                 default:
 375                         ret = -EINVAL;
 376                         break;
 377                 }
 378                 if (ret)
 379                         return ret;
 380
 381         } else {
 382                 pr_info("use vbios provided pptable\n");
 383                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 384                                                     powerplayinfo);
 385
 386                 ret = smu_get_atom_data_table(smu, index, &atom_table_size, &frev, &crev,
 387                                               (uint8_t **)&table);
 388                 if (ret)
 389                         return ret;
 390                 size = atom_table_size;
 391         }
 392
 393         if (!smu->smu_table.power_play_table)
 394                 smu->smu_table.power_play_table = table;
 395         if (!smu->smu_table.power_play_table_size)
 396                 smu->smu_table.power_play_table_size = size;
 397
 398         return 0;
 399 }
 400
 401 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
 402 {
 403         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 404
 405         if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
 406                 return -EINVAL;
 407
 408         return smu_alloc_dpm_context(smu);
 409 }
 410
 411 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
 412 {
 413         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 414
 415         if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
 416                 return -EINVAL;
 417
 418         kfree(smu_dpm->dpm_context);
 419         kfree(smu_dpm->golden_dpm_context);
 420         kfree(smu_dpm->dpm_current_power_state);
 421         kfree(smu_dpm->dpm_request_power_state);
 422         smu_dpm->dpm_context = NULL;
 423         smu_dpm->golden_dpm_context = NULL;
 424         smu_dpm->dpm_context_size = 0;
 425         smu_dpm->dpm_current_power_state = NULL;
 426         smu_dpm->dpm_request_power_state = NULL;
 427
 428         return 0;
 429 }
 430
 431 int smu_v11_0_init_smc_tables(struct smu_context *smu)
 432 {
 433         struct smu_table_context *smu_table = &smu->smu_table;
 434         struct smu_table *tables = NULL;
 435         int ret = 0;
 436
 437         if (smu_table->tables)
 438                 return -EINVAL;
 439
 440         tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
 441                          GFP_KERNEL);
 442         if (!tables)
 443                 return -ENOMEM;
 444
 445         smu_table->tables = tables;
 446
 447         ret = smu_tables_init(smu, tables);
 448         if (ret)
 449                 return ret;
 450
 451         ret = smu_v11_0_init_dpm_context(smu);
 452         if (ret)
 453                 return ret;
 454
 455         return 0;
 456 }
 457
 458 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 459 {
 460         struct smu_table_context *smu_table = &smu->smu_table;
 461         int ret = 0;
 462
 463         if (!smu_table->tables)
 464                 return -EINVAL;
 465
 466         kfree(smu_table->tables);
 467         kfree(smu_table->metrics_table);
 468         kfree(smu_table->watermarks_table);
 469         smu_table->tables = NULL;
 470         smu_table->metrics_table = NULL;
 471         smu_table->watermarks_table = NULL;
 472         smu_table->metrics_time = 0;
 473
 474         ret = smu_v11_0_fini_dpm_context(smu);
 475         if (ret)
 476                 return ret;
 477         return 0;
 478 }
 479
 480 int smu_v11_0_init_power(struct smu_context *smu)
 481 {
 482         struct smu_power_context *smu_power = &smu->smu_power;
 483
 484         if (smu_power->power_context || smu_power->power_context_size != 0)
 485                 return -EINVAL;
 486
 487         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 488                                            GFP_KERNEL);
 489         if (!smu_power->power_context)
 490                 return -ENOMEM;
 491         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 492
 493         return 0;
 494 }
 495
 496 int smu_v11_0_fini_power(struct smu_context *smu)
 497 {
 498         struct smu_power_context *smu_power = &smu->smu_power;
 499
 500         if (!smu_power->power_context || smu_power->power_context_size == 0)
 501                 return -EINVAL;
 502
 503         kfree(smu_power->power_context);
 504         smu_power->power_context = NULL;
 505         smu_power->power_context_size = 0;
 506
 507         return 0;
 508 }
 509
 510 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 511 {
 512         int ret, index;
 513         uint16_t size;
 514         uint8_t frev, crev;
 515         struct atom_common_table_header *header;
 516         struct atom_firmware_info_v3_3 *v_3_3;
 517         struct atom_firmware_info_v3_1 *v_3_1;
 518
 519         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 520                                             firmwareinfo);
 521
 522         ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
 523                                       (uint8_t **)&header);
 524         if (ret)
 525                 return ret;
 526
 527         if (header->format_revision != 3) {
 528                 pr_err("unknown atom_firmware_info version! for smu11\n");
 529                 return -EINVAL;
 530         }
 531
 532         switch (header->content_revision) {
 533         case 0:
 534         case 1:
 535         case 2:
 536                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 537                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 538                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 539                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 540                 smu->smu_table.boot_values.socclk = 0;
 541                 smu->smu_table.boot_values.dcefclk = 0;
 542                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 543                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 544                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 545                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 546                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 547                 smu->smu_table.boot_values.pp_table_id = 0;
 548                 break;
 549         case 3:
 550         default:
 551                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 552                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 553                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 554                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 555                 smu->smu_table.boot_values.socclk = 0;
 556                 smu->smu_table.boot_values.dcefclk = 0;
 557                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 558                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 559                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 560                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 561                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 562                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 563         }
 564
 565         smu->smu_table.boot_values.format_revision = header->format_revision;
 566         smu->smu_table.boot_values.content_revision = header->content_revision;
 567
 568         return 0;
 569 }
 570
 571 int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 572 {
 573         int ret, index;
 574         struct amdgpu_device *adev = smu->adev;
 575         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 576         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 577
 578         input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
 579         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 580         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 581                                             getsmuclockinfo);
 582
 583         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 584                                         (uint32_t *)&input);
 585         if (ret)
 586                 return -EINVAL;
 587
 588         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 589         smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 590
 591         memset(&input, 0, sizeof(input));
 592         input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
 593         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 594         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 595                                             getsmuclockinfo);
 596
 597         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 598                                         (uint32_t *)&input);
 599         if (ret)
 600                 return -EINVAL;
 601
 602         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 603         smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 604
 605         memset(&input, 0, sizeof(input));
 606         input.clk_id = SMU11_SYSPLL0_ECLK_ID;
 607         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 608         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 609                                             getsmuclockinfo);
 610
 611         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 612                                         (uint32_t *)&input);
 613         if (ret)
 614                 return -EINVAL;
 615
 616         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 617         smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 618
 619         memset(&input, 0, sizeof(input));
 620         input.clk_id = SMU11_SYSPLL0_VCLK_ID;
 621         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 622         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 623                                             getsmuclockinfo);
 624
 625         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 626                                         (uint32_t *)&input);
 627         if (ret)
 628                 return -EINVAL;
 629
 630         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 631         smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 632
 633         memset(&input, 0, sizeof(input));
 634         input.clk_id = SMU11_SYSPLL0_DCLK_ID;
 635         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 636         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 637                                             getsmuclockinfo);
 638
 639         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 640                                         (uint32_t *)&input);
 641         if (ret)
 642                 return -EINVAL;
 643
 644         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 645         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 646
 647         if ((smu->smu_table.boot_values.format_revision == 3) &&
 648             (smu->smu_table.boot_values.content_revision >= 2)) {
 649                 memset(&input, 0, sizeof(input));
 650                 input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
 651                 input.syspll_id = SMU11_SYSPLL1_2_ID;
 652                 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 653                 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 654                                                     getsmuclockinfo);
 655
 656                 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 657                                                 (uint32_t *)&input);
 658                 if (ret)
 659                         return -EINVAL;
 660
 661                 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 662                 smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 663         }
 664
 665         return 0;
 666 }
 667
 668 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 669 {
 670         struct smu_table_context *smu_table = &smu->smu_table;
 671         struct smu_table *memory_pool = &smu_table->memory_pool;
 672         int ret = 0;
 673         uint64_t address;
 674         uint32_t address_low, address_high;
 675
 676         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 677                 return ret;
 678
 679         address = (uintptr_t)memory_pool->cpu_addr;
 680         address_high = (uint32_t)upper_32_bits(address);
 681         address_low  = (uint32_t)lower_32_bits(address);
 682
 683         ret = smu_send_smc_msg_with_param(smu,
 684                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 685                                           address_high,
 686                                           NULL);
 687         if (ret)
 688                 return ret;
 689         ret = smu_send_smc_msg_with_param(smu,
 690                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 691                                           address_low,
 692                                           NULL);
 693         if (ret)
 694                 return ret;
 695
 696         address = memory_pool->mc_address;
 697         address_high = (uint32_t)upper_32_bits(address);
 698         address_low  = (uint32_t)lower_32_bits(address);
 699
 700         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 701                                           address_high, NULL);
 702         if (ret)
 703                 return ret;
 704         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 705                                           address_low, NULL);
 706         if (ret)
 707                 return ret;
 708         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 709                                           (uint32_t)memory_pool->size, NULL);
 710         if (ret)
 711                 return ret;
 712
 713         return ret;
 714 }
 715
 716 int smu_v11_0_check_pptable(struct smu_context *smu)
 717 {
 718         int ret;
 719
 720         ret = smu_check_powerplay_table(smu);
 721         return ret;
 722 }
 723
 724 int smu_v11_0_parse_pptable(struct smu_context *smu)
 725 {
 726         int ret;
 727
 728         struct smu_table_context *table_context = &smu->smu_table;
 729         struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
 730
 731         if (table_context->driver_pptable)
 732                 return -EINVAL;
 733
 734         table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
 735
 736         if (!table_context->driver_pptable)
 737                 return -ENOMEM;
 738
 739         ret = smu_store_powerplay_table(smu);
 740         if (ret)
 741                 return -EINVAL;
 742
 743         ret = smu_append_powerplay_table(smu);
 744
 745         return ret;
 746 }
 747
 748 int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
 749 {
 750         int ret;
 751
 752         ret = smu_set_default_dpm_table(smu);
 753
 754         return ret;
 755 }
 756
 757 int smu_v11_0_write_pptable(struct smu_context *smu)
 758 {
 759         struct smu_table_context *table_context = &smu->smu_table;
 760         int ret = 0;
 761
 762         ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0,
 763                                table_context->driver_pptable, true);
 764
 765         return ret;
 766 }
 767
 768 int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 769 {
 770         int ret;
 771
 772         ret = smu_send_smc_msg_with_param(smu,
 773                                           SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
 774         if (ret)
 775                 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
 776
 777         return ret;
 778 }
 779
 780 int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
 781 {
 782         struct smu_table_context *table_context = &smu->smu_table;
 783
 784         if (!table_context)
 785                 return -EINVAL;
 786
 787         return smu_v11_0_set_deep_sleep_dcefclk(smu, table_context->boot_values.dcefclk / 100);
 788 }
 789
 790 int smu_v11_0_set_driver_table_location(struct smu_context *smu)
 791 {
 792         struct smu_table *driver_table = &smu->smu_table.driver_table;
 793         int ret = 0;
 794
 795         if (driver_table->mc_address) {
 796                 ret = smu_send_smc_msg_with_param(smu,
 797                                 SMU_MSG_SetDriverDramAddrHigh,
 798                                 upper_32_bits(driver_table->mc_address),
 799                                 NULL);
 800                 if (!ret)
 801                         ret = smu_send_smc_msg_with_param(smu,
 802                                 SMU_MSG_SetDriverDramAddrLow,
 803                                 lower_32_bits(driver_table->mc_address),
 804                                 NULL);
 805         }
 806
 807         return ret;
 808 }
 809
 810 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 811 {
 812         int ret = 0;
 813         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 814
 815         if (tool_table->mc_address) {
 816                 ret = smu_send_smc_msg_with_param(smu,
 817                                 SMU_MSG_SetToolsDramAddrHigh,
 818                                 upper_32_bits(tool_table->mc_address),
 819                                 NULL);
 820                 if (!ret)
 821                         ret = smu_send_smc_msg_with_param(smu,
 822                                 SMU_MSG_SetToolsDramAddrLow,
 823                                 lower_32_bits(tool_table->mc_address),
 824                                 NULL);
 825         }
 826
 827         return ret;
 828 }
 829
 830 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 831 {
 832         int ret = 0;
 833
 834         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
 835         return ret;
 836 }
 837
 838
 839 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 840 {
 841         struct smu_feature *feature = &smu->smu_feature;
 842         int ret = 0;
 843         uint32_t feature_mask[2];
 844
 845         mutex_lock(&feature->mutex);
 846         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 847                 goto failed;
 848
 849         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 850
 851         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 852                                           feature_mask[1], NULL);
 853         if (ret)
 854                 goto failed;
 855
 856         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 857                                           feature_mask[0], NULL);
 858         if (ret)
 859                 goto failed;
 860
 861 failed:
 862         mutex_unlock(&feature->mutex);
 863         return ret;
 864 }
 865
 866 int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 867                                       uint32_t *feature_mask, uint32_t num)
 868 {
 869         uint32_t feature_mask_high = 0, feature_mask_low = 0;
 870         struct smu_feature *feature = &smu->smu_feature;
 871         int ret = 0;
 872
 873         if (!feature_mask || num < 2)
 874                 return -EINVAL;
 875
 876         if (bitmap_empty(feature->enabled, feature->feature_num)) {
 877                 ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh, &feature_mask_high);
 878                 if (ret)
 879                         return ret;
 880
 881                 ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow, &feature_mask_low);
 882                 if (ret)
 883                         return ret;
 884
 885                 feature_mask[0] = feature_mask_low;
 886                 feature_mask[1] = feature_mask_high;
 887         } else {
 888                 bitmap_copy((unsigned long *)feature_mask, feature->enabled,
 889                              feature->feature_num);
 890         }
 891
 892         return ret;
 893 }
 894
 895 int smu_v11_0_system_features_control(struct smu_context *smu,
 896                                              bool en)
 897 {
 898         struct smu_feature *feature = &smu->smu_feature;
 899         uint32_t feature_mask[2];
 900         int ret = 0;
 901
 902         ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 903                                      SMU_MSG_DisableAllSmuFeatures), NULL);
 904         if (ret)
 905                 return ret;
 906
 907         bitmap_zero(feature->enabled, feature->feature_num);
 908         bitmap_zero(feature->supported, feature->feature_num);
 909
 910         if (en) {
 911                 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 912                 if (ret)
 913                         return ret;
 914
 915                 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 916                             feature->feature_num);
 917                 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 918                             feature->feature_num);
 919         }
 920
 921         return ret;
 922 }
 923
 924 int smu_v11_0_notify_display_change(struct smu_context *smu)
 925 {
 926         int ret = 0;
 927
 928         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 929             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 930                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
 931
 932         return ret;
 933 }
 934
 935 static int
 936 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 937                                     enum smu_clk_type clock_select)
 938 {
 939         int ret = 0;
 940         int clk_id;
 941
 942         if ((smu_msg_get_index(smu, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 943             (smu_msg_get_index(smu, SMU_MSG_GetMaxDpmFreq) < 0))
 944                 return 0;
 945
 946         clk_id = smu_clk_get_index(smu, clock_select);
 947         if (clk_id < 0)
 948                 return -EINVAL;
 949
 950         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 951                                           clk_id << 16, clock);
 952         if (ret) {
 953                 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 954                 return ret;
 955         }
 956
 957         if (*clock != 0)
 958                 return 0;
 959
 960         /* if DC limit is zero, return AC limit */
 961         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 962                                           clk_id << 16, clock);
 963         if (ret) {
 964                 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 965                 return ret;
 966         }
 967
 968         return 0;
 969 }
 970
 971 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 972 {
 973         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 974         int ret = 0;
 975
 976         if (!smu->smu_table.max_sustainable_clocks)
 977                 max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
 978                                          GFP_KERNEL);
 979         else
 980                 max_sustainable_clocks = smu->smu_table.max_sustainable_clocks;
 981
 982         smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 983
 984         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 985         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 986         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 987         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 988         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 989         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 990
 991         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 992                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 993                                                           &(max_sustainable_clocks->uclock),
 994                                                           SMU_UCLK);
 995                 if (ret) {
 996                         pr_err("[%s] failed to get max UCLK from SMC!",
 997                                __func__);
 998                         return ret;
 999                 }
1000         }
1001
1002         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1003                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1004                                                           &(max_sustainable_clocks->soc_clock),
1005                                                           SMU_SOCCLK);
1006                 if (ret) {
1007                         pr_err("[%s] failed to get max SOCCLK from SMC!",
1008                                __func__);
1009                         return ret;
1010                 }
1011         }
1012
1013         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1014                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1015                                                           &(max_sustainable_clocks->dcef_clock),
1016                                                           SMU_DCEFCLK);
1017                 if (ret) {
1018                         pr_err("[%s] failed to get max DCEFCLK from SMC!",
1019                                __func__);
1020                         return ret;
1021                 }
1022
1023                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1024                                                           &(max_sustainable_clocks->display_clock),
1025                                                           SMU_DISPCLK);
1026                 if (ret) {
1027                         pr_err("[%s] failed to get max DISPCLK from SMC!",
1028                                __func__);
1029                         return ret;
1030                 }
1031                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1032                                                           &(max_sustainable_clocks->phy_clock),
1033                                                           SMU_PHYCLK);
1034                 if (ret) {
1035                         pr_err("[%s] failed to get max PHYCLK from SMC!",
1036                                __func__);
1037                         return ret;
1038                 }
1039                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1040                                                           &(max_sustainable_clocks->pixel_clock),
1041                                                           SMU_PIXCLK);
1042                 if (ret) {
1043                         pr_err("[%s] failed to get max PIXCLK from SMC!",
1044                                __func__);
1045                         return ret;
1046                 }
1047         }
1048
1049         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1050                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1051
1052         return 0;
1053 }
1054
1055 uint32_t smu_v11_0_get_max_power_limit(struct smu_context *smu) {
1056         uint32_t od_limit, max_power_limit;
1057         struct smu_11_0_powerplay_table *powerplay_table = NULL;
1058         struct smu_table_context *table_context = &smu->smu_table;
1059         powerplay_table = table_context->power_play_table;
1060
1061         max_power_limit = smu_get_pptable_power_limit(smu);
1062
1063         if (!max_power_limit) {
1064                 // If we couldn't get the table limit, fall back on first-read value
1065                 if (!smu->default_power_limit)
1066                         smu->default_power_limit = smu->power_limit;
1067                 max_power_limit = smu->default_power_limit;
1068         }
1069
1070         if (smu->od_enabled) {
1071                 od_limit = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1072
1073                 pr_debug("ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_limit, smu->default_power_limit);
1074
1075                 max_power_limit *= (100 + od_limit);
1076                 max_power_limit /= 100;
1077         }
1078
1079         return max_power_limit;
1080 }
1081
1082 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1083 {
1084         int ret = 0;
1085         uint32_t max_power_limit;
1086
1087         max_power_limit = smu_v11_0_get_max_power_limit(smu);
1088
1089         if (n > max_power_limit) {
1090                 pr_err("New power limit (%d) is over the max allowed %d\n",
1091                                 n,
1092                                 max_power_limit);
1093                 return -EINVAL;
1094         }
1095
1096         if (n == 0)
1097                 n = smu->default_power_limit;
1098
1099         if (!smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1100                 pr_err("Setting new power limit is not supported!\n");
1101                 return -EOPNOTSUPP;
1102         }
1103
1104         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
1105         if (ret) {
1106                 pr_err("[%s] Set power limit Failed!\n", __func__);
1107                 return ret;
1108         }
1109         smu->power_limit = n;
1110
1111         return 0;
1112 }
1113
1114 int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1115                                           enum smu_clk_type clk_id,
1116                                           uint32_t *value)
1117 {
1118         int ret = 0;
1119         uint32_t freq = 0;
1120         int asic_clk_id;
1121
1122         if (clk_id >= SMU_CLK_COUNT || !value)
1123                 return -EINVAL;
1124
1125         asic_clk_id = smu_clk_get_index(smu, clk_id);
1126         if (asic_clk_id < 0)
1127                 return -EINVAL;
1128
1129         /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
1130         if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) < 0)
1131                 ret =  smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
1132         else {
1133                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1134                                                   (asic_clk_id << 16), &freq);
1135                 if (ret)
1136                         return ret;
1137         }
1138
1139         freq *= 100;
1140         *value = freq;
1141
1142         return ret;
1143 }
1144
1145 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1146                                        struct smu_temperature_range range)
1147 {
1148         struct amdgpu_device *adev = smu->adev;
1149         int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
1150         int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
1151         uint32_t val;
1152         struct smu_table_context *table_context = &smu->smu_table;
1153         struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1154
1155         low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1156                         range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1157         high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp);
1158
1159         if (low > high)
1160                 return -EINVAL;
1161
1162         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1163         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1164         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1165         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1166         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1167         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1168         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1169         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1170
1171         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1172
1173         return 0;
1174 }
1175
1176 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1177 {
1178         struct amdgpu_device *adev = smu->adev;
1179         uint32_t val = 0;
1180
1181         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1182         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1183         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1184
1185         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1186
1187         return 0;
1188 }
1189
1190 int smu_v11_0_start_thermal_control(struct smu_context *smu)
1191 {
1192         int ret = 0;
1193         struct smu_temperature_range range;
1194         struct amdgpu_device *adev = smu->adev;
1195
1196         memcpy(&range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1197
1198         ret = smu_get_thermal_temperature_range(smu, &range);
1199         if (ret)
1200                 return ret;
1201
1202         if (smu->smu_table.thermal_controller_type) {
1203                 ret = smu_v11_0_set_thermal_range(smu, range);
1204                 if (ret)
1205                         return ret;
1206
1207                 ret = smu_v11_0_enable_thermal_alert(smu);
1208                 if (ret)
1209                         return ret;
1210
1211                 ret = smu_set_thermal_fan_table(smu);
1212                 if (ret)
1213                         return ret;
1214         }
1215
1216         adev->pm.dpm.thermal.min_temp = range.min;
1217         adev->pm.dpm.thermal.max_temp = range.max;
1218         adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1219         adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1220         adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1221         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1222         adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1223         adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1224         adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1225
1226         return ret;
1227 }
1228
1229 int smu_v11_0_stop_thermal_control(struct smu_context *smu)
1230 {
1231         struct amdgpu_device *adev = smu->adev;
1232
1233         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1234
1235         return 0;
1236 }
1237
1238 static uint16_t convert_to_vddc(uint8_t vid)
1239 {
1240         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1241 }
1242
1243 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1244 {
1245         struct amdgpu_device *adev = smu->adev;
1246         uint32_t vdd = 0, val_vid = 0;
1247
1248         if (!value)
1249                 return -EINVAL;
1250         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1251                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1252                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1253
1254         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1255
1256         *value = vdd;
1257
1258         return 0;
1259
1260 }
1261
1262 int smu_v11_0_read_sensor(struct smu_context *smu,
1263                                  enum amd_pp_sensors sensor,
1264                                  void *data, uint32_t *size)
1265 {
1266         int ret = 0;
1267
1268         if(!data || !size)
1269                 return -EINVAL;
1270
1271         switch (sensor) {
1272         case AMDGPU_PP_SENSOR_GFX_MCLK:
1273                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1274                 *size = 4;
1275                 break;
1276         case AMDGPU_PP_SENSOR_GFX_SCLK:
1277                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1278                 *size = 4;
1279                 break;
1280         case AMDGPU_PP_SENSOR_VDDGFX:
1281                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1282                 *size = 4;
1283                 break;
1284         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1285                 *(uint32_t *)data = 0;
1286                 *size = 4;
1287                 break;
1288         default:
1289                 ret = smu_common_read_sensor(smu, sensor, data, size);
1290                 break;
1291         }
1292
1293         if (ret)
1294                 *size = 0;
1295
1296         return ret;
1297 }
1298
1299 int
1300 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1301                                         struct pp_display_clock_request
1302                                         *clock_req)
1303 {
1304         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1305         int ret = 0;
1306         enum smu_clk_type clk_select = 0;
1307         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1308
1309         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1310                 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1311                 switch (clk_type) {
1312                 case amd_pp_dcef_clock:
1313                         clk_select = SMU_DCEFCLK;
1314                         break;
1315                 case amd_pp_disp_clock:
1316                         clk_select = SMU_DISPCLK;
1317                         break;
1318                 case amd_pp_pixel_clock:
1319                         clk_select = SMU_PIXCLK;
1320                         break;
1321                 case amd_pp_phy_clock:
1322                         clk_select = SMU_PHYCLK;
1323                         break;
1324                 case amd_pp_mem_clock:
1325                         clk_select = SMU_UCLK;
1326                         break;
1327                 default:
1328                         pr_info("[%s] Invalid Clock Type!", __func__);
1329                         ret = -EINVAL;
1330                         break;
1331                 }
1332
1333                 if (ret)
1334                         goto failed;
1335
1336                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1337                         return 0;
1338
1339                 ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0);
1340
1341                 if(clk_select == SMU_UCLK)
1342                         smu->hard_min_uclk_req_from_dal = clk_freq;
1343         }
1344
1345 failed:
1346         return ret;
1347 }
1348
1349 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1350 {
1351         int ret = 0;
1352         struct amdgpu_device *adev = smu->adev;
1353
1354         switch (adev->asic_type) {
1355         case CHIP_VEGA20:
1356                 break;
1357         case CHIP_NAVI10:
1358         case CHIP_NAVI14:
1359         case CHIP_NAVI12:
1360                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1361                         return 0;
1362                 if (enable)
1363                         ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
1364                 else
1365                         ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
1366                 break;
1367         default:
1368                 break;
1369         }
1370
1371         return ret;
1372 }
1373
1374 uint32_t
1375 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1376 {
1377         if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1378                 return AMD_FAN_CTRL_MANUAL;
1379         else
1380                 return AMD_FAN_CTRL_AUTO;
1381 }
1382
1383 static int
1384 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1385 {
1386         int ret = 0;
1387
1388         if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1389                 return 0;
1390
1391         ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1392         if (ret)
1393                 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1394                        __func__, (auto_fan_control ? "Start" : "Stop"));
1395
1396         return ret;
1397 }
1398
1399 static int
1400 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1401 {
1402         struct amdgpu_device *adev = smu->adev;
1403
1404         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1405                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1406                                    CG_FDO_CTRL2, TMIN, 0));
1407         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1408                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1409                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1410
1411         return 0;
1412 }
1413
1414 int
1415 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1416 {
1417         struct amdgpu_device *adev = smu->adev;
1418         uint32_t duty100, duty;
1419         uint64_t tmp64;
1420
1421         if (speed > 100)
1422                 speed = 100;
1423
1424         if (smu_v11_0_auto_fan_control(smu, 0))
1425                 return -EINVAL;
1426
1427         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1428                                 CG_FDO_CTRL1, FMAX_DUTY100);
1429         if (!duty100)
1430                 return -EINVAL;
1431
1432         tmp64 = (uint64_t)speed * duty100;
1433         do_div(tmp64, 100);
1434         duty = (uint32_t)tmp64;
1435
1436         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1437                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1438                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1439
1440         return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1441 }
1442
1443 int
1444 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1445                                uint32_t mode)
1446 {
1447         int ret = 0;
1448
1449         switch (mode) {
1450         case AMD_FAN_CTRL_NONE:
1451                 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1452                 break;
1453         case AMD_FAN_CTRL_MANUAL:
1454                 ret = smu_v11_0_auto_fan_control(smu, 0);
1455                 break;
1456         case AMD_FAN_CTRL_AUTO:
1457                 ret = smu_v11_0_auto_fan_control(smu, 1);
1458                 break;
1459         default:
1460                 break;
1461         }
1462
1463         if (ret) {
1464                 pr_err("[%s]Set fan control mode failed!", __func__);
1465                 return -EINVAL;
1466         }
1467
1468         return ret;
1469 }
1470
1471 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1472                                        uint32_t speed)
1473 {
1474         struct amdgpu_device *adev = smu->adev;
1475         int ret;
1476         uint32_t tach_period, crystal_clock_freq;
1477
1478         if (!speed)
1479                 return -EINVAL;
1480
1481         ret = smu_v11_0_auto_fan_control(smu, 0);
1482         if (ret)
1483                 return ret;
1484
1485         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1486         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1487         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1488                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1489                                    CG_TACH_CTRL, TARGET_PERIOD,
1490                                    tach_period));
1491
1492         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1493
1494         return ret;
1495 }
1496
1497 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1498                                      uint32_t pstate)
1499 {
1500         int ret = 0;
1501         ret = smu_send_smc_msg_with_param(smu,
1502                                           SMU_MSG_SetXgmiMode,
1503                                           pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1504                                           NULL);
1505         return ret;
1506 }
1507
1508 static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
1509 {
1510         return smu_send_smc_msg(smu,
1511                                 SMU_MSG_ReenableAcDcInterrupt,
1512                                 NULL);
1513 }
1514
1515 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1516 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1517
1518 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1519                                  struct amdgpu_irq_src *source,
1520                                  struct amdgpu_iv_entry *entry)
1521 {
1522         uint32_t client_id = entry->client_id;
1523         uint32_t src_id = entry->src_id;
1524
1525         if (client_id == SOC15_IH_CLIENTID_THM) {
1526                 switch (src_id) {
1527                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1528                         pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
1529                                 PCI_BUS_NUM(adev->pdev->devfn),
1530                                 PCI_SLOT(adev->pdev->devfn),
1531                                 PCI_FUNC(adev->pdev->devfn));
1532                 break;
1533                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1534                         pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
1535                                 PCI_BUS_NUM(adev->pdev->devfn),
1536                                 PCI_SLOT(adev->pdev->devfn),
1537                                 PCI_FUNC(adev->pdev->devfn));
1538                 break;
1539                 default:
1540                         pr_warn("GPU under temperature range unknown src id (%d), detected on PCIe %d:%d.%d!\n",
1541                                 src_id,
1542                                 PCI_BUS_NUM(adev->pdev->devfn),
1543                                 PCI_SLOT(adev->pdev->devfn),
1544                                 PCI_FUNC(adev->pdev->devfn));
1545                 break;
1546
1547                 }
1548         } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1549                 if (src_id == 0xfe)
1550                         smu_v11_0_ack_ac_dc_interrupt(&adev->smu);
1551         }
1552
1553         return 0;
1554 }
1555
1556 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1557 {
1558         .process = smu_v11_0_irq_process,
1559 };
1560
1561 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1562 {
1563         struct amdgpu_device *adev = smu->adev;
1564         struct amdgpu_irq_src *irq_src = smu->irq_source;
1565         int ret = 0;
1566
1567         /* already register */
1568         if (irq_src)
1569                 return 0;
1570
1571         irq_src = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
1572         if (!irq_src)
1573                 return -ENOMEM;
1574         smu->irq_source = irq_src;
1575
1576         irq_src->funcs = &smu_v11_0_irq_funcs;
1577
1578         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1579                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1580                                 irq_src);
1581         if (ret)
1582                 return ret;
1583
1584         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1585                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1586                                 irq_src);
1587         if (ret)
1588                 return ret;
1589
1590         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1591                                 0xfe,
1592                                 irq_src);
1593         if (ret)
1594                 return ret;
1595
1596         return ret;
1597 }
1598
1599 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1600                 struct pp_smu_nv_clock_table *max_clocks)
1601 {
1602         struct smu_table_context *table_context = &smu->smu_table;
1603         struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1604
1605         if (!max_clocks || !table_context->max_sustainable_clocks)
1606                 return -EINVAL;
1607
1608         sustainable_clocks = table_context->max_sustainable_clocks;
1609
1610         max_clocks->dcfClockInKhz =
1611                         (unsigned int) sustainable_clocks->dcef_clock * 1000;
1612         max_clocks->displayClockInKhz =
1613                         (unsigned int) sustainable_clocks->display_clock * 1000;
1614         max_clocks->phyClockInKhz =
1615                         (unsigned int) sustainable_clocks->phy_clock * 1000;
1616         max_clocks->pixelClockInKhz =
1617                         (unsigned int) sustainable_clocks->pixel_clock * 1000;
1618         max_clocks->uClockInKhz =
1619                         (unsigned int) sustainable_clocks->uclock * 1000;
1620         max_clocks->socClockInKhz =
1621                         (unsigned int) sustainable_clocks->soc_clock * 1000;
1622         max_clocks->dscClockInKhz = 0;
1623         max_clocks->dppClockInKhz = 0;
1624         max_clocks->fabricClockInKhz = 0;
1625
1626         return 0;
1627 }
1628
1629 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1630 {
1631         int ret = 0;
1632
1633         ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1634
1635         return ret;
1636 }
1637
1638 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1639 {
1640         return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
1641 }
1642
1643 bool smu_v11_0_baco_is_support(struct smu_context *smu)
1644 {
1645         struct smu_baco_context *smu_baco = &smu->smu_baco;
1646         bool baco_support;
1647
1648         mutex_lock(&smu_baco->mutex);
1649         baco_support = smu_baco->platform_support;
1650         mutex_unlock(&smu_baco->mutex);
1651
1652         if (!baco_support)
1653                 return false;
1654
1655         /* Arcturus does not support this bit mask */
1656         if (smu_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1657            !smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1658                 return false;
1659
1660         return true;
1661 }
1662
1663 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1664 {
1665         struct smu_baco_context *smu_baco = &smu->smu_baco;
1666         enum smu_baco_state baco_state;
1667
1668         mutex_lock(&smu_baco->mutex);
1669         baco_state = smu_baco->state;
1670         mutex_unlock(&smu_baco->mutex);
1671
1672         return baco_state;
1673 }
1674
1675 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1676 {
1677         struct smu_baco_context *smu_baco = &smu->smu_baco;
1678         struct amdgpu_device *adev = smu->adev;
1679         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1680         uint32_t data;
1681         int ret = 0;
1682
1683         if (smu_v11_0_baco_get_state(smu) == state)
1684                 return 0;
1685
1686         mutex_lock(&smu_baco->mutex);
1687
1688         if (state == SMU_BACO_STATE_ENTER) {
1689                 if (!ras || !ras->supported) {
1690                         data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1691                         data |= 0x80000000;
1692                         WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1693
1694                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
1695                 } else {
1696                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);
1697                 }
1698         } else {
1699                 ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
1700                 if (ret)
1701                         goto out;
1702
1703                 if (ras && ras->supported) {
1704                         ret = smu_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
1705                         if (ret)
1706                                 goto out;
1707                 }
1708
1709                 /* clear vbios scratch 6 and 7 for coming asic reinit */
1710                 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1711                 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1712         }
1713         if (ret)
1714                 goto out;
1715
1716         smu_baco->state = state;
1717 out:
1718         mutex_unlock(&smu_baco->mutex);
1719         return ret;
1720 }
1721
1722 int smu_v11_0_baco_enter(struct smu_context *smu)
1723 {
1724         struct amdgpu_device *adev = smu->adev;
1725         int ret = 0;
1726
1727         /* Arcturus does not need this audio workaround */
1728         if (adev->asic_type != CHIP_ARCTURUS) {
1729                 ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1730                 if (ret)
1731                         return ret;
1732         }
1733
1734         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1735         if (ret)
1736                 return ret;
1737
1738         msleep(10);
1739
1740         return ret;
1741 }
1742
1743 int smu_v11_0_baco_exit(struct smu_context *smu)
1744 {
1745         int ret = 0;
1746
1747         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1748         if (ret)
1749                 return ret;
1750
1751         return ret;
1752 }
1753
1754 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1755                                                  uint32_t *min, uint32_t *max)
1756 {
1757         int ret = 0, clk_id = 0;
1758         uint32_t param = 0;
1759
1760         clk_id = smu_clk_get_index(smu, clk_type);
1761         if (clk_id < 0) {
1762                 ret = -EINVAL;
1763                 goto failed;
1764         }
1765         param = (clk_id & 0xffff) << 16;
1766
1767         if (max) {
1768                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1769                 if (ret)
1770                         goto failed;
1771         }
1772
1773         if (min) {
1774                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1775                 if (ret)
1776                         goto failed;
1777         }
1778
1779 failed:
1780         return ret;
1781 }
1782
1783 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
1784                             uint32_t min, uint32_t max)
1785 {
1786         int ret = 0, clk_id = 0;
1787         uint32_t param;
1788
1789         clk_id = smu_clk_get_index(smu, clk_type);
1790         if (clk_id < 0)
1791                 return clk_id;
1792
1793         if (max > 0) {
1794                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1795                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1796                                                   param, NULL);
1797                 if (ret)
1798                         return ret;
1799         }
1800
1801         if (min > 0) {
1802                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1803                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1804                                                   param, NULL);
1805                 if (ret)
1806                         return ret;
1807         }
1808
1809         return ret;
1810 }
1811
1812 int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
1813 {
1814         struct amdgpu_device *adev = smu->adev;
1815         uint32_t pcie_gen = 0, pcie_width = 0;
1816         int ret;
1817
1818         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1819                 pcie_gen = 3;
1820         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1821                 pcie_gen = 2;
1822         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1823                 pcie_gen = 1;
1824         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1825                 pcie_gen = 0;
1826
1827         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1828          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1829          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
1830          */
1831         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1832                 pcie_width = 6;
1833         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1834                 pcie_width = 5;
1835         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1836                 pcie_width = 4;
1837         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1838                 pcie_width = 3;
1839         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1840                 pcie_width = 2;
1841         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1842                 pcie_width = 1;
1843
1844         ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1845
1846         if (ret)
1847                 pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
1848
1849         return ret;
1850
1851 }
1852
1853 int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size)
1854 {
1855         struct smu_table_context *table_context = &smu->smu_table;
1856         int ret = 0;
1857
1858         if (initialize) {
1859                 if (table_context->overdrive_table) {
1860                         return -EINVAL;
1861                 }
1862                 table_context->overdrive_table = kzalloc(overdrive_table_size, GFP_KERNEL);
1863                 if (!table_context->overdrive_table) {
1864                         return -ENOMEM;
1865                 }
1866                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
1867                 if (ret) {
1868                         pr_err("Failed to export overdrive table!\n");
1869                         return ret;
1870                 }
1871                 if (!table_context->boot_overdrive_table) {
1872                         table_context->boot_overdrive_table = kmemdup(table_context->overdrive_table, overdrive_table_size, GFP_KERNEL);
1873                         if (!table_context->boot_overdrive_table) {
1874                                 return -ENOMEM;
1875                         }
1876                 }
1877         }
1878         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
1879         if (ret) {
1880                 pr_err("Failed to import overdrive table!\n");
1881                 return ret;
1882         }
1883         return ret;
1884 }
1885
1886 int smu_v11_0_set_performance_level(struct smu_context *smu,
1887                                     enum amd_dpm_forced_level level)
1888 {
1889         int ret = 0;
1890         uint32_t sclk_mask, mclk_mask, soc_mask;
1891
1892         switch (level) {
1893         case AMD_DPM_FORCED_LEVEL_HIGH:
1894                 ret = smu_force_dpm_limit_value(smu, true);
1895                 break;
1896         case AMD_DPM_FORCED_LEVEL_LOW:
1897                 ret = smu_force_dpm_limit_value(smu, false);
1898                 break;
1899         case AMD_DPM_FORCED_LEVEL_AUTO:
1900         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1901                 ret = smu_unforce_dpm_levels(smu);
1902                 break;
1903         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1904         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1905         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1906                 ret = smu_get_profiling_clk_mask(smu, level,
1907                                                  &sclk_mask,
1908                                                  &mclk_mask,
1909                                                  &soc_mask);
1910                 if (ret)
1911                         return ret;
1912                 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1913                 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1914                 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1915                 break;
1916         case AMD_DPM_FORCED_LEVEL_MANUAL:
1917         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1918         default:
1919                 break;
1920         }
1921         return ret;
1922 }
1923
1924 int smu_v11_0_set_power_source(struct smu_context *smu,
1925                                enum smu_power_src_type power_src)
1926 {
1927         int pwr_source;
1928
1929         pwr_source = smu_power_get_index(smu, (uint32_t)power_src);
1930         if (pwr_source < 0)
1931                 return -EINVAL;
1932
1933         return smu_send_smc_msg_with_param(smu,
1934                                         SMU_MSG_NotifyPowerSource,
1935                                         pwr_source,
1936                                         NULL);
1937 }
1938