drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/pci.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_internal.h"
  29 #include "atomfirmware.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "smu_v11_0.h"
  32 #include "smu11_driver_if_sienna_cichlid.h"
  33 #include "soc15_common.h"
  34 #include "atom.h"
  35 #include "sienna_cichlid_ppt.h"
  36 #include "smu_v11_0_7_pptable.h"
  37 #include "smu_v11_0_7_ppsmc.h"
  38 #include "nbio/nbio_2_3_offset.h"
  39 #include "nbio/nbio_2_3_sh_mask.h"
  40 #include "thm/thm_11_0_2_offset.h"
  41 #include "thm/thm_11_0_2_sh_mask.h"
  42
  43 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  44
  45 /*
  46  * DO NOT use these for err/warn/info/debug messages.
  47  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  48  * They are more MGPU friendly.
  49  */
  50 #undef pr_err
  51 #undef pr_warn
  52 #undef pr_info
  53 #undef pr_debug
  54
  55 #define FEATURE_MASK(feature) (1ULL << feature)
  56 #define SMC_DPM_FEATURE ( \
  57         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  58         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  59         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  60         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  61         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  62         FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  63         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  64
  65 #define MSG_MAP(msg, index) \
  66         [SMU_MSG_##msg] = {1, (index)}
  67
  68 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
  69         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
  70         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
  71         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
  72         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow),
  73         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  74         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures),
  75         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures),
  76         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow),
  77         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh),
  78         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow),
  79         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh),
  80         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow),
  81         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh),
  82         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask),
  83         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit),
  84         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
  85         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
  86         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh),
  87         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow),
  88         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
  89         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
  90         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable),
  91         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco),
  92         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq),
  93         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq),
  94         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq),
  95         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq),
  96         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq),
  97         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq),
  98         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex),
  99         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode),
 100         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh),
 101         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow),
 102         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters),
 103         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt),
 104         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource),
 105         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch),
 106         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
 107         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload),
 108         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff),
 109         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff),
 110         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit),
 111         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq),
 112         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco),
 113         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn),
 114         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn),
 115         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg),
 116         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg),
 117         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME),
 118         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3),
 119 };
 120
 121 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
 122         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 123         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 124         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 125         CLK_MAP(FCLK,           PPCLK_FCLK),
 126         CLK_MAP(UCLK,           PPCLK_UCLK),
 127         CLK_MAP(MCLK,           PPCLK_UCLK),
 128         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 129         CLK_MAP(DCLK1,          PPCLK_DCLK_0),
 130         CLK_MAP(VCLK,           PPCLK_VCLK_1),
 131         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 132         CLK_MAP(DCEFCLK,        PPCLK_DCEFCLK),
 133         CLK_MAP(DISPCLK,        PPCLK_DISPCLK),
 134         CLK_MAP(PIXCLK,         PPCLK_PIXCLK),
 135         CLK_MAP(PHYCLK,         PPCLK_PHYCLK),
 136 };
 137
 138 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
 139         FEA_MAP(DPM_PREFETCHER),
 140         FEA_MAP(DPM_GFXCLK),
 141         FEA_MAP(DPM_GFX_GPO),
 142         FEA_MAP(DPM_UCLK),
 143         FEA_MAP(DPM_SOCCLK),
 144         FEA_MAP(DPM_MP0CLK),
 145         FEA_MAP(DPM_LINK),
 146         FEA_MAP(DPM_DCEFCLK),
 147         FEA_MAP(MEM_VDDCI_SCALING),
 148         FEA_MAP(MEM_MVDD_SCALING),
 149         FEA_MAP(DS_GFXCLK),
 150         FEA_MAP(DS_SOCCLK),
 151         FEA_MAP(DS_LCLK),
 152         FEA_MAP(DS_DCEFCLK),
 153         FEA_MAP(DS_UCLK),
 154         FEA_MAP(GFX_ULV),
 155         FEA_MAP(FW_DSTATE),
 156         FEA_MAP(GFXOFF),
 157         FEA_MAP(BACO),
 158         FEA_MAP(MM_DPM_PG),
 159         FEA_MAP(RSMU_SMN_CG),
 160         FEA_MAP(PPT),
 161         FEA_MAP(TDC),
 162         FEA_MAP(APCC_PLUS),
 163         FEA_MAP(GTHR),
 164         FEA_MAP(ACDC),
 165         FEA_MAP(VR0HOT),
 166         FEA_MAP(VR1HOT),
 167         FEA_MAP(FW_CTF),
 168         FEA_MAP(FAN_CONTROL),
 169         FEA_MAP(THERMAL),
 170         FEA_MAP(GFX_DCS),
 171         FEA_MAP(RM),
 172         FEA_MAP(LED_DISPLAY),
 173         FEA_MAP(GFX_SS),
 174         FEA_MAP(OUT_OF_BAND_MONITOR),
 175         FEA_MAP(TEMP_DEPENDENT_VMIN),
 176         FEA_MAP(MMHUB_PG),
 177         FEA_MAP(ATHUB_PG),
 178         FEA_MAP(APCC_DFLL),
 179 };
 180
 181 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
 182         TAB_MAP(PPTABLE),
 183         TAB_MAP(WATERMARKS),
 184         TAB_MAP(AVFS_PSM_DEBUG),
 185         TAB_MAP(AVFS_FUSE_OVERRIDE),
 186         TAB_MAP(PMSTATUSLOG),
 187         TAB_MAP(SMU_METRICS),
 188         TAB_MAP(DRIVER_SMU_CONFIG),
 189         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 190         TAB_MAP(OVERDRIVE),
 191         TAB_MAP(I2C_COMMANDS),
 192         TAB_MAP(PACE),
 193 };
 194
 195 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 196         PWR_MAP(AC),
 197         PWR_MAP(DC),
 198 };
 199
 200 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 201         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 202         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 203         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 204         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 205         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 206         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_CUSTOM_BIT),
 207         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 208 };
 209
 210 static int sienna_cichlid_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 211 {
 212         struct smu_11_0_cmn2aisc_mapping mapping;
 213
 214         if (index >= SMU_MSG_MAX_COUNT)
 215                 return -EINVAL;
 216
 217         mapping = sienna_cichlid_message_map[index];
 218         if (!(mapping.valid_mapping)) {
 219                 return -EINVAL;
 220         }
 221
 222         return mapping.map_to;
 223 }
 224
 225 static int sienna_cichlid_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 226 {
 227         struct smu_11_0_cmn2aisc_mapping mapping;
 228
 229         if (index >= SMU_CLK_COUNT)
 230                 return -EINVAL;
 231
 232         mapping = sienna_cichlid_clk_map[index];
 233         if (!(mapping.valid_mapping)) {
 234                 return -EINVAL;
 235         }
 236
 237         return mapping.map_to;
 238 }
 239
 240 static int sienna_cichlid_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 241 {
 242         struct smu_11_0_cmn2aisc_mapping mapping;
 243
 244         if (index >= SMU_FEATURE_COUNT)
 245                 return -EINVAL;
 246
 247         mapping = sienna_cichlid_feature_mask_map[index];
 248         if (!(mapping.valid_mapping)) {
 249                 return -EINVAL;
 250         }
 251
 252         return mapping.map_to;
 253 }
 254
 255 static int sienna_cichlid_get_smu_table_index(struct smu_context *smc, uint32_t index)
 256 {
 257         struct smu_11_0_cmn2aisc_mapping mapping;
 258
 259         if (index >= SMU_TABLE_COUNT)
 260                 return -EINVAL;
 261
 262         mapping = sienna_cichlid_table_map[index];
 263         if (!(mapping.valid_mapping)) {
 264                 return -EINVAL;
 265         }
 266
 267         return mapping.map_to;
 268 }
 269
 270 static int sienna_cichlid_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 271 {
 272         struct smu_11_0_cmn2aisc_mapping mapping;
 273
 274         if (index >= SMU_POWER_SOURCE_COUNT)
 275                 return -EINVAL;
 276
 277         mapping = sienna_cichlid_pwr_src_map[index];
 278         if (!(mapping.valid_mapping)) {
 279                 return -EINVAL;
 280         }
 281
 282         return mapping.map_to;
 283 }
 284
 285 static int sienna_cichlid_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 286 {
 287         struct smu_11_0_cmn2aisc_mapping mapping;
 288
 289         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 290                 return -EINVAL;
 291
 292         mapping = sienna_cichlid_workload_map[profile];
 293         if (!(mapping.valid_mapping)) {
 294                 return -EINVAL;
 295         }
 296
 297         return mapping.map_to;
 298 }
 299
 300 static int
 301 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 302                                   uint32_t *feature_mask, uint32_t num)
 303 {
 304         struct amdgpu_device *adev = smu->adev;
 305
 306         if (num > 2)
 307                 return -EINVAL;
 308
 309         memset(feature_mask, 0, sizeof(uint32_t) * num);
 310
 311         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 312                                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 313                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 314                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 315                                 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
 316                                 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
 317                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 318                                 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
 319                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 320                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 321                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 322                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 323                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 324                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 325                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 326                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 327                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 328                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 329                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 330
 331         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
 332                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 333                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
 334         }
 335
 336         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 337                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 338                                         | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 339                                         | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 340
 341         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 342                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 343
 344         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 345                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 346
 347         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 348                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 349
 350         if (adev->pm.pp_feature & PP_ULV_MASK)
 351                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 352
 353         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 354                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 355
 356         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 357                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 358
 359         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 360                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 361
 362         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 363                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 364
 365         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
 366             smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 367                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
 368
 369         return 0;
 370 }
 371
 372 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
 373 {
 374         struct smu_table_context *table_context = &smu->smu_table;
 375         struct smu_11_0_7_powerplay_table *powerplay_table =
 376                 table_context->power_play_table;
 377         struct smu_baco_context *smu_baco = &smu->smu_baco;
 378
 379         mutex_lock(&smu_baco->mutex);
 380         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
 381             powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO)
 382                 smu_baco->platform_support = true;
 383         mutex_unlock(&smu_baco->mutex);
 384
 385         table_context->thermal_controller_type =
 386                 powerplay_table->thermal_controller_type;
 387
 388         return 0;
 389 }
 390
 391 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
 392 {
 393         struct smu_table_context *table_context = &smu->smu_table;
 394         PPTable_t *smc_pptable = table_context->driver_pptable;
 395         struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
 396         int index, ret;
 397         int i;
 398
 399         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 400                                             smc_dpm_info);
 401
 402         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 403                                       (uint8_t **)&smc_dpm_table);
 404         if (ret)
 405                 return ret;
 406
 407         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 408                sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
 409
 410         /* SVI2 Board Parameters */
 411         smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
 412         smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
 413         smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
 414         smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
 415         smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
 416         smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
 417         smc_pptable->VddciUlvPhaseSheddingMask = smc_dpm_table->VddciUlvPhaseSheddingMask;
 418         smc_pptable->MvddUlvPhaseSheddingMask = smc_dpm_table->MvddUlvPhaseSheddingMask;
 419
 420         /* Telemetry Settings */
 421         smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
 422         smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
 423         smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
 424         smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
 425         smc_pptable->SocOffset = smc_dpm_table->SocOffset;
 426         smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
 427         smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
 428         smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
 429         smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
 430         smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
 431         smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
 432         smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
 433         smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
 434
 435         /* GPIO Settings */
 436         smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
 437         smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
 438         smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
 439         smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
 440         smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
 441         smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
 442         smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
 443         smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
 444
 445         /* LED Display Settings */
 446         smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
 447         smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
 448         smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
 449         smc_pptable->LedEnableMask = smc_dpm_table->LedEnableMask;
 450         smc_pptable->LedPcie = smc_dpm_table->LedPcie;
 451         smc_pptable->LedError = smc_dpm_table->LedError;
 452         smc_pptable->LedSpare1[0] = smc_dpm_table->LedSpare1[0];
 453         smc_pptable->LedSpare1[1] = smc_dpm_table->LedSpare1[1];
 454
 455         /* GFXCLK PLL Spread Spectrum */
 456         smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
 457         smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
 458         smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
 459
 460         /* GFXCLK DFLL Spread Spectrum */
 461         smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
 462         smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
 463         smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
 464
 465         /* UCLK Spread Spectrum */
 466         smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
 467         smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
 468         smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
 469
 470         /* FCLK Spred Spectrum */
 471         smc_pptable->FclkSpreadEnabled = smc_dpm_table->FclkSpreadEnabled;
 472         smc_pptable->FclkSpreadPercent = smc_dpm_table->FclkSpreadPercent;
 473         smc_pptable->FclkSpreadFreq = smc_dpm_table->FclkSpreadFreq;
 474
 475         /* Memory Config */
 476         smc_pptable->MemoryChannelEnabled = smc_dpm_table->MemoryChannelEnabled;
 477         smc_pptable->DramBitWidth = smc_dpm_table->DramBitWidth;
 478         smc_pptable->PaddingMem1[0] = smc_dpm_table->PaddingMem1[0];
 479         smc_pptable->PaddingMem1[1] = smc_dpm_table->PaddingMem1[1];
 480         smc_pptable->PaddingMem1[2] = smc_dpm_table->PaddingMem1[2];
 481
 482         /* Total board power */
 483         smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
 484         smc_pptable->BoardPowerPadding = smc_dpm_table->BoardPowerPadding;
 485
 486         /* XGMI Training */
 487         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) {
 488                 smc_pptable->XgmiLinkSpeed[i] = smc_dpm_table->XgmiLinkSpeed[i];
 489                 smc_pptable->XgmiLinkWidth[i] = smc_dpm_table->XgmiLinkWidth[i];
 490                 smc_pptable->XgmiFclkFreq[i] = smc_dpm_table->XgmiFclkFreq[i];
 491                 smc_pptable->XgmiSocVoltage[i] = smc_dpm_table->XgmiSocVoltage[i];
 492         }
 493
 494         return 0;
 495 }
 496
 497 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
 498 {
 499         struct smu_table_context *table_context = &smu->smu_table;
 500         struct smu_11_0_7_powerplay_table *powerplay_table =
 501                 table_context->power_play_table;
 502
 503         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 504                sizeof(PPTable_t));
 505
 506         return 0;
 507 }
 508
 509 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
 510 {
 511         int ret = 0;
 512
 513         ret = smu_v11_0_setup_pptable(smu);
 514         if (ret)
 515                 return ret;
 516
 517         ret = sienna_cichlid_store_powerplay_table(smu);
 518         if (ret)
 519                 return ret;
 520
 521         ret = sienna_cichlid_append_powerplay_table(smu);
 522         if (ret)
 523                 return ret;
 524
 525         ret = sienna_cichlid_check_powerplay_table(smu);
 526         if (ret)
 527                 return ret;
 528
 529         return ret;
 530 }
 531
 532 static int sienna_cichlid_tables_init(struct smu_context *smu, struct smu_table *tables)
 533 {
 534         struct smu_table_context *smu_table = &smu->smu_table;
 535
 536         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 537                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 538         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 539                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 540         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 541                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 542         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 543                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 544         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 545                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 546         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 547                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 548                        AMDGPU_GEM_DOMAIN_VRAM);
 549
 550         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 551         if (!smu_table->metrics_table)
 552                 return -ENOMEM;
 553         smu_table->metrics_time = 0;
 554
 555         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 556         if (!smu_table->watermarks_table)
 557                 return -ENOMEM;
 558
 559         return 0;
 560 }
 561
 562 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
 563                                                MetricsMember_t member,
 564                                                uint32_t *value)
 565 {
 566         struct smu_table_context *smu_table= &smu->smu_table;
 567         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 568         int ret = 0;
 569
 570         mutex_lock(&smu->metrics_lock);
 571         if (!smu_table->metrics_time ||
 572              time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) {
 573                 ret = smu_update_table(smu,
 574                                        SMU_TABLE_SMU_METRICS,
 575                                        0,
 576                                        smu_table->metrics_table,
 577                                        false);
 578                 if (ret) {
 579                         dev_info(smu->adev->dev, "Failed to export SMU metrics table!\n");
 580                         mutex_unlock(&smu->metrics_lock);
 581                         return ret;
 582                 }
 583                 smu_table->metrics_time = jiffies;
 584         }
 585
 586         switch (member) {
 587         case METRICS_CURR_GFXCLK:
 588                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 589                 break;
 590         case METRICS_CURR_SOCCLK:
 591                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 592                 break;
 593         case METRICS_CURR_UCLK:
 594                 *value = metrics->CurrClock[PPCLK_UCLK];
 595                 break;
 596         case METRICS_CURR_VCLK:
 597                 *value = metrics->CurrClock[PPCLK_VCLK_0];
 598                 break;
 599         case METRICS_CURR_VCLK1:
 600                 *value = metrics->CurrClock[PPCLK_VCLK_1];
 601                 break;
 602         case METRICS_CURR_DCLK:
 603                 *value = metrics->CurrClock[PPCLK_DCLK_0];
 604                 break;
 605         case METRICS_CURR_DCLK1:
 606                 *value = metrics->CurrClock[PPCLK_DCLK_1];
 607                 break;
 608         case METRICS_AVERAGE_GFXCLK:
 609                 *value = metrics->AverageGfxclkFrequency;
 610                 break;
 611         case METRICS_AVERAGE_FCLK:
 612                 *value = metrics->AverageFclkFrequency;
 613                 break;
 614         case METRICS_AVERAGE_UCLK:
 615                 *value = metrics->AverageUclkFrequency;
 616                 break;
 617         case METRICS_AVERAGE_GFXACTIVITY:
 618                 *value = metrics->AverageGfxActivity;
 619                 break;
 620         case METRICS_AVERAGE_MEMACTIVITY:
 621                 *value = metrics->AverageUclkActivity;
 622                 break;
 623         case METRICS_AVERAGE_SOCKETPOWER:
 624                 *value = metrics->AverageSocketPower << 8;
 625                 break;
 626         case METRICS_TEMPERATURE_EDGE:
 627                 *value = metrics->TemperatureEdge *
 628                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 629                 break;
 630         case METRICS_TEMPERATURE_HOTSPOT:
 631                 *value = metrics->TemperatureHotspot *
 632                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 633                 break;
 634         case METRICS_TEMPERATURE_MEM:
 635                 *value = metrics->TemperatureMem *
 636                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 637                 break;
 638         case METRICS_TEMPERATURE_VRGFX:
 639                 *value = metrics->TemperatureVrGfx *
 640                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 641                 break;
 642         case METRICS_TEMPERATURE_VRSOC:
 643                 *value = metrics->TemperatureVrSoc *
 644                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 645                 break;
 646         case METRICS_THROTTLER_STATUS:
 647                 *value = metrics->ThrottlerStatus;
 648                 break;
 649         case METRICS_CURR_FANSPEED:
 650                 *value = metrics->CurrFanSpeed;
 651                 break;
 652         default:
 653                 *value = UINT_MAX;
 654                 break;
 655         }
 656
 657         mutex_unlock(&smu->metrics_lock);
 658
 659         return ret;
 660
 661 }
 662
 663 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
 664 {
 665         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 666
 667         if (smu_dpm->dpm_context)
 668                 return -EINVAL;
 669
 670         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 671                                        GFP_KERNEL);
 672         if (!smu_dpm->dpm_context)
 673                 return -ENOMEM;
 674
 675         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 676
 677         return 0;
 678 }
 679
 680 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 681 {
 682         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 683         struct smu_table_context *table_context = &smu->smu_table;
 684         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 685         PPTable_t *driver_ppt = NULL;
 686         int i;
 687
 688         driver_ppt = table_context->driver_pptable;
 689
 690         dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
 691         dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
 692
 693         dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
 694         dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
 695
 696         dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
 697         dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
 698
 699         dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
 700         dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
 701
 702         dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
 703         dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
 704
 705         dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
 706         dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
 707
 708         dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
 709         dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
 710
 711         dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
 712         dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
 713
 714         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
 715         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
 716
 717         for (i = 0; i < MAX_PCIE_CONF; i++) {
 718                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
 719                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
 720         }
 721
 722         return 0;
 723 }
 724
 725 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 726 {
 727         struct smu_power_context *smu_power = &smu->smu_power;
 728         struct smu_power_gate *power_gate = &smu_power->power_gate;
 729         int ret = 0;
 730
 731         if (enable) {
 732                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 733                 if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 734                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
 735                         if (ret)
 736                                 return ret;
 737                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0x10000, NULL);
 738                         if (ret)
 739                                 return ret;
 740                 }
 741                 power_gate->vcn_gated = false;
 742         } else {
 743                 if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 744                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
 745                         if (ret)
 746                                 return ret;
 747                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0x10000, NULL);
 748                         if (ret)
 749                                 return ret;
 750                 }
 751                 power_gate->vcn_gated = true;
 752         }
 753
 754         return ret;
 755 }
 756
 757 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 758 {
 759         struct smu_power_context *smu_power = &smu->smu_power;
 760         struct smu_power_gate *power_gate = &smu_power->power_gate;
 761         int ret = 0;
 762
 763         if (enable) {
 764                 if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 765                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
 766                         if (ret)
 767                                 return ret;
 768                 }
 769                 power_gate->jpeg_gated = false;
 770         } else {
 771                 if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 772                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 773                         if (ret)
 774                                 return ret;
 775                 }
 776                 power_gate->jpeg_gated = true;
 777         }
 778
 779         return ret;
 780 }
 781
 782 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
 783                                        enum smu_clk_type clk_type,
 784                                        uint32_t *value)
 785 {
 786         MetricsMember_t member_type;
 787         int clk_id = 0;
 788
 789         clk_id = smu_clk_get_index(smu, clk_type);
 790         if (clk_id < 0)
 791                 return clk_id;
 792
 793         switch (clk_id) {
 794         case PPCLK_GFXCLK:
 795                 member_type = METRICS_CURR_GFXCLK;
 796                 break;
 797         case PPCLK_UCLK:
 798                 member_type = METRICS_CURR_UCLK;
 799                 break;
 800         case PPCLK_SOCCLK:
 801                 member_type = METRICS_CURR_SOCCLK;
 802                 break;
 803         case PPCLK_FCLK:
 804                 member_type = METRICS_CURR_FCLK;
 805                 break;
 806         case PPCLK_VCLK_0:
 807                 member_type = METRICS_CURR_VCLK;
 808                 break;
 809         case PPCLK_VCLK_1:
 810                 member_type = METRICS_CURR_VCLK1;
 811                 break;
 812         case PPCLK_DCLK_0:
 813                 member_type = METRICS_CURR_DCLK;
 814                 break;
 815         case PPCLK_DCLK_1:
 816                 member_type = METRICS_CURR_DCLK1;
 817                 break;
 818         case PPCLK_DCEFCLK:
 819                 member_type = METRICS_CURR_DCEFCLK;
 820                 break;
 821         default:
 822                 return -EINVAL;
 823         }
 824
 825         return sienna_cichlid_get_smu_metrics_data(smu,
 826                                                    member_type,
 827                                                    value);
 828
 829 }
 830
 831 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 832 {
 833         PPTable_t *pptable = smu->smu_table.driver_pptable;
 834         DpmDescriptor_t *dpm_desc = NULL;
 835         uint32_t clk_index = 0;
 836
 837         clk_index = smu_clk_get_index(smu, clk_type);
 838         dpm_desc = &pptable->DpmDescriptor[clk_index];
 839
 840         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 841         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 842 }
 843
 844 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
 845                         enum smu_clk_type clk_type, char *buf)
 846 {
 847         struct amdgpu_device *adev = smu->adev;
 848         struct smu_table_context *table_context = &smu->smu_table;
 849         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 850         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 851         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 852         int i, size = 0, ret = 0;
 853         uint32_t cur_value = 0, value = 0, count = 0;
 854         uint32_t freq_values[3] = {0};
 855         uint32_t mark_index = 0;
 856         uint32_t gen_speed, lane_width;
 857
 858         switch (clk_type) {
 859         case SMU_GFXCLK:
 860         case SMU_SCLK:
 861         case SMU_SOCCLK:
 862         case SMU_MCLK:
 863         case SMU_UCLK:
 864         case SMU_FCLK:
 865         case SMU_DCEFCLK:
 866                 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
 867                 if (ret)
 868                         goto print_clk_out;
 869
 870                 /* 10KHz -> MHz */
 871                 cur_value = cur_value / 100;
 872
 873                 /* no need to disable gfxoff when retrieving the current gfxclk */
 874                 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
 875                         amdgpu_gfx_off_ctrl(adev, false);
 876
 877                 ret = smu_get_dpm_level_count(smu, clk_type, &count);
 878                 if (ret)
 879                         goto print_clk_out;
 880
 881                 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
 882                         for (i = 0; i < count; i++) {
 883                                 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
 884                                 if (ret)
 885                                         goto print_clk_out;
 886
 887                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 888                                                 cur_value == value ? "*" : "");
 889                         }
 890                 } else {
 891                         ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 892                         if (ret)
 893                                 goto print_clk_out;
 894                         ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 895                         if (ret)
 896                                 goto print_clk_out;
 897
 898                         freq_values[1] = cur_value;
 899                         mark_index = cur_value == freq_values[0] ? 0 :
 900                                      cur_value == freq_values[2] ? 2 : 1;
 901                         if (mark_index != 1)
 902                                 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
 903
 904                         for (i = 0; i < 3; i++) {
 905                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 906                                                 i == mark_index ? "*" : "");
 907                         }
 908
 909                 }
 910                 break;
 911         case SMU_PCIE:
 912                 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
 913                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
 914                         >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
 915                 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
 916                               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
 917                         >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
 918                 for (i = 0; i < NUM_LINK_LEVELS; i++)
 919                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 920                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
 921                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
 922                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
 923                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
 924                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
 925                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
 926                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
 927                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
 928                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
 929                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
 930                                         pptable->LclkFreq[i],
 931                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
 932                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
 933                                         "*" : "");
 934                 break;
 935         default:
 936                 break;
 937         }
 938
 939 print_clk_out:
 940         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
 941                 amdgpu_gfx_off_ctrl(adev, true);
 942
 943         return size;
 944 }
 945
 946 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
 947                                    enum smu_clk_type clk_type, uint32_t mask)
 948 {
 949         struct amdgpu_device *adev = smu->adev;
 950         int ret = 0, size = 0;
 951         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 952
 953         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 954         soft_max_level = mask ? (fls(mask) - 1) : 0;
 955
 956         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
 957                 amdgpu_gfx_off_ctrl(adev, false);
 958
 959         switch (clk_type) {
 960         case SMU_GFXCLK:
 961         case SMU_SCLK:
 962         case SMU_SOCCLK:
 963         case SMU_MCLK:
 964         case SMU_UCLK:
 965         case SMU_DCEFCLK:
 966         case SMU_FCLK:
 967                 /* There is only 2 levels for fine grained DPM */
 968                 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
 969                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
 970                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
 971                 }
 972
 973                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
 974                 if (ret)
 975                         goto forec_level_out;
 976
 977                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
 978                 if (ret)
 979                         goto forec_level_out;
 980
 981                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
 982                 if (ret)
 983                         goto forec_level_out;
 984                 break;
 985         default:
 986                 break;
 987         }
 988
 989 forec_level_out:
 990         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
 991                 amdgpu_gfx_off_ctrl(adev, true);
 992
 993         return size;
 994 }
 995
 996 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
 997 {
 998         int ret = 0;
 999         uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
1000
1001         ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
1002         if (ret)
1003                 return ret;
1004
1005         smu->pstate_sclk = min_sclk_freq * 100;
1006
1007         ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
1008         if (ret)
1009                 return ret;
1010
1011         smu->pstate_mclk = min_mclk_freq * 100;
1012
1013         return ret;
1014 }
1015
1016 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1017 {
1018         int ret = 0;
1019         uint32_t max_freq = 0;
1020
1021         /* Sienna_Cichlid do not support to change display num currently */
1022         return 0;
1023 #if 0
1024         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1025         if (ret)
1026                 return ret;
1027 #endif
1028
1029         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1030                 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
1031                 if (ret)
1032                         return ret;
1033                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
1034                 if (ret)
1035                         return ret;
1036         }
1037
1038         return ret;
1039 }
1040
1041 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1042 {
1043         int ret = 0;
1044
1045         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1046             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1047             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1048 #if 0
1049                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1050                                                   smu->display_config->num_display,
1051                                                   NULL);
1052 #endif
1053                 if (ret)
1054                         return ret;
1055         }
1056
1057         return ret;
1058 }
1059
1060 static int sienna_cichlid_force_dpm_limit_value(struct smu_context *smu, bool highest)
1061 {
1062         int ret = 0, i = 0;
1063         uint32_t min_freq, max_freq, force_freq;
1064         enum smu_clk_type clk_type;
1065
1066         enum smu_clk_type clks[] = {
1067                 SMU_GFXCLK,
1068                 SMU_MCLK,
1069                 SMU_SOCCLK,
1070         };
1071
1072         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1073                 clk_type = clks[i];
1074                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
1075                 if (ret)
1076                         return ret;
1077
1078                 force_freq = highest ? max_freq : min_freq;
1079                 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq, false);
1080                 if (ret)
1081                         return ret;
1082         }
1083
1084         return ret;
1085 }
1086
1087 static int sienna_cichlid_unforce_dpm_levels(struct smu_context *smu)
1088 {
1089         int ret = 0, i = 0;
1090         uint32_t min_freq, max_freq;
1091         enum smu_clk_type clk_type;
1092
1093         enum smu_clk_type clks[] = {
1094                 SMU_GFXCLK,
1095                 SMU_MCLK,
1096                 SMU_SOCCLK,
1097         };
1098
1099         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1100                 clk_type = clks[i];
1101                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
1102                 if (ret)
1103                         return ret;
1104
1105                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
1106                 if (ret)
1107                         return ret;
1108         }
1109
1110         return ret;
1111 }
1112
1113 static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
1114 {
1115         if (!value)
1116                 return -EINVAL;
1117
1118         return sienna_cichlid_get_smu_metrics_data(smu,
1119                                                    METRICS_AVERAGE_SOCKETPOWER,
1120                                                    value);
1121 }
1122
1123 static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
1124                                                enum amd_pp_sensors sensor,
1125                                                uint32_t *value)
1126 {
1127         int ret = 0;
1128
1129         if (!value)
1130                 return -EINVAL;
1131
1132         switch (sensor) {
1133         case AMDGPU_PP_SENSOR_GPU_LOAD:
1134                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1135                                                           METRICS_AVERAGE_GFXACTIVITY,
1136                                                           value);
1137                 break;
1138         case AMDGPU_PP_SENSOR_MEM_LOAD:
1139                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1140                                                           METRICS_AVERAGE_MEMACTIVITY,
1141                                                           value);
1142                 break;
1143         default:
1144                 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1145                 return -EINVAL;
1146         }
1147
1148         return ret;
1149 }
1150
1151 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1152 {
1153         int ret = 0;
1154         uint32_t feature_mask[2];
1155         unsigned long feature_enabled;
1156         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1157         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1158                            ((uint64_t)feature_mask[1] << 32));
1159         return !!(feature_enabled & SMC_DPM_FEATURE);
1160 }
1161
1162 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1163                                     uint32_t *speed)
1164 {
1165         if (!speed)
1166                 return -EINVAL;
1167
1168         return sienna_cichlid_get_smu_metrics_data(smu,
1169                                                    METRICS_CURR_FANSPEED,
1170                                                    speed);
1171 }
1172
1173 static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
1174                                         uint32_t *speed)
1175 {
1176         int ret = 0;
1177         uint32_t percent = 0;
1178         uint32_t current_rpm;
1179         PPTable_t *pptable = smu->smu_table.driver_pptable;
1180
1181         ret = sienna_cichlid_get_fan_speed_rpm(smu, &current_rpm);
1182         if (ret)
1183                 return ret;
1184
1185         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1186         *speed = percent > 100 ? 100 : percent;
1187
1188         return ret;
1189 }
1190
1191 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1192 {
1193         DpmActivityMonitorCoeffInt_t activity_monitor;
1194         uint32_t i, size = 0;
1195         int16_t workload_type = 0;
1196         static const char *profile_name[] = {
1197                                         "BOOTUP_DEFAULT",
1198                                         "3D_FULL_SCREEN",
1199                                         "POWER_SAVING",
1200                                         "VIDEO",
1201                                         "VR",
1202                                         "COMPUTE",
1203                                         "CUSTOM"};
1204         static const char *title[] = {
1205                         "PROFILE_INDEX(NAME)",
1206                         "CLOCK_TYPE(NAME)",
1207                         "FPS",
1208                         "MinFreqType",
1209                         "MinActiveFreqType",
1210                         "MinActiveFreq",
1211                         "BoosterFreqType",
1212                         "BoosterFreq",
1213                         "PD_Data_limit_c",
1214                         "PD_Data_error_coeff",
1215                         "PD_Data_error_rate_coeff"};
1216         int result = 0;
1217
1218         if (!buf)
1219                 return -EINVAL;
1220
1221         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1222                         title[0], title[1], title[2], title[3], title[4], title[5],
1223                         title[6], title[7], title[8], title[9], title[10]);
1224
1225         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1226                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1227                 workload_type = smu_workload_get_type(smu, i);
1228                 if (workload_type < 0)
1229                         return -EINVAL;
1230
1231                 result = smu_update_table(smu,
1232                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1233                                           (void *)(&activity_monitor), false);
1234                 if (result) {
1235                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1236                         return result;
1237                 }
1238
1239                 size += sprintf(buf + size, "%2d %14s%s:\n",
1240                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1241
1242                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1243                         " ",
1244                         0,
1245                         "GFXCLK",
1246                         activity_monitor.Gfx_FPS,
1247                         activity_monitor.Gfx_MinFreqStep,
1248                         activity_monitor.Gfx_MinActiveFreqType,
1249                         activity_monitor.Gfx_MinActiveFreq,
1250                         activity_monitor.Gfx_BoosterFreqType,
1251                         activity_monitor.Gfx_BoosterFreq,
1252                         activity_monitor.Gfx_PD_Data_limit_c,
1253                         activity_monitor.Gfx_PD_Data_error_coeff,
1254                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1255
1256                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1257                         " ",
1258                         1,
1259                         "SOCCLK",
1260                         activity_monitor.Fclk_FPS,
1261                         activity_monitor.Fclk_MinFreqStep,
1262                         activity_monitor.Fclk_MinActiveFreqType,
1263                         activity_monitor.Fclk_MinActiveFreq,
1264                         activity_monitor.Fclk_BoosterFreqType,
1265                         activity_monitor.Fclk_BoosterFreq,
1266                         activity_monitor.Fclk_PD_Data_limit_c,
1267                         activity_monitor.Fclk_PD_Data_error_coeff,
1268                         activity_monitor.Fclk_PD_Data_error_rate_coeff);
1269
1270                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1271                         " ",
1272                         2,
1273                         "MEMLK",
1274                         activity_monitor.Mem_FPS,
1275                         activity_monitor.Mem_MinFreqStep,
1276                         activity_monitor.Mem_MinActiveFreqType,
1277                         activity_monitor.Mem_MinActiveFreq,
1278                         activity_monitor.Mem_BoosterFreqType,
1279                         activity_monitor.Mem_BoosterFreq,
1280                         activity_monitor.Mem_PD_Data_limit_c,
1281                         activity_monitor.Mem_PD_Data_error_coeff,
1282                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1283         }
1284
1285         return size;
1286 }
1287
1288 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1289 {
1290         DpmActivityMonitorCoeffInt_t activity_monitor;
1291         int workload_type, ret = 0;
1292
1293         smu->power_profile_mode = input[size];
1294
1295         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1296                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1297                 return -EINVAL;
1298         }
1299
1300         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1301
1302                 ret = smu_update_table(smu,
1303                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1304                                        (void *)(&activity_monitor), false);
1305                 if (ret) {
1306                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1307                         return ret;
1308                 }
1309
1310                 switch (input[0]) {
1311                 case 0: /* Gfxclk */
1312                         activity_monitor.Gfx_FPS = input[1];
1313                         activity_monitor.Gfx_MinFreqStep = input[2];
1314                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1315                         activity_monitor.Gfx_MinActiveFreq = input[4];
1316                         activity_monitor.Gfx_BoosterFreqType = input[5];
1317                         activity_monitor.Gfx_BoosterFreq = input[6];
1318                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1319                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1320                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1321                         break;
1322                 case 1: /* Socclk */
1323                         activity_monitor.Fclk_FPS = input[1];
1324                         activity_monitor.Fclk_MinFreqStep = input[2];
1325                         activity_monitor.Fclk_MinActiveFreqType = input[3];
1326                         activity_monitor.Fclk_MinActiveFreq = input[4];
1327                         activity_monitor.Fclk_BoosterFreqType = input[5];
1328                         activity_monitor.Fclk_BoosterFreq = input[6];
1329                         activity_monitor.Fclk_PD_Data_limit_c = input[7];
1330                         activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1331                         activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1332                         break;
1333                 case 2: /* Memlk */
1334                         activity_monitor.Mem_FPS = input[1];
1335                         activity_monitor.Mem_MinFreqStep = input[2];
1336                         activity_monitor.Mem_MinActiveFreqType = input[3];
1337                         activity_monitor.Mem_MinActiveFreq = input[4];
1338                         activity_monitor.Mem_BoosterFreqType = input[5];
1339                         activity_monitor.Mem_BoosterFreq = input[6];
1340                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1341                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1342                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1343                         break;
1344                 }
1345
1346                 ret = smu_update_table(smu,
1347                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1348                                        (void *)(&activity_monitor), true);
1349                 if (ret) {
1350                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1351                         return ret;
1352                 }
1353         }
1354
1355         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1356         workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1357         if (workload_type < 0)
1358                 return -EINVAL;
1359         smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1360                                     1 << workload_type, NULL);
1361
1362         return ret;
1363 }
1364
1365 static int sienna_cichlid_get_profiling_clk_mask(struct smu_context *smu,
1366                                          enum amd_dpm_forced_level level,
1367                                          uint32_t *sclk_mask,
1368                                          uint32_t *mclk_mask,
1369                                          uint32_t *soc_mask)
1370 {
1371         struct amdgpu_device *adev = smu->adev;
1372         int ret = 0;
1373         uint32_t level_count = 0;
1374
1375         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1376                 if (sclk_mask)
1377                         *sclk_mask = 0;
1378         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1379                 if (mclk_mask)
1380                         *mclk_mask = 0;
1381         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1382                 if(sclk_mask) {
1383                         amdgpu_gfx_off_ctrl(adev, false);
1384                         ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1385                         amdgpu_gfx_off_ctrl(adev, true);
1386                         if (ret)
1387                                 return ret;
1388                         *sclk_mask = level_count - 1;
1389                 }
1390
1391                 if(mclk_mask) {
1392                         ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1393                         if (ret)
1394                                 return ret;
1395                         *mclk_mask = level_count - 1;
1396                 }
1397
1398                 if(soc_mask) {
1399                         ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1400                         if (ret)
1401                                 return ret;
1402                         *soc_mask = level_count - 1;
1403                 }
1404         }
1405
1406         return ret;
1407 }
1408
1409 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1410 {
1411         struct smu_clocks min_clocks = {0};
1412         struct pp_display_clock_request clock_req;
1413         int ret = 0;
1414
1415         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1416         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1417         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1418
1419         if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1420                 clock_req.clock_type = amd_pp_dcef_clock;
1421                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1422
1423                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1424                 if (!ret) {
1425                         if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1426                                 ret = smu_send_smc_msg_with_param(smu,
1427                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1428                                                                   min_clocks.dcef_clock_in_sr/100,
1429                                                                   NULL);
1430                                 if (ret) {
1431                                         dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1432                                         return ret;
1433                                 }
1434                         }
1435                 } else {
1436                         dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1437                 }
1438         }
1439
1440         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1441                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1442                 if (ret) {
1443                         dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1444                         return ret;
1445                 }
1446         }
1447
1448         return 0;
1449 }
1450
1451 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1452                                        void *watermarks, struct
1453                                        dm_pp_wm_sets_with_clock_ranges_soc15
1454                                        *clock_ranges)
1455 {
1456         int i;
1457         int ret = 0;
1458         Watermarks_t *table = watermarks;
1459
1460         if (!table || !clock_ranges)
1461                 return -EINVAL;
1462
1463         if (clock_ranges->num_wm_dmif_sets > 4 ||
1464             clock_ranges->num_wm_mcif_sets > 4)
1465                 return -EINVAL;
1466
1467         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1468                 table->WatermarkRow[1][i].MinClock =
1469                         cpu_to_le16((uint16_t)
1470                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1471                         1000));
1472                 table->WatermarkRow[1][i].MaxClock =
1473                         cpu_to_le16((uint16_t)
1474                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1475                         1000));
1476                 table->WatermarkRow[1][i].MinUclk =
1477                         cpu_to_le16((uint16_t)
1478                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1479                         1000));
1480                 table->WatermarkRow[1][i].MaxUclk =
1481                         cpu_to_le16((uint16_t)
1482                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1483                         1000));
1484                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1485                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1486         }
1487
1488         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1489                 table->WatermarkRow[0][i].MinClock =
1490                         cpu_to_le16((uint16_t)
1491                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1492                         1000));
1493                 table->WatermarkRow[0][i].MaxClock =
1494                         cpu_to_le16((uint16_t)
1495                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1496                         1000));
1497                 table->WatermarkRow[0][i].MinUclk =
1498                         cpu_to_le16((uint16_t)
1499                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1500                         1000));
1501                 table->WatermarkRow[0][i].MaxUclk =
1502                         cpu_to_le16((uint16_t)
1503                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1504                         1000));
1505                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1506                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1507         }
1508
1509         smu->watermarks_bitmap |= WATERMARKS_EXIST;
1510
1511         if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1512                 ret = smu_write_watermarks_table(smu);
1513                 if (ret) {
1514                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1515                         return ret;
1516                 }
1517                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1518         }
1519
1520         return 0;
1521 }
1522
1523 static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
1524                                              enum amd_pp_sensors sensor,
1525                                              uint32_t *value)
1526 {
1527         int ret = 0;
1528
1529         if (!value)
1530                 return -EINVAL;
1531
1532         switch (sensor) {
1533         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1534                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1535                                                           METRICS_TEMPERATURE_HOTSPOT,
1536                                                           value);
1537                 break;
1538         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1539                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1540                                                           METRICS_TEMPERATURE_EDGE,
1541                                                           value);
1542                 break;
1543         case AMDGPU_PP_SENSOR_MEM_TEMP:
1544                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1545                                                           METRICS_TEMPERATURE_MEM,
1546                                                           value);
1547                 break;
1548         default:
1549                 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1550                 return -EINVAL;
1551         }
1552
1553         return ret;
1554 }
1555
1556 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1557                                  enum amd_pp_sensors sensor,
1558                                  void *data, uint32_t *size)
1559 {
1560         int ret = 0;
1561         struct smu_table_context *table_context = &smu->smu_table;
1562         PPTable_t *pptable = table_context->driver_pptable;
1563
1564         if(!data || !size)
1565                 return -EINVAL;
1566
1567         mutex_lock(&smu->sensor_lock);
1568         switch (sensor) {
1569         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1570                 *(uint32_t *)data = pptable->FanMaximumRpm;
1571                 *size = 4;
1572                 break;
1573         case AMDGPU_PP_SENSOR_MEM_LOAD:
1574         case AMDGPU_PP_SENSOR_GPU_LOAD:
1575                 ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1576                 *size = 4;
1577                 break;
1578         case AMDGPU_PP_SENSOR_GPU_POWER:
1579                 ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
1580                 *size = 4;
1581                 break;
1582         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1583         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1584         case AMDGPU_PP_SENSOR_MEM_TEMP:
1585                 ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1586                 *size = 4;
1587                 break;
1588         default:
1589                 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1590         }
1591         mutex_unlock(&smu->sensor_lock);
1592
1593         return ret;
1594 }
1595
1596 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1597 {
1598         uint32_t num_discrete_levels = 0;
1599         uint16_t *dpm_levels = NULL;
1600         uint16_t i = 0;
1601         struct smu_table_context *table_context = &smu->smu_table;
1602         PPTable_t *driver_ppt = NULL;
1603
1604         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1605                 return -EINVAL;
1606
1607         driver_ppt = table_context->driver_pptable;
1608         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1609         dpm_levels = driver_ppt->FreqTableUclk;
1610
1611         if (num_discrete_levels == 0 || dpm_levels == NULL)
1612                 return -EINVAL;
1613
1614         *num_states = num_discrete_levels;
1615         for (i = 0; i < num_discrete_levels; i++) {
1616                 /* convert to khz */
1617                 *clocks_in_khz = (*dpm_levels) * 1000;
1618                 clocks_in_khz++;
1619                 dpm_levels++;
1620         }
1621
1622         return 0;
1623 }
1624
1625 static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1626                                         enum amd_dpm_forced_level level);
1627
1628 static int sienna_cichlid_set_standard_performance_level(struct smu_context *smu)
1629 {
1630         struct amdgpu_device *adev = smu->adev;
1631         int ret = 0;
1632         uint32_t sclk_freq = 0, uclk_freq = 0;
1633
1634         switch (adev->asic_type) {
1635         /* TODO: need to set specify clk value by asic type, not support yet*/
1636         default:
1637                 /* by default, this is same as auto performance level */
1638                 return sienna_cichlid_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
1639         }
1640
1641         ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
1642         if (ret)
1643                 return ret;
1644         ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
1645         if (ret)
1646                 return ret;
1647
1648         return ret;
1649 }
1650
1651 static int sienna_cichlid_set_peak_performance_level(struct smu_context *smu)
1652 {
1653         int ret = 0;
1654
1655         /* TODO: not support yet*/
1656         return ret;
1657 }
1658
1659 static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1660                                         enum amd_dpm_forced_level level)
1661 {
1662         int ret = 0;
1663         uint32_t sclk_mask, mclk_mask, soc_mask;
1664
1665         switch (level) {
1666         case AMD_DPM_FORCED_LEVEL_HIGH:
1667                 ret = smu_force_dpm_limit_value(smu, true);
1668                 break;
1669         case AMD_DPM_FORCED_LEVEL_LOW:
1670                 ret = smu_force_dpm_limit_value(smu, false);
1671                 break;
1672         case AMD_DPM_FORCED_LEVEL_AUTO:
1673                 ret = smu_unforce_dpm_levels(smu);
1674                 break;
1675         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1676                 ret = sienna_cichlid_set_standard_performance_level(smu);
1677                 break;
1678         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1679         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1680                 ret = smu_get_profiling_clk_mask(smu, level,
1681                                                  &sclk_mask,
1682                                                  &mclk_mask,
1683                                                  &soc_mask);
1684                 if (ret)
1685                         return ret;
1686                 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1687                 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1688                 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1689                 break;
1690         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1691                 ret = sienna_cichlid_set_peak_performance_level(smu);
1692                 break;
1693         case AMD_DPM_FORCED_LEVEL_MANUAL:
1694         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1695         default:
1696                 break;
1697         }
1698         return ret;
1699 }
1700
1701 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1702                                                 struct smu_temperature_range *range)
1703 {
1704         struct smu_table_context *table_context = &smu->smu_table;
1705         struct smu_11_0_7_powerplay_table *powerplay_table = table_context->power_play_table;
1706
1707         if (!range || !powerplay_table)
1708                 return -EINVAL;
1709
1710         range->max = powerplay_table->software_shutdown_temp *
1711                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1712
1713         return 0;
1714 }
1715
1716 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1717                                                 bool disable_memory_clock_switch)
1718 {
1719         int ret = 0;
1720         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1721                 (struct smu_11_0_max_sustainable_clocks *)
1722                         smu->smu_table.max_sustainable_clocks;
1723         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1724         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1725
1726         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1727                 return 0;
1728
1729         if(disable_memory_clock_switch)
1730                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1731         else
1732                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1733
1734         if(!ret)
1735                 smu->disable_uclk_switch = disable_memory_clock_switch;
1736
1737         return ret;
1738 }
1739
1740 static int sienna_cichlid_get_power_limit(struct smu_context *smu)
1741 {
1742         struct smu_11_0_7_powerplay_table *powerplay_table =
1743                 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
1744         PPTable_t *pptable = smu->smu_table.driver_pptable;
1745         uint32_t power_limit, od_percent;
1746
1747         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1748                 /* the last hope to figure out the ppt limit */
1749                 if (!pptable) {
1750                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1751                         return -EINVAL;
1752                 }
1753                 power_limit =
1754                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1755         }
1756         smu->current_power_limit = power_limit;
1757
1758         if (smu->od_enabled) {
1759                 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1760
1761                 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1762
1763                 power_limit *= (100 + od_percent);
1764                 power_limit /= 100;
1765         }
1766         smu->max_power_limit = power_limit;
1767
1768         return 0;
1769 }
1770
1771 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1772                                          uint32_t pcie_gen_cap,
1773                                          uint32_t pcie_width_cap)
1774 {
1775         PPTable_t *pptable = smu->smu_table.driver_pptable;
1776         int ret, i;
1777         uint32_t smu_pcie_arg;
1778
1779         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1780         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1781
1782         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1783                 smu_pcie_arg = (i << 16) |
1784                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
1785                                         (pptable->PcieGenSpeed[i] << 8) :
1786                                         (pcie_gen_cap << 8)) |
1787                         ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1788                                         pptable->PcieLaneCount[i] :
1789                                         pcie_width_cap);
1790
1791                 ret = smu_send_smc_msg_with_param(smu,
1792                                           SMU_MSG_OverridePcieParameters,
1793                                           smu_pcie_arg,
1794                                           NULL);
1795
1796                 if (ret)
1797                         return ret;
1798
1799                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1800                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1801                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1802                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1803         }
1804
1805         return 0;
1806 }
1807
1808 int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
1809                                 enum smu_clk_type clk_type,
1810                                 uint32_t *min, uint32_t *max)
1811 {
1812         struct amdgpu_device *adev = smu->adev;
1813         int ret;
1814
1815         if (clk_type == SMU_GFXCLK)
1816                 amdgpu_gfx_off_ctrl(adev, false);
1817         ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1818         if (clk_type == SMU_GFXCLK)
1819                 amdgpu_gfx_off_ctrl(adev, true);
1820
1821         return ret;
1822 }
1823
1824 int sienna_cichlid_set_soft_freq_limited_range(struct smu_context *smu,
1825                                       enum smu_clk_type clk_type,
1826                                       uint32_t min, uint32_t max)
1827 {
1828         struct amdgpu_device *adev = smu->adev;
1829         int ret;
1830
1831         if (clk_type == SMU_GFXCLK)
1832                 amdgpu_gfx_off_ctrl(adev, false);
1833         ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min, max);
1834         if (clk_type == SMU_GFXCLK)
1835                 amdgpu_gfx_off_ctrl(adev, true);
1836
1837         return ret;
1838 }
1839
1840 static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
1841 {
1842         struct amdgpu_device *adev = smu->adev;
1843         uint32_t val;
1844
1845         if (!smu_v11_0_baco_is_support(smu))
1846                 return false;
1847
1848         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1849         return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
1850 }
1851
1852 static int sienna_cichlid_set_thermal_range(struct smu_context *smu,
1853                                        struct smu_temperature_range range)
1854 {
1855         struct amdgpu_device *adev = smu->adev;
1856         int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
1857         int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
1858         uint32_t val;
1859         struct smu_table_context *table_context = &smu->smu_table;
1860         struct smu_11_0_7_powerplay_table *powerplay_table = table_context->power_play_table;
1861
1862         low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1863                         range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1864         high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp);
1865
1866         if (low > high)
1867                 return -EINVAL;
1868
1869         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1870         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1871         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1872         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1873         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1874         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1875         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1876         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1877
1878         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1879
1880         return 0;
1881 }
1882
1883 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1884 {
1885         struct smu_table_context *table_context = &smu->smu_table;
1886         PPTable_t *pptable = table_context->driver_pptable;
1887         int i;
1888
1889         dev_info(smu->adev->dev, "Dumped PPTable:\n");
1890
1891         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1892         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1893         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1894
1895         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1896                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1897                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1898                 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1899                 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
1900         }
1901
1902         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
1903                 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1904                 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
1905         }
1906
1907         for (i = 0; i < TEMP_COUNT; i++) {
1908                 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
1909         }
1910
1911         dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
1912         dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1913         dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1914         dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1915         dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
1916
1917         dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
1918         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
1919                 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1920                 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
1921         }
1922         dev_info(smu->adev->dev, "PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]);
1923         dev_info(smu->adev->dev, "PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]);
1924         dev_info(smu->adev->dev, "PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]);
1925         dev_info(smu->adev->dev, "PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]);
1926
1927         dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1928
1929         dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1930
1931         dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1932         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1933         dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1934         dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1935
1936         dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1937         dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1938
1939         dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1940         dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1941         dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1942         dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1943
1944         dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1945         dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1946         dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1947         dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1948
1949         dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1950         dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1951
1952         dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1953         dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1954         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1955         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1956         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1957         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1958         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1959         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1960
1961         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1962                         "  .VoltageMode          = 0x%02x\n"
1963                         "  .SnapToDiscrete       = 0x%02x\n"
1964                         "  .NumDiscreteLevels    = 0x%02x\n"
1965                         "  .padding              = 0x%02x\n"
1966                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1967                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1968                         "  .SsFmin               = 0x%04x\n"
1969                         "  .Padding_16           = 0x%04x\n",
1970                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1971                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1972                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1973                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1974                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1975                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1976                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1977                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1978                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1979                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1980                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1981
1982         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1983                         "  .VoltageMode          = 0x%02x\n"
1984                         "  .SnapToDiscrete       = 0x%02x\n"
1985                         "  .NumDiscreteLevels    = 0x%02x\n"
1986                         "  .padding              = 0x%02x\n"
1987                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1988                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1989                         "  .SsFmin               = 0x%04x\n"
1990                         "  .Padding_16           = 0x%04x\n",
1991                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1992                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1993                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1994                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1995                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1996                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1997                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1998                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1999                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2000                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2001                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2002
2003         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2004                         "  .VoltageMode          = 0x%02x\n"
2005                         "  .SnapToDiscrete       = 0x%02x\n"
2006                         "  .NumDiscreteLevels    = 0x%02x\n"
2007                         "  .padding              = 0x%02x\n"
2008                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2009                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2010                         "  .SsFmin               = 0x%04x\n"
2011                         "  .Padding_16           = 0x%04x\n",
2012                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2013                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2014                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2015                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2016                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2017                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2018                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2019                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2020                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2021                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2022                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2023
2024         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2025                         "  .VoltageMode          = 0x%02x\n"
2026                         "  .SnapToDiscrete       = 0x%02x\n"
2027                         "  .NumDiscreteLevels    = 0x%02x\n"
2028                         "  .padding              = 0x%02x\n"
2029                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2030                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2031                         "  .SsFmin               = 0x%04x\n"
2032                         "  .Padding_16           = 0x%04x\n",
2033                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2034                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2035                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2036                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2037                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2038                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2039                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2040                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2041                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2042                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2043                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2044
2045         dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2046                         "  .VoltageMode          = 0x%02x\n"
2047                         "  .SnapToDiscrete       = 0x%02x\n"
2048                         "  .NumDiscreteLevels    = 0x%02x\n"
2049                         "  .padding              = 0x%02x\n"
2050                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2051                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2052                         "  .SsFmin               = 0x%04x\n"
2053                         "  .Padding_16           = 0x%04x\n",
2054                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2055                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2056                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2057                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2058                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2059                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2060                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2061                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2062                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2063                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2064                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2065
2066         dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2067                         "  .VoltageMode          = 0x%02x\n"
2068                         "  .SnapToDiscrete       = 0x%02x\n"
2069                         "  .NumDiscreteLevels    = 0x%02x\n"
2070                         "  .padding              = 0x%02x\n"
2071                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2072                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2073                         "  .SsFmin               = 0x%04x\n"
2074                         "  .Padding_16           = 0x%04x\n",
2075                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2076                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2077                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2078                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2079                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2080                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2081                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2082                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2083                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2084                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2085                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2086
2087         dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2088                         "  .VoltageMode          = 0x%02x\n"
2089                         "  .SnapToDiscrete       = 0x%02x\n"
2090                         "  .NumDiscreteLevels    = 0x%02x\n"
2091                         "  .padding              = 0x%02x\n"
2092                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2093                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2094                         "  .SsFmin               = 0x%04x\n"
2095                         "  .Padding_16           = 0x%04x\n",
2096                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2097                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2098                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2099                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2100                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2101                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2102                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2103                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2104                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2105                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2106                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2107
2108         dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2109                         "  .VoltageMode          = 0x%02x\n"
2110                         "  .SnapToDiscrete       = 0x%02x\n"
2111                         "  .NumDiscreteLevels    = 0x%02x\n"
2112                         "  .padding              = 0x%02x\n"
2113                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2114                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2115                         "  .SsFmin               = 0x%04x\n"
2116                         "  .Padding_16           = 0x%04x\n",
2117                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2118                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2119                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2120                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2121                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2122                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2123                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2124                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2125                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2126                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2127                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2128
2129         dev_info(smu->adev->dev, "FreqTableGfx\n");
2130         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2131                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2132
2133         dev_info(smu->adev->dev, "FreqTableVclk\n");
2134         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2135                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2136
2137         dev_info(smu->adev->dev, "FreqTableDclk\n");
2138         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2139                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2140
2141         dev_info(smu->adev->dev, "FreqTableSocclk\n");
2142         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2143                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2144
2145         dev_info(smu->adev->dev, "FreqTableUclk\n");
2146         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2147                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2148
2149         dev_info(smu->adev->dev, "FreqTableFclk\n");
2150         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2151                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2152
2153         dev_info(smu->adev->dev, "Paddingclks[0] = 0x%x\n",  pptable->Paddingclks[0]);
2154         dev_info(smu->adev->dev, "Paddingclks[1] = 0x%x\n",  pptable->Paddingclks[1]);
2155         dev_info(smu->adev->dev, "Paddingclks[2] = 0x%x\n",  pptable->Paddingclks[2]);
2156         dev_info(smu->adev->dev, "Paddingclks[3] = 0x%x\n",  pptable->Paddingclks[3]);
2157         dev_info(smu->adev->dev, "Paddingclks[4] = 0x%x\n",  pptable->Paddingclks[4]);
2158         dev_info(smu->adev->dev, "Paddingclks[5] = 0x%x\n",  pptable->Paddingclks[5]);
2159         dev_info(smu->adev->dev, "Paddingclks[6] = 0x%x\n",  pptable->Paddingclks[6]);
2160         dev_info(smu->adev->dev, "Paddingclks[7] = 0x%x\n",  pptable->Paddingclks[7]);
2161         dev_info(smu->adev->dev, "Paddingclks[8] = 0x%x\n",  pptable->Paddingclks[8]);
2162         dev_info(smu->adev->dev, "Paddingclks[9] = 0x%x\n",  pptable->Paddingclks[9]);
2163         dev_info(smu->adev->dev, "Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]);
2164         dev_info(smu->adev->dev, "Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]);
2165         dev_info(smu->adev->dev, "Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]);
2166         dev_info(smu->adev->dev, "Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]);
2167         dev_info(smu->adev->dev, "Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]);
2168         dev_info(smu->adev->dev, "Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]);
2169
2170         dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2171         dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2172         dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2173         dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2174         dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2175         dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2176         dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2177         dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2178         dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2179
2180         dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2181         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2182                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2183
2184         dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2185         dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2186
2187         dev_info(smu->adev->dev, "Mp0clkFreq\n");
2188         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2189                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2190
2191         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2192         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2193                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2194
2195         dev_info(smu->adev->dev, "MemVddciVoltage\n");
2196         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2197                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2198
2199         dev_info(smu->adev->dev, "MemMvddVoltage\n");
2200         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2201                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2202
2203         dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2204         dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2205         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2206         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2207         dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2208
2209         dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2210
2211         dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2212         dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2213         dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2214         dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2215         dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2216         dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2217         dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2218         dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2219         dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2220         dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2221         dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2222
2223         dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2224         dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2225         dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2226         dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2227         dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2228         dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2229
2230         dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2231         dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2232         dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2233         dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2234         dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2235
2236         dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2237         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2238                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2239
2240         dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2241         dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2242         dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2243         dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2244
2245         dev_info(smu->adev->dev, "UclkDpmPstates\n");
2246         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2247                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2248
2249         dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2250         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2251                 pptable->UclkDpmSrcFreqRange.Fmin);
2252         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2253                 pptable->UclkDpmSrcFreqRange.Fmax);
2254         dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2255         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2256                 pptable->UclkDpmTargFreqRange.Fmin);
2257         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2258                 pptable->UclkDpmTargFreqRange.Fmax);
2259         dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2260         dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2261
2262         dev_info(smu->adev->dev, "PcieGenSpeed\n");
2263         for (i = 0; i < NUM_LINK_LEVELS; i++)
2264                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2265
2266         dev_info(smu->adev->dev, "PcieLaneCount\n");
2267         for (i = 0; i < NUM_LINK_LEVELS; i++)
2268                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2269
2270         dev_info(smu->adev->dev, "LclkFreq\n");
2271         for (i = 0; i < NUM_LINK_LEVELS; i++)
2272                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2273
2274         dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2275         dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2276
2277         dev_info(smu->adev->dev, "FanGain\n");
2278         for (i = 0; i < TEMP_COUNT; i++)
2279                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2280
2281         dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2282         dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2283         dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2284         dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2285         dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2286         dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2287         dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2288         dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2289         dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2290         dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2291         dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2292         dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2293
2294         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2295         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2296         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2297         dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2298
2299         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2300         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2301         dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2302         dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2303
2304         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2305                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2306                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2307                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2308         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2309                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2310                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2311                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2312         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2313                         pptable->dBtcGbGfxPll.a,
2314                         pptable->dBtcGbGfxPll.b,
2315                         pptable->dBtcGbGfxPll.c);
2316         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2317                         pptable->dBtcGbGfxDfll.a,
2318                         pptable->dBtcGbGfxDfll.b,
2319                         pptable->dBtcGbGfxDfll.c);
2320         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2321                         pptable->dBtcGbSoc.a,
2322                         pptable->dBtcGbSoc.b,
2323                         pptable->dBtcGbSoc.c);
2324         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2325                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2326                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2327         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2328                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2329                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2330
2331         dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2332         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2333                 dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
2334                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2335                 dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
2336                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2337         }
2338
2339         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2340                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2341                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2342                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2343         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2344                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2345                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2346                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2347
2348         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2349         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2350
2351         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2352         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2353         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2354         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2355
2356         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2357         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2358         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2359         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2360
2361         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2362         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2363
2364         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2365         for (i = 0; i < NUM_XGMI_LEVELS; i++)
2366                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2367         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2368         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2369
2370         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2371         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2372                         pptable->ReservedEquation0.a,
2373                         pptable->ReservedEquation0.b,
2374                         pptable->ReservedEquation0.c);
2375         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2376                         pptable->ReservedEquation1.a,
2377                         pptable->ReservedEquation1.b,
2378                         pptable->ReservedEquation1.c);
2379         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2380                         pptable->ReservedEquation2.a,
2381                         pptable->ReservedEquation2.b,
2382                         pptable->ReservedEquation2.c);
2383         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2384                         pptable->ReservedEquation3.a,
2385                         pptable->ReservedEquation3.b,
2386                         pptable->ReservedEquation3.c);
2387
2388         dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2389         dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2390         dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2391         dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2392         dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2393         dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2394         dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2395         dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2396         dev_info(smu->adev->dev, "SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
2397         dev_info(smu->adev->dev, "SkuReserved[9] = 0x%x\n", pptable->SkuReserved[9]);
2398         dev_info(smu->adev->dev, "SkuReserved[10] = 0x%x\n", pptable->SkuReserved[10]);
2399         dev_info(smu->adev->dev, "SkuReserved[11] = 0x%x\n", pptable->SkuReserved[11]);
2400         dev_info(smu->adev->dev, "SkuReserved[12] = 0x%x\n", pptable->SkuReserved[12]);
2401         dev_info(smu->adev->dev, "SkuReserved[13] = 0x%x\n", pptable->SkuReserved[13]);
2402         dev_info(smu->adev->dev, "SkuReserved[14] = 0x%x\n", pptable->SkuReserved[14]);
2403
2404         dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2405         dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2406         dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2407         dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2408         dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2409         dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2410
2411         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2412                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2413                 dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
2414                                 pptable->I2cControllers[i].Enabled);
2415                 dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
2416                                 pptable->I2cControllers[i].Speed);
2417                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
2418                                 pptable->I2cControllers[i].SlaveAddress);
2419                 dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
2420                                 pptable->I2cControllers[i].ControllerPort);
2421                 dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
2422                                 pptable->I2cControllers[i].ControllerName);
2423                 dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
2424                                 pptable->I2cControllers[i].ThermalThrotter);
2425                 dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
2426                                 pptable->I2cControllers[i].I2cProtocol);
2427                 dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
2428                                 pptable->I2cControllers[i].PaddingConfig);
2429         }
2430
2431         dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2432         dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2433         dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2434         dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2435
2436         dev_info(smu->adev->dev, "Board Parameters:\n");
2437         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2438         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2439         dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2440         dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2441         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2442         dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2443         dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2444         dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2445
2446         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2447         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2448         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2449
2450         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2451         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2452         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2453
2454         dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2455         dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2456         dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2457
2458         dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2459         dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2460         dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2461
2462         dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2463
2464         dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2465         dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2466         dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2467         dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2468         dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2469         dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2470         dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2471         dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2472         dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2473         dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2474         dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2475         dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2476         dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2477         dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2478         dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2479         dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2480
2481         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2482         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2483         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
2484
2485         dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2486         dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2487         dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
2488
2489         dev_info(smu->adev->dev, "UclkSpreadEnabled = 0x%x\n", pptable->UclkSpreadEnabled);
2490         dev_info(smu->adev->dev, "UclkSpreadPercent = 0x%x\n", pptable->UclkSpreadPercent);
2491         dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2492
2493         dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2494         dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2495         dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2496
2497         dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2498         dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2499         dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2500         dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2501         dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2502
2503         dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2504         dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2505
2506         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2507         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2508                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2509         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2510         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2511                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2512         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2513         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2514                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2515         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2516         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2517                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2518
2519         dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2520         dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2521         dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2522         dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2523
2524         dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2525         dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2526         dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2527         dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2528         dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2529         dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2530         dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2531         dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2532         dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2533         dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2534         dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2535         dev_info(smu->adev->dev, "BoardReserved[11] = 0x%x\n", pptable->BoardReserved[11]);
2536         dev_info(smu->adev->dev, "BoardReserved[12] = 0x%x\n", pptable->BoardReserved[12]);
2537         dev_info(smu->adev->dev, "BoardReserved[13] = 0x%x\n", pptable->BoardReserved[13]);
2538         dev_info(smu->adev->dev, "BoardReserved[14] = 0x%x\n", pptable->BoardReserved[14]);
2539
2540         dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2541         dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2542         dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2543         dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2544         dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2545         dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2546         dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2547         dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2548 }
2549
2550 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
2551         .tables_init = sienna_cichlid_tables_init,
2552         .alloc_dpm_context = sienna_cichlid_allocate_dpm_context,
2553         .get_smu_msg_index = sienna_cichlid_get_smu_msg_index,
2554         .get_smu_clk_index = sienna_cichlid_get_smu_clk_index,
2555         .get_smu_feature_index = sienna_cichlid_get_smu_feature_index,
2556         .get_smu_table_index = sienna_cichlid_get_smu_table_index,
2557         .get_smu_power_index = sienna_cichlid_get_pwr_src_index,
2558         .get_workload_type = sienna_cichlid_get_workload_type,
2559         .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2560         .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
2561         .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
2562         .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
2563         .get_current_clk_freq_by_table = sienna_cichlid_get_current_clk_freq_by_table,
2564         .print_clk_levels = sienna_cichlid_print_clk_levels,
2565         .force_clk_levels = sienna_cichlid_force_clk_levels,
2566         .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
2567         .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2568         .display_config_changed = sienna_cichlid_display_config_changed,
2569         .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
2570         .force_dpm_limit_value = sienna_cichlid_force_dpm_limit_value,
2571         .unforce_dpm_levels = sienna_cichlid_unforce_dpm_levels,
2572         .is_dpm_running = sienna_cichlid_is_dpm_running,
2573         .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
2574         .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2575         .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2576         .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
2577         .get_profiling_clk_mask = sienna_cichlid_get_profiling_clk_mask,
2578         .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2579         .read_sensor = sienna_cichlid_read_sensor,
2580         .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
2581         .set_performance_level = sienna_cichlid_set_performance_level,
2582         .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2583         .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2584         .get_power_limit = sienna_cichlid_get_power_limit,
2585         .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
2586         .dump_pptable = sienna_cichlid_dump_pptable,
2587         .init_microcode = smu_v11_0_init_microcode,
2588         .load_microcode = smu_v11_0_load_microcode,
2589         .init_smc_tables = smu_v11_0_init_smc_tables,
2590         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2591         .init_power = smu_v11_0_init_power,
2592         .fini_power = smu_v11_0_fini_power,
2593         .check_fw_status = smu_v11_0_check_fw_status,
2594         .setup_pptable = sienna_cichlid_setup_pptable,
2595         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2596         .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2597         .check_fw_version = smu_v11_0_check_fw_version,
2598         .write_pptable = smu_v11_0_write_pptable,
2599         .set_min_dcef_deep_sleep = NULL,
2600         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2601         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2602         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2603         .system_features_control = smu_v11_0_system_features_control,
2604         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2605         .init_display_count = NULL,
2606         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2607         .get_enabled_mask = smu_v11_0_get_enabled_mask,
2608         .notify_display_change = NULL,
2609         .set_power_limit = smu_v11_0_set_power_limit,
2610         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2611         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2612         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2613         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2614         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2615         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2616         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2617         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2618         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2619         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2620         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2621         .gfx_off_control = smu_v11_0_gfx_off_control,
2622         .register_irq_handler = smu_v11_0_register_irq_handler,
2623         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2624         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2625         .baco_is_support= sienna_cichlid_is_baco_supported,
2626         .baco_get_state = smu_v11_0_baco_get_state,
2627         .baco_set_state = smu_v11_0_baco_set_state,
2628         .baco_enter = smu_v11_0_baco_enter,
2629         .baco_exit = smu_v11_0_baco_exit,
2630         .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
2631         .set_soft_freq_limited_range = sienna_cichlid_set_soft_freq_limited_range,
2632         .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2633         .set_thermal_range = sienna_cichlid_set_thermal_range,
2634 };
2635
2636 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2637 {
2638         smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
2639 }