drivers/gpu/drm/amd/powerplay/navi10_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/pci.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_internal.h"
  29 #include "atomfirmware.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "soc15_common.h"
  32 #include "smu_v11_0.h"
  33 #include "smu11_driver_if_navi10.h"
  34 #include "atom.h"
  35 #include "navi10_ppt.h"
  36 #include "smu_v11_0_pptable.h"
  37 #include "smu_v11_0_ppsmc.h"
  38 #include "nbio/nbio_2_3_offset.h"
  39 #include "nbio/nbio_2_3_sh_mask.h"
  40 #include "thm/thm_11_0_2_offset.h"
  41 #include "thm/thm_11_0_2_sh_mask.h"
  42
  43 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  44
  45 /*
  46  * DO NOT use these for err/warn/info/debug messages.
  47  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  48  * They are more MGPU friendly.
  49  */
  50 #undef pr_err
  51 #undef pr_warn
  52 #undef pr_info
  53 #undef pr_debug
  54
  55 #define FEATURE_MASK(feature) (1ULL << feature)
  56 #define SMC_DPM_FEATURE ( \
  57         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  58         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  59         FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT)   | \
  60         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  61         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  62         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)     | \
  63         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  64         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  65
  66 #define MSG_MAP(msg, index, valid_in_vf) \
  67         [SMU_MSG_##msg] = {1, (index), (valid_in_vf)}
  68
  69 static struct smu_11_0_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
  70         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                  1),
  71         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,                1),
  72         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,           1),
  73         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,    0),
  74         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,   0),
  75         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,         0),
  76         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,        0),
  77         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,         1),
  78         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,        1),
  79         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,        1),
  80         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,       1),
  81         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetEnabledSmuFeaturesLow,     1),
  82         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetEnabledSmuFeaturesHigh,    1),
  83         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,              1),
  84         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                  0),
  85         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,        0),
  86         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,         0),
  87         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,         0),
  88         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,          0),
  89         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,        0),
  90         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,        0),
  91         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,            0),
  92         MSG_MAP(UseBackupPPTable,               PPSMC_MSG_UseBackupPPTable,             0),
  93         MSG_MAP(RunBtc,                         PPSMC_MSG_RunBtc,                       0),
  94         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                    0),
  95         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,             0),
  96         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,             0),
  97         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,             1),
  98         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,             0),
  99         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,                1),
 100         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,                1),
 101         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,            1),
 102         MSG_MAP(SetMemoryChannelConfig,         PPSMC_MSG_SetMemoryChannelConfig,       0),
 103         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode,                0),
 104         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh,        0),
 105         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow,         0),
 106         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,       0),
 107         MSG_MAP(SetMinDeepSleepDcefclk,         PPSMC_MSG_SetMinDeepSleepDcefclk,       0),
 108         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,        0),
 109         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,            0),
 110         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch,            0),
 111         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                  0),
 112         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,          1),
 113         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh,       0),
 114         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow,        0),
 115         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize,           0),
 116         MSG_MAP(ConfigureGfxDidt,               PPSMC_MSG_ConfigureGfxDidt,             0),
 117         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_NumOfDisplays,                0),
 118         MSG_MAP(SetSystemVirtualDramAddrHigh,   PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
 119         MSG_MAP(SetSystemVirtualDramAddrLow,    PPSMC_MSG_SetSystemVirtualDramAddrLow,  0),
 120         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                  0),
 121         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,               0),
 122         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                  0),
 123         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,          1),
 124         MSG_MAP(GetDebugData,                   PPSMC_MSG_GetDebugData,                 0),
 125         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                     0),
 126         MSG_MAP(PrepareMp1ForReset,             PPSMC_MSG_PrepareMp1ForReset,           0),
 127         MSG_MAP(PrepareMp1ForShutdown,          PPSMC_MSG_PrepareMp1ForShutdown,        0),
 128         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                   0),
 129         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                 0),
 130         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                  0),
 131         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,                0),
 132         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME,               0),
 133         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                        0),
 134         MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,PPSMC_MSG_DALDisableDummyPstateChange,  0),
 135         MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange,   0),
 136         MSG_MAP(GetVoltageByDpm,                PPSMC_MSG_GetVoltageByDpm,              0),
 137         MSG_MAP(GetVoltageByDpmOverdrive,       PPSMC_MSG_GetVoltageByDpmOverdrive,     0),
 138 };
 139
 140 static struct smu_11_0_cmn2aisc_mapping navi10_clk_map[SMU_CLK_COUNT] = {
 141         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 142         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 143         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 144         CLK_MAP(FCLK, PPCLK_SOCCLK),
 145         CLK_MAP(UCLK, PPCLK_UCLK),
 146         CLK_MAP(MCLK, PPCLK_UCLK),
 147         CLK_MAP(DCLK, PPCLK_DCLK),
 148         CLK_MAP(VCLK, PPCLK_VCLK),
 149         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 150         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 151         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 152         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 153 };
 154
 155 static struct smu_11_0_cmn2aisc_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
 156         FEA_MAP(DPM_PREFETCHER),
 157         FEA_MAP(DPM_GFXCLK),
 158         FEA_MAP(DPM_GFX_PACE),
 159         FEA_MAP(DPM_UCLK),
 160         FEA_MAP(DPM_SOCCLK),
 161         FEA_MAP(DPM_MP0CLK),
 162         FEA_MAP(DPM_LINK),
 163         FEA_MAP(DPM_DCEFCLK),
 164         FEA_MAP(MEM_VDDCI_SCALING),
 165         FEA_MAP(MEM_MVDD_SCALING),
 166         FEA_MAP(DS_GFXCLK),
 167         FEA_MAP(DS_SOCCLK),
 168         FEA_MAP(DS_LCLK),
 169         FEA_MAP(DS_DCEFCLK),
 170         FEA_MAP(DS_UCLK),
 171         FEA_MAP(GFX_ULV),
 172         FEA_MAP(FW_DSTATE),
 173         FEA_MAP(GFXOFF),
 174         FEA_MAP(BACO),
 175         FEA_MAP(VCN_PG),
 176         FEA_MAP(JPEG_PG),
 177         FEA_MAP(USB_PG),
 178         FEA_MAP(RSMU_SMN_CG),
 179         FEA_MAP(PPT),
 180         FEA_MAP(TDC),
 181         FEA_MAP(GFX_EDC),
 182         FEA_MAP(APCC_PLUS),
 183         FEA_MAP(GTHR),
 184         FEA_MAP(ACDC),
 185         FEA_MAP(VR0HOT),
 186         FEA_MAP(VR1HOT),
 187         FEA_MAP(FW_CTF),
 188         FEA_MAP(FAN_CONTROL),
 189         FEA_MAP(THERMAL),
 190         FEA_MAP(GFX_DCS),
 191         FEA_MAP(RM),
 192         FEA_MAP(LED_DISPLAY),
 193         FEA_MAP(GFX_SS),
 194         FEA_MAP(OUT_OF_BAND_MONITOR),
 195         FEA_MAP(TEMP_DEPENDENT_VMIN),
 196         FEA_MAP(MMHUB_PG),
 197         FEA_MAP(ATHUB_PG),
 198         FEA_MAP(APCC_DFLL),
 199 };
 200
 201 static struct smu_11_0_cmn2aisc_mapping navi10_table_map[SMU_TABLE_COUNT] = {
 202         TAB_MAP(PPTABLE),
 203         TAB_MAP(WATERMARKS),
 204         TAB_MAP(AVFS),
 205         TAB_MAP(AVFS_PSM_DEBUG),
 206         TAB_MAP(AVFS_FUSE_OVERRIDE),
 207         TAB_MAP(PMSTATUSLOG),
 208         TAB_MAP(SMU_METRICS),
 209         TAB_MAP(DRIVER_SMU_CONFIG),
 210         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 211         TAB_MAP(OVERDRIVE),
 212         TAB_MAP(I2C_COMMANDS),
 213         TAB_MAP(PACE),
 214 };
 215
 216 static struct smu_11_0_cmn2aisc_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 217         PWR_MAP(AC),
 218         PWR_MAP(DC),
 219 };
 220
 221 static struct smu_11_0_cmn2aisc_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 222         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 223         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 224         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 225         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 226         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 227         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 228         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 229 };
 230
 231 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 232 {
 233         struct smu_11_0_msg_mapping mapping;
 234
 235         if (index >= SMU_MSG_MAX_COUNT)
 236                 return -EINVAL;
 237
 238         mapping = navi10_message_map[index];
 239         if (!(mapping.valid_mapping)) {
 240                 return -EINVAL;
 241         }
 242
 243         if (amdgpu_sriov_vf(smc->adev) && !mapping.valid_in_vf)
 244                 return -EACCES;
 245
 246         return mapping.map_to;
 247 }
 248
 249 static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 250 {
 251         struct smu_11_0_cmn2aisc_mapping mapping;
 252
 253         if (index >= SMU_CLK_COUNT)
 254                 return -EINVAL;
 255
 256         mapping = navi10_clk_map[index];
 257         if (!(mapping.valid_mapping)) {
 258                 return -EINVAL;
 259         }
 260
 261         return mapping.map_to;
 262 }
 263
 264 static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 265 {
 266         struct smu_11_0_cmn2aisc_mapping mapping;
 267
 268         if (index >= SMU_FEATURE_COUNT)
 269                 return -EINVAL;
 270
 271         mapping = navi10_feature_mask_map[index];
 272         if (!(mapping.valid_mapping)) {
 273                 return -EINVAL;
 274         }
 275
 276         return mapping.map_to;
 277 }
 278
 279 static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
 280 {
 281         struct smu_11_0_cmn2aisc_mapping mapping;
 282
 283         if (index >= SMU_TABLE_COUNT)
 284                 return -EINVAL;
 285
 286         mapping = navi10_table_map[index];
 287         if (!(mapping.valid_mapping)) {
 288                 return -EINVAL;
 289         }
 290
 291         return mapping.map_to;
 292 }
 293
 294 static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 295 {
 296         struct smu_11_0_cmn2aisc_mapping mapping;
 297
 298         if (index >= SMU_POWER_SOURCE_COUNT)
 299                 return -EINVAL;
 300
 301         mapping = navi10_pwr_src_map[index];
 302         if (!(mapping.valid_mapping)) {
 303                 return -EINVAL;
 304         }
 305
 306         return mapping.map_to;
 307 }
 308
 309
 310 static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 311 {
 312         struct smu_11_0_cmn2aisc_mapping mapping;
 313
 314         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 315                 return -EINVAL;
 316
 317         mapping = navi10_workload_map[profile];
 318         if (!(mapping.valid_mapping)) {
 319                 return -EINVAL;
 320         }
 321
 322         return mapping.map_to;
 323 }
 324
 325 static bool is_asic_secure(struct smu_context *smu)
 326 {
 327         struct amdgpu_device *adev = smu->adev;
 328         bool is_secure = true;
 329         uint32_t mp0_fw_intf;
 330
 331         mp0_fw_intf = RREG32_PCIE(MP0_Public |
 332                                    (smnMP0_FW_INTF & 0xffffffff));
 333
 334         if (!(mp0_fw_intf & (1 << 19)))
 335                 is_secure = false;
 336
 337         return is_secure;
 338 }
 339
 340 static int
 341 navi10_get_allowed_feature_mask(struct smu_context *smu,
 342                                   uint32_t *feature_mask, uint32_t num)
 343 {
 344         struct amdgpu_device *adev = smu->adev;
 345
 346         if (num > 2)
 347                 return -EINVAL;
 348
 349         memset(feature_mask, 0, sizeof(uint32_t) * num);
 350
 351         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 352                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 353                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 354                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 355                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 356                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 357                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 358                                 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
 359                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 360                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 361                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 362                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 363                                 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
 364                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 365                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 366                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 367                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 368                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 369                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 370                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 371
 372         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 373                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 374
 375         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
 376                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 377
 378         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 379                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 380
 381         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 382                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 383
 384         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 385                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 386                                 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 387                                 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 388
 389         if (adev->pm.pp_feature & PP_ULV_MASK)
 390                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 391
 392         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 393                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 394
 395         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 396                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 397
 398         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 399                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 400
 401         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 402                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 403
 404         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
 405                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
 406
 407         if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 408                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
 409
 410         if (smu->dc_controlled_by_gpio)
 411                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
 412
 413         /* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
 414         if (is_asic_secure(smu)) {
 415                 /* only for navi10 A0 */
 416                 if ((adev->asic_type == CHIP_NAVI10) &&
 417                         (adev->rev_id == 0)) {
 418                         *(uint64_t *)feature_mask &=
 419                                         ~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 420                                           | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 421                                           | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT));
 422                         *(uint64_t *)feature_mask &=
 423                                         ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
 424                 }
 425         }
 426
 427         return 0;
 428 }
 429
 430 static int navi10_check_powerplay_table(struct smu_context *smu)
 431 {
 432         struct smu_table_context *table_context = &smu->smu_table;
 433         struct smu_11_0_powerplay_table *powerplay_table =
 434                 table_context->power_play_table;
 435         struct smu_baco_context *smu_baco = &smu->smu_baco;
 436
 437         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC)
 438                 smu->dc_controlled_by_gpio = true;
 439
 440         mutex_lock(&smu_baco->mutex);
 441         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 442             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 443                 smu_baco->platform_support = true;
 444         mutex_unlock(&smu_baco->mutex);
 445
 446         table_context->thermal_controller_type =
 447                 powerplay_table->thermal_controller_type;
 448
 449         /*
 450          * Instead of having its own buffer space and get overdrive_table copied,
 451          * smu->od_settings just points to the actual overdrive_table
 452          */
 453         smu->od_settings = &powerplay_table->overdrive_table;
 454
 455         return 0;
 456 }
 457
 458 static int navi10_append_powerplay_table(struct smu_context *smu)
 459 {
 460         struct amdgpu_device *adev = smu->adev;
 461         struct smu_table_context *table_context = &smu->smu_table;
 462         PPTable_t *smc_pptable = table_context->driver_pptable;
 463         struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
 464         struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7;
 465         int index, ret;
 466
 467         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 468                                            smc_dpm_info);
 469
 470         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 471                                       (uint8_t **)&smc_dpm_table);
 472         if (ret)
 473                 return ret;
 474
 475         dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 476                         smc_dpm_table->table_header.format_revision,
 477                         smc_dpm_table->table_header.content_revision);
 478
 479         if (smc_dpm_table->table_header.format_revision != 4) {
 480                 dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n");
 481                 return -EINVAL;
 482         }
 483
 484         switch (smc_dpm_table->table_header.content_revision) {
 485         case 5: /* nv10 and nv14 */
 486                 memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 487                         sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
 488                 break;
 489         case 7: /* nv12 */
 490                 ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 491                                               (uint8_t **)&smc_dpm_table_v4_7);
 492                 if (ret)
 493                         return ret;
 494                 memcpy(smc_pptable->I2cControllers, smc_dpm_table_v4_7->I2cControllers,
 495                         sizeof(*smc_dpm_table_v4_7) - sizeof(smc_dpm_table_v4_7->table_header));
 496                 break;
 497         default:
 498                 dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n",
 499                                 smc_dpm_table->table_header.content_revision);
 500                 return -EINVAL;
 501         }
 502
 503         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 504                 /* TODO: remove it once SMU fw fix it */
 505                 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
 506         }
 507
 508         return 0;
 509 }
 510
 511 static int navi10_store_powerplay_table(struct smu_context *smu)
 512 {
 513         struct smu_table_context *table_context = &smu->smu_table;
 514         struct smu_11_0_powerplay_table *powerplay_table =
 515                 table_context->power_play_table;
 516
 517         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 518                sizeof(PPTable_t));
 519
 520         return 0;
 521 }
 522
 523 static int navi10_setup_pptable(struct smu_context *smu)
 524 {
 525         int ret = 0;
 526
 527         ret = smu_v11_0_setup_pptable(smu);
 528         if (ret)
 529                 return ret;
 530
 531         ret = navi10_store_powerplay_table(smu);
 532         if (ret)
 533                 return ret;
 534
 535         ret = navi10_append_powerplay_table(smu);
 536         if (ret)
 537                 return ret;
 538
 539         ret = navi10_check_powerplay_table(smu);
 540         if (ret)
 541                 return ret;
 542
 543         return ret;
 544 }
 545
 546 static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
 547 {
 548         struct smu_table_context *smu_table = &smu->smu_table;
 549
 550         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 551                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 552         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 553                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 554         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 555                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 556         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 557                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 558         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 559                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 560         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 561                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 562                        AMDGPU_GEM_DOMAIN_VRAM);
 563
 564         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 565         if (!smu_table->metrics_table)
 566                 return -ENOMEM;
 567         smu_table->metrics_time = 0;
 568
 569         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 570         if (!smu_table->watermarks_table)
 571                 return -ENOMEM;
 572
 573         return 0;
 574 }
 575
 576 static int navi10_get_smu_metrics_data(struct smu_context *smu,
 577                                        MetricsMember_t member,
 578                                        uint32_t *value)
 579 {
 580         struct smu_table_context *smu_table= &smu->smu_table;
 581         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 582         int ret = 0;
 583
 584         mutex_lock(&smu->metrics_lock);
 585         if (!smu_table->metrics_time ||
 586              time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) {
 587                 ret = smu_update_table(smu,
 588                                        SMU_TABLE_SMU_METRICS,
 589                                        0,
 590                                        smu_table->metrics_table,
 591                                        false);
 592                 if (ret) {
 593                         dev_info(smu->adev->dev, "Failed to export SMU metrics table!\n");
 594                         mutex_unlock(&smu->metrics_lock);
 595                         return ret;
 596                 }
 597                 smu_table->metrics_time = jiffies;
 598         }
 599
 600         switch (member) {
 601         case METRICS_CURR_GFXCLK:
 602                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 603                 break;
 604         case METRICS_CURR_SOCCLK:
 605                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 606                 break;
 607         case METRICS_CURR_UCLK:
 608                 *value = metrics->CurrClock[PPCLK_UCLK];
 609                 break;
 610         case METRICS_CURR_VCLK:
 611                 *value = metrics->CurrClock[PPCLK_VCLK];
 612                 break;
 613         case METRICS_CURR_DCLK:
 614                 *value = metrics->CurrClock[PPCLK_DCLK];
 615                 break;
 616         case METRICS_AVERAGE_GFXCLK:
 617                 *value = metrics->AverageGfxclkFrequency;
 618                 break;
 619         case METRICS_AVERAGE_SOCCLK:
 620                 *value = metrics->AverageSocclkFrequency;
 621                 break;
 622         case METRICS_AVERAGE_UCLK:
 623                 *value = metrics->AverageUclkFrequency;
 624                 break;
 625         case METRICS_AVERAGE_GFXACTIVITY:
 626                 *value = metrics->AverageGfxActivity;
 627                 break;
 628         case METRICS_AVERAGE_MEMACTIVITY:
 629                 *value = metrics->AverageUclkActivity;
 630                 break;
 631         case METRICS_AVERAGE_SOCKETPOWER:
 632                 *value = metrics->AverageSocketPower << 8;
 633                 break;
 634         case METRICS_TEMPERATURE_EDGE:
 635                 *value = metrics->TemperatureEdge *
 636                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 637                 break;
 638         case METRICS_TEMPERATURE_HOTSPOT:
 639                 *value = metrics->TemperatureHotspot *
 640                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 641                 break;
 642         case METRICS_TEMPERATURE_MEM:
 643                 *value = metrics->TemperatureMem *
 644                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 645                 break;
 646         case METRICS_TEMPERATURE_VRGFX:
 647                 *value = metrics->TemperatureVrGfx *
 648                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 649                 break;
 650         case METRICS_TEMPERATURE_VRSOC:
 651                 *value = metrics->TemperatureVrSoc *
 652                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 653                 break;
 654         case METRICS_THROTTLER_STATUS:
 655                 *value = metrics->ThrottlerStatus;
 656                 break;
 657         case METRICS_CURR_FANSPEED:
 658                 *value = metrics->CurrFanSpeed;
 659                 break;
 660         default:
 661                 *value = UINT_MAX;
 662                 break;
 663         }
 664
 665         mutex_unlock(&smu->metrics_lock);
 666
 667         return ret;
 668 }
 669
 670 static int navi10_allocate_dpm_context(struct smu_context *smu)
 671 {
 672         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 673
 674         if (smu_dpm->dpm_context)
 675                 return -EINVAL;
 676
 677         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 678                                        GFP_KERNEL);
 679         if (!smu_dpm->dpm_context)
 680                 return -ENOMEM;
 681
 682         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 683
 684         return 0;
 685 }
 686
 687 static int navi10_set_default_dpm_table(struct smu_context *smu)
 688 {
 689         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 690         struct smu_table_context *table_context = &smu->smu_table;
 691         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 692         PPTable_t *driver_ppt = NULL;
 693         int i;
 694
 695         driver_ppt = table_context->driver_pptable;
 696
 697         dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
 698         dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
 699
 700         dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
 701         dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
 702
 703         dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
 704         dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
 705
 706         dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
 707         dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
 708
 709         dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
 710         dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
 711
 712         dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
 713         dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
 714
 715         dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
 716         dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
 717
 718         dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
 719         dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
 720
 721         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
 722         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
 723
 724         for (i = 0; i < MAX_PCIE_CONF; i++) {
 725                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
 726                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
 727         }
 728
 729         return 0;
 730 }
 731
 732 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 733 {
 734         struct smu_power_context *smu_power = &smu->smu_power;
 735         struct smu_power_gate *power_gate = &smu_power->power_gate;
 736         int ret = 0;
 737
 738         if (enable) {
 739                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 740                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 741                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
 742                         if (ret)
 743                                 return ret;
 744                 }
 745                 power_gate->vcn_gated = false;
 746         } else {
 747                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 748                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
 749                         if (ret)
 750                                 return ret;
 751                 }
 752                 power_gate->vcn_gated = true;
 753         }
 754
 755         return ret;
 756 }
 757
 758 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 759 {
 760         struct smu_power_context *smu_power = &smu->smu_power;
 761         struct smu_power_gate *power_gate = &smu_power->power_gate;
 762         int ret = 0;
 763
 764         if (enable) {
 765                 if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 766                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL);
 767                         if (ret)
 768                                 return ret;
 769                 }
 770                 power_gate->jpeg_gated = false;
 771         } else {
 772                 if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 773                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);
 774                         if (ret)
 775                                 return ret;
 776                 }
 777                 power_gate->jpeg_gated = true;
 778         }
 779
 780         return ret;
 781 }
 782
 783 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
 784                                        enum smu_clk_type clk_type,
 785                                        uint32_t *value)
 786 {
 787         MetricsMember_t member_type;
 788         int clk_id = 0;
 789
 790         clk_id = smu_clk_get_index(smu, clk_type);
 791         if (clk_id < 0)
 792                 return clk_id;
 793
 794         switch (clk_id) {
 795         case PPCLK_GFXCLK:
 796                 member_type = METRICS_CURR_GFXCLK;
 797                 break;
 798         case PPCLK_UCLK:
 799                 member_type = METRICS_CURR_UCLK;
 800                 break;
 801         case PPCLK_SOCCLK:
 802                 member_type = METRICS_CURR_SOCCLK;
 803                 break;
 804         case PPCLK_VCLK:
 805                 member_type = METRICS_CURR_VCLK;
 806                 break;
 807         case PPCLK_DCLK:
 808                 member_type = METRICS_CURR_DCLK;
 809                 break;
 810         case PPCLK_DCEFCLK:
 811                 member_type = METRICS_CURR_DCEFCLK;
 812                 break;
 813         default:
 814                 return -EINVAL;
 815         }
 816
 817         return navi10_get_smu_metrics_data(smu,
 818                                            member_type,
 819                                            value);
 820 }
 821
 822 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 823 {
 824         PPTable_t *pptable = smu->smu_table.driver_pptable;
 825         DpmDescriptor_t *dpm_desc = NULL;
 826         uint32_t clk_index = 0;
 827
 828         clk_index = smu_clk_get_index(smu, clk_type);
 829         dpm_desc = &pptable->DpmDescriptor[clk_index];
 830
 831         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 832         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 833 }
 834
 835 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap)
 836 {
 837         return od_table->cap[cap];
 838 }
 839
 840 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table,
 841                                         enum SMU_11_0_ODSETTING_ID setting,
 842                                         uint32_t *min, uint32_t *max)
 843 {
 844         if (min)
 845                 *min = od_table->min[setting];
 846         if (max)
 847                 *max = od_table->max[setting];
 848 }
 849
 850 static int navi10_print_clk_levels(struct smu_context *smu,
 851                         enum smu_clk_type clk_type, char *buf)
 852 {
 853         uint16_t *curve_settings;
 854         int i, size = 0, ret = 0;
 855         uint32_t cur_value = 0, value = 0, count = 0;
 856         uint32_t freq_values[3] = {0};
 857         uint32_t mark_index = 0;
 858         struct smu_table_context *table_context = &smu->smu_table;
 859         uint32_t gen_speed, lane_width;
 860         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 861         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 862         struct amdgpu_device *adev = smu->adev;
 863         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 864         OverDriveTable_t *od_table =
 865                 (OverDriveTable_t *)table_context->overdrive_table;
 866         struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
 867         uint32_t min_value, max_value;
 868
 869         switch (clk_type) {
 870         case SMU_GFXCLK:
 871         case SMU_SCLK:
 872         case SMU_SOCCLK:
 873         case SMU_MCLK:
 874         case SMU_UCLK:
 875         case SMU_FCLK:
 876         case SMU_DCEFCLK:
 877                 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
 878                 if (ret)
 879                         return size;
 880
 881                 /* 10KHz -> MHz */
 882                 cur_value = cur_value / 100;
 883
 884                 ret = smu_get_dpm_level_count(smu, clk_type, &count);
 885                 if (ret)
 886                         return size;
 887
 888                 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
 889                         for (i = 0; i < count; i++) {
 890                                 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
 891                                 if (ret)
 892                                         return size;
 893
 894                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 895                                                 cur_value == value ? "*" : "");
 896                         }
 897                 } else {
 898                         ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 899                         if (ret)
 900                                 return size;
 901                         ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 902                         if (ret)
 903                                 return size;
 904
 905                         freq_values[1] = cur_value;
 906                         mark_index = cur_value == freq_values[0] ? 0 :
 907                                      cur_value == freq_values[2] ? 2 : 1;
 908                         if (mark_index != 1)
 909                                 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
 910
 911                         for (i = 0; i < 3; i++) {
 912                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 913                                                 i == mark_index ? "*" : "");
 914                         }
 915
 916                 }
 917                 break;
 918         case SMU_PCIE:
 919                 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
 920                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
 921                         >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
 922                 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
 923                               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
 924                         >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
 925                 for (i = 0; i < NUM_LINK_LEVELS; i++)
 926                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 927                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
 928                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
 929                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
 930                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
 931                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
 932                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
 933                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
 934                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
 935                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
 936                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
 937                                         pptable->LclkFreq[i],
 938                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
 939                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
 940                                         "*" : "");
 941                 break;
 942         case SMU_OD_SCLK:
 943                 if (!smu->od_enabled || !od_table || !od_settings)
 944                         break;
 945                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
 946                         break;
 947                 size += sprintf(buf + size, "OD_SCLK:\n");
 948                 size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
 949                 break;
 950         case SMU_OD_MCLK:
 951                 if (!smu->od_enabled || !od_table || !od_settings)
 952                         break;
 953                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
 954                         break;
 955                 size += sprintf(buf + size, "OD_MCLK:\n");
 956                 size += sprintf(buf + size, "1: %uMHz\n", od_table->UclkFmax);
 957                 break;
 958         case SMU_OD_VDDC_CURVE:
 959                 if (!smu->od_enabled || !od_table || !od_settings)
 960                         break;
 961                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
 962                         break;
 963                 size += sprintf(buf + size, "OD_VDDC_CURVE:\n");
 964                 for (i = 0; i < 3; i++) {
 965                         switch (i) {
 966                         case 0:
 967                                 curve_settings = &od_table->GfxclkFreq1;
 968                                 break;
 969                         case 1:
 970                                 curve_settings = &od_table->GfxclkFreq2;
 971                                 break;
 972                         case 2:
 973                                 curve_settings = &od_table->GfxclkFreq3;
 974                                 break;
 975                         default:
 976                                 break;
 977                         }
 978                         size += sprintf(buf + size, "%d: %uMHz @ %umV\n", i, curve_settings[0], curve_settings[1] / NAVI10_VOLTAGE_SCALE);
 979                 }
 980                 break;
 981         case SMU_OD_RANGE:
 982                 if (!smu->od_enabled || !od_table || !od_settings)
 983                         break;
 984                 size = sprintf(buf, "%s:\n", "OD_RANGE");
 985
 986                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
 987                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
 988                                                     &min_value, NULL);
 989                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
 990                                                     NULL, &max_value);
 991                         size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
 992                                         min_value, max_value);
 993                 }
 994
 995                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
 996                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
 997                                                     &min_value, &max_value);
 998                         size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
 999                                         min_value, max_value);
1000                 }
1001
1002                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
1003                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
1004                                                     &min_value, &max_value);
1005                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1006                                         min_value, max_value);
1007                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
1008                                                     &min_value, &max_value);
1009                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1010                                         min_value, max_value);
1011                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
1012                                                     &min_value, &max_value);
1013                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1014                                         min_value, max_value);
1015                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
1016                                                     &min_value, &max_value);
1017                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1018                                         min_value, max_value);
1019                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
1020                                                     &min_value, &max_value);
1021                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1022                                         min_value, max_value);
1023                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
1024                                                     &min_value, &max_value);
1025                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1026                                         min_value, max_value);
1027                 }
1028
1029                 break;
1030         default:
1031                 break;
1032         }
1033
1034         return size;
1035 }
1036
1037 static int navi10_force_clk_levels(struct smu_context *smu,
1038                                    enum smu_clk_type clk_type, uint32_t mask)
1039 {
1040
1041         int ret = 0, size = 0;
1042         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1043
1044         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1045         soft_max_level = mask ? (fls(mask) - 1) : 0;
1046
1047         switch (clk_type) {
1048         case SMU_GFXCLK:
1049         case SMU_SCLK:
1050         case SMU_SOCCLK:
1051         case SMU_MCLK:
1052         case SMU_UCLK:
1053         case SMU_DCEFCLK:
1054         case SMU_FCLK:
1055                 /* There is only 2 levels for fine grained DPM */
1056                 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1057                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1058                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1059                 }
1060
1061                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1062                 if (ret)
1063                         return size;
1064
1065                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1066                 if (ret)
1067                         return size;
1068
1069                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
1070                 if (ret)
1071                         return size;
1072                 break;
1073         default:
1074                 break;
1075         }
1076
1077         return size;
1078 }
1079
1080 static int navi10_populate_umd_state_clk(struct smu_context *smu)
1081 {
1082         int ret = 0;
1083         uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
1084
1085         ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
1086         if (ret)
1087                 return ret;
1088
1089         smu->pstate_sclk = min_sclk_freq * 100;
1090
1091         ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
1092         if (ret)
1093                 return ret;
1094
1095         smu->pstate_mclk = min_mclk_freq * 100;
1096
1097         return ret;
1098 }
1099
1100 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
1101                                                  enum smu_clk_type clk_type,
1102                                                  struct pp_clock_levels_with_latency *clocks)
1103 {
1104         int ret = 0, i = 0;
1105         uint32_t level_count = 0, freq = 0;
1106
1107         switch (clk_type) {
1108         case SMU_GFXCLK:
1109         case SMU_DCEFCLK:
1110         case SMU_SOCCLK:
1111         case SMU_MCLK:
1112         case SMU_UCLK:
1113                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
1114                 if (ret)
1115                         return ret;
1116
1117                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
1118                 clocks->num_levels = level_count;
1119
1120                 for (i = 0; i < level_count; i++) {
1121                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
1122                         if (ret)
1123                                 return ret;
1124
1125                         clocks->data[i].clocks_in_khz = freq * 1000;
1126                         clocks->data[i].latency_in_us = 0;
1127                 }
1128                 break;
1129         default:
1130                 break;
1131         }
1132
1133         return ret;
1134 }
1135
1136 static int navi10_pre_display_config_changed(struct smu_context *smu)
1137 {
1138         int ret = 0;
1139         uint32_t max_freq = 0;
1140
1141         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1142         if (ret)
1143                 return ret;
1144
1145         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1146                 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
1147                 if (ret)
1148                         return ret;
1149                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
1150                 if (ret)
1151                         return ret;
1152         }
1153
1154         return ret;
1155 }
1156
1157 static int navi10_display_config_changed(struct smu_context *smu)
1158 {
1159         int ret = 0;
1160
1161         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1162             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1163             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1164                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1165                                                   smu->display_config->num_display,
1166                                                   NULL);
1167                 if (ret)
1168                         return ret;
1169         }
1170
1171         return ret;
1172 }
1173
1174 static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
1175 {
1176         int ret = 0, i = 0;
1177         uint32_t min_freq, max_freq, force_freq;
1178         enum smu_clk_type clk_type;
1179
1180         enum smu_clk_type clks[] = {
1181                 SMU_GFXCLK,
1182                 SMU_MCLK,
1183                 SMU_SOCCLK,
1184         };
1185
1186         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1187                 clk_type = clks[i];
1188                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
1189                 if (ret)
1190                         return ret;
1191
1192                 force_freq = highest ? max_freq : min_freq;
1193                 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq, false);
1194                 if (ret)
1195                         return ret;
1196         }
1197
1198         return ret;
1199 }
1200
1201 static int navi10_unforce_dpm_levels(struct smu_context *smu)
1202 {
1203         int ret = 0, i = 0;
1204         uint32_t min_freq, max_freq;
1205         enum smu_clk_type clk_type;
1206
1207         enum smu_clk_type clks[] = {
1208                 SMU_GFXCLK,
1209                 SMU_MCLK,
1210                 SMU_SOCCLK,
1211         };
1212
1213         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1214                 clk_type = clks[i];
1215                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
1216                 if (ret)
1217                         return ret;
1218
1219                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
1220                 if (ret)
1221                         return ret;
1222         }
1223
1224         return ret;
1225 }
1226
1227 static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
1228 {
1229         if (!value)
1230                 return -EINVAL;
1231
1232         return navi10_get_smu_metrics_data(smu,
1233                                            METRICS_AVERAGE_SOCKETPOWER,
1234                                            value);
1235 }
1236
1237 static int navi10_get_current_activity_percent(struct smu_context *smu,
1238                                                enum amd_pp_sensors sensor,
1239                                                uint32_t *value)
1240 {
1241         int ret = 0;
1242
1243         if (!value)
1244                 return -EINVAL;
1245
1246         switch (sensor) {
1247         case AMDGPU_PP_SENSOR_GPU_LOAD:
1248                 ret = navi10_get_smu_metrics_data(smu,
1249                                                   METRICS_AVERAGE_GFXACTIVITY,
1250                                                   value);
1251                 break;
1252         case AMDGPU_PP_SENSOR_MEM_LOAD:
1253                 ret = navi10_get_smu_metrics_data(smu,
1254                                                   METRICS_AVERAGE_MEMACTIVITY,
1255                                                   value);
1256                 break;
1257         default:
1258                 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1259                 return -EINVAL;
1260         }
1261
1262         return ret;
1263 }
1264
1265 static bool navi10_is_dpm_running(struct smu_context *smu)
1266 {
1267         int ret = 0;
1268         uint32_t feature_mask[2];
1269         unsigned long feature_enabled;
1270         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1271         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1272                            ((uint64_t)feature_mask[1] << 32));
1273         return !!(feature_enabled & SMC_DPM_FEATURE);
1274 }
1275
1276 static int navi10_get_fan_speed_rpm(struct smu_context *smu,
1277                                     uint32_t *speed)
1278 {
1279         if (!speed)
1280                 return -EINVAL;
1281
1282         return navi10_get_smu_metrics_data(smu,
1283                                            METRICS_CURR_FANSPEED,
1284                                            speed);
1285 }
1286
1287 static int navi10_get_fan_speed_percent(struct smu_context *smu,
1288                                         uint32_t *speed)
1289 {
1290         int ret = 0;
1291         uint32_t percent = 0;
1292         uint32_t current_rpm;
1293         PPTable_t *pptable = smu->smu_table.driver_pptable;
1294
1295         ret = navi10_get_fan_speed_rpm(smu, &current_rpm);
1296         if (ret)
1297                 return ret;
1298
1299         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1300         *speed = percent > 100 ? 100 : percent;
1301
1302         return ret;
1303 }
1304
1305 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1306 {
1307         DpmActivityMonitorCoeffInt_t activity_monitor;
1308         uint32_t i, size = 0;
1309         int16_t workload_type = 0;
1310         static const char *profile_name[] = {
1311                                         "BOOTUP_DEFAULT",
1312                                         "3D_FULL_SCREEN",
1313                                         "POWER_SAVING",
1314                                         "VIDEO",
1315                                         "VR",
1316                                         "COMPUTE",
1317                                         "CUSTOM"};
1318         static const char *title[] = {
1319                         "PROFILE_INDEX(NAME)",
1320                         "CLOCK_TYPE(NAME)",
1321                         "FPS",
1322                         "MinFreqType",
1323                         "MinActiveFreqType",
1324                         "MinActiveFreq",
1325                         "BoosterFreqType",
1326                         "BoosterFreq",
1327                         "PD_Data_limit_c",
1328                         "PD_Data_error_coeff",
1329                         "PD_Data_error_rate_coeff"};
1330         int result = 0;
1331
1332         if (!buf)
1333                 return -EINVAL;
1334
1335         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1336                         title[0], title[1], title[2], title[3], title[4], title[5],
1337                         title[6], title[7], title[8], title[9], title[10]);
1338
1339         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1340                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1341                 workload_type = smu_workload_get_type(smu, i);
1342                 if (workload_type < 0)
1343                         return -EINVAL;
1344
1345                 result = smu_update_table(smu,
1346                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1347                                           (void *)(&activity_monitor), false);
1348                 if (result) {
1349                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1350                         return result;
1351                 }
1352
1353                 size += sprintf(buf + size, "%2d %14s%s:\n",
1354                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1355
1356                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1357                         " ",
1358                         0,
1359                         "GFXCLK",
1360                         activity_monitor.Gfx_FPS,
1361                         activity_monitor.Gfx_MinFreqStep,
1362                         activity_monitor.Gfx_MinActiveFreqType,
1363                         activity_monitor.Gfx_MinActiveFreq,
1364                         activity_monitor.Gfx_BoosterFreqType,
1365                         activity_monitor.Gfx_BoosterFreq,
1366                         activity_monitor.Gfx_PD_Data_limit_c,
1367                         activity_monitor.Gfx_PD_Data_error_coeff,
1368                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1369
1370                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1371                         " ",
1372                         1,
1373                         "SOCCLK",
1374                         activity_monitor.Soc_FPS,
1375                         activity_monitor.Soc_MinFreqStep,
1376                         activity_monitor.Soc_MinActiveFreqType,
1377                         activity_monitor.Soc_MinActiveFreq,
1378                         activity_monitor.Soc_BoosterFreqType,
1379                         activity_monitor.Soc_BoosterFreq,
1380                         activity_monitor.Soc_PD_Data_limit_c,
1381                         activity_monitor.Soc_PD_Data_error_coeff,
1382                         activity_monitor.Soc_PD_Data_error_rate_coeff);
1383
1384                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1385                         " ",
1386                         2,
1387                         "MEMLK",
1388                         activity_monitor.Mem_FPS,
1389                         activity_monitor.Mem_MinFreqStep,
1390                         activity_monitor.Mem_MinActiveFreqType,
1391                         activity_monitor.Mem_MinActiveFreq,
1392                         activity_monitor.Mem_BoosterFreqType,
1393                         activity_monitor.Mem_BoosterFreq,
1394                         activity_monitor.Mem_PD_Data_limit_c,
1395                         activity_monitor.Mem_PD_Data_error_coeff,
1396                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1397         }
1398
1399         return size;
1400 }
1401
1402 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1403 {
1404         DpmActivityMonitorCoeffInt_t activity_monitor;
1405         int workload_type, ret = 0;
1406
1407         smu->power_profile_mode = input[size];
1408
1409         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1410                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1411                 return -EINVAL;
1412         }
1413
1414         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1415
1416                 ret = smu_update_table(smu,
1417                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1418                                        (void *)(&activity_monitor), false);
1419                 if (ret) {
1420                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1421                         return ret;
1422                 }
1423
1424                 switch (input[0]) {
1425                 case 0: /* Gfxclk */
1426                         activity_monitor.Gfx_FPS = input[1];
1427                         activity_monitor.Gfx_MinFreqStep = input[2];
1428                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1429                         activity_monitor.Gfx_MinActiveFreq = input[4];
1430                         activity_monitor.Gfx_BoosterFreqType = input[5];
1431                         activity_monitor.Gfx_BoosterFreq = input[6];
1432                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1433                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1434                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1435                         break;
1436                 case 1: /* Socclk */
1437                         activity_monitor.Soc_FPS = input[1];
1438                         activity_monitor.Soc_MinFreqStep = input[2];
1439                         activity_monitor.Soc_MinActiveFreqType = input[3];
1440                         activity_monitor.Soc_MinActiveFreq = input[4];
1441                         activity_monitor.Soc_BoosterFreqType = input[5];
1442                         activity_monitor.Soc_BoosterFreq = input[6];
1443                         activity_monitor.Soc_PD_Data_limit_c = input[7];
1444                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
1445                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1446                         break;
1447                 case 2: /* Memlk */
1448                         activity_monitor.Mem_FPS = input[1];
1449                         activity_monitor.Mem_MinFreqStep = input[2];
1450                         activity_monitor.Mem_MinActiveFreqType = input[3];
1451                         activity_monitor.Mem_MinActiveFreq = input[4];
1452                         activity_monitor.Mem_BoosterFreqType = input[5];
1453                         activity_monitor.Mem_BoosterFreq = input[6];
1454                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1455                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1456                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1457                         break;
1458                 }
1459
1460                 ret = smu_update_table(smu,
1461                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1462                                        (void *)(&activity_monitor), true);
1463                 if (ret) {
1464                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1465                         return ret;
1466                 }
1467         }
1468
1469         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1470         workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1471         if (workload_type < 0)
1472                 return -EINVAL;
1473         smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1474                                     1 << workload_type, NULL);
1475
1476         return ret;
1477 }
1478
1479 static int navi10_get_profiling_clk_mask(struct smu_context *smu,
1480                                          enum amd_dpm_forced_level level,
1481                                          uint32_t *sclk_mask,
1482                                          uint32_t *mclk_mask,
1483                                          uint32_t *soc_mask)
1484 {
1485         int ret = 0;
1486         uint32_t level_count = 0;
1487
1488         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1489                 if (sclk_mask)
1490                         *sclk_mask = 0;
1491         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1492                 if (mclk_mask)
1493                         *mclk_mask = 0;
1494         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1495                 if(sclk_mask) {
1496                         ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1497                         if (ret)
1498                                 return ret;
1499                         *sclk_mask = level_count - 1;
1500                 }
1501
1502                 if(mclk_mask) {
1503                         ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1504                         if (ret)
1505                                 return ret;
1506                         *mclk_mask = level_count - 1;
1507                 }
1508
1509                 if(soc_mask) {
1510                         ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1511                         if (ret)
1512                                 return ret;
1513                         *soc_mask = level_count - 1;
1514                 }
1515         }
1516
1517         return ret;
1518 }
1519
1520 static int navi10_notify_smc_display_config(struct smu_context *smu)
1521 {
1522         struct smu_clocks min_clocks = {0};
1523         struct pp_display_clock_request clock_req;
1524         int ret = 0;
1525
1526         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1527         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1528         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1529
1530         if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1531                 clock_req.clock_type = amd_pp_dcef_clock;
1532                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1533
1534                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1535                 if (!ret) {
1536                         if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1537                                 ret = smu_send_smc_msg_with_param(smu,
1538                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1539                                                                   min_clocks.dcef_clock_in_sr/100,
1540                                                                   NULL);
1541                                 if (ret) {
1542                                         dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1543                                         return ret;
1544                                 }
1545                         }
1546                 } else {
1547                         dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1548                 }
1549         }
1550
1551         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1552                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1553                 if (ret) {
1554                         dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1555                         return ret;
1556                 }
1557         }
1558
1559         return 0;
1560 }
1561
1562 static int navi10_set_watermarks_table(struct smu_context *smu,
1563                                        void *watermarks, struct
1564                                        dm_pp_wm_sets_with_clock_ranges_soc15
1565                                        *clock_ranges)
1566 {
1567         int i;
1568         int ret = 0;
1569         Watermarks_t *table = watermarks;
1570
1571         if (!table || !clock_ranges)
1572                 return -EINVAL;
1573
1574         if (clock_ranges->num_wm_dmif_sets > 4 ||
1575             clock_ranges->num_wm_mcif_sets > 4)
1576                 return -EINVAL;
1577
1578         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1579                 table->WatermarkRow[1][i].MinClock =
1580                         cpu_to_le16((uint16_t)
1581                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1582                         1000));
1583                 table->WatermarkRow[1][i].MaxClock =
1584                         cpu_to_le16((uint16_t)
1585                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1586                         1000));
1587                 table->WatermarkRow[1][i].MinUclk =
1588                         cpu_to_le16((uint16_t)
1589                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1590                         1000));
1591                 table->WatermarkRow[1][i].MaxUclk =
1592                         cpu_to_le16((uint16_t)
1593                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1594                         1000));
1595                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1596                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1597         }
1598
1599         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1600                 table->WatermarkRow[0][i].MinClock =
1601                         cpu_to_le16((uint16_t)
1602                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1603                         1000));
1604                 table->WatermarkRow[0][i].MaxClock =
1605                         cpu_to_le16((uint16_t)
1606                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1607                         1000));
1608                 table->WatermarkRow[0][i].MinUclk =
1609                         cpu_to_le16((uint16_t)
1610                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1611                         1000));
1612                 table->WatermarkRow[0][i].MaxUclk =
1613                         cpu_to_le16((uint16_t)
1614                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1615                         1000));
1616                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1617                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1618         }
1619
1620         smu->watermarks_bitmap |= WATERMARKS_EXIST;
1621
1622         /* pass data to smu controller */
1623         if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1624                 ret = smu_write_watermarks_table(smu);
1625                 if (ret) {
1626                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1627                         return ret;
1628                 }
1629                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1630         }
1631
1632         return 0;
1633 }
1634
1635 static int navi10_thermal_get_temperature(struct smu_context *smu,
1636                                              enum amd_pp_sensors sensor,
1637                                              uint32_t *value)
1638 {
1639         int ret = 0;
1640
1641         if (!value)
1642                 return -EINVAL;
1643
1644         switch (sensor) {
1645         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1646                 ret = navi10_get_smu_metrics_data(smu,
1647                                                   METRICS_TEMPERATURE_HOTSPOT,
1648                                                   value);
1649                 break;
1650         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1651                 ret = navi10_get_smu_metrics_data(smu,
1652                                                   METRICS_TEMPERATURE_EDGE,
1653                                                   value);
1654                 break;
1655         case AMDGPU_PP_SENSOR_MEM_TEMP:
1656                 ret = navi10_get_smu_metrics_data(smu,
1657                                                   METRICS_TEMPERATURE_MEM,
1658                                                   value);
1659                 break;
1660         default:
1661                 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1662                 return -EINVAL;
1663         }
1664
1665         return ret;
1666 }
1667
1668 static int navi10_read_sensor(struct smu_context *smu,
1669                                  enum amd_pp_sensors sensor,
1670                                  void *data, uint32_t *size)
1671 {
1672         int ret = 0;
1673         struct smu_table_context *table_context = &smu->smu_table;
1674         PPTable_t *pptable = table_context->driver_pptable;
1675
1676         if(!data || !size)
1677                 return -EINVAL;
1678
1679         mutex_lock(&smu->sensor_lock);
1680         switch (sensor) {
1681         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1682                 *(uint32_t *)data = pptable->FanMaximumRpm;
1683                 *size = 4;
1684                 break;
1685         case AMDGPU_PP_SENSOR_MEM_LOAD:
1686         case AMDGPU_PP_SENSOR_GPU_LOAD:
1687                 ret = navi10_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1688                 *size = 4;
1689                 break;
1690         case AMDGPU_PP_SENSOR_GPU_POWER:
1691                 ret = navi10_get_gpu_power(smu, (uint32_t *)data);
1692                 *size = 4;
1693                 break;
1694         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1695         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1696         case AMDGPU_PP_SENSOR_MEM_TEMP:
1697                 ret = navi10_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1698                 *size = 4;
1699                 break;
1700         default:
1701                 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1702         }
1703         mutex_unlock(&smu->sensor_lock);
1704
1705         return ret;
1706 }
1707
1708 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1709 {
1710         uint32_t num_discrete_levels = 0;
1711         uint16_t *dpm_levels = NULL;
1712         uint16_t i = 0;
1713         struct smu_table_context *table_context = &smu->smu_table;
1714         PPTable_t *driver_ppt = NULL;
1715
1716         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1717                 return -EINVAL;
1718
1719         driver_ppt = table_context->driver_pptable;
1720         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1721         dpm_levels = driver_ppt->FreqTableUclk;
1722
1723         if (num_discrete_levels == 0 || dpm_levels == NULL)
1724                 return -EINVAL;
1725
1726         *num_states = num_discrete_levels;
1727         for (i = 0; i < num_discrete_levels; i++) {
1728                 /* convert to khz */
1729                 *clocks_in_khz = (*dpm_levels) * 1000;
1730                 clocks_in_khz++;
1731                 dpm_levels++;
1732         }
1733
1734         return 0;
1735 }
1736
1737 static int navi10_set_performance_level(struct smu_context *smu,
1738                                         enum amd_dpm_forced_level level);
1739
1740 static int navi10_set_standard_performance_level(struct smu_context *smu)
1741 {
1742         struct amdgpu_device *adev = smu->adev;
1743         int ret = 0;
1744         uint32_t sclk_freq = 0, uclk_freq = 0;
1745
1746         switch (adev->asic_type) {
1747         case CHIP_NAVI10:
1748                 sclk_freq = NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
1749                 uclk_freq = NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
1750                 break;
1751         case CHIP_NAVI14:
1752                 sclk_freq = NAVI14_UMD_PSTATE_PROFILING_GFXCLK;
1753                 uclk_freq = NAVI14_UMD_PSTATE_PROFILING_MEMCLK;
1754                 break;
1755         default:
1756                 /* by default, this is same as auto performance level */
1757                 return navi10_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
1758         }
1759
1760         ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
1761         if (ret)
1762                 return ret;
1763         ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
1764         if (ret)
1765                 return ret;
1766
1767         return ret;
1768 }
1769
1770 static int navi10_set_peak_performance_level(struct smu_context *smu)
1771 {
1772         struct amdgpu_device *adev = smu->adev;
1773         int ret = 0;
1774         uint32_t sclk_freq = 0, uclk_freq = 0;
1775
1776         switch (adev->asic_type) {
1777         case CHIP_NAVI10:
1778                 switch (adev->pdev->revision) {
1779                 case 0xf0: /* XTX */
1780                 case 0xc0:
1781                         sclk_freq = NAVI10_PEAK_SCLK_XTX;
1782                         break;
1783                 case 0xf1: /* XT */
1784                 case 0xc1:
1785                         sclk_freq = NAVI10_PEAK_SCLK_XT;
1786                         break;
1787                 default: /* XL */
1788                         sclk_freq = NAVI10_PEAK_SCLK_XL;
1789                         break;
1790                 }
1791                 break;
1792         case CHIP_NAVI14:
1793                 switch (adev->pdev->revision) {
1794                 case 0xc7: /* XT */
1795                 case 0xf4:
1796                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1797                         break;
1798                 case 0xc1: /* XTM */
1799                 case 0xf2:
1800                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1801                         break;
1802                 case 0xc3: /* XLM */
1803                 case 0xf3:
1804                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1805                         break;
1806                 case 0xc5: /* XTX */
1807                 case 0xf6:
1808                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1809                         break;
1810                 default: /* XL */
1811                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1812                         break;
1813                 }
1814                 break;
1815         case CHIP_NAVI12:
1816                 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
1817                 break;
1818         default:
1819                 ret = smu_get_dpm_level_range(smu, SMU_SCLK, NULL, &sclk_freq);
1820                 if (ret)
1821                         return ret;
1822         }
1823
1824         ret = smu_get_dpm_level_range(smu, SMU_UCLK, NULL, &uclk_freq);
1825         if (ret)
1826                 return ret;
1827
1828         ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
1829         if (ret)
1830                 return ret;
1831         ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
1832         if (ret)
1833                 return ret;
1834
1835         return ret;
1836 }
1837
1838 static int navi10_set_performance_level(struct smu_context *smu,
1839                                         enum amd_dpm_forced_level level)
1840 {
1841         int ret = 0;
1842         uint32_t sclk_mask, mclk_mask, soc_mask;
1843
1844         switch (level) {
1845         case AMD_DPM_FORCED_LEVEL_HIGH:
1846                 ret = smu_force_dpm_limit_value(smu, true);
1847                 break;
1848         case AMD_DPM_FORCED_LEVEL_LOW:
1849                 ret = smu_force_dpm_limit_value(smu, false);
1850                 break;
1851         case AMD_DPM_FORCED_LEVEL_AUTO:
1852                 ret = smu_unforce_dpm_levels(smu);
1853                 break;
1854         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1855                 ret = navi10_set_standard_performance_level(smu);
1856                 break;
1857         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1858         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1859                 ret = smu_get_profiling_clk_mask(smu, level,
1860                                                  &sclk_mask,
1861                                                  &mclk_mask,
1862                                                  &soc_mask);
1863                 if (ret)
1864                         return ret;
1865                 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1866                 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1867                 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1868                 break;
1869         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1870                 ret = navi10_set_peak_performance_level(smu);
1871                 break;
1872         case AMD_DPM_FORCED_LEVEL_MANUAL:
1873         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1874         default:
1875                 break;
1876         }
1877         return ret;
1878 }
1879
1880 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
1881                                                 struct smu_temperature_range *range)
1882 {
1883         struct smu_table_context *table_context = &smu->smu_table;
1884         struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1885
1886         if (!range || !powerplay_table)
1887                 return -EINVAL;
1888
1889         range->max = powerplay_table->software_shutdown_temp *
1890                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1891
1892         return 0;
1893 }
1894
1895 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
1896                                                 bool disable_memory_clock_switch)
1897 {
1898         int ret = 0;
1899         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1900                 (struct smu_11_0_max_sustainable_clocks *)
1901                         smu->smu_table.max_sustainable_clocks;
1902         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1903         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1904
1905         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1906                 return 0;
1907
1908         if(disable_memory_clock_switch)
1909                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1910         else
1911                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1912
1913         if(!ret)
1914                 smu->disable_uclk_switch = disable_memory_clock_switch;
1915
1916         return ret;
1917 }
1918
1919 static int navi10_get_power_limit(struct smu_context *smu)
1920 {
1921         struct smu_11_0_powerplay_table *powerplay_table =
1922                 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1923         struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
1924         PPTable_t *pptable = smu->smu_table.driver_pptable;
1925         uint32_t power_limit, od_percent;
1926
1927         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1928                 /* the last hope to figure out the ppt limit */
1929                 if (!pptable) {
1930                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1931                         return -EINVAL;
1932                 }
1933                 power_limit =
1934                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1935         }
1936         smu->current_power_limit = power_limit;
1937
1938         if (smu->od_enabled &&
1939             navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {
1940                 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1941
1942                 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1943
1944                 power_limit *= (100 + od_percent);
1945                 power_limit /= 100;
1946         }
1947         smu->max_power_limit = power_limit;
1948
1949         return 0;
1950 }
1951
1952 static int navi10_update_pcie_parameters(struct smu_context *smu,
1953                                      uint32_t pcie_gen_cap,
1954                                      uint32_t pcie_width_cap)
1955 {
1956         PPTable_t *pptable = smu->smu_table.driver_pptable;
1957         int ret, i;
1958         uint32_t smu_pcie_arg;
1959
1960         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1961         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1962
1963         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1964                 smu_pcie_arg = (i << 16) |
1965                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
1966                                 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1967                                         pptable->PcieLaneCount[i] : pcie_width_cap);
1968                 ret = smu_send_smc_msg_with_param(smu,
1969                                           SMU_MSG_OverridePcieParameters,
1970                                           smu_pcie_arg,
1971                                           NULL);
1972
1973                 if (ret)
1974                         return ret;
1975
1976                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1977                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1978                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1979                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1980         }
1981
1982         return 0;
1983 }
1984
1985 static inline void navi10_dump_od_table(struct smu_context *smu,
1986                                         OverDriveTable_t *od_table)
1987 {
1988         dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1989         dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
1990         dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
1991         dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
1992         dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax);
1993         dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct);
1994 }
1995
1996 static int navi10_od_setting_check_range(struct smu_context *smu,
1997                                          struct smu_11_0_overdrive_table *od_table,
1998                                          enum SMU_11_0_ODSETTING_ID setting,
1999                                          uint32_t value)
2000 {
2001         if (value < od_table->min[setting]) {
2002                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
2003                 return -EINVAL;
2004         }
2005         if (value > od_table->max[setting]) {
2006                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
2007                 return -EINVAL;
2008         }
2009         return 0;
2010 }
2011
2012 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
2013                                                      uint16_t *voltage,
2014                                                      uint32_t freq)
2015 {
2016         uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16);
2017         uint32_t value = 0;
2018         int ret;
2019
2020         ret = smu_send_smc_msg_with_param(smu,
2021                                           SMU_MSG_GetVoltageByDpm,
2022                                           param,
2023                                           &value);
2024         if (ret) {
2025                 dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
2026                 return ret;
2027         }
2028
2029         *voltage = (uint16_t)value;
2030
2031         return 0;
2032 }
2033
2034 static bool navi10_is_baco_supported(struct smu_context *smu)
2035 {
2036         struct amdgpu_device *adev = smu->adev;
2037         uint32_t val;
2038
2039         if (!smu_v11_0_baco_is_support(smu))
2040                 return false;
2041
2042         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
2043         return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
2044 }
2045
2046 static int navi10_set_default_od_settings(struct smu_context *smu)
2047 {
2048         OverDriveTable_t *od_table =
2049                 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2050         OverDriveTable_t *boot_od_table =
2051                 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2052         int ret = 0;
2053
2054         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, false);
2055         if (ret) {
2056                 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2057                 return ret;
2058         }
2059
2060         if (!od_table->GfxclkVolt1) {
2061                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2062                                                                 &od_table->GfxclkVolt1,
2063                                                                 od_table->GfxclkFreq1);
2064                 if (ret)
2065                         return ret;
2066         }
2067
2068         if (!od_table->GfxclkVolt2) {
2069                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2070                                                                 &od_table->GfxclkVolt2,
2071                                                                 od_table->GfxclkFreq2);
2072                 if (ret)
2073                         return ret;
2074         }
2075
2076         if (!od_table->GfxclkVolt3) {
2077                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2078                                                                 &od_table->GfxclkVolt3,
2079                                                                 od_table->GfxclkFreq3);
2080                 if (ret)
2081                         return ret;
2082         }
2083
2084         memcpy(boot_od_table, od_table, sizeof(OverDriveTable_t));
2085
2086         navi10_dump_od_table(smu, od_table);
2087
2088         return 0;
2089 }
2090
2091 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) {
2092         int i;
2093         int ret = 0;
2094         struct smu_table_context *table_context = &smu->smu_table;
2095         OverDriveTable_t *od_table;
2096         struct smu_11_0_overdrive_table *od_settings;
2097         enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
2098         uint16_t *freq_ptr, *voltage_ptr;
2099         od_table = (OverDriveTable_t *)table_context->overdrive_table;
2100
2101         if (!smu->od_enabled) {
2102                 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2103                 return -EINVAL;
2104         }
2105
2106         if (!smu->od_settings) {
2107                 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2108                 return -ENOENT;
2109         }
2110
2111         od_settings = smu->od_settings;
2112
2113         switch (type) {
2114         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2115                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
2116                         dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2117                         return -ENOTSUPP;
2118                 }
2119                 if (!table_context->overdrive_table) {
2120                         dev_err(smu->adev->dev, "Overdrive is not initialized\n");
2121                         return -EINVAL;
2122                 }
2123                 for (i = 0; i < size; i += 2) {
2124                         if (i + 2 > size) {
2125                                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2126                                 return -EINVAL;
2127                         }
2128                         switch (input[i]) {
2129                         case 0:
2130                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
2131                                 freq_ptr = &od_table->GfxclkFmin;
2132                                 if (input[i + 1] > od_table->GfxclkFmax) {
2133                                         dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2134                                                 input[i + 1],
2135                                                 od_table->GfxclkFmin);
2136                                         return -EINVAL;
2137                                 }
2138                                 break;
2139                         case 1:
2140                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
2141                                 freq_ptr = &od_table->GfxclkFmax;
2142                                 if (input[i + 1] < od_table->GfxclkFmin) {
2143                                         dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2144                                                 input[i + 1],
2145                                                 od_table->GfxclkFmax);
2146                                         return -EINVAL;
2147                                 }
2148                                 break;
2149                         default:
2150                                 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2151                                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2152                                 return -EINVAL;
2153                         }
2154                         ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]);
2155                         if (ret)
2156                                 return ret;
2157                         *freq_ptr = input[i + 1];
2158                 }
2159                 break;
2160         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2161                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
2162                         dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n");
2163                         return -ENOTSUPP;
2164                 }
2165                 if (size < 2) {
2166                         dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2167                         return -EINVAL;
2168                 }
2169                 if (input[0] != 1) {
2170                         dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
2171                         dev_info(smu->adev->dev, "Supported indices: [1:max]\n");
2172                         return -EINVAL;
2173                 }
2174                 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
2175                 if (ret)
2176                         return ret;
2177                 od_table->UclkFmax = input[1];
2178                 break;
2179         case PP_OD_RESTORE_DEFAULT_TABLE:
2180                 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2181                         dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2182                         return -EINVAL;
2183                 }
2184                 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t));
2185                 break;
2186         case PP_OD_COMMIT_DPM_TABLE:
2187                 navi10_dump_od_table(smu, od_table);
2188                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2189                 if (ret) {
2190                         dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2191                         return ret;
2192                 }
2193                 // no lock needed because smu_od_edit_dpm_table has it
2194                 ret = smu_handle_task(smu, smu->smu_dpm.dpm_level,
2195                         AMD_PP_TASK_READJUST_POWER_STATE,
2196                         false);
2197                 if (ret) {
2198                         return ret;
2199                 }
2200                 break;
2201         case PP_OD_EDIT_VDDC_CURVE:
2202                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
2203                         dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n");
2204                         return -ENOTSUPP;
2205                 }
2206                 if (size < 3) {
2207                         dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2208                         return -EINVAL;
2209                 }
2210                 if (!od_table) {
2211                         dev_info(smu->adev->dev, "Overdrive is not initialized\n");
2212                         return -EINVAL;
2213                 }
2214
2215                 switch (input[0]) {
2216                 case 0:
2217                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
2218                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
2219                         freq_ptr = &od_table->GfxclkFreq1;
2220                         voltage_ptr = &od_table->GfxclkVolt1;
2221                         break;
2222                 case 1:
2223                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
2224                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
2225                         freq_ptr = &od_table->GfxclkFreq2;
2226                         voltage_ptr = &od_table->GfxclkVolt2;
2227                         break;
2228                 case 2:
2229                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
2230                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
2231                         freq_ptr = &od_table->GfxclkFreq3;
2232                         voltage_ptr = &od_table->GfxclkVolt3;
2233                         break;
2234                 default:
2235                         dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]);
2236                         dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n");
2237                         return -EINVAL;
2238                 }
2239                 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]);
2240                 if (ret)
2241                         return ret;
2242                 // Allow setting zero to disable the OverDrive VDDC curve
2243                 if (input[2] != 0) {
2244                         ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]);
2245                         if (ret)
2246                                 return ret;
2247                         *freq_ptr = input[1];
2248                         *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
2249                         dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
2250                 } else {
2251                         // If setting 0, disable all voltage curve settings
2252                         od_table->GfxclkVolt1 = 0;
2253                         od_table->GfxclkVolt2 = 0;
2254                         od_table->GfxclkVolt3 = 0;
2255                 }
2256                 navi10_dump_od_table(smu, od_table);
2257                 break;
2258         default:
2259                 return -ENOSYS;
2260         }
2261         return ret;
2262 }
2263
2264 static int navi10_run_btc(struct smu_context *smu)
2265 {
2266         int ret = 0;
2267
2268         ret = smu_send_smc_msg(smu, SMU_MSG_RunBtc, NULL);
2269         if (ret)
2270                 dev_err(smu->adev->dev, "RunBtc failed!\n");
2271
2272         return ret;
2273 }
2274
2275 static int navi10_dummy_pstate_control(struct smu_context *smu, bool enable)
2276 {
2277         int result = 0;
2278
2279         if (!enable)
2280                 result = smu_send_smc_msg(smu, SMU_MSG_DAL_DISABLE_DUMMY_PSTATE_CHANGE, NULL);
2281         else
2282                 result = smu_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL);
2283
2284         return result;
2285 }
2286
2287 static inline bool navi10_need_umc_cdr_12gbps_workaround(struct amdgpu_device *adev)
2288 {
2289         if (adev->asic_type != CHIP_NAVI10)
2290                 return false;
2291
2292         if (adev->pdev->device == 0x731f &&
2293             (adev->pdev->revision == 0xc2 ||
2294              adev->pdev->revision == 0xc3 ||
2295              adev->pdev->revision == 0xca ||
2296              adev->pdev->revision == 0xcb))
2297                 return true;
2298         else
2299                 return false;
2300 }
2301
2302 static int navi10_disable_umc_cdr_12gbps_workaround(struct smu_context *smu)
2303 {
2304         uint32_t uclk_count, uclk_min, uclk_max;
2305         uint32_t smu_version;
2306         int ret = 0;
2307
2308         if (!navi10_need_umc_cdr_12gbps_workaround(smu->adev))
2309                 return 0;
2310
2311         ret = smu_get_smc_version(smu, NULL, &smu_version);
2312         if (ret)
2313                 return ret;
2314
2315         /* This workaround is available only for 42.50 or later SMC firmwares */
2316         if (smu_version < 0x2A3200)
2317                 return 0;
2318
2319         ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_count);
2320         if (ret)
2321                 return ret;
2322
2323         ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min);
2324         if (ret)
2325                 return ret;
2326
2327         ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max);
2328         if (ret)
2329                 return ret;
2330
2331         /* Force UCLK out of the highest DPM */
2332         ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, uclk_min);
2333         if (ret)
2334                 return ret;
2335
2336         /* Revert the UCLK Hardmax */
2337         ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, uclk_max);
2338         if (ret)
2339                 return ret;
2340
2341         /*
2342          * In this case, SMU already disabled dummy pstate during enablement
2343          * of UCLK DPM, we have to re-enabled it.
2344          * */
2345         return navi10_dummy_pstate_control(smu, true);
2346 }
2347
2348 static int navi10_set_thermal_range(struct smu_context *smu,
2349                                        struct smu_temperature_range range)
2350 {
2351         struct amdgpu_device *adev = smu->adev;
2352         int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
2353         int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
2354         uint32_t val;
2355         struct smu_table_context *table_context = &smu->smu_table;
2356         struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
2357
2358         low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
2359                         range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
2360         high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp);
2361
2362         if (low > high)
2363                 return -EINVAL;
2364
2365         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
2366         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
2367         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
2368         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
2369         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
2370         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
2371         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
2372         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
2373
2374         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
2375
2376         return 0;
2377 }
2378
2379 static const struct pptable_funcs navi10_ppt_funcs = {
2380         .tables_init = navi10_tables_init,
2381         .alloc_dpm_context = navi10_allocate_dpm_context,
2382         .get_smu_msg_index = navi10_get_smu_msg_index,
2383         .get_smu_clk_index = navi10_get_smu_clk_index,
2384         .get_smu_feature_index = navi10_get_smu_feature_index,
2385         .get_smu_table_index = navi10_get_smu_table_index,
2386         .get_smu_power_index = navi10_get_pwr_src_index,
2387         .get_workload_type = navi10_get_workload_type,
2388         .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
2389         .set_default_dpm_table = navi10_set_default_dpm_table,
2390         .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,
2391         .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
2392         .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
2393         .print_clk_levels = navi10_print_clk_levels,
2394         .force_clk_levels = navi10_force_clk_levels,
2395         .populate_umd_state_clk = navi10_populate_umd_state_clk,
2396         .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
2397         .pre_display_config_changed = navi10_pre_display_config_changed,
2398         .display_config_changed = navi10_display_config_changed,
2399         .notify_smc_display_config = navi10_notify_smc_display_config,
2400         .force_dpm_limit_value = navi10_force_dpm_limit_value,
2401         .unforce_dpm_levels = navi10_unforce_dpm_levels,
2402         .is_dpm_running = navi10_is_dpm_running,
2403         .get_fan_speed_percent = navi10_get_fan_speed_percent,
2404         .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
2405         .get_power_profile_mode = navi10_get_power_profile_mode,
2406         .set_power_profile_mode = navi10_set_power_profile_mode,
2407         .get_profiling_clk_mask = navi10_get_profiling_clk_mask,
2408         .set_watermarks_table = navi10_set_watermarks_table,
2409         .read_sensor = navi10_read_sensor,
2410         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
2411         .set_performance_level = navi10_set_performance_level,
2412         .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
2413         .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
2414         .get_power_limit = navi10_get_power_limit,
2415         .update_pcie_parameters = navi10_update_pcie_parameters,
2416         .init_microcode = smu_v11_0_init_microcode,
2417         .load_microcode = smu_v11_0_load_microcode,
2418         .fini_microcode = smu_v11_0_fini_microcode,
2419         .init_smc_tables = smu_v11_0_init_smc_tables,
2420         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2421         .init_power = smu_v11_0_init_power,
2422         .fini_power = smu_v11_0_fini_power,
2423         .check_fw_status = smu_v11_0_check_fw_status,
2424         .setup_pptable = navi10_setup_pptable,
2425         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2426         .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2427         .check_fw_version = smu_v11_0_check_fw_version,
2428         .write_pptable = smu_v11_0_write_pptable,
2429         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2430         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2431         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2432         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2433         .system_features_control = smu_v11_0_system_features_control,
2434         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2435         .init_display_count = smu_v11_0_init_display_count,
2436         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2437         .get_enabled_mask = smu_v11_0_get_enabled_mask,
2438         .notify_display_change = smu_v11_0_notify_display_change,
2439         .set_power_limit = smu_v11_0_set_power_limit,
2440         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2441         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2442         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2443         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2444         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2445         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2446         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2447         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2448         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2449         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2450         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2451         .gfx_off_control = smu_v11_0_gfx_off_control,
2452         .register_irq_handler = smu_v11_0_register_irq_handler,
2453         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2454         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2455         .baco_is_support= navi10_is_baco_supported,
2456         .baco_get_state = smu_v11_0_baco_get_state,
2457         .baco_set_state = smu_v11_0_baco_set_state,
2458         .baco_enter = smu_v11_0_baco_enter,
2459         .baco_exit = smu_v11_0_baco_exit,
2460         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2461         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2462         .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2463         .set_default_od_settings = navi10_set_default_od_settings,
2464         .od_edit_dpm_table = navi10_od_edit_dpm_table,
2465         .run_btc = navi10_run_btc,
2466         .disable_umc_cdr_12gbps_workaround = navi10_disable_umc_cdr_12gbps_workaround,
2467         .set_power_source = smu_v11_0_set_power_source,
2468         .set_thermal_range = navi10_set_thermal_range,
2469 };
2470
2471 void navi10_set_ppt_funcs(struct smu_context *smu)
2472 {
2473         smu->ppt_funcs = &navi10_ppt_funcs;
2474 }