drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/fb.h>
  26 #include <linux/module.h>
  27 #include <linux/slab.h>
  28
  29 #include "hwmgr.h"
  30 #include "amd_powerplay.h"
  31 #include "vega20_smumgr.h"
  32 #include "hardwaremanager.h"
  33 #include "ppatomfwctrl.h"
  34 #include "atomfirmware.h"
  35 #include "cgs_common.h"
  36 #include "vega20_powertune.h"
  37 #include "vega20_inc.h"
  38 #include "pppcielanes.h"
  39 #include "vega20_hwmgr.h"
  40 #include "vega20_processpptables.h"
  41 #include "vega20_pptable.h"
  42 #include "vega20_thermal.h"
  43 #include "vega20_ppsmc.h"
  44 #include "pp_debug.h"
  45 #include "amd_pcie_helpers.h"
  46 #include "ppinterrupt.h"
  47 #include "pp_overdriver.h"
  48 #include "pp_thermal.h"
  49 #include "soc15_common.h"
  50 #include "smuio/smuio_9_0_offset.h"
  51 #include "smuio/smuio_9_0_sh_mask.h"
  52
  53 static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
  54 {
  55         struct vega20_hwmgr *data =
  56                         (struct vega20_hwmgr *)(hwmgr->backend);
  57
  58         data->gfxclk_average_alpha = PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT;
  59         data->socclk_average_alpha = PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT;
  60         data->uclk_average_alpha = PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT;
  61         data->gfx_activity_average_alpha = PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT;
  62         data->lowest_uclk_reserved_for_ulv = PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT;
  63
  64         data->display_voltage_mode = PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT;
  65         data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  66         data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  67         data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  68         data->disp_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  69         data->disp_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  70         data->disp_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  71         data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  72         data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  73         data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  74         data->phy_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  75         data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  76         data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  77
  78         data->registry_data.disallowed_features = 0x0;
  79         data->registry_data.od_state_in_dc_support = 0;
  80         data->registry_data.thermal_support = 1;
  81         data->registry_data.skip_baco_hardware = 0;
  82
  83         data->registry_data.log_avfs_param = 0;
  84         data->registry_data.sclk_throttle_low_notification = 1;
  85         data->registry_data.force_dpm_high = 0;
  86         data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
  87
  88         data->registry_data.didt_support = 0;
  89         if (data->registry_data.didt_support) {
  90                 data->registry_data.didt_mode = 6;
  91                 data->registry_data.sq_ramping_support = 1;
  92                 data->registry_data.db_ramping_support = 0;
  93                 data->registry_data.td_ramping_support = 0;
  94                 data->registry_data.tcp_ramping_support = 0;
  95                 data->registry_data.dbr_ramping_support = 0;
  96                 data->registry_data.edc_didt_support = 1;
  97                 data->registry_data.gc_didt_support = 0;
  98                 data->registry_data.psm_didt_support = 0;
  99         }
 100
 101         data->registry_data.pcie_lane_override = 0xff;
 102         data->registry_data.pcie_speed_override = 0xff;
 103         data->registry_data.pcie_clock_override = 0xffffffff;
 104         data->registry_data.regulator_hot_gpio_support = 1;
 105         data->registry_data.ac_dc_switch_gpio_support = 0;
 106         data->registry_data.quick_transition_support = 0;
 107         data->registry_data.zrpm_start_temp = 0xffff;
 108         data->registry_data.zrpm_stop_temp = 0xffff;
 109         data->registry_data.od8_feature_enable = 1;
 110         data->registry_data.disable_water_mark = 0;
 111         data->registry_data.disable_pp_tuning = 0;
 112         data->registry_data.disable_xlpp_tuning = 0;
 113         data->registry_data.disable_workload_policy = 0;
 114         data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
 115         data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
 116         data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
 117         data->registry_data.force_workload_policy_mask = 0;
 118         data->registry_data.disable_3d_fs_detection = 0;
 119         data->registry_data.fps_support = 1;
 120         data->registry_data.disable_auto_wattman = 1;
 121         data->registry_data.auto_wattman_debug = 0;
 122         data->registry_data.auto_wattman_sample_period = 100;
 123         data->registry_data.fclk_gfxclk_ratio = 0x3F6CCCCD;
 124         data->registry_data.auto_wattman_threshold = 50;
 125         data->registry_data.gfxoff_controlled_by_driver = 1;
 126         data->gfxoff_allowed = false;
 127         data->counter_gfxoff = 0;
 128 }
 129
 130 static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
 131 {
 132         struct vega20_hwmgr *data =
 133                         (struct vega20_hwmgr *)(hwmgr->backend);
 134         struct amdgpu_device *adev = hwmgr->adev;
 135
 136         if (data->vddci_control == VEGA20_VOLTAGE_CONTROL_NONE)
 137                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 138                                 PHM_PlatformCaps_ControlVDDCI);
 139
 140         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 141                         PHM_PlatformCaps_TablelessHardwareInterface);
 142
 143         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 144                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
 145
 146         if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
 147                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 148                                 PHM_PlatformCaps_UVDPowerGating);
 149
 150         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
 151                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 152                                 PHM_PlatformCaps_VCEPowerGating);
 153
 154         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 155                         PHM_PlatformCaps_UnTabledHardwareInterface);
 156
 157         if (data->registry_data.od8_feature_enable)
 158                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 159                                 PHM_PlatformCaps_OD8inACSupport);
 160
 161         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 162                         PHM_PlatformCaps_ActivityReporting);
 163         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 164                         PHM_PlatformCaps_FanSpeedInTableIsRPM);
 165
 166         if (data->registry_data.od_state_in_dc_support) {
 167                 if (data->registry_data.od8_feature_enable)
 168                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 169                                         PHM_PlatformCaps_OD8inDCSupport);
 170         }
 171
 172         if (data->registry_data.thermal_support &&
 173             data->registry_data.fuzzy_fan_control_support &&
 174             hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
 175                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 176                                 PHM_PlatformCaps_ODFuzzyFanControlSupport);
 177
 178         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 179                         PHM_PlatformCaps_DynamicPowerManagement);
 180         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 181                         PHM_PlatformCaps_SMC);
 182         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 183                         PHM_PlatformCaps_ThermalPolicyDelay);
 184
 185         if (data->registry_data.force_dpm_high)
 186                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 187                                 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
 188
 189         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 190                         PHM_PlatformCaps_DynamicUVDState);
 191
 192         if (data->registry_data.sclk_throttle_low_notification)
 193                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 194                                 PHM_PlatformCaps_SclkThrottleLowNotification);
 195
 196         /* power tune caps */
 197         /* assume disabled */
 198         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 199                         PHM_PlatformCaps_PowerContainment);
 200         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 201                         PHM_PlatformCaps_DiDtSupport);
 202         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 203                         PHM_PlatformCaps_SQRamping);
 204         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 205                         PHM_PlatformCaps_DBRamping);
 206         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 207                         PHM_PlatformCaps_TDRamping);
 208         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 209                         PHM_PlatformCaps_TCPRamping);
 210         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 211                         PHM_PlatformCaps_DBRRamping);
 212         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 213                         PHM_PlatformCaps_DiDtEDCEnable);
 214         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 215                         PHM_PlatformCaps_GCEDC);
 216         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 217                         PHM_PlatformCaps_PSM);
 218
 219         if (data->registry_data.didt_support) {
 220                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 221                                 PHM_PlatformCaps_DiDtSupport);
 222                 if (data->registry_data.sq_ramping_support)
 223                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 224                                         PHM_PlatformCaps_SQRamping);
 225                 if (data->registry_data.db_ramping_support)
 226                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 227                                         PHM_PlatformCaps_DBRamping);
 228                 if (data->registry_data.td_ramping_support)
 229                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 230                                         PHM_PlatformCaps_TDRamping);
 231                 if (data->registry_data.tcp_ramping_support)
 232                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 233                                         PHM_PlatformCaps_TCPRamping);
 234                 if (data->registry_data.dbr_ramping_support)
 235                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 236                                         PHM_PlatformCaps_DBRRamping);
 237                 if (data->registry_data.edc_didt_support)
 238                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 239                                         PHM_PlatformCaps_DiDtEDCEnable);
 240                 if (data->registry_data.gc_didt_support)
 241                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 242                                         PHM_PlatformCaps_GCEDC);
 243                 if (data->registry_data.psm_didt_support)
 244                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 245                                         PHM_PlatformCaps_PSM);
 246         }
 247
 248         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 249                         PHM_PlatformCaps_RegulatorHot);
 250
 251         if (data->registry_data.ac_dc_switch_gpio_support) {
 252                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 253                                 PHM_PlatformCaps_AutomaticDCTransition);
 254                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 255                                 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
 256         }
 257
 258         if (data->registry_data.quick_transition_support) {
 259                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 260                                 PHM_PlatformCaps_AutomaticDCTransition);
 261                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 262                                 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
 263                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 264                                 PHM_PlatformCaps_Falcon_QuickTransition);
 265         }
 266
 267         if (data->lowest_uclk_reserved_for_ulv != PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT) {
 268                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 269                                 PHM_PlatformCaps_LowestUclkReservedForUlv);
 270                 if (data->lowest_uclk_reserved_for_ulv == 1)
 271                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 272                                         PHM_PlatformCaps_LowestUclkReservedForUlv);
 273         }
 274
 275         if (data->registry_data.custom_fan_support)
 276                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 277                                 PHM_PlatformCaps_CustomFanControlSupport);
 278
 279         return 0;
 280 }
 281
 282 static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 283 {
 284         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 285         int i;
 286
 287         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
 288                         FEATURE_DPM_PREFETCHER_BIT;
 289         data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
 290                         FEATURE_DPM_GFXCLK_BIT;
 291         data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
 292                         FEATURE_DPM_UCLK_BIT;
 293         data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
 294                         FEATURE_DPM_SOCCLK_BIT;
 295         data->smu_features[GNLD_DPM_UVD].smu_feature_id =
 296                         FEATURE_DPM_UVD_BIT;
 297         data->smu_features[GNLD_DPM_VCE].smu_feature_id =
 298                         FEATURE_DPM_VCE_BIT;
 299         data->smu_features[GNLD_ULV].smu_feature_id =
 300                         FEATURE_ULV_BIT;
 301         data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
 302                         FEATURE_DPM_MP0CLK_BIT;
 303         data->smu_features[GNLD_DPM_LINK].smu_feature_id =
 304                         FEATURE_DPM_LINK_BIT;
 305         data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
 306                         FEATURE_DPM_DCEFCLK_BIT;
 307         data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
 308                         FEATURE_DS_GFXCLK_BIT;
 309         data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
 310                         FEATURE_DS_SOCCLK_BIT;
 311         data->smu_features[GNLD_DS_LCLK].smu_feature_id =
 312                         FEATURE_DS_LCLK_BIT;
 313         data->smu_features[GNLD_PPT].smu_feature_id =
 314                         FEATURE_PPT_BIT;
 315         data->smu_features[GNLD_TDC].smu_feature_id =
 316                         FEATURE_TDC_BIT;
 317         data->smu_features[GNLD_THERMAL].smu_feature_id =
 318                         FEATURE_THERMAL_BIT;
 319         data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
 320                         FEATURE_GFX_PER_CU_CG_BIT;
 321         data->smu_features[GNLD_RM].smu_feature_id =
 322                         FEATURE_RM_BIT;
 323         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
 324                         FEATURE_DS_DCEFCLK_BIT;
 325         data->smu_features[GNLD_ACDC].smu_feature_id =
 326                         FEATURE_ACDC_BIT;
 327         data->smu_features[GNLD_VR0HOT].smu_feature_id =
 328                         FEATURE_VR0HOT_BIT;
 329         data->smu_features[GNLD_VR1HOT].smu_feature_id =
 330                         FEATURE_VR1HOT_BIT;
 331         data->smu_features[GNLD_FW_CTF].smu_feature_id =
 332                         FEATURE_FW_CTF_BIT;
 333         data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
 334                         FEATURE_LED_DISPLAY_BIT;
 335         data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
 336                         FEATURE_FAN_CONTROL_BIT;
 337         data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
 338         data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
 339         data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
 340         data->smu_features[GNLD_DPM_FCLK].smu_feature_id = FEATURE_DPM_FCLK_BIT;
 341         data->smu_features[GNLD_DS_FCLK].smu_feature_id = FEATURE_DS_FCLK_BIT;
 342         data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;
 343         data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;
 344         data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
 345
 346         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 347                 data->smu_features[i].smu_feature_bitmap =
 348                         (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
 349                 data->smu_features[i].allowed =
 350                         ((data->registry_data.disallowed_features >> i) & 1) ?
 351                         false : true;
 352         }
 353 }
 354
 355 static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 356 {
 357         return 0;
 358 }
 359
 360 static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 361 {
 362         kfree(hwmgr->backend);
 363         hwmgr->backend = NULL;
 364
 365         return 0;
 366 }
 367
 368 static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 369 {
 370         struct vega20_hwmgr *data;
 371         struct amdgpu_device *adev = hwmgr->adev;
 372
 373         data = kzalloc(sizeof(struct vega20_hwmgr), GFP_KERNEL);
 374         if (data == NULL)
 375                 return -ENOMEM;
 376
 377         hwmgr->backend = data;
 378
 379         hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO];
 380         hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
 381         hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
 382
 383         vega20_set_default_registry_data(hwmgr);
 384
 385         data->disable_dpm_mask = 0xff;
 386
 387         /* need to set voltage control types before EVV patching */
 388         data->vddc_control = VEGA20_VOLTAGE_CONTROL_NONE;
 389         data->mvdd_control = VEGA20_VOLTAGE_CONTROL_NONE;
 390         data->vddci_control = VEGA20_VOLTAGE_CONTROL_NONE;
 391
 392         data->water_marks_bitmap = 0;
 393         data->avfs_exist = false;
 394
 395         vega20_set_features_platform_caps(hwmgr);
 396
 397         vega20_init_dpm_defaults(hwmgr);
 398
 399         /* Parse pptable data read from VBIOS */
 400         vega20_set_private_data_based_on_pptable(hwmgr);
 401
 402         data->is_tlu_enabled = false;
 403
 404         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 405                         VEGA20_MAX_HARDWARE_POWERLEVELS;
 406         hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
 407         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 408
 409         hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
 410         /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
 411         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 412         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 413
 414         data->total_active_cus = adev->gfx.cu_info.number;
 415
 416         return 0;
 417 }
 418
 419 static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 420 {
 421         struct vega20_hwmgr *data =
 422                         (struct vega20_hwmgr *)(hwmgr->backend);
 423
 424         data->low_sclk_interrupt_threshold = 0;
 425
 426         return 0;
 427 }
 428
 429 static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
 430 {
 431         int ret = 0;
 432
 433         ret = vega20_init_sclk_threshold(hwmgr);
 434         PP_ASSERT_WITH_CODE(!ret,
 435                         "Failed to init sclk threshold!",
 436                         return ret);
 437
 438         return 0;
 439 }
 440
 441 /*
 442  * @fn vega20_init_dpm_state
 443  * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
 444  *
 445  * @param    dpm_state - the address of the DPM Table to initiailize.
 446  * @return   None.
 447  */
 448 static void vega20_init_dpm_state(struct vega20_dpm_state *dpm_state)
 449 {
 450         dpm_state->soft_min_level = 0x0;
 451         dpm_state->soft_max_level = 0xffff;
 452         dpm_state->hard_min_level = 0x0;
 453         dpm_state->hard_max_level = 0xffff;
 454 }
 455
 456 static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
 457                 PPCLK_e clk_id, uint32_t *num_of_levels)
 458 {
 459         int ret = 0;
 460
 461         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 462                         PPSMC_MSG_GetDpmFreqByIndex,
 463                         (clk_id << 16 | 0xFF));
 464         PP_ASSERT_WITH_CODE(!ret,
 465                         "[GetNumOfDpmLevel] failed to get dpm levels!",
 466                         return ret);
 467
 468         *num_of_levels = smum_get_argument(hwmgr);
 469         PP_ASSERT_WITH_CODE(*num_of_levels > 0,
 470                         "[GetNumOfDpmLevel] number of clk levels is invalid!",
 471                         return -EINVAL);
 472
 473         return ret;
 474 }
 475
 476 static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
 477                 PPCLK_e clk_id, uint32_t index, uint32_t *clk)
 478 {
 479         int ret = 0;
 480
 481         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 482                         PPSMC_MSG_GetDpmFreqByIndex,
 483                         (clk_id << 16 | index));
 484         PP_ASSERT_WITH_CODE(!ret,
 485                         "[GetDpmFreqByIndex] failed to get dpm freq by index!",
 486                         return ret);
 487
 488         *clk = smum_get_argument(hwmgr);
 489         PP_ASSERT_WITH_CODE(*clk,
 490                         "[GetDpmFreqByIndex] clk value is invalid!",
 491                         return -EINVAL);
 492
 493         return ret;
 494 }
 495
 496 static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
 497                 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id)
 498 {
 499         int ret = 0;
 500         uint32_t i, num_of_levels, clk;
 501
 502         ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
 503         PP_ASSERT_WITH_CODE(!ret,
 504                         "[SetupSingleDpmTable] failed to get clk levels!",
 505                         return ret);
 506
 507         dpm_table->count = num_of_levels;
 508
 509         for (i = 0; i < num_of_levels; i++) {
 510                 ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
 511                 PP_ASSERT_WITH_CODE(!ret,
 512                         "[SetupSingleDpmTable] failed to get clk of specific level!",
 513                         return ret);
 514                 dpm_table->dpm_levels[i].value = clk;
 515                 dpm_table->dpm_levels[i].enabled = true;
 516         }
 517
 518         return ret;
 519 }
 520
 521 static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr)
 522 {
 523         struct vega20_hwmgr *data =
 524                         (struct vega20_hwmgr *)(hwmgr->backend);
 525         struct vega20_single_dpm_table *dpm_table;
 526         int ret = 0;
 527
 528         dpm_table = &(data->dpm_table.gfx_table);
 529         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
 530                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
 531                 PP_ASSERT_WITH_CODE(!ret,
 532                                 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
 533                                 return ret);
 534         } else {
 535                 dpm_table->count = 1;
 536                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
 537         }
 538
 539         return ret;
 540 }
 541
 542 static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr)
 543 {
 544         struct vega20_hwmgr *data =
 545                         (struct vega20_hwmgr *)(hwmgr->backend);
 546         struct vega20_single_dpm_table *dpm_table;
 547         int ret = 0;
 548
 549         dpm_table = &(data->dpm_table.mem_table);
 550         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
 551                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
 552                 PP_ASSERT_WITH_CODE(!ret,
 553                                 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
 554                                 return ret);
 555         } else {
 556                 dpm_table->count = 1;
 557                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
 558         }
 559
 560         return ret;
 561 }
 562
 563 /*
 564  * This function is to initialize all DPM state tables
 565  * for SMU based on the dependency table.
 566  * Dynamic state patching function will then trim these
 567  * state tables to the allowed range based
 568  * on the power policy or external client requests,
 569  * such as UVD request, etc.
 570  */
 571 static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 572 {
 573         struct vega20_hwmgr *data =
 574                         (struct vega20_hwmgr *)(hwmgr->backend);
 575         struct vega20_single_dpm_table *dpm_table;
 576         int ret = 0;
 577
 578         memset(&data->dpm_table, 0, sizeof(data->dpm_table));
 579
 580         /* socclk */
 581         dpm_table = &(data->dpm_table.soc_table);
 582         if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
 583                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
 584                 PP_ASSERT_WITH_CODE(!ret,
 585                                 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
 586                                 return ret);
 587         } else {
 588                 dpm_table->count = 1;
 589                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
 590         }
 591         vega20_init_dpm_state(&(dpm_table->dpm_state));
 592
 593         /* gfxclk */
 594         dpm_table = &(data->dpm_table.gfx_table);
 595         ret = vega20_setup_gfxclk_dpm_table(hwmgr);
 596         if (ret)
 597                 return ret;
 598         vega20_init_dpm_state(&(dpm_table->dpm_state));
 599
 600         /* memclk */
 601         dpm_table = &(data->dpm_table.mem_table);
 602         ret = vega20_setup_memclk_dpm_table(hwmgr);
 603         if (ret)
 604                 return ret;
 605         vega20_init_dpm_state(&(dpm_table->dpm_state));
 606
 607         /* eclk */
 608         dpm_table = &(data->dpm_table.eclk_table);
 609         if (data->smu_features[GNLD_DPM_VCE].enabled) {
 610                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
 611                 PP_ASSERT_WITH_CODE(!ret,
 612                                 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
 613                                 return ret);
 614         } else {
 615                 dpm_table->count = 1;
 616                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
 617         }
 618         vega20_init_dpm_state(&(dpm_table->dpm_state));
 619
 620         /* vclk */
 621         dpm_table = &(data->dpm_table.vclk_table);
 622         if (data->smu_features[GNLD_DPM_UVD].enabled) {
 623                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
 624                 PP_ASSERT_WITH_CODE(!ret,
 625                                 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
 626                                 return ret);
 627         } else {
 628                 dpm_table->count = 1;
 629                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
 630         }
 631         vega20_init_dpm_state(&(dpm_table->dpm_state));
 632
 633         /* dclk */
 634         dpm_table = &(data->dpm_table.dclk_table);
 635         if (data->smu_features[GNLD_DPM_UVD].enabled) {
 636                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
 637                 PP_ASSERT_WITH_CODE(!ret,
 638                                 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
 639                                 return ret);
 640         } else {
 641                 dpm_table->count = 1;
 642                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
 643         }
 644         vega20_init_dpm_state(&(dpm_table->dpm_state));
 645
 646         /* dcefclk */
 647         dpm_table = &(data->dpm_table.dcef_table);
 648         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 649                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
 650                 PP_ASSERT_WITH_CODE(!ret,
 651                                 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
 652                                 return ret);
 653         } else {
 654                 dpm_table->count = 1;
 655                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
 656         }
 657         vega20_init_dpm_state(&(dpm_table->dpm_state));
 658
 659         /* pixclk */
 660         dpm_table = &(data->dpm_table.pixel_table);
 661         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 662                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
 663                 PP_ASSERT_WITH_CODE(!ret,
 664                                 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
 665                                 return ret);
 666         } else
 667                 dpm_table->count = 0;
 668         vega20_init_dpm_state(&(dpm_table->dpm_state));
 669
 670         /* dispclk */
 671         dpm_table = &(data->dpm_table.display_table);
 672         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 673                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
 674                 PP_ASSERT_WITH_CODE(!ret,
 675                                 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
 676                                 return ret);
 677         } else
 678                 dpm_table->count = 0;
 679         vega20_init_dpm_state(&(dpm_table->dpm_state));
 680
 681         /* phyclk */
 682         dpm_table = &(data->dpm_table.phy_table);
 683         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 684                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
 685                 PP_ASSERT_WITH_CODE(!ret,
 686                                 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
 687                                 return ret);
 688         } else
 689                 dpm_table->count = 0;
 690         vega20_init_dpm_state(&(dpm_table->dpm_state));
 691
 692         /* fclk */
 693         dpm_table = &(data->dpm_table.fclk_table);
 694         if (data->smu_features[GNLD_DPM_FCLK].enabled) {
 695                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK);
 696                 PP_ASSERT_WITH_CODE(!ret,
 697                                 "[SetupDefaultDpmTable] failed to get fclk dpm levels!",
 698                                 return ret);
 699         } else
 700                 dpm_table->count = 0;
 701         vega20_init_dpm_state(&(dpm_table->dpm_state));
 702
 703         /* save a copy of the default DPM table */
 704         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 705                         sizeof(struct vega20_dpm_table));
 706
 707         return 0;
 708 }
 709
 710 /**
 711 * Initializes the SMC table and uploads it
 712 *
 713 * @param    hwmgr  the address of the powerplay hardware manager.
 714 * @param    pInput  the pointer to input data (PowerState)
 715 * @return   always 0
 716 */
 717 static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
 718 {
 719         int result;
 720         struct vega20_hwmgr *data =
 721                         (struct vega20_hwmgr *)(hwmgr->backend);
 722         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 723         struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
 724         struct phm_ppt_v3_information *pptable_information =
 725                 (struct phm_ppt_v3_information *)hwmgr->pptable;
 726
 727         result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
 728         PP_ASSERT_WITH_CODE(!result,
 729                         "[InitSMCTable] Failed to get vbios bootup values!",
 730                         return result);
 731
 732         data->vbios_boot_state.vddc     = boot_up_values.usVddc;
 733         data->vbios_boot_state.vddci    = boot_up_values.usVddci;
 734         data->vbios_boot_state.mvddc    = boot_up_values.usMvddc;
 735         data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
 736         data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
 737         data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
 738         data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
 739         data->vbios_boot_state.eclock = boot_up_values.ulEClk;
 740         data->vbios_boot_state.vclock = boot_up_values.ulVClk;
 741         data->vbios_boot_state.dclock = boot_up_values.ulDClk;
 742         data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
 743
 744         smum_send_msg_to_smc_with_parameter(hwmgr,
 745                         PPSMC_MSG_SetMinDeepSleepDcefclk,
 746                 (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
 747
 748         memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
 749
 750         result = smum_smc_table_manager(hwmgr,
 751                                         (uint8_t *)pp_table, TABLE_PPTABLE, false);
 752         PP_ASSERT_WITH_CODE(!result,
 753                         "[InitSMCTable] Failed to upload PPtable!",
 754                         return result);
 755
 756         return 0;
 757 }
 758
 759 static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
 760 {
 761         struct vega20_hwmgr *data =
 762                         (struct vega20_hwmgr *)(hwmgr->backend);
 763         uint32_t allowed_features_low = 0, allowed_features_high = 0;
 764         int i;
 765         int ret = 0;
 766
 767         for (i = 0; i < GNLD_FEATURES_MAX; i++)
 768                 if (data->smu_features[i].allowed)
 769                         data->smu_features[i].smu_feature_id > 31 ?
 770                                 (allowed_features_high |=
 771                                  ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT)
 772                                   & 0xFFFFFFFF)) :
 773                                 (allowed_features_low |=
 774                                  ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT)
 775                                   & 0xFFFFFFFF));
 776
 777         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 778                 PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high);
 779         PP_ASSERT_WITH_CODE(!ret,
 780                 "[SetAllowedFeaturesMask] Attempt to set allowed features mask(high) failed!",
 781                 return ret);
 782
 783         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 784                 PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low);
 785         PP_ASSERT_WITH_CODE(!ret,
 786                 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
 787                 return ret);
 788
 789         return 0;
 790 }
 791
 792 static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr)
 793 {
 794         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc);
 795 }
 796
 797 static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
 798 {
 799         struct vega20_hwmgr *data =
 800                         (struct vega20_hwmgr *)(hwmgr->backend);
 801         uint64_t features_enabled;
 802         int i;
 803         bool enabled;
 804         int ret = 0;
 805
 806         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
 807                         PPSMC_MSG_EnableAllSmuFeatures)) == 0,
 808                         "[EnableAllSMUFeatures] Failed to enable all smu features!",
 809                         return ret);
 810
 811         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
 812         PP_ASSERT_WITH_CODE(!ret,
 813                         "[EnableAllSmuFeatures] Failed to get enabled smc features!",
 814                         return ret);
 815
 816         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 817                 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
 818                         true : false;
 819                 data->smu_features[i].enabled = enabled;
 820                 data->smu_features[i].supported = enabled;
 821
 822 #if 0
 823                 if (data->smu_features[i].allowed && !enabled)
 824                         pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i);
 825                 else if (!data->smu_features[i].allowed && enabled)
 826                         pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i);
 827 #endif
 828         }
 829
 830         return 0;
 831 }
 832
 833 static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
 834 {
 835         struct vega20_hwmgr *data =
 836                         (struct vega20_hwmgr *)(hwmgr->backend);
 837
 838         return smum_send_msg_to_smc_with_parameter(hwmgr,
 839                         PPSMC_MSG_SetFclkGfxClkRatio,
 840                         data->registry_data.fclk_gfxclk_ratio);
 841 }
 842
 843 static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
 844 {
 845         struct vega20_hwmgr *data =
 846                         (struct vega20_hwmgr *)(hwmgr->backend);
 847         uint64_t features_enabled;
 848         int i;
 849         bool enabled;
 850         int ret = 0;
 851
 852         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
 853                         PPSMC_MSG_DisableAllSmuFeatures)) == 0,
 854                         "[DisableAllSMUFeatures] Failed to disable all smu features!",
 855                         return ret);
 856
 857         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
 858         PP_ASSERT_WITH_CODE(!ret,
 859                         "[DisableAllSMUFeatures] Failed to get enabled smc features!",
 860                         return ret);
 861
 862         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 863                 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
 864                         true : false;
 865                 data->smu_features[i].enabled = enabled;
 866                 data->smu_features[i].supported = enabled;
 867         }
 868
 869         return 0;
 870 }
 871
 872 static int vega20_od8_set_feature_capabilities(
 873                 struct pp_hwmgr *hwmgr)
 874 {
 875         struct phm_ppt_v3_information *pptable_information =
 876                 (struct phm_ppt_v3_information *)hwmgr->pptable;
 877         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 878         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 879         struct vega20_od8_settings *od_settings = &(data->od8_settings);
 880
 881         od_settings->overdrive8_capabilities = 0;
 882
 883         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
 884                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
 885                     pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
 886                     pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
 887                     (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
 888                     pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN]))
 889                         od_settings->overdrive8_capabilities |= OD8_GFXCLK_LIMITS;
 890
 891                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
 892                     (pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
 893                      pp_table->MinVoltageGfx / VOLTAGE_SCALE) &&
 894                     (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
 895                      pp_table->MaxVoltageGfx / VOLTAGE_SCALE) &&
 896                     (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] >=
 897                      pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1]))
 898                         od_settings->overdrive8_capabilities |= OD8_GFXCLK_CURVE;
 899         }
 900
 901         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
 902                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
 903                     pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
 904                     pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
 905                     (pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
 906                     pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX]))
 907                         od_settings->overdrive8_capabilities |= OD8_UCLK_MAX;
 908         }
 909
 910         if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
 911             pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
 912             pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
 913             pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
 914             pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100)
 915                 od_settings->overdrive8_capabilities |= OD8_POWER_LIMIT;
 916
 917         if (data->smu_features[GNLD_FAN_CONTROL].enabled) {
 918                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
 919                     pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
 920                     pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
 921                     (pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
 922                      pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT]))
 923                         od_settings->overdrive8_capabilities |= OD8_ACOUSTIC_LIMIT_SCLK;
 924
 925                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
 926                     (pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] >=
 927                     (pp_table->FanPwmMin * pp_table->FanMaximumRpm / 100)) &&
 928                     pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
 929                     (pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
 930                      pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED]))
 931                         od_settings->overdrive8_capabilities |= OD8_FAN_SPEED_MIN;
 932         }
 933
 934         if (data->smu_features[GNLD_THERMAL].enabled) {
 935                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
 936                     pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
 937                     pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
 938                     (pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
 939                      pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP]))
 940                         od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_FAN;
 941
 942                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
 943                     pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
 944                     pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
 945                     (pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
 946                      pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX]))
 947                         od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_SYSTEM;
 948         }
 949
 950         if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE])
 951                 od_settings->overdrive8_capabilities |= OD8_MEMORY_TIMING_TUNE;
 952
 953         if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL] &&
 954             pp_table->FanZeroRpmEnable)
 955                 od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL;
 956
 957         return 0;
 958 }
 959
 960 static int vega20_od8_set_feature_id(
 961                 struct pp_hwmgr *hwmgr)
 962 {
 963         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 964         struct vega20_od8_settings *od_settings = &(data->od8_settings);
 965
 966         if (od_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
 967                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
 968                         OD8_GFXCLK_LIMITS;
 969                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
 970                         OD8_GFXCLK_LIMITS;
 971         } else {
 972                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
 973                         0;
 974                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
 975                         0;
 976         }
 977
 978         if (od_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
 979                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
 980                         OD8_GFXCLK_CURVE;
 981                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
 982                         OD8_GFXCLK_CURVE;
 983                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
 984                         OD8_GFXCLK_CURVE;
 985                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
 986                         OD8_GFXCLK_CURVE;
 987                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
 988                         OD8_GFXCLK_CURVE;
 989                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
 990                         OD8_GFXCLK_CURVE;
 991         } else {
 992                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
 993                         0;
 994                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
 995                         0;
 996                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
 997                         0;
 998                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
 999                         0;
1000                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1001                         0;
1002                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1003                         0;
1004         }
1005
1006         if (od_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1007                 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = OD8_UCLK_MAX;
1008         else
1009                 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = 0;
1010
1011         if (od_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1012                 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = OD8_POWER_LIMIT;
1013         else
1014                 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = 0;
1015
1016         if (od_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1017                 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1018                         OD8_ACOUSTIC_LIMIT_SCLK;
1019         else
1020                 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1021                         0;
1022
1023         if (od_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1024                 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1025                         OD8_FAN_SPEED_MIN;
1026         else
1027                 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1028                         0;
1029
1030         if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1031                 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1032                         OD8_TEMPERATURE_FAN;
1033         else
1034                 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1035                         0;
1036
1037         if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1038                 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1039                         OD8_TEMPERATURE_SYSTEM;
1040         else
1041                 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1042                         0;
1043
1044         return 0;
1045 }
1046
1047 static int vega20_od8_get_gfx_clock_base_voltage(
1048                 struct pp_hwmgr *hwmgr,
1049                 uint32_t *voltage,
1050                 uint32_t freq)
1051 {
1052         int ret = 0;
1053
1054         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1055                         PPSMC_MSG_GetAVFSVoltageByDpm,
1056                         ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1057         PP_ASSERT_WITH_CODE(!ret,
1058                         "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!",
1059                         return ret);
1060
1061         *voltage = smum_get_argument(hwmgr);
1062         *voltage = *voltage / VOLTAGE_SCALE;
1063
1064         return 0;
1065 }
1066
1067 static int vega20_od8_initialize_default_settings(
1068                 struct pp_hwmgr *hwmgr)
1069 {
1070         struct phm_ppt_v3_information *pptable_information =
1071                 (struct phm_ppt_v3_information *)hwmgr->pptable;
1072         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1073         struct vega20_od8_settings *od8_settings = &(data->od8_settings);
1074         OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table);
1075         int i, ret = 0;
1076
1077         /* Set Feature Capabilities */
1078         vega20_od8_set_feature_capabilities(hwmgr);
1079
1080         /* Map FeatureID to individual settings */
1081         vega20_od8_set_feature_id(hwmgr);
1082
1083         /* Set default values */
1084         ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);
1085         PP_ASSERT_WITH_CODE(!ret,
1086                         "Failed to export over drive table!",
1087                         return ret);
1088
1089         if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1090                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1091                         od_table->GfxclkFmin;
1092                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1093                         od_table->GfxclkFmax;
1094         } else {
1095                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1096                         0;
1097                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1098                         0;
1099         }
1100
1101         if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1102                 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1103                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1104                         od_table->GfxclkFreq1;
1105
1106                 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1107                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1108                         od_table->GfxclkFreq3;
1109
1110                 od_table->GfxclkFreq2 = (od_table->GfxclkFreq1 + od_table->GfxclkFreq3) / 2;
1111                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1112                         od_table->GfxclkFreq2;
1113
1114                 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1115                                    &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value),
1116                                      od_table->GfxclkFreq1),
1117                                 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1118                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0);
1119                 od_table->GfxclkVolt1 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1120                         * VOLTAGE_SCALE;
1121
1122                 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1123                                    &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value),
1124                                      od_table->GfxclkFreq2),
1125                                 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1126                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0);
1127                 od_table->GfxclkVolt2 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1128                         * VOLTAGE_SCALE;
1129
1130                 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1131                                    &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value),
1132                                      od_table->GfxclkFreq3),
1133                                 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1134                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0);
1135                 od_table->GfxclkVolt3 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1136                         * VOLTAGE_SCALE;
1137         } else {
1138                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1139                         0;
1140                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value =
1141                         0;
1142                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1143                         0;
1144                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value =
1145                         0;
1146                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1147                         0;
1148                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value =
1149                         0;
1150         }
1151
1152         if (od8_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1153                 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1154                         od_table->UclkFmax;
1155         else
1156                 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1157                         0;
1158
1159         if (od8_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1160                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1161                         od_table->OverDrivePct;
1162         else
1163                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1164                         0;
1165
1166         if (od8_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1167                 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1168                         od_table->FanMaximumRpm;
1169         else
1170                 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1171                         0;
1172
1173         if (od8_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1174                 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1175                         od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100;
1176         else
1177                 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1178                         0;
1179
1180         if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1181                 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1182                         od_table->FanTargetTemperature;
1183         else
1184                 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1185                         0;
1186
1187         if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1188                 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1189                         od_table->MaxOpTemp;
1190         else
1191                 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1192                         0;
1193
1194         for (i = 0; i < OD8_SETTING_COUNT; i++) {
1195                 if (od8_settings->od8_settings_array[i].feature_id) {
1196                         od8_settings->od8_settings_array[i].min_value =
1197                                 pptable_information->od_settings_min[i];
1198                         od8_settings->od8_settings_array[i].max_value =
1199                                 pptable_information->od_settings_max[i];
1200                         od8_settings->od8_settings_array[i].current_value =
1201                                 od8_settings->od8_settings_array[i].default_value;
1202                 } else {
1203                         od8_settings->od8_settings_array[i].min_value =
1204                                 0;
1205                         od8_settings->od8_settings_array[i].max_value =
1206                                 0;
1207                         od8_settings->od8_settings_array[i].current_value =
1208                                 0;
1209                 }
1210         }
1211
1212         ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
1213         PP_ASSERT_WITH_CODE(!ret,
1214                         "Failed to import over drive table!",
1215                         return ret);
1216
1217         return 0;
1218 }
1219
1220 static int vega20_od8_set_settings(
1221                 struct pp_hwmgr *hwmgr,
1222                 uint32_t index,
1223                 uint32_t value)
1224 {
1225         OverDriveTable_t od_table;
1226         int ret = 0;
1227         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1228         struct vega20_od8_single_setting *od8_settings =
1229                         data->od8_settings.od8_settings_array;
1230
1231         ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);
1232         PP_ASSERT_WITH_CODE(!ret,
1233                         "Failed to export over drive table!",
1234                         return ret);
1235
1236         switch(index) {
1237         case OD8_SETTING_GFXCLK_FMIN:
1238                 od_table.GfxclkFmin = (uint16_t)value;
1239                 break;
1240         case OD8_SETTING_GFXCLK_FMAX:
1241                 if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value ||
1242                     value > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value)
1243                         return -EINVAL;
1244
1245                 od_table.GfxclkFmax = (uint16_t)value;
1246                 break;
1247         case OD8_SETTING_GFXCLK_FREQ1:
1248                 od_table.GfxclkFreq1 = (uint16_t)value;
1249                 break;
1250         case OD8_SETTING_GFXCLK_VOLTAGE1:
1251                 od_table.GfxclkVolt1 = (uint16_t)value;
1252                 break;
1253         case OD8_SETTING_GFXCLK_FREQ2:
1254                 od_table.GfxclkFreq2 = (uint16_t)value;
1255                 break;
1256         case OD8_SETTING_GFXCLK_VOLTAGE2:
1257                 od_table.GfxclkVolt2 = (uint16_t)value;
1258                 break;
1259         case OD8_SETTING_GFXCLK_FREQ3:
1260                 od_table.GfxclkFreq3 = (uint16_t)value;
1261                 break;
1262         case OD8_SETTING_GFXCLK_VOLTAGE3:
1263                 od_table.GfxclkVolt3 = (uint16_t)value;
1264                 break;
1265         case OD8_SETTING_UCLK_FMAX:
1266                 if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
1267                     value > od8_settings[OD8_SETTING_UCLK_FMAX].max_value)
1268                         return -EINVAL;
1269                 od_table.UclkFmax = (uint16_t)value;
1270                 break;
1271         case OD8_SETTING_POWER_PERCENTAGE:
1272                 od_table.OverDrivePct = (int16_t)value;
1273                 break;
1274         case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
1275                 od_table.FanMaximumRpm = (uint16_t)value;
1276                 break;
1277         case OD8_SETTING_FAN_MIN_SPEED:
1278                 od_table.FanMinimumPwm = (uint16_t)value;
1279                 break;
1280         case OD8_SETTING_FAN_TARGET_TEMP:
1281                 od_table.FanTargetTemperature = (uint16_t)value;
1282                 break;
1283         case OD8_SETTING_OPERATING_TEMP_MAX:
1284                 od_table.MaxOpTemp = (uint16_t)value;
1285                 break;
1286         }
1287
1288         ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);
1289         PP_ASSERT_WITH_CODE(!ret,
1290                         "Failed to import over drive table!",
1291                         return ret);
1292
1293         return 0;
1294 }
1295
1296 static int vega20_get_sclk_od(
1297                 struct pp_hwmgr *hwmgr)
1298 {
1299         struct vega20_hwmgr *data = hwmgr->backend;
1300         struct vega20_single_dpm_table *sclk_table =
1301                         &(data->dpm_table.gfx_table);
1302         struct vega20_single_dpm_table *golden_sclk_table =
1303                         &(data->golden_dpm_table.gfx_table);
1304         int value;
1305
1306         /* od percentage */
1307         value = DIV_ROUND_UP((sclk_table->dpm_levels[sclk_table->count - 1].value -
1308                 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) * 100,
1309                 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value);
1310
1311         return value;
1312 }
1313
1314 static int vega20_set_sclk_od(
1315                 struct pp_hwmgr *hwmgr, uint32_t value)
1316 {
1317         struct vega20_hwmgr *data = hwmgr->backend;
1318         struct vega20_single_dpm_table *golden_sclk_table =
1319                         &(data->golden_dpm_table.gfx_table);
1320         uint32_t od_sclk;
1321         int ret = 0;
1322
1323         od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value;
1324         od_sclk /= 100;
1325         od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
1326
1327         ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk);
1328         PP_ASSERT_WITH_CODE(!ret,
1329                         "[SetSclkOD] failed to set od gfxclk!",
1330                         return ret);
1331
1332         /* retrieve updated gfxclk table */
1333         ret = vega20_setup_gfxclk_dpm_table(hwmgr);
1334         PP_ASSERT_WITH_CODE(!ret,
1335                         "[SetSclkOD] failed to refresh gfxclk table!",
1336                         return ret);
1337
1338         return 0;
1339 }
1340
1341 static int vega20_get_mclk_od(
1342                 struct pp_hwmgr *hwmgr)
1343 {
1344         struct vega20_hwmgr *data = hwmgr->backend;
1345         struct vega20_single_dpm_table *mclk_table =
1346                         &(data->dpm_table.mem_table);
1347         struct vega20_single_dpm_table *golden_mclk_table =
1348                         &(data->golden_dpm_table.mem_table);
1349         int value;
1350
1351         /* od percentage */
1352         value = DIV_ROUND_UP((mclk_table->dpm_levels[mclk_table->count - 1].value -
1353                 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) * 100,
1354                 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value);
1355
1356         return value;
1357 }
1358
1359 static int vega20_set_mclk_od(
1360                 struct pp_hwmgr *hwmgr, uint32_t value)
1361 {
1362         struct vega20_hwmgr *data = hwmgr->backend;
1363         struct vega20_single_dpm_table *golden_mclk_table =
1364                         &(data->golden_dpm_table.mem_table);
1365         uint32_t od_mclk;
1366         int ret = 0;
1367
1368         od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value;
1369         od_mclk /= 100;
1370         od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
1371
1372         ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk);
1373         PP_ASSERT_WITH_CODE(!ret,
1374                         "[SetMclkOD] failed to set od memclk!",
1375                         return ret);
1376
1377         /* retrieve updated memclk table */
1378         ret = vega20_setup_memclk_dpm_table(hwmgr);
1379         PP_ASSERT_WITH_CODE(!ret,
1380                         "[SetMclkOD] failed to refresh memclk table!",
1381                         return ret);
1382
1383         return 0;
1384 }
1385
1386 static int vega20_populate_umdpstate_clocks(
1387                 struct pp_hwmgr *hwmgr)
1388 {
1389         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1390         struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table);
1391         struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table);
1392
1393         hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
1394         hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
1395
1396         if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1397             mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
1398                 hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
1399                 hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
1400         }
1401
1402         hwmgr->pstate_sclk = hwmgr->pstate_sclk * 100;
1403         hwmgr->pstate_mclk = hwmgr->pstate_mclk * 100;
1404
1405         return 0;
1406 }
1407
1408 static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr,
1409                 PP_Clock *clock, PPCLK_e clock_select)
1410 {
1411         int ret = 0;
1412
1413         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1414                         PPSMC_MSG_GetDcModeMaxDpmFreq,
1415                         (clock_select << 16))) == 0,
1416                         "[GetMaxSustainableClock] Failed to get max DC clock from SMC!",
1417                         return ret);
1418         *clock = smum_get_argument(hwmgr);
1419
1420         /* if DC limit is zero, return AC limit */
1421         if (*clock == 0) {
1422                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1423                         PPSMC_MSG_GetMaxDpmFreq,
1424                         (clock_select << 16))) == 0,
1425                         "[GetMaxSustainableClock] failed to get max AC clock from SMC!",
1426                         return ret);
1427                 *clock = smum_get_argument(hwmgr);
1428         }
1429
1430         return 0;
1431 }
1432
1433 static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr)
1434 {
1435         struct vega20_hwmgr *data =
1436                 (struct vega20_hwmgr *)(hwmgr->backend);
1437         struct vega20_max_sustainable_clocks *max_sustainable_clocks =
1438                 &(data->max_sustainable_clocks);
1439         int ret = 0;
1440
1441         max_sustainable_clocks->uclock = data->vbios_boot_state.mem_clock / 100;
1442         max_sustainable_clocks->soc_clock = data->vbios_boot_state.soc_clock / 100;
1443         max_sustainable_clocks->dcef_clock = data->vbios_boot_state.dcef_clock / 100;
1444         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
1445         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
1446         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
1447
1448         if (data->smu_features[GNLD_DPM_UCLK].enabled)
1449                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1450                                 &(max_sustainable_clocks->uclock),
1451                                 PPCLK_UCLK)) == 0,
1452                                 "[InitMaxSustainableClocks] failed to get max UCLK from SMC!",
1453                                 return ret);
1454
1455         if (data->smu_features[GNLD_DPM_SOCCLK].enabled)
1456                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1457                                 &(max_sustainable_clocks->soc_clock),
1458                                 PPCLK_SOCCLK)) == 0,
1459                                 "[InitMaxSustainableClocks] failed to get max SOCCLK from SMC!",
1460                                 return ret);
1461
1462         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1463                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1464                                 &(max_sustainable_clocks->dcef_clock),
1465                                 PPCLK_DCEFCLK)) == 0,
1466                                 "[InitMaxSustainableClocks] failed to get max DCEFCLK from SMC!",
1467                                 return ret);
1468                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1469                                 &(max_sustainable_clocks->display_clock),
1470                                 PPCLK_DISPCLK)) == 0,
1471                                 "[InitMaxSustainableClocks] failed to get max DISPCLK from SMC!",
1472                                 return ret);
1473                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1474                                 &(max_sustainable_clocks->phy_clock),
1475                                 PPCLK_PHYCLK)) == 0,
1476                                 "[InitMaxSustainableClocks] failed to get max PHYCLK from SMC!",
1477                                 return ret);
1478                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1479                                 &(max_sustainable_clocks->pixel_clock),
1480                                 PPCLK_PIXCLK)) == 0,
1481                                 "[InitMaxSustainableClocks] failed to get max PIXCLK from SMC!",
1482                                 return ret);
1483         }
1484
1485         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1486                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1487
1488         return 0;
1489 }
1490
1491 static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
1492 {
1493         int result;
1494
1495         result = smum_send_msg_to_smc(hwmgr,
1496                 PPSMC_MSG_SetMGpuFanBoostLimitRpm);
1497         PP_ASSERT_WITH_CODE(!result,
1498                         "[EnableMgpuFan] Failed to enable mgpu fan boost!",
1499                         return result);
1500
1501         return 0;
1502 }
1503
1504 static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
1505 {
1506         struct vega20_hwmgr *data =
1507                 (struct vega20_hwmgr *)(hwmgr->backend);
1508
1509         data->uvd_power_gated = true;
1510         data->vce_power_gated = true;
1511
1512         if (data->smu_features[GNLD_DPM_UVD].enabled)
1513                 data->uvd_power_gated = false;
1514
1515         if (data->smu_features[GNLD_DPM_VCE].enabled)
1516                 data->vce_power_gated = false;
1517 }
1518
1519 static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1520 {
1521         int result = 0;
1522
1523         smum_send_msg_to_smc_with_parameter(hwmgr,
1524                         PPSMC_MSG_NumOfDisplays, 0);
1525
1526         result = vega20_set_allowed_featuresmask(hwmgr);
1527         PP_ASSERT_WITH_CODE(!result,
1528                         "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1529                         return result);
1530
1531         result = vega20_init_smc_table(hwmgr);
1532         PP_ASSERT_WITH_CODE(!result,
1533                         "[EnableDPMTasks] Failed to initialize SMC table!",
1534                         return result);
1535
1536         result = vega20_run_btc_afll(hwmgr);
1537         PP_ASSERT_WITH_CODE(!result,
1538                         "[EnableDPMTasks] Failed to run btc afll!",
1539                         return result);
1540
1541         result = vega20_enable_all_smu_features(hwmgr);
1542         PP_ASSERT_WITH_CODE(!result,
1543                         "[EnableDPMTasks] Failed to enable all smu features!",
1544                         return result);
1545
1546         result = vega20_send_clock_ratio(hwmgr);
1547         PP_ASSERT_WITH_CODE(!result,
1548                         "[EnableDPMTasks] Failed to send clock ratio!",
1549                         return result);
1550
1551         /* Initialize UVD/VCE powergating state */
1552         vega20_init_powergate_state(hwmgr);
1553
1554         result = vega20_setup_default_dpm_tables(hwmgr);
1555         PP_ASSERT_WITH_CODE(!result,
1556                         "[EnableDPMTasks] Failed to setup default DPM tables!",
1557                         return result);
1558
1559         result = vega20_init_max_sustainable_clocks(hwmgr);
1560         PP_ASSERT_WITH_CODE(!result,
1561                         "[EnableDPMTasks] Failed to get maximum sustainable clocks!",
1562                         return result);
1563
1564         result = vega20_power_control_set_level(hwmgr);
1565         PP_ASSERT_WITH_CODE(!result,
1566                         "[EnableDPMTasks] Failed to power control set level!",
1567                         return result);
1568
1569         result = vega20_od8_initialize_default_settings(hwmgr);
1570         PP_ASSERT_WITH_CODE(!result,
1571                         "[EnableDPMTasks] Failed to initialize odn settings!",
1572                         return result);
1573
1574         result = vega20_populate_umdpstate_clocks(hwmgr);
1575         PP_ASSERT_WITH_CODE(!result,
1576                         "[EnableDPMTasks] Failed to populate umdpstate clocks!",
1577                         return result);
1578
1579         result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit,
1580                         POWER_SOURCE_AC << 16);
1581         PP_ASSERT_WITH_CODE(!result,
1582                         "[GetPptLimit] get default PPT limit failed!",
1583                         return result);
1584         hwmgr->power_limit =
1585                 hwmgr->default_power_limit = smum_get_argument(hwmgr);
1586
1587         return 0;
1588 }
1589
1590 static uint32_t vega20_find_lowest_dpm_level(
1591                 struct vega20_single_dpm_table *table)
1592 {
1593         uint32_t i;
1594
1595         for (i = 0; i < table->count; i++) {
1596                 if (table->dpm_levels[i].enabled)
1597                         break;
1598         }
1599         if (i >= table->count) {
1600                 i = 0;
1601                 table->dpm_levels[i].enabled = true;
1602         }
1603
1604         return i;
1605 }
1606
1607 static uint32_t vega20_find_highest_dpm_level(
1608                 struct vega20_single_dpm_table *table)
1609 {
1610         int i = 0;
1611
1612         PP_ASSERT_WITH_CODE(table != NULL,
1613                         "[FindHighestDPMLevel] DPM Table does not exist!",
1614                         return 0);
1615         PP_ASSERT_WITH_CODE(table->count > 0,
1616                         "[FindHighestDPMLevel] DPM Table has no entry!",
1617                         return 0);
1618         PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1619                         "[FindHighestDPMLevel] DPM Table has too many entries!",
1620                         return MAX_REGULAR_DPM_NUMBER - 1);
1621
1622         for (i = table->count - 1; i >= 0; i--) {
1623                 if (table->dpm_levels[i].enabled)
1624                         break;
1625         }
1626         if (i < 0) {
1627                 i = 0;
1628                 table->dpm_levels[i].enabled = true;
1629         }
1630
1631         return i;
1632 }
1633
1634 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
1635 {
1636         struct vega20_hwmgr *data =
1637                         (struct vega20_hwmgr *)(hwmgr->backend);
1638         uint32_t min_freq;
1639         int ret = 0;
1640
1641         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1642                 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1643                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1644                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1645                                         (PPCLK_GFXCLK << 16) | (min_freq & 0xffff))),
1646                                         "Failed to set soft min gfxclk !",
1647                                         return ret);
1648         }
1649
1650         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1651                 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1652                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1653                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1654                                         (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1655                                         "Failed to set soft min memclk !",
1656                                         return ret);
1657
1658                 min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
1659                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1660                                         hwmgr, PPSMC_MSG_SetHardMinByFreq,
1661                                         (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1662                                         "Failed to set hard min memclk !",
1663                                         return ret);
1664         }
1665
1666         if (data->smu_features[GNLD_DPM_UVD].enabled) {
1667                 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1668
1669                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1670                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1671                                         (PPCLK_VCLK << 16) | (min_freq & 0xffff))),
1672                                         "Failed to set soft min vclk!",
1673                                         return ret);
1674
1675                 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1676
1677                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1678                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1679                                         (PPCLK_DCLK << 16) | (min_freq & 0xffff))),
1680                                         "Failed to set soft min dclk!",
1681                                         return ret);
1682         }
1683
1684         if (data->smu_features[GNLD_DPM_VCE].enabled) {
1685                 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1686
1687                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1688                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1689                                         (PPCLK_ECLK << 16) | (min_freq & 0xffff))),
1690                                         "Failed to set soft min eclk!",
1691                                         return ret);
1692         }
1693
1694         if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1695                 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1696
1697                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1698                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1699                                         (PPCLK_SOCCLK << 16) | (min_freq & 0xffff))),
1700                                         "Failed to set soft min socclk!",
1701                                         return ret);
1702         }
1703
1704         return ret;
1705 }
1706
1707 static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
1708 {
1709         struct vega20_hwmgr *data =
1710                         (struct vega20_hwmgr *)(hwmgr->backend);
1711         uint32_t max_freq;
1712         int ret = 0;
1713
1714         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1715                 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1716
1717                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1718                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1719                                         (PPCLK_GFXCLK << 16) | (max_freq & 0xffff))),
1720                                         "Failed to set soft max gfxclk!",
1721                                         return ret);
1722         }
1723
1724         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1725                 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1726
1727                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1728                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1729                                         (PPCLK_UCLK << 16) | (max_freq & 0xffff))),
1730                                         "Failed to set soft max memclk!",
1731                                         return ret);
1732         }
1733
1734         if (data->smu_features[GNLD_DPM_UVD].enabled) {
1735                 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1736
1737                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1738                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1739                                         (PPCLK_VCLK << 16) | (max_freq & 0xffff))),
1740                                         "Failed to set soft max vclk!",
1741                                         return ret);
1742
1743                 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1744                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1745                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1746                                         (PPCLK_DCLK << 16) | (max_freq & 0xffff))),
1747                                         "Failed to set soft max dclk!",
1748                                         return ret);
1749         }
1750
1751         if (data->smu_features[GNLD_DPM_VCE].enabled) {
1752                 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1753
1754                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1755                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1756                                         (PPCLK_ECLK << 16) | (max_freq & 0xffff))),
1757                                         "Failed to set soft max eclk!",
1758                                         return ret);
1759         }
1760
1761         if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1762                 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1763
1764                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1765                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1766                                         (PPCLK_SOCCLK << 16) | (max_freq & 0xffff))),
1767                                         "Failed to set soft max socclk!",
1768                                         return ret);
1769         }
1770
1771         return ret;
1772 }
1773
1774 int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1775 {
1776         struct vega20_hwmgr *data =
1777                         (struct vega20_hwmgr *)(hwmgr->backend);
1778         int ret = 0;
1779
1780         if (data->smu_features[GNLD_DPM_VCE].supported) {
1781                 if (data->smu_features[GNLD_DPM_VCE].enabled == enable) {
1782                         if (enable)
1783                                 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already enabled!\n");
1784                         else
1785                                 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already disabled!\n");
1786                 }
1787
1788                 ret = vega20_enable_smc_features(hwmgr,
1789                                 enable,
1790                                 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap);
1791                 PP_ASSERT_WITH_CODE(!ret,
1792                                 "Attempt to Enable/Disable DPM VCE Failed!",
1793                                 return ret);
1794                 data->smu_features[GNLD_DPM_VCE].enabled = enable;
1795         }
1796
1797         return 0;
1798 }
1799
1800 static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr,
1801                 uint32_t *clock,
1802                 PPCLK_e clock_select,
1803                 bool max)
1804 {
1805         int ret;
1806         *clock = 0;
1807
1808         if (max) {
1809                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1810                                 PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16))) == 0,
1811                                 "[GetClockRanges] Failed to get max clock from SMC!",
1812                                 return ret);
1813                 *clock = smum_get_argument(hwmgr);
1814         } else {
1815                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1816                                 PPSMC_MSG_GetMinDpmFreq,
1817                                 (clock_select << 16))) == 0,
1818                                 "[GetClockRanges] Failed to get min clock from SMC!",
1819                                 return ret);
1820                 *clock = smum_get_argument(hwmgr);
1821         }
1822
1823         return 0;
1824 }
1825
1826 static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1827 {
1828         struct vega20_hwmgr *data =
1829                         (struct vega20_hwmgr *)(hwmgr->backend);
1830         uint32_t gfx_clk;
1831         int ret = 0;
1832
1833         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
1834                         "[GetSclks]: gfxclk dpm not enabled!\n",
1835                         return -EPERM);
1836
1837         if (low) {
1838                 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false);
1839                 PP_ASSERT_WITH_CODE(!ret,
1840                         "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
1841                         return ret);
1842         } else {
1843                 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true);
1844                 PP_ASSERT_WITH_CODE(!ret,
1845                         "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
1846                         return ret);
1847         }
1848
1849         return (gfx_clk * 100);
1850 }
1851
1852 static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1853 {
1854         struct vega20_hwmgr *data =
1855                         (struct vega20_hwmgr *)(hwmgr->backend);
1856         uint32_t mem_clk;
1857         int ret = 0;
1858
1859         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
1860                         "[MemMclks]: memclk dpm not enabled!\n",
1861                         return -EPERM);
1862
1863         if (low) {
1864                 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);
1865                 PP_ASSERT_WITH_CODE(!ret,
1866                         "[GetMclks]: fail to get min PPCLK_UCLK\n",
1867                         return ret);
1868         } else {
1869                 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);
1870                 PP_ASSERT_WITH_CODE(!ret,
1871                         "[GetMclks]: fail to get max PPCLK_UCLK\n",
1872                         return ret);
1873         }
1874
1875         return (mem_clk * 100);
1876 }
1877
1878 static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
1879                 uint32_t *query)
1880 {
1881         int ret = 0;
1882         SmuMetrics_t metrics_table;
1883
1884         ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
1885         PP_ASSERT_WITH_CODE(!ret,
1886                         "Failed to export SMU METRICS table!",
1887                         return ret);
1888
1889         *query = metrics_table.CurrSocketPower << 8;
1890
1891         return ret;
1892 }
1893
1894 static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr,
1895                 PPCLK_e clk_id, uint32_t *clk_freq)
1896 {
1897         int ret = 0;
1898
1899         *clk_freq = 0;
1900
1901         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1902                         PPSMC_MSG_GetDpmClockFreq, (clk_id << 16))) == 0,
1903                         "[GetCurrentClkFreq] Attempt to get Current Frequency Failed!",
1904                         return ret);
1905         *clk_freq = smum_get_argument(hwmgr);
1906
1907         *clk_freq = *clk_freq * 100;
1908
1909         return 0;
1910 }
1911
1912 static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr,
1913                 uint32_t *activity_percent)
1914 {
1915         int ret = 0;
1916         SmuMetrics_t metrics_table;
1917
1918         ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
1919         PP_ASSERT_WITH_CODE(!ret,
1920                         "Failed to export SMU METRICS table!",
1921                         return ret);
1922
1923         *activity_percent = metrics_table.AverageGfxActivity;
1924
1925         return ret;
1926 }
1927
1928 static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1929                               void *value, int *size)
1930 {
1931         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1932         struct amdgpu_device *adev = hwmgr->adev;
1933         uint32_t val_vid;
1934         int ret = 0;
1935
1936         switch (idx) {
1937         case AMDGPU_PP_SENSOR_GFX_SCLK:
1938                 ret = vega20_get_current_clk_freq(hwmgr,
1939                                 PPCLK_GFXCLK,
1940                                 (uint32_t *)value);
1941                 if (!ret)
1942                         *size = 4;
1943                 break;
1944         case AMDGPU_PP_SENSOR_GFX_MCLK:
1945                 ret = vega20_get_current_clk_freq(hwmgr,
1946                                 PPCLK_UCLK,
1947                                 (uint32_t *)value);
1948                 if (!ret)
1949                         *size = 4;
1950                 break;
1951         case AMDGPU_PP_SENSOR_GPU_LOAD:
1952                 ret = vega20_get_current_activity_percent(hwmgr, (uint32_t *)value);
1953                 if (!ret)
1954                         *size = 4;
1955                 break;
1956         case AMDGPU_PP_SENSOR_GPU_TEMP:
1957                 *((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr);
1958                 *size = 4;
1959                 break;
1960         case AMDGPU_PP_SENSOR_UVD_POWER:
1961                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
1962                 *size = 4;
1963                 break;
1964         case AMDGPU_PP_SENSOR_VCE_POWER:
1965                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
1966                 *size = 4;
1967                 break;
1968         case AMDGPU_PP_SENSOR_GPU_POWER:
1969                 *size = 16;
1970                 ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value);
1971                 break;
1972         case AMDGPU_PP_SENSOR_VDDGFX:
1973                 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1974                         SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1975                         SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1976                 *((uint32_t *)value) =
1977                         (uint32_t)convert_to_vddc((uint8_t)val_vid);
1978                 break;
1979         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
1980                 ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value);
1981                 if (!ret)
1982                         *size = 8;
1983                 break;
1984         default:
1985                 ret = -EINVAL;
1986                 break;
1987         }
1988         return ret;
1989 }
1990
1991 static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr,
1992                 bool has_disp)
1993 {
1994         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1995
1996         if (data->smu_features[GNLD_DPM_UCLK].enabled)
1997                 return smum_send_msg_to_smc_with_parameter(hwmgr,
1998                         PPSMC_MSG_SetUclkFastSwitch,
1999                         has_disp ? 1 : 0);
2000
2001         return 0;
2002 }
2003
2004 int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
2005                 struct pp_display_clock_request *clock_req)
2006 {
2007         int result = 0;
2008         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2009         enum amd_pp_clock_type clk_type = clock_req->clock_type;
2010         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
2011         PPCLK_e clk_select = 0;
2012         uint32_t clk_request = 0;
2013
2014         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
2015                 switch (clk_type) {
2016                 case amd_pp_dcef_clock:
2017                         clk_select = PPCLK_DCEFCLK;
2018                         break;
2019                 case amd_pp_disp_clock:
2020                         clk_select = PPCLK_DISPCLK;
2021                         break;
2022                 case amd_pp_pixel_clock:
2023                         clk_select = PPCLK_PIXCLK;
2024                         break;
2025                 case amd_pp_phy_clock:
2026                         clk_select = PPCLK_PHYCLK;
2027                         break;
2028                 default:
2029                         pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
2030                         result = -EINVAL;
2031                         break;
2032                 }
2033
2034                 if (!result) {
2035                         clk_request = (clk_select << 16) | clk_freq;
2036                         result = smum_send_msg_to_smc_with_parameter(hwmgr,
2037                                         PPSMC_MSG_SetHardMinByFreq,
2038                                         clk_request);
2039                 }
2040         }
2041
2042         return result;
2043 }
2044
2045 static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2046                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
2047                                 PHM_PerformanceLevel *level)
2048 {
2049         return 0;
2050 }
2051
2052 static int vega20_notify_smc_display_config_after_ps_adjustment(
2053                 struct pp_hwmgr *hwmgr)
2054 {
2055         struct vega20_hwmgr *data =
2056                         (struct vega20_hwmgr *)(hwmgr->backend);
2057         struct vega20_single_dpm_table *dpm_table =
2058                         &data->dpm_table.mem_table;
2059         struct PP_Clocks min_clocks = {0};
2060         struct pp_display_clock_request clock_req;
2061         int ret = 0;
2062
2063         if ((hwmgr->display_config->num_display > 1) &&
2064              !hwmgr->display_config->multi_monitor_in_sync &&
2065              !hwmgr->display_config->nb_pstate_switch_disable)
2066                 vega20_notify_smc_display_change(hwmgr, false);
2067         else
2068                 vega20_notify_smc_display_change(hwmgr, true);
2069
2070         min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2071         min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2072         min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2073
2074         if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
2075                 clock_req.clock_type = amd_pp_dcef_clock;
2076                 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
2077                 if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) {
2078                         if (data->smu_features[GNLD_DS_DCEFCLK].supported)
2079                                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(
2080                                         hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
2081                                         min_clocks.dcefClockInSR / 100)) == 0,
2082                                         "Attempt to set divider for DCEFCLK Failed!",
2083                                         return ret);
2084                 } else {
2085                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2086                 }
2087         }
2088
2089         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2090                 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
2091                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2092                                 PPSMC_MSG_SetHardMinByFreq,
2093                                 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2094                                 "[SetHardMinFreq] Set hard min uclk failed!",
2095                                 return ret);
2096         }
2097
2098         return 0;
2099 }
2100
2101 static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
2102 {
2103         struct vega20_hwmgr *data =
2104                         (struct vega20_hwmgr *)(hwmgr->backend);
2105         uint32_t soft_level;
2106         int ret = 0;
2107
2108         soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2109
2110         data->dpm_table.gfx_table.dpm_state.soft_min_level =
2111                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2112                 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2113
2114         soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2115
2116         data->dpm_table.mem_table.dpm_state.soft_min_level =
2117                 data->dpm_table.mem_table.dpm_state.soft_max_level =
2118                 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2119
2120         ret = vega20_upload_dpm_min_level(hwmgr);
2121         PP_ASSERT_WITH_CODE(!ret,
2122                         "Failed to upload boot level to highest!",
2123                         return ret);
2124
2125         ret = vega20_upload_dpm_max_level(hwmgr);
2126         PP_ASSERT_WITH_CODE(!ret,
2127                         "Failed to upload dpm max level to highest!",
2128                         return ret);
2129
2130         return 0;
2131 }
2132
2133 static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2134 {
2135         struct vega20_hwmgr *data =
2136                         (struct vega20_hwmgr *)(hwmgr->backend);
2137         uint32_t soft_level;
2138         int ret = 0;
2139
2140         soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2141
2142         data->dpm_table.gfx_table.dpm_state.soft_min_level =
2143                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2144                 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2145
2146         soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2147
2148         data->dpm_table.mem_table.dpm_state.soft_min_level =
2149                 data->dpm_table.mem_table.dpm_state.soft_max_level =
2150                 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2151
2152         ret = vega20_upload_dpm_min_level(hwmgr);
2153         PP_ASSERT_WITH_CODE(!ret,
2154                         "Failed to upload boot level to highest!",
2155                         return ret);
2156
2157         ret = vega20_upload_dpm_max_level(hwmgr);
2158         PP_ASSERT_WITH_CODE(!ret,
2159                         "Failed to upload dpm max level to highest!",
2160                         return ret);
2161
2162         return 0;
2163
2164 }
2165
2166 static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2167 {
2168         int ret = 0;
2169
2170         ret = vega20_upload_dpm_min_level(hwmgr);
2171         PP_ASSERT_WITH_CODE(!ret,
2172                         "Failed to upload DPM Bootup Levels!",
2173                         return ret);
2174
2175         ret = vega20_upload_dpm_max_level(hwmgr);
2176         PP_ASSERT_WITH_CODE(!ret,
2177                         "Failed to upload DPM Max Levels!",
2178                         return ret);
2179
2180         return 0;
2181 }
2182
2183 static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2184                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2185 {
2186         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2187         struct vega20_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
2188         struct vega20_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
2189         struct vega20_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
2190
2191         *sclk_mask = 0;
2192         *mclk_mask = 0;
2193         *soc_mask  = 0;
2194
2195         if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
2196             mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
2197             soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
2198                 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
2199                 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2200                 *soc_mask  = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2201         }
2202
2203         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2204                 *sclk_mask = 0;
2205         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2206                 *mclk_mask = 0;
2207         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2208                 *sclk_mask = gfx_dpm_table->count - 1;
2209                 *mclk_mask = mem_dpm_table->count - 1;
2210                 *soc_mask  = soc_dpm_table->count - 1;
2211         }
2212
2213         return 0;
2214 }
2215
2216 static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
2217                 enum pp_clock_type type, uint32_t mask)
2218 {
2219         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2220         uint32_t soft_min_level, soft_max_level;
2221         int ret = 0;
2222
2223         switch (type) {
2224         case PP_SCLK:
2225                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2226                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2227
2228                 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2229                         data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2230                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2231                         data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2232
2233                 ret = vega20_upload_dpm_min_level(hwmgr);
2234                 PP_ASSERT_WITH_CODE(!ret,
2235                         "Failed to upload boot level to lowest!",
2236                         return ret);
2237
2238                 ret = vega20_upload_dpm_max_level(hwmgr);
2239                 PP_ASSERT_WITH_CODE(!ret,
2240                         "Failed to upload dpm max level to highest!",
2241                         return ret);
2242                 break;
2243
2244         case PP_MCLK:
2245                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2246                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2247
2248                 data->dpm_table.mem_table.dpm_state.soft_min_level =
2249                         data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2250                 data->dpm_table.mem_table.dpm_state.soft_max_level =
2251                         data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2252
2253                 ret = vega20_upload_dpm_min_level(hwmgr);
2254                 PP_ASSERT_WITH_CODE(!ret,
2255                         "Failed to upload boot level to lowest!",
2256                         return ret);
2257
2258                 ret = vega20_upload_dpm_max_level(hwmgr);
2259                 PP_ASSERT_WITH_CODE(!ret,
2260                         "Failed to upload dpm max level to highest!",
2261                         return ret);
2262
2263                 break;
2264
2265         case PP_PCIE:
2266                 break;
2267
2268         default:
2269                 break;
2270         }
2271
2272         return 0;
2273 }
2274
2275 static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
2276                                 enum amd_dpm_forced_level level)
2277 {
2278         int ret = 0;
2279         uint32_t sclk_mask, mclk_mask, soc_mask;
2280
2281         switch (level) {
2282         case AMD_DPM_FORCED_LEVEL_HIGH:
2283                 ret = vega20_force_dpm_highest(hwmgr);
2284                 break;
2285
2286         case AMD_DPM_FORCED_LEVEL_LOW:
2287                 ret = vega20_force_dpm_lowest(hwmgr);
2288                 break;
2289
2290         case AMD_DPM_FORCED_LEVEL_AUTO:
2291                 ret = vega20_unforce_dpm_levels(hwmgr);
2292                 break;
2293
2294         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2295         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2296         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2297         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2298                 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2299                 if (ret)
2300                         return ret;
2301                 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
2302                 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
2303                 break;
2304
2305         case AMD_DPM_FORCED_LEVEL_MANUAL:
2306         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2307         default:
2308                 break;
2309         }
2310
2311         return ret;
2312 }
2313
2314 static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr)
2315 {
2316         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2317
2318         if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
2319                 return AMD_FAN_CTRL_MANUAL;
2320         else
2321                 return AMD_FAN_CTRL_AUTO;
2322 }
2323
2324 static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
2325 {
2326         switch (mode) {
2327         case AMD_FAN_CTRL_NONE:
2328                 vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
2329                 break;
2330         case AMD_FAN_CTRL_MANUAL:
2331                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2332                         vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
2333                 break;
2334         case AMD_FAN_CTRL_AUTO:
2335                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2336                         vega20_fan_ctrl_start_smc_fan_control(hwmgr);
2337                 break;
2338         default:
2339                 break;
2340         }
2341 }
2342
2343 static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr,
2344                 struct amd_pp_simple_clock_info *info)
2345 {
2346 #if 0
2347         struct phm_ppt_v2_information *table_info =
2348                         (struct phm_ppt_v2_information *)hwmgr->pptable;
2349         struct phm_clock_and_voltage_limits *max_limits =
2350                         &table_info->max_clock_voltage_on_ac;
2351
2352         info->engine_max_clock = max_limits->sclk;
2353         info->memory_max_clock = max_limits->mclk;
2354 #endif
2355         return 0;
2356 }
2357
2358
2359 static int vega20_get_sclks(struct pp_hwmgr *hwmgr,
2360                 struct pp_clock_levels_with_latency *clocks)
2361 {
2362         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2363         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
2364         int i, count;
2365
2366         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
2367                 "[GetSclks]: gfxclk dpm not enabled!\n",
2368                 return -EPERM);
2369
2370         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2371         clocks->num_levels = count;
2372
2373         for (i = 0; i < count; i++) {
2374                 clocks->data[i].clocks_in_khz =
2375                         dpm_table->dpm_levels[i].value * 1000;
2376                 clocks->data[i].latency_in_us = 0;
2377         }
2378
2379         return 0;
2380 }
2381
2382 static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr,
2383                 uint32_t clock)
2384 {
2385         return 25;
2386 }
2387
2388 static int vega20_get_memclocks(struct pp_hwmgr *hwmgr,
2389                 struct pp_clock_levels_with_latency *clocks)
2390 {
2391         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2392         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table);
2393         int i, count;
2394
2395         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
2396                 "[GetMclks]: uclk dpm not enabled!\n",
2397                 return -EPERM);
2398
2399         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2400         clocks->num_levels = data->mclk_latency_table.count = count;
2401
2402         for (i = 0; i < count; i++) {
2403                 clocks->data[i].clocks_in_khz =
2404                         data->mclk_latency_table.entries[i].frequency =
2405                         dpm_table->dpm_levels[i].value * 1000;
2406                 clocks->data[i].latency_in_us =
2407                         data->mclk_latency_table.entries[i].latency =
2408                         vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
2409         }
2410
2411         return 0;
2412 }
2413
2414 static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr,
2415                 struct pp_clock_levels_with_latency *clocks)
2416 {
2417         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2418         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table);
2419         int i, count;
2420
2421         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_DCEFCLK].enabled,
2422                 "[GetDcfclocks]: dcefclk dpm not enabled!\n",
2423                 return -EPERM);
2424
2425         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2426         clocks->num_levels = count;
2427
2428         for (i = 0; i < count; i++) {
2429                 clocks->data[i].clocks_in_khz =
2430                         dpm_table->dpm_levels[i].value * 1000;
2431                 clocks->data[i].latency_in_us = 0;
2432         }
2433
2434         return 0;
2435 }
2436
2437 static int vega20_get_socclocks(struct pp_hwmgr *hwmgr,
2438                 struct pp_clock_levels_with_latency *clocks)
2439 {
2440         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2441         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table);
2442         int i, count;
2443
2444         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_SOCCLK].enabled,
2445                 "[GetSocclks]: socclk dpm not enabled!\n",
2446                 return -EPERM);
2447
2448         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2449         clocks->num_levels = count;
2450
2451         for (i = 0; i < count; i++) {
2452                 clocks->data[i].clocks_in_khz =
2453                         dpm_table->dpm_levels[i].value * 1000;
2454                 clocks->data[i].latency_in_us = 0;
2455         }
2456
2457         return 0;
2458
2459 }
2460
2461 static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
2462                 enum amd_pp_clock_type type,
2463                 struct pp_clock_levels_with_latency *clocks)
2464 {
2465         int ret;
2466
2467         switch (type) {
2468         case amd_pp_sys_clock:
2469                 ret = vega20_get_sclks(hwmgr, clocks);
2470                 break;
2471         case amd_pp_mem_clock:
2472                 ret = vega20_get_memclocks(hwmgr, clocks);
2473                 break;
2474         case amd_pp_dcef_clock:
2475                 ret = vega20_get_dcefclocks(hwmgr, clocks);
2476                 break;
2477         case amd_pp_soc_clock:
2478                 ret = vega20_get_socclocks(hwmgr, clocks);
2479                 break;
2480         default:
2481                 return -EINVAL;
2482         }
2483
2484         return ret;
2485 }
2486
2487 static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
2488                 enum amd_pp_clock_type type,
2489                 struct pp_clock_levels_with_voltage *clocks)
2490 {
2491         clocks->num_levels = 0;
2492
2493         return 0;
2494 }
2495
2496 static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
2497                                                    void *clock_ranges)
2498 {
2499         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2500         Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2501         struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
2502
2503         if (!data->registry_data.disable_water_mark &&
2504             data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2505             data->smu_features[GNLD_DPM_SOCCLK].supported) {
2506                 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
2507                 data->water_marks_bitmap |= WaterMarksExist;
2508                 data->water_marks_bitmap &= ~WaterMarksLoaded;
2509         }
2510
2511         return 0;
2512 }
2513
2514 static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
2515                                         enum PP_OD_DPM_TABLE_COMMAND type,
2516                                         long *input, uint32_t size)
2517 {
2518         struct vega20_hwmgr *data =
2519                         (struct vega20_hwmgr *)(hwmgr->backend);
2520         struct vega20_od8_single_setting *od8_settings =
2521                         data->od8_settings.od8_settings_array;
2522         OverDriveTable_t *od_table =
2523                         &(data->smc_state_table.overdrive_table);
2524         struct pp_clock_levels_with_latency clocks;
2525         int32_t input_index, input_clk, input_vol, i;
2526         int od8_id;
2527         int ret;
2528
2529         PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
2530                                 return -EINVAL);
2531
2532         switch (type) {
2533         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2534                 if (!(od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2535                       od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2536                         pr_info("Sclk min/max frequency overdrive not supported\n");
2537                         return -EOPNOTSUPP;
2538                 }
2539
2540                 for (i = 0; i < size; i += 2) {
2541                         if (i + 2 > size) {
2542                                 pr_info("invalid number of input parameters %d\n",
2543                                         size);
2544                                 return -EINVAL;
2545                         }
2546
2547                         input_index = input[i];
2548                         input_clk = input[i + 1];
2549
2550                         if (input_index != 0 && input_index != 1) {
2551                                 pr_info("Invalid index %d\n", input_index);
2552                                 pr_info("Support min/max sclk frequency setting only which index by 0/1\n");
2553                                 return -EINVAL;
2554                         }
2555
2556                         if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value ||
2557                             input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) {
2558                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2559                                         input_clk,
2560                                         od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2561                                         od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2562                                 return -EINVAL;
2563                         }
2564
2565                         if ((input_index == 0 && od_table->GfxclkFmin != input_clk) ||
2566                             (input_index == 1 && od_table->GfxclkFmax != input_clk))
2567                                 data->gfxclk_overdrive = true;
2568
2569                         if (input_index == 0)
2570                                 od_table->GfxclkFmin = input_clk;
2571                         else
2572                                 od_table->GfxclkFmax = input_clk;
2573                 }
2574
2575                 break;
2576
2577         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2578                 if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2579                         pr_info("Mclk max frequency overdrive not supported\n");
2580                         return -EOPNOTSUPP;
2581                 }
2582
2583                 ret = vega20_get_memclocks(hwmgr, &clocks);
2584                 PP_ASSERT_WITH_CODE(!ret,
2585                                 "Attempt to get memory clk levels failed!",
2586                                 return ret);
2587
2588                 for (i = 0; i < size; i += 2) {
2589                         if (i + 2 > size) {
2590                                 pr_info("invalid number of input parameters %d\n",
2591                                         size);
2592                                 return -EINVAL;
2593                         }
2594
2595                         input_index = input[i];
2596                         input_clk = input[i + 1];
2597
2598                         if (input_index != 1) {
2599                                 pr_info("Invalid index %d\n", input_index);
2600                                 pr_info("Support max Mclk frequency setting only which index by 1\n");
2601                                 return -EINVAL;
2602                         }
2603
2604                         if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2605                             input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) {
2606                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2607                                         input_clk,
2608                                         clocks.data[0].clocks_in_khz / 1000,
2609                                         od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2610                                 return -EINVAL;
2611                         }
2612
2613                         if (input_index == 1 && od_table->UclkFmax != input_clk)
2614                                 data->memclk_overdrive = true;
2615
2616                         od_table->UclkFmax = input_clk;
2617                 }
2618
2619                 break;
2620
2621         case PP_OD_EDIT_VDDC_CURVE:
2622                 if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2623                     od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2624                     od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2625                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2626                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2627                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2628                         pr_info("Voltage curve calibrate not supported\n");
2629                         return -EOPNOTSUPP;
2630                 }
2631
2632                 for (i = 0; i < size; i += 3) {
2633                         if (i + 3 > size) {
2634                                 pr_info("invalid number of input parameters %d\n",
2635                                         size);
2636                                 return -EINVAL;
2637                         }
2638
2639                         input_index = input[i];
2640                         input_clk = input[i + 1];
2641                         input_vol = input[i + 2];
2642
2643                         if (input_index > 2) {
2644                                 pr_info("Setting for point %d is not supported\n",
2645                                                 input_index + 1);
2646                                 pr_info("Three supported points index by 0, 1, 2\n");
2647                                 return -EINVAL;
2648                         }
2649
2650                         od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2651                         if (input_clk < od8_settings[od8_id].min_value ||
2652                             input_clk > od8_settings[od8_id].max_value) {
2653                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2654                                         input_clk,
2655                                         od8_settings[od8_id].min_value,
2656                                         od8_settings[od8_id].max_value);
2657                                 return -EINVAL;
2658                         }
2659
2660                         od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2661                         if (input_vol < od8_settings[od8_id].min_value ||
2662                             input_vol > od8_settings[od8_id].max_value) {
2663                                 pr_info("clock voltage %d is not within allowed range [%d - %d]\n",
2664                                         input_vol,
2665                                         od8_settings[od8_id].min_value,
2666                                         od8_settings[od8_id].max_value);
2667                                 return -EINVAL;
2668                         }
2669
2670                         switch (input_index) {
2671                         case 0:
2672                                 od_table->GfxclkFreq1 = input_clk;
2673                                 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2674                                 break;
2675                         case 1:
2676                                 od_table->GfxclkFreq2 = input_clk;
2677                                 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2678                                 break;
2679                         case 2:
2680                                 od_table->GfxclkFreq3 = input_clk;
2681                                 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2682                                 break;
2683                         }
2684                 }
2685                 break;
2686
2687         case PP_OD_RESTORE_DEFAULT_TABLE:
2688                 data->gfxclk_overdrive = false;
2689                 data->memclk_overdrive = false;
2690
2691                 ret = smum_smc_table_manager(hwmgr,
2692                                              (uint8_t *)od_table,
2693                                              TABLE_OVERDRIVE, true);
2694                 PP_ASSERT_WITH_CODE(!ret,
2695                                 "Failed to export overdrive table!",
2696                                 return ret);
2697                 break;
2698
2699         case PP_OD_COMMIT_DPM_TABLE:
2700                 ret = smum_smc_table_manager(hwmgr,
2701                                              (uint8_t *)od_table,
2702                                              TABLE_OVERDRIVE, false);
2703                 PP_ASSERT_WITH_CODE(!ret,
2704                                 "Failed to import overdrive table!",
2705                                 return ret);
2706
2707                 /* retrieve updated gfxclk table */
2708                 if (data->gfxclk_overdrive) {
2709                         data->gfxclk_overdrive = false;
2710
2711                         ret = vega20_setup_gfxclk_dpm_table(hwmgr);
2712                         if (ret)
2713                                 return ret;
2714                 }
2715
2716                 /* retrieve updated memclk table */
2717                 if (data->memclk_overdrive) {
2718                         data->memclk_overdrive = false;
2719
2720                         ret = vega20_setup_memclk_dpm_table(hwmgr);
2721                         if (ret)
2722                                 return ret;
2723                 }
2724                 break;
2725
2726         default:
2727                 return -EINVAL;
2728         }
2729
2730         return 0;
2731 }
2732
2733 static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
2734                 enum pp_clock_type type, char *buf)
2735 {
2736         struct vega20_hwmgr *data =
2737                         (struct vega20_hwmgr *)(hwmgr->backend);
2738         struct vega20_od8_single_setting *od8_settings =
2739                         data->od8_settings.od8_settings_array;
2740         OverDriveTable_t *od_table =
2741                         &(data->smc_state_table.overdrive_table);
2742         struct pp_clock_levels_with_latency clocks;
2743         int i, now, size = 0;
2744         int ret = 0;
2745
2746         switch (type) {
2747         case PP_SCLK:
2748                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now);
2749                 PP_ASSERT_WITH_CODE(!ret,
2750                                 "Attempt to get current gfx clk Failed!",
2751                                 return ret);
2752
2753                 ret = vega20_get_sclks(hwmgr, &clocks);
2754                 PP_ASSERT_WITH_CODE(!ret,
2755                                 "Attempt to get gfx clk levels Failed!",
2756                                 return ret);
2757
2758                 for (i = 0; i < clocks.num_levels; i++)
2759                         size += sprintf(buf + size, "%d: %uMhz %s\n",
2760                                 i, clocks.data[i].clocks_in_khz / 1000,
2761                                 (clocks.data[i].clocks_in_khz == now) ? "*" : "");
2762                 break;
2763
2764         case PP_MCLK:
2765                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);
2766                 PP_ASSERT_WITH_CODE(!ret,
2767                                 "Attempt to get current mclk freq Failed!",
2768                                 return ret);
2769
2770                 ret = vega20_get_memclocks(hwmgr, &clocks);
2771                 PP_ASSERT_WITH_CODE(!ret,
2772                                 "Attempt to get memory clk levels Failed!",
2773                                 return ret);
2774
2775                 for (i = 0; i < clocks.num_levels; i++)
2776                         size += sprintf(buf + size, "%d: %uMhz %s\n",
2777                                 i, clocks.data[i].clocks_in_khz / 1000,
2778                                 (clocks.data[i].clocks_in_khz == now) ? "*" : "");
2779                 break;
2780
2781         case PP_PCIE:
2782                 break;
2783
2784         case OD_SCLK:
2785                 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2786                     od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
2787                         size = sprintf(buf, "%s:\n", "OD_SCLK");
2788                         size += sprintf(buf + size, "0: %10uMhz\n",
2789                                 od_table->GfxclkFmin);
2790                         size += sprintf(buf + size, "1: %10uMhz\n",
2791                                 od_table->GfxclkFmax);
2792                 }
2793                 break;
2794
2795         case OD_MCLK:
2796                 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2797                         size = sprintf(buf, "%s:\n", "OD_MCLK");
2798                         size += sprintf(buf + size, "1: %10uMhz\n",
2799                                 od_table->UclkFmax);
2800                 }
2801
2802                 break;
2803
2804         case OD_VDDC_CURVE:
2805                 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2806                     od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2807                     od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2808                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2809                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2810                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
2811                         size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
2812                         size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
2813                                 od_table->GfxclkFreq1,
2814                                 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
2815                         size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
2816                                 od_table->GfxclkFreq2,
2817                                 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
2818                         size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
2819                                 od_table->GfxclkFreq3,
2820                                 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
2821                 }
2822
2823                 break;
2824
2825         case OD_RANGE:
2826                 size = sprintf(buf, "%s:\n", "OD_RANGE");
2827
2828                 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2829                     od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
2830                         size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
2831                                 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2832                                 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2833                 }
2834
2835                 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2836                         ret = vega20_get_memclocks(hwmgr, &clocks);
2837                         PP_ASSERT_WITH_CODE(!ret,
2838                                         "Fail to get memory clk levels!",
2839                                         return ret);
2840
2841                         size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
2842                                 clocks.data[0].clocks_in_khz / 1000,
2843                                 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2844                 }
2845
2846                 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2847                     od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2848                     od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2849                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2850                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2851                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
2852                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
2853                                 od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
2854                                 od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);
2855                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
2856                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
2857                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
2858                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
2859                                 od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
2860                                 od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);
2861                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
2862                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
2863                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
2864                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
2865                                 od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
2866                                 od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);
2867                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
2868                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
2869                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
2870                 }
2871
2872                 break;
2873         default:
2874                 break;
2875         }
2876         return size;
2877 }
2878
2879 static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
2880                 struct vega20_single_dpm_table *dpm_table)
2881 {
2882         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2883         int ret = 0;
2884
2885         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2886                 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
2887                                 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
2888                                 return -EINVAL);
2889                 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
2890                                 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
2891                                 return -EINVAL);
2892
2893                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2894                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2895                                 PPSMC_MSG_SetHardMinByFreq,
2896                                 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2897                                 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
2898                                 return ret);
2899         }
2900
2901         return ret;
2902 }
2903
2904 static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2905 {
2906         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2907         int ret = 0;
2908
2909         smum_send_msg_to_smc_with_parameter(hwmgr,
2910                         PPSMC_MSG_NumOfDisplays, 0);
2911
2912         ret = vega20_set_uclk_to_highest_dpm_level(hwmgr,
2913                         &data->dpm_table.mem_table);
2914
2915         return ret;
2916 }
2917
2918 static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2919 {
2920         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2921         int result = 0;
2922         Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
2923
2924         if ((data->water_marks_bitmap & WaterMarksExist) &&
2925             !(data->water_marks_bitmap & WaterMarksLoaded)) {
2926                 result = smum_smc_table_manager(hwmgr,
2927                                                 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
2928                 PP_ASSERT_WITH_CODE(!result,
2929                                 "Failed to update WMTABLE!",
2930                                 return result);
2931                 data->water_marks_bitmap |= WaterMarksLoaded;
2932         }
2933
2934         if ((data->water_marks_bitmap & WaterMarksExist) &&
2935             data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2936             data->smu_features[GNLD_DPM_SOCCLK].supported) {
2937                 result = smum_send_msg_to_smc_with_parameter(hwmgr,
2938                         PPSMC_MSG_NumOfDisplays,
2939                         hwmgr->display_config->num_display);
2940         }
2941
2942         return result;
2943 }
2944
2945 int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
2946 {
2947         struct vega20_hwmgr *data =
2948                         (struct vega20_hwmgr *)(hwmgr->backend);
2949         int ret = 0;
2950
2951         if (data->smu_features[GNLD_DPM_UVD].supported) {
2952                 if (data->smu_features[GNLD_DPM_UVD].enabled == enable) {
2953                         if (enable)
2954                                 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already enabled!\n");
2955                         else
2956                                 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already disabled!\n");
2957                 }
2958
2959                 ret = vega20_enable_smc_features(hwmgr,
2960                                 enable,
2961                                 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap);
2962                 PP_ASSERT_WITH_CODE(!ret,
2963                                 "[EnableDisableUVDDPM] Attempt to Enable/Disable DPM UVD Failed!",
2964                                 return ret);
2965                 data->smu_features[GNLD_DPM_UVD].enabled = enable;
2966         }
2967
2968         return 0;
2969 }
2970
2971 static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
2972 {
2973         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2974
2975         if (data->vce_power_gated == bgate)
2976                 return ;
2977
2978         data->vce_power_gated = bgate;
2979         vega20_enable_disable_vce_dpm(hwmgr, !bgate);
2980 }
2981
2982 static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
2983 {
2984         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2985
2986         if (data->uvd_power_gated == bgate)
2987                 return ;
2988
2989         data->uvd_power_gated = bgate;
2990         vega20_enable_disable_uvd_dpm(hwmgr, !bgate);
2991 }
2992
2993 static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
2994 {
2995         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2996         struct vega20_single_dpm_table *dpm_table;
2997         bool vblank_too_short = false;
2998         bool disable_mclk_switching;
2999         uint32_t i, latency;
3000
3001         disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3002                            !hwmgr->display_config->multi_monitor_in_sync) ||
3003                             vblank_too_short;
3004     latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3005
3006         /* gfxclk */
3007         dpm_table = &(data->dpm_table.gfx_table);
3008         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3009         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3010         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3011         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3012
3013         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3014                 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
3015                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3016                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3017                 }
3018
3019                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3020                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3021                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3022                 }
3023
3024                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3025                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3026                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3027                 }
3028         }
3029
3030         /* memclk */
3031         dpm_table = &(data->dpm_table.mem_table);
3032         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3033         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3034         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3035         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3036
3037         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3038                 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
3039                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3040                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3041                 }
3042
3043                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
3044                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3045                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3046                 }
3047
3048                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3049                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3050                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3051                 }
3052         }
3053
3054         /* honour DAL's UCLK Hardmin */
3055         if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
3056                 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
3057
3058         /* Hardmin is dependent on displayconfig */
3059         if (disable_mclk_switching) {
3060                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3061                 for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
3062                         if (data->mclk_latency_table.entries[i].latency <= latency) {
3063                                 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
3064                                         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
3065                                         break;
3066                                 }
3067                         }
3068                 }
3069         }
3070
3071         if (hwmgr->display_config->nb_pstate_switch_disable)
3072                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3073
3074         /* vclk */
3075         dpm_table = &(data->dpm_table.vclk_table);
3076         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3077         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3078         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3079         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3080
3081         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3082                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3083                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3084                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3085                 }
3086
3087                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3088                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3089                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3090                 }
3091         }
3092
3093         /* dclk */
3094         dpm_table = &(data->dpm_table.dclk_table);
3095         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3096         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3097         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3098         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3099
3100         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3101                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3102                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3103                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3104                 }
3105
3106                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3107                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3108                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3109                 }
3110         }
3111
3112         /* socclk */
3113         dpm_table = &(data->dpm_table.soc_table);
3114         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3115         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3116         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3117         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3118
3119         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3120                 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
3121                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3122                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3123                 }
3124
3125                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3126                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3127                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3128                 }
3129         }
3130
3131         /* eclk */
3132         dpm_table = &(data->dpm_table.eclk_table);
3133         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3134         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3135         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3136         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3137
3138         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3139                 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
3140                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3141                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3142                 }
3143
3144                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3145                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3146                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3147                 }
3148         }
3149
3150         return 0;
3151 }
3152
3153 static bool
3154 vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
3155 {
3156         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3157         bool is_update_required = false;
3158
3159         if (data->display_timing.num_existing_displays !=
3160                         hwmgr->display_config->num_display)
3161                 is_update_required = true;
3162
3163         if (data->registry_data.gfx_clk_deep_sleep_support &&
3164            (data->display_timing.min_clock_in_sr !=
3165             hwmgr->display_config->min_core_set_clock_in_sr))
3166                 is_update_required = true;
3167
3168         return is_update_required;
3169 }
3170
3171 static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
3172 {
3173         int ret = 0;
3174
3175         ret = vega20_disable_all_smu_features(hwmgr);
3176         PP_ASSERT_WITH_CODE(!ret,
3177                         "[DisableDpmTasks] Failed to disable all smu features!",
3178                         return ret);
3179
3180         return 0;
3181 }
3182
3183 static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
3184 {
3185         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3186         int result;
3187
3188         result = vega20_disable_dpm_tasks(hwmgr);
3189         PP_ASSERT_WITH_CODE((0 == result),
3190                         "[PowerOffAsic] Failed to disable DPM!",
3191                         );
3192         data->water_marks_bitmap &= ~(WaterMarksLoaded);
3193
3194         return result;
3195 }
3196
3197 static int conv_power_profile_to_pplib_workload(int power_profile)
3198 {
3199         int pplib_workload = 0;
3200
3201         switch (power_profile) {
3202         case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
3203                 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
3204                 break;
3205         case PP_SMC_POWER_PROFILE_POWERSAVING:
3206                 pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
3207                 break;
3208         case PP_SMC_POWER_PROFILE_VIDEO:
3209                 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
3210                 break;
3211         case PP_SMC_POWER_PROFILE_VR:
3212                 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
3213                 break;
3214         case PP_SMC_POWER_PROFILE_COMPUTE:
3215                 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
3216                 break;
3217         case PP_SMC_POWER_PROFILE_CUSTOM:
3218                 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
3219                 break;
3220         }
3221
3222         return pplib_workload;
3223 }
3224
3225 static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
3226 {
3227         DpmActivityMonitorCoeffInt_t activity_monitor;
3228         uint32_t i, size = 0;
3229         uint16_t workload_type = 0;
3230         static const char *profile_name[] = {
3231                                         "3D_FULL_SCREEN",
3232                                         "POWER_SAVING",
3233                                         "VIDEO",
3234                                         "VR",
3235                                         "COMPUTE",
3236                                         "CUSTOM"};
3237         static const char *title[] = {
3238                         "PROFILE_INDEX(NAME)",
3239                         "CLOCK_TYPE(NAME)",
3240                         "FPS",
3241                         "UseRlcBusy",
3242                         "MinActiveFreqType",
3243                         "MinActiveFreq",
3244                         "BoosterFreqType",
3245                         "BoosterFreq",
3246                         "PD_Data_limit_c",
3247                         "PD_Data_error_coeff",
3248                         "PD_Data_error_rate_coeff"};
3249         int result = 0;
3250
3251         if (!buf)
3252                 return -EINVAL;
3253
3254         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
3255                         title[0], title[1], title[2], title[3], title[4], title[5],
3256                         title[6], title[7], title[8], title[9], title[10]);
3257
3258         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
3259                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3260                 workload_type = conv_power_profile_to_pplib_workload(i);
3261                 result = vega20_get_activity_monitor_coeff(hwmgr,
3262                                 (uint8_t *)(&activity_monitor), workload_type);
3263                 PP_ASSERT_WITH_CODE(!result,
3264                                 "[GetPowerProfile] Failed to get activity monitor!",
3265                                 return result);
3266
3267                 size += sprintf(buf + size, "%2d %14s%s:\n",
3268                         i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ");
3269
3270                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3271                         " ",
3272                         0,
3273                         "GFXCLK",
3274                         activity_monitor.Gfx_FPS,
3275                         activity_monitor.Gfx_UseRlcBusy,
3276                         activity_monitor.Gfx_MinActiveFreqType,
3277                         activity_monitor.Gfx_MinActiveFreq,
3278                         activity_monitor.Gfx_BoosterFreqType,
3279                         activity_monitor.Gfx_BoosterFreq,
3280                         activity_monitor.Gfx_PD_Data_limit_c,
3281                         activity_monitor.Gfx_PD_Data_error_coeff,
3282                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
3283
3284                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3285                         " ",
3286                         1,
3287                         "SOCCLK",
3288                         activity_monitor.Soc_FPS,
3289                         activity_monitor.Soc_UseRlcBusy,
3290                         activity_monitor.Soc_MinActiveFreqType,
3291                         activity_monitor.Soc_MinActiveFreq,
3292                         activity_monitor.Soc_BoosterFreqType,
3293                         activity_monitor.Soc_BoosterFreq,
3294                         activity_monitor.Soc_PD_Data_limit_c,
3295                         activity_monitor.Soc_PD_Data_error_coeff,
3296                         activity_monitor.Soc_PD_Data_error_rate_coeff);
3297
3298                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3299                         " ",
3300                         2,
3301                         "UCLK",
3302                         activity_monitor.Mem_FPS,
3303                         activity_monitor.Mem_UseRlcBusy,
3304                         activity_monitor.Mem_MinActiveFreqType,
3305                         activity_monitor.Mem_MinActiveFreq,
3306                         activity_monitor.Mem_BoosterFreqType,
3307                         activity_monitor.Mem_BoosterFreq,
3308                         activity_monitor.Mem_PD_Data_limit_c,
3309                         activity_monitor.Mem_PD_Data_error_coeff,
3310                         activity_monitor.Mem_PD_Data_error_rate_coeff);
3311
3312                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3313                         " ",
3314                         3,
3315                         "FCLK",
3316                         activity_monitor.Fclk_FPS,
3317                         activity_monitor.Fclk_UseRlcBusy,
3318                         activity_monitor.Fclk_MinActiveFreqType,
3319                         activity_monitor.Fclk_MinActiveFreq,
3320                         activity_monitor.Fclk_BoosterFreqType,
3321                         activity_monitor.Fclk_BoosterFreq,
3322                         activity_monitor.Fclk_PD_Data_limit_c,
3323                         activity_monitor.Fclk_PD_Data_error_coeff,
3324                         activity_monitor.Fclk_PD_Data_error_rate_coeff);
3325         }
3326
3327         return size;
3328 }
3329
3330 static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
3331 {
3332         DpmActivityMonitorCoeffInt_t activity_monitor;
3333         int workload_type, result = 0;
3334
3335         hwmgr->power_profile_mode = input[size];
3336
3337         if (hwmgr->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
3338                 pr_err("Invalid power profile mode %d\n", hwmgr->power_profile_mode);
3339                 return -EINVAL;
3340         }
3341
3342         if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
3343                 if (size < 10)
3344                         return -EINVAL;
3345
3346                 result = vega20_get_activity_monitor_coeff(hwmgr,
3347                                 (uint8_t *)(&activity_monitor),
3348                                 WORKLOAD_PPLIB_CUSTOM_BIT);
3349                 PP_ASSERT_WITH_CODE(!result,
3350                                 "[SetPowerProfile] Failed to get activity monitor!",
3351                                 return result);
3352
3353                 switch (input[0]) {
3354                 case 0: /* Gfxclk */
3355                         activity_monitor.Gfx_FPS = input[1];
3356                         activity_monitor.Gfx_UseRlcBusy = input[2];
3357                         activity_monitor.Gfx_MinActiveFreqType = input[3];
3358                         activity_monitor.Gfx_MinActiveFreq = input[4];
3359                         activity_monitor.Gfx_BoosterFreqType = input[5];
3360                         activity_monitor.Gfx_BoosterFreq = input[6];
3361                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
3362                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
3363                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
3364                         break;
3365                 case 1: /* Socclk */
3366                         activity_monitor.Soc_FPS = input[1];
3367                         activity_monitor.Soc_UseRlcBusy = input[2];
3368                         activity_monitor.Soc_MinActiveFreqType = input[3];
3369                         activity_monitor.Soc_MinActiveFreq = input[4];
3370                         activity_monitor.Soc_BoosterFreqType = input[5];
3371                         activity_monitor.Soc_BoosterFreq = input[6];
3372                         activity_monitor.Soc_PD_Data_limit_c = input[7];
3373                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
3374                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
3375                         break;
3376                 case 2: /* Uclk */
3377                         activity_monitor.Mem_FPS = input[1];
3378                         activity_monitor.Mem_UseRlcBusy = input[2];
3379                         activity_monitor.Mem_MinActiveFreqType = input[3];
3380                         activity_monitor.Mem_MinActiveFreq = input[4];
3381                         activity_monitor.Mem_BoosterFreqType = input[5];
3382                         activity_monitor.Mem_BoosterFreq = input[6];
3383                         activity_monitor.Mem_PD_Data_limit_c = input[7];
3384                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
3385                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
3386                         break;
3387                 case 3: /* Fclk */
3388                         activity_monitor.Fclk_FPS = input[1];
3389                         activity_monitor.Fclk_UseRlcBusy = input[2];
3390                         activity_monitor.Fclk_MinActiveFreqType = input[3];
3391                         activity_monitor.Fclk_MinActiveFreq = input[4];
3392                         activity_monitor.Fclk_BoosterFreqType = input[5];
3393                         activity_monitor.Fclk_BoosterFreq = input[6];
3394                         activity_monitor.Fclk_PD_Data_limit_c = input[7];
3395                         activity_monitor.Fclk_PD_Data_error_coeff = input[8];
3396                         activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
3397                         break;
3398                 }
3399
3400                 result = vega20_set_activity_monitor_coeff(hwmgr,
3401                                 (uint8_t *)(&activity_monitor),
3402                                 WORKLOAD_PPLIB_CUSTOM_BIT);
3403                 PP_ASSERT_WITH_CODE(!result,
3404                                 "[SetPowerProfile] Failed to set activity monitor!",
3405                                 return result);
3406         }
3407
3408         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3409         workload_type =
3410                 conv_power_profile_to_pplib_workload(hwmgr->power_profile_mode);
3411         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
3412                                                 1 << workload_type);
3413
3414         return 0;
3415 }
3416
3417 static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
3418                                         uint32_t virtual_addr_low,
3419                                         uint32_t virtual_addr_hi,
3420                                         uint32_t mc_addr_low,
3421                                         uint32_t mc_addr_hi,
3422                                         uint32_t size)
3423 {
3424         smum_send_msg_to_smc_with_parameter(hwmgr,
3425                                         PPSMC_MSG_SetSystemVirtualDramAddrHigh,
3426                                         virtual_addr_hi);
3427         smum_send_msg_to_smc_with_parameter(hwmgr,
3428                                         PPSMC_MSG_SetSystemVirtualDramAddrLow,
3429                                         virtual_addr_low);
3430         smum_send_msg_to_smc_with_parameter(hwmgr,
3431                                         PPSMC_MSG_DramLogSetDramAddrHigh,
3432                                         mc_addr_hi);
3433
3434         smum_send_msg_to_smc_with_parameter(hwmgr,
3435                                         PPSMC_MSG_DramLogSetDramAddrLow,
3436                                         mc_addr_low);
3437
3438         smum_send_msg_to_smc_with_parameter(hwmgr,
3439                                         PPSMC_MSG_DramLogSetDramSize,
3440                                         size);
3441         return 0;
3442 }
3443
3444 static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
3445                 struct PP_TemperatureRange *thermal_data)
3446 {
3447         struct phm_ppt_v3_information *pptable_information =
3448                 (struct phm_ppt_v3_information *)hwmgr->pptable;
3449
3450         memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
3451
3452         thermal_data->max = pptable_information->us_software_shutdown_temp *
3453                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3454
3455         return 0;
3456 }
3457
3458 static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
3459         /* init/fini related */
3460         .backend_init =
3461                 vega20_hwmgr_backend_init,
3462         .backend_fini =
3463                 vega20_hwmgr_backend_fini,
3464         .asic_setup =
3465                 vega20_setup_asic_task,
3466         .power_off_asic =
3467                 vega20_power_off_asic,
3468         .dynamic_state_management_enable =
3469                 vega20_enable_dpm_tasks,
3470         .dynamic_state_management_disable =
3471                 vega20_disable_dpm_tasks,
3472         /* power state related */
3473         .apply_clocks_adjust_rules =
3474                 vega20_apply_clocks_adjust_rules,
3475         .pre_display_config_changed =
3476                 vega20_pre_display_configuration_changed_task,
3477         .display_config_changed =
3478                 vega20_display_configuration_changed_task,
3479         .check_smc_update_required_for_display_configuration =
3480                 vega20_check_smc_update_required_for_display_configuration,
3481         .notify_smc_display_config_after_ps_adjustment =
3482                 vega20_notify_smc_display_config_after_ps_adjustment,
3483         /* export to DAL */
3484         .get_sclk =
3485                 vega20_dpm_get_sclk,
3486         .get_mclk =
3487                 vega20_dpm_get_mclk,
3488         .get_dal_power_level =
3489                 vega20_get_dal_power_level,
3490         .get_clock_by_type_with_latency =
3491                 vega20_get_clock_by_type_with_latency,
3492         .get_clock_by_type_with_voltage =
3493                 vega20_get_clock_by_type_with_voltage,
3494         .set_watermarks_for_clocks_ranges =
3495                 vega20_set_watermarks_for_clocks_ranges,
3496         .display_clock_voltage_request =
3497                 vega20_display_clock_voltage_request,
3498         .get_performance_level =
3499                 vega20_get_performance_level,
3500         /* UMD pstate, profile related */
3501         .force_dpm_level =
3502                 vega20_dpm_force_dpm_level,
3503         .get_power_profile_mode =
3504                 vega20_get_power_profile_mode,
3505         .set_power_profile_mode =
3506                 vega20_set_power_profile_mode,
3507         /* od related */
3508         .set_power_limit =
3509                 vega20_set_power_limit,
3510         .get_sclk_od =
3511                 vega20_get_sclk_od,
3512         .set_sclk_od =
3513                 vega20_set_sclk_od,
3514         .get_mclk_od =
3515                 vega20_get_mclk_od,
3516         .set_mclk_od =
3517                 vega20_set_mclk_od,
3518         .odn_edit_dpm_table =
3519                 vega20_odn_edit_dpm_table,
3520         /* for sysfs to retrive/set gfxclk/memclk */
3521         .force_clock_level =
3522                 vega20_force_clock_level,
3523         .print_clock_levels =
3524                 vega20_print_clock_levels,
3525         .read_sensor =
3526                 vega20_read_sensor,
3527         /* powergate related */
3528         .powergate_uvd =
3529                 vega20_power_gate_uvd,
3530         .powergate_vce =
3531                 vega20_power_gate_vce,
3532         /* thermal related */
3533         .start_thermal_controller =
3534                 vega20_start_thermal_controller,
3535         .stop_thermal_controller =
3536                 vega20_thermal_stop_thermal_controller,
3537         .get_thermal_temperature_range =
3538                 vega20_get_thermal_temperature_range,
3539         .register_irq_handlers =
3540                 smu9_register_irq_handlers,
3541         .disable_smc_firmware_ctf =
3542                 vega20_thermal_disable_alert,
3543         /* fan control related */
3544         .get_fan_speed_percent =
3545                 vega20_fan_ctrl_get_fan_speed_percent,
3546         .set_fan_speed_percent =
3547                 vega20_fan_ctrl_set_fan_speed_percent,
3548         .get_fan_speed_info =
3549                 vega20_fan_ctrl_get_fan_speed_info,
3550         .get_fan_speed_rpm =
3551                 vega20_fan_ctrl_get_fan_speed_rpm,
3552         .set_fan_speed_rpm =
3553                 vega20_fan_ctrl_set_fan_speed_rpm,
3554         .get_fan_control_mode =
3555                 vega20_get_fan_control_mode,
3556         .set_fan_control_mode =
3557                 vega20_set_fan_control_mode,
3558         /* smu memory related */
3559         .notify_cac_buffer_info =
3560                 vega20_notify_cac_buffer_info,
3561         .enable_mgpu_fan_boost =
3562                 vega20_enable_mgpu_fan_boost,
3563 };
3564
3565 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
3566 {
3567         hwmgr->hwmgr_func = &vega20_hwmgr_funcs;
3568         hwmgr->pptable_func = &vega20_pptable_funcs;
3569
3570         return 0;
3571 }