drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/fb.h>
  26 #include "linux/delay.h"
  27 #include "pp_acpi.h"
  28 #include "hwmgr.h"
  29 #include <atombios.h>
  30 #include "tonga_hwmgr.h"
  31 #include "pptable.h"
  32 #include "processpptables.h"
  33 #include "tonga_processpptables.h"
  34 #include "tonga_pptable.h"
  35 #include "pp_debug.h"
  36 #include "tonga_ppsmc.h"
  37 #include "cgs_common.h"
  38 #include "pppcielanes.h"
  39 #include "tonga_dyn_defaults.h"
  40 #include "smumgr.h"
  41 #include "tonga_smumgr.h"
  42 #include "tonga_clockpowergating.h"
  43 #include "tonga_thermal.h"
  44
  45 #include "smu/smu_7_1_2_d.h"
  46 #include "smu/smu_7_1_2_sh_mask.h"
  47
  48 #include "gmc/gmc_8_1_d.h"
  49 #include "gmc/gmc_8_1_sh_mask.h"
  50
  51 #include "bif/bif_5_0_d.h"
  52 #include "bif/bif_5_0_sh_mask.h"
  53
  54 #include "cgs_linux.h"
  55 #include "eventmgr.h"
  56
  57 #define MC_CG_ARB_FREQ_F0           0x0a
  58 #define MC_CG_ARB_FREQ_F1           0x0b
  59 #define MC_CG_ARB_FREQ_F2           0x0c
  60 #define MC_CG_ARB_FREQ_F3           0x0d
  61
  62 #define MC_CG_SEQ_DRAMCONF_S0       0x05
  63 #define MC_CG_SEQ_DRAMCONF_S1       0x06
  64 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
  65 #define MC_CG_SEQ_YCLK_RESUME       0x0a
  66
  67 #define PCIE_BUS_CLK                10000
  68 #define TCLK                        (PCIE_BUS_CLK / 10)
  69
  70 #define SMC_RAM_END 0x40000
  71 #define SMC_CG_IND_START            0xc0030000
  72 #define SMC_CG_IND_END              0xc0040000  /* First byte after SMC_CG_IND*/
  73
  74 #define VOLTAGE_SCALE               4
  75 #define VOLTAGE_VID_OFFSET_SCALE1   625
  76 #define VOLTAGE_VID_OFFSET_SCALE2   100
  77
  78 #define VDDC_VDDCI_DELTA            200
  79 #define VDDC_VDDGFX_DELTA           300
  80
  81 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  82 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  83 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  84
  85 typedef uint32_t PECI_RegistryValue;
  86
  87 /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */
  88 uint16_t PP_ClockStretcherLookupTable[2][4] = {
  89         {600, 1050, 3, 0},
  90         {600, 1050, 6, 1} };
  91
  92 /* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
  93 uint32_t PP_ClockStretcherDDTTable[2][4][4] = {
  94         { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
  95         { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
  96
  97 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
  98 uint8_t PP_ClockStretchAmountConversion[2][6] = {
  99         {0, 1, 3, 2, 4, 5},
 100         {0, 2, 4, 5, 6, 5} };
 101
 102 /* Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 103 enum DPM_EVENT_SRC {
 104         DPM_EVENT_SRC_ANALOG = 0,               /* Internal analog trip point */
 105         DPM_EVENT_SRC_EXTERNAL = 1,             /* External (GPIO 17) signal */
 106         DPM_EVENT_SRC_DIGITAL = 2,              /* Internal digital trip point (DIG_THERM_DPM) */
 107         DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,   /* Internal analog or external */
 108         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4   /* Internal digital or external */
 109 };
 110 typedef enum DPM_EVENT_SRC DPM_EVENT_SRC;
 111
 112 enum DISPLAY_GAP {
 113         DISPLAY_GAP_VBLANK_OR_WM = 0,   /* Wait for vblank or MCHG watermark. */
 114         DISPLAY_GAP_VBLANK       = 1,   /* Wait for vblank. */
 115         DISPLAY_GAP_WATERMARK    = 2,   /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
 116         DISPLAY_GAP_IGNORE       = 3    /* Do not wait. */
 117 };
 118 typedef enum DISPLAY_GAP DISPLAY_GAP;
 119
 120 const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic);
 121
 122 struct tonga_power_state *cast_phw_tonga_power_state(
 123                                   struct pp_hw_power_state *hw_ps)
 124 {
 125         PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
 126                                 "Invalid Powerstate Type!",
 127                                  return NULL;);
 128
 129         return (struct tonga_power_state *)hw_ps;
 130 }
 131
 132 const struct tonga_power_state *cast_const_phw_tonga_power_state(
 133                                  const struct pp_hw_power_state *hw_ps)
 134 {
 135         PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
 136                                 "Invalid Powerstate Type!",
 137                                  return NULL;);
 138
 139         return (const struct tonga_power_state *)hw_ps;
 140 }
 141
 142 int tonga_add_voltage(struct pp_hwmgr *hwmgr,
 143         phm_ppt_v1_voltage_lookup_table *look_up_table,
 144         phm_ppt_v1_voltage_lookup_record *record)
 145 {
 146         uint32_t i;
 147         PP_ASSERT_WITH_CODE((NULL != look_up_table),
 148                 "Lookup Table empty.", return -1;);
 149         PP_ASSERT_WITH_CODE((0 != look_up_table->count),
 150                 "Lookup Table empty.", return -1;);
 151         PP_ASSERT_WITH_CODE((SMU72_MAX_LEVELS_VDDGFX >= look_up_table->count),
 152                 "Lookup Table is full.", return -1;);
 153
 154         /* This is to avoid entering duplicate calculated records. */
 155         for (i = 0; i < look_up_table->count; i++) {
 156                 if (look_up_table->entries[i].us_vdd == record->us_vdd) {
 157                         if (look_up_table->entries[i].us_calculated == 1)
 158                                 return 0;
 159                         else
 160                                 break;
 161                 }
 162         }
 163
 164         look_up_table->entries[i].us_calculated = 1;
 165         look_up_table->entries[i].us_vdd = record->us_vdd;
 166         look_up_table->entries[i].us_cac_low = record->us_cac_low;
 167         look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
 168         look_up_table->entries[i].us_cac_high = record->us_cac_high;
 169         /* Only increment the count when we're appending, not replacing duplicate entry. */
 170         if (i == look_up_table->count)
 171                 look_up_table->count++;
 172
 173         return 0;
 174 }
 175
 176 int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
 177 {
 178         PPSMC_Msg msg = has_display? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
 179
 180         return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
 181 }
 182
 183 uint8_t tonga_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
 184                 uint32_t voltage)
 185 {
 186         uint8_t count = (uint8_t) (voltage_table->count);
 187         uint8_t i = 0;
 188
 189         PP_ASSERT_WITH_CODE((NULL != voltage_table),
 190                 "Voltage Table empty.", return 0;);
 191         PP_ASSERT_WITH_CODE((0 != count),
 192                 "Voltage Table empty.", return 0;);
 193
 194         for (i = 0; i < count; i++) {
 195                 /* find first voltage bigger than requested */
 196                 if (voltage_table->entries[i].value >= voltage)
 197                         return i;
 198         }
 199
 200         /* voltage is bigger than max voltage in the table */
 201         return i - 1;
 202 }
 203
 204 /**
 205  * @brief PhwTonga_GetVoltageOrder
 206  *  Returns index of requested voltage record in lookup(table)
 207  * @param hwmgr - pointer to hardware manager
 208  * @param lookupTable - lookup list to search in
 209  * @param voltage - voltage to look for
 210  * @return 0 on success
 211  */
 212 uint8_t tonga_get_voltage_index(phm_ppt_v1_voltage_lookup_table *look_up_table,
 213                 uint16_t voltage)
 214 {
 215         uint8_t count = (uint8_t) (look_up_table->count);
 216         uint8_t i;
 217
 218         PP_ASSERT_WITH_CODE((NULL != look_up_table), "Lookup Table empty.", return 0;);
 219         PP_ASSERT_WITH_CODE((0 != count), "Lookup Table empty.", return 0;);
 220
 221         for (i = 0; i < count; i++) {
 222                 /* find first voltage equal or bigger than requested */
 223                 if (look_up_table->entries[i].us_vdd >= voltage)
 224                         return i;
 225         }
 226
 227         /* voltage is bigger than max voltage in the table */
 228         return i-1;
 229 }
 230
 231 bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr)
 232 {
 233         /*
 234          * We return the status of Voltage Control instead of checking SCLK/MCLK DPM
 235          * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
 236          * whereas voltage control is a fundemental change that will not be disabled
 237          */
 238
 239         return (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 240                                         FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) ? 1 : 0);
 241 }
 242
 243 /**
 244  * Re-generate the DPM level mask value
 245  * @param    hwmgr      the address of the hardware manager
 246  */
 247 static uint32_t tonga_get_dpm_level_enable_mask_value(
 248                         struct tonga_single_dpm_table * dpm_table)
 249 {
 250         uint32_t i;
 251         uint32_t mask_value = 0;
 252
 253         for (i = dpm_table->count; i > 0; i--) {
 254                 mask_value = mask_value << 1;
 255
 256                 if (dpm_table->dpm_levels[i-1].enabled)
 257                         mask_value |= 0x1;
 258                 else
 259                         mask_value &= 0xFFFFFFFE;
 260         }
 261         return mask_value;
 262 }
 263
 264 /**
 265  * Retrieve DPM default values from registry (if available)
 266  *
 267  * @param    hwmgr  the address of the powerplay hardware manager.
 268  */
 269 void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
 270 {
 271         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 272         phw_tonga_ulv_parm *ulv = &(data->ulv);
 273         uint32_t tmp;
 274
 275         ulv->ch_ulv_parameter = PPTONGA_CGULVPARAMETER_DFLT;
 276         data->voting_rights_clients0 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT0;
 277         data->voting_rights_clients1 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT1;
 278         data->voting_rights_clients2 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT2;
 279         data->voting_rights_clients3 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT3;
 280         data->voting_rights_clients4 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT4;
 281         data->voting_rights_clients5 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT5;
 282         data->voting_rights_clients6 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT6;
 283         data->voting_rights_clients7 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT7;
 284
 285         data->static_screen_threshold_unit = PPTONGA_STATICSCREENTHRESHOLDUNIT_DFLT;
 286         data->static_screen_threshold = PPTONGA_STATICSCREENTHRESHOLD_DFLT;
 287
 288         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 289                 PHM_PlatformCaps_ABM);
 290         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 291                 PHM_PlatformCaps_NonABMSupportInPPLib);
 292
 293         tmp = 0;
 294         if (tmp == 0)
 295                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 296                         PHM_PlatformCaps_DynamicACTiming);
 297
 298         tmp = 0;
 299         if (0 != tmp)
 300                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 301                         PHM_PlatformCaps_DisableMemoryTransition);
 302
 303         data->mclk_strobe_mode_threshold = 40000;
 304         data->mclk_stutter_mode_threshold = 30000;
 305         data->mclk_edc_enable_threshold = 40000;
 306         data->mclk_edc_wr_enable_threshold = 40000;
 307
 308         tmp = 0;
 309         if (tmp != 0)
 310                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 311                         PHM_PlatformCaps_DisableMCLS);
 312
 313         data->pcie_gen_performance.max = PP_PCIEGen1;
 314         data->pcie_gen_performance.min = PP_PCIEGen3;
 315         data->pcie_gen_power_saving.max = PP_PCIEGen1;
 316         data->pcie_gen_power_saving.min = PP_PCIEGen3;
 317
 318         data->pcie_lane_performance.max = 0;
 319         data->pcie_lane_performance.min = 16;
 320         data->pcie_lane_power_saving.max = 0;
 321         data->pcie_lane_power_saving.min = 16;
 322
 323         tmp = 0;
 324
 325         if (tmp)
 326                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 327                         PHM_PlatformCaps_SclkThrottleLowNotification);
 328
 329         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 330                 PHM_PlatformCaps_DynamicUVDState);
 331
 332 }
 333
 334 int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
 335 {
 336         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 337
 338         int result = 0;
 339         uint32_t low_sclk_interrupt_threshold = 0;
 340
 341         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 342                         PHM_PlatformCaps_SclkThrottleLowNotification)
 343                 && (hwmgr->gfx_arbiter.sclk_threshold != data->low_sclk_interrupt_threshold)) {
 344                 data->low_sclk_interrupt_threshold = hwmgr->gfx_arbiter.sclk_threshold;
 345                 low_sclk_interrupt_threshold = data->low_sclk_interrupt_threshold;
 346
 347                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
 348
 349                 result = tonga_copy_bytes_to_smc(
 350                                 hwmgr->smumgr,
 351                                 data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable,
 352                                 LowSclkInterruptThreshold),
 353                                 (uint8_t *)&low_sclk_interrupt_threshold,
 354                                 sizeof(uint32_t),
 355                                 data->sram_end
 356                                 );
 357         }
 358
 359         return result;
 360 }
 361
 362 /**
 363  * Find SCLK value that is associated with specified virtual_voltage_Id.
 364  *
 365  * @param    hwmgr  the address of the powerplay hardware manager.
 366  * @param    virtual_voltage_Id  voltageId to look for.
 367  * @param    sclk output value .
 368  * @return   always 0 if success and 2 if association not found
 369  */
 370 static int tonga_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
 371         phm_ppt_v1_voltage_lookup_table *lookup_table,
 372         uint16_t virtual_voltage_id, uint32_t *sclk)
 373 {
 374         uint8_t entryId;
 375         uint8_t voltageId;
 376         struct phm_ppt_v1_information *pptable_info =
 377                                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 378
 379         PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -1);
 380
 381         /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
 382         for (entryId = 0; entryId < pptable_info->vdd_dep_on_sclk->count; entryId++) {
 383                 voltageId = pptable_info->vdd_dep_on_sclk->entries[entryId].vddInd;
 384                 if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
 385                         break;
 386         }
 387
 388         PP_ASSERT_WITH_CODE(entryId < pptable_info->vdd_dep_on_sclk->count,
 389                         "Can't find requested voltage id in vdd_dep_on_sclk table!",
 390                         return -1;
 391                         );
 392
 393         *sclk = pptable_info->vdd_dep_on_sclk->entries[entryId].clk;
 394
 395         return 0;
 396 }
 397
 398 /**
 399  * Get Leakage VDDC based on leakage ID.
 400  *
 401  * @param    hwmgr  the address of the powerplay hardware manager.
 402  * @return   2 if vddgfx returned is greater than 2V or if BIOS
 403  */
 404 int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr)
 405 {
 406         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 407         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
 408         phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
 409         uint16_t    virtual_voltage_id;
 410         uint16_t    vddc = 0;
 411         uint16_t    vddgfx = 0;
 412         uint16_t    i, j;
 413         uint32_t  sclk = 0;
 414
 415         /* retrieve voltage for leakage ID (0xff01 + i) */
 416         for (i = 0; i < TONGA_MAX_LEAKAGE_COUNT; i++) {
 417                 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 418
 419                 /* in split mode we should have only vddgfx EVV leakages */
 420                 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
 421                         if (0 == tonga_get_sclk_for_voltage_evv(hwmgr,
 422                                                 pptable_info->vddgfx_lookup_table, virtual_voltage_id, &sclk)) {
 423                                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 424                                                         PHM_PlatformCaps_ClockStretcher)) {
 425                                         for (j = 1; j < sclk_table->count; j++) {
 426                                                 if (sclk_table->entries[j].clk == sclk &&
 427                                                                 sclk_table->entries[j].cks_enable == 0) {
 428                                                         sclk += 5000;
 429                                                         break;
 430                                                 }
 431                                         }
 432                                 }
 433                                 PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk
 434                                                 (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
 435                                                  virtual_voltage_id, &vddgfx),
 436                                                 "Error retrieving EVV voltage value!", continue);
 437
 438                                 /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
 439                                 PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -1);
 440
 441                                 /* the voltage should not be zero nor equal to leakage ID */
 442                                 if (vddgfx != 0 && vddgfx != virtual_voltage_id) {
 443                                         data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
 444                                         data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = virtual_voltage_id;
 445                                         data->vddcgfx_leakage.count++;
 446                                 }
 447                         }
 448                 } else {
 449                         /*  in merged mode we have only vddc EVV leakages */
 450                         if (0 == tonga_get_sclk_for_voltage_evv(hwmgr,
 451                                                 pptable_info->vddc_lookup_table,
 452                                                 virtual_voltage_id, &sclk)) {
 453                                 PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk
 454                                                 (hwmgr, VOLTAGE_TYPE_VDDC, sclk,
 455                                                  virtual_voltage_id, &vddc),
 456                                                 "Error retrieving EVV voltage value!", continue);
 457
 458                                 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
 459                                 if (vddc > 2000)
 460                                         printk(KERN_ERR "[ powerplay ] Invalid VDDC value! \n");
 461
 462                                 /* the voltage should not be zero nor equal to leakage ID */
 463                                 if (vddc != 0 && vddc != virtual_voltage_id) {
 464                                         data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
 465                                         data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
 466                                         data->vddc_leakage.count++;
 467                                 }
 468                         }
 469                 }
 470         }
 471
 472         return 0;
 473 }
 474
 475 int tonga_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
 476 {
 477         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 478
 479         /* enable SCLK dpm */
 480         if (0 == data->sclk_dpm_key_disabled) {
 481                 PP_ASSERT_WITH_CODE(
 482                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
 483                                                    PPSMC_MSG_DPM_Enable)),
 484                                 "Failed to enable SCLK DPM during DPM Start Function!",
 485                                 return -1);
 486         }
 487
 488         /* enable MCLK dpm */
 489         if (0 == data->mclk_dpm_key_disabled) {
 490                 PP_ASSERT_WITH_CODE(
 491                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
 492                                              PPSMC_MSG_MCLKDPM_Enable)),
 493                                 "Failed to enable MCLK DPM during DPM Start Function!",
 494                                 return -1);
 495
 496                 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
 497
 498                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 499                         ixLCAC_MC0_CNTL, 0x05);/* CH0,1 read */
 500                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 501                         ixLCAC_MC1_CNTL, 0x05);/* CH2,3 read */
 502                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 503                         ixLCAC_CPL_CNTL, 0x100005);/*Read */
 504
 505                 udelay(10);
 506
 507                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 508                         ixLCAC_MC0_CNTL, 0x400005);/* CH0,1 write */
 509                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 510                         ixLCAC_MC1_CNTL, 0x400005);/* CH2,3 write */
 511                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 512                         ixLCAC_CPL_CNTL, 0x500005);/* write */
 513
 514         }
 515
 516         return 0;
 517 }
 518
 519 int tonga_start_dpm(struct pp_hwmgr *hwmgr)
 520 {
 521         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 522
 523         /* enable general power management */
 524         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 1);
 525         /* enable sclk deep sleep */
 526         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 1);
 527
 528         /* prepare for PCIE DPM */
 529         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start +
 530                         offsetof(SMU72_SoftRegisters, VoltageChangeTimeout), 0x1000);
 531
 532         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, SWRST_COMMAND_1, RESETLC, 0x0);
 533
 534         PP_ASSERT_WITH_CODE(
 535                         (0 == smum_send_msg_to_smc(hwmgr->smumgr,
 536                                         PPSMC_MSG_Voltage_Cntl_Enable)),
 537                         "Failed to enable voltage DPM during DPM Start Function!",
 538                         return -1);
 539
 540         if (0 != tonga_enable_sclk_mclk_dpm(hwmgr)) {
 541                 PP_ASSERT_WITH_CODE(0, "Failed to enable Sclk DPM and Mclk DPM!", return -1);
 542         }
 543
 544         /* enable PCIE dpm */
 545         if (0 == data->pcie_dpm_key_disabled) {
 546                 PP_ASSERT_WITH_CODE(
 547                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
 548                                                 PPSMC_MSG_PCIeDPM_Enable)),
 549                                 "Failed to enable pcie DPM during DPM Start Function!",
 550                                 return -1
 551                                 );
 552         }
 553
 554         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 555                                 PHM_PlatformCaps_Falcon_QuickTransition)) {
 556                                    smum_send_msg_to_smc(hwmgr->smumgr,
 557                                     PPSMC_MSG_EnableACDCGPIOInterrupt);
 558         }
 559
 560         return 0;
 561 }
 562
 563 int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
 564 {
 565         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 566
 567         /* disable SCLK dpm */
 568         if (0 == data->sclk_dpm_key_disabled) {
 569                 /* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
 570                 PP_ASSERT_WITH_CODE(
 571                                 (0 == tonga_is_dpm_running(hwmgr)),
 572                                 "Trying to Disable SCLK DPM when DPM is disabled",
 573                                 return -1
 574                                 );
 575
 576                 PP_ASSERT_WITH_CODE(
 577                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
 578                                                   PPSMC_MSG_DPM_Disable)),
 579                                 "Failed to disable SCLK DPM during DPM stop Function!",
 580                                 return -1);
 581         }
 582
 583         /* disable MCLK dpm */
 584         if (0 == data->mclk_dpm_key_disabled) {
 585                 /* Checking if DPM is running.  If we discover hang because of this, we should skip this message. */
 586                 PP_ASSERT_WITH_CODE(
 587                                 (0 == tonga_is_dpm_running(hwmgr)),
 588                                 "Trying to Disable MCLK DPM when DPM is disabled",
 589                                 return -1
 590                                 );
 591
 592                 PP_ASSERT_WITH_CODE(
 593                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
 594                                             PPSMC_MSG_MCLKDPM_Disable)),
 595                                 "Failed to Disable MCLK DPM during DPM stop Function!",
 596                                 return -1);
 597         }
 598
 599         return 0;
 600 }
 601
 602 int tonga_stop_dpm(struct pp_hwmgr *hwmgr)
 603 {
 604         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 605
 606         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 0);
 607         /* disable sclk deep sleep*/
 608         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 0);
 609
 610         /* disable PCIE dpm */
 611         if (0 == data->pcie_dpm_key_disabled) {
 612                 /* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
 613                 PP_ASSERT_WITH_CODE(
 614                                 (0 == tonga_is_dpm_running(hwmgr)),
 615                                 "Trying to Disable PCIE DPM when DPM is disabled",
 616                                 return -1
 617                                 );
 618                 PP_ASSERT_WITH_CODE(
 619                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
 620                                                 PPSMC_MSG_PCIeDPM_Disable)),
 621                                 "Failed to disable pcie DPM during DPM stop Function!",
 622                                 return -1);
 623         }
 624
 625         if (0 != tonga_disable_sclk_mclk_dpm(hwmgr))
 626                 PP_ASSERT_WITH_CODE(0, "Failed to disable Sclk DPM and Mclk DPM!", return -1);
 627
 628         /* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
 629         PP_ASSERT_WITH_CODE(
 630                         (0 == tonga_is_dpm_running(hwmgr)),
 631                         "Trying to Disable Voltage CNTL when DPM is disabled",
 632                         return -1
 633                         );
 634
 635         PP_ASSERT_WITH_CODE(
 636                         (0 == smum_send_msg_to_smc(hwmgr->smumgr,
 637                                         PPSMC_MSG_Voltage_Cntl_Disable)),
 638                         "Failed to disable voltage DPM during DPM stop Function!",
 639                         return -1);
 640
 641         return 0;
 642 }
 643
 644 int tonga_enable_sclk_control(struct pp_hwmgr *hwmgr)
 645 {
 646         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, 0);
 647
 648         return 0;
 649 }
 650
 651 /**
 652  * Send a message to the SMC and return a parameter
 653  *
 654  * @param    hwmgr:  the address of the powerplay hardware manager.
 655  * @param    msg: the message to send.
 656  * @param    parameter: pointer to the received parameter
 657  * @return   The response that came from the SMC.
 658  */
 659 PPSMC_Result tonga_send_msg_to_smc_return_parameter(
 660                 struct pp_hwmgr *hwmgr,
 661                 PPSMC_Msg msg,
 662                 uint32_t *parameter)
 663 {
 664         int result;
 665
 666         result = smum_send_msg_to_smc(hwmgr->smumgr, msg);
 667
 668         if ((0 == result) && parameter) {
 669                 *parameter = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
 670         }
 671
 672         return result;
 673 }
 674
 675 /**
 676  * force DPM power State
 677  *
 678  * @param    hwmgr:  the address of the powerplay hardware manager.
 679  * @param    n     :  DPM level
 680  * @return   The response that came from the SMC.
 681  */
 682 int tonga_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n)
 683 {
 684         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 685         uint32_t level_mask = 1 << n;
 686
 687         /* Checking if DPM is running.  If we discover hang because of this, we should skip this message. */
 688         PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
 689                         "Trying to force SCLK when DPM is disabled", return -1;);
 690         if (0 == data->sclk_dpm_key_disabled)
 691                 return (0 == smum_send_msg_to_smc_with_parameter(
 692                                                              hwmgr->smumgr,
 693                      (PPSMC_Msg)(PPSMC_MSG_SCLKDPM_SetEnabledMask),
 694                                                     level_mask) ? 0 : 1);
 695
 696         return 0;
 697 }
 698
 699 /**
 700  * force DPM power State
 701  *
 702  * @param    hwmgr:  the address of the powerplay hardware manager.
 703  * @param    n     :  DPM level
 704  * @return   The response that came from the SMC.
 705  */
 706 int tonga_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n)
 707 {
 708         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 709         uint32_t level_mask = 1 << n;
 710
 711         /* Checking if DPM is running.  If we discover hang because of this, we should skip this message. */
 712         PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
 713                         "Trying to Force MCLK when DPM is disabled", return -1;);
 714         if (0 == data->mclk_dpm_key_disabled)
 715                 return (0 == smum_send_msg_to_smc_with_parameter(
 716                                                                 hwmgr->smumgr,
 717                                                                 (PPSMC_Msg)(PPSMC_MSG_MCLKDPM_SetEnabledMask),
 718                                                                 level_mask) ? 0 : 1);
 719
 720         return 0;
 721 }
 722
 723 /**
 724  * force DPM power State
 725  *
 726  * @param    hwmgr:  the address of the powerplay hardware manager.
 727  * @param    n     :  DPM level
 728  * @return   The response that came from the SMC.
 729  */
 730 int tonga_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n)
 731 {
 732         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 733
 734         /* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
 735         PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
 736                         "Trying to Force PCIE level when DPM is disabled", return -1;);
 737         if (0 == data->pcie_dpm_key_disabled)
 738                 return (0 == smum_send_msg_to_smc_with_parameter(
 739                                                              hwmgr->smumgr,
 740                            (PPSMC_Msg)(PPSMC_MSG_PCIeDPM_ForceLevel),
 741                                                                 n) ? 0 : 1);
 742
 743         return 0;
 744 }
 745
 746 /**
 747  * Set the initial state by calling SMC to switch to this state directly
 748  *
 749  * @param    hwmgr  the address of the powerplay hardware manager.
 750  * @return   always 0
 751  */
 752 int tonga_set_boot_state(struct pp_hwmgr *hwmgr)
 753 {
 754         /*
 755         * SMC only stores one state that SW will ask to switch too,
 756         * so we switch the the just uploaded one
 757         */
 758         return (0 == tonga_disable_sclk_mclk_dpm(hwmgr)) ? 0 : 1;
 759 }
 760
 761 /**
 762  * Get the location of various tables inside the FW image.
 763  *
 764  * @param    hwmgr  the address of the powerplay hardware manager.
 765  * @return   always 0
 766  */
 767 int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
 768 {
 769         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 770         struct tonga_smumgr *tonga_smu = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
 771
 772         uint32_t tmp;
 773         int result;
 774         bool error = 0;
 775
 776         result = tonga_read_smc_sram_dword(hwmgr->smumgr,
 777                                 SMU72_FIRMWARE_HEADER_LOCATION +
 778                                 offsetof(SMU72_Firmware_Header, DpmTable),
 779                                 &tmp, data->sram_end);
 780
 781         if (0 == result) {
 782                 data->dpm_table_start = tmp;
 783         }
 784
 785         error |= (0 != result);
 786
 787         result = tonga_read_smc_sram_dword(hwmgr->smumgr,
 788                                 SMU72_FIRMWARE_HEADER_LOCATION +
 789                                 offsetof(SMU72_Firmware_Header, SoftRegisters),
 790                                 &tmp, data->sram_end);
 791
 792         if (0 == result) {
 793                 data->soft_regs_start = tmp;
 794                 tonga_smu->ulSoftRegsStart = tmp;
 795         }
 796
 797         error |= (0 != result);
 798
 799
 800         result = tonga_read_smc_sram_dword(hwmgr->smumgr,
 801                                 SMU72_FIRMWARE_HEADER_LOCATION +
 802                                 offsetof(SMU72_Firmware_Header, mcRegisterTable),
 803                                 &tmp, data->sram_end);
 804
 805         if (0 == result) {
 806                 data->mc_reg_table_start = tmp;
 807         }
 808
 809         result = tonga_read_smc_sram_dword(hwmgr->smumgr,
 810                                 SMU72_FIRMWARE_HEADER_LOCATION +
 811                                 offsetof(SMU72_Firmware_Header, FanTable),
 812                                 &tmp, data->sram_end);
 813
 814         if (0 == result) {
 815                 data->fan_table_start = tmp;
 816         }
 817
 818         error |= (0 != result);
 819
 820         result = tonga_read_smc_sram_dword(hwmgr->smumgr,
 821                                 SMU72_FIRMWARE_HEADER_LOCATION +
 822                                 offsetof(SMU72_Firmware_Header, mcArbDramTimingTable),
 823                                 &tmp, data->sram_end);
 824
 825         if (0 == result) {
 826                 data->arb_table_start = tmp;
 827         }
 828
 829         error |= (0 != result);
 830
 831
 832         result = tonga_read_smc_sram_dword(hwmgr->smumgr,
 833                                 SMU72_FIRMWARE_HEADER_LOCATION +
 834                                 offsetof(SMU72_Firmware_Header, Version),
 835                                 &tmp, data->sram_end);
 836
 837         if (0 == result) {
 838                 hwmgr->microcode_version_info.SMC = tmp;
 839         }
 840
 841         error |= (0 != result);
 842
 843         return error ? 1 : 0;
 844 }
 845
 846 /**
 847  * Read clock related registers.
 848  *
 849  * @param    hwmgr  the address of the powerplay hardware manager.
 850  * @return   always 0
 851  */
 852 int tonga_read_clock_registers(struct pp_hwmgr *hwmgr)
 853 {
 854         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 855
 856         data->clock_registers.vCG_SPLL_FUNC_CNTL         =
 857                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
 858         data->clock_registers.vCG_SPLL_FUNC_CNTL_2       =
 859                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
 860         data->clock_registers.vCG_SPLL_FUNC_CNTL_3       =
 861                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
 862         data->clock_registers.vCG_SPLL_FUNC_CNTL_4       =
 863                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
 864         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM   =
 865                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
 866         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
 867                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
 868         data->clock_registers.vDLL_CNTL                  =
 869                 cgs_read_register(hwmgr->device, mmDLL_CNTL);
 870         data->clock_registers.vMCLK_PWRMGT_CNTL          =
 871                 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
 872         data->clock_registers.vMPLL_AD_FUNC_CNTL         =
 873                 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
 874         data->clock_registers.vMPLL_DQ_FUNC_CNTL         =
 875                 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
 876         data->clock_registers.vMPLL_FUNC_CNTL            =
 877                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
 878         data->clock_registers.vMPLL_FUNC_CNTL_1          =
 879                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
 880         data->clock_registers.vMPLL_FUNC_CNTL_2          =
 881                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
 882         data->clock_registers.vMPLL_SS1                  =
 883                 cgs_read_register(hwmgr->device, mmMPLL_SS1);
 884         data->clock_registers.vMPLL_SS2                  =
 885                 cgs_read_register(hwmgr->device, mmMPLL_SS2);
 886
 887         return 0;
 888 }
 889
 890 /**
 891  * Find out if memory is GDDR5.
 892  *
 893  * @param    hwmgr  the address of the powerplay hardware manager.
 894  * @return   always 0
 895  */
 896 int tonga_get_memory_type(struct pp_hwmgr *hwmgr)
 897 {
 898         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 899         uint32_t temp;
 900
 901         temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
 902
 903         data->is_memory_GDDR5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
 904                         ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
 905                          MC_SEQ_MISC0_GDDR5_SHIFT));
 906
 907         return 0;
 908 }
 909
 910 /**
 911  * Enables Dynamic Power Management by SMC
 912  *
 913  * @param    hwmgr  the address of the powerplay hardware manager.
 914  * @return   always 0
 915  */
 916 int tonga_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
 917 {
 918         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, STATIC_PM_EN, 1);
 919
 920         return 0;
 921 }
 922
 923 /**
 924  * Initialize PowerGating States for different engines
 925  *
 926  * @param    hwmgr  the address of the powerplay hardware manager.
 927  * @return   always 0
 928  */
 929 int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr)
 930 {
 931         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 932
 933         data->uvd_power_gated = 0;
 934         data->vce_power_gated = 0;
 935         data->samu_power_gated = 0;
 936         data->acp_power_gated = 0;
 937         data->pg_acp_init = 1;
 938
 939         return 0;
 940 }
 941
 942 /**
 943  * Checks if DPM is enabled
 944  *
 945  * @param    hwmgr  the address of the powerplay hardware manager.
 946  * @return   always 0
 947  */
 948 int tonga_check_for_dpm_running(struct pp_hwmgr *hwmgr)
 949 {
 950         /*
 951          * We return the status of Voltage Control instead of checking SCLK/MCLK DPM
 952          * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
 953          * whereas voltage control is a fundemental change that will not be disabled
 954          */
 955         return (0 == tonga_is_dpm_running(hwmgr) ? 0 : 1);
 956 }
 957
 958 /**
 959  * Checks if DPM is stopped
 960  *
 961  * @param    hwmgr  the address of the powerplay hardware manager.
 962  * @return   always 0
 963  */
 964 int tonga_check_for_dpm_stopped(struct pp_hwmgr *hwmgr)
 965 {
 966         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 967
 968         if (0 != tonga_is_dpm_running(hwmgr)) {
 969                 /* If HW Virtualization is enabled, dpm_table_start will not have a valid value */
 970                 if (!data->dpm_table_start) {
 971                         return 1;
 972                 }
 973         }
 974
 975         return 0;
 976 }
 977
 978 /**
 979  * Remove repeated voltage values and create table with unique values.
 980  *
 981  * @param    hwmgr  the address of the powerplay hardware manager.
 982  * @param    voltage_table  the pointer to changing voltage table
 983  * @return    1 in success
 984  */
 985
 986 static int tonga_trim_voltage_table(struct pp_hwmgr *hwmgr,
 987                         pp_atomctrl_voltage_table *voltage_table)
 988 {
 989         uint32_t table_size, i, j;
 990         uint16_t vvalue;
 991         bool bVoltageFound = 0;
 992         pp_atomctrl_voltage_table *table;
 993
 994         PP_ASSERT_WITH_CODE((NULL != voltage_table), "Voltage Table empty.", return -1;);
 995         table_size = sizeof(pp_atomctrl_voltage_table);
 996         table = kzalloc(table_size, GFP_KERNEL);
 997
 998         if (NULL == table)
 999                 return -ENOMEM;
1000
1001         memset(table, 0x00, table_size);
1002         table->mask_low = voltage_table->mask_low;
1003         table->phase_delay = voltage_table->phase_delay;
1004
1005         for (i = 0; i < voltage_table->count; i++) {
1006                 vvalue = voltage_table->entries[i].value;
1007                 bVoltageFound = 0;
1008
1009                 for (j = 0; j < table->count; j++) {
1010                         if (vvalue == table->entries[j].value) {
1011                                 bVoltageFound = 1;
1012                                 break;
1013                         }
1014                 }
1015
1016                 if (!bVoltageFound) {
1017                         table->entries[table->count].value = vvalue;
1018                         table->entries[table->count].smio_low =
1019                                 voltage_table->entries[i].smio_low;
1020                         table->count++;
1021                 }
1022         }
1023
1024         memcpy(table, voltage_table, sizeof(pp_atomctrl_voltage_table));
1025
1026         kfree(table);
1027
1028         return 0;
1029 }
1030
1031 static int tonga_get_svi2_vdd_ci_voltage_table(
1032                 struct pp_hwmgr *hwmgr,
1033                 phm_ppt_v1_clock_voltage_dependency_table *voltage_dependency_table)
1034 {
1035         uint32_t i;
1036         int result;
1037         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1038         pp_atomctrl_voltage_table *vddci_voltage_table = &(data->vddci_voltage_table);
1039
1040         PP_ASSERT_WITH_CODE((0 != voltage_dependency_table->count),
1041                         "Voltage Dependency Table empty.", return -1;);
1042
1043         vddci_voltage_table->mask_low = 0;
1044         vddci_voltage_table->phase_delay = 0;
1045         vddci_voltage_table->count = voltage_dependency_table->count;
1046
1047         for (i = 0; i < voltage_dependency_table->count; i++) {
1048                 vddci_voltage_table->entries[i].value =
1049                         voltage_dependency_table->entries[i].vddci;
1050                 vddci_voltage_table->entries[i].smio_low = 0;
1051         }
1052
1053         result = tonga_trim_voltage_table(hwmgr, vddci_voltage_table);
1054         PP_ASSERT_WITH_CODE((0 == result),
1055                         "Failed to trim VDDCI table.", return result;);
1056
1057         return 0;
1058 }
1059
1060
1061
1062 static int tonga_get_svi2_vdd_voltage_table(
1063                 struct pp_hwmgr *hwmgr,
1064                 phm_ppt_v1_voltage_lookup_table *look_up_table,
1065                 pp_atomctrl_voltage_table *voltage_table)
1066 {
1067         uint8_t i = 0;
1068
1069         PP_ASSERT_WITH_CODE((0 != look_up_table->count),
1070                         "Voltage Lookup Table empty.", return -1;);
1071
1072         voltage_table->mask_low = 0;
1073         voltage_table->phase_delay = 0;
1074
1075         voltage_table->count = look_up_table->count;
1076
1077         for (i = 0; i < voltage_table->count; i++) {
1078                 voltage_table->entries[i].value = look_up_table->entries[i].us_vdd;
1079                 voltage_table->entries[i].smio_low = 0;
1080         }
1081
1082         return 0;
1083 }
1084
1085 /*
1086  * -------------------------------------------------------- Voltage Tables --------------------------------------------------------------------------
1087  * If the voltage table would be bigger than what will fit into the state table on the SMC keep only the higher entries.
1088  */
1089
1090 static void tonga_trim_voltage_table_to_fit_state_table(
1091                 struct pp_hwmgr *hwmgr,
1092                 uint32_t max_voltage_steps,
1093                 pp_atomctrl_voltage_table *voltage_table)
1094 {
1095         unsigned int i, diff;
1096
1097         if (voltage_table->count <= max_voltage_steps) {
1098                 return;
1099         }
1100
1101         diff = voltage_table->count - max_voltage_steps;
1102
1103         for (i = 0; i < max_voltage_steps; i++) {
1104                 voltage_table->entries[i] = voltage_table->entries[i + diff];
1105         }
1106
1107         voltage_table->count = max_voltage_steps;
1108
1109         return;
1110 }
1111
1112 /**
1113  * Create Voltage Tables.
1114  *
1115  * @param    hwmgr  the address of the powerplay hardware manager.
1116  * @return   always 0
1117  */
1118 int tonga_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1119 {
1120         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1121         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1122         int result;
1123
1124         /* MVDD has only GPIO voltage control */
1125         if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1126                 result = atomctrl_get_voltage_table_v3(hwmgr,
1127                                         VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, &(data->mvdd_voltage_table));
1128                 PP_ASSERT_WITH_CODE((0 == result),
1129                         "Failed to retrieve MVDD table.", return result;);
1130         }
1131
1132         if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1133                 /* GPIO voltage */
1134                 result = atomctrl_get_voltage_table_v3(hwmgr,
1135                                         VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, &(data->vddci_voltage_table));
1136                 PP_ASSERT_WITH_CODE((0 == result),
1137                         "Failed to retrieve VDDCI table.", return result;);
1138         } else if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1139                 /* SVI2 voltage */
1140                 result = tonga_get_svi2_vdd_ci_voltage_table(hwmgr,
1141                                         pptable_info->vdd_dep_on_mclk);
1142                 PP_ASSERT_WITH_CODE((0 == result),
1143                         "Failed to retrieve SVI2 VDDCI table from dependancy table.", return result;);
1144         }
1145
1146         if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1147                 /* VDDGFX has only SVI2 voltage control */
1148                 result = tonga_get_svi2_vdd_voltage_table(hwmgr,
1149                                         pptable_info->vddgfx_lookup_table, &(data->vddgfx_voltage_table));
1150                 PP_ASSERT_WITH_CODE((0 == result),
1151                         "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
1152         }
1153
1154         if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1155                 /* VDDC has only SVI2 voltage control */
1156                 result = tonga_get_svi2_vdd_voltage_table(hwmgr,
1157                                         pptable_info->vddc_lookup_table, &(data->vddc_voltage_table));
1158                 PP_ASSERT_WITH_CODE((0 == result),
1159                         "Failed to retrieve SVI2 VDDC table from lookup table.", return result;);
1160         }
1161
1162         PP_ASSERT_WITH_CODE(
1163                         (data->vddc_voltage_table.count <= (SMU72_MAX_LEVELS_VDDC)),
1164                         "Too many voltage values for VDDC. Trimming to fit state table.",
1165                         tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1166                         SMU72_MAX_LEVELS_VDDC, &(data->vddc_voltage_table));
1167                         );
1168
1169         PP_ASSERT_WITH_CODE(
1170                         (data->vddgfx_voltage_table.count <= (SMU72_MAX_LEVELS_VDDGFX)),
1171                         "Too many voltage values for VDDGFX. Trimming to fit state table.",
1172                         tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1173                         SMU72_MAX_LEVELS_VDDGFX, &(data->vddgfx_voltage_table));
1174                         );
1175
1176         PP_ASSERT_WITH_CODE(
1177                         (data->vddci_voltage_table.count <= (SMU72_MAX_LEVELS_VDDCI)),
1178                         "Too many voltage values for VDDCI. Trimming to fit state table.",
1179                         tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1180                         SMU72_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table));
1181                         );
1182
1183         PP_ASSERT_WITH_CODE(
1184                         (data->mvdd_voltage_table.count <= (SMU72_MAX_LEVELS_MVDD)),
1185                         "Too many voltage values for MVDD. Trimming to fit state table.",
1186                         tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1187                         SMU72_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table));
1188                         );
1189
1190         return 0;
1191 }
1192
1193 /**
1194  * Vddc table preparation for SMC.
1195  *
1196  * @param    hwmgr      the address of the hardware manager
1197  * @param    table     the SMC DPM table structure to be populated
1198  * @return   always 0
1199  */
1200 static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
1201                         SMU72_Discrete_DpmTable *table)
1202 {
1203         unsigned int count;
1204         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1205
1206         if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1207                 table->VddcLevelCount = data->vddc_voltage_table.count;
1208                 for (count = 0; count < table->VddcLevelCount; count++) {
1209                         table->VddcTable[count] =
1210                                 PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[count].value * VOLTAGE_SCALE);
1211                 }
1212                 CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
1213         }
1214         return 0;
1215 }
1216
1217 /**
1218  * VddGfx table preparation for SMC.
1219  *
1220  * @param    hwmgr      the address of the hardware manager
1221  * @param    table     the SMC DPM table structure to be populated
1222  * @return   always 0
1223  */
1224 static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr,
1225                         SMU72_Discrete_DpmTable *table)
1226 {
1227         unsigned int count;
1228         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1229
1230         if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1231                 table->VddGfxLevelCount = data->vddgfx_voltage_table.count;
1232                 for (count = 0; count < data->vddgfx_voltage_table.count; count++) {
1233                         table->VddGfxTable[count] =
1234                                 PP_HOST_TO_SMC_US(data->vddgfx_voltage_table.entries[count].value * VOLTAGE_SCALE);
1235                 }
1236                 CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount);
1237         }
1238         return 0;
1239 }
1240
1241 /**
1242  * Vddci table preparation for SMC.
1243  *
1244  * @param    *hwmgr The address of the hardware manager.
1245  * @param    *table The SMC DPM table structure to be populated.
1246  * @return   0
1247  */
1248 static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
1249                         SMU72_Discrete_DpmTable *table)
1250 {
1251         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1252         uint32_t count;
1253
1254         table->VddciLevelCount = data->vddci_voltage_table.count;
1255         for (count = 0; count < table->VddciLevelCount; count++) {
1256                 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1257                         table->VddciTable[count] =
1258                                 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1259                 } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1260                         table->SmioTable1.Pattern[count].Voltage =
1261                                 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1262                         /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level. */
1263                         table->SmioTable1.Pattern[count].Smio =
1264                                 (uint8_t) count;
1265                         table->Smio[count] |=
1266                                 data->vddci_voltage_table.entries[count].smio_low;
1267                         table->VddciTable[count] =
1268                                 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1269                 }
1270         }
1271
1272         table->SmioMask1 = data->vddci_voltage_table.mask_low;
1273         CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
1274
1275         return 0;
1276 }
1277
1278 /**
1279  * Mvdd table preparation for SMC.
1280  *
1281  * @param    *hwmgr The address of the hardware manager.
1282  * @param    *table The SMC DPM table structure to be populated.
1283  * @return   0
1284  */
1285 static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
1286                         SMU72_Discrete_DpmTable *table)
1287 {
1288         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1289         uint32_t count;
1290
1291         if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1292                 table->MvddLevelCount = data->mvdd_voltage_table.count;
1293                 for (count = 0; count < table->MvddLevelCount; count++) {
1294                         table->SmioTable2.Pattern[count].Voltage =
1295                                 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
1296                         /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
1297                         table->SmioTable2.Pattern[count].Smio =
1298                                 (uint8_t) count;
1299                         table->Smio[count] |=
1300                                 data->mvdd_voltage_table.entries[count].smio_low;
1301                 }
1302                 table->SmioMask2 = data->vddci_voltage_table.mask_low;
1303
1304                 CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
1305         }
1306
1307         return 0;
1308 }
1309
1310 /**
1311  * Convert a voltage value in mv unit to VID number required by SMU firmware
1312  */
1313 static uint8_t convert_to_vid(uint16_t vddc)
1314 {
1315         return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
1316 }
1317
1318
1319 /**
1320  * Preparation of vddc and vddgfx CAC tables for SMC.
1321  *
1322  * @param    hwmgr      the address of the hardware manager
1323  * @param    table     the SMC DPM table structure to be populated
1324  * @return   always 0
1325  */
1326 static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr,
1327                         SMU72_Discrete_DpmTable *table)
1328 {
1329         uint32_t count;
1330         uint8_t index;
1331         int result = 0;
1332         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1333         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1334         struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table = pptable_info->vddgfx_lookup_table;
1335         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table = pptable_info->vddc_lookup_table;
1336
1337         /* pTables is already swapped, so in order to use the value from it, we need to swap it back. */
1338         uint32_t vddcLevelCount = PP_SMC_TO_HOST_UL(table->VddcLevelCount);
1339         uint32_t vddgfxLevelCount = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount);
1340
1341         for (count = 0; count < vddcLevelCount; count++) {
1342                 /* We are populating vddc CAC data to BapmVddc table in split and merged mode */
1343                 index = tonga_get_voltage_index(vddc_lookup_table,
1344                         data->vddc_voltage_table.entries[count].value);
1345                 table->BapmVddcVidLoSidd[count] =
1346                         convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
1347                 table->BapmVddcVidHiSidd[count] =
1348                         convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
1349                 table->BapmVddcVidHiSidd2[count] =
1350                         convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
1351         }
1352
1353         if ((data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2)) {
1354                 /* We are populating vddgfx CAC data to BapmVddgfx table in split mode */
1355                 for (count = 0; count < vddgfxLevelCount; count++) {
1356                         index = tonga_get_voltage_index(vddgfx_lookup_table,
1357                                 data->vddgfx_voltage_table.entries[count].value);
1358                         table->BapmVddGfxVidLoSidd[count] =
1359                                 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_low);
1360                         table->BapmVddGfxVidHiSidd[count] =
1361                                 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_mid);
1362                         table->BapmVddGfxVidHiSidd2[count] =
1363                                 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_high);
1364                 }
1365         } else {
1366                 for (count = 0; count < vddcLevelCount; count++) {
1367                         index = tonga_get_voltage_index(vddc_lookup_table,
1368                                 data->vddc_voltage_table.entries[count].value);
1369                         table->BapmVddGfxVidLoSidd[count] =
1370                                 convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
1371                         table->BapmVddGfxVidHiSidd[count] =
1372                                 convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
1373                         table->BapmVddGfxVidHiSidd2[count] =
1374                                 convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
1375                 }
1376         }
1377
1378         return result;
1379 }
1380
1381
1382 /**
1383  * Preparation of voltage tables for SMC.
1384  *
1385  * @param    hwmgr      the address of the hardware manager
1386  * @param    table     the SMC DPM table structure to be populated
1387  * @return   always 0
1388  */
1389
1390 int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
1391         SMU72_Discrete_DpmTable *table)
1392 {
1393         int result;
1394
1395         result = tonga_populate_smc_vddc_table(hwmgr, table);
1396         PP_ASSERT_WITH_CODE(0 == result,
1397                         "can not populate VDDC voltage table to SMC", return -1);
1398
1399         result = tonga_populate_smc_vdd_ci_table(hwmgr, table);
1400         PP_ASSERT_WITH_CODE(0 == result,
1401                         "can not populate VDDCI voltage table to SMC", return -1);
1402
1403         result = tonga_populate_smc_vdd_gfx_table(hwmgr, table);
1404         PP_ASSERT_WITH_CODE(0 == result,
1405                         "can not populate VDDGFX voltage table to SMC", return -1);
1406
1407         result = tonga_populate_smc_mvdd_table(hwmgr, table);
1408         PP_ASSERT_WITH_CODE(0 == result,
1409                         "can not populate MVDD voltage table to SMC", return -1);
1410
1411         result = tonga_populate_cac_tables(hwmgr, table);
1412         PP_ASSERT_WITH_CODE(0 == result,
1413                         "can not populate CAC voltage tables to SMC", return -1);
1414
1415         return 0;
1416 }
1417
1418 /**
1419  * Populates the SMC VRConfig field in DPM table.
1420  *
1421  * @param    hwmgr      the address of the hardware manager
1422  * @param    table     the SMC DPM table structure to be populated
1423  * @return   always 0
1424  */
1425 static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
1426                         SMU72_Discrete_DpmTable *table)
1427 {
1428         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1429         uint16_t config;
1430
1431         if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1432                 /*  Splitted mode */
1433                 config = VR_SVI2_PLANE_1;
1434                 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1435
1436                 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1437                         config = VR_SVI2_PLANE_2;
1438                         table->VRConfig |= config;
1439                 } else {
1440                         printk(KERN_ERR "[ powerplay ] VDDC and VDDGFX should be both on SVI2 control in splitted mode! \n");
1441                 }
1442         } else {
1443                 /* Merged mode  */
1444                 config = VR_MERGED_WITH_VDDC;
1445                 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1446
1447                 /* Set Vddc Voltage Controller  */
1448                 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1449                         config = VR_SVI2_PLANE_1;
1450                         table->VRConfig |= config;
1451                 } else {
1452                         printk(KERN_ERR "[ powerplay ] VDDC should be on SVI2 control in merged mode! \n");
1453                 }
1454         }
1455
1456         /* Set Vddci Voltage Controller  */
1457         if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1458                 config = VR_SVI2_PLANE_2;  /* only in merged mode */
1459                 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1460         } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1461                 config = VR_SMIO_PATTERN_1;
1462                 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1463         }
1464
1465         /* Set Mvdd Voltage Controller */
1466         if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1467                 config = VR_SMIO_PATTERN_2;
1468                 table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);
1469         }
1470
1471         return 0;
1472 }
1473
1474 static int tonga_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr,
1475         phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table,
1476         uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1477 {
1478         uint32_t i = 0;
1479         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1480         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1481
1482         /* clock - voltage dependency table is empty table */
1483         if (allowed_clock_voltage_table->count == 0)
1484                 return -1;
1485
1486         for (i = 0; i < allowed_clock_voltage_table->count; i++) {
1487                 /* find first sclk bigger than request */
1488                 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
1489                         voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1490                                                                 allowed_clock_voltage_table->entries[i].vddgfx);
1491
1492                         voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1493                                                                 allowed_clock_voltage_table->entries[i].vddc);
1494
1495                         if (allowed_clock_voltage_table->entries[i].vddci) {
1496                                 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1497                                                                         allowed_clock_voltage_table->entries[i].vddci);
1498                         } else {
1499                                 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1500                                                                         allowed_clock_voltage_table->entries[i].vddc - data->vddc_vddci_delta);
1501                         }
1502
1503                         if (allowed_clock_voltage_table->entries[i].mvdd) {
1504                                 *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd;
1505                         }
1506
1507                         voltage->Phases = 1;
1508                         return 0;
1509                 }
1510         }
1511
1512         /* sclk is bigger than max sclk in the dependence table */
1513         voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1514                 allowed_clock_voltage_table->entries[i-1].vddgfx);
1515         voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1516                 allowed_clock_voltage_table->entries[i-1].vddc);
1517
1518         if (allowed_clock_voltage_table->entries[i-1].vddci) {
1519                 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1520                         allowed_clock_voltage_table->entries[i-1].vddci);
1521         }
1522         if (allowed_clock_voltage_table->entries[i-1].mvdd) {
1523                 *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd;
1524         }
1525
1526         return 0;
1527 }
1528
1529 /**
1530  * Call SMC to reset S0/S1 to S1 and Reset SMIO to initial value
1531  *
1532  * @param    hwmgr  the address of the powerplay hardware manager.
1533  * @return   always 0
1534  */
1535 int tonga_reset_to_default(struct pp_hwmgr *hwmgr)
1536 {
1537         return (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults) == 0) ? 0 : 1;
1538 }
1539
1540 int tonga_populate_memory_timing_parameters(
1541                 struct pp_hwmgr *hwmgr,
1542                 uint32_t engine_clock,
1543                 uint32_t memory_clock,
1544                 struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs
1545                 )
1546 {
1547         uint32_t dramTiming;
1548         uint32_t dramTiming2;
1549         uint32_t burstTime;
1550         int result;
1551
1552         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1553                                 engine_clock, memory_clock);
1554
1555         PP_ASSERT_WITH_CODE(result == 0,
1556                 "Error calling VBIOS to set DRAM_TIMING.", return result);
1557
1558         dramTiming  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1559         dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1560         burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1561
1562         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dramTiming);
1563         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
1564         arb_regs->McArbBurstTime = (uint8_t)burstTime;
1565
1566         return 0;
1567 }
1568
1569 /**
1570  * Setup parameters for the MC ARB.
1571  *
1572  * @param    hwmgr  the address of the powerplay hardware manager.
1573  * @return   always 0
1574  * This function is to be called from the SetPowerState table.
1575  */
1576 int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1577 {
1578         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1579         int result = 0;
1580         SMU72_Discrete_MCArbDramTimingTable  arb_regs;
1581         uint32_t i, j;
1582
1583         memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable));
1584
1585         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1586                 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1587                         result = tonga_populate_memory_timing_parameters
1588                                 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
1589                                  data->dpm_table.mclk_table.dpm_levels[j].value,
1590                                  &arb_regs.entries[i][j]);
1591
1592                         if (0 != result) {
1593                                 break;
1594                         }
1595                 }
1596         }
1597
1598         if (0 == result) {
1599                 result = tonga_copy_bytes_to_smc(
1600                                 hwmgr->smumgr,
1601                                 data->arb_table_start,
1602                                 (uint8_t *)&arb_regs,
1603                                 sizeof(SMU72_Discrete_MCArbDramTimingTable),
1604                                 data->sram_end
1605                                 );
1606         }
1607
1608         return result;
1609 }
1610
1611 static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table)
1612 {
1613         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1614         struct tonga_dpm_table *dpm_table = &data->dpm_table;
1615         uint32_t i;
1616
1617         /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
1618         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1619                 table->LinkLevel[i].PcieGenSpeed  =
1620                         (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1621                 table->LinkLevel[i].PcieLaneCount =
1622                         (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
1623                 table->LinkLevel[i].EnabledForActivity =
1624                         1;
1625                 table->LinkLevel[i].SPC =
1626                         (uint8_t)(data->pcie_spc_cap & 0xff);
1627                 table->LinkLevel[i].DownThreshold =
1628                         PP_HOST_TO_SMC_UL(5);
1629                 table->LinkLevel[i].UpThreshold =
1630                         PP_HOST_TO_SMC_UL(30);
1631         }
1632
1633         data->smc_state_table.LinkLevelCount =
1634                 (uint8_t)dpm_table->pcie_speed_table.count;
1635         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1636                 tonga_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1637
1638         return 0;
1639 }
1640
1641
1642 static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1643                 SMU72_Discrete_DpmTable *table)
1644 {
1645         int result = 0;
1646
1647         uint8_t count;
1648         pp_atomctrl_clock_dividers_vi dividers;
1649         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1650         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1651         phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1652
1653         table->VceLevelCount = (uint8_t) (mm_table->count);
1654         table->VceBootLevel = 0;
1655
1656         for (count = 0; count < table->VceLevelCount; count++) {
1657                 table->VceLevel[count].Frequency =
1658                         mm_table->entries[count].eclk;
1659                 table->VceLevel[count].MinVoltage.Vddc =
1660                         tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1661                                 mm_table->entries[count].vddc);
1662                 table->VceLevel[count].MinVoltage.VddGfx =
1663                         (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1664                         tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1665                                 mm_table->entries[count].vddgfx) : 0;
1666                 table->VceLevel[count].MinVoltage.Vddci =
1667                         tonga_get_voltage_id(&data->vddci_voltage_table,
1668                                 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1669                 table->VceLevel[count].MinVoltage.Phases = 1;
1670
1671                 /* retrieve divider value for VBIOS */
1672                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1673                                         table->VceLevel[count].Frequency, &dividers);
1674                 PP_ASSERT_WITH_CODE((0 == result),
1675                                 "can not find divide id for VCE engine clock", return result);
1676
1677                 table->VceLevel[count].Divider    = (uint8_t)dividers.pll_post_divider;
1678
1679                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1680         }
1681
1682         return result;
1683 }
1684
1685 static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
1686                 SMU72_Discrete_DpmTable *table)
1687 {
1688         int result = 0;
1689         uint8_t count;
1690         pp_atomctrl_clock_dividers_vi dividers;
1691         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1692         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1693         phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1694
1695         table->AcpLevelCount = (uint8_t) (mm_table->count);
1696         table->AcpBootLevel = 0;
1697
1698         for (count = 0; count < table->AcpLevelCount; count++) {
1699                 table->AcpLevel[count].Frequency =
1700                         pptable_info->mm_dep_table->entries[count].aclk;
1701                 table->AcpLevel[count].MinVoltage.Vddc =
1702                         tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1703                         mm_table->entries[count].vddc);
1704                 table->AcpLevel[count].MinVoltage.VddGfx =
1705                         (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1706                         tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1707                                 mm_table->entries[count].vddgfx) : 0;
1708                 table->AcpLevel[count].MinVoltage.Vddci =
1709                         tonga_get_voltage_id(&data->vddci_voltage_table,
1710                                 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1711                 table->AcpLevel[count].MinVoltage.Phases = 1;
1712
1713                 /* retrieve divider value for VBIOS */
1714                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1715                         table->AcpLevel[count].Frequency, &dividers);
1716                 PP_ASSERT_WITH_CODE((0 == result),
1717                         "can not find divide id for engine clock", return result);
1718
1719                 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1720
1721                 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
1722         }
1723
1724         return result;
1725 }
1726
1727 static int tonga_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1728         SMU72_Discrete_DpmTable *table)
1729 {
1730         int result = 0;
1731         uint8_t count;
1732         pp_atomctrl_clock_dividers_vi dividers;
1733         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1734         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1735         phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1736
1737         table->SamuBootLevel = 0;
1738         table->SamuLevelCount = (uint8_t) (mm_table->count);
1739
1740         for (count = 0; count < table->SamuLevelCount; count++) {
1741                 /* not sure whether we need evclk or not */
1742                 table->SamuLevel[count].Frequency =
1743                         pptable_info->mm_dep_table->entries[count].samclock;
1744                 table->SamuLevel[count].MinVoltage.Vddc =
1745                         tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1746                                 mm_table->entries[count].vddc);
1747                 table->SamuLevel[count].MinVoltage.VddGfx =
1748                         (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1749                         tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1750                                 mm_table->entries[count].vddgfx) : 0;
1751                 table->SamuLevel[count].MinVoltage.Vddci =
1752                         tonga_get_voltage_id(&data->vddci_voltage_table,
1753                                 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1754                 table->SamuLevel[count].MinVoltage.Phases = 1;
1755
1756                 /* retrieve divider value for VBIOS */
1757                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1758                                         table->SamuLevel[count].Frequency, &dividers);
1759                 PP_ASSERT_WITH_CODE((0 == result),
1760                         "can not find divide id for samu clock", return result);
1761
1762                 table->SamuLevel[count].Divider     = (uint8_t)dividers.pll_post_divider;
1763
1764                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1765         }
1766
1767         return result;
1768 }
1769
1770 /**
1771  * Populates the SMC MCLK structure using the provided memory clock
1772  *
1773  * @param    hwmgr      the address of the hardware manager
1774  * @param    memory_clock the memory clock to use to populate the structure
1775  * @param    sclk        the SMC SCLK structure to be populated
1776  */
1777 static int tonga_calculate_mclk_params(
1778                 struct pp_hwmgr *hwmgr,
1779                 uint32_t memory_clock,
1780                 SMU72_Discrete_MemoryLevel *mclk,
1781                 bool strobe_mode,
1782                 bool dllStateOn
1783                 )
1784 {
1785         const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1786         uint32_t  dll_cntl = data->clock_registers.vDLL_CNTL;
1787         uint32_t  mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
1788         uint32_t  mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
1789         uint32_t  mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
1790         uint32_t  mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
1791         uint32_t  mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
1792         uint32_t  mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
1793         uint32_t  mpll_ss1 = data->clock_registers.vMPLL_SS1;
1794         uint32_t  mpll_ss2 = data->clock_registers.vMPLL_SS2;
1795
1796         pp_atomctrl_memory_clock_param mpll_param;
1797         int result;
1798
1799         result = atomctrl_get_memory_pll_dividers_si(hwmgr,
1800                                 memory_clock, &mpll_param, strobe_mode);
1801         PP_ASSERT_WITH_CODE(0 == result,
1802                 "Error retrieving Memory Clock Parameters from VBIOS.", return result);
1803
1804         /* MPLL_FUNC_CNTL setup*/
1805         mpll_func_cntl    = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
1806
1807         /* MPLL_FUNC_CNTL_1 setup*/
1808         mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
1809                                                         MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
1810         mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
1811                                                         MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
1812         mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
1813                                                         MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
1814
1815         /* MPLL_AD_FUNC_CNTL setup*/
1816         mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
1817                                                         MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1818
1819         if (data->is_memory_GDDR5) {
1820                 /* MPLL_DQ_FUNC_CNTL setup*/
1821                 mpll_dq_func_cntl  = PHM_SET_FIELD(mpll_dq_func_cntl,
1822                                                                 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
1823                 mpll_dq_func_cntl  = PHM_SET_FIELD(mpll_dq_func_cntl,
1824                                                                 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1825         }
1826
1827         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1828                         PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
1829                 /*
1830                  ************************************
1831                  Fref = Reference Frequency
1832                  NF = Feedback divider ratio
1833                  NR = Reference divider ratio
1834                  Fnom = Nominal VCO output frequency = Fref * NF / NR
1835                  Fs = Spreading Rate
1836                  D = Percentage down-spread / 2
1837                  Fint = Reference input frequency to PFD = Fref / NR
1838                  NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
1839                  CLKS = NS - 1 = ISS_STEP_NUM[11:0]
1840                  NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
1841                  CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
1842                  *************************************
1843                  */
1844                 pp_atomctrl_internal_ss_info ss_info;
1845                 uint32_t freq_nom;
1846                 uint32_t tmp;
1847                 uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
1848
1849                 /* for GDDR5 for all modes and DDR3 */
1850                 if (1 == mpll_param.qdr)
1851                         freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
1852                 else
1853                         freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
1854
1855                 /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2  Note: S.I. reference_divider = 1*/
1856                 tmp = (freq_nom / reference_clock);
1857                 tmp = tmp * tmp;
1858
1859                 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
1860                         /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
1861                         /* ss.Info.speed_spectrum_rate -- in unit of khz */
1862                         /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
1863                         /*     = reference_clock * 5 / speed_spectrum_rate */
1864                         uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
1865
1866                         /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
1867                         /*     = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
1868                         uint32_t clkv =
1869                                 (uint32_t)((((131 * ss_info.speed_spectrum_percentage *
1870                                                         ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
1871
1872                         mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
1873                         mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
1874                 }
1875         }
1876
1877         /* MCLK_PWRMGT_CNTL setup */
1878         mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1879                 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
1880         mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1881                 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
1882         mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1883                 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
1884
1885
1886         /* Save the result data to outpupt memory level structure */
1887         mclk->MclkFrequency   = memory_clock;
1888         mclk->MpllFuncCntl    = mpll_func_cntl;
1889         mclk->MpllFuncCntl_1  = mpll_func_cntl_1;
1890         mclk->MpllFuncCntl_2  = mpll_func_cntl_2;
1891         mclk->MpllAdFuncCntl  = mpll_ad_func_cntl;
1892         mclk->MpllDqFuncCntl  = mpll_dq_func_cntl;
1893         mclk->MclkPwrmgtCntl  = mclk_pwrmgt_cntl;
1894         mclk->DllCntl         = dll_cntl;
1895         mclk->MpllSs1         = mpll_ss1;
1896         mclk->MpllSs2         = mpll_ss2;
1897
1898         return 0;
1899 }
1900
1901 static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock,
1902                 bool strobe_mode)
1903 {
1904         uint8_t mc_para_index;
1905
1906         if (strobe_mode) {
1907                 if (memory_clock < 12500) {
1908                         mc_para_index = 0x00;
1909                 } else if (memory_clock > 47500) {
1910                         mc_para_index = 0x0f;
1911                 } else {
1912                         mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
1913                 }
1914         } else {
1915                 if (memory_clock < 65000) {
1916                         mc_para_index = 0x00;
1917                 } else if (memory_clock > 135000) {
1918                         mc_para_index = 0x0f;
1919                 } else {
1920                         mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
1921                 }
1922         }
1923
1924         return mc_para_index;
1925 }
1926
1927 static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
1928 {
1929         uint8_t mc_para_index;
1930
1931         if (memory_clock < 10000) {
1932                 mc_para_index = 0;
1933         } else if (memory_clock >= 80000) {
1934                 mc_para_index = 0x0f;
1935         } else {
1936                 mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
1937         }
1938
1939         return mc_para_index;
1940 }
1941
1942 static int tonga_populate_single_memory_level(
1943                 struct pp_hwmgr *hwmgr,
1944                 uint32_t memory_clock,
1945                 SMU72_Discrete_MemoryLevel *memory_level
1946                 )
1947 {
1948         uint32_t minMvdd = 0;
1949         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1950         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1951         int result = 0;
1952         bool dllStateOn;
1953         struct cgs_display_info info = {0};
1954
1955
1956         if (NULL != pptable_info->vdd_dep_on_mclk) {
1957                 result = tonga_get_dependecy_volt_by_clk(hwmgr,
1958                         pptable_info->vdd_dep_on_mclk, memory_clock, &memory_level->MinVoltage, &minMvdd);
1959                 PP_ASSERT_WITH_CODE((0 == result),
1960                         "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
1961         }
1962
1963         if (data->mvdd_control == TONGA_VOLTAGE_CONTROL_NONE) {
1964                 memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value;
1965         } else {
1966                 memory_level->MinMvdd = minMvdd;
1967         }
1968         memory_level->EnabledForThrottle = 1;
1969         memory_level->EnabledForActivity = 0;
1970         memory_level->UpHyst = 0;
1971         memory_level->DownHyst = 100;
1972         memory_level->VoltageDownHyst = 0;
1973
1974         /* Indicates maximum activity level for this performance level.*/
1975         memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1976         memory_level->StutterEnable = 0;
1977         memory_level->StrobeEnable = 0;
1978         memory_level->EdcReadEnable = 0;
1979         memory_level->EdcWriteEnable = 0;
1980         memory_level->RttEnable = 0;
1981
1982         /* default set to low watermark. Highest level will be set to high later.*/
1983         memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1984
1985         cgs_get_active_displays_info(hwmgr->device, &info);
1986         data->display_timing.num_existing_displays = info.display_count;
1987
1988         if ((data->mclk_stutter_mode_threshold != 0) &&
1989                         (memory_clock <= data->mclk_stutter_mode_threshold) &&
1990                         (data->is_uvd_enabled == 0)
1991 #if defined(LINUX)
1992                         && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
1993                         && (data->display_timing.num_existing_displays <= 2)
1994                         && (data->display_timing.num_existing_displays != 0)
1995 #endif
1996         )
1997                 memory_level->StutterEnable = 1;
1998
1999         /* decide strobe mode*/
2000         memory_level->StrobeEnable = (data->mclk_strobe_mode_threshold != 0) &&
2001                 (memory_clock <= data->mclk_strobe_mode_threshold);
2002
2003         /* decide EDC mode and memory clock ratio*/
2004         if (data->is_memory_GDDR5) {
2005                 memory_level->StrobeRatio = tonga_get_mclk_frequency_ratio(memory_clock,
2006                                         memory_level->StrobeEnable);
2007
2008                 if ((data->mclk_edc_enable_threshold != 0) &&
2009                                 (memory_clock > data->mclk_edc_enable_threshold)) {
2010                         memory_level->EdcReadEnable = 1;
2011                 }
2012
2013                 if ((data->mclk_edc_wr_enable_threshold != 0) &&
2014                                 (memory_clock > data->mclk_edc_wr_enable_threshold)) {
2015                         memory_level->EdcWriteEnable = 1;
2016                 }
2017
2018                 if (memory_level->StrobeEnable) {
2019                         if (tonga_get_mclk_frequency_ratio(memory_clock, 1) >=
2020                                         ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) {
2021                                 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
2022                         } else {
2023                                 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
2024                         }
2025
2026                 } else {
2027                         dllStateOn = data->dll_defaule_on;
2028                 }
2029         } else {
2030                 memory_level->StrobeRatio =
2031                         tonga_get_ddr3_mclk_frequency_ratio(memory_clock);
2032                 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
2033         }
2034
2035         result = tonga_calculate_mclk_params(hwmgr,
2036                 memory_clock, memory_level, memory_level->StrobeEnable, dllStateOn);
2037
2038         if (0 == result) {
2039                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinMvdd);
2040                 /* MCLK frequency in units of 10KHz*/
2041                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
2042                 /* Indicates maximum activity level for this performance level.*/
2043                 CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
2044                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
2045                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
2046                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
2047                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
2048                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
2049                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
2050                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
2051                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
2052                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
2053         }
2054
2055         return result;
2056 }
2057
2058 /**
2059  * Populates the SMC MVDD structure using the provided memory clock.
2060  *
2061  * @param    hwmgr      the address of the hardware manager
2062  * @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
2063  * @param    voltage     the SMC VOLTAGE structure to be populated
2064  */
2065 int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMIO_Pattern *smio_pattern)
2066 {
2067         const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2068         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2069         uint32_t i = 0;
2070
2071         if (TONGA_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
2072                 /* find mvdd value which clock is more than request */
2073                 for (i = 0; i < pptable_info->vdd_dep_on_mclk->count; i++) {
2074                         if (mclk <= pptable_info->vdd_dep_on_mclk->entries[i].clk) {
2075                                 /* Always round to higher voltage. */
2076                                 smio_pattern->Voltage = data->mvdd_voltage_table.entries[i].value;
2077                                 break;
2078                         }
2079                 }
2080
2081                 PP_ASSERT_WITH_CODE(i < pptable_info->vdd_dep_on_mclk->count,
2082                         "MVDD Voltage is outside the supported range.", return -1);
2083
2084         } else {
2085                 return -1;
2086         }
2087
2088         return 0;
2089 }
2090
2091
2092 static int tonga_populate_smv_acpi_level(struct pp_hwmgr *hwmgr,
2093         SMU72_Discrete_DpmTable *table)
2094 {
2095         int result = 0;
2096         const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2097         pp_atomctrl_clock_dividers_vi dividers;
2098         SMIO_Pattern voltage_level;
2099         uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2100         uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
2101         uint32_t dll_cntl          = data->clock_registers.vDLL_CNTL;
2102         uint32_t mclk_pwrmgt_cntl  = data->clock_registers.vMCLK_PWRMGT_CNTL;
2103
2104         /* The ACPI state should not do DPM on DC (or ever).*/
2105         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2106
2107         table->ACPILevel.MinVoltage = data->smc_state_table.GraphicsLevel[0].MinVoltage;
2108
2109         /* assign zero for now*/
2110         table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
2111
2112         /* get the engine clock dividers for this clock value*/
2113         result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
2114                 table->ACPILevel.SclkFrequency,  &dividers);
2115
2116         PP_ASSERT_WITH_CODE(result == 0,
2117                 "Error retrieving Engine Clock dividers from VBIOS.", return result);
2118
2119         /* divider ID for required SCLK*/
2120         table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
2121         table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2122         table->ACPILevel.DeepSleepDivId = 0;
2123
2124         spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
2125                                                         CG_SPLL_FUNC_CNTL,   SPLL_PWRON,     0);
2126         spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
2127                                                         CG_SPLL_FUNC_CNTL,   SPLL_RESET,     1);
2128         spll_func_cntl_2    = PHM_SET_FIELD(spll_func_cntl_2,
2129                                                         CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL,   4);
2130
2131         table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2132         table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2133         table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2134         table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2135         table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2136         table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2137         table->ACPILevel.CcPwrDynRm = 0;
2138         table->ACPILevel.CcPwrDynRm1 = 0;
2139
2140
2141         /* For various features to be enabled/disabled while this level is active.*/
2142         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
2143         /* SCLK frequency in units of 10KHz*/
2144         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
2145         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
2146         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
2147         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
2148         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
2149         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
2150         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
2151         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
2152         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
2153
2154         /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
2155         table->MemoryACPILevel.MinVoltage = data->smc_state_table.MemoryLevel[0].MinVoltage;
2156
2157         /*  CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/
2158
2159         if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level))
2160                 table->MemoryACPILevel.MinMvdd =
2161                         PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
2162         else
2163                 table->MemoryACPILevel.MinMvdd = 0;
2164
2165         /* Force reset on DLL*/
2166         mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2167                 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
2168         mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2169                 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
2170
2171         /* Disable DLL in ACPIState*/
2172         mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2173                 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
2174         mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2175                 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
2176
2177         /* Enable DLL bypass signal*/
2178         dll_cntl            = PHM_SET_FIELD(dll_cntl,
2179                 DLL_CNTL, MRDCK0_BYPASS, 0);
2180         dll_cntl            = PHM_SET_FIELD(dll_cntl,
2181                 DLL_CNTL, MRDCK1_BYPASS, 0);
2182
2183         table->MemoryACPILevel.DllCntl            =
2184                 PP_HOST_TO_SMC_UL(dll_cntl);
2185         table->MemoryACPILevel.MclkPwrmgtCntl     =
2186                 PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
2187         table->MemoryACPILevel.MpllAdFuncCntl     =
2188                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
2189         table->MemoryACPILevel.MpllDqFuncCntl     =
2190                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
2191         table->MemoryACPILevel.MpllFuncCntl       =
2192                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
2193         table->MemoryACPILevel.MpllFuncCntl_1     =
2194                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
2195         table->MemoryACPILevel.MpllFuncCntl_2     =
2196                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
2197         table->MemoryACPILevel.MpllSs1            =
2198                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
2199         table->MemoryACPILevel.MpllSs2            =
2200                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
2201
2202         table->MemoryACPILevel.EnabledForThrottle = 0;
2203         table->MemoryACPILevel.EnabledForActivity = 0;
2204         table->MemoryACPILevel.UpHyst = 0;
2205         table->MemoryACPILevel.DownHyst = 100;
2206         table->MemoryACPILevel.VoltageDownHyst = 0;
2207         /* Indicates maximum activity level for this performance level.*/
2208         table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
2209
2210         table->MemoryACPILevel.StutterEnable = 0;
2211         table->MemoryACPILevel.StrobeEnable = 0;
2212         table->MemoryACPILevel.EdcReadEnable = 0;
2213         table->MemoryACPILevel.EdcWriteEnable = 0;
2214         table->MemoryACPILevel.RttEnable = 0;
2215
2216         return result;
2217 }
2218
2219 static int tonga_find_boot_level(struct tonga_single_dpm_table *table, uint32_t value, uint32_t *boot_level)
2220 {
2221         int result = 0;
2222         uint32_t i;
2223
2224         for (i = 0; i < table->count; i++) {
2225                 if (value == table->dpm_levels[i].value) {
2226                         *boot_level = i;
2227                         result = 0;
2228                 }
2229         }
2230         return result;
2231 }
2232
2233 static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
2234                         SMU72_Discrete_DpmTable *table)
2235 {
2236         int result = 0;
2237         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2238
2239         table->GraphicsBootLevel  = 0;        /* 0 == DPM[0] (low), etc. */
2240         table->MemoryBootLevel    = 0;        /* 0 == DPM[0] (low), etc. */
2241
2242         /* find boot level from dpm table*/
2243         result = tonga_find_boot_level(&(data->dpm_table.sclk_table),
2244         data->vbios_boot_state.sclk_bootup_value,
2245         (uint32_t *)&(data->smc_state_table.GraphicsBootLevel));
2246
2247         if (0 != result) {
2248                 data->smc_state_table.GraphicsBootLevel = 0;
2249                 printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
2250                         in dependency table. Using Graphics DPM level 0!");
2251                 result = 0;
2252         }
2253
2254         result = tonga_find_boot_level(&(data->dpm_table.mclk_table),
2255                 data->vbios_boot_state.mclk_bootup_value,
2256                 (uint32_t *)&(data->smc_state_table.MemoryBootLevel));
2257
2258         if (0 != result) {
2259                 data->smc_state_table.MemoryBootLevel = 0;
2260                 printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
2261                         in dependency table. Using Memory DPM level 0!");
2262                 result = 0;
2263         }
2264
2265         table->BootVoltage.Vddc =
2266                 tonga_get_voltage_id(&(data->vddc_voltage_table),
2267                         data->vbios_boot_state.vddc_bootup_value);
2268         table->BootVoltage.VddGfx =
2269                 tonga_get_voltage_id(&(data->vddgfx_voltage_table),
2270                         data->vbios_boot_state.vddgfx_bootup_value);
2271         table->BootVoltage.Vddci =
2272                 tonga_get_voltage_id(&(data->vddci_voltage_table),
2273                         data->vbios_boot_state.vddci_bootup_value);
2274         table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
2275
2276         CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
2277
2278         return result;
2279 }
2280
2281
2282 /**
2283  * Calculates the SCLK dividers using the provided engine clock
2284  *
2285  * @param    hwmgr      the address of the hardware manager
2286  * @param    engine_clock the engine clock to use to populate the structure
2287  * @param    sclk        the SMC SCLK structure to be populated
2288  */
2289 int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
2290                 uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)
2291 {
2292         const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2293         pp_atomctrl_clock_dividers_vi dividers;
2294         uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2295         uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2296         uint32_t spll_func_cntl_4          = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2297         uint32_t cg_spll_spread_spectrum   = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2298         uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2299         uint32_t    reference_clock;
2300         uint32_t reference_divider;
2301         uint32_t fbdiv;
2302         int result;
2303
2304         /* get the engine clock dividers for this clock value*/
2305         result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock,  &dividers);
2306
2307         PP_ASSERT_WITH_CODE(result == 0,
2308                 "Error retrieving Engine Clock dividers from VBIOS.", return result);
2309
2310         /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
2311         reference_clock = atomctrl_get_reference_clock(hwmgr);
2312
2313         reference_divider = 1 + dividers.uc_pll_ref_div;
2314
2315         /* low 14 bits is fraction and high 12 bits is divider*/
2316         fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
2317
2318         /* SPLL_FUNC_CNTL setup*/
2319         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2320                 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
2321         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2322                 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A,  dividers.uc_pll_post_div);
2323
2324         /* SPLL_FUNC_CNTL_3 setup*/
2325         spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
2326                 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
2327
2328         /* set to use fractional accumulation*/
2329         spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
2330                 CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
2331
2332         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2333                         PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
2334                 pp_atomctrl_internal_ss_info ss_info;
2335
2336                 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
2337                 if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
2338                         /*
2339                         * ss_info.speed_spectrum_percentage -- in unit of 0.01%
2340                         * ss_info.speed_spectrum_rate -- in unit of khz
2341                         */
2342                         /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
2343                         uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
2344
2345                         /* clkv = 2 * D * fbdiv / NS */
2346                         uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
2347
2348                         cg_spll_spread_spectrum =
2349                                 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
2350                         cg_spll_spread_spectrum =
2351                                 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
2352                         cg_spll_spread_spectrum_2 =
2353                                 PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
2354                 }
2355         }
2356
2357         sclk->SclkFrequency        = engine_clock;
2358         sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
2359         sclk->CgSpllFuncCntl4      = spll_func_cntl_4;
2360         sclk->SpllSpreadSpectrum   = cg_spll_spread_spectrum;
2361         sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
2362         sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
2363
2364         return 0;
2365 }
2366
2367 /**
2368  * Populates single SMC SCLK structure using the provided engine clock
2369  *
2370  * @param    hwmgr      the address of the hardware manager
2371  * @param    engine_clock the engine clock to use to populate the structure
2372  * @param    sclk        the SMC SCLK structure to be populated
2373  */
2374 static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint16_t sclk_activity_level_threshold, SMU72_Discrete_GraphicsLevel *graphic_level)
2375 {
2376         int result;
2377         uint32_t threshold;
2378         uint32_t mvdd;
2379         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2380         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2381
2382         result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
2383
2384
2385         /* populate graphics levels*/
2386         result = tonga_get_dependecy_volt_by_clk(hwmgr,
2387                 pptable_info->vdd_dep_on_sclk, engine_clock,
2388                 &graphic_level->MinVoltage, &mvdd);
2389         PP_ASSERT_WITH_CODE((0 == result),
2390                 "can not find VDDC voltage value for VDDC       \
2391                 engine clock dependency table", return result);
2392
2393         /* SCLK frequency in units of 10KHz*/
2394         graphic_level->SclkFrequency = engine_clock;
2395
2396         /* Indicates maximum activity level for this performance level. 50% for now*/
2397         graphic_level->ActivityLevel = sclk_activity_level_threshold;
2398
2399         graphic_level->CcPwrDynRm = 0;
2400         graphic_level->CcPwrDynRm1 = 0;
2401         /* this level can be used if activity is high enough.*/
2402         graphic_level->EnabledForActivity = 0;
2403         /* this level can be used for throttling.*/
2404         graphic_level->EnabledForThrottle = 1;
2405         graphic_level->UpHyst = 0;
2406         graphic_level->DownHyst = 0;
2407         graphic_level->VoltageDownHyst = 0;
2408         graphic_level->PowerThrottle = 0;
2409
2410         threshold = engine_clock * data->fast_watemark_threshold / 100;
2411 /*
2412         *get the DAL clock. do it in funture.
2413         PECI_GetMinClockSettings(hwmgr->peci, &minClocks);
2414         data->display_timing.min_clock_insr = minClocks.engineClockInSR;
2415
2416         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
2417         {
2418                 graphic_level->DeepSleepDivId = PhwTonga_GetSleepDividerIdFromClock(hwmgr, engine_clock, minClocks.engineClockInSR);
2419         }
2420 */
2421
2422         /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
2423         graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2424
2425         if (0 == result) {
2426                 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/
2427                 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);*/
2428                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
2429                 CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
2430                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
2431                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
2432                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
2433                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
2434                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
2435                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
2436         }
2437
2438         return result;
2439 }
2440
2441 /**
2442  * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
2443  *
2444  * @param    hwmgr      the address of the hardware manager
2445  */
2446 static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
2447 {
2448         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2449         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2450         struct tonga_dpm_table *dpm_table = &data->dpm_table;
2451         phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
2452         uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count;
2453         int result = 0;
2454         uint32_t level_array_adress = data->dpm_table_start +
2455                 offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
2456         uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) *
2457                 SMU72_MAX_LEVELS_GRAPHICS;   /* 64 -> long; 32 -> int*/
2458         SMU72_Discrete_GraphicsLevel *levels = data->smc_state_table.GraphicsLevel;
2459         uint32_t i, maxEntry;
2460         uint8_t highest_pcie_level_enabled = 0, lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0, count = 0;
2461         PECI_RegistryValue reg_value;
2462         memset(levels, 0x00, level_array_size);
2463
2464         for (i = 0; i < dpm_table->sclk_table.count; i++) {
2465                 result = tonga_populate_single_graphic_level(hwmgr,
2466                                         dpm_table->sclk_table.dpm_levels[i].value,
2467                                         (uint16_t)data->activity_target[i],
2468                                         &(data->smc_state_table.GraphicsLevel[i]));
2469
2470                 if (0 != result)
2471                         return result;
2472
2473                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
2474                 if (i > 1)
2475                         data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
2476
2477                 if (0 == i) {
2478                         reg_value = 0;
2479                         if (reg_value != 0)
2480                                 data->smc_state_table.GraphicsLevel[0].UpHyst = (uint8_t)reg_value;
2481                 }
2482
2483                 if (1 == i) {
2484                         reg_value = 0;
2485                         if (reg_value != 0)
2486                                 data->smc_state_table.GraphicsLevel[1].UpHyst = (uint8_t)reg_value;
2487                 }
2488         }
2489
2490         /* Only enable level 0 for now. */
2491         data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
2492
2493         /* set highest level watermark to high */
2494         if (dpm_table->sclk_table.count > 1)
2495                 data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
2496                         PPSMC_DISPLAY_WATERMARK_HIGH;
2497
2498         data->smc_state_table.GraphicsDpmLevelCount =
2499                 (uint8_t)dpm_table->sclk_table.count;
2500         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
2501                 tonga_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2502
2503         if (pcie_table != NULL) {
2504                 PP_ASSERT_WITH_CODE((pcie_entry_count >= 1),
2505                         "There must be 1 or more PCIE levels defined in PPTable.", return -1);
2506                 maxEntry = pcie_entry_count - 1; /* for indexing, we need to decrement by 1.*/
2507                 for (i = 0; i < dpm_table->sclk_table.count; i++) {
2508                         data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
2509                                 (uint8_t) ((i < maxEntry) ? i : maxEntry);
2510                 }
2511         } else {
2512                 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask)
2513                         printk(KERN_ERR "[ powerplay ] Pcie Dpm Enablemask is 0!");
2514
2515                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2516                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2517                                         (1<<(highest_pcie_level_enabled+1))) != 0)) {
2518                         highest_pcie_level_enabled++;
2519                 }
2520
2521                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2522                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2523                                         (1<<lowest_pcie_level_enabled)) == 0)) {
2524                         lowest_pcie_level_enabled++;
2525                 }
2526
2527                 while ((count < highest_pcie_level_enabled) &&
2528                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2529                                         (1<<(lowest_pcie_level_enabled+1+count))) == 0)) {
2530                         count++;
2531                 }
2532                 mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
2533                         (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
2534
2535
2536                 /* set pcieDpmLevel to highest_pcie_level_enabled*/
2537                 for (i = 2; i < dpm_table->sclk_table.count; i++) {
2538                         data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
2539                 }
2540
2541                 /* set pcieDpmLevel to lowest_pcie_level_enabled*/
2542                 data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
2543
2544                 /* set pcieDpmLevel to mid_pcie_level_enabled*/
2545                 data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
2546         }
2547         /* level count will send to smc once at init smc table and never change*/
2548         result = tonga_copy_bytes_to_smc(hwmgr->smumgr, level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end);
2549
2550         if (0 != result)
2551                 return result;
2552
2553         return 0;
2554 }
2555
2556 /**
2557  * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
2558  *
2559  * @param    hwmgr      the address of the hardware manager
2560  */
2561
2562 static int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
2563 {
2564         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2565         struct tonga_dpm_table *dpm_table = &data->dpm_table;
2566         int result;
2567         /* populate MCLK dpm table to SMU7 */
2568         uint32_t level_array_adress = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, MemoryLevel);
2569         uint32_t level_array_size = sizeof(SMU72_Discrete_MemoryLevel) * SMU72_MAX_LEVELS_MEMORY;
2570         SMU72_Discrete_MemoryLevel *levels = data->smc_state_table.MemoryLevel;
2571         uint32_t i;
2572
2573         memset(levels, 0x00, level_array_size);
2574
2575         for (i = 0; i < dpm_table->mclk_table.count; i++) {
2576                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
2577                         "can not populate memory level as memory clock is zero", return -1);
2578                 result = tonga_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
2579                         &(data->smc_state_table.MemoryLevel[i]));
2580                 if (0 != result) {
2581                         return result;
2582                 }
2583         }
2584
2585         /* Only enable level 0 for now.*/
2586         data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
2587
2588         /*
2589         * in order to prevent MC activity from stutter mode to push DPM up.
2590         * the UVD change complements this by putting the MCLK in a higher state
2591         * by default such that we are not effected by up threshold or and MCLK DPM latency.
2592         */
2593         data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
2594         CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.MemoryLevel[0].ActivityLevel);
2595
2596         data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
2597         data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2598         /* set highest level watermark to high*/
2599         data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
2600
2601         /* level count will send to smc once at init smc table and never change*/
2602         result = tonga_copy_bytes_to_smc(hwmgr->smumgr,
2603                 level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end);
2604
2605         if (0 != result) {
2606                 return result;
2607         }
2608
2609         return 0;
2610 }
2611
2612 struct TONGA_DLL_SPEED_SETTING {
2613         uint16_t            Min;                          /* Minimum Data Rate*/
2614         uint16_t            Max;                          /* Maximum Data Rate*/
2615         uint32_t                        dll_speed;                     /* The desired DLL_SPEED setting*/
2616 };
2617
2618 static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
2619 {
2620         return 0;
2621 }
2622
2623 /* ---------------------------------------- ULV related functions ----------------------------------------------------*/
2624
2625
2626 static int tonga_reset_single_dpm_table(
2627         struct pp_hwmgr *hwmgr,
2628         struct tonga_single_dpm_table *dpm_table,
2629         uint32_t count)
2630 {
2631         uint32_t i;
2632         if (!(count <= MAX_REGULAR_DPM_NUMBER))
2633                 printk(KERN_ERR "[ powerplay ] Fatal error, can not set up single DPM \
2634                         table entries to exceed max number! \n");
2635
2636         dpm_table->count = count;
2637         for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) {
2638                 dpm_table->dpm_levels[i].enabled = 0;
2639         }
2640
2641         return 0;
2642 }
2643
2644 static void tonga_setup_pcie_table_entry(
2645         struct tonga_single_dpm_table *dpm_table,
2646         uint32_t index, uint32_t pcie_gen,
2647         uint32_t pcie_lanes)
2648 {
2649         dpm_table->dpm_levels[index].value = pcie_gen;
2650         dpm_table->dpm_levels[index].param1 = pcie_lanes;
2651         dpm_table->dpm_levels[index].enabled = 1;
2652 }
2653
2654 bool is_pcie_gen3_supported(uint32_t pcie_link_speed_cap)
2655 {
2656         if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
2657                 return 1;
2658
2659         return 0;
2660 }
2661
2662 bool is_pcie_gen2_supported(uint32_t pcie_link_speed_cap)
2663 {
2664         if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
2665                 return 1;
2666
2667         return 0;
2668 }
2669
2670 /* Get the new PCIE speed given the ASIC PCIE Cap and the NewState's requested PCIE speed*/
2671 uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap, uint16_t ns_pcie_gen)
2672 {
2673         uint32_t asic_pcie_link_speed_cap = (pcie_link_speed_cap &
2674                 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK);
2675         uint32_t sys_pcie_link_speed_cap  = (pcie_link_speed_cap &
2676                 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK);
2677
2678         switch (asic_pcie_link_speed_cap) {
2679         case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1:
2680                 return PP_PCIEGen1;
2681
2682         case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2:
2683                 return PP_PCIEGen2;
2684
2685         case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3:
2686                 return PP_PCIEGen3;
2687
2688         default:
2689                 if (is_pcie_gen3_supported(sys_pcie_link_speed_cap) &&
2690                         (ns_pcie_gen == PP_PCIEGen3)) {
2691                         return PP_PCIEGen3;
2692                 } else if (is_pcie_gen2_supported(sys_pcie_link_speed_cap) &&
2693                         ((ns_pcie_gen == PP_PCIEGen3) || (ns_pcie_gen == PP_PCIEGen2))) {
2694                         return PP_PCIEGen2;
2695                 }
2696         }
2697
2698         return PP_PCIEGen1;
2699 }
2700
2701 uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap, uint16_t ns_pcie_lanes)
2702 {
2703         int i, j;
2704         uint16_t new_pcie_lanes = ns_pcie_lanes;
2705         uint16_t pcie_lanes[7] = {1, 2, 4, 8, 12, 16, 32};
2706
2707         switch (pcie_lane_width_cap) {
2708         case 0:
2709                 printk(KERN_ERR "[ powerplay ] No valid PCIE lane width reported by CAIL!");
2710                 break;
2711         case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
2712                 new_pcie_lanes = 1;
2713                 break;
2714         case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
2715                 new_pcie_lanes = 2;
2716                 break;
2717         case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
2718                 new_pcie_lanes = 4;
2719                 break;
2720         case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
2721                 new_pcie_lanes = 8;
2722                 break;
2723         case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
2724                 new_pcie_lanes = 12;
2725                 break;
2726         case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
2727                 new_pcie_lanes = 16;
2728                 break;
2729         case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
2730                 new_pcie_lanes = 32;
2731                 break;
2732         default:
2733                 for (i = 0; i < 7; i++) {
2734                         if (ns_pcie_lanes == pcie_lanes[i]) {
2735                                 if (pcie_lane_width_cap & (0x10000 << i)) {
2736                                         break;
2737                                 } else {
2738                                         for (j = i - 1; j >= 0; j--) {
2739                                                 if (pcie_lane_width_cap & (0x10000 << j)) {
2740                                                         new_pcie_lanes = pcie_lanes[j];
2741                                                         break;
2742                                                 }
2743                                         }
2744
2745                                         if (j < 0) {
2746                                                 for (j = i + 1; j < 7; j++) {
2747                                                         if (pcie_lane_width_cap & (0x10000 << j)) {
2748                                                                 new_pcie_lanes = pcie_lanes[j];
2749                                                                 break;
2750                                                         }
2751                                                 }
2752                                                 if (j > 7)
2753                                                         printk(KERN_ERR "[ powerplay ] Cannot find a valid PCIE lane width!");
2754                                         }
2755                                 }
2756                                 break;
2757                         }
2758                 }
2759                 break;
2760         }
2761
2762         return new_pcie_lanes;
2763 }
2764
2765 static int tonga_setup_default_pcie_tables(struct pp_hwmgr *hwmgr)
2766 {
2767         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2768         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2769         phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
2770         uint32_t i, maxEntry;
2771
2772         if (data->use_pcie_performance_levels && !data->use_pcie_power_saving_levels) {
2773                 data->pcie_gen_power_saving = data->pcie_gen_performance;
2774                 data->pcie_lane_power_saving = data->pcie_lane_performance;
2775         } else if (!data->use_pcie_performance_levels && data->use_pcie_power_saving_levels) {
2776                 data->pcie_gen_performance = data->pcie_gen_power_saving;
2777                 data->pcie_lane_performance = data->pcie_lane_power_saving;
2778         }
2779
2780         tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.pcie_speed_table, SMU72_MAX_LEVELS_LINK);
2781
2782         if (pcie_table != NULL) {
2783                 /*
2784                 * maxEntry is used to make sure we reserve one PCIE level for boot level (fix for A+A PSPP issue).
2785                 * If PCIE table from PPTable have ULV entry + 8 entries, then ignore the last entry.
2786                 */
2787                 maxEntry = (SMU72_MAX_LEVELS_LINK < pcie_table->count) ?
2788                                                 SMU72_MAX_LEVELS_LINK : pcie_table->count;
2789                 for (i = 1; i < maxEntry; i++) {
2790                         tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i-1,
2791                                 get_pcie_gen_support(data->pcie_gen_cap, pcie_table->entries[i].gen_speed),
2792                                 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2793                 }
2794                 data->dpm_table.pcie_speed_table.count = maxEntry - 1;
2795         } else {
2796                 /* Hardcode Pcie Table */
2797                 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
2798                         get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2799                         get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2800                 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
2801                         get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2802                         get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2803                 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
2804                         get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2805                         get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2806                 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
2807                         get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2808                         get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2809                 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
2810                         get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2811                         get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2812                 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
2813                         get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2814                         get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2815                 data->dpm_table.pcie_speed_table.count = 6;
2816         }
2817         /* Populate last level for boot PCIE level, but do not increment count. */
2818         tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
2819                 data->dpm_table.pcie_speed_table.count,
2820                 get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2821                 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2822
2823         return 0;
2824
2825 }
2826
2827 /*
2828  * This function is to initalize all DPM state tables for SMU7 based on the dependency table.
2829  * Dynamic state patching function will then trim these state tables to the allowed range based
2830  * on the power policy or external client requests, such as UVD request, etc.
2831  */
2832 static int tonga_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
2833 {
2834         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2835         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2836         uint32_t i;
2837
2838         phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_sclk_table =
2839                 pptable_info->vdd_dep_on_sclk;
2840         phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_mclk_table =
2841                 pptable_info->vdd_dep_on_mclk;
2842
2843         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
2844                 "SCLK dependency table is missing. This table is mandatory", return -1);
2845         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
2846                 "SCLK dependency table has to have is missing. This table is mandatory", return -1);
2847
2848         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
2849                 "MCLK dependency table is missing. This table is mandatory", return -1);
2850         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
2851                 "VMCLK dependency table has to have is missing. This table is mandatory", return -1);
2852
2853         /* clear the state table to reset everything to default */
2854         memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
2855         tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.sclk_table, SMU72_MAX_LEVELS_GRAPHICS);
2856         tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.mclk_table, SMU72_MAX_LEVELS_MEMORY);
2857         /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.VddcTable, SMU72_MAX_LEVELS_VDDC); */
2858         /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_gfx_table, SMU72_MAX_LEVELS_VDDGFX);*/
2859         /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_ci_table, SMU72_MAX_LEVELS_VDDCI);*/
2860         /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.mvdd_table, SMU72_MAX_LEVELS_MVDD);*/
2861
2862         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
2863                 "SCLK dependency table is missing. This table is mandatory", return -1);
2864         /* Initialize Sclk DPM table based on allow Sclk values*/
2865         data->dpm_table.sclk_table.count = 0;
2866
2867         for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
2868                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
2869                                 allowed_vdd_sclk_table->entries[i].clk) {
2870                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
2871                                 allowed_vdd_sclk_table->entries[i].clk;
2872                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; to do */
2873                         data->dpm_table.sclk_table.count++;
2874                 }
2875         }
2876
2877         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
2878                 "MCLK dependency table is missing. This table is mandatory", return -1);
2879         /* Initialize Mclk DPM table based on allow Mclk values */
2880         data->dpm_table.mclk_table.count = 0;
2881         for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
2882                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
2883                         allowed_vdd_mclk_table->entries[i].clk) {
2884                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
2885                                 allowed_vdd_mclk_table->entries[i].clk;
2886                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; */
2887                         data->dpm_table.mclk_table.count++;
2888                 }
2889         }
2890
2891         /* Initialize Vddc DPM table based on allow Vddc values.  And populate corresponding std values. */
2892         for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
2893                 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].vddc;
2894                 /* tonga_hwmgr->dpm_table.VddcTable.dpm_levels[i].param1 = stdVoltageTable->entries[i].Leakage; */
2895                 /* param1 is for corresponding std voltage */
2896                 data->dpm_table.vddc_table.dpm_levels[i].enabled = 1;
2897         }
2898         data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
2899
2900         if (NULL != allowed_vdd_mclk_table) {
2901                 /* Initialize Vddci DPM table based on allow Mclk values */
2902                 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
2903                         data->dpm_table.vdd_ci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].vddci;
2904                         data->dpm_table.vdd_ci_table.dpm_levels[i].enabled = 1;
2905                         data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].mvdd;
2906                         data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1;
2907                 }
2908                 data->dpm_table.vdd_ci_table.count = allowed_vdd_mclk_table->count;
2909                 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
2910         }
2911
2912         /* setup PCIE gen speed levels*/
2913         tonga_setup_default_pcie_tables(hwmgr);
2914
2915         /* save a copy of the default DPM table*/
2916         memcpy(&(data->golden_dpm_table), &(data->dpm_table), sizeof(struct tonga_dpm_table));
2917
2918         return 0;
2919 }
2920
2921 int tonga_populate_smc_initial_state(struct pp_hwmgr *hwmgr,
2922                 const struct tonga_power_state *bootState)
2923 {
2924         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2925         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2926         uint8_t count, level;
2927
2928         count = (uint8_t) (pptable_info->vdd_dep_on_sclk->count);
2929         for (level = 0; level < count; level++) {
2930                 if (pptable_info->vdd_dep_on_sclk->entries[level].clk >=
2931                         bootState->performance_levels[0].engine_clock) {
2932                         data->smc_state_table.GraphicsBootLevel = level;
2933                         break;
2934                 }
2935         }
2936
2937         count = (uint8_t) (pptable_info->vdd_dep_on_mclk->count);
2938         for (level = 0; level < count; level++) {
2939                 if (pptable_info->vdd_dep_on_mclk->entries[level].clk >=
2940                         bootState->performance_levels[0].memory_clock) {
2941                         data->smc_state_table.MemoryBootLevel = level;
2942                         break;
2943                 }
2944         }
2945
2946         return 0;
2947 }
2948
2949 /**
2950  * Initializes the SMC table and uploads it
2951  *
2952  * @param    hwmgr  the address of the powerplay hardware manager.
2953  * @param    pInput  the pointer to input data (PowerState)
2954  * @return   always 0
2955  */
2956 int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
2957 {
2958         int result;
2959         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2960         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2961         SMU72_Discrete_DpmTable  *table = &(data->smc_state_table);
2962         const phw_tonga_ulv_parm *ulv = &(data->ulv);
2963         uint8_t i;
2964         PECI_RegistryValue reg_value;
2965         pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2966
2967         result = tonga_setup_default_dpm_tables(hwmgr);
2968         PP_ASSERT_WITH_CODE(0 == result,
2969                 "Failed to setup default DPM tables!", return result;);
2970         memset(&(data->smc_state_table), 0x00, sizeof(data->smc_state_table));
2971         if (TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control) {
2972                 tonga_populate_smc_voltage_tables(hwmgr, table);
2973         }
2974
2975         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2976                         PHM_PlatformCaps_AutomaticDCTransition)) {
2977                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2978         }
2979
2980         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2981                         PHM_PlatformCaps_StepVddc)) {
2982                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2983         }
2984
2985         if (data->is_memory_GDDR5) {
2986                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2987         }
2988
2989         i = PHM_READ_FIELD(hwmgr->device, CC_MC_MAX_CHANNEL, NOOFCHAN);
2990
2991         if (i == 1 || i == 0) {
2992                 table->SystemFlags |= PPSMC_SYSTEMFLAG_12CHANNEL;
2993         }
2994
2995         if (ulv->ulv_supported && pptable_info->us_ulv_voltage_offset) {
2996                 PP_ASSERT_WITH_CODE(0 == result,
2997                         "Failed to initialize ULV state!", return result;);
2998
2999                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3000                         ixCG_ULV_PARAMETER, ulv->ch_ulv_parameter);
3001         }
3002
3003         result = tonga_populate_smc_link_level(hwmgr, table);
3004         PP_ASSERT_WITH_CODE(0 == result,
3005                 "Failed to initialize Link Level!", return result;);
3006
3007         result = tonga_populate_all_graphic_levels(hwmgr);
3008         PP_ASSERT_WITH_CODE(0 == result,
3009                 "Failed to initialize Graphics Level!", return result;);
3010
3011         result = tonga_populate_all_memory_levels(hwmgr);
3012         PP_ASSERT_WITH_CODE(0 == result,
3013                 "Failed to initialize Memory Level!", return result;);
3014
3015         result = tonga_populate_smv_acpi_level(hwmgr, table);
3016         PP_ASSERT_WITH_CODE(0 == result,
3017                 "Failed to initialize ACPI Level!", return result;);
3018
3019         result = tonga_populate_smc_vce_level(hwmgr, table);
3020         PP_ASSERT_WITH_CODE(0 == result,
3021                 "Failed to initialize VCE Level!", return result;);
3022
3023         result = tonga_populate_smc_acp_level(hwmgr, table);
3024         PP_ASSERT_WITH_CODE(0 == result,
3025                 "Failed to initialize ACP Level!", return result;);
3026
3027         result = tonga_populate_smc_samu_level(hwmgr, table);
3028         PP_ASSERT_WITH_CODE(0 == result,
3029                 "Failed to initialize SAMU Level!", return result;);
3030
3031         /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
3032         /* need to populate the  ARB settings for the initial state. */
3033         result = tonga_program_memory_timing_parameters(hwmgr);
3034         PP_ASSERT_WITH_CODE(0 == result,
3035                 "Failed to Write ARB settings for the initial state.", return result;);
3036
3037         result = tonga_populate_smc_boot_level(hwmgr, table);
3038         PP_ASSERT_WITH_CODE(0 == result,
3039                 "Failed to initialize Boot Level!", return result;);
3040
3041         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3042                         PHM_PlatformCaps_ClockStretcher)) {
3043                 result = tonga_populate_clock_stretcher_data_table(hwmgr);
3044                 PP_ASSERT_WITH_CODE(0 == result,
3045                         "Failed to populate Clock Stretcher Data Table!", return result;);
3046         }
3047         table->GraphicsVoltageChangeEnable  = 1;
3048         table->GraphicsThermThrottleEnable  = 1;
3049         table->GraphicsInterval = 1;
3050         table->VoltageInterval  = 1;
3051         table->ThermalInterval  = 1;
3052         table->TemperatureLimitHigh =
3053                 pptable_info->cac_dtp_table->usTargetOperatingTemp *
3054                 TONGA_Q88_FORMAT_CONVERSION_UNIT;
3055         table->TemperatureLimitLow =
3056                 (pptable_info->cac_dtp_table->usTargetOperatingTemp - 1) *
3057                 TONGA_Q88_FORMAT_CONVERSION_UNIT;
3058         table->MemoryVoltageChangeEnable  = 1;
3059         table->MemoryInterval  = 1;
3060         table->VoltageResponseTime  = 0;
3061         table->PhaseResponseTime  = 0;
3062         table->MemoryThermThrottleEnable  = 1;
3063
3064         /*
3065         * Cail reads current link status and reports it as cap (we cannot change this due to some previous issues we had)
3066         * SMC drops the link status to lowest level after enabling DPM by PowerPlay. After pnp or toggling CF, driver gets reloaded again
3067         * but this time Cail reads current link status which was set to low by SMC and reports it as cap to powerplay
3068         * To avoid it, we set PCIeBootLinkLevel to highest dpm level
3069         */
3070         PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
3071                         "There must be 1 or more PCIE levels defined in PPTable.",
3072                         return -1);
3073
3074         table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
3075
3076         table->PCIeGenInterval  = 1;
3077
3078         result = tonga_populate_vr_config(hwmgr, table);
3079         PP_ASSERT_WITH_CODE(0 == result,
3080                 "Failed to populate VRConfig setting!", return result);
3081
3082         table->ThermGpio  = 17;
3083         table->SclkStepSize = 0x4000;
3084
3085         reg_value = 0;
3086         if ((0 == reg_value) &&
3087                 (0 == atomctrl_get_pp_assign_pin(hwmgr,
3088                         VDDC_VRHOT_GPIO_PINID, &gpio_pin_assignment))) {
3089                 table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3090                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3091                         PHM_PlatformCaps_RegulatorHot);
3092         } else {
3093                 table->VRHotGpio = TONGA_UNUSED_GPIO_PIN;
3094                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3095                         PHM_PlatformCaps_RegulatorHot);
3096         }
3097
3098         /* ACDC Switch GPIO */
3099         reg_value = 0;
3100         if ((0 == reg_value) &&
3101                 (0 == atomctrl_get_pp_assign_pin(hwmgr,
3102                         PP_AC_DC_SWITCH_GPIO_PINID, &gpio_pin_assignment))) {
3103                 table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3104                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3105                         PHM_PlatformCaps_AutomaticDCTransition);
3106         } else {
3107                 table->AcDcGpio = TONGA_UNUSED_GPIO_PIN;
3108                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3109                         PHM_PlatformCaps_AutomaticDCTransition);
3110         }
3111
3112         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3113                 PHM_PlatformCaps_Falcon_QuickTransition);
3114
3115         reg_value = 0;
3116         if (1 == reg_value) {
3117                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3118                         PHM_PlatformCaps_AutomaticDCTransition);
3119                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3120                         PHM_PlatformCaps_Falcon_QuickTransition);
3121         }
3122
3123         reg_value = 0;
3124         if ((0 == reg_value) &&
3125                 (0 == atomctrl_get_pp_assign_pin(hwmgr,
3126                         THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin_assignment))) {
3127                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3128                         PHM_PlatformCaps_ThermalOutGPIO);
3129
3130                 table->ThermOutGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3131
3132                 table->ThermOutPolarity =
3133                         (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
3134                         (1 << gpio_pin_assignment.uc_gpio_pin_bit_shift))) ? 1:0;
3135
3136                 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
3137
3138                 /* if required, combine VRHot/PCC with thermal out GPIO*/
3139                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3140                         PHM_PlatformCaps_RegulatorHot) &&
3141                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3142                         PHM_PlatformCaps_CombinePCCWithThermalSignal)){
3143                         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
3144                 }
3145         } else {
3146                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3147                         PHM_PlatformCaps_ThermalOutGPIO);
3148
3149                 table->ThermOutGpio = 17;
3150                 table->ThermOutPolarity = 1;
3151                 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
3152         }
3153
3154         for (i = 0; i < SMU72_MAX_ENTRIES_SMIO; i++) {
3155                 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
3156         }
3157         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
3158         CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
3159         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
3160         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
3161         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
3162         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
3163         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
3164         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
3165         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
3166
3167         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
3168         result = tonga_copy_bytes_to_smc(hwmgr->smumgr, data->dpm_table_start +
3169                                                                                 offsetof(SMU72_Discrete_DpmTable, SystemFlags),
3170                                                                                 (uint8_t *)&(table->SystemFlags),
3171                                                                                 sizeof(SMU72_Discrete_DpmTable)-3 * sizeof(SMU72_PIDController),
3172                                                                                 data->sram_end);
3173
3174         PP_ASSERT_WITH_CODE(0 == result,
3175                 "Failed to upload dpm data to SMC memory!", return result;);
3176
3177         return result;
3178 }
3179
3180 /* Look up the voltaged based on DAL's requested level. and then send the requested VDDC voltage to SMC*/
3181 static void tonga_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr)
3182 {
3183         return;
3184 }
3185
3186 int tonga_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3187 {
3188         PPSMC_Result result;
3189         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3190
3191         /* Apply minimum voltage based on DAL's request level */
3192         tonga_apply_dal_minimum_voltage_request(hwmgr);
3193
3194         if (0 == data->sclk_dpm_key_disabled) {
3195                 /* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
3196                 if (0 != tonga_is_dpm_running(hwmgr))
3197                         printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n");
3198
3199                 if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3200                         result = smum_send_msg_to_smc_with_parameter(
3201                                                                 hwmgr->smumgr,
3202                                 (PPSMC_Msg)PPSMC_MSG_SCLKDPM_SetEnabledMask,
3203                                 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3204                         PP_ASSERT_WITH_CODE((0 == result),
3205                                 "Set Sclk Dpm enable Mask failed", return -1);
3206                 }
3207         }
3208
3209         if (0 == data->mclk_dpm_key_disabled) {
3210                 /* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
3211                 if (0 != tonga_is_dpm_running(hwmgr))
3212                         printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n");
3213
3214                 if (0 != data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3215                         result = smum_send_msg_to_smc_with_parameter(
3216                                                                 hwmgr->smumgr,
3217                                 (PPSMC_Msg)PPSMC_MSG_MCLKDPM_SetEnabledMask,
3218                                 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3219                         PP_ASSERT_WITH_CODE((0 == result),
3220                                 "Set Mclk Dpm enable Mask failed", return -1);
3221                 }
3222         }
3223
3224         return 0;
3225 }
3226
3227
3228 int tonga_force_dpm_highest(struct pp_hwmgr *hwmgr)
3229 {
3230         uint32_t level, tmp;
3231         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3232
3233         if (0 == data->pcie_dpm_key_disabled) {
3234                 /* PCIE */
3235                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) {
3236                         level = 0;
3237                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3238                         while (tmp >>= 1)
3239                                 level++ ;
3240
3241                         if (0 != level) {
3242                                 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)),
3243                                         "force highest pcie dpm state failed!", return -1);
3244                         }
3245                 }
3246         }
3247
3248         if (0 == data->sclk_dpm_key_disabled) {
3249                 /* SCLK */
3250                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask != 0) {
3251                         level = 0;
3252                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3253                         while (tmp >>= 1)
3254                                 level++ ;
3255
3256                         if (0 != level) {
3257                                 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)),
3258                                         "force highest sclk dpm state failed!", return -1);
3259                                 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
3260                                         CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level)
3261                                         printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
3262                                                 Curr_Sclk_Index does not match the level \n");
3263
3264                         }
3265                 }
3266         }
3267
3268         if (0 == data->mclk_dpm_key_disabled) {
3269                 /* MCLK */
3270                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) {
3271                         level = 0;
3272                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3273                         while (tmp >>= 1)
3274                                 level++ ;
3275
3276                         if (0 != level) {
3277                                 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)),
3278                                         "force highest mclk dpm state failed!", return -1);
3279                                 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3280                                         TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level)
3281                                         printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
3282                                                 Curr_Mclk_Index does not match the level \n");
3283                         }
3284                 }
3285         }
3286
3287         return 0;
3288 }
3289
3290 /**
3291  * Find the MC microcode version and store it in the HwMgr struct
3292  *
3293  * @param    hwmgr  the address of the powerplay hardware manager.
3294  * @return   always 0
3295  */
3296 int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
3297 {
3298         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
3299
3300         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
3301
3302         return 0;
3303 }
3304
3305 /**
3306  * Initialize Dynamic State Adjustment Rule Settings
3307  *
3308  * @param    hwmgr  the address of the powerplay hardware manager.
3309  */
3310 int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
3311 {
3312         uint32_t table_size;
3313         struct phm_clock_voltage_dependency_table *table_clk_vlt;
3314         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3315
3316         hwmgr->dyn_state.mclk_sclk_ratio = 4;
3317         hwmgr->dyn_state.sclk_mclk_delta = 15000;      /* 150 MHz */
3318         hwmgr->dyn_state.vddc_vddci_delta = 200;       /* 200mV */
3319
3320         /* initialize vddc_dep_on_dal_pwrl table */
3321         table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record);
3322         table_clk_vlt = (struct phm_clock_voltage_dependency_table *)kzalloc(table_size, GFP_KERNEL);
3323
3324         if (NULL == table_clk_vlt) {
3325                 printk(KERN_ERR "[ powerplay ] Can not allocate space for vddc_dep_on_dal_pwrl! \n");
3326                 return -ENOMEM;
3327         } else {
3328                 table_clk_vlt->count = 4;
3329                 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
3330                 table_clk_vlt->entries[0].v = 0;
3331                 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
3332                 table_clk_vlt->entries[1].v = 720;
3333                 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;
3334                 table_clk_vlt->entries[2].v = 810;
3335                 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;
3336                 table_clk_vlt->entries[3].v = 900;
3337                 pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt;
3338                 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
3339         }
3340
3341         return 0;
3342 }
3343
3344 static int tonga_set_private_var_based_on_pptale(struct pp_hwmgr *hwmgr)
3345 {
3346         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3347         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3348
3349         phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
3350                 pptable_info->vdd_dep_on_sclk;
3351         phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
3352                 pptable_info->vdd_dep_on_mclk;
3353
3354         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
3355                 "VDD dependency on SCLK table is missing.       \
3356                 This table is mandatory", return -1);
3357         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
3358                 "VDD dependency on SCLK table has to have is missing.   \
3359                 This table is mandatory", return -1);
3360
3361         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
3362                 "VDD dependency on MCLK table is missing.       \
3363                 This table is mandatory", return -1);
3364         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
3365                 "VDD dependency on MCLK table has to have is missing.    \
3366                 This table is mandatory", return -1);
3367
3368         data->min_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc;
3369         data->max_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3370
3371         pptable_info->max_clock_voltage_on_ac.sclk =
3372                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
3373         pptable_info->max_clock_voltage_on_ac.mclk =
3374                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
3375         pptable_info->max_clock_voltage_on_ac.vddc =
3376                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3377         pptable_info->max_clock_voltage_on_ac.vddci =
3378                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
3379
3380         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
3381                 pptable_info->max_clock_voltage_on_ac.sclk;
3382         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
3383                 pptable_info->max_clock_voltage_on_ac.mclk;
3384         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
3385                 pptable_info->max_clock_voltage_on_ac.vddc;
3386         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
3387                 pptable_info->max_clock_voltage_on_ac.vddci;
3388
3389         return 0;
3390 }
3391
3392 int tonga_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3393 {
3394         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3395         int result = 1;
3396
3397         PP_ASSERT_WITH_CODE (0 == tonga_is_dpm_running(hwmgr),
3398                 "Trying to Unforce DPM when DPM is disabled. Returning without sending SMC message.",
3399                                                         return result);
3400
3401         if (0 == data->pcie_dpm_key_disabled) {
3402                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(
3403                                                              hwmgr->smumgr,
3404                                         PPSMC_MSG_PCIeDPM_UnForceLevel)),
3405                                            "unforce pcie level failed!",
3406                                                                 return -1);
3407         }
3408
3409         result = tonga_upload_dpm_level_enable_mask(hwmgr);
3410
3411         return result;
3412 }
3413
3414 static uint32_t tonga_get_lowest_enable_level(
3415                                 struct pp_hwmgr *hwmgr, uint32_t level_mask)
3416 {
3417         uint32_t level = 0;
3418
3419         while (0 == (level_mask & (1 << level)))
3420                 level++;
3421
3422         return level;
3423 }
3424
3425 static int tonga_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3426 {
3427         uint32_t level;
3428         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3429
3430         if (0 == data->pcie_dpm_key_disabled) {
3431                 /* PCIE */
3432                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) {
3433                         level = tonga_get_lowest_enable_level(hwmgr,
3434                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3435                         PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)),
3436                                             "force lowest pcie dpm state failed!", return -1);
3437                 }
3438         }
3439
3440         if (0 == data->sclk_dpm_key_disabled) {
3441                 /* SCLK */
3442                 if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3443                         level = tonga_get_lowest_enable_level(hwmgr,
3444                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3445
3446                         PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)),
3447                                             "force sclk dpm state failed!", return -1);
3448
3449                         if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
3450                                                          CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level)
3451                                 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index.        \
3452                                 Curr_Sclk_Index does not match the level \n");
3453                 }
3454         }
3455
3456         if (0 == data->mclk_dpm_key_disabled) {
3457                 /* MCLK */
3458                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) {
3459                         level = tonga_get_lowest_enable_level(hwmgr,
3460                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3461                         PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)),
3462                                             "force lowest mclk dpm state failed!", return -1);
3463                         if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3464                                                          TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level)
3465                                 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
3466                                                 Curr_Mclk_Index does not match the level \n");
3467                 }
3468         }
3469
3470         return 0;
3471 }
3472
3473 static int tonga_patch_voltage_dependency_tables_with_lookup_table(struct pp_hwmgr *hwmgr)
3474 {
3475         uint8_t entryId;
3476         uint8_t voltageId;
3477         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3478         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3479
3480         phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
3481         phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
3482         phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
3483
3484         if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3485                 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3486                         voltageId = sclk_table->entries[entryId].vddInd;
3487                         sclk_table->entries[entryId].vddgfx =
3488                                 pptable_info->vddgfx_lookup_table->entries[voltageId].us_vdd;
3489                 }
3490         } else {
3491                 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3492                         voltageId = sclk_table->entries[entryId].vddInd;
3493                         sclk_table->entries[entryId].vddc =
3494                                 pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3495                 }
3496         }
3497
3498         for (entryId = 0; entryId < mclk_table->count; ++entryId) {
3499                 voltageId = mclk_table->entries[entryId].vddInd;
3500                 mclk_table->entries[entryId].vddc =
3501                         pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3502         }
3503
3504         for (entryId = 0; entryId < mm_table->count; ++entryId) {
3505                 voltageId = mm_table->entries[entryId].vddcInd;
3506                 mm_table->entries[entryId].vddc =
3507                         pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3508         }
3509
3510         return 0;
3511
3512 }
3513
3514 static int tonga_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
3515 {
3516         uint8_t entryId;
3517         phm_ppt_v1_voltage_lookup_record v_record;
3518         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3519         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3520
3521         phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
3522         phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
3523
3524         if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3525                 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3526                         if (sclk_table->entries[entryId].vdd_offset & (1 << 15))
3527                                 v_record.us_vdd = sclk_table->entries[entryId].vddgfx +
3528                                         sclk_table->entries[entryId].vdd_offset - 0xFFFF;
3529                         else
3530                                 v_record.us_vdd = sclk_table->entries[entryId].vddgfx +
3531                                         sclk_table->entries[entryId].vdd_offset;
3532
3533                         sclk_table->entries[entryId].vddc =
3534                                 v_record.us_cac_low = v_record.us_cac_mid =
3535                                 v_record.us_cac_high = v_record.us_vdd;
3536
3537                         tonga_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record);
3538                 }
3539
3540                 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
3541                         if (mclk_table->entries[entryId].vdd_offset & (1 << 15))
3542                                 v_record.us_vdd = mclk_table->entries[entryId].vddc +
3543                                         mclk_table->entries[entryId].vdd_offset - 0xFFFF;
3544                         else
3545                                 v_record.us_vdd = mclk_table->entries[entryId].vddc +
3546                                         mclk_table->entries[entryId].vdd_offset;
3547
3548                         mclk_table->entries[entryId].vddgfx = v_record.us_cac_low =
3549                                 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
3550                         tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
3551                 }
3552         }
3553
3554         return 0;
3555
3556 }
3557
3558 static int tonga_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
3559 {
3560         uint32_t entryId;
3561         phm_ppt_v1_voltage_lookup_record v_record;
3562         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3563         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3564         phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
3565
3566         if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3567                 for (entryId = 0; entryId < mm_table->count; entryId++) {
3568                         if (mm_table->entries[entryId].vddgfx_offset & (1 << 15))
3569                                 v_record.us_vdd = mm_table->entries[entryId].vddc +
3570                                         mm_table->entries[entryId].vddgfx_offset - 0xFFFF;
3571                         else
3572                                 v_record.us_vdd = mm_table->entries[entryId].vddc +
3573                                         mm_table->entries[entryId].vddgfx_offset;
3574
3575                         /* Add the calculated VDDGFX to the VDDGFX lookup table */
3576                         mm_table->entries[entryId].vddgfx = v_record.us_cac_low =
3577                                 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
3578                         tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
3579                 }
3580         }
3581         return 0;
3582 }
3583
3584
3585 /**
3586  * Change virtual leakage voltage to actual value.
3587  *
3588  * @param     hwmgr  the address of the powerplay hardware manager.
3589  * @param     pointer to changing voltage
3590  * @param     pointer to leakage table
3591  */
3592 static void tonga_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
3593                 uint16_t *voltage, phw_tonga_leakage_voltage *pLeakageTable)
3594 {
3595         uint32_t leakage_index;
3596
3597         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
3598         for (leakage_index = 0; leakage_index < pLeakageTable->count; leakage_index++) {
3599                 /* if this voltage matches a leakage voltage ID */
3600                 /* patch with actual leakage voltage */
3601                 if (pLeakageTable->leakage_id[leakage_index] == *voltage) {
3602                         *voltage = pLeakageTable->actual_voltage[leakage_index];
3603                         break;
3604                 }
3605         }
3606
3607         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
3608                 printk(KERN_ERR "[ powerplay ] Voltage value looks like a Leakage ID but it's not patched \n");
3609 }
3610
3611 /**
3612  * Patch voltage lookup table by EVV leakages.
3613  *
3614  * @param     hwmgr  the address of the powerplay hardware manager.
3615  * @param     pointer to voltage lookup table
3616  * @param     pointer to leakage table
3617  * @return     always 0
3618  */
3619 static int tonga_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
3620                 phm_ppt_v1_voltage_lookup_table *lookup_table,
3621                 phw_tonga_leakage_voltage *pLeakageTable)
3622 {
3623         uint32_t i;
3624
3625         for (i = 0; i < lookup_table->count; i++) {
3626                 tonga_patch_with_vdd_leakage(hwmgr,
3627                         &lookup_table->entries[i].us_vdd, pLeakageTable);
3628         }
3629
3630         return 0;
3631 }
3632
3633 static int tonga_patch_clock_voltage_lomits_with_vddc_leakage(struct pp_hwmgr *hwmgr,
3634                 phw_tonga_leakage_voltage *pLeakageTable, uint16_t *Vddc)
3635 {
3636         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3637
3638         tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddc, pLeakageTable);
3639         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
3640                 pptable_info->max_clock_voltage_on_dc.vddc;
3641
3642         return 0;
3643 }
3644
3645 static int tonga_patch_clock_voltage_limits_with_vddgfx_leakage(
3646                 struct pp_hwmgr *hwmgr, phw_tonga_leakage_voltage *pLeakageTable,
3647                 uint16_t *Vddgfx)
3648 {
3649         tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddgfx, pLeakageTable);
3650         return 0;
3651 }
3652
3653 int tonga_sort_lookup_table(struct pp_hwmgr *hwmgr,
3654                 phm_ppt_v1_voltage_lookup_table *lookup_table)
3655 {
3656         uint32_t table_size, i, j;
3657         phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
3658         table_size = lookup_table->count;
3659
3660         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
3661                 "Lookup table is empty", return -1);
3662
3663         /* Sorting voltages */
3664         for (i = 0; i < table_size - 1; i++) {
3665                 for (j = i + 1; j > 0; j--) {
3666                         if (lookup_table->entries[j].us_vdd < lookup_table->entries[j-1].us_vdd) {
3667                                 tmp_voltage_lookup_record = lookup_table->entries[j-1];
3668                                 lookup_table->entries[j-1] = lookup_table->entries[j];
3669                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
3670                         }
3671                 }
3672         }
3673
3674         return 0;
3675 }
3676
3677 static int tonga_complete_dependency_tables(struct pp_hwmgr *hwmgr)
3678 {
3679         int result = 0;
3680         int tmp_result;
3681         tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3682         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3683
3684         if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3685                 tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr,
3686                         pptable_info->vddgfx_lookup_table, &(data->vddcgfx_leakage));
3687                 if (tmp_result != 0)
3688                         result = tmp_result;
3689
3690                 tmp_result = tonga_patch_clock_voltage_limits_with_vddgfx_leakage(hwmgr,
3691                         &(data->vddcgfx_leakage), &pptable_info->max_clock_voltage_on_dc.vddgfx);
3692                 if (tmp_result != 0)
3693                         result = tmp_result;
3694         } else {
3695                 tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr,
3696                         pptable_info->vddc_lookup_table, &(data->vddc_leakage));
3697                 if (tmp_result != 0)
3698                         result = tmp_result;
3699
3700                 tmp_result = tonga_patch_clock_voltage_lomits_with_vddc_leakage(hwmgr,
3701                         &(data->vddc_leakage), &pptable_info->max_clock_voltage_on_dc.vddc);
3702                 if (tmp_result != 0)
3703                         result = tmp_result;
3704         }
3705
3706         tmp_result = tonga_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
3707         if (tmp_result != 0)
3708                 result = tmp_result;
3709
3710         tmp_result = tonga_calc_voltage_dependency_tables(hwmgr);
3711         if (tmp_result != 0)
3712                 result = tmp_result;
3713
3714         tmp_result = tonga_calc_mm_voltage_dependency_table(hwmgr);
3715         if (tmp_result != 0)
3716                 result = tmp_result;
3717
3718         tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddgfx_lookup_table);
3719         if (tmp_result != 0)
3720                 result = tmp_result;
3721
3722         tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddc_lookup_table);
3723         if (tmp_result != 0)
3724                 result = tmp_result;
3725
3726         return result;
3727 }
3728
3729 int tonga_init_sclk_threshold(struct pp_hwmgr *hwmgr)
3730 {
3731         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3732         data->low_sclk_interrupt_threshold = 0;
3733
3734         return 0;
3735 }
3736
3737 int tonga_setup_asic_task(struct pp_hwmgr *hwmgr)
3738 {
3739         int tmp_result, result = 0;
3740
3741         tmp_result = tonga_read_clock_registers(hwmgr);
3742         PP_ASSERT_WITH_CODE((0 == tmp_result),
3743                 "Failed to read clock registers!", result = tmp_result);
3744
3745         tmp_result = tonga_get_memory_type(hwmgr);
3746         PP_ASSERT_WITH_CODE((0 == tmp_result),
3747                 "Failed to get memory type!", result = tmp_result);
3748
3749         tmp_result = tonga_enable_acpi_power_management(hwmgr);
3750         PP_ASSERT_WITH_CODE((0 == tmp_result),
3751                 "Failed to enable ACPI power management!", result = tmp_result);
3752
3753         tmp_result = tonga_init_power_gate_state(hwmgr);
3754         PP_ASSERT_WITH_CODE((0 == tmp_result),
3755                 "Failed to init power gate state!", result = tmp_result);
3756
3757         tmp_result = tonga_get_mc_microcode_version(hwmgr);
3758         PP_ASSERT_WITH_CODE((0 == tmp_result),
3759                 "Failed to get MC microcode version!", result = tmp_result);
3760
3761         tmp_result = tonga_init_sclk_threshold(hwmgr);
3762         PP_ASSERT_WITH_CODE((0 == tmp_result),
3763                 "Failed to init sclk threshold!", result = tmp_result);
3764
3765         return result;
3766 }
3767
3768 /**
3769  * Enable voltage control
3770  *
3771  * @param    hwmgr  the address of the powerplay hardware manager.
3772  * @return   always 0
3773  */
3774 int tonga_enable_voltage_control(struct pp_hwmgr *hwmgr)
3775 {
3776         /* enable voltage control */
3777         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
3778
3779         return 0;
3780 }
3781
3782 /**
3783  * Checks if we want to support voltage control
3784  *
3785  * @param    hwmgr  the address of the powerplay hardware manager.
3786  */
3787 bool cf_tonga_voltage_control(const struct pp_hwmgr *hwmgr)
3788 {
3789         const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3790
3791         return(TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control);
3792 }
3793
3794 /*---------------------------MC----------------------------*/
3795
3796 uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)
3797 {
3798         return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
3799 }
3800
3801 bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg)
3802 {
3803         bool result = 1;
3804
3805         switch (inReg) {
3806         case  mmMC_SEQ_RAS_TIMING:
3807                 *outReg = mmMC_SEQ_RAS_TIMING_LP;
3808                 break;
3809
3810         case  mmMC_SEQ_DLL_STBY:
3811                 *outReg = mmMC_SEQ_DLL_STBY_LP;
3812                 break;
3813
3814         case  mmMC_SEQ_G5PDX_CMD0:
3815                 *outReg = mmMC_SEQ_G5PDX_CMD0_LP;
3816                 break;
3817
3818         case  mmMC_SEQ_G5PDX_CMD1:
3819                 *outReg = mmMC_SEQ_G5PDX_CMD1_LP;
3820                 break;
3821
3822         case  mmMC_SEQ_G5PDX_CTRL:
3823                 *outReg = mmMC_SEQ_G5PDX_CTRL_LP;
3824                 break;
3825
3826         case mmMC_SEQ_CAS_TIMING:
3827                 *outReg = mmMC_SEQ_CAS_TIMING_LP;
3828                 break;
3829
3830         case mmMC_SEQ_MISC_TIMING:
3831                 *outReg = mmMC_SEQ_MISC_TIMING_LP;
3832                 break;
3833
3834         case mmMC_SEQ_MISC_TIMING2:
3835                 *outReg = mmMC_SEQ_MISC_TIMING2_LP;
3836                 break;
3837
3838         case mmMC_SEQ_PMG_DVS_CMD:
3839                 *outReg = mmMC_SEQ_PMG_DVS_CMD_LP;
3840                 break;
3841
3842         case mmMC_SEQ_PMG_DVS_CTL:
3843                 *outReg = mmMC_SEQ_PMG_DVS_CTL_LP;
3844                 break;
3845
3846         case mmMC_SEQ_RD_CTL_D0:
3847                 *outReg = mmMC_SEQ_RD_CTL_D0_LP;
3848                 break;
3849
3850         case mmMC_SEQ_RD_CTL_D1:
3851                 *outReg = mmMC_SEQ_RD_CTL_D1_LP;
3852                 break;
3853
3854         case mmMC_SEQ_WR_CTL_D0:
3855                 *outReg = mmMC_SEQ_WR_CTL_D0_LP;
3856                 break;
3857
3858         case mmMC_SEQ_WR_CTL_D1:
3859                 *outReg = mmMC_SEQ_WR_CTL_D1_LP;
3860                 break;
3861
3862         case mmMC_PMG_CMD_EMRS:
3863                 *outReg = mmMC_SEQ_PMG_CMD_EMRS_LP;
3864                 break;
3865
3866         case mmMC_PMG_CMD_MRS:
3867                 *outReg = mmMC_SEQ_PMG_CMD_MRS_LP;
3868                 break;
3869
3870         case mmMC_PMG_CMD_MRS1:
3871                 *outReg = mmMC_SEQ_PMG_CMD_MRS1_LP;
3872                 break;
3873
3874         case mmMC_SEQ_PMG_TIMING:
3875                 *outReg = mmMC_SEQ_PMG_TIMING_LP;
3876                 break;
3877
3878         case mmMC_PMG_CMD_MRS2:
3879                 *outReg = mmMC_SEQ_PMG_CMD_MRS2_LP;
3880                 break;
3881
3882         case mmMC_SEQ_WR_CTL_2:
3883                 *outReg = mmMC_SEQ_WR_CTL_2_LP;
3884                 break;
3885
3886         default:
3887                 result = 0;
3888                 break;
3889         }
3890
3891         return result;
3892 }
3893
3894 int tonga_set_s0_mc_reg_index(phw_tonga_mc_reg_table *table)
3895 {
3896         uint32_t i;
3897         uint16_t address;
3898
3899         for (i = 0; i < table->last; i++) {
3900                 table->mc_reg_address[i].s0 =
3901                         tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
3902                         ? address : table->mc_reg_address[i].s1;
3903         }
3904         return 0;
3905 }
3906
3907 int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_tonga_mc_reg_table *ni_table)
3908 {
3909         uint8_t i, j;
3910
3911         PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3912                 "Invalid VramInfo table.", return -1);
3913         PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
3914                 "Invalid VramInfo table.", return -1);
3915
3916         for (i = 0; i < table->last; i++) {
3917                 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
3918         }
3919         ni_table->last = table->last;
3920
3921         for (i = 0; i < table->num_entries; i++) {
3922                 ni_table->mc_reg_table_entry[i].mclk_max =
3923                         table->mc_reg_table_entry[i].mclk_max;
3924                 for (j = 0; j < table->last; j++) {
3925                         ni_table->mc_reg_table_entry[i].mc_data[j] =
3926                                 table->mc_reg_table_entry[i].mc_data[j];
3927                 }
3928         }
3929         ni_table->num_entries = table->num_entries;
3930
3931         return 0;
3932 }
3933
3934 /**
3935  * VBIOS omits some information to reduce size, we need to recover them here.
3936  * 1.   when we see mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to  mmMC_PMG_CMD_EMRS /_LP[15:0].
3937  *      Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0]
3938  * 2.   when we see mmMC_SEQ_RESERVE_M, bit[15:0] EMRS2, need to be write to mmMC_PMG_CMD_MRS1/_LP[15:0].
3939  * 3.   need to set these data for each clock range
3940  *
3941  * @param    hwmgr the address of the powerplay hardware manager.
3942  * @param    table the address of MCRegTable
3943  * @return   always 0
3944  */
3945 int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, phw_tonga_mc_reg_table *table)
3946 {
3947         uint8_t i, j, k;
3948         uint32_t temp_reg;
3949         const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3950
3951         for (i = 0, j = table->last; i < table->last; i++) {
3952                 PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3953                         "Invalid VramInfo table.", return -1);
3954                 switch (table->mc_reg_address[i].s1) {
3955                 /*
3956                 * mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to  mmMC_PMG_CMD_EMRS /_LP[15:0].
3957                 * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0]
3958                 */
3959                 case mmMC_SEQ_MISC1:
3960                         temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
3961                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
3962                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
3963                         for (k = 0; k < table->num_entries; k++) {
3964                                 table->mc_reg_table_entry[k].mc_data[j] =
3965                                         ((temp_reg & 0xffff0000)) |
3966                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3967                         }
3968                         j++;
3969                         PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3970                                 "Invalid VramInfo table.", return -1);
3971
3972                         temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
3973                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
3974                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
3975                         for (k = 0; k < table->num_entries; k++) {
3976                                 table->mc_reg_table_entry[k].mc_data[j] =
3977                                         (temp_reg & 0xffff0000) |
3978                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3979
3980                                 if (!data->is_memory_GDDR5) {
3981                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3982                                 }
3983                         }
3984                         j++;
3985                         PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3986                                 "Invalid VramInfo table.", return -1);
3987
3988                         if (!data->is_memory_GDDR5) {
3989                                 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
3990                                 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
3991                                 for (k = 0; k < table->num_entries; k++) {
3992                                         table->mc_reg_table_entry[k].mc_data[j] =
3993                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3994                                 }
3995                                 j++;
3996                                 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3997                                         "Invalid VramInfo table.", return -1);
3998                         }
3999
4000                         break;
4001
4002                 case mmMC_SEQ_RESERVE_M:
4003                         temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
4004                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
4005                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
4006                         for (k = 0; k < table->num_entries; k++) {
4007                                 table->mc_reg_table_entry[k].mc_data[j] =
4008                                         (temp_reg & 0xffff0000) |
4009                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4010                         }
4011                         j++;
4012                         PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
4013                                 "Invalid VramInfo table.", return -1);
4014                         break;
4015
4016                 default:
4017                         break;
4018                 }
4019
4020         }
4021
4022         table->last = j;
4023
4024         return 0;
4025 }
4026
4027 int tonga_set_valid_flag(phw_tonga_mc_reg_table *table)
4028 {
4029         uint8_t i, j;
4030         for (i = 0; i < table->last; i++) {
4031                 for (j = 1; j < table->num_entries; j++) {
4032                         if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4033                                 table->mc_reg_table_entry[j].mc_data[i]) {
4034                                 table->validflag |= (1<<i);
4035                                 break;
4036                         }
4037                 }
4038         }
4039
4040         return 0;
4041 }
4042
4043 int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
4044 {
4045         int result;
4046         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
4047         pp_atomctrl_mc_reg_table *table;
4048         phw_tonga_mc_reg_table *ni_table = &data->tonga_mc_reg_table;
4049         uint8_t module_index = tonga_get_memory_modile_index(hwmgr);
4050
4051         table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
4052
4053         if (NULL == table)
4054                 return -1;
4055
4056         /* Program additional LP registers that are no longer programmed by VBIOS */
4057         cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
4058         cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
4059         cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
4060         cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
4061         cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
4062         cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
4063         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
4064         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
4065         cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
4066         cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
4067         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
4068         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
4069         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
4070         cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
4071         cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
4072         cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
4073         cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
4074         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
4075         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
4076         cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
4077
4078         memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
4079
4080         result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
4081
4082         if (0 == result)
4083                 result = tonga_copy_vbios_smc_reg_table(table, ni_table);
4084
4085         if (0 == result) {
4086                 tonga_set_s0_mc_reg_index(ni_table);
4087                 result = tonga_set_mc_special_registers(hwmgr, ni_table);
4088         }
4089
4090         if (0 == result)
4091                 tonga_set_valid_flag(ni_table);
4092
4093         kfree(table);
4094         return result;
4095 }
4096
4097 /*
4098 * Copy one arb setting to another and then switch the active set.
4099 * arbFreqSrc and arbFreqDest is one of the MC_CG_ARB_FREQ_Fx constants.
4100 */
4101 int tonga_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
4102                 uint32_t arbFreqSrc, uint32_t arbFreqDest)
4103 {
4104         uint32_t mc_arb_dram_timing;
4105         uint32_t mc_arb_dram_timing2;
4106         uint32_t burst_time;
4107         uint32_t mc_cg_config;
4108
4109         switch (arbFreqSrc) {
4110         case MC_CG_ARB_FREQ_F0:
4111                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
4112                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
4113                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
4114                 break;
4115
4116         case MC_CG_ARB_FREQ_F1:
4117                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
4118                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
4119                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
4120                 break;
4121
4122         default:
4123                 return -1;
4124         }
4125
4126         switch (arbFreqDest) {
4127         case MC_CG_ARB_FREQ_F0:
4128                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
4129                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
4130                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
4131                 break;
4132
4133         case MC_CG_ARB_FREQ_F1:
4134                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
4135                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
4136                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
4137                 break;
4138
4139         default:
4140                 return -1;
4141         }
4142
4143         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
4144         mc_cg_config |= 0x0000000F;
4145         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
4146         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arbFreqDest);
4147
4148         return 0;
4149 }
4150
4151 /**
4152  * Initial switch from ARB F0->F1
4153  *
4154  * @param    hwmgr  the address of the powerplay hardware manager.
4155  * @return   always 0
4156  * This function is to be called from the SetPowerState table.
4157  */
4158 int tonga_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr)
4159 {
4160         return tonga_copy_and_switch_arb_sets(hwmgr, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4161 }
4162
4163 /**
4164  * Initialize the ARB DRAM timing table's index field.
4165  *
4166  * @param    hwmgr  the address of the powerplay hardware manager.
4167  * @return   always 0
4168  */
4169 int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
4170 {
4171         const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4172         uint32_t tmp;
4173         int result;
4174
4175         /*
4176         * This is a read-modify-write on the first byte of the ARB table.
4177         * The first byte in the SMU72_Discrete_MCArbDramTimingTable structure is the field 'current'.
4178         * This solution is ugly, but we never write the whole table only individual fields in it.
4179         * In reality this field should not be in that structure but in a soft register.
4180         */
4181         result = tonga_read_smc_sram_dword(hwmgr->smumgr,
4182                                 data->arb_table_start, &tmp, data->sram_end);
4183
4184         if (0 != result)
4185                 return result;
4186
4187         tmp &= 0x00FFFFFF;
4188         tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
4189
4190         return tonga_write_smc_sram_dword(hwmgr->smumgr,
4191                         data->arb_table_start,  tmp, data->sram_end);
4192 }
4193
4194 int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU72_Discrete_MCRegisters *mc_reg_table)
4195 {
4196         const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4197
4198         uint32_t i, j;
4199
4200         for (i = 0, j = 0; j < data->tonga_mc_reg_table.last; j++) {
4201                 if (data->tonga_mc_reg_table.validflag & 1<<j) {
4202                         PP_ASSERT_WITH_CODE(i < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE,
4203                                 "Index of mc_reg_table->address[] array out of boundary", return -1);
4204                         mc_reg_table->address[i].s0 =
4205                                 PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s0);
4206                         mc_reg_table->address[i].s1 =
4207                                 PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s1);
4208                         i++;
4209                 }
4210         }
4211
4212         mc_reg_table->last = (uint8_t)i;
4213
4214         return 0;
4215 }
4216
4217 /*convert register values from driver to SMC format */
4218 void tonga_convert_mc_registers(
4219         const phw_tonga_mc_reg_entry * pEntry,
4220         SMU72_Discrete_MCRegisterSet *pData,
4221         uint32_t numEntries, uint32_t validflag)
4222 {
4223         uint32_t i, j;
4224
4225         for (i = 0, j = 0; j < numEntries; j++) {
4226                 if (validflag & 1<<j) {
4227                         pData->value[i] = PP_HOST_TO_SMC_UL(pEntry->mc_data[j]);
4228                         i++;
4229                 }
4230         }
4231 }
4232
4233 /* find the entry in the memory range table, then populate the value to SMC's tonga_mc_reg_table */
4234 int tonga_convert_mc_reg_table_entry_to_smc(
4235                 struct pp_hwmgr *hwmgr,
4236                 const uint32_t memory_clock,
4237                 SMU72_Discrete_MCRegisterSet *mc_reg_table_data
4238                 )
4239 {
4240         const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4241         uint32_t i = 0;
4242
4243         for (i = 0; i < data->tonga_mc_reg_table.num_entries; i++) {
4244                 if (memory_clock <=
4245                         data->tonga_mc_reg_table.mc_reg_table_entry[i].mclk_max) {
4246                         break;
4247                 }
4248         }
4249
4250         if ((i == data->tonga_mc_reg_table.num_entries) && (i > 0))
4251                 --i;
4252
4253         tonga_convert_mc_registers(&data->tonga_mc_reg_table.mc_reg_table_entry[i],
4254                 mc_reg_table_data, data->tonga_mc_reg_table.last, data->tonga_mc_reg_table.validflag);
4255
4256         return 0;
4257 }
4258
4259 int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
4260                 SMU72_Discrete_MCRegisters *mc_reg_table)
4261 {
4262         int result = 0;
4263         tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4264         int res;
4265         uint32_t i;
4266
4267         for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
4268                 res = tonga_convert_mc_reg_table_entry_to_smc(
4269                                 hwmgr,
4270                                 data->dpm_table.mclk_table.dpm_levels[i].value,
4271                                 &mc_reg_table->data[i]
4272                                 );
4273
4274                 if (0 != res)
4275                         result = res;
4276         }
4277
4278         return result;
4279 }
4280
4281 int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
4282 {
4283         int result;
4284         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4285
4286         memset(&data->mc_reg_table, 0x00, sizeof(SMU72_Discrete_MCRegisters));
4287         result = tonga_populate_mc_reg_address(hwmgr, &(data->mc_reg_table));
4288         PP_ASSERT_WITH_CODE(0 == result,
4289                 "Failed to initialize MCRegTable for the MC register addresses!", return result;);
4290
4291         result = tonga_convert_mc_reg_table_to_smc(hwmgr, &data->mc_reg_table);
4292         PP_ASSERT_WITH_CODE(0 == result,
4293                 "Failed to initialize MCRegTable for driver state!", return result;);
4294
4295         return tonga_copy_bytes_to_smc(hwmgr->smumgr, data->mc_reg_table_start,
4296                         (uint8_t *)&data->mc_reg_table, sizeof(SMU72_Discrete_MCRegisters), data->sram_end);
4297 }
4298
4299 /**
4300  * Programs static screed detection parameters
4301  *
4302  * @param   hwmgr  the address of the powerplay hardware manager.
4303  * @return   always 0
4304  */
4305 int tonga_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr)
4306 {
4307         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
4308
4309         /* Set static screen threshold unit*/
4310         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
4311                 CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
4312                 data->static_screen_threshold_unit);
4313         /* Set static screen threshold*/
4314         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
4315                 CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
4316                 data->static_screen_threshold);
4317
4318         return 0;
4319 }
4320
4321 /**
4322  * Setup display gap for glitch free memory clock switching.
4323  *
4324  * @param    hwmgr  the address of the powerplay hardware manager.
4325  * @return   always 0
4326  */
4327 int tonga_enable_display_gap(struct pp_hwmgr *hwmgr)
4328 {
4329         uint32_t display_gap = cgs_read_ind_register(hwmgr->device,
4330                                                         CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4331
4332         display_gap = PHM_SET_FIELD(display_gap,
4333                                         CG_DISPLAY_GAP_CNTL, DISP_GAP, DISPLAY_GAP_IGNORE);
4334
4335         display_gap = PHM_SET_FIELD(display_gap,
4336                                         CG_DISPLAY_GAP_CNTL, DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
4337
4338         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4339                 ixCG_DISPLAY_GAP_CNTL, display_gap);
4340
4341         return 0;
4342 }
4343
4344 /**
4345  * Programs activity state transition voting clients
4346  *
4347  * @param    hwmgr  the address of the powerplay hardware manager.
4348  * @return   always 0
4349  */
4350 int tonga_program_voting_clients(struct pp_hwmgr *hwmgr)
4351 {
4352         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
4353
4354         /* Clear reset for voting clients before enabling DPM */
4355         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4356                 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
4357         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4358                 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
4359
4360         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4361                 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
4362         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4363                 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
4364         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4365                 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
4366         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4367                 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
4368         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4369                 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
4370         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4371                 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
4372         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4373                 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
4374         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4375                 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
4376
4377         return 0;
4378 }
4379
4380
4381 int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
4382 {
4383         int tmp_result, result = 0;
4384
4385         tmp_result = tonga_check_for_dpm_stopped(hwmgr);
4386
4387         if (cf_tonga_voltage_control(hwmgr)) {
4388                 tmp_result = tonga_enable_voltage_control(hwmgr);
4389                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4390                         "Failed to enable voltage control!", result = tmp_result);
4391
4392                 tmp_result = tonga_construct_voltage_tables(hwmgr);
4393                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4394                         "Failed to contruct voltage tables!", result = tmp_result);
4395         }
4396
4397         tmp_result = tonga_initialize_mc_reg_table(hwmgr);
4398         PP_ASSERT_WITH_CODE((0 == tmp_result),
4399                 "Failed to initialize MC reg table!", result = tmp_result);
4400
4401         tmp_result = tonga_program_static_screen_threshold_parameters(hwmgr);
4402         PP_ASSERT_WITH_CODE((0 == tmp_result),
4403                 "Failed to program static screen threshold parameters!", result = tmp_result);
4404
4405         tmp_result = tonga_enable_display_gap(hwmgr);
4406         PP_ASSERT_WITH_CODE((0 == tmp_result),
4407                 "Failed to enable display gap!", result = tmp_result);
4408
4409         tmp_result = tonga_program_voting_clients(hwmgr);
4410         PP_ASSERT_WITH_CODE((0 == tmp_result),
4411                 "Failed to program voting clients!", result = tmp_result);
4412
4413         tmp_result = tonga_process_firmware_header(hwmgr);
4414         PP_ASSERT_WITH_CODE((0 == tmp_result),
4415                 "Failed to process firmware header!", result = tmp_result);
4416
4417         tmp_result = tonga_initial_switch_from_arb_f0_to_f1(hwmgr);
4418         PP_ASSERT_WITH_CODE((0 == tmp_result),
4419                 "Failed to initialize switch from ArbF0 to F1!", result = tmp_result);
4420
4421         tmp_result = tonga_init_smc_table(hwmgr);
4422         PP_ASSERT_WITH_CODE((0 == tmp_result),
4423                 "Failed to initialize SMC table!", result = tmp_result);
4424
4425         tmp_result = tonga_init_arb_table_index(hwmgr);
4426         PP_ASSERT_WITH_CODE((0 == tmp_result),
4427                 "Failed to initialize ARB table index!", result = tmp_result);
4428
4429         tmp_result = tonga_populate_initial_mc_reg_table(hwmgr);
4430         PP_ASSERT_WITH_CODE((0 == tmp_result),
4431                 "Failed to populate initialize MC Reg table!", result = tmp_result);
4432
4433         tmp_result = tonga_notify_smc_display_change(hwmgr, false);
4434         PP_ASSERT_WITH_CODE((0 == tmp_result),
4435                 "Failed to notify no display!", result = tmp_result);
4436
4437         /* enable SCLK control */
4438         tmp_result = tonga_enable_sclk_control(hwmgr);
4439         PP_ASSERT_WITH_CODE((0 == tmp_result),
4440                 "Failed to enable SCLK control!", result = tmp_result);
4441
4442         /* enable DPM */
4443         tmp_result = tonga_start_dpm(hwmgr);
4444         PP_ASSERT_WITH_CODE((0 == tmp_result),
4445                 "Failed to start DPM!", result = tmp_result);
4446
4447         return result;
4448 }
4449
4450 int tonga_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
4451 {
4452         int tmp_result, result = 0;
4453
4454         tmp_result = tonga_check_for_dpm_running(hwmgr);
4455         PP_ASSERT_WITH_CODE((0 == tmp_result),
4456                 "SMC is still running!", return 0);
4457
4458         tmp_result = tonga_stop_dpm(hwmgr);
4459         PP_ASSERT_WITH_CODE((0 == tmp_result),
4460                 "Failed to stop DPM!", result = tmp_result);
4461
4462         tmp_result = tonga_reset_to_default(hwmgr);
4463         PP_ASSERT_WITH_CODE((0 == tmp_result),
4464                 "Failed to reset to default!", result = tmp_result);
4465
4466         return result;
4467 }
4468
4469 int tonga_reset_asic_tasks(struct pp_hwmgr *hwmgr)
4470 {
4471         int result;
4472
4473         result = tonga_set_boot_state(hwmgr);
4474         if (0 != result)
4475                 printk(KERN_ERR "[ powerplay ] Failed to reset asic via set boot state! \n");
4476
4477         return result;
4478 }
4479
4480 int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
4481 {
4482         if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) {
4483                 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
4484                 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
4485         }
4486
4487         if (NULL != hwmgr->backend) {
4488                 kfree(hwmgr->backend);
4489                 hwmgr->backend = NULL;
4490         }
4491
4492         return 0;
4493 }
4494
4495 /**
4496  * Initializes the Volcanic Islands Hardware Manager
4497  *
4498  * @param   hwmgr the address of the powerplay hardware manager.
4499  * @return   1 if success; otherwise appropriate error code.
4500  */
4501 int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
4502 {
4503         int result = 0;
4504         SMU72_Discrete_DpmTable  *table = NULL;
4505         tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4506         pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
4507         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
4508         phw_tonga_ulv_parm *ulv;
4509
4510         PP_ASSERT_WITH_CODE((NULL != hwmgr),
4511                 "Invalid Parameter!", return -1;);
4512
4513         data->dll_defaule_on = 0;
4514         data->sram_end = SMC_RAM_END;
4515
4516         data->activity_target[0] = PPTONGA_TARGETACTIVITY_DFLT;
4517         data->activity_target[1] = PPTONGA_TARGETACTIVITY_DFLT;
4518         data->activity_target[2] = PPTONGA_TARGETACTIVITY_DFLT;
4519         data->activity_target[3] = PPTONGA_TARGETACTIVITY_DFLT;
4520         data->activity_target[4] = PPTONGA_TARGETACTIVITY_DFLT;
4521         data->activity_target[5] = PPTONGA_TARGETACTIVITY_DFLT;
4522         data->activity_target[6] = PPTONGA_TARGETACTIVITY_DFLT;
4523         data->activity_target[7] = PPTONGA_TARGETACTIVITY_DFLT;
4524
4525         data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
4526         data->vddc_vddgfx_delta = VDDC_VDDGFX_DELTA;
4527         data->mclk_activity_target = PPTONGA_MCLK_TARGETACTIVITY_DFLT;
4528
4529         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4530                 PHM_PlatformCaps_DisableVoltageIsland);
4531
4532         data->sclk_dpm_key_disabled = 0;
4533         data->mclk_dpm_key_disabled = 0;
4534         data->pcie_dpm_key_disabled = 0;
4535         data->pcc_monitor_enabled = 0;
4536
4537         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4538                 PHM_PlatformCaps_UnTabledHardwareInterface);
4539
4540         data->gpio_debug = 0;
4541         data->engine_clock_data = 0;
4542         data->memory_clock_data = 0;
4543         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4544                 PHM_PlatformCaps_DynamicPatchPowerState);
4545
4546         /* need to set voltage control types before EVV patching*/
4547         data->voltage_control = TONGA_VOLTAGE_CONTROL_NONE;
4548         data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_NONE;
4549         data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_NONE;
4550         data->mvdd_control = TONGA_VOLTAGE_CONTROL_NONE;
4551
4552         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
4553                                 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
4554                 data->voltage_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4555         }
4556
4557         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4558                         PHM_PlatformCaps_ControlVDDGFX)) {
4559                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
4560                         VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
4561                         data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4562                 }
4563         }
4564
4565         if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) {
4566                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4567                         PHM_PlatformCaps_ControlVDDGFX);
4568         }
4569
4570         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4571                         PHM_PlatformCaps_EnableMVDDControl)) {
4572                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
4573                                         VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) {
4574                         data->mvdd_control = TONGA_VOLTAGE_CONTROL_BY_GPIO;
4575                 }
4576         }
4577
4578         if (TONGA_VOLTAGE_CONTROL_NONE == data->mvdd_control) {
4579                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4580                         PHM_PlatformCaps_EnableMVDDControl);
4581         }
4582
4583         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4584                         PHM_PlatformCaps_ControlVDDCI)) {
4585                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
4586                                         VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
4587                         data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_GPIO;
4588                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
4589                                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
4590                         data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4591         }
4592
4593         if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_ci_control)
4594                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4595                 PHM_PlatformCaps_ControlVDDCI);
4596
4597         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4598                 PHM_PlatformCaps_TablelessHardwareInterface);
4599
4600         if (pptable_info->cac_dtp_table->usClockStretchAmount != 0)
4601                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4602                         PHM_PlatformCaps_ClockStretcher);
4603
4604         /* Initializes DPM default values*/
4605         tonga_initialize_dpm_defaults(hwmgr);
4606
4607         /* Get leakage voltage based on leakage ID.*/
4608         PP_ASSERT_WITH_CODE((0 == tonga_get_evv_voltage(hwmgr)),
4609                 "Get EVV Voltage Failed.  Abort Driver loading!", return -1);
4610
4611         tonga_complete_dependency_tables(hwmgr);
4612
4613         /* Parse pptable data read from VBIOS*/
4614         tonga_set_private_var_based_on_pptale(hwmgr);
4615
4616         /* ULV Support*/
4617         ulv = &(data->ulv);
4618         ulv->ulv_supported = 0;
4619
4620         /* Initalize Dynamic State Adjustment Rule Settings*/
4621         result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
4622         data->uvd_enabled = 0;
4623
4624         table = &(data->smc_state_table);
4625
4626         /*
4627         * if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable,
4628         * Peak Current Control feature is enabled and we should program PCC HW register
4629         */
4630         if (0 == atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
4631                 uint32_t temp_reg = cgs_read_ind_register(hwmgr->device,
4632                                                                                 CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
4633
4634                 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
4635                 case 0:
4636                         temp_reg = PHM_SET_FIELD(temp_reg,
4637                                 CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
4638                         break;
4639                 case 1:
4640                         temp_reg = PHM_SET_FIELD(temp_reg,
4641                                 CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
4642                         break;
4643                 case 2:
4644                         temp_reg = PHM_SET_FIELD(temp_reg,
4645                                 CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
4646                         break;
4647                 case 3:
4648                         temp_reg = PHM_SET_FIELD(temp_reg,
4649                                 CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
4650                         break;
4651                 case 4:
4652                         temp_reg = PHM_SET_FIELD(temp_reg,
4653                                 CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
4654                         break;
4655                 default:
4656                         printk(KERN_ERR "[ powerplay ] Failed to setup PCC HW register! \
4657                                 Wrong GPIO assigned for VDDC_PCC_GPIO_PINID! \n");
4658                         break;
4659                 }
4660                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4661                         ixCNB_PWRMGT_CNTL, temp_reg);
4662         }
4663
4664         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4665                 PHM_PlatformCaps_EnableSMU7ThermalManagement);
4666         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4667                 PHM_PlatformCaps_SMU7);
4668
4669         data->vddc_phase_shed_control = 0;
4670
4671         if (0 == result) {
4672                 data->is_tlu_enabled = 0;
4673                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
4674                         TONGA_MAX_HARDWARE_POWERLEVELS;
4675                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
4676                 hwmgr->platform_descriptor.minimumClocksReductionPercentage  = 50;
4677
4678                 data->pcie_gen_cap = 0x30007;
4679                 data->pcie_lane_cap = 0x2f0000;
4680         } else {
4681                 /* Ignore return value in here, we are cleaning up a mess. */
4682                 tonga_hwmgr_backend_fini(hwmgr);
4683         }
4684
4685         return result;
4686 }
4687
4688 static int tonga_force_dpm_level(struct pp_hwmgr *hwmgr,
4689                 enum amd_dpm_forced_level level)
4690 {
4691         int ret = 0;
4692
4693         switch (level) {
4694         case AMD_DPM_FORCED_LEVEL_HIGH:
4695                 ret = tonga_force_dpm_highest(hwmgr);
4696                 if (ret)
4697                         return ret;
4698                 break;
4699         case AMD_DPM_FORCED_LEVEL_LOW:
4700                 ret = tonga_force_dpm_lowest(hwmgr);
4701                 if (ret)
4702                         return ret;
4703                 break;
4704         case AMD_DPM_FORCED_LEVEL_AUTO:
4705                 ret = tonga_unforce_dpm_levels(hwmgr);
4706                 if (ret)
4707                         return ret;
4708                 break;
4709         default:
4710                 break;
4711         }
4712
4713         hwmgr->dpm_level = level;
4714         return ret;
4715 }
4716
4717 static int tonga_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
4718                                 struct pp_power_state  *prequest_ps,
4719                         const struct pp_power_state *pcurrent_ps)
4720 {
4721         struct tonga_power_state *tonga_ps =
4722                                 cast_phw_tonga_power_state(&prequest_ps->hardware);
4723
4724         uint32_t sclk;
4725         uint32_t mclk;
4726         struct PP_Clocks minimum_clocks = {0};
4727         bool disable_mclk_switching;
4728         bool disable_mclk_switching_for_frame_lock;
4729         struct cgs_display_info info = {0};
4730         const struct phm_clock_and_voltage_limits *max_limits;
4731         uint32_t i;
4732         tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4733         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
4734
4735         int32_t count;
4736         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
4737
4738         data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
4739
4740         PP_ASSERT_WITH_CODE(tonga_ps->performance_level_count == 2,
4741                                  "VI should always have 2 performance levels",
4742                                  );
4743
4744         max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
4745                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
4746                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
4747
4748         if (PP_PowerSource_DC == hwmgr->power_source) {
4749                 for (i = 0; i < tonga_ps->performance_level_count; i++) {
4750                         if (tonga_ps->performance_levels[i].memory_clock > max_limits->mclk)
4751                                 tonga_ps->performance_levels[i].memory_clock = max_limits->mclk;
4752                         if (tonga_ps->performance_levels[i].engine_clock > max_limits->sclk)
4753                                 tonga_ps->performance_levels[i].engine_clock = max_limits->sclk;
4754                 }
4755         }
4756
4757         tonga_ps->vce_clocks.EVCLK = hwmgr->vce_arbiter.evclk;
4758         tonga_ps->vce_clocks.ECCLK = hwmgr->vce_arbiter.ecclk;
4759
4760         tonga_ps->acp_clk = hwmgr->acp_arbiter.acpclk;
4761
4762         cgs_get_active_displays_info(hwmgr->device, &info);
4763
4764         /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
4765
4766         /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
4767
4768         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4769
4770                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
4771                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
4772
4773                 for (count = pptable_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
4774                         if (stable_pstate_sclk >= pptable_info->vdd_dep_on_sclk->entries[count].clk) {
4775                                 stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[count].clk;
4776                                 break;
4777                         }
4778                 }
4779
4780                 if (count < 0)
4781                         stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[0].clk;
4782
4783                 stable_pstate_mclk = max_limits->mclk;
4784
4785                 minimum_clocks.engineClock = stable_pstate_sclk;
4786                 minimum_clocks.memoryClock = stable_pstate_mclk;
4787         }
4788
4789         if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
4790                 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
4791
4792         if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
4793                 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
4794
4795         tonga_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
4796
4797         if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
4798                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.engineClock),
4799                                         "Overdrive sclk exceeds limit",
4800                                         hwmgr->gfx_arbiter.sclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.engineClock);
4801
4802                 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
4803                         tonga_ps->performance_levels[1].engine_clock = hwmgr->gfx_arbiter.sclk_over_drive;
4804         }
4805
4806         if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
4807                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.memoryClock),
4808                         "Overdrive mclk exceeds limit",
4809                         hwmgr->gfx_arbiter.mclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.memoryClock);
4810
4811                 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
4812                         tonga_ps->performance_levels[1].memory_clock = hwmgr->gfx_arbiter.mclk_over_drive;
4813         }
4814
4815         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
4816                                     hwmgr->platform_descriptor.platformCaps,
4817                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
4818
4819         disable_mclk_switching = (1 < info.display_count) ||
4820                                     disable_mclk_switching_for_frame_lock;
4821
4822         sclk  = tonga_ps->performance_levels[0].engine_clock;
4823         mclk  = tonga_ps->performance_levels[0].memory_clock;
4824
4825         if (disable_mclk_switching)
4826                 mclk  = tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].memory_clock;
4827
4828         if (sclk < minimum_clocks.engineClock)
4829                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? max_limits->sclk : minimum_clocks.engineClock;
4830
4831         if (mclk < minimum_clocks.memoryClock)
4832                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? max_limits->mclk : minimum_clocks.memoryClock;
4833
4834         tonga_ps->performance_levels[0].engine_clock = sclk;
4835         tonga_ps->performance_levels[0].memory_clock = mclk;
4836
4837         tonga_ps->performance_levels[1].engine_clock =
4838                 (tonga_ps->performance_levels[1].engine_clock >= tonga_ps->performance_levels[0].engine_clock) ?
4839                               tonga_ps->performance_levels[1].engine_clock :
4840                               tonga_ps->performance_levels[0].engine_clock;
4841
4842         if (disable_mclk_switching) {
4843                 if (mclk < tonga_ps->performance_levels[1].memory_clock)
4844                         mclk = tonga_ps->performance_levels[1].memory_clock;
4845
4846                 tonga_ps->performance_levels[0].memory_clock = mclk;
4847                 tonga_ps->performance_levels[1].memory_clock = mclk;
4848         } else {
4849                 if (tonga_ps->performance_levels[1].memory_clock < tonga_ps->performance_levels[0].memory_clock)
4850                         tonga_ps->performance_levels[1].memory_clock = tonga_ps->performance_levels[0].memory_clock;
4851         }
4852
4853         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4854                 for (i=0; i < tonga_ps->performance_level_count; i++) {
4855                         tonga_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
4856                         tonga_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
4857                         tonga_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
4858                         tonga_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
4859                 }
4860         }
4861
4862         return 0;
4863 }
4864
4865 int tonga_get_power_state_size(struct pp_hwmgr *hwmgr)
4866 {
4867         return sizeof(struct tonga_power_state);
4868 }
4869
4870 static int tonga_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
4871 {
4872         struct pp_power_state  *ps;
4873         struct tonga_power_state  *tonga_ps;
4874
4875         if (hwmgr == NULL)
4876                 return -EINVAL;
4877
4878         ps = hwmgr->request_ps;
4879
4880         if (ps == NULL)
4881                 return -EINVAL;
4882
4883         tonga_ps = cast_phw_tonga_power_state(&ps->hardware);
4884
4885         if (low)
4886                 return tonga_ps->performance_levels[0].memory_clock;
4887         else
4888                 return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
4889 }
4890
4891 static int tonga_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
4892 {
4893         struct pp_power_state  *ps;
4894         struct tonga_power_state  *tonga_ps;
4895
4896         if (hwmgr == NULL)
4897                 return -EINVAL;
4898
4899         ps = hwmgr->request_ps;
4900
4901         if (ps == NULL)
4902                 return -EINVAL;
4903
4904         tonga_ps = cast_phw_tonga_power_state(&ps->hardware);
4905
4906         if (low)
4907                 return tonga_ps->performance_levels[0].engine_clock;
4908         else
4909                 return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
4910 }
4911
4912 static uint16_t tonga_get_current_pcie_speed(
4913                                                    struct pp_hwmgr *hwmgr)
4914 {
4915         uint32_t speed_cntl = 0;
4916
4917         speed_cntl = cgs_read_ind_register(hwmgr->device,
4918                                                    CGS_IND_REG__PCIE,
4919                                                    ixPCIE_LC_SPEED_CNTL);
4920         return((uint16_t)PHM_GET_FIELD(speed_cntl,
4921                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4922 }
4923
4924 static int tonga_get_current_pcie_lane_number(
4925                                                    struct pp_hwmgr *hwmgr)
4926 {
4927         uint32_t link_width;
4928
4929         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device,
4930                                                         CGS_IND_REG__PCIE,
4931                                                   PCIE_LC_LINK_WIDTH_CNTL,
4932                                                         LC_LINK_WIDTH_RD);
4933
4934         PP_ASSERT_WITH_CODE((7 >= link_width),
4935                         "Invalid PCIe lane width!", return 0);
4936
4937         return decode_pcie_lane_width(link_width);
4938 }
4939
4940 static int tonga_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
4941                                         struct pp_hw_power_state *hw_ps)
4942 {
4943         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4944         struct tonga_power_state *ps = (struct tonga_power_state *)hw_ps;
4945         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
4946         uint16_t size;
4947         uint8_t frev, crev;
4948         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
4949
4950         /* First retrieve the Boot clocks and VDDC from the firmware info table.
4951          * We assume here that fw_info is unchanged if this call fails.
4952          */
4953         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
4954                         hwmgr->device, index,
4955                         &size, &frev, &crev);
4956         if (!fw_info)
4957                 /* During a test, there is no firmware info table. */
4958                 return 0;
4959
4960         /* Patch the state. */
4961         data->vbios_boot_state.sclk_bootup_value  = le32_to_cpu(fw_info->ulDefaultEngineClock);
4962         data->vbios_boot_state.mclk_bootup_value  = le32_to_cpu(fw_info->ulDefaultMemoryClock);
4963         data->vbios_boot_state.mvdd_bootup_value  = le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
4964         data->vbios_boot_state.vddc_bootup_value  = le16_to_cpu(fw_info->usBootUpVDDCVoltage);
4965         data->vbios_boot_state.vddci_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
4966         data->vbios_boot_state.pcie_gen_bootup_value = tonga_get_current_pcie_speed(hwmgr);
4967         data->vbios_boot_state.pcie_lane_bootup_value =
4968                         (uint16_t)tonga_get_current_pcie_lane_number(hwmgr);
4969
4970         /* set boot power state */
4971         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
4972         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
4973         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
4974         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
4975
4976         return 0;
4977 }
4978
4979 static int tonga_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
4980                 void *state, struct pp_power_state *power_state,
4981                 void *pp_table, uint32_t classification_flag)
4982 {
4983         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4984
4985         struct tonga_power_state  *tonga_ps =
4986                         (struct tonga_power_state *)(&(power_state->hardware));
4987
4988         struct tonga_performance_level *performance_level;
4989
4990         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
4991
4992         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
4993                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
4994
4995         ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
4996                         (ATOM_Tonga_SCLK_Dependency_Table *)
4997                         (((uint64_t)powerplay_table) +
4998                         le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
4999
5000         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
5001                         (ATOM_Tonga_MCLK_Dependency_Table *)
5002                         (((uint64_t)powerplay_table) +
5003                         le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
5004
5005         /* The following fields are not initialized here: id orderedList allStatesList */
5006         power_state->classification.ui_label =
5007                         (le16_to_cpu(state_entry->usClassification) &
5008                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
5009                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
5010         power_state->classification.flags = classification_flag;
5011         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
5012
5013         power_state->classification.temporary_state = false;
5014         power_state->classification.to_be_deleted = false;
5015
5016         power_state->validation.disallowOnDC =
5017                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_DISALLOW_ON_DC));
5018
5019         power_state->pcie.lanes = 0;
5020
5021         power_state->display.disableFrameModulation = false;
5022         power_state->display.limitRefreshrate = false;
5023         power_state->display.enableVariBright =
5024                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_ENABLE_VARIBRIGHT));
5025
5026         power_state->validation.supportedPowerLevels = 0;
5027         power_state->uvd_clocks.VCLK = 0;
5028         power_state->uvd_clocks.DCLK = 0;
5029         power_state->temperatures.min = 0;
5030         power_state->temperatures.max = 0;
5031
5032         performance_level = &(tonga_ps->performance_levels
5033                         [tonga_ps->performance_level_count++]);
5034
5035         PP_ASSERT_WITH_CODE(
5036                         (tonga_ps->performance_level_count < SMU72_MAX_LEVELS_GRAPHICS),
5037                         "Performance levels exceeds SMC limit!",
5038                         return -1);
5039
5040         PP_ASSERT_WITH_CODE(
5041                         (tonga_ps->performance_level_count <=
5042                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
5043                         "Performance levels exceeds Driver limit!",
5044                         return -1);
5045
5046         /* Performance levels are arranged from low to high. */
5047         performance_level->memory_clock =
5048                                 le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexLow].ulMclk);
5049
5050         performance_level->engine_clock =
5051                                 le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexLow].ulSclk);
5052
5053         performance_level->pcie_gen = get_pcie_gen_support(
5054                                                         data->pcie_gen_cap,
5055                                              state_entry->ucPCIEGenLow);
5056
5057         performance_level->pcie_lane = get_pcie_lane_support(
5058                                                     data->pcie_lane_cap,
5059                                            state_entry->ucPCIELaneHigh);
5060
5061         performance_level =
5062                         &(tonga_ps->performance_levels[tonga_ps->performance_level_count++]);
5063
5064         performance_level->memory_clock =
5065                                 le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexHigh].ulMclk);
5066
5067         performance_level->engine_clock =
5068                                 le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexHigh].ulSclk);
5069
5070         performance_level->pcie_gen = get_pcie_gen_support(
5071                                                         data->pcie_gen_cap,
5072                                             state_entry->ucPCIEGenHigh);
5073
5074         performance_level->pcie_lane = get_pcie_lane_support(
5075                                                     data->pcie_lane_cap,
5076                                            state_entry->ucPCIELaneHigh);
5077
5078         return 0;
5079 }
5080
5081 static int tonga_get_pp_table_entry(struct pp_hwmgr *hwmgr,
5082                     unsigned long entry_index, struct pp_power_state *ps)
5083 {
5084         int result;
5085         struct tonga_power_state *tonga_ps;
5086         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5087
5088         struct phm_ppt_v1_information *table_info =
5089                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
5090
5091         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
5092                                            table_info->vdd_dep_on_mclk;
5093
5094         ps->hardware.magic = PhwTonga_Magic;
5095
5096         tonga_ps = cast_phw_tonga_power_state(&(ps->hardware));
5097
5098         result = tonga_get_powerplay_table_entry(hwmgr, entry_index, ps,
5099                         tonga_get_pp_table_entry_callback_func);
5100
5101         /* This is the earliest time we have all the dependency table and the VBIOS boot state
5102          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
5103          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
5104          */
5105         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
5106                 if (dep_mclk_table->entries[0].clk !=
5107                                 data->vbios_boot_state.mclk_bootup_value)
5108                         printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
5109                                         "does not match VBIOS boot MCLK level");
5110                 if (dep_mclk_table->entries[0].vddci !=
5111                                 data->vbios_boot_state.vddci_bootup_value)
5112                         printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
5113                                         "does not match VBIOS boot VDDCI level");
5114         }
5115
5116         /* set DC compatible flag if this state supports DC */
5117         if (!ps->validation.disallowOnDC)
5118                 tonga_ps->dc_compatible = true;
5119
5120         if (ps->classification.flags & PP_StateClassificationFlag_ACPI)
5121                 data->acpi_pcie_gen = tonga_ps->performance_levels[0].pcie_gen;
5122         else if (ps->classification.flags & PP_StateClassificationFlag_Boot) {
5123                 if (data->bacos.best_match == 0xffff) {
5124                         /* For V.I. use boot state as base BACO state */
5125                         data->bacos.best_match = PP_StateClassificationFlag_Boot;
5126                         data->bacos.performance_level = tonga_ps->performance_levels[0];
5127                 }
5128         }
5129
5130         tonga_ps->uvd_clocks.VCLK = ps->uvd_clocks.VCLK;
5131         tonga_ps->uvd_clocks.DCLK = ps->uvd_clocks.DCLK;
5132
5133         if (!result) {
5134                 uint32_t i;
5135
5136                 switch (ps->classification.ui_label) {
5137                 case PP_StateUILabel_Performance:
5138                         data->use_pcie_performance_levels = true;
5139
5140                         for (i = 0; i < tonga_ps->performance_level_count; i++) {
5141                                 if (data->pcie_gen_performance.max <
5142                                                 tonga_ps->performance_levels[i].pcie_gen)
5143                                         data->pcie_gen_performance.max =
5144                                                         tonga_ps->performance_levels[i].pcie_gen;
5145
5146                                 if (data->pcie_gen_performance.min >
5147                                                 tonga_ps->performance_levels[i].pcie_gen)
5148                                         data->pcie_gen_performance.min =
5149                                                         tonga_ps->performance_levels[i].pcie_gen;
5150
5151                                 if (data->pcie_lane_performance.max <
5152                                                 tonga_ps->performance_levels[i].pcie_lane)
5153                                         data->pcie_lane_performance.max =
5154                                                         tonga_ps->performance_levels[i].pcie_lane;
5155
5156                                 if (data->pcie_lane_performance.min >
5157                                                 tonga_ps->performance_levels[i].pcie_lane)
5158                                         data->pcie_lane_performance.min =
5159                                                         tonga_ps->performance_levels[i].pcie_lane;
5160                         }
5161                         break;
5162                 case PP_StateUILabel_Battery:
5163                         data->use_pcie_power_saving_levels = true;
5164
5165                         for (i = 0; i < tonga_ps->performance_level_count; i++) {
5166                                 if (data->pcie_gen_power_saving.max <
5167                                                 tonga_ps->performance_levels[i].pcie_gen)
5168                                         data->pcie_gen_power_saving.max =
5169                                                         tonga_ps->performance_levels[i].pcie_gen;
5170
5171                                 if (data->pcie_gen_power_saving.min >
5172                                                 tonga_ps->performance_levels[i].pcie_gen)
5173                                         data->pcie_gen_power_saving.min =
5174                                                         tonga_ps->performance_levels[i].pcie_gen;
5175
5176                                 if (data->pcie_lane_power_saving.max <
5177                                                 tonga_ps->performance_levels[i].pcie_lane)
5178                                         data->pcie_lane_power_saving.max =
5179                                                         tonga_ps->performance_levels[i].pcie_lane;
5180
5181                                 if (data->pcie_lane_power_saving.min >
5182                                                 tonga_ps->performance_levels[i].pcie_lane)
5183                                         data->pcie_lane_power_saving.min =
5184                                                         tonga_ps->performance_levels[i].pcie_lane;
5185                         }
5186                         break;
5187                 default:
5188                         break;
5189                 }
5190         }
5191         return 0;
5192 }
5193
5194 static void
5195 tonga_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
5196 {
5197         uint32_t sclk, mclk;
5198
5199         smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetSclkFrequency));
5200
5201         sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5202
5203         smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetMclkFrequency));
5204
5205         mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5206         seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n", mclk/100, sclk/100);
5207 }
5208
5209 static int tonga_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
5210 {
5211         const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5212         const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5213         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5214         struct tonga_single_dpm_table *psclk_table = &(data->dpm_table.sclk_table);
5215         uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
5216         struct tonga_single_dpm_table *pmclk_table = &(data->dpm_table.mclk_table);
5217         uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
5218         struct PP_Clocks min_clocks = {0};
5219         uint32_t i;
5220         struct cgs_display_info info = {0};
5221
5222         data->need_update_smu7_dpm_table = 0;
5223
5224         for (i = 0; i < psclk_table->count; i++) {
5225                 if (sclk == psclk_table->dpm_levels[i].value)
5226                         break;
5227         }
5228
5229         if (i >= psclk_table->count)
5230                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
5231         else {
5232         /* TODO: Check SCLK in DAL's minimum clocks in case DeepSleep divider update is required.*/
5233                 if(data->display_timing.min_clock_insr != min_clocks.engineClockInSR)
5234                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
5235         }
5236
5237         for (i=0; i < pmclk_table->count; i++) {
5238                 if (mclk == pmclk_table->dpm_levels[i].value)
5239                         break;
5240         }
5241
5242         if (i >= pmclk_table->count)
5243                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
5244
5245         cgs_get_active_displays_info(hwmgr->device, &info);
5246
5247         if (data->display_timing.num_existing_displays != info.display_count)
5248                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
5249
5250         return 0;
5251 }
5252
5253 static uint16_t tonga_get_maximum_link_speed(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_ps)
5254 {
5255         uint32_t i;
5256         uint32_t sclk, max_sclk = 0;
5257         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5258         struct tonga_dpm_table *pdpm_table = &data->dpm_table;
5259
5260         for (i = 0; i < hw_ps->performance_level_count; i++) {
5261                 sclk = hw_ps->performance_levels[i].engine_clock;
5262                 if (max_sclk < sclk)
5263                         max_sclk = sclk;
5264         }
5265
5266         for (i = 0; i < pdpm_table->sclk_table.count; i++) {
5267                 if (pdpm_table->sclk_table.dpm_levels[i].value == max_sclk)
5268                         return (uint16_t) ((i >= pdpm_table->pcie_speed_table.count) ?
5269                                         pdpm_table->pcie_speed_table.dpm_levels[pdpm_table->pcie_speed_table.count-1].value :
5270                                         pdpm_table->pcie_speed_table.dpm_levels[i].value);
5271         }
5272
5273         return 0;
5274 }
5275
5276 static int tonga_request_link_speed_change_before_state_change(struct pp_hwmgr *hwmgr, const void *input)
5277 {
5278         const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5279         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5280         const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state);
5281         const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state);
5282
5283         uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_nps);
5284         uint16_t current_link_speed;
5285
5286         if (data->force_pcie_gen == PP_PCIEGenInvalid)
5287                 current_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_cps);
5288         else
5289                 current_link_speed = data->force_pcie_gen;
5290
5291         data->force_pcie_gen = PP_PCIEGenInvalid;
5292         data->pspp_notify_required = false;
5293         if (target_link_speed > current_link_speed) {
5294                 switch(target_link_speed) {
5295                 case PP_PCIEGen3:
5296                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
5297                                 break;
5298                         data->force_pcie_gen = PP_PCIEGen2;
5299                         if (current_link_speed == PP_PCIEGen2)
5300                                 break;
5301                 case PP_PCIEGen2:
5302                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
5303                                 break;
5304                 default:
5305                         data->force_pcie_gen = tonga_get_current_pcie_speed(hwmgr);
5306                         break;
5307                 }
5308         } else {
5309                 if (target_link_speed < current_link_speed)
5310                         data->pspp_notify_required = true;
5311         }
5312
5313         return 0;
5314 }
5315
5316 static int tonga_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
5317 {
5318         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5319
5320         if (0 == data->need_update_smu7_dpm_table)
5321                 return 0;
5322
5323         if ((0 == data->sclk_dpm_key_disabled) &&
5324                 (data->need_update_smu7_dpm_table &
5325                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
5326                 PP_ASSERT_WITH_CODE(
5327                         true == tonga_is_dpm_running(hwmgr),
5328                         "Trying to freeze SCLK DPM when DPM is disabled",
5329                         );
5330                 PP_ASSERT_WITH_CODE(
5331                         0 == smum_send_msg_to_smc(hwmgr->smumgr,
5332                                           PPSMC_MSG_SCLKDPM_FreezeLevel),
5333                         "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
5334                         return -1);
5335         }
5336
5337         if ((0 == data->mclk_dpm_key_disabled) &&
5338                 (data->need_update_smu7_dpm_table &
5339                  DPMTABLE_OD_UPDATE_MCLK)) {
5340                 PP_ASSERT_WITH_CODE(true == tonga_is_dpm_running(hwmgr),
5341                         "Trying to freeze MCLK DPM when DPM is disabled",
5342                         );
5343                 PP_ASSERT_WITH_CODE(
5344                         0 == smum_send_msg_to_smc(hwmgr->smumgr,
5345                                                         PPSMC_MSG_MCLKDPM_FreezeLevel),
5346                         "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
5347                         return -1);
5348         }
5349
5350         return 0;
5351 }
5352
5353 static int tonga_populate_and_upload_sclk_mclk_dpm_levels(struct pp_hwmgr *hwmgr, const void *input)
5354 {
5355         int result = 0;
5356
5357         const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5358         const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5359         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5360         uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
5361         uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
5362         struct tonga_dpm_table *pdpm_table = &data->dpm_table;
5363
5364         struct tonga_dpm_table *pgolden_dpm_table = &data->golden_dpm_table;
5365         uint32_t dpm_count, clock_percent;
5366         uint32_t i;
5367
5368         if (0 == data->need_update_smu7_dpm_table)
5369                 return 0;
5370
5371         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
5372                 pdpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value = sclk;
5373
5374                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
5375                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
5376                 /* Need to do calculation based on the golden DPM table
5377                  * as the Heatmap GPU Clock axis is also based on the default values
5378                  */
5379                         PP_ASSERT_WITH_CODE(
5380                                 (pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value != 0),
5381                                 "Divide by 0!",
5382                                 return -1);
5383                         dpm_count = pdpm_table->sclk_table.count < 2 ? 0 : pdpm_table->sclk_table.count-2;
5384                         for (i = dpm_count; i > 1; i--) {
5385                                 if (sclk > pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value) {
5386                                         clock_percent = ((sclk - pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value)*100) /
5387                                                         pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value;
5388
5389                                         pdpm_table->sclk_table.dpm_levels[i].value =
5390                                                         pgolden_dpm_table->sclk_table.dpm_levels[i].value +
5391                                                         (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100;
5392
5393                                 } else if (pgolden_dpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value > sclk) {
5394                                         clock_percent = ((pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value - sclk)*100) /
5395                                                                 pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value;
5396
5397                                         pdpm_table->sclk_table.dpm_levels[i].value =
5398                                                         pgolden_dpm_table->sclk_table.dpm_levels[i].value -
5399                                                         (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100;
5400                                 } else
5401                                         pdpm_table->sclk_table.dpm_levels[i].value =
5402                                                         pgolden_dpm_table->sclk_table.dpm_levels[i].value;
5403                         }
5404                 }
5405         }
5406
5407         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
5408                 pdpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value = mclk;
5409
5410                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
5411                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
5412
5413                         PP_ASSERT_WITH_CODE(
5414                                         (pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value != 0),
5415                                         "Divide by 0!",
5416                                         return -1);
5417                         dpm_count = pdpm_table->mclk_table.count < 2? 0 : pdpm_table->mclk_table.count-2;
5418                         for (i = dpm_count; i > 1; i--) {
5419                                 if (mclk > pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value) {
5420                                                 clock_percent = ((mclk - pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value)*100) /
5421                                                                     pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value;
5422
5423                                                 pdpm_table->mclk_table.dpm_levels[i].value =
5424                                                                                 pgolden_dpm_table->mclk_table.dpm_levels[i].value +
5425                                                                                 (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100;
5426
5427                                 } else if (pgolden_dpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value > mclk) {
5428                                                 clock_percent = ((pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value - mclk)*100) /
5429                                                                     pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value;
5430
5431                                                 pdpm_table->mclk_table.dpm_levels[i].value =
5432                                                                         pgolden_dpm_table->mclk_table.dpm_levels[i].value -
5433                                                                         (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100;
5434                                 } else
5435                                         pdpm_table->mclk_table.dpm_levels[i].value = pgolden_dpm_table->mclk_table.dpm_levels[i].value;
5436                         }
5437                 }
5438         }
5439
5440         if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
5441                 result = tonga_populate_all_memory_levels(hwmgr);
5442                 PP_ASSERT_WITH_CODE((0 == result),
5443                         "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
5444                         return result);
5445         }
5446
5447         if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
5448                 /*populate MCLK dpm table to SMU7 */
5449                 result = tonga_populate_all_memory_levels(hwmgr);
5450                 PP_ASSERT_WITH_CODE((0 == result),
5451                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
5452                                 return result);
5453         }
5454
5455         return result;
5456 }
5457
5458 static  int tonga_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
5459                           struct tonga_single_dpm_table * pdpm_table,
5460                              uint32_t low_limit, uint32_t high_limit)
5461 {
5462         uint32_t i;
5463
5464         for (i = 0; i < pdpm_table->count; i++) {
5465                 if ((pdpm_table->dpm_levels[i].value < low_limit) ||
5466                     (pdpm_table->dpm_levels[i].value > high_limit))
5467                         pdpm_table->dpm_levels[i].enabled = false;
5468                 else
5469                         pdpm_table->dpm_levels[i].enabled = true;
5470         }
5471         return 0;
5472 }
5473
5474 static int tonga_trim_dpm_states(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_state)
5475 {
5476         int result = 0;
5477         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5478         uint32_t high_limit_count;
5479
5480         PP_ASSERT_WITH_CODE((hw_state->performance_level_count >= 1),
5481                                 "power state did not have any performance level",
5482                                  return -1);
5483
5484         high_limit_count = (1 == hw_state->performance_level_count) ? 0: 1;
5485
5486         tonga_trim_single_dpm_states(hwmgr,
5487                                         &(data->dpm_table.sclk_table),
5488                                         hw_state->performance_levels[0].engine_clock,
5489                                         hw_state->performance_levels[high_limit_count].engine_clock);
5490
5491         tonga_trim_single_dpm_states(hwmgr,
5492                                                 &(data->dpm_table.mclk_table),
5493                                                 hw_state->performance_levels[0].memory_clock,
5494                                                 hw_state->performance_levels[high_limit_count].memory_clock);
5495
5496         return result;
5497 }
5498
5499 static int tonga_generate_dpm_level_enable_mask(struct pp_hwmgr *hwmgr, const void *input)
5500 {
5501         int result;
5502         const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5503         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5504         const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5505
5506
5507         result = tonga_trim_dpm_states(hwmgr, tonga_ps);
5508         if (0 != result)
5509                 return result;
5510
5511         data->dpm_level_enable_mask.sclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
5512         data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
5513         data->last_mclk_dpm_enable_mask = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
5514         if (data->uvd_enabled)
5515                 data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
5516
5517         data->dpm_level_enable_mask.pcie_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
5518
5519         return 0;
5520 }
5521
5522 int tonga_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
5523 {
5524         return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
5525                                   (PPSMC_Msg)PPSMC_MSG_VCEDPM_Enable :
5526                                   (PPSMC_Msg)PPSMC_MSG_VCEDPM_Disable);
5527 }
5528
5529 int tonga_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
5530 {
5531         return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
5532                                   (PPSMC_Msg)PPSMC_MSG_UVDDPM_Enable :
5533                                   (PPSMC_Msg)PPSMC_MSG_UVDDPM_Disable);
5534 }
5535
5536 int tonga_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
5537 {
5538         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5539         uint32_t mm_boot_level_offset, mm_boot_level_value;
5540         struct phm_ppt_v1_information *ptable_information = (struct phm_ppt_v1_information *)(hwmgr->pptable);
5541
5542         if (!bgate) {
5543                 data->smc_state_table.UvdBootLevel = (uint8_t) (ptable_information->mm_dep_table->count - 1);
5544                 mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
5545                 mm_boot_level_offset /= 4;
5546                 mm_boot_level_offset *= 4;
5547                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset);
5548                 mm_boot_level_value &= 0x00FFFFFF;
5549                 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
5550                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
5551
5552                 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM) ||
5553                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
5554                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5555                                                 PPSMC_MSG_UVDDPM_SetEnabledMask,
5556                                                 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
5557         }
5558
5559         return tonga_enable_disable_uvd_dpm(hwmgr, !bgate);
5560 }
5561
5562 int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
5563 {
5564         const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5565         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5566         const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state);
5567         const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state);
5568
5569         uint32_t mm_boot_level_offset, mm_boot_level_value;
5570         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
5571
5572         if (tonga_nps->vce_clocks.EVCLK > 0 && (tonga_cps == NULL || tonga_cps->vce_clocks.EVCLK == 0)) {
5573                 data->smc_state_table.VceBootLevel = (uint8_t) (pptable_info->mm_dep_table->count - 1);
5574
5575                 mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
5576                 mm_boot_level_offset /= 4;
5577                 mm_boot_level_offset *= 4;
5578                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset);
5579                 mm_boot_level_value &= 0xFF00FFFF;
5580                 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
5581                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
5582
5583                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
5584                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5585                                         PPSMC_MSG_VCEDPM_SetEnabledMask,
5586                                 (uint32_t)(1 << data->smc_state_table.VceBootLevel));
5587
5588                 tonga_enable_disable_vce_dpm(hwmgr, true);
5589         } else if (tonga_nps->vce_clocks.EVCLK == 0 && tonga_cps != NULL && tonga_cps->vce_clocks.EVCLK > 0)
5590                 tonga_enable_disable_vce_dpm(hwmgr, false);
5591
5592         return 0;
5593 }
5594
5595 static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
5596 {
5597         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5598
5599         uint32_t address;
5600         int32_t result;
5601
5602         if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
5603                 return 0;
5604
5605
5606         memset(&data->mc_reg_table, 0, sizeof(SMU72_Discrete_MCRegisters));
5607
5608         result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(data->mc_reg_table));
5609
5610         if(result != 0)
5611                 return result;
5612
5613
5614         address = data->mc_reg_table_start + (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]);
5615
5616         return  tonga_copy_bytes_to_smc(hwmgr->smumgr, address,
5617                                  (uint8_t *)&data->mc_reg_table.data[0],
5618                                 sizeof(SMU72_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
5619                                 data->sram_end);
5620 }
5621
5622 static int tonga_program_memory_timing_parameters_conditionally(struct pp_hwmgr *hwmgr)
5623 {
5624         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5625
5626         if (data->need_update_smu7_dpm_table &
5627                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
5628                 return tonga_program_memory_timing_parameters(hwmgr);
5629
5630         return 0;
5631 }
5632
5633 static int tonga_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
5634 {
5635         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5636
5637         if (0 == data->need_update_smu7_dpm_table)
5638                 return 0;
5639
5640         if ((0 == data->sclk_dpm_key_disabled) &&
5641                 (data->need_update_smu7_dpm_table &
5642                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
5643
5644                 PP_ASSERT_WITH_CODE(true == tonga_is_dpm_running(hwmgr),
5645                         "Trying to Unfreeze SCLK DPM when DPM is disabled",
5646                         );
5647                 PP_ASSERT_WITH_CODE(
5648                          0 == smum_send_msg_to_smc(hwmgr->smumgr,
5649                                          PPSMC_MSG_SCLKDPM_UnfreezeLevel),
5650                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
5651                         return -1);
5652         }
5653
5654         if ((0 == data->mclk_dpm_key_disabled) &&
5655                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
5656
5657                 PP_ASSERT_WITH_CODE(
5658                                 true == tonga_is_dpm_running(hwmgr),
5659                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",
5660                                 );
5661                 PP_ASSERT_WITH_CODE(
5662                          0 == smum_send_msg_to_smc(hwmgr->smumgr,
5663                                          PPSMC_MSG_SCLKDPM_UnfreezeLevel),
5664                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
5665                     return -1);
5666         }
5667
5668         data->need_update_smu7_dpm_table = 0;
5669
5670         return 0;
5671 }
5672
5673 static int tonga_notify_link_speed_change_after_state_change(struct pp_hwmgr *hwmgr, const void *input)
5674 {
5675         const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5676         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5677         const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5678         uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_ps);
5679         uint8_t  request;
5680
5681         if (data->pspp_notify_required  ||
5682             data->pcie_performance_request) {
5683                 if (target_link_speed == PP_PCIEGen3)
5684                         request = PCIE_PERF_REQ_GEN3;
5685                 else if (target_link_speed == PP_PCIEGen2)
5686                         request = PCIE_PERF_REQ_GEN2;
5687                 else
5688                         request = PCIE_PERF_REQ_GEN1;
5689
5690                 if(request == PCIE_PERF_REQ_GEN1 && tonga_get_current_pcie_speed(hwmgr) > 0) {
5691                         data->pcie_performance_request = false;
5692                         return 0;
5693                 }
5694
5695                 if (0 != acpi_pcie_perf_request(hwmgr->device, request, false)) {
5696                         if (PP_PCIEGen2 == target_link_speed)
5697                                 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
5698                         else
5699                                 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
5700                 }
5701         }
5702
5703         data->pcie_performance_request = false;
5704         return 0;
5705 }
5706
5707 static int tonga_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
5708 {
5709         int tmp_result, result = 0;
5710
5711         tmp_result = tonga_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
5712         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to find DPM states clocks in DPM table!", result = tmp_result);
5713
5714         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) {
5715                 tmp_result = tonga_request_link_speed_change_before_state_change(hwmgr, input);
5716                 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to request link speed change before state change!", result = tmp_result);
5717         }
5718
5719         tmp_result = tonga_freeze_sclk_mclk_dpm(hwmgr);
5720         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
5721
5722         tmp_result = tonga_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
5723         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to populate and upload SCLK MCLK DPM levels!", result = tmp_result);
5724
5725         tmp_result = tonga_generate_dpm_level_enable_mask(hwmgr, input);
5726         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to generate DPM level enabled mask!", result = tmp_result);
5727
5728         tmp_result = tonga_update_vce_dpm(hwmgr, input);
5729         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update VCE DPM!", result = tmp_result);
5730
5731         tmp_result = tonga_update_sclk_threshold(hwmgr);
5732         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update SCLK threshold!", result = tmp_result);
5733
5734         tmp_result = tonga_update_and_upload_mc_reg_table(hwmgr);
5735         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload MC reg table!", result = tmp_result);
5736
5737         tmp_result = tonga_program_memory_timing_parameters_conditionally(hwmgr);
5738         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to program memory timing parameters!", result = tmp_result);
5739
5740         tmp_result = tonga_unfreeze_sclk_mclk_dpm(hwmgr);
5741         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to unfreeze SCLK MCLK DPM!", result = tmp_result);
5742
5743         tmp_result = tonga_upload_dpm_level_enable_mask(hwmgr);
5744         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload DPM level enabled mask!", result = tmp_result);
5745
5746         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) {
5747                 tmp_result = tonga_notify_link_speed_change_after_state_change(hwmgr, input);
5748                 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to notify link speed change after state change!", result = tmp_result);
5749         }
5750
5751         return result;
5752 }
5753
5754 /**
5755 *  Set maximum target operating fan output PWM
5756 *
5757 * @param    pHwMgr:  the address of the powerplay hardware manager.
5758 * @param    usMaxFanPwm:  max operating fan PWM in percents
5759 * @return   The response that came from the SMC.
5760 */
5761 static int tonga_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
5762 {
5763         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
5764
5765         if (phm_is_hw_access_blocked(hwmgr))
5766                 return 0;
5767
5768     return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm) ? 0 : -EINVAL);
5769 }
5770
5771 int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
5772 {
5773         uint32_t num_active_displays = 0;
5774         struct cgs_display_info info = {0};
5775         info.mode_info = NULL;
5776
5777         cgs_get_active_displays_info(hwmgr->device, &info);
5778
5779         num_active_displays = info.display_count;
5780
5781         if (num_active_displays > 1)  /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
5782                 tonga_notify_smc_display_change(hwmgr, false);
5783         else
5784                 tonga_notify_smc_display_change(hwmgr, true);
5785
5786         return 0;
5787 }
5788
5789 /**
5790 * Programs the display gap
5791 *
5792 * @param    hwmgr  the address of the powerplay hardware manager.
5793 * @return   always OK
5794 */
5795 int tonga_program_display_gap(struct pp_hwmgr *hwmgr)
5796 {
5797         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5798         uint32_t num_active_displays = 0;
5799         uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
5800         uint32_t display_gap2;
5801         uint32_t pre_vbi_time_in_us;
5802         uint32_t frame_time_in_us;
5803         uint32_t ref_clock;
5804         uint32_t refresh_rate = 0;
5805         struct cgs_display_info info = {0};
5806         struct cgs_mode_info mode_info;
5807
5808         info.mode_info = &mode_info;
5809
5810         cgs_get_active_displays_info(hwmgr->device, &info);
5811         num_active_displays = info.display_count;
5812
5813         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0)? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
5814         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
5815
5816         ref_clock = mode_info.ref_clock;
5817         refresh_rate = mode_info.refresh_rate;
5818
5819         if(0 == refresh_rate)
5820                 refresh_rate = 60;
5821
5822         frame_time_in_us = 1000000 / refresh_rate;
5823
5824         pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
5825         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
5826
5827         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
5828
5829         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, PreVBlankGap), 0x64);
5830
5831         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
5832
5833         if (num_active_displays == 1)
5834                 tonga_notify_smc_display_change(hwmgr, true);
5835
5836         return 0;
5837 }
5838
5839 int tonga_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
5840 {
5841
5842         tonga_program_display_gap(hwmgr);
5843
5844         /* to do PhwTonga_CacUpdateDisplayConfiguration(pHwMgr); */
5845         return 0;
5846 }
5847
5848 /**
5849 *  Set maximum target operating fan output RPM
5850 *
5851 * @param    pHwMgr:  the address of the powerplay hardware manager.
5852 * @param    usMaxFanRpm:  max operating fan RPM value.
5853 * @return   The response that came from the SMC.
5854 */
5855 static int tonga_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
5856 {
5857         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = us_max_fan_pwm;
5858
5859         if (phm_is_hw_access_blocked(hwmgr))
5860                 return 0;
5861
5862         return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanRpmMax, us_max_fan_pwm) ? 0 : -EINVAL);
5863 }
5864
5865 uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr)
5866 {
5867         uint32_t reference_clock;
5868         uint32_t tc;
5869         uint32_t divide;
5870
5871         ATOM_FIRMWARE_INFO *fw_info;
5872         uint16_t size;
5873         uint8_t frev, crev;
5874         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5875
5876         tc = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
5877
5878         if (tc)
5879                 return TCLK;
5880
5881         fw_info = (ATOM_FIRMWARE_INFO *)cgs_atom_get_data_table(hwmgr->device, index,
5882                                                   &size, &frev, &crev);
5883
5884         if (!fw_info)
5885                 return 0;
5886
5887         reference_clock = le16_to_cpu(fw_info->usMinPixelClockPLL_Output);
5888
5889         divide = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
5890
5891         if (0 != divide)
5892                 return reference_clock / 4;
5893
5894         return reference_clock;
5895 }
5896
5897 int tonga_dpm_set_interrupt_state(void *private_data,
5898                                          unsigned src_id, unsigned type,
5899                                          int enabled)
5900 {
5901         uint32_t cg_thermal_int;
5902         struct pp_hwmgr *hwmgr = ((struct pp_eventmgr *)private_data)->hwmgr;
5903
5904         if (hwmgr == NULL)
5905                 return -EINVAL;
5906
5907         switch (type) {
5908         case AMD_THERMAL_IRQ_LOW_TO_HIGH:
5909                 if (enabled) {
5910                         cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5911                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5912                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5913                 } else {
5914                         cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5915                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5916                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5917                 }
5918                 break;
5919
5920         case AMD_THERMAL_IRQ_HIGH_TO_LOW:
5921                 if (enabled) {
5922                         cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5923                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5924                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5925                 } else {
5926                         cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5927                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5928                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5929                 }
5930                 break;
5931         default:
5932                 break;
5933         }
5934         return 0;
5935 }
5936
5937 int tonga_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
5938                                         const void *thermal_interrupt_info)
5939 {
5940         int result;
5941         const struct pp_interrupt_registration_info *info =
5942                         (const struct pp_interrupt_registration_info *)thermal_interrupt_info;
5943
5944         if (info == NULL)
5945                 return -EINVAL;
5946
5947         result = cgs_add_irq_source(hwmgr->device, 230, AMD_THERMAL_IRQ_LAST,
5948                                 tonga_dpm_set_interrupt_state,
5949                                 info->call_back, info->context);
5950
5951         if (result)
5952                 return -EINVAL;
5953
5954         result = cgs_add_irq_source(hwmgr->device, 231, AMD_THERMAL_IRQ_LAST,
5955                                 tonga_dpm_set_interrupt_state,
5956                                 info->call_back, info->context);
5957
5958         if (result)
5959                 return -EINVAL;
5960
5961         return 0;
5962 }
5963
5964 bool tonga_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
5965 {
5966         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5967         bool is_update_required = false;
5968         struct cgs_display_info info = {0,0,NULL};
5969
5970         cgs_get_active_displays_info(hwmgr->device, &info);
5971
5972         if (data->display_timing.num_existing_displays != info.display_count)
5973                 is_update_required = true;
5974 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
5975         if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
5976                 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
5977                 if(min_clocks.engineClockInSR != data->display_timing.minClockInSR)
5978                         is_update_required = true;
5979 */
5980         return is_update_required;
5981 }
5982
5983 static inline bool tonga_are_power_levels_equal(const struct tonga_performance_level *pl1,
5984                                                            const struct tonga_performance_level *pl2)
5985 {
5986         return ((pl1->memory_clock == pl2->memory_clock) &&
5987                   (pl1->engine_clock == pl2->engine_clock) &&
5988                   (pl1->pcie_gen == pl2->pcie_gen) &&
5989                   (pl1->pcie_lane == pl2->pcie_lane));
5990 }
5991
5992 int tonga_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
5993 {
5994         const struct tonga_power_state *psa = cast_const_phw_tonga_power_state(pstate1);
5995         const struct tonga_power_state *psb = cast_const_phw_tonga_power_state(pstate2);
5996         int i;
5997
5998         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
5999                 return -EINVAL;
6000
6001         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
6002         if (psa->performance_level_count != psb->performance_level_count) {
6003                 *equal = false;
6004                 return 0;
6005         }
6006
6007         for (i = 0; i < psa->performance_level_count; i++) {
6008                 if (!tonga_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
6009                         /* If we have found even one performance level pair that is different the states are different. */
6010                         *equal = false;
6011                         return 0;
6012                 }
6013         }
6014
6015         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
6016         *equal = ((psa->uvd_clocks.VCLK == psb->uvd_clocks.VCLK) && (psa->uvd_clocks.DCLK == psb->uvd_clocks.DCLK));
6017         *equal &= ((psa->vce_clocks.EVCLK == psb->vce_clocks.EVCLK) && (psa->vce_clocks.ECCLK == psb->vce_clocks.ECCLK));
6018         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
6019         *equal &= (psa->acp_clk == psb->acp_clk);
6020
6021         return 0;
6022 }
6023
6024 static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
6025         .backend_init = &tonga_hwmgr_backend_init,
6026         .backend_fini = &tonga_hwmgr_backend_fini,
6027         .asic_setup = &tonga_setup_asic_task,
6028         .dynamic_state_management_enable = &tonga_enable_dpm_tasks,
6029         .apply_state_adjust_rules = tonga_apply_state_adjust_rules,
6030         .force_dpm_level = &tonga_force_dpm_level,
6031         .power_state_set = tonga_set_power_state_tasks,
6032         .get_power_state_size = tonga_get_power_state_size,
6033         .get_mclk = tonga_dpm_get_mclk,
6034         .get_sclk = tonga_dpm_get_sclk,
6035         .patch_boot_state = tonga_dpm_patch_boot_state,
6036         .get_pp_table_entry = tonga_get_pp_table_entry,
6037         .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
6038         .print_current_perforce_level = tonga_print_current_perforce_level,
6039         .powerdown_uvd = tonga_phm_powerdown_uvd,
6040         .powergate_uvd = tonga_phm_powergate_uvd,
6041         .powergate_vce = tonga_phm_powergate_vce,
6042         .disable_clock_power_gating = tonga_phm_disable_clock_power_gating,
6043         .notify_smc_display_config_after_ps_adjustment = tonga_notify_smc_display_config_after_ps_adjustment,
6044         .display_config_changed = tonga_display_configuration_changed_task,
6045         .set_max_fan_pwm_output = tonga_set_max_fan_pwm_output,
6046         .set_max_fan_rpm_output = tonga_set_max_fan_rpm_output,
6047         .get_temperature = tonga_thermal_get_temperature,
6048         .stop_thermal_controller = tonga_thermal_stop_thermal_controller,
6049         .get_fan_speed_info = tonga_fan_ctrl_get_fan_speed_info,
6050         .get_fan_speed_percent = tonga_fan_ctrl_get_fan_speed_percent,
6051         .set_fan_speed_percent = tonga_fan_ctrl_set_fan_speed_percent,
6052         .reset_fan_speed_to_default = tonga_fan_ctrl_reset_fan_speed_to_default,
6053         .get_fan_speed_rpm = tonga_fan_ctrl_get_fan_speed_rpm,
6054         .set_fan_speed_rpm = tonga_fan_ctrl_set_fan_speed_rpm,
6055         .uninitialize_thermal_controller = tonga_thermal_ctrl_uninitialize_thermal_controller,
6056         .register_internal_thermal_interrupt = tonga_register_internal_thermal_interrupt,
6057         .check_smc_update_required_for_display_configuration = tonga_check_smc_update_required_for_display_configuration,
6058         .check_states_equal = tonga_check_states_equal,
6059 };
6060
6061 int tonga_hwmgr_init(struct pp_hwmgr *hwmgr)
6062 {
6063         tonga_hwmgr  *data;
6064
6065         data = kzalloc (sizeof(tonga_hwmgr), GFP_KERNEL);
6066         if (data == NULL)
6067                 return -ENOMEM;
6068         memset(data, 0x00, sizeof(tonga_hwmgr));
6069
6070         hwmgr->backend = data;
6071         hwmgr->hwmgr_func = &tonga_hwmgr_funcs;
6072         hwmgr->pptable_func = &tonga_pptable_funcs;
6073         pp_tonga_thermal_initialize(hwmgr);
6074         return 0;
6075 }
6076