2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
28 #include "ppatomctrl.h"
30 #define SMU7_MAX_HARDWARE_POWERLEVELS 2
32 #define SMU7_VOLTAGE_CONTROL_NONE 0x0
33 #define SMU7_VOLTAGE_CONTROL_BY_GPIO 0x1
34 #define SMU7_VOLTAGE_CONTROL_BY_SVID2 0x2
35 #define SMU7_VOLTAGE_CONTROL_MERGED 0x3
37 #define DPMTABLE_OD_UPDATE_SCLK 0x00000001
38 #define DPMTABLE_OD_UPDATE_MCLK 0x00000002
39 #define DPMTABLE_UPDATE_SCLK 0x00000004
40 #define DPMTABLE_UPDATE_MCLK 0x00000008
42 enum gpu_pt_config_reg_type {
43 GPU_CONFIGREG_MMR = 0,
44 GPU_CONFIGREG_SMC_IND,
45 GPU_CONFIGREG_DIDT_IND,
46 GPU_CONFIGREG_GC_CAC_IND,
51 struct gpu_pt_config_reg {
56 enum gpu_pt_config_reg_type type;
59 struct smu7_performance_level {
60 uint32_t memory_clock;
61 uint32_t engine_clock;
66 struct smu7_thermal_temperature_setting {
68 long temperature_high;
69 long temperature_shutdown;
72 struct smu7_uvd_clocks {
77 struct smu7_vce_clocks {
82 struct smu7_power_state {
84 struct smu7_uvd_clocks uvd_clks;
85 struct smu7_vce_clocks vce_clks;
87 uint16_t performance_level_count;
89 uint32_t sclk_threshold;
90 struct smu7_performance_level performance_levels[SMU7_MAX_HARDWARE_POWERLEVELS];
93 struct smu7_dpm_level {
99 #define SMU7_MAX_DEEPSLEEP_DIVIDER_ID 5
100 #define MAX_REGULAR_DPM_NUMBER 8
101 #define SMU7_MINIMUM_ENGINE_CLOCK 2500
103 struct smu7_single_dpm_table {
105 struct smu7_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
108 struct smu7_dpm_table {
109 struct smu7_single_dpm_table sclk_table;
110 struct smu7_single_dpm_table mclk_table;
111 struct smu7_single_dpm_table pcie_speed_table;
112 struct smu7_single_dpm_table vddc_table;
113 struct smu7_single_dpm_table vddci_table;
114 struct smu7_single_dpm_table mvdd_table;
117 struct smu7_clock_registers {
118 uint32_t vCG_SPLL_FUNC_CNTL;
119 uint32_t vCG_SPLL_FUNC_CNTL_2;
120 uint32_t vCG_SPLL_FUNC_CNTL_3;
121 uint32_t vCG_SPLL_FUNC_CNTL_4;
122 uint32_t vCG_SPLL_SPREAD_SPECTRUM;
123 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;
125 uint32_t vMCLK_PWRMGT_CNTL;
126 uint32_t vMPLL_AD_FUNC_CNTL;
127 uint32_t vMPLL_DQ_FUNC_CNTL;
128 uint32_t vMPLL_FUNC_CNTL;
129 uint32_t vMPLL_FUNC_CNTL_1;
130 uint32_t vMPLL_FUNC_CNTL_2;
135 #define DISABLE_MC_LOADMICROCODE 1
136 #define DISABLE_MC_CFGPROGRAMMING 2
138 struct smu7_voltage_smio_registers {
139 uint32_t vS0_VID_LOWER_SMIO_CNTL;
142 #define SMU7_MAX_LEAKAGE_COUNT 8
144 struct smu7_leakage_voltage {
146 uint16_t leakage_id[SMU7_MAX_LEAKAGE_COUNT];
147 uint16_t actual_voltage[SMU7_MAX_LEAKAGE_COUNT];
150 struct smu7_vbios_boot_state {
151 uint16_t mvdd_bootup_value;
152 uint16_t vddc_bootup_value;
153 uint16_t vddci_bootup_value;
154 uint16_t vddgfx_bootup_value;
155 uint32_t sclk_bootup_value;
156 uint32_t mclk_bootup_value;
157 uint16_t pcie_gen_bootup_value;
158 uint16_t pcie_lane_bootup_value;
161 struct smu7_display_timing {
162 uint32_t min_clock_in_sr;
163 uint32_t num_existing_displays;
166 struct smu7_dpmlevel_enable_mask {
167 uint32_t uvd_dpm_enable_mask;
168 uint32_t vce_dpm_enable_mask;
169 uint32_t acp_dpm_enable_mask;
170 uint32_t samu_dpm_enable_mask;
171 uint32_t sclk_dpm_enable_mask;
172 uint32_t mclk_dpm_enable_mask;
173 uint32_t pcie_dpm_enable_mask;
176 struct smu7_pcie_perf_range {
182 struct smu7_dpm_table dpm_table;
183 struct smu7_dpm_table golden_dpm_table;
185 uint32_t voting_rights_clients[8];
186 uint32_t static_screen_threshold_unit;
187 uint32_t static_screen_threshold;
188 uint32_t voltage_control;
189 uint32_t vdd_gfx_control;
190 uint32_t vddc_vddgfx_delta;
191 uint32_t active_auto_throttle_sources;
193 struct smu7_clock_registers clock_registers;
195 bool is_memory_gddr5;
197 bool pspp_notify_required;
198 uint16_t force_pcie_gen;
199 uint16_t acpi_pcie_gen;
200 uint32_t pcie_gen_cap;
201 uint32_t pcie_lane_cap;
202 uint32_t pcie_spc_cap;
203 struct smu7_leakage_voltage vddc_leakage;
204 struct smu7_leakage_voltage vddci_leakage;
205 struct smu7_leakage_voltage vddcgfx_leakage;
207 uint32_t mvdd_control;
208 uint32_t vddc_mask_low;
209 uint32_t mvdd_mask_low;
210 uint16_t max_vddc_in_pptable;
211 uint16_t min_vddc_in_pptable;
212 uint16_t max_vddci_in_pptable;
213 uint16_t min_vddci_in_pptable;
215 struct smu7_vbios_boot_state vbios_boot_state;
217 bool pcie_performance_request;
220 bool disable_handshake;
221 bool smc_voltage_control_enabled;
222 bool vbi_time_out_support;
224 uint32_t soft_regs_start;
225 /* ---- Stuff originally coming from Evergreen ---- */
226 uint32_t vddci_control;
227 struct pp_atomctrl_voltage_table vddc_voltage_table;
228 struct pp_atomctrl_voltage_table vddci_voltage_table;
229 struct pp_atomctrl_voltage_table mvdd_voltage_table;
230 struct pp_atomctrl_voltage_table vddgfx_voltage_table;
232 uint32_t mgcg_cgtt_local2;
233 uint32_t mgcg_cgtt_local3;
235 uint32_t mc_micro_code_feature;
236 uint32_t highest_mclk;
238 uint8_t mvdd_high_index;
239 uint8_t mvdd_low_index;
241 bool performance_request_registered;
243 /* ---- Low Power Features ---- */
246 /* ---- CAC Stuff ---- */
247 uint32_t cac_table_start;
248 bool cac_configuration_required;
249 bool driver_calculate_cac_leakage;
252 /* ---- DPM2 Parameters ---- */
253 uint32_t power_containment_features;
254 bool enable_dte_feature;
255 bool enable_tdc_limit_feature;
256 bool enable_pkg_pwr_tracking_feature;
257 bool disable_uvd_power_tune_feature;
260 uint32_t dte_tj_offset;
261 uint32_t fast_watermark_threshold;
263 /* ---- Phase Shedding ---- */
264 uint8_t vddc_phase_shed_control;
266 /* ---- DI/DT ---- */
267 struct smu7_display_timing display_timing;
269 /* ---- Thermal Temperature Setting ---- */
270 struct smu7_thermal_temperature_setting thermal_temp_setting;
271 struct smu7_dpmlevel_enable_mask dpm_level_enable_mask;
272 uint32_t need_update_smu7_dpm_table;
273 uint32_t sclk_dpm_key_disabled;
274 uint32_t mclk_dpm_key_disabled;
275 uint32_t pcie_dpm_key_disabled;
276 uint32_t min_engine_clocks;
277 struct smu7_pcie_perf_range pcie_gen_performance;
278 struct smu7_pcie_perf_range pcie_lane_performance;
279 struct smu7_pcie_perf_range pcie_gen_power_saving;
280 struct smu7_pcie_perf_range pcie_lane_power_saving;
281 bool use_pcie_performance_levels;
282 bool use_pcie_power_saving_levels;
283 uint32_t mclk_activity_target;
284 uint32_t mclk_dpm0_activity_target;
285 uint32_t low_sclk_interrupt_threshold;
286 uint32_t last_mclk_dpm_enable_mask;
289 /* ---- Power Gating States ---- */
290 bool uvd_power_gated;
291 bool vce_power_gated;
292 bool samu_power_gated;
293 bool need_long_memory_training;
295 /* Application power optimization parameters */
297 bool update_down_hyst;
300 uint32_t disable_dpm_mask;
301 bool apply_optimized_settings;
303 uint32_t avfs_vdroop_override_setting;
304 bool apply_avfs_cks_off_voltage;
305 uint32_t frame_time_x2;
306 uint16_t mem_latency_high;
307 uint16_t mem_latency_low;
310 /* To convert to Q8.8 format for firmware */
311 #define SMU7_Q88_FORMAT_CONVERSION_UNIT 256
313 enum SMU7_I2CLineID {
314 SMU7_I2CLineID_DDC1 = 0x90,
315 SMU7_I2CLineID_DDC2 = 0x91,
316 SMU7_I2CLineID_DDC3 = 0x92,
317 SMU7_I2CLineID_DDC4 = 0x93,
318 SMU7_I2CLineID_DDC5 = 0x94,
319 SMU7_I2CLineID_DDC6 = 0x95,
320 SMU7_I2CLineID_SCLSDA = 0x96,
321 SMU7_I2CLineID_DDCVGA = 0x97
324 #define SMU7_I2C_DDC1DATA 0
325 #define SMU7_I2C_DDC1CLK 1
326 #define SMU7_I2C_DDC2DATA 2
327 #define SMU7_I2C_DDC2CLK 3
328 #define SMU7_I2C_DDC3DATA 4
329 #define SMU7_I2C_DDC3CLK 5
330 #define SMU7_I2C_SDA 40
331 #define SMU7_I2C_SCL 41
332 #define SMU7_I2C_DDC4DATA 65
333 #define SMU7_I2C_DDC4CLK 66
334 #define SMU7_I2C_DDC5DATA 0x48
335 #define SMU7_I2C_DDC5CLK 0x49
336 #define SMU7_I2C_DDC6DATA 0x4a
337 #define SMU7_I2C_DDC6CLK 0x4b
338 #define SMU7_I2C_DDCVGADATA 0x4c
339 #define SMU7_I2C_DDCVGACLK 0x4d
341 #define SMU7_UNUSED_GPIO_PIN 0x7F
342 uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr);
343 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
344 uint32_t clock_insr);