drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "pp_debug.h"
  24 #include <linux/delay.h>
  25 #include <linux/fb.h>
  26 #include <linux/module.h>
  27 #include <linux/slab.h>
  28 #include <asm/div64.h>
  29 #include <drm/amdgpu_drm.h>
  30 #include "pp_acpi.h"
  31 #include "ppatomctrl.h"
  32 #include "atombios.h"
  33 #include "pptable_v1_0.h"
  34 #include "pppcielanes.h"
  35 #include "amd_pcie_helpers.h"
  36 #include "hardwaremanager.h"
  37 #include "process_pptables_v1_0.h"
  38 #include "cgs_common.h"
  39
  40 #include "smu7_common.h"
  41
  42 #include "hwmgr.h"
  43 #include "smu7_hwmgr.h"
  44 #include "smu7_smumgr.h"
  45 #include "smu_ucode_xfer_vi.h"
  46 #include "smu7_powertune.h"
  47 #include "smu7_dyn_defaults.h"
  48 #include "smu7_thermal.h"
  49 #include "smu7_clockpowergating.h"
  50 #include "processpptables.h"
  51
  52 #define MC_CG_ARB_FREQ_F0           0x0a
  53 #define MC_CG_ARB_FREQ_F1           0x0b
  54 #define MC_CG_ARB_FREQ_F2           0x0c
  55 #define MC_CG_ARB_FREQ_F3           0x0d
  56
  57 #define MC_CG_SEQ_DRAMCONF_S0       0x05
  58 #define MC_CG_SEQ_DRAMCONF_S1       0x06
  59 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
  60 #define MC_CG_SEQ_YCLK_RESUME       0x0a
  61
  62 #define SMC_CG_IND_START            0xc0030000
  63 #define SMC_CG_IND_END              0xc0040000
  64
  65 #define VOLTAGE_SCALE               4
  66 #define VOLTAGE_VID_OFFSET_SCALE1   625
  67 #define VOLTAGE_VID_OFFSET_SCALE2   100
  68
  69 #define MEM_FREQ_LOW_LATENCY        25000
  70 #define MEM_FREQ_HIGH_LATENCY       80000
  71
  72 #define MEM_LATENCY_HIGH            45
  73 #define MEM_LATENCY_LOW             35
  74 #define MEM_LATENCY_ERR             0xFFFF
  75
  76 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  77 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  78 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  79
  80 #define PCIE_BUS_CLK                10000
  81 #define TCLK                        (PCIE_BUS_CLK / 10)
  82
  83
  84 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
  85 enum DPM_EVENT_SRC {
  86         DPM_EVENT_SRC_ANALOG = 0,
  87         DPM_EVENT_SRC_EXTERNAL = 1,
  88         DPM_EVENT_SRC_DIGITAL = 2,
  89         DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
  90         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
  91 };
  92
  93 static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable);
  94 static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
  95 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
  96                 enum pp_clock_type type, uint32_t mask);
  97
  98 static struct smu7_power_state *cast_phw_smu7_power_state(
  99                                   struct pp_hw_power_state *hw_ps)
 100 {
 101         PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
 102                                 "Invalid Powerstate Type!",
 103                                  return NULL);
 104
 105         return (struct smu7_power_state *)hw_ps;
 106 }
 107
 108 static const struct smu7_power_state *cast_const_phw_smu7_power_state(
 109                                  const struct pp_hw_power_state *hw_ps)
 110 {
 111         PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
 112                                 "Invalid Powerstate Type!",
 113                                  return NULL);
 114
 115         return (const struct smu7_power_state *)hw_ps;
 116 }
 117
 118 /**
 119  * Find the MC microcode version and store it in the HwMgr struct
 120  *
 121  * @param    hwmgr  the address of the powerplay hardware manager.
 122  * @return   always 0
 123  */
 124 static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr)
 125 {
 126         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 127
 128         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
 129
 130         return 0;
 131 }
 132
 133 static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 134 {
 135         uint32_t speedCntl = 0;
 136
 137         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 138         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
 139                         ixPCIE_LC_SPEED_CNTL);
 140         return((uint16_t)PHM_GET_FIELD(speedCntl,
 141                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 142 }
 143
 144 static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 145 {
 146         uint32_t link_width;
 147
 148         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 149         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 150                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
 151
 152         PP_ASSERT_WITH_CODE((7 >= link_width),
 153                         "Invalid PCIe lane width!", return 0);
 154
 155         return decode_pcie_lane_width(link_width);
 156 }
 157
 158 /**
 159 * Enable voltage control
 160 *
 161 * @param    pHwMgr  the address of the powerplay hardware manager.
 162 * @return   always PP_Result_OK
 163 */
 164 static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
 165 {
 166         if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
 167                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable);
 168
 169         return 0;
 170 }
 171
 172 /**
 173 * Checks if we want to support voltage control
 174 *
 175 * @param    hwmgr  the address of the powerplay hardware manager.
 176 */
 177 static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr)
 178 {
 179         const struct smu7_hwmgr *data =
 180                         (const struct smu7_hwmgr *)(hwmgr->backend);
 181
 182         return (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control);
 183 }
 184
 185 /**
 186 * Enable voltage control
 187 *
 188 * @param    hwmgr  the address of the powerplay hardware manager.
 189 * @return   always 0
 190 */
 191 static int smu7_enable_voltage_control(struct pp_hwmgr *hwmgr)
 192 {
 193         /* enable voltage control */
 194         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 195                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 196
 197         return 0;
 198 }
 199
 200 static int phm_get_svi2_voltage_table_v0(pp_atomctrl_voltage_table *voltage_table,
 201                 struct phm_clock_voltage_dependency_table *voltage_dependency_table
 202                 )
 203 {
 204         uint32_t i;
 205
 206         PP_ASSERT_WITH_CODE((NULL != voltage_table),
 207                         "Voltage Dependency Table empty.", return -EINVAL;);
 208
 209         voltage_table->mask_low = 0;
 210         voltage_table->phase_delay = 0;
 211         voltage_table->count = voltage_dependency_table->count;
 212
 213         for (i = 0; i < voltage_dependency_table->count; i++) {
 214                 voltage_table->entries[i].value =
 215                         voltage_dependency_table->entries[i].v;
 216                 voltage_table->entries[i].smio_low = 0;
 217         }
 218
 219         return 0;
 220 }
 221
 222
 223 /**
 224 * Create Voltage Tables.
 225 *
 226 * @param    hwmgr  the address of the powerplay hardware manager.
 227 * @return   always 0
 228 */
 229 static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr)
 230 {
 231         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 232         struct phm_ppt_v1_information *table_info =
 233                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 234         int result = 0;
 235         uint32_t tmp;
 236
 237         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 238                 result = atomctrl_get_voltage_table_v3(hwmgr,
 239                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
 240                                 &(data->mvdd_voltage_table));
 241                 PP_ASSERT_WITH_CODE((0 == result),
 242                                 "Failed to retrieve MVDD table.",
 243                                 return result);
 244         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
 245                 if (hwmgr->pp_table_version == PP_TABLE_V1)
 246                         result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
 247                                         table_info->vdd_dep_on_mclk);
 248                 else if (hwmgr->pp_table_version == PP_TABLE_V0)
 249                         result = phm_get_svi2_voltage_table_v0(&(data->mvdd_voltage_table),
 250                                         hwmgr->dyn_state.mvdd_dependency_on_mclk);
 251
 252                 PP_ASSERT_WITH_CODE((0 == result),
 253                                 "Failed to retrieve SVI2 MVDD table from dependancy table.",
 254                                 return result;);
 255         }
 256
 257         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 258                 result = atomctrl_get_voltage_table_v3(hwmgr,
 259                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
 260                                 &(data->vddci_voltage_table));
 261                 PP_ASSERT_WITH_CODE((0 == result),
 262                                 "Failed to retrieve VDDCI table.",
 263                                 return result);
 264         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
 265                 if (hwmgr->pp_table_version == PP_TABLE_V1)
 266                         result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
 267                                         table_info->vdd_dep_on_mclk);
 268                 else if (hwmgr->pp_table_version == PP_TABLE_V0)
 269                         result = phm_get_svi2_voltage_table_v0(&(data->vddci_voltage_table),
 270                                         hwmgr->dyn_state.vddci_dependency_on_mclk);
 271                 PP_ASSERT_WITH_CODE((0 == result),
 272                                 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
 273                                 return result);
 274         }
 275
 276         if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
 277                 /* VDDGFX has only SVI2 voltage control */
 278                 result = phm_get_svi2_vdd_voltage_table(&(data->vddgfx_voltage_table),
 279                                         table_info->vddgfx_lookup_table);
 280                 PP_ASSERT_WITH_CODE((0 == result),
 281                         "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
 282         }
 283
 284
 285         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
 286                 result = atomctrl_get_voltage_table_v3(hwmgr,
 287                                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT,
 288                                         &data->vddc_voltage_table);
 289                 PP_ASSERT_WITH_CODE((0 == result),
 290                         "Failed to retrieve VDDC table.", return result;);
 291         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
 292
 293                 if (hwmgr->pp_table_version == PP_TABLE_V0)
 294                         result = phm_get_svi2_voltage_table_v0(&data->vddc_voltage_table,
 295                                         hwmgr->dyn_state.vddc_dependency_on_mclk);
 296                 else if (hwmgr->pp_table_version == PP_TABLE_V1)
 297                         result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
 298                                 table_info->vddc_lookup_table);
 299
 300                 PP_ASSERT_WITH_CODE((0 == result),
 301                         "Failed to retrieve SVI2 VDDC table from dependancy table.", return result;);
 302         }
 303
 304         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC);
 305         PP_ASSERT_WITH_CODE(
 306                         (data->vddc_voltage_table.count <= tmp),
 307                 "Too many voltage values for VDDC. Trimming to fit state table.",
 308                         phm_trim_voltage_table_to_fit_state_table(tmp,
 309                                                 &(data->vddc_voltage_table)));
 310
 311         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
 312         PP_ASSERT_WITH_CODE(
 313                         (data->vddgfx_voltage_table.count <= tmp),
 314                 "Too many voltage values for VDDC. Trimming to fit state table.",
 315                         phm_trim_voltage_table_to_fit_state_table(tmp,
 316                                                 &(data->vddgfx_voltage_table)));
 317
 318         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI);
 319         PP_ASSERT_WITH_CODE(
 320                         (data->vddci_voltage_table.count <= tmp),
 321                 "Too many voltage values for VDDCI. Trimming to fit state table.",
 322                         phm_trim_voltage_table_to_fit_state_table(tmp,
 323                                         &(data->vddci_voltage_table)));
 324
 325         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD);
 326         PP_ASSERT_WITH_CODE(
 327                         (data->mvdd_voltage_table.count <= tmp),
 328                 "Too many voltage values for MVDD. Trimming to fit state table.",
 329                         phm_trim_voltage_table_to_fit_state_table(tmp,
 330                                                 &(data->mvdd_voltage_table)));
 331
 332         return 0;
 333 }
 334
 335 /**
 336 * Programs static screed detection parameters
 337 *
 338 * @param    hwmgr  the address of the powerplay hardware manager.
 339 * @return   always 0
 340 */
 341 static int smu7_program_static_screen_threshold_parameters(
 342                                                         struct pp_hwmgr *hwmgr)
 343 {
 344         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 345
 346         /* Set static screen threshold unit */
 347         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 348                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
 349                         data->static_screen_threshold_unit);
 350         /* Set static screen threshold */
 351         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 352                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
 353                         data->static_screen_threshold);
 354
 355         return 0;
 356 }
 357
 358 /**
 359 * Setup display gap for glitch free memory clock switching.
 360 *
 361 * @param    hwmgr  the address of the powerplay hardware manager.
 362 * @return   always  0
 363 */
 364 static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr)
 365 {
 366         uint32_t display_gap =
 367                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 368                                         ixCG_DISPLAY_GAP_CNTL);
 369
 370         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 371                         DISP_GAP, DISPLAY_GAP_IGNORE);
 372
 373         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 374                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
 375
 376         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 377                         ixCG_DISPLAY_GAP_CNTL, display_gap);
 378
 379         return 0;
 380 }
 381
 382 /**
 383 * Programs activity state transition voting clients
 384 *
 385 * @param    hwmgr  the address of the powerplay hardware manager.
 386 * @return   always  0
 387 */
 388 static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr)
 389 {
 390         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 391         int i;
 392
 393         /* Clear reset for voting clients before enabling DPM */
 394         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 395                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
 396         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 397                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
 398
 399         for (i = 0; i < 8; i++)
 400                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 401                                         ixCG_FREQ_TRAN_VOTING_0 + i * 4,
 402                                         data->voting_rights_clients[i]);
 403         return 0;
 404 }
 405
 406 static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr)
 407 {
 408         int i;
 409
 410         /* Reset voting clients before disabling DPM */
 411         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 412                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
 413         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 414                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
 415
 416         for (i = 0; i < 8; i++)
 417                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 418                                 ixCG_FREQ_TRAN_VOTING_0 + i * 4, 0);
 419
 420         return 0;
 421 }
 422
 423 /* Copy one arb setting to another and then switch the active set.
 424  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
 425  */
 426 static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
 427                 uint32_t arb_src, uint32_t arb_dest)
 428 {
 429         uint32_t mc_arb_dram_timing;
 430         uint32_t mc_arb_dram_timing2;
 431         uint32_t burst_time;
 432         uint32_t mc_cg_config;
 433
 434         switch (arb_src) {
 435         case MC_CG_ARB_FREQ_F0:
 436                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
 437                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
 438                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
 439                 break;
 440         case MC_CG_ARB_FREQ_F1:
 441                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
 442                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
 443                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
 444                 break;
 445         default:
 446                 return -EINVAL;
 447         }
 448
 449         switch (arb_dest) {
 450         case MC_CG_ARB_FREQ_F0:
 451                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 452                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 453                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
 454                 break;
 455         case MC_CG_ARB_FREQ_F1:
 456                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 457                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 458                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
 459                 break;
 460         default:
 461                 return -EINVAL;
 462         }
 463
 464         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
 465         mc_cg_config |= 0x0000000F;
 466         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
 467         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
 468
 469         return 0;
 470 }
 471
 472 static int smu7_reset_to_default(struct pp_hwmgr *hwmgr)
 473 {
 474         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults);
 475 }
 476
 477 /**
 478 * Initial switch from ARB F0->F1
 479 *
 480 * @param    hwmgr  the address of the powerplay hardware manager.
 481 * @return   always 0
 482 * This function is to be called from the SetPowerState table.
 483 */
 484 static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
 485 {
 486         return smu7_copy_and_switch_arb_sets(hwmgr,
 487                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
 488 }
 489
 490 static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
 491 {
 492         uint32_t tmp;
 493
 494         tmp = (cgs_read_ind_register(hwmgr->device,
 495                         CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
 496                         0x0000ff00) >> 8;
 497
 498         if (tmp == MC_CG_ARB_FREQ_F0)
 499                 return 0;
 500
 501         return smu7_copy_and_switch_arb_sets(hwmgr,
 502                         tmp, MC_CG_ARB_FREQ_F0);
 503 }
 504
 505 static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
 506 {
 507         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 508
 509         struct phm_ppt_v1_information *table_info =
 510                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 511         struct phm_ppt_v1_pcie_table *pcie_table = NULL;
 512
 513         uint32_t i, max_entry;
 514         uint32_t tmp;
 515
 516         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
 517                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
 518                         return -EINVAL);
 519
 520         if (table_info != NULL)
 521                 pcie_table = table_info->pcie_table;
 522
 523         if (data->use_pcie_performance_levels &&
 524                         !data->use_pcie_power_saving_levels) {
 525                 data->pcie_gen_power_saving = data->pcie_gen_performance;
 526                 data->pcie_lane_power_saving = data->pcie_lane_performance;
 527         } else if (!data->use_pcie_performance_levels &&
 528                         data->use_pcie_power_saving_levels) {
 529                 data->pcie_gen_performance = data->pcie_gen_power_saving;
 530                 data->pcie_lane_performance = data->pcie_lane_power_saving;
 531         }
 532         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK);
 533         phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
 534                                         tmp,
 535                                         MAX_REGULAR_DPM_NUMBER);
 536
 537         if (pcie_table != NULL) {
 538                 /* max_entry is used to make sure we reserve one PCIE level
 539                  * for boot level (fix for A+A PSPP issue).
 540                  * If PCIE table from PPTable have ULV entry + 8 entries,
 541                  * then ignore the last entry.*/
 542                 max_entry = (tmp < pcie_table->count) ? tmp : pcie_table->count;
 543                 for (i = 1; i < max_entry; i++) {
 544                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
 545                                         get_pcie_gen_support(data->pcie_gen_cap,
 546                                                         pcie_table->entries[i].gen_speed),
 547                                         get_pcie_lane_support(data->pcie_lane_cap,
 548                                                         pcie_table->entries[i].lane_width));
 549                 }
 550                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
 551                 smum_update_smc_table(hwmgr, SMU_BIF_TABLE);
 552         } else {
 553                 /* Hardcode Pcie Table */
 554                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
 555                                 get_pcie_gen_support(data->pcie_gen_cap,
 556                                                 PP_Min_PCIEGen),
 557                                 get_pcie_lane_support(data->pcie_lane_cap,
 558                                                 PP_Max_PCIELane));
 559                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
 560                                 get_pcie_gen_support(data->pcie_gen_cap,
 561                                                 PP_Min_PCIEGen),
 562                                 get_pcie_lane_support(data->pcie_lane_cap,
 563                                                 PP_Max_PCIELane));
 564                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
 565                                 get_pcie_gen_support(data->pcie_gen_cap,
 566                                                 PP_Max_PCIEGen),
 567                                 get_pcie_lane_support(data->pcie_lane_cap,
 568                                                 PP_Max_PCIELane));
 569                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
 570                                 get_pcie_gen_support(data->pcie_gen_cap,
 571                                                 PP_Max_PCIEGen),
 572                                 get_pcie_lane_support(data->pcie_lane_cap,
 573                                                 PP_Max_PCIELane));
 574                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
 575                                 get_pcie_gen_support(data->pcie_gen_cap,
 576                                                 PP_Max_PCIEGen),
 577                                 get_pcie_lane_support(data->pcie_lane_cap,
 578                                                 PP_Max_PCIELane));
 579                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
 580                                 get_pcie_gen_support(data->pcie_gen_cap,
 581                                                 PP_Max_PCIEGen),
 582                                 get_pcie_lane_support(data->pcie_lane_cap,
 583                                                 PP_Max_PCIELane));
 584
 585                 data->dpm_table.pcie_speed_table.count = 6;
 586         }
 587         /* Populate last level for boot PCIE level, but do not increment count. */
 588         if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
 589                 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++)
 590                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i,
 591                                 get_pcie_gen_support(data->pcie_gen_cap,
 592                                                 PP_Max_PCIEGen),
 593                                 data->vbios_boot_state.pcie_lane_bootup_value);
 594         } else {
 595                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
 596                         data->dpm_table.pcie_speed_table.count,
 597                         get_pcie_gen_support(data->pcie_gen_cap,
 598                                         PP_Min_PCIEGen),
 599                         get_pcie_lane_support(data->pcie_lane_cap,
 600                                         PP_Max_PCIELane));
 601         }
 602         return 0;
 603 }
 604
 605 static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr)
 606 {
 607         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 608
 609         memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
 610
 611         phm_reset_single_dpm_table(
 612                         &data->dpm_table.sclk_table,
 613                                 smum_get_mac_definition(hwmgr,
 614                                         SMU_MAX_LEVELS_GRAPHICS),
 615                                         MAX_REGULAR_DPM_NUMBER);
 616         phm_reset_single_dpm_table(
 617                         &data->dpm_table.mclk_table,
 618                         smum_get_mac_definition(hwmgr,
 619                                 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER);
 620
 621         phm_reset_single_dpm_table(
 622                         &data->dpm_table.vddc_table,
 623                                 smum_get_mac_definition(hwmgr,
 624                                         SMU_MAX_LEVELS_VDDC),
 625                                         MAX_REGULAR_DPM_NUMBER);
 626         phm_reset_single_dpm_table(
 627                         &data->dpm_table.vddci_table,
 628                         smum_get_mac_definition(hwmgr,
 629                                 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER);
 630
 631         phm_reset_single_dpm_table(
 632                         &data->dpm_table.mvdd_table,
 633                                 smum_get_mac_definition(hwmgr,
 634                                         SMU_MAX_LEVELS_MVDD),
 635                                         MAX_REGULAR_DPM_NUMBER);
 636         return 0;
 637 }
 638 /*
 639  * This function is to initialize all DPM state tables
 640  * for SMU7 based on the dependency table.
 641  * Dynamic state patching function will then trim these
 642  * state tables to the allowed range based
 643  * on the power policy or external client requests,
 644  * such as UVD request, etc.
 645  */
 646
 647 static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr)
 648 {
 649         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 650         struct phm_clock_voltage_dependency_table *allowed_vdd_sclk_table =
 651                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 652         struct phm_clock_voltage_dependency_table *allowed_vdd_mclk_table =
 653                 hwmgr->dyn_state.vddc_dependency_on_mclk;
 654         struct phm_cac_leakage_table *std_voltage_table =
 655                 hwmgr->dyn_state.cac_leakage_table;
 656         uint32_t i;
 657
 658         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
 659                 "SCLK dependency table is missing. This table is mandatory", return -EINVAL);
 660         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
 661                 "SCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
 662
 663         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
 664                 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
 665         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
 666                 "VMCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
 667
 668
 669         /* Initialize Sclk DPM table based on allow Sclk values*/
 670         data->dpm_table.sclk_table.count = 0;
 671
 672         for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
 673                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
 674                                 allowed_vdd_sclk_table->entries[i].clk) {
 675                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 676                                 allowed_vdd_sclk_table->entries[i].clk;
 677                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0;
 678                         data->dpm_table.sclk_table.count++;
 679                 }
 680         }
 681
 682         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
 683                 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
 684         /* Initialize Mclk DPM table based on allow Mclk values */
 685         data->dpm_table.mclk_table.count = 0;
 686         for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
 687                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
 688                         allowed_vdd_mclk_table->entries[i].clk) {
 689                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 690                                 allowed_vdd_mclk_table->entries[i].clk;
 691                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0;
 692                         data->dpm_table.mclk_table.count++;
 693                 }
 694         }
 695
 696         /* Initialize Vddc DPM table based on allow Vddc values.  And populate corresponding std values. */
 697         for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
 698                 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
 699                 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage;
 700                 /* param1 is for corresponding std voltage */
 701                 data->dpm_table.vddc_table.dpm_levels[i].enabled = 1;
 702         }
 703
 704         data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
 705         allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
 706
 707         if (NULL != allowed_vdd_mclk_table) {
 708                 /* Initialize Vddci DPM table based on allow Mclk values */
 709                 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
 710                         data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
 711                         data->dpm_table.vddci_table.dpm_levels[i].enabled = 1;
 712                 }
 713                 data->dpm_table.vddci_table.count = allowed_vdd_mclk_table->count;
 714         }
 715
 716         allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk;
 717
 718         if (NULL != allowed_vdd_mclk_table) {
 719                 /*
 720                  * Initialize MVDD DPM table based on allow Mclk
 721                  * values
 722                  */
 723                 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
 724                         data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
 725                         data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1;
 726                 }
 727                 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
 728         }
 729
 730         return 0;
 731 }
 732
 733 static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
 734 {
 735         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 736         struct phm_ppt_v1_information *table_info =
 737                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 738         uint32_t i;
 739
 740         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
 741         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
 742
 743         if (table_info == NULL)
 744                 return -EINVAL;
 745
 746         dep_sclk_table = table_info->vdd_dep_on_sclk;
 747         dep_mclk_table = table_info->vdd_dep_on_mclk;
 748
 749         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
 750                         "SCLK dependency table is missing.",
 751                         return -EINVAL);
 752         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
 753                         "SCLK dependency table count is 0.",
 754                         return -EINVAL);
 755
 756         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
 757                         "MCLK dependency table is missing.",
 758                         return -EINVAL);
 759         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
 760                         "MCLK dependency table count is 0",
 761                         return -EINVAL);
 762
 763         /* Initialize Sclk DPM table based on allow Sclk values */
 764         data->dpm_table.sclk_table.count = 0;
 765         for (i = 0; i < dep_sclk_table->count; i++) {
 766                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
 767                                                 dep_sclk_table->entries[i].clk) {
 768
 769                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 770                                         dep_sclk_table->entries[i].clk;
 771
 772                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
 773                                         (i == 0) ? true : false;
 774                         data->dpm_table.sclk_table.count++;
 775                 }
 776         }
 777
 778         /* Initialize Mclk DPM table based on allow Mclk values */
 779         data->dpm_table.mclk_table.count = 0;
 780         for (i = 0; i < dep_mclk_table->count; i++) {
 781                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
 782                                 [data->dpm_table.mclk_table.count - 1].value !=
 783                                                 dep_mclk_table->entries[i].clk) {
 784                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 785                                                         dep_mclk_table->entries[i].clk;
 786                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
 787                                                         (i == 0) ? true : false;
 788                         data->dpm_table.mclk_table.count++;
 789                 }
 790         }
 791
 792         return 0;
 793 }
 794
 795 static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 796 {
 797         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 798
 799         smu7_reset_dpm_tables(hwmgr);
 800
 801         if (hwmgr->pp_table_version == PP_TABLE_V1)
 802                 smu7_setup_dpm_tables_v1(hwmgr);
 803         else if (hwmgr->pp_table_version == PP_TABLE_V0)
 804                 smu7_setup_dpm_tables_v0(hwmgr);
 805
 806         smu7_setup_default_pcie_table(hwmgr);
 807
 808         /* save a copy of the default DPM table */
 809         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 810                         sizeof(struct smu7_dpm_table));
 811         return 0;
 812 }
 813
 814 uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr)
 815 {
 816         uint32_t reference_clock, tmp;
 817         struct cgs_display_info info = {0};
 818         struct cgs_mode_info mode_info = {0};
 819
 820         info.mode_info = &mode_info;
 821
 822         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
 823
 824         if (tmp)
 825                 return TCLK;
 826
 827         cgs_get_active_displays_info(hwmgr->device, &info);
 828         reference_clock = mode_info.ref_clock;
 829
 830         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
 831
 832         if (0 != tmp)
 833                 return reference_clock / 4;
 834
 835         return reference_clock;
 836 }
 837
 838 static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
 839 {
 840
 841         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 842                         PHM_PlatformCaps_RegulatorHot))
 843                 return smum_send_msg_to_smc(hwmgr,
 844                                 PPSMC_MSG_EnableVRHotGPIOInterrupt);
 845
 846         return 0;
 847 }
 848
 849 static int smu7_enable_sclk_control(struct pp_hwmgr *hwmgr)
 850 {
 851         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
 852                         SCLK_PWRMGT_OFF, 0);
 853         return 0;
 854 }
 855
 856 static int smu7_enable_ulv(struct pp_hwmgr *hwmgr)
 857 {
 858         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 859
 860         if (data->ulv_supported)
 861                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV);
 862
 863         return 0;
 864 }
 865
 866 static int smu7_disable_ulv(struct pp_hwmgr *hwmgr)
 867 {
 868         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 869
 870         if (data->ulv_supported)
 871                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV);
 872
 873         return 0;
 874 }
 875
 876 static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
 877 {
 878         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 879                         PHM_PlatformCaps_SclkDeepSleep)) {
 880                 if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON))
 881                         PP_ASSERT_WITH_CODE(false,
 882                                         "Attempt to enable Master Deep Sleep switch failed!",
 883                                         return -EINVAL);
 884         } else {
 885                 if (smum_send_msg_to_smc(hwmgr,
 886                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
 887                         PP_ASSERT_WITH_CODE(false,
 888                                         "Attempt to disable Master Deep Sleep switch failed!",
 889                                         return -EINVAL);
 890                 }
 891         }
 892
 893         return 0;
 894 }
 895
 896 static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
 897 {
 898         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 899                         PHM_PlatformCaps_SclkDeepSleep)) {
 900                 if (smum_send_msg_to_smc(hwmgr,
 901                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
 902                         PP_ASSERT_WITH_CODE(false,
 903                                         "Attempt to disable Master Deep Sleep switch failed!",
 904                                         return -EINVAL);
 905                 }
 906         }
 907
 908         return 0;
 909 }
 910
 911 static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr)
 912 {
 913         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 914         uint32_t soft_register_value = 0;
 915         uint32_t handshake_disables_offset = data->soft_regs_start
 916                                 + smum_get_offsetof(hwmgr,
 917                                         SMU_SoftRegisters, HandshakeDisables);
 918
 919         soft_register_value = cgs_read_ind_register(hwmgr->device,
 920                                 CGS_IND_REG__SMC, handshake_disables_offset);
 921         soft_register_value |= smum_get_mac_definition(hwmgr,
 922                                         SMU_UVD_MCLK_HANDSHAKE_DISABLE);
 923         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 924                         handshake_disables_offset, soft_register_value);
 925         return 0;
 926 }
 927
 928 static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
 929 {
 930         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 931
 932         /* enable SCLK dpm */
 933         if (!data->sclk_dpm_key_disabled)
 934                 PP_ASSERT_WITH_CODE(
 935                 (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable)),
 936                 "Failed to enable SCLK DPM during DPM Start Function!",
 937                 return -EINVAL);
 938
 939         /* enable MCLK dpm */
 940         if (0 == data->mclk_dpm_key_disabled) {
 941                 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK))
 942                         smu7_disable_handshake_uvd(hwmgr);
 943                 PP_ASSERT_WITH_CODE(
 944                                 (0 == smum_send_msg_to_smc(hwmgr,
 945                                                 PPSMC_MSG_MCLKDPM_Enable)),
 946                                 "Failed to enable MCLK DPM during DPM Start Function!",
 947                                 return -EINVAL);
 948
 949                 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
 950
 951
 952                 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
 953                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5);
 954                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5);
 955                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005);
 956                         udelay(10);
 957                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005);
 958                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005);
 959                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005);
 960                 } else {
 961                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
 962                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
 963                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
 964                         udelay(10);
 965                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
 966                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
 967                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
 968                 }
 969         }
 970
 971         return 0;
 972 }
 973
 974 static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
 975 {
 976         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 977
 978         /*enable general power management */
 979
 980         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
 981                         GLOBAL_PWRMGT_EN, 1);
 982
 983         /* enable sclk deep sleep */
 984
 985         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
 986                         DYNAMIC_PM_EN, 1);
 987
 988         /* prepare for PCIE DPM */
 989
 990         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 991                         data->soft_regs_start +
 992                         smum_get_offsetof(hwmgr, SMU_SoftRegisters,
 993                                                 VoltageChangeTimeout), 0x1000);
 994         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 995                         SWRST_COMMAND_1, RESETLC, 0x0);
 996
 997         if (hwmgr->chip_family == AMDGPU_FAMILY_CI)
 998                 cgs_write_register(hwmgr->device, 0x1488,
 999                         (cgs_read_register(hwmgr->device, 0x1488) & ~0x1));
1000
1001         if (smu7_enable_sclk_mclk_dpm(hwmgr)) {
1002                 pr_err("Failed to enable Sclk DPM and Mclk DPM!");
1003                 return -EINVAL;
1004         }
1005
1006         /* enable PCIE dpm */
1007         if (0 == data->pcie_dpm_key_disabled) {
1008                 PP_ASSERT_WITH_CODE(
1009                                 (0 == smum_send_msg_to_smc(hwmgr,
1010                                                 PPSMC_MSG_PCIeDPM_Enable)),
1011                                 "Failed to enable pcie DPM during DPM Start Function!",
1012                                 return -EINVAL);
1013         }
1014
1015         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1016                                 PHM_PlatformCaps_Falcon_QuickTransition)) {
1017                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr,
1018                                 PPSMC_MSG_EnableACDCGPIOInterrupt)),
1019                                 "Failed to enable AC DC GPIO Interrupt!",
1020                                 );
1021         }
1022
1023         return 0;
1024 }
1025
1026 static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1027 {
1028         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1029
1030         /* disable SCLK dpm */
1031         if (!data->sclk_dpm_key_disabled) {
1032                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1033                                 "Trying to disable SCLK DPM when DPM is disabled",
1034                                 return 0);
1035                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable);
1036         }
1037
1038         /* disable MCLK dpm */
1039         if (!data->mclk_dpm_key_disabled) {
1040                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1041                                 "Trying to disable MCLK DPM when DPM is disabled",
1042                                 return 0);
1043                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable);
1044         }
1045
1046         return 0;
1047 }
1048
1049 static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
1050 {
1051         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1052
1053         /* disable general power management */
1054         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1055                         GLOBAL_PWRMGT_EN, 0);
1056         /* disable sclk deep sleep */
1057         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1058                         DYNAMIC_PM_EN, 0);
1059
1060         /* disable PCIE dpm */
1061         if (!data->pcie_dpm_key_disabled) {
1062                 PP_ASSERT_WITH_CODE(
1063                                 (smum_send_msg_to_smc(hwmgr,
1064                                                 PPSMC_MSG_PCIeDPM_Disable) == 0),
1065                                 "Failed to disable pcie DPM during DPM Stop Function!",
1066                                 return -EINVAL);
1067         }
1068
1069         smu7_disable_sclk_mclk_dpm(hwmgr);
1070
1071         PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1072                         "Trying to disable voltage DPM when DPM is disabled",
1073                         return 0);
1074
1075         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable);
1076
1077         return 0;
1078 }
1079
1080 static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
1081 {
1082         bool protection;
1083         enum DPM_EVENT_SRC src;
1084
1085         switch (sources) {
1086         default:
1087                 pr_err("Unknown throttling event sources.");
1088                 /* fall through */
1089         case 0:
1090                 protection = false;
1091                 /* src is unused */
1092                 break;
1093         case (1 << PHM_AutoThrottleSource_Thermal):
1094                 protection = true;
1095                 src = DPM_EVENT_SRC_DIGITAL;
1096                 break;
1097         case (1 << PHM_AutoThrottleSource_External):
1098                 protection = true;
1099                 src = DPM_EVENT_SRC_EXTERNAL;
1100                 break;
1101         case (1 << PHM_AutoThrottleSource_External) |
1102                         (1 << PHM_AutoThrottleSource_Thermal):
1103                 protection = true;
1104                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
1105                 break;
1106         }
1107         /* Order matters - don't enable thermal protection for the wrong source. */
1108         if (protection) {
1109                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
1110                                 DPM_EVENT_SRC, src);
1111                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1112                                 THERMAL_PROTECTION_DIS,
1113                                 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1114                                                 PHM_PlatformCaps_ThermalController));
1115         } else
1116                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1117                                 THERMAL_PROTECTION_DIS, 1);
1118 }
1119
1120 static int smu7_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1121                 PHM_AutoThrottleSource source)
1122 {
1123         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1124
1125         if (!(data->active_auto_throttle_sources & (1 << source))) {
1126                 data->active_auto_throttle_sources |= 1 << source;
1127                 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1128         }
1129         return 0;
1130 }
1131
1132 static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1133 {
1134         return smu7_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1135 }
1136
1137 static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1138                 PHM_AutoThrottleSource source)
1139 {
1140         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1141
1142         if (data->active_auto_throttle_sources & (1 << source)) {
1143                 data->active_auto_throttle_sources &= ~(1 << source);
1144                 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1145         }
1146         return 0;
1147 }
1148
1149 static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1150 {
1151         return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1152 }
1153
1154 static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
1155 {
1156         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1157         data->pcie_performance_request = true;
1158
1159         return 0;
1160 }
1161
1162 static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1163 {
1164         int tmp_result = 0;
1165         int result = 0;
1166
1167         tmp_result = (!smum_is_dpm_running(hwmgr)) ? 0 : -1;
1168         PP_ASSERT_WITH_CODE(tmp_result == 0,
1169                         "DPM is already running",
1170                         );
1171
1172         if (smu7_voltage_control(hwmgr)) {
1173                 tmp_result = smu7_enable_voltage_control(hwmgr);
1174                 PP_ASSERT_WITH_CODE(tmp_result == 0,
1175                                 "Failed to enable voltage control!",
1176                                 result = tmp_result);
1177
1178                 tmp_result = smu7_construct_voltage_tables(hwmgr);
1179                 PP_ASSERT_WITH_CODE((0 == tmp_result),
1180                                 "Failed to contruct voltage tables!",
1181                                 result = tmp_result);
1182         }
1183         smum_initialize_mc_reg_table(hwmgr);
1184
1185         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1186                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
1187                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1188                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
1189
1190         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1191                         PHM_PlatformCaps_ThermalController))
1192                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1193                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
1194
1195         tmp_result = smu7_program_static_screen_threshold_parameters(hwmgr);
1196         PP_ASSERT_WITH_CODE((0 == tmp_result),
1197                         "Failed to program static screen threshold parameters!",
1198                         result = tmp_result);
1199
1200         tmp_result = smu7_enable_display_gap(hwmgr);
1201         PP_ASSERT_WITH_CODE((0 == tmp_result),
1202                         "Failed to enable display gap!", result = tmp_result);
1203
1204         tmp_result = smu7_program_voting_clients(hwmgr);
1205         PP_ASSERT_WITH_CODE((0 == tmp_result),
1206                         "Failed to program voting clients!", result = tmp_result);
1207
1208         tmp_result = smum_process_firmware_header(hwmgr);
1209         PP_ASSERT_WITH_CODE((0 == tmp_result),
1210                         "Failed to process firmware header!", result = tmp_result);
1211
1212         tmp_result = smu7_initial_switch_from_arbf0_to_f1(hwmgr);
1213         PP_ASSERT_WITH_CODE((0 == tmp_result),
1214                         "Failed to initialize switch from ArbF0 to F1!",
1215                         result = tmp_result);
1216
1217         result = smu7_setup_default_dpm_tables(hwmgr);
1218         PP_ASSERT_WITH_CODE(0 == result,
1219                         "Failed to setup default DPM tables!", return result);
1220
1221         tmp_result = smum_init_smc_table(hwmgr);
1222         PP_ASSERT_WITH_CODE((0 == tmp_result),
1223                         "Failed to initialize SMC table!", result = tmp_result);
1224
1225         tmp_result = smu7_enable_vrhot_gpio_interrupt(hwmgr);
1226         PP_ASSERT_WITH_CODE((0 == tmp_result),
1227                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
1228
1229         smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay);
1230
1231         tmp_result = smu7_enable_sclk_control(hwmgr);
1232         PP_ASSERT_WITH_CODE((0 == tmp_result),
1233                         "Failed to enable SCLK control!", result = tmp_result);
1234
1235         tmp_result = smu7_enable_smc_voltage_controller(hwmgr);
1236         PP_ASSERT_WITH_CODE((0 == tmp_result),
1237                         "Failed to enable voltage control!", result = tmp_result);
1238
1239         tmp_result = smu7_enable_ulv(hwmgr);
1240         PP_ASSERT_WITH_CODE((0 == tmp_result),
1241                         "Failed to enable ULV!", result = tmp_result);
1242
1243         tmp_result = smu7_enable_deep_sleep_master_switch(hwmgr);
1244         PP_ASSERT_WITH_CODE((0 == tmp_result),
1245                         "Failed to enable deep sleep master switch!", result = tmp_result);
1246
1247         tmp_result = smu7_enable_didt_config(hwmgr);
1248         PP_ASSERT_WITH_CODE((tmp_result == 0),
1249                         "Failed to enable deep sleep master switch!", result = tmp_result);
1250
1251         tmp_result = smu7_start_dpm(hwmgr);
1252         PP_ASSERT_WITH_CODE((0 == tmp_result),
1253                         "Failed to start DPM!", result = tmp_result);
1254
1255         tmp_result = smu7_enable_smc_cac(hwmgr);
1256         PP_ASSERT_WITH_CODE((0 == tmp_result),
1257                         "Failed to enable SMC CAC!", result = tmp_result);
1258
1259         tmp_result = smu7_enable_power_containment(hwmgr);
1260         PP_ASSERT_WITH_CODE((0 == tmp_result),
1261                         "Failed to enable power containment!", result = tmp_result);
1262
1263         tmp_result = smu7_power_control_set_level(hwmgr);
1264         PP_ASSERT_WITH_CODE((0 == tmp_result),
1265                         "Failed to power control set level!", result = tmp_result);
1266
1267         tmp_result = smu7_enable_thermal_auto_throttle(hwmgr);
1268         PP_ASSERT_WITH_CODE((0 == tmp_result),
1269                         "Failed to enable thermal auto throttle!", result = tmp_result);
1270
1271         tmp_result = smu7_pcie_performance_request(hwmgr);
1272         PP_ASSERT_WITH_CODE((0 == tmp_result),
1273                         "pcie performance request failed!", result = tmp_result);
1274
1275         return 0;
1276 }
1277
1278 int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
1279 {
1280         int tmp_result, result = 0;
1281
1282         tmp_result = (smum_is_dpm_running(hwmgr)) ? 0 : -1;
1283         PP_ASSERT_WITH_CODE(tmp_result == 0,
1284                         "DPM is not running right now, no need to disable DPM!",
1285                         return 0);
1286
1287         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1288                         PHM_PlatformCaps_ThermalController))
1289                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1290                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
1291
1292         tmp_result = smu7_disable_power_containment(hwmgr);
1293         PP_ASSERT_WITH_CODE((tmp_result == 0),
1294                         "Failed to disable power containment!", result = tmp_result);
1295
1296         tmp_result = smu7_disable_smc_cac(hwmgr);
1297         PP_ASSERT_WITH_CODE((tmp_result == 0),
1298                         "Failed to disable SMC CAC!", result = tmp_result);
1299
1300         tmp_result = smu7_disable_didt_config(hwmgr);
1301         PP_ASSERT_WITH_CODE((tmp_result == 0),
1302                         "Failed to disable DIDT!", result = tmp_result);
1303
1304         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1305                         CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
1306         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1307                         GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
1308
1309         tmp_result = smu7_disable_thermal_auto_throttle(hwmgr);
1310         PP_ASSERT_WITH_CODE((tmp_result == 0),
1311                         "Failed to disable thermal auto throttle!", result = tmp_result);
1312
1313         tmp_result = smu7_avfs_control(hwmgr, false);
1314         PP_ASSERT_WITH_CODE((tmp_result == 0),
1315                         "Failed to disable AVFS!", result = tmp_result);
1316
1317         tmp_result = smu7_stop_dpm(hwmgr);
1318         PP_ASSERT_WITH_CODE((tmp_result == 0),
1319                         "Failed to stop DPM!", result = tmp_result);
1320
1321         tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr);
1322         PP_ASSERT_WITH_CODE((tmp_result == 0),
1323                         "Failed to disable deep sleep master switch!", result = tmp_result);
1324
1325         tmp_result = smu7_disable_ulv(hwmgr);
1326         PP_ASSERT_WITH_CODE((tmp_result == 0),
1327                         "Failed to disable ULV!", result = tmp_result);
1328
1329         tmp_result = smu7_clear_voting_clients(hwmgr);
1330         PP_ASSERT_WITH_CODE((tmp_result == 0),
1331                         "Failed to clear voting clients!", result = tmp_result);
1332
1333         tmp_result = smu7_reset_to_default(hwmgr);
1334         PP_ASSERT_WITH_CODE((tmp_result == 0),
1335                         "Failed to reset to default!", result = tmp_result);
1336
1337         tmp_result = smu7_force_switch_to_arbf0(hwmgr);
1338         PP_ASSERT_WITH_CODE((tmp_result == 0),
1339                         "Failed to force to switch arbf0!", result = tmp_result);
1340
1341         return result;
1342 }
1343
1344 int smu7_reset_asic_tasks(struct pp_hwmgr *hwmgr)
1345 {
1346
1347         return 0;
1348 }
1349
1350 static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
1351 {
1352         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1353         struct phm_ppt_v1_information *table_info =
1354                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1355         struct cgs_system_info sys_info = {0};
1356         int result;
1357
1358         data->dll_default_on = false;
1359         data->mclk_dpm0_activity_target = 0xa;
1360         data->mclk_activity_target = SMU7_MCLK_TARGETACTIVITY_DFLT;
1361         data->vddc_vddgfx_delta = 300;
1362         data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT;
1363         data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT;
1364         data->voting_rights_clients[0] = SMU7_VOTINGRIGHTSCLIENTS_DFLT0;
1365         data->voting_rights_clients[1]= SMU7_VOTINGRIGHTSCLIENTS_DFLT1;
1366         data->voting_rights_clients[2] = SMU7_VOTINGRIGHTSCLIENTS_DFLT2;
1367         data->voting_rights_clients[3]= SMU7_VOTINGRIGHTSCLIENTS_DFLT3;
1368         data->voting_rights_clients[4]= SMU7_VOTINGRIGHTSCLIENTS_DFLT4;
1369         data->voting_rights_clients[5]= SMU7_VOTINGRIGHTSCLIENTS_DFLT5;
1370         data->voting_rights_clients[6]= SMU7_VOTINGRIGHTSCLIENTS_DFLT6;
1371         data->voting_rights_clients[7]= SMU7_VOTINGRIGHTSCLIENTS_DFLT7;
1372
1373         data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
1374         data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
1375         data->pcie_dpm_key_disabled = hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
1376         /* need to set voltage control types before EVV patching */
1377         data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;
1378         data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;
1379         data->mvdd_control = SMU7_VOLTAGE_CONTROL_NONE;
1380         data->enable_tdc_limit_feature = true;
1381         data->enable_pkg_pwr_tracking_feature = true;
1382         data->force_pcie_gen = PP_PCIEGenInvalid;
1383         data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
1384
1385         if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) {
1386                 uint8_t tmp1, tmp2;
1387                 uint16_t tmp3 = 0;
1388                 atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2,
1389                                                 &tmp3);
1390                 tmp3 = (tmp3 >> 5) & 0x3;
1391                 data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3;
1392         } else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
1393                 data->vddc_phase_shed_control = 1;
1394         } else {
1395                 data->vddc_phase_shed_control = 0;
1396         }
1397
1398         if (hwmgr->chip_id  == CHIP_HAWAII) {
1399                 data->thermal_temp_setting.temperature_low = 94500;
1400                 data->thermal_temp_setting.temperature_high = 95000;
1401                 data->thermal_temp_setting.temperature_shutdown = 104000;
1402         } else {
1403                 data->thermal_temp_setting.temperature_low = 99500;
1404                 data->thermal_temp_setting.temperature_high = 100000;
1405                 data->thermal_temp_setting.temperature_shutdown = 104000;
1406         }
1407
1408         data->fast_watermark_threshold = 100;
1409         if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1410                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
1411                 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1412         else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1413                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
1414                 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1415
1416         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1417                         PHM_PlatformCaps_ControlVDDGFX)) {
1418                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1419                         VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
1420                         data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1421                 }
1422         }
1423
1424         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1425                         PHM_PlatformCaps_EnableMVDDControl)) {
1426                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1427                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
1428                         data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1429                 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1430                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
1431                         data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1432         }
1433
1434         if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control)
1435                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1436                         PHM_PlatformCaps_ControlVDDGFX);
1437
1438         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1439                         PHM_PlatformCaps_ControlVDDCI)) {
1440                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1441                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
1442                         data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1443                 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1444                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
1445                         data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1446         }
1447
1448         if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE)
1449                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1450                                 PHM_PlatformCaps_EnableMVDDControl);
1451
1452         if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE)
1453                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1454                                 PHM_PlatformCaps_ControlVDDCI);
1455
1456         if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK)
1457                 && (table_info->cac_dtp_table->usClockStretchAmount != 0))
1458                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1459                                         PHM_PlatformCaps_ClockStretcher);
1460
1461         data->pcie_gen_performance.max = PP_PCIEGen1;
1462         data->pcie_gen_performance.min = PP_PCIEGen3;
1463         data->pcie_gen_power_saving.max = PP_PCIEGen1;
1464         data->pcie_gen_power_saving.min = PP_PCIEGen3;
1465         data->pcie_lane_performance.max = 0;
1466         data->pcie_lane_performance.min = 16;
1467         data->pcie_lane_power_saving.max = 0;
1468         data->pcie_lane_power_saving.min = 16;
1469
1470         sys_info.size = sizeof(struct cgs_system_info);
1471         sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
1472         result = cgs_query_system_info(hwmgr->device, &sys_info);
1473         if (!result) {
1474                 if (sys_info.value & AMD_PG_SUPPORT_UVD)
1475                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1476                                       PHM_PlatformCaps_UVDPowerGating);
1477                 if (sys_info.value & AMD_PG_SUPPORT_VCE)
1478                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1479                                       PHM_PlatformCaps_VCEPowerGating);
1480         }
1481 }
1482
1483 /**
1484 * Get Leakage VDDC based on leakage ID.
1485 *
1486 * @param    hwmgr  the address of the powerplay hardware manager.
1487 * @return   always 0
1488 */
1489 static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
1490 {
1491         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1492         uint16_t vv_id;
1493         uint16_t vddc = 0;
1494         uint16_t vddgfx = 0;
1495         uint16_t i, j;
1496         uint32_t sclk = 0;
1497         struct phm_ppt_v1_information *table_info =
1498                         (struct phm_ppt_v1_information *)hwmgr->pptable;
1499         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL;
1500
1501
1502         for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
1503                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1504
1505                 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1506                         if ((hwmgr->pp_table_version == PP_TABLE_V1)
1507                             && !phm_get_sclk_for_voltage_evv(hwmgr,
1508                                                 table_info->vddgfx_lookup_table, vv_id, &sclk)) {
1509                                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1510                                                         PHM_PlatformCaps_ClockStretcher)) {
1511                                         sclk_table = table_info->vdd_dep_on_sclk;
1512
1513                                         for (j = 1; j < sclk_table->count; j++) {
1514                                                 if (sclk_table->entries[j].clk == sclk &&
1515                                                                 sclk_table->entries[j].cks_enable == 0) {
1516                                                         sclk += 5000;
1517                                                         break;
1518                                                 }
1519                                         }
1520                                 }
1521                                 if (0 == atomctrl_get_voltage_evv_on_sclk
1522                                     (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
1523                                      vv_id, &vddgfx)) {
1524                                         /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
1525                                         PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -EINVAL);
1526
1527                                         /* the voltage should not be zero nor equal to leakage ID */
1528                                         if (vddgfx != 0 && vddgfx != vv_id) {
1529                                                 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
1530                                                 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = vv_id;
1531                                                 data->vddcgfx_leakage.count++;
1532                                         }
1533                                 } else {
1534                                         pr_info("Error retrieving EVV voltage value!\n");
1535                                 }
1536                         }
1537                 } else {
1538                         if ((hwmgr->pp_table_version == PP_TABLE_V0)
1539                                 || !phm_get_sclk_for_voltage_evv(hwmgr,
1540                                         table_info->vddc_lookup_table, vv_id, &sclk)) {
1541                                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1542                                                 PHM_PlatformCaps_ClockStretcher)) {
1543                                         if (table_info == NULL)
1544                                                 return -EINVAL;
1545                                         sclk_table = table_info->vdd_dep_on_sclk;
1546
1547                                         for (j = 1; j < sclk_table->count; j++) {
1548                                                 if (sclk_table->entries[j].clk == sclk &&
1549                                                                 sclk_table->entries[j].cks_enable == 0) {
1550                                                         sclk += 5000;
1551                                                         break;
1552                                                 }
1553                                         }
1554                                 }
1555
1556                                 if (phm_get_voltage_evv_on_sclk(hwmgr,
1557                                                         VOLTAGE_TYPE_VDDC,
1558                                                         sclk, vv_id, &vddc) == 0) {
1559                                         if (vddc >= 2000 || vddc == 0)
1560                                                 return -EINVAL;
1561                                 } else {
1562                                         pr_debug("failed to retrieving EVV voltage!\n");
1563                                         continue;
1564                                 }
1565
1566                                 /* the voltage should not be zero nor equal to leakage ID */
1567                                 if (vddc != 0 && vddc != vv_id) {
1568                                         data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc);
1569                                         data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
1570                                         data->vddc_leakage.count++;
1571                                 }
1572                         }
1573                 }
1574         }
1575
1576         return 0;
1577 }
1578
1579 /**
1580  * Change virtual leakage voltage to actual value.
1581  *
1582  * @param     hwmgr  the address of the powerplay hardware manager.
1583  * @param     pointer to changing voltage
1584  * @param     pointer to leakage table
1585  */
1586 static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr,
1587                 uint16_t *voltage, struct smu7_leakage_voltage *leakage_table)
1588 {
1589         uint32_t index;
1590
1591         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
1592         for (index = 0; index < leakage_table->count; index++) {
1593                 /* if this voltage matches a leakage voltage ID */
1594                 /* patch with actual leakage voltage */
1595                 if (leakage_table->leakage_id[index] == *voltage) {
1596                         *voltage = leakage_table->actual_voltage[index];
1597                         break;
1598                 }
1599         }
1600
1601         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
1602                 pr_err("Voltage value looks like a Leakage ID but it's not patched \n");
1603 }
1604
1605 /**
1606 * Patch voltage lookup table by EVV leakages.
1607 *
1608 * @param     hwmgr  the address of the powerplay hardware manager.
1609 * @param     pointer to voltage lookup table
1610 * @param     pointer to leakage table
1611 * @return     always 0
1612 */
1613 static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
1614                 phm_ppt_v1_voltage_lookup_table *lookup_table,
1615                 struct smu7_leakage_voltage *leakage_table)
1616 {
1617         uint32_t i;
1618
1619         for (i = 0; i < lookup_table->count; i++)
1620                 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
1621                                 &lookup_table->entries[i].us_vdd, leakage_table);
1622
1623         return 0;
1624 }
1625
1626 static int smu7_patch_clock_voltage_limits_with_vddc_leakage(
1627                 struct pp_hwmgr *hwmgr, struct smu7_leakage_voltage *leakage_table,
1628                 uint16_t *vddc)
1629 {
1630         struct phm_ppt_v1_information *table_info =
1631                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1632         smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
1633         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
1634                         table_info->max_clock_voltage_on_dc.vddc;
1635         return 0;
1636 }
1637
1638 static int smu7_patch_voltage_dependency_tables_with_lookup_table(
1639                 struct pp_hwmgr *hwmgr)
1640 {
1641         uint8_t entry_id;
1642         uint8_t voltage_id;
1643         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1644         struct phm_ppt_v1_information *table_info =
1645                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1646
1647         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1648                         table_info->vdd_dep_on_sclk;
1649         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
1650                         table_info->vdd_dep_on_mclk;
1651         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1652                         table_info->mm_dep_table;
1653
1654         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1655                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1656                         voltage_id = sclk_table->entries[entry_id].vddInd;
1657                         sclk_table->entries[entry_id].vddgfx =
1658                                 table_info->vddgfx_lookup_table->entries[voltage_id].us_vdd;
1659                 }
1660         } else {
1661                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1662                         voltage_id = sclk_table->entries[entry_id].vddInd;
1663                         sclk_table->entries[entry_id].vddc =
1664                                 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1665                 }
1666         }
1667
1668         for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
1669                 voltage_id = mclk_table->entries[entry_id].vddInd;
1670                 mclk_table->entries[entry_id].vddc =
1671                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1672         }
1673
1674         for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
1675                 voltage_id = mm_table->entries[entry_id].vddcInd;
1676                 mm_table->entries[entry_id].vddc =
1677                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1678         }
1679
1680         return 0;
1681
1682 }
1683
1684 static int phm_add_voltage(struct pp_hwmgr *hwmgr,
1685                         phm_ppt_v1_voltage_lookup_table *look_up_table,
1686                         phm_ppt_v1_voltage_lookup_record *record)
1687 {
1688         uint32_t i;
1689
1690         PP_ASSERT_WITH_CODE((NULL != look_up_table),
1691                 "Lookup Table empty.", return -EINVAL);
1692         PP_ASSERT_WITH_CODE((0 != look_up_table->count),
1693                 "Lookup Table empty.", return -EINVAL);
1694
1695         i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
1696         PP_ASSERT_WITH_CODE((i >= look_up_table->count),
1697                 "Lookup Table is full.", return -EINVAL);
1698
1699         /* This is to avoid entering duplicate calculated records. */
1700         for (i = 0; i < look_up_table->count; i++) {
1701                 if (look_up_table->entries[i].us_vdd == record->us_vdd) {
1702                         if (look_up_table->entries[i].us_calculated == 1)
1703                                 return 0;
1704                         break;
1705                 }
1706         }
1707
1708         look_up_table->entries[i].us_calculated = 1;
1709         look_up_table->entries[i].us_vdd = record->us_vdd;
1710         look_up_table->entries[i].us_cac_low = record->us_cac_low;
1711         look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
1712         look_up_table->entries[i].us_cac_high = record->us_cac_high;
1713         /* Only increment the count when we're appending, not replacing duplicate entry. */
1714         if (i == look_up_table->count)
1715                 look_up_table->count++;
1716
1717         return 0;
1718 }
1719
1720
1721 static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
1722 {
1723         uint8_t entry_id;
1724         struct phm_ppt_v1_voltage_lookup_record v_record;
1725         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1726         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1727
1728         phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
1729         phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
1730
1731         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1732                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1733                         if (sclk_table->entries[entry_id].vdd_offset & (1 << 15))
1734                                 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
1735                                         sclk_table->entries[entry_id].vdd_offset - 0xFFFF;
1736                         else
1737                                 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
1738                                         sclk_table->entries[entry_id].vdd_offset;
1739
1740                         sclk_table->entries[entry_id].vddc =
1741                                 v_record.us_cac_low = v_record.us_cac_mid =
1742                                 v_record.us_cac_high = v_record.us_vdd;
1743
1744                         phm_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record);
1745                 }
1746
1747                 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
1748                         if (mclk_table->entries[entry_id].vdd_offset & (1 << 15))
1749                                 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
1750                                         mclk_table->entries[entry_id].vdd_offset - 0xFFFF;
1751                         else
1752                                 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
1753                                         mclk_table->entries[entry_id].vdd_offset;
1754
1755                         mclk_table->entries[entry_id].vddgfx = v_record.us_cac_low =
1756                                 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
1757                         phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
1758                 }
1759         }
1760         return 0;
1761 }
1762
1763 static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
1764 {
1765         uint8_t entry_id;
1766         struct phm_ppt_v1_voltage_lookup_record v_record;
1767         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1768         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1769         phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1770
1771         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1772                 for (entry_id = 0; entry_id < mm_table->count; entry_id++) {
1773                         if (mm_table->entries[entry_id].vddgfx_offset & (1 << 15))
1774                                 v_record.us_vdd = mm_table->entries[entry_id].vddc +
1775                                         mm_table->entries[entry_id].vddgfx_offset - 0xFFFF;
1776                         else
1777                                 v_record.us_vdd = mm_table->entries[entry_id].vddc +
1778                                         mm_table->entries[entry_id].vddgfx_offset;
1779
1780                         /* Add the calculated VDDGFX to the VDDGFX lookup table */
1781                         mm_table->entries[entry_id].vddgfx = v_record.us_cac_low =
1782                                 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
1783                         phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
1784                 }
1785         }
1786         return 0;
1787 }
1788
1789 static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr,
1790                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
1791 {
1792         uint32_t table_size, i, j;
1793         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
1794         table_size = lookup_table->count;
1795
1796         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
1797                 "Lookup table is empty", return -EINVAL);
1798
1799         /* Sorting voltages */
1800         for (i = 0; i < table_size - 1; i++) {
1801                 for (j = i + 1; j > 0; j--) {
1802                         if (lookup_table->entries[j].us_vdd <
1803                                         lookup_table->entries[j - 1].us_vdd) {
1804                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
1805                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
1806                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
1807                         }
1808                 }
1809         }
1810
1811         return 0;
1812 }
1813
1814 static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr)
1815 {
1816         int result = 0;
1817         int tmp_result;
1818         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1819         struct phm_ppt_v1_information *table_info =
1820                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1821
1822         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1823                 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
1824                         table_info->vddgfx_lookup_table, &(data->vddcgfx_leakage));
1825                 if (tmp_result != 0)
1826                         result = tmp_result;
1827
1828                 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
1829                         &table_info->max_clock_voltage_on_dc.vddgfx, &(data->vddcgfx_leakage));
1830         } else {
1831
1832                 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
1833                                 table_info->vddc_lookup_table, &(data->vddc_leakage));
1834                 if (tmp_result)
1835                         result = tmp_result;
1836
1837                 tmp_result = smu7_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
1838                                 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
1839                 if (tmp_result)
1840                         result = tmp_result;
1841         }
1842
1843         tmp_result = smu7_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
1844         if (tmp_result)
1845                 result = tmp_result;
1846
1847         tmp_result = smu7_calc_voltage_dependency_tables(hwmgr);
1848         if (tmp_result)
1849                 result = tmp_result;
1850
1851         tmp_result = smu7_calc_mm_voltage_dependency_table(hwmgr);
1852         if (tmp_result)
1853                 result = tmp_result;
1854
1855         tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddgfx_lookup_table);
1856         if (tmp_result)
1857                 result = tmp_result;
1858
1859         tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
1860         if (tmp_result)
1861                 result = tmp_result;
1862
1863         return result;
1864 }
1865
1866 static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr)
1867 {
1868         struct phm_ppt_v1_information *table_info =
1869                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1870
1871         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
1872                                                 table_info->vdd_dep_on_sclk;
1873         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
1874                                                 table_info->vdd_dep_on_mclk;
1875
1876         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
1877                 "VDD dependency on SCLK table is missing.",
1878                 return -EINVAL);
1879         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
1880                 "VDD dependency on SCLK table has to have is missing.",
1881                 return -EINVAL);
1882
1883         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
1884                 "VDD dependency on MCLK table is missing",
1885                 return -EINVAL);
1886         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
1887                 "VDD dependency on MCLK table has to have is missing.",
1888                 return -EINVAL);
1889
1890         table_info->max_clock_voltage_on_ac.sclk =
1891                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
1892         table_info->max_clock_voltage_on_ac.mclk =
1893                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
1894         table_info->max_clock_voltage_on_ac.vddc =
1895                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
1896         table_info->max_clock_voltage_on_ac.vddci =
1897                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
1898
1899         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
1900         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
1901         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
1902         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = table_info->max_clock_voltage_on_ac.vddci;
1903
1904         return 0;
1905 }
1906
1907 static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
1908 {
1909         struct phm_ppt_v1_information *table_info =
1910                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
1911         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
1912         struct phm_ppt_v1_voltage_lookup_table *lookup_table;
1913         uint32_t i;
1914         uint32_t hw_revision, sub_vendor_id, sub_sys_id;
1915         struct cgs_system_info sys_info = {0};
1916
1917         if (table_info != NULL) {
1918                 dep_mclk_table = table_info->vdd_dep_on_mclk;
1919                 lookup_table = table_info->vddc_lookup_table;
1920         } else
1921                 return 0;
1922
1923         sys_info.size = sizeof(struct cgs_system_info);
1924
1925         sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
1926         cgs_query_system_info(hwmgr->device, &sys_info);
1927         hw_revision = (uint32_t)sys_info.value;
1928
1929         sys_info.info_id = CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID;
1930         cgs_query_system_info(hwmgr->device, &sys_info);
1931         sub_sys_id = (uint32_t)sys_info.value;
1932
1933         sys_info.info_id = CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID;
1934         cgs_query_system_info(hwmgr->device, &sys_info);
1935         sub_vendor_id = (uint32_t)sys_info.value;
1936
1937         if (hwmgr->chip_id == CHIP_POLARIS10 && hw_revision == 0xC7 &&
1938                         ((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) ||
1939                     (sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) ||
1940                     (sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) {
1941                 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
1942                         return 0;
1943
1944                 for (i = 0; i < lookup_table->count; i++) {
1945                         if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) {
1946                                 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;
1947                                 return 0;
1948                         }
1949                 }
1950         }
1951         return 0;
1952 }
1953
1954 static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr)
1955 {
1956         struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
1957         uint32_t temp_reg;
1958         struct phm_ppt_v1_information *table_info =
1959                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1960
1961
1962         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
1963                 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
1964                 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
1965                 case 0:
1966                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
1967                         break;
1968                 case 1:
1969                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
1970                         break;
1971                 case 2:
1972                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
1973                         break;
1974                 case 3:
1975                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
1976                         break;
1977                 case 4:
1978                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
1979                         break;
1980                 default:
1981                         break;
1982                 }
1983                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
1984         }
1985
1986         if (table_info == NULL)
1987                 return 0;
1988
1989         if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
1990                 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
1991                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
1992                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
1993
1994                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
1995                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
1996
1997                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
1998
1999                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
2000
2001                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
2002                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
2003
2004                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
2005
2006                 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
2007                                                                 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp - 50) : 0;
2008
2009                 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2010                 table_info->cac_dtp_table->usOperatingTempStep = 1;
2011                 table_info->cac_dtp_table->usOperatingTempHyst = 1;
2012
2013                 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
2014                                hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
2015
2016                 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
2017                                hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
2018
2019                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
2020                                table_info->cac_dtp_table->usOperatingTempMinLimit;
2021
2022                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
2023                                table_info->cac_dtp_table->usOperatingTempMaxLimit;
2024
2025                 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
2026                                table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2027
2028                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
2029                                table_info->cac_dtp_table->usOperatingTempStep;
2030
2031                 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
2032                                table_info->cac_dtp_table->usTargetOperatingTemp;
2033                 if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK)
2034                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2035                                         PHM_PlatformCaps_ODFuzzyFanControlSupport);
2036         }
2037
2038         return 0;
2039 }
2040
2041 /**
2042  * Change virtual leakage voltage to actual value.
2043  *
2044  * @param     hwmgr  the address of the powerplay hardware manager.
2045  * @param     pointer to changing voltage
2046  * @param     pointer to leakage table
2047  */
2048 static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2049                 uint32_t *voltage, struct smu7_leakage_voltage *leakage_table)
2050 {
2051         uint32_t index;
2052
2053         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2054         for (index = 0; index < leakage_table->count; index++) {
2055                 /* if this voltage matches a leakage voltage ID */
2056                 /* patch with actual leakage voltage */
2057                 if (leakage_table->leakage_id[index] == *voltage) {
2058                         *voltage = leakage_table->actual_voltage[index];
2059                         break;
2060                 }
2061         }
2062
2063         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2064                 pr_err("Voltage value looks like a Leakage ID but it's not patched \n");
2065 }
2066
2067
2068 static int smu7_patch_vddc(struct pp_hwmgr *hwmgr,
2069                               struct phm_clock_voltage_dependency_table *tab)
2070 {
2071         uint16_t i;
2072         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2073
2074         if (tab)
2075                 for (i = 0; i < tab->count; i++)
2076                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2077                                                 &data->vddc_leakage);
2078
2079         return 0;
2080 }
2081
2082 static int smu7_patch_vddci(struct pp_hwmgr *hwmgr,
2083                                struct phm_clock_voltage_dependency_table *tab)
2084 {
2085         uint16_t i;
2086         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2087
2088         if (tab)
2089                 for (i = 0; i < tab->count; i++)
2090                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2091                                                         &data->vddci_leakage);
2092
2093         return 0;
2094 }
2095
2096 static int smu7_patch_vce_vddc(struct pp_hwmgr *hwmgr,
2097                                   struct phm_vce_clock_voltage_dependency_table *tab)
2098 {
2099         uint16_t i;
2100         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2101
2102         if (tab)
2103                 for (i = 0; i < tab->count; i++)
2104                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2105                                                         &data->vddc_leakage);
2106
2107         return 0;
2108 }
2109
2110
2111 static int smu7_patch_uvd_vddc(struct pp_hwmgr *hwmgr,
2112                                   struct phm_uvd_clock_voltage_dependency_table *tab)
2113 {
2114         uint16_t i;
2115         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2116
2117         if (tab)
2118                 for (i = 0; i < tab->count; i++)
2119                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2120                                                         &data->vddc_leakage);
2121
2122         return 0;
2123 }
2124
2125 static int smu7_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr,
2126                                          struct phm_phase_shedding_limits_table *tab)
2127 {
2128         uint16_t i;
2129         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2130
2131         if (tab)
2132                 for (i = 0; i < tab->count; i++)
2133                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].Voltage,
2134                                                         &data->vddc_leakage);
2135
2136         return 0;
2137 }
2138
2139 static int smu7_patch_samu_vddc(struct pp_hwmgr *hwmgr,
2140                                    struct phm_samu_clock_voltage_dependency_table *tab)
2141 {
2142         uint16_t i;
2143         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2144
2145         if (tab)
2146                 for (i = 0; i < tab->count; i++)
2147                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2148                                                         &data->vddc_leakage);
2149
2150         return 0;
2151 }
2152
2153 static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr,
2154                                   struct phm_acp_clock_voltage_dependency_table *tab)
2155 {
2156         uint16_t i;
2157         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2158
2159         if (tab)
2160                 for (i = 0; i < tab->count; i++)
2161                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2162                                         &data->vddc_leakage);
2163
2164         return 0;
2165 }
2166
2167 static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr,
2168                                   struct phm_clock_and_voltage_limits *tab)
2169 {
2170         uint32_t vddc, vddci;
2171         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2172
2173         if (tab) {
2174                 vddc = tab->vddc;
2175                 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc,
2176                                                    &data->vddc_leakage);
2177                 tab->vddc = vddc;
2178                 vddci = tab->vddci;
2179                 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci,
2180                                                    &data->vddci_leakage);
2181                 tab->vddci = vddci;
2182         }
2183
2184         return 0;
2185 }
2186
2187 static int smu7_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab)
2188 {
2189         uint32_t i;
2190         uint32_t vddc;
2191         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2192
2193         if (tab) {
2194                 for (i = 0; i < tab->count; i++) {
2195                         vddc = (uint32_t)(tab->entries[i].Vddc);
2196                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, &data->vddc_leakage);
2197                         tab->entries[i].Vddc = (uint16_t)vddc;
2198                 }
2199         }
2200
2201         return 0;
2202 }
2203
2204 static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr)
2205 {
2206         int tmp;
2207
2208         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk);
2209         if (tmp)
2210                 return -EINVAL;
2211
2212         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk);
2213         if (tmp)
2214                 return -EINVAL;
2215
2216         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2217         if (tmp)
2218                 return -EINVAL;
2219
2220         tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk);
2221         if (tmp)
2222                 return -EINVAL;
2223
2224         tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table);
2225         if (tmp)
2226                 return -EINVAL;
2227
2228         tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
2229         if (tmp)
2230                 return -EINVAL;
2231
2232         tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table);
2233         if (tmp)
2234                 return -EINVAL;
2235
2236         tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table);
2237         if (tmp)
2238                 return -EINVAL;
2239
2240         tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table);
2241         if (tmp)
2242                 return -EINVAL;
2243
2244         tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac);
2245         if (tmp)
2246                 return -EINVAL;
2247
2248         tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc);
2249         if (tmp)
2250                 return -EINVAL;
2251
2252         tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table);
2253         if (tmp)
2254                 return -EINVAL;
2255
2256         return 0;
2257 }
2258
2259
2260 static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
2261 {
2262         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2263
2264         struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
2265         struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
2266         struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
2267
2268         PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL,
2269                 "VDDC dependency on SCLK table is missing. This table is mandatory\n", return -EINVAL);
2270         PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1,
2271                 "VDDC dependency on SCLK table has to have is missing. This table is mandatory\n", return -EINVAL);
2272
2273         PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL,
2274                 "VDDC dependency on MCLK table is missing. This table is mandatory\n", return -EINVAL);
2275         PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1,
2276                 "VDD dependency on MCLK table has to have is missing. This table is mandatory\n", return -EINVAL);
2277
2278         data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v;
2279         data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2280
2281         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
2282                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
2283         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
2284                 allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk;
2285         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
2286                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2287
2288         if (allowed_mclk_vddci_table != NULL && allowed_mclk_vddci_table->count >= 1) {
2289                 data->min_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[0].v;
2290                 data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
2291         }
2292
2293         if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1)
2294                 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v;
2295
2296         return 0;
2297 }
2298
2299 static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2300 {
2301         kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2302         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
2303         kfree(hwmgr->backend);
2304         hwmgr->backend = NULL;
2305
2306         return 0;
2307 }
2308
2309 static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr)
2310 {
2311         uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id;
2312         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2313         int i;
2314
2315         if (atomctrl_get_leakage_id_from_efuse(hwmgr, &efuse_voltage_id) == 0) {
2316                 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
2317                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2318                         if (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, &vddc, &vddci,
2319                                                                 virtual_voltage_id,
2320                                                                 efuse_voltage_id) == 0) {
2321                                 if (vddc != 0 && vddc != virtual_voltage_id) {
2322                                         data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
2323                                         data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
2324                                         data->vddc_leakage.count++;
2325                                 }
2326                                 if (vddci != 0 && vddci != virtual_voltage_id) {
2327                                         data->vddci_leakage.actual_voltage[data->vddci_leakage.count] = vddci;
2328                                         data->vddci_leakage.leakage_id[data->vddci_leakage.count] = virtual_voltage_id;
2329                                         data->vddci_leakage.count++;
2330                                 }
2331                         }
2332                 }
2333         }
2334         return 0;
2335 }
2336
2337 static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2338 {
2339         struct smu7_hwmgr *data;
2340         int result = 0;
2341
2342         data = kzalloc(sizeof(struct smu7_hwmgr), GFP_KERNEL);
2343         if (data == NULL)
2344                 return -ENOMEM;
2345
2346         hwmgr->backend = data;
2347         smu7_patch_voltage_workaround(hwmgr);
2348         smu7_init_dpm_defaults(hwmgr);
2349
2350         /* Get leakage voltage based on leakage ID. */
2351         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2352                         PHM_PlatformCaps_EVV)) {
2353                 result = smu7_get_evv_voltages(hwmgr);
2354                 if (result) {
2355                         pr_info("Get EVV Voltage Failed.  Abort Driver loading!\n");
2356                         return -EINVAL;
2357                 }
2358         } else {
2359                 smu7_get_elb_voltages(hwmgr);
2360         }
2361
2362         if (hwmgr->pp_table_version == PP_TABLE_V1) {
2363                 smu7_complete_dependency_tables(hwmgr);
2364                 smu7_set_private_data_based_on_pptable_v1(hwmgr);
2365         } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
2366                 smu7_patch_dependency_tables_with_leakage(hwmgr);
2367                 smu7_set_private_data_based_on_pptable_v0(hwmgr);
2368         }
2369
2370         /* Initalize Dynamic State Adjustment Rule Settings */
2371         result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
2372
2373         if (0 == result) {
2374                 struct cgs_system_info sys_info = {0};
2375
2376                 data->is_tlu_enabled = false;
2377
2378                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
2379                                                         SMU7_MAX_HARDWARE_POWERLEVELS;
2380                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
2381                 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
2382
2383                 sys_info.size = sizeof(struct cgs_system_info);
2384                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
2385                 result = cgs_query_system_info(hwmgr->device, &sys_info);
2386                 if (result)
2387                         data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2388                 else
2389                         data->pcie_gen_cap = (uint32_t)sys_info.value;
2390                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
2391                         data->pcie_spc_cap = 20;
2392                 sys_info.size = sizeof(struct cgs_system_info);
2393                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
2394                 result = cgs_query_system_info(hwmgr->device, &sys_info);
2395                 if (result)
2396                         data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2397                 else
2398                         data->pcie_lane_cap = (uint32_t)sys_info.value;
2399
2400                 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
2401 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
2402                 hwmgr->platform_descriptor.clockStep.engineClock = 500;
2403                 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
2404                 smu7_thermal_parameter_init(hwmgr);
2405         } else {
2406                 /* Ignore return value in here, we are cleaning up a mess. */
2407                 smu7_hwmgr_backend_fini(hwmgr);
2408         }
2409
2410         return 0;
2411 }
2412
2413 static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
2414 {
2415         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2416         uint32_t level, tmp;
2417
2418         if (!data->pcie_dpm_key_disabled) {
2419                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
2420                         level = 0;
2421                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
2422                         while (tmp >>= 1)
2423                                 level++;
2424
2425                         if (level)
2426                                 smum_send_msg_to_smc_with_parameter(hwmgr,
2427                                                 PPSMC_MSG_PCIeDPM_ForceLevel, level);
2428                 }
2429         }
2430
2431         if (!data->sclk_dpm_key_disabled) {
2432                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2433                         level = 0;
2434                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
2435                         while (tmp >>= 1)
2436                                 level++;
2437
2438                         if (level)
2439                                 smum_send_msg_to_smc_with_parameter(hwmgr,
2440                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2441                                                 (1 << level));
2442                 }
2443         }
2444
2445         if (!data->mclk_dpm_key_disabled) {
2446                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
2447                         level = 0;
2448                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
2449                         while (tmp >>= 1)
2450                                 level++;
2451
2452                         if (level)
2453                                 smum_send_msg_to_smc_with_parameter(hwmgr,
2454                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
2455                                                 (1 << level));
2456                 }
2457         }
2458
2459         return 0;
2460 }
2461
2462 static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
2463 {
2464         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2465
2466         if (hwmgr->pp_table_version == PP_TABLE_V1)
2467                 phm_apply_dal_min_voltage_request(hwmgr);
2468 /* TO DO  for v0 iceland and Ci*/
2469
2470         if (!data->sclk_dpm_key_disabled) {
2471                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
2472                         smum_send_msg_to_smc_with_parameter(hwmgr,
2473                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
2474                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
2475         }
2476
2477         if (!data->mclk_dpm_key_disabled) {
2478                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
2479                         smum_send_msg_to_smc_with_parameter(hwmgr,
2480                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
2481                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask);
2482         }
2483
2484         return 0;
2485 }
2486
2487 static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2488 {
2489         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2490
2491         if (!smum_is_dpm_running(hwmgr))
2492                 return -EINVAL;
2493
2494         if (!data->pcie_dpm_key_disabled) {
2495                 smum_send_msg_to_smc(hwmgr,
2496                                 PPSMC_MSG_PCIeDPM_UnForceLevel);
2497         }
2498
2499         return smu7_upload_dpm_level_enable_mask(hwmgr);
2500 }
2501
2502 static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2503 {
2504         struct smu7_hwmgr *data =
2505                         (struct smu7_hwmgr *)(hwmgr->backend);
2506         uint32_t level;
2507
2508         if (!data->sclk_dpm_key_disabled)
2509                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2510                         level = phm_get_lowest_enabled_level(hwmgr,
2511                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
2512                         smum_send_msg_to_smc_with_parameter(hwmgr,
2513                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
2514                                                             (1 << level));
2515
2516         }
2517
2518         if (!data->mclk_dpm_key_disabled) {
2519                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
2520                         level = phm_get_lowest_enabled_level(hwmgr,
2521                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
2522                         smum_send_msg_to_smc_with_parameter(hwmgr,
2523                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
2524                                                             (1 << level));
2525                 }
2526         }
2527
2528         if (!data->pcie_dpm_key_disabled) {
2529                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
2530                         level = phm_get_lowest_enabled_level(hwmgr,
2531                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
2532                         smum_send_msg_to_smc_with_parameter(hwmgr,
2533                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
2534                                                             (level));
2535                 }
2536         }
2537
2538         return 0;
2539 }
2540
2541 static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2542                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask)
2543 {
2544         uint32_t percentage;
2545         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2546         struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
2547         int32_t tmp_mclk;
2548         int32_t tmp_sclk;
2549         int32_t count;
2550
2551         if (golden_dpm_table->mclk_table.count < 1)
2552                 return -EINVAL;
2553
2554         percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value /
2555                         golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
2556
2557         if (golden_dpm_table->mclk_table.count == 1) {
2558                 percentage = 70;
2559                 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
2560                 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
2561         } else {
2562                 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value;
2563                 *mclk_mask = golden_dpm_table->mclk_table.count - 2;
2564         }
2565
2566         tmp_sclk = tmp_mclk * percentage / 100;
2567
2568         if (hwmgr->pp_table_version == PP_TABLE_V0) {
2569                 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
2570                         count >= 0; count--) {
2571                         if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) {
2572                                 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk;
2573                                 *sclk_mask = count;
2574                                 break;
2575                         }
2576                 }
2577                 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
2578                         *sclk_mask = 0;
2579
2580                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2581                         *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
2582         } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
2583                 struct phm_ppt_v1_information *table_info =
2584                                 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2585
2586                 for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
2587                         if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) {
2588                                 tmp_sclk = table_info->vdd_dep_on_sclk->entries[count].clk;
2589                                 *sclk_mask = count;
2590                                 break;
2591                         }
2592                 }
2593                 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
2594                         *sclk_mask = 0;
2595
2596                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2597                         *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
2598         }
2599
2600         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
2601                 *mclk_mask = 0;
2602         else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2603                 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
2604
2605         *pcie_mask = data->dpm_table.pcie_speed_table.count - 1;
2606         return 0;
2607 }
2608
2609 static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
2610                                 enum amd_dpm_forced_level level)
2611 {
2612         int ret = 0;
2613         uint32_t sclk_mask = 0;
2614         uint32_t mclk_mask = 0;
2615         uint32_t pcie_mask = 0;
2616
2617         switch (level) {
2618         case AMD_DPM_FORCED_LEVEL_HIGH:
2619                 ret = smu7_force_dpm_highest(hwmgr);
2620                 break;
2621         case AMD_DPM_FORCED_LEVEL_LOW:
2622                 ret = smu7_force_dpm_lowest(hwmgr);
2623                 break;
2624         case AMD_DPM_FORCED_LEVEL_AUTO:
2625                 ret = smu7_unforce_dpm_levels(hwmgr);
2626                 break;
2627         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2628         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2629         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2630         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2631                 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
2632                 if (ret)
2633                         return ret;
2634                 smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
2635                 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
2636                 smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask);
2637                 break;
2638         case AMD_DPM_FORCED_LEVEL_MANUAL:
2639         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2640         default:
2641                 break;
2642         }
2643
2644         if (!ret) {
2645                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2646                         smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
2647                 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2648                         smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
2649         }
2650         return ret;
2651 }
2652
2653 static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr)
2654 {
2655         return sizeof(struct smu7_power_state);
2656 }
2657
2658 static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr,
2659                                  uint32_t vblank_time_us)
2660 {
2661         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2662         uint32_t switch_limit_us;
2663
2664         switch (hwmgr->chip_id) {
2665         case CHIP_POLARIS10:
2666         case CHIP_POLARIS11:
2667         case CHIP_POLARIS12:
2668                 switch_limit_us = data->is_memory_gddr5 ? 190 : 150;
2669                 break;
2670         default:
2671                 switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
2672                 break;
2673         }
2674
2675         if (vblank_time_us < switch_limit_us)
2676                 return true;
2677         else
2678                 return false;
2679 }
2680
2681 static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
2682                                 struct pp_power_state *request_ps,
2683                         const struct pp_power_state *current_ps)
2684 {
2685
2686         struct smu7_power_state *smu7_ps =
2687                                 cast_phw_smu7_power_state(&request_ps->hardware);
2688         uint32_t sclk;
2689         uint32_t mclk;
2690         struct PP_Clocks minimum_clocks = {0};
2691         bool disable_mclk_switching;
2692         bool disable_mclk_switching_for_frame_lock;
2693         struct cgs_display_info info = {0};
2694         struct cgs_mode_info mode_info = {0};
2695         const struct phm_clock_and_voltage_limits *max_limits;
2696         uint32_t i;
2697         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2698         struct phm_ppt_v1_information *table_info =
2699                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2700         int32_t count;
2701         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
2702
2703         info.mode_info = &mode_info;
2704         data->battery_state = (PP_StateUILabel_Battery ==
2705                         request_ps->classification.ui_label);
2706
2707         PP_ASSERT_WITH_CODE(smu7_ps->performance_level_count == 2,
2708                                  "VI should always have 2 performance levels",
2709                                 );
2710
2711         max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
2712                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
2713                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
2714
2715         /* Cap clock DPM tables at DC MAX if it is in DC. */
2716         if (PP_PowerSource_DC == hwmgr->power_source) {
2717                 for (i = 0; i < smu7_ps->performance_level_count; i++) {
2718                         if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk)
2719                                 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk;
2720                         if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk)
2721                                 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk;
2722                 }
2723         }
2724
2725         cgs_get_active_displays_info(hwmgr->device, &info);
2726
2727         minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
2728         minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
2729
2730         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2731                         PHM_PlatformCaps_StablePState)) {
2732                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
2733                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
2734
2735                 for (count = table_info->vdd_dep_on_sclk->count - 1;
2736                                 count >= 0; count--) {
2737                         if (stable_pstate_sclk >=
2738                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
2739                                 stable_pstate_sclk =
2740                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
2741                                 break;
2742                         }
2743                 }
2744
2745                 if (count < 0)
2746                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
2747
2748                 stable_pstate_mclk = max_limits->mclk;
2749
2750                 minimum_clocks.engineClock = stable_pstate_sclk;
2751                 minimum_clocks.memoryClock = stable_pstate_mclk;
2752         }
2753
2754         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
2755                                     hwmgr->platform_descriptor.platformCaps,
2756                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
2757
2758
2759         disable_mclk_switching = ((1 < info.display_count) ||
2760                                   disable_mclk_switching_for_frame_lock ||
2761                                   smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) ||
2762                                   (mode_info.refresh_rate > 120));
2763
2764         sclk = smu7_ps->performance_levels[0].engine_clock;
2765         mclk = smu7_ps->performance_levels[0].memory_clock;
2766
2767         if (disable_mclk_switching)
2768                 mclk = smu7_ps->performance_levels
2769                 [smu7_ps->performance_level_count - 1].memory_clock;
2770
2771         if (sclk < minimum_clocks.engineClock)
2772                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
2773                                 max_limits->sclk : minimum_clocks.engineClock;
2774
2775         if (mclk < minimum_clocks.memoryClock)
2776                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
2777                                 max_limits->mclk : minimum_clocks.memoryClock;
2778
2779         smu7_ps->performance_levels[0].engine_clock = sclk;
2780         smu7_ps->performance_levels[0].memory_clock = mclk;
2781
2782         smu7_ps->performance_levels[1].engine_clock =
2783                 (smu7_ps->performance_levels[1].engine_clock >=
2784                                 smu7_ps->performance_levels[0].engine_clock) ?
2785                                                 smu7_ps->performance_levels[1].engine_clock :
2786                                                 smu7_ps->performance_levels[0].engine_clock;
2787
2788         if (disable_mclk_switching) {
2789                 if (mclk < smu7_ps->performance_levels[1].memory_clock)
2790                         mclk = smu7_ps->performance_levels[1].memory_clock;
2791
2792                 smu7_ps->performance_levels[0].memory_clock = mclk;
2793                 smu7_ps->performance_levels[1].memory_clock = mclk;
2794         } else {
2795                 if (smu7_ps->performance_levels[1].memory_clock <
2796                                 smu7_ps->performance_levels[0].memory_clock)
2797                         smu7_ps->performance_levels[1].memory_clock =
2798                                         smu7_ps->performance_levels[0].memory_clock;
2799         }
2800
2801         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2802                         PHM_PlatformCaps_StablePState)) {
2803                 for (i = 0; i < smu7_ps->performance_level_count; i++) {
2804                         smu7_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
2805                         smu7_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
2806                         smu7_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
2807                         smu7_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
2808                 }
2809         }
2810         return 0;
2811 }
2812
2813
2814 static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
2815 {
2816         struct pp_power_state  *ps;
2817         struct smu7_power_state  *smu7_ps;
2818
2819         if (hwmgr == NULL)
2820                 return -EINVAL;
2821
2822         ps = hwmgr->request_ps;
2823
2824         if (ps == NULL)
2825                 return -EINVAL;
2826
2827         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
2828
2829         if (low)
2830                 return smu7_ps->performance_levels[0].memory_clock;
2831         else
2832                 return smu7_ps->performance_levels
2833                                 [smu7_ps->performance_level_count-1].memory_clock;
2834 }
2835
2836 static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
2837 {
2838         struct pp_power_state  *ps;
2839         struct smu7_power_state  *smu7_ps;
2840
2841         if (hwmgr == NULL)
2842                 return -EINVAL;
2843
2844         ps = hwmgr->request_ps;
2845
2846         if (ps == NULL)
2847                 return -EINVAL;
2848
2849         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
2850
2851         if (low)
2852                 return smu7_ps->performance_levels[0].engine_clock;
2853         else
2854                 return smu7_ps->performance_levels
2855                                 [smu7_ps->performance_level_count-1].engine_clock;
2856 }
2857
2858 static int smu7_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
2859                                         struct pp_hw_power_state *hw_ps)
2860 {
2861         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2862         struct smu7_power_state *ps = (struct smu7_power_state *)hw_ps;
2863         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
2864         uint16_t size;
2865         uint8_t frev, crev;
2866         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2867
2868         /* First retrieve the Boot clocks and VDDC from the firmware info table.
2869          * We assume here that fw_info is unchanged if this call fails.
2870          */
2871         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
2872                         hwmgr->device, index,
2873                         &size, &frev, &crev);
2874         if (!fw_info)
2875                 /* During a test, there is no firmware info table. */
2876                 return 0;
2877
2878         /* Patch the state. */
2879         data->vbios_boot_state.sclk_bootup_value =
2880                         le32_to_cpu(fw_info->ulDefaultEngineClock);
2881         data->vbios_boot_state.mclk_bootup_value =
2882                         le32_to_cpu(fw_info->ulDefaultMemoryClock);
2883         data->vbios_boot_state.mvdd_bootup_value =
2884                         le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
2885         data->vbios_boot_state.vddc_bootup_value =
2886                         le16_to_cpu(fw_info->usBootUpVDDCVoltage);
2887         data->vbios_boot_state.vddci_bootup_value =
2888                         le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
2889         data->vbios_boot_state.pcie_gen_bootup_value =
2890                         smu7_get_current_pcie_speed(hwmgr);
2891
2892         data->vbios_boot_state.pcie_lane_bootup_value =
2893                         (uint16_t)smu7_get_current_pcie_lane_number(hwmgr);
2894
2895         /* set boot power state */
2896         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
2897         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
2898         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
2899         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
2900
2901         return 0;
2902 }
2903
2904 static int smu7_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr)
2905 {
2906         int result;
2907         unsigned long ret = 0;
2908
2909         if (hwmgr->pp_table_version == PP_TABLE_V0) {
2910                 result = pp_tables_get_num_of_entries(hwmgr, &ret);
2911                 return result ? 0 : ret;
2912         } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
2913                 result = get_number_of_powerplay_table_entries_v1_0(hwmgr);
2914                 return result;
2915         }
2916         return 0;
2917 }
2918
2919 static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
2920                 void *state, struct pp_power_state *power_state,
2921                 void *pp_table, uint32_t classification_flag)
2922 {
2923         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2924         struct smu7_power_state  *smu7_power_state =
2925                         (struct smu7_power_state *)(&(power_state->hardware));
2926         struct smu7_performance_level *performance_level;
2927         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
2928         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
2929                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
2930         PPTable_Generic_SubTable_Header *sclk_dep_table =
2931                         (PPTable_Generic_SubTable_Header *)
2932                         (((unsigned long)powerplay_table) +
2933                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
2934
2935         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
2936                         (ATOM_Tonga_MCLK_Dependency_Table *)
2937                         (((unsigned long)powerplay_table) +
2938                                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
2939
2940         /* The following fields are not initialized here: id orderedList allStatesList */
2941         power_state->classification.ui_label =
2942                         (le16_to_cpu(state_entry->usClassification) &
2943                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
2944                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
2945         power_state->classification.flags = classification_flag;
2946         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
2947
2948         power_state->classification.temporary_state = false;
2949         power_state->classification.to_be_deleted = false;
2950
2951         power_state->validation.disallowOnDC =
2952                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
2953                                         ATOM_Tonga_DISALLOW_ON_DC));
2954
2955         power_state->pcie.lanes = 0;
2956
2957         power_state->display.disableFrameModulation = false;
2958         power_state->display.limitRefreshrate = false;
2959         power_state->display.enableVariBright =
2960                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
2961                                         ATOM_Tonga_ENABLE_VARIBRIGHT));
2962
2963         power_state->validation.supportedPowerLevels = 0;
2964         power_state->uvd_clocks.VCLK = 0;
2965         power_state->uvd_clocks.DCLK = 0;
2966         power_state->temperatures.min = 0;
2967         power_state->temperatures.max = 0;
2968
2969         performance_level = &(smu7_power_state->performance_levels
2970                         [smu7_power_state->performance_level_count++]);
2971
2972         PP_ASSERT_WITH_CODE(
2973                         (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
2974                         "Performance levels exceeds SMC limit!",
2975                         return -EINVAL);
2976
2977         PP_ASSERT_WITH_CODE(
2978                         (smu7_power_state->performance_level_count <=
2979                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
2980                         "Performance levels exceeds Driver limit!",
2981                         return -EINVAL);
2982
2983         /* Performance levels are arranged from low to high. */
2984         performance_level->memory_clock = mclk_dep_table->entries
2985                         [state_entry->ucMemoryClockIndexLow].ulMclk;
2986         if (sclk_dep_table->ucRevId == 0)
2987                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
2988                         [state_entry->ucEngineClockIndexLow].ulSclk;
2989         else if (sclk_dep_table->ucRevId == 1)
2990                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
2991                         [state_entry->ucEngineClockIndexLow].ulSclk;
2992         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
2993                         state_entry->ucPCIEGenLow);
2994         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
2995                         state_entry->ucPCIELaneHigh);
2996
2997         performance_level = &(smu7_power_state->performance_levels
2998                         [smu7_power_state->performance_level_count++]);
2999         performance_level->memory_clock = mclk_dep_table->entries
3000                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
3001
3002         if (sclk_dep_table->ucRevId == 0)
3003                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3004                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3005         else if (sclk_dep_table->ucRevId == 1)
3006                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3007                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3008
3009         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3010                         state_entry->ucPCIEGenHigh);
3011         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3012                         state_entry->ucPCIELaneHigh);
3013
3014         return 0;
3015 }
3016
3017 static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr,
3018                 unsigned long entry_index, struct pp_power_state *state)
3019 {
3020         int result;
3021         struct smu7_power_state *ps;
3022         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3023         struct phm_ppt_v1_information *table_info =
3024                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3025         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3026                         table_info->vdd_dep_on_mclk;
3027
3028         state->hardware.magic = PHM_VIslands_Magic;
3029
3030         ps = (struct smu7_power_state *)(&state->hardware);
3031
3032         result = get_powerplay_table_entry_v1_0(hwmgr, entry_index, state,
3033                         smu7_get_pp_table_entry_callback_func_v1);
3034
3035         /* This is the earliest time we have all the dependency table and the VBIOS boot state
3036          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3037          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3038          */
3039         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3040                 if (dep_mclk_table->entries[0].clk !=
3041                                 data->vbios_boot_state.mclk_bootup_value)
3042                         pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
3043                                         "does not match VBIOS boot MCLK level");
3044                 if (dep_mclk_table->entries[0].vddci !=
3045                                 data->vbios_boot_state.vddci_bootup_value)
3046                         pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
3047                                         "does not match VBIOS boot VDDCI level");
3048         }
3049
3050         /* set DC compatible flag if this state supports DC */
3051         if (!state->validation.disallowOnDC)
3052                 ps->dc_compatible = true;
3053
3054         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3055                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3056
3057         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3058         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3059
3060         if (!result) {
3061                 uint32_t i;
3062
3063                 switch (state->classification.ui_label) {
3064                 case PP_StateUILabel_Performance:
3065                         data->use_pcie_performance_levels = true;
3066                         for (i = 0; i < ps->performance_level_count; i++) {
3067                                 if (data->pcie_gen_performance.max <
3068                                                 ps->performance_levels[i].pcie_gen)
3069                                         data->pcie_gen_performance.max =
3070                                                         ps->performance_levels[i].pcie_gen;
3071
3072                                 if (data->pcie_gen_performance.min >
3073                                                 ps->performance_levels[i].pcie_gen)
3074                                         data->pcie_gen_performance.min =
3075                                                         ps->performance_levels[i].pcie_gen;
3076
3077                                 if (data->pcie_lane_performance.max <
3078                                                 ps->performance_levels[i].pcie_lane)
3079                                         data->pcie_lane_performance.max =
3080                                                         ps->performance_levels[i].pcie_lane;
3081                                 if (data->pcie_lane_performance.min >
3082                                                 ps->performance_levels[i].pcie_lane)
3083                                         data->pcie_lane_performance.min =
3084                                                         ps->performance_levels[i].pcie_lane;
3085                         }
3086                         break;
3087                 case PP_StateUILabel_Battery:
3088                         data->use_pcie_power_saving_levels = true;
3089
3090                         for (i = 0; i < ps->performance_level_count; i++) {
3091                                 if (data->pcie_gen_power_saving.max <
3092                                                 ps->performance_levels[i].pcie_gen)
3093                                         data->pcie_gen_power_saving.max =
3094                                                         ps->performance_levels[i].pcie_gen;
3095
3096                                 if (data->pcie_gen_power_saving.min >
3097                                                 ps->performance_levels[i].pcie_gen)
3098                                         data->pcie_gen_power_saving.min =
3099                                                         ps->performance_levels[i].pcie_gen;
3100
3101                                 if (data->pcie_lane_power_saving.max <
3102                                                 ps->performance_levels[i].pcie_lane)
3103                                         data->pcie_lane_power_saving.max =
3104                                                         ps->performance_levels[i].pcie_lane;
3105
3106                                 if (data->pcie_lane_power_saving.min >
3107                                                 ps->performance_levels[i].pcie_lane)
3108                                         data->pcie_lane_power_saving.min =
3109                                                         ps->performance_levels[i].pcie_lane;
3110                         }
3111                         break;
3112                 default:
3113                         break;
3114                 }
3115         }
3116         return 0;
3117 }
3118
3119 static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr,
3120                                         struct pp_hw_power_state *power_state,
3121                                         unsigned int index, const void *clock_info)
3122 {
3123         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3124         struct smu7_power_state  *ps = cast_phw_smu7_power_state(power_state);
3125         const ATOM_PPLIB_CI_CLOCK_INFO *visland_clk_info = clock_info;
3126         struct smu7_performance_level *performance_level;
3127         uint32_t engine_clock, memory_clock;
3128         uint16_t pcie_gen_from_bios;
3129
3130         engine_clock = visland_clk_info->ucEngineClockHigh << 16 | visland_clk_info->usEngineClockLow;
3131         memory_clock = visland_clk_info->ucMemoryClockHigh << 16 | visland_clk_info->usMemoryClockLow;
3132
3133         if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk)
3134                 data->highest_mclk = memory_clock;
3135
3136         PP_ASSERT_WITH_CODE(
3137                         (ps->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
3138                         "Performance levels exceeds SMC limit!",
3139                         return -EINVAL);
3140
3141         PP_ASSERT_WITH_CODE(
3142                         (ps->performance_level_count <
3143                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3144                         "Performance levels exceeds Driver limit, Skip!",
3145                         return 0);
3146
3147         performance_level = &(ps->performance_levels
3148                         [ps->performance_level_count++]);
3149
3150         /* Performance levels are arranged from low to high. */
3151         performance_level->memory_clock = memory_clock;
3152         performance_level->engine_clock = engine_clock;
3153
3154         pcie_gen_from_bios = visland_clk_info->ucPCIEGen;
3155
3156         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, pcie_gen_from_bios);
3157         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, visland_clk_info->usPCIELane);
3158
3159         return 0;
3160 }
3161
3162 static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr,
3163                 unsigned long entry_index, struct pp_power_state *state)
3164 {
3165         int result;
3166         struct smu7_power_state *ps;
3167         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3168         struct phm_clock_voltage_dependency_table *dep_mclk_table =
3169                         hwmgr->dyn_state.vddci_dependency_on_mclk;
3170
3171         memset(&state->hardware, 0x00, sizeof(struct pp_hw_power_state));
3172
3173         state->hardware.magic = PHM_VIslands_Magic;
3174
3175         ps = (struct smu7_power_state *)(&state->hardware);
3176
3177         result = pp_tables_get_entry(hwmgr, entry_index, state,
3178                         smu7_get_pp_table_entry_callback_func_v0);
3179
3180         /*
3181          * This is the earliest time we have all the dependency table
3182          * and the VBIOS boot state as
3183          * PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot
3184          * state if there is only one VDDCI/MCLK level, check if it's
3185          * the same as VBIOS boot state
3186          */
3187         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3188                 if (dep_mclk_table->entries[0].clk !=
3189                                 data->vbios_boot_state.mclk_bootup_value)
3190                         pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
3191                                         "does not match VBIOS boot MCLK level");
3192                 if (dep_mclk_table->entries[0].v !=
3193                                 data->vbios_boot_state.vddci_bootup_value)
3194                         pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
3195                                         "does not match VBIOS boot VDDCI level");
3196         }
3197
3198         /* set DC compatible flag if this state supports DC */
3199         if (!state->validation.disallowOnDC)
3200                 ps->dc_compatible = true;
3201
3202         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3203                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3204
3205         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3206         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3207
3208         if (!result) {
3209                 uint32_t i;
3210
3211                 switch (state->classification.ui_label) {
3212                 case PP_StateUILabel_Performance:
3213                         data->use_pcie_performance_levels = true;
3214
3215                         for (i = 0; i < ps->performance_level_count; i++) {
3216                                 if (data->pcie_gen_performance.max <
3217                                                 ps->performance_levels[i].pcie_gen)
3218                                         data->pcie_gen_performance.max =
3219                                                         ps->performance_levels[i].pcie_gen;
3220
3221                                 if (data->pcie_gen_performance.min >
3222                                                 ps->performance_levels[i].pcie_gen)
3223                                         data->pcie_gen_performance.min =
3224                                                         ps->performance_levels[i].pcie_gen;
3225
3226                                 if (data->pcie_lane_performance.max <
3227                                                 ps->performance_levels[i].pcie_lane)
3228                                         data->pcie_lane_performance.max =
3229                                                         ps->performance_levels[i].pcie_lane;
3230
3231                                 if (data->pcie_lane_performance.min >
3232                                                 ps->performance_levels[i].pcie_lane)
3233                                         data->pcie_lane_performance.min =
3234                                                         ps->performance_levels[i].pcie_lane;
3235                         }
3236                         break;
3237                 case PP_StateUILabel_Battery:
3238                         data->use_pcie_power_saving_levels = true;
3239
3240                         for (i = 0; i < ps->performance_level_count; i++) {
3241                                 if (data->pcie_gen_power_saving.max <
3242                                                 ps->performance_levels[i].pcie_gen)
3243                                         data->pcie_gen_power_saving.max =
3244                                                         ps->performance_levels[i].pcie_gen;
3245
3246                                 if (data->pcie_gen_power_saving.min >
3247                                                 ps->performance_levels[i].pcie_gen)
3248                                         data->pcie_gen_power_saving.min =
3249                                                         ps->performance_levels[i].pcie_gen;
3250
3251                                 if (data->pcie_lane_power_saving.max <
3252                                                 ps->performance_levels[i].pcie_lane)
3253                                         data->pcie_lane_power_saving.max =
3254                                                         ps->performance_levels[i].pcie_lane;
3255
3256                                 if (data->pcie_lane_power_saving.min >
3257                                                 ps->performance_levels[i].pcie_lane)
3258                                         data->pcie_lane_power_saving.min =
3259                                                         ps->performance_levels[i].pcie_lane;
3260                         }
3261                         break;
3262                 default:
3263                         break;
3264                 }
3265         }
3266         return 0;
3267 }
3268
3269 static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3270                 unsigned long entry_index, struct pp_power_state *state)
3271 {
3272         if (hwmgr->pp_table_version == PP_TABLE_V0)
3273                 return smu7_get_pp_table_entry_v0(hwmgr, entry_index, state);
3274         else if (hwmgr->pp_table_version == PP_TABLE_V1)
3275                 return smu7_get_pp_table_entry_v1(hwmgr, entry_index, state);
3276
3277         return 0;
3278 }
3279
3280 static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr,
3281                 struct pp_gpu_power *query)
3282 {
3283         PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
3284                         PPSMC_MSG_PmStatusLogStart),
3285                         "Failed to start pm status log!",
3286                         return -1);
3287
3288         msleep_interruptible(20);
3289
3290         PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
3291                         PPSMC_MSG_PmStatusLogSample),
3292                         "Failed to sample pm status log!",
3293                         return -1);
3294
3295         query->vddc_power = cgs_read_ind_register(hwmgr->device,
3296                         CGS_IND_REG__SMC,
3297                         ixSMU_PM_STATUS_40);
3298         query->vddci_power = cgs_read_ind_register(hwmgr->device,
3299                         CGS_IND_REG__SMC,
3300                         ixSMU_PM_STATUS_49);
3301         query->max_gpu_power = cgs_read_ind_register(hwmgr->device,
3302                         CGS_IND_REG__SMC,
3303                         ixSMU_PM_STATUS_94);
3304         query->average_gpu_power = cgs_read_ind_register(hwmgr->device,
3305                         CGS_IND_REG__SMC,
3306                         ixSMU_PM_STATUS_95);
3307
3308         return 0;
3309 }
3310
3311 static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3312                             void *value, int *size)
3313 {
3314         uint32_t sclk, mclk, activity_percent;
3315         uint32_t offset;
3316         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3317
3318         /* size must be at least 4 bytes for all sensors */
3319         if (*size < 4)
3320                 return -EINVAL;
3321
3322         switch (idx) {
3323         case AMDGPU_PP_SENSOR_GFX_SCLK:
3324                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency);
3325                 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3326                 *((uint32_t *)value) = sclk;
3327                 *size = 4;
3328                 return 0;
3329         case AMDGPU_PP_SENSOR_GFX_MCLK:
3330                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
3331                 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3332                 *((uint32_t *)value) = mclk;
3333                 *size = 4;
3334                 return 0;
3335         case AMDGPU_PP_SENSOR_GPU_LOAD:
3336                 offset = data->soft_regs_start + smum_get_offsetof(hwmgr,
3337                                                                 SMU_SoftRegisters,
3338                                                                 AverageGraphicsActivity);
3339
3340                 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3341                 activity_percent += 0x80;
3342                 activity_percent >>= 8;
3343                 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
3344                 *size = 4;
3345                 return 0;
3346         case AMDGPU_PP_SENSOR_GPU_TEMP:
3347                 *((uint32_t *)value) = smu7_thermal_get_temperature(hwmgr);
3348                 *size = 4;
3349                 return 0;
3350         case AMDGPU_PP_SENSOR_UVD_POWER:
3351                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
3352                 *size = 4;
3353                 return 0;
3354         case AMDGPU_PP_SENSOR_VCE_POWER:
3355                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
3356                 *size = 4;
3357                 return 0;
3358         case AMDGPU_PP_SENSOR_GPU_POWER:
3359                 if (*size < sizeof(struct pp_gpu_power))
3360                         return -EINVAL;
3361                 *size = sizeof(struct pp_gpu_power);
3362                 return smu7_get_gpu_power(hwmgr, (struct pp_gpu_power *)value);
3363         default:
3364                 return -EINVAL;
3365         }
3366 }
3367
3368 static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3369 {
3370         const struct phm_set_power_state_input *states =
3371                         (const struct phm_set_power_state_input *)input;
3372         const struct smu7_power_state *smu7_ps =
3373                         cast_const_phw_smu7_power_state(states->pnew_state);
3374         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3375         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3376         uint32_t sclk = smu7_ps->performance_levels
3377                         [smu7_ps->performance_level_count - 1].engine_clock;
3378         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3379         uint32_t mclk = smu7_ps->performance_levels
3380                         [smu7_ps->performance_level_count - 1].memory_clock;
3381         struct PP_Clocks min_clocks = {0};
3382         uint32_t i;
3383         struct cgs_display_info info = {0};
3384
3385         data->need_update_smu7_dpm_table = 0;
3386
3387         for (i = 0; i < sclk_table->count; i++) {
3388                 if (sclk == sclk_table->dpm_levels[i].value)
3389                         break;
3390         }
3391
3392         if (i >= sclk_table->count)
3393                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3394         else {
3395         /* TODO: Check SCLK in DAL's minimum clocks
3396          * in case DeepSleep divider update is required.
3397          */
3398                 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3399                         (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK ||
3400                                 data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
3401                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3402         }
3403
3404         for (i = 0; i < mclk_table->count; i++) {
3405                 if (mclk == mclk_table->dpm_levels[i].value)
3406                         break;
3407         }
3408
3409         if (i >= mclk_table->count)
3410                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3411
3412         cgs_get_active_displays_info(hwmgr->device, &info);
3413
3414         if (data->display_timing.num_existing_displays != info.display_count)
3415                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3416
3417         return 0;
3418 }
3419
3420 static uint16_t smu7_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
3421                 const struct smu7_power_state *smu7_ps)
3422 {
3423         uint32_t i;
3424         uint32_t sclk, max_sclk = 0;
3425         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3426         struct smu7_dpm_table *dpm_table = &data->dpm_table;
3427
3428         for (i = 0; i < smu7_ps->performance_level_count; i++) {
3429                 sclk = smu7_ps->performance_levels[i].engine_clock;
3430                 if (max_sclk < sclk)
3431                         max_sclk = sclk;
3432         }
3433
3434         for (i = 0; i < dpm_table->sclk_table.count; i++) {
3435                 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
3436                         return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
3437                                         dpm_table->pcie_speed_table.dpm_levels
3438                                         [dpm_table->pcie_speed_table.count - 1].value :
3439                                         dpm_table->pcie_speed_table.dpm_levels[i].value);
3440         }
3441
3442         return 0;
3443 }
3444
3445 static int smu7_request_link_speed_change_before_state_change(
3446                 struct pp_hwmgr *hwmgr, const void *input)
3447 {
3448         const struct phm_set_power_state_input *states =
3449                         (const struct phm_set_power_state_input *)input;
3450         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3451         const struct smu7_power_state *smu7_nps =
3452                         cast_const_phw_smu7_power_state(states->pnew_state);
3453         const struct smu7_power_state *polaris10_cps =
3454                         cast_const_phw_smu7_power_state(states->pcurrent_state);
3455
3456         uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_nps);
3457         uint16_t current_link_speed;
3458
3459         if (data->force_pcie_gen == PP_PCIEGenInvalid)
3460                 current_link_speed = smu7_get_maximum_link_speed(hwmgr, polaris10_cps);
3461         else
3462                 current_link_speed = data->force_pcie_gen;
3463
3464         data->force_pcie_gen = PP_PCIEGenInvalid;
3465         data->pspp_notify_required = false;
3466
3467         if (target_link_speed > current_link_speed) {
3468                 switch (target_link_speed) {
3469                 case PP_PCIEGen3:
3470                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
3471                                 break;
3472                         data->force_pcie_gen = PP_PCIEGen2;
3473                         if (current_link_speed == PP_PCIEGen2)
3474                                 break;
3475                 case PP_PCIEGen2:
3476                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
3477                                 break;
3478                 default:
3479                         data->force_pcie_gen = smu7_get_current_pcie_speed(hwmgr);
3480                         break;
3481                 }
3482         } else {
3483                 if (target_link_speed < current_link_speed)
3484                         data->pspp_notify_required = true;
3485         }
3486
3487         return 0;
3488 }
3489
3490 static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3491 {
3492         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3493
3494         if (0 == data->need_update_smu7_dpm_table)
3495                 return 0;
3496
3497         if ((0 == data->sclk_dpm_key_disabled) &&
3498                 (data->need_update_smu7_dpm_table &
3499                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3500                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3501                                 "Trying to freeze SCLK DPM when DPM is disabled",
3502                                 );
3503                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3504                                 PPSMC_MSG_SCLKDPM_FreezeLevel),
3505                                 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3506                                 return -EINVAL);
3507         }
3508
3509         if ((0 == data->mclk_dpm_key_disabled) &&
3510                 (data->need_update_smu7_dpm_table &
3511                  DPMTABLE_OD_UPDATE_MCLK)) {
3512                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3513                                 "Trying to freeze MCLK DPM when DPM is disabled",
3514                                 );
3515                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3516                                 PPSMC_MSG_MCLKDPM_FreezeLevel),
3517                                 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3518                                 return -EINVAL);
3519         }
3520
3521         return 0;
3522 }
3523
3524 static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
3525                 struct pp_hwmgr *hwmgr, const void *input)
3526 {
3527         int result = 0;
3528         const struct phm_set_power_state_input *states =
3529                         (const struct phm_set_power_state_input *)input;
3530         const struct smu7_power_state *smu7_ps =
3531                         cast_const_phw_smu7_power_state(states->pnew_state);
3532         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3533         uint32_t sclk = smu7_ps->performance_levels
3534                         [smu7_ps->performance_level_count - 1].engine_clock;
3535         uint32_t mclk = smu7_ps->performance_levels
3536                         [smu7_ps->performance_level_count - 1].memory_clock;
3537         struct smu7_dpm_table *dpm_table = &data->dpm_table;
3538
3539         struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
3540         uint32_t dpm_count, clock_percent;
3541         uint32_t i;
3542
3543         if (0 == data->need_update_smu7_dpm_table)
3544                 return 0;
3545
3546         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3547                 dpm_table->sclk_table.dpm_levels
3548                 [dpm_table->sclk_table.count - 1].value = sclk;
3549
3550                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3551                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3552                 /* Need to do calculation based on the golden DPM table
3553                  * as the Heatmap GPU Clock axis is also based on the default values
3554                  */
3555                         PP_ASSERT_WITH_CODE(
3556                                 (golden_dpm_table->sclk_table.dpm_levels
3557                                                 [golden_dpm_table->sclk_table.count - 1].value != 0),
3558                                 "Divide by 0!",
3559                                 return -EINVAL);
3560                         dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
3561
3562                         for (i = dpm_count; i > 1; i--) {
3563                                 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
3564                                         clock_percent =
3565                                               ((sclk
3566                                                 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
3567                                                 ) * 100)
3568                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3569
3570                                         dpm_table->sclk_table.dpm_levels[i].value =
3571                                                         golden_dpm_table->sclk_table.dpm_levels[i].value +
3572                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
3573                                                                 clock_percent)/100;
3574
3575                                 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
3576                                         clock_percent =
3577                                                 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
3578                                                 - sclk) * 100)
3579                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3580
3581                                         dpm_table->sclk_table.dpm_levels[i].value =
3582                                                         golden_dpm_table->sclk_table.dpm_levels[i].value -
3583                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
3584                                                                         clock_percent) / 100;
3585                                 } else
3586                                         dpm_table->sclk_table.dpm_levels[i].value =
3587                                                         golden_dpm_table->sclk_table.dpm_levels[i].value;
3588                         }
3589                 }
3590         }
3591
3592         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3593                 dpm_table->mclk_table.dpm_levels
3594                         [dpm_table->mclk_table.count - 1].value = mclk;
3595
3596                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3597                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3598
3599                         PP_ASSERT_WITH_CODE(
3600                                         (golden_dpm_table->mclk_table.dpm_levels
3601                                                 [golden_dpm_table->mclk_table.count-1].value != 0),
3602                                         "Divide by 0!",
3603                                         return -EINVAL);
3604                         dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
3605                         for (i = dpm_count; i > 1; i--) {
3606                                 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
3607                                         clock_percent = ((mclk -
3608                                         golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
3609                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
3610
3611                                         dpm_table->mclk_table.dpm_levels[i].value =
3612                                                         golden_dpm_table->mclk_table.dpm_levels[i].value +
3613                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
3614                                                         clock_percent) / 100;
3615
3616                                 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
3617                                         clock_percent = (
3618                                          (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
3619                                         * 100)
3620                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
3621
3622                                         dpm_table->mclk_table.dpm_levels[i].value =
3623                                                         golden_dpm_table->mclk_table.dpm_levels[i].value -
3624                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
3625                                                                         clock_percent) / 100;
3626                                 } else
3627                                         dpm_table->mclk_table.dpm_levels[i].value =
3628                                                         golden_dpm_table->mclk_table.dpm_levels[i].value;
3629                         }
3630                 }
3631         }
3632
3633         if (data->need_update_smu7_dpm_table &
3634                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
3635                 result = smum_populate_all_graphic_levels(hwmgr);
3636                 PP_ASSERT_WITH_CODE((0 == result),
3637                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
3638                                 return result);
3639         }
3640
3641         if (data->need_update_smu7_dpm_table &
3642                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
3643                 /*populate MCLK dpm table to SMU7 */
3644                 result = smum_populate_all_memory_levels(hwmgr);
3645                 PP_ASSERT_WITH_CODE((0 == result),
3646                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
3647                                 return result);
3648         }
3649
3650         return result;
3651 }
3652
3653 static int smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
3654                           struct smu7_single_dpm_table *dpm_table,
3655                         uint32_t low_limit, uint32_t high_limit)
3656 {
3657         uint32_t i;
3658
3659         for (i = 0; i < dpm_table->count; i++) {
3660                 if ((dpm_table->dpm_levels[i].value < low_limit)
3661                 || (dpm_table->dpm_levels[i].value > high_limit))
3662                         dpm_table->dpm_levels[i].enabled = false;
3663                 else
3664                         dpm_table->dpm_levels[i].enabled = true;
3665         }
3666
3667         return 0;
3668 }
3669
3670 static int smu7_trim_dpm_states(struct pp_hwmgr *hwmgr,
3671                 const struct smu7_power_state *smu7_ps)
3672 {
3673         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3674         uint32_t high_limit_count;
3675
3676         PP_ASSERT_WITH_CODE((smu7_ps->performance_level_count >= 1),
3677                         "power state did not have any performance level",
3678                         return -EINVAL);
3679
3680         high_limit_count = (1 == smu7_ps->performance_level_count) ? 0 : 1;
3681
3682         smu7_trim_single_dpm_states(hwmgr,
3683                         &(data->dpm_table.sclk_table),
3684                         smu7_ps->performance_levels[0].engine_clock,
3685                         smu7_ps->performance_levels[high_limit_count].engine_clock);
3686
3687         smu7_trim_single_dpm_states(hwmgr,
3688                         &(data->dpm_table.mclk_table),
3689                         smu7_ps->performance_levels[0].memory_clock,
3690                         smu7_ps->performance_levels[high_limit_count].memory_clock);
3691
3692         return 0;
3693 }
3694
3695 static int smu7_generate_dpm_level_enable_mask(
3696                 struct pp_hwmgr *hwmgr, const void *input)
3697 {
3698         int result;
3699         const struct phm_set_power_state_input *states =
3700                         (const struct phm_set_power_state_input *)input;
3701         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3702         const struct smu7_power_state *smu7_ps =
3703                         cast_const_phw_smu7_power_state(states->pnew_state);
3704
3705         result = smu7_trim_dpm_states(hwmgr, smu7_ps);
3706         if (result)
3707                 return result;
3708
3709         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
3710                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
3711         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
3712                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
3713         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
3714                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
3715
3716         return 0;
3717 }
3718
3719 static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3720 {
3721         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3722
3723         if (0 == data->need_update_smu7_dpm_table)
3724                 return 0;
3725
3726         if ((0 == data->sclk_dpm_key_disabled) &&
3727                 (data->need_update_smu7_dpm_table &
3728                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3729
3730                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3731                                 "Trying to Unfreeze SCLK DPM when DPM is disabled",
3732                                 );
3733                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3734                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
3735                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
3736                         return -EINVAL);
3737         }
3738
3739         if ((0 == data->mclk_dpm_key_disabled) &&
3740                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
3741
3742                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3743                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",
3744                                 );
3745                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3746                                 PPSMC_MSG_MCLKDPM_UnfreezeLevel),
3747                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
3748                     return -EINVAL);
3749         }
3750
3751         data->need_update_smu7_dpm_table = 0;
3752
3753         return 0;
3754 }
3755
3756 static int smu7_notify_link_speed_change_after_state_change(
3757                 struct pp_hwmgr *hwmgr, const void *input)
3758 {
3759         const struct phm_set_power_state_input *states =
3760                         (const struct phm_set_power_state_input *)input;
3761         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3762         const struct smu7_power_state *smu7_ps =
3763                         cast_const_phw_smu7_power_state(states->pnew_state);
3764         uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_ps);
3765         uint8_t  request;
3766
3767         if (data->pspp_notify_required) {
3768                 if (target_link_speed == PP_PCIEGen3)
3769                         request = PCIE_PERF_REQ_GEN3;
3770                 else if (target_link_speed == PP_PCIEGen2)
3771                         request = PCIE_PERF_REQ_GEN2;
3772                 else
3773                         request = PCIE_PERF_REQ_GEN1;
3774
3775                 if (request == PCIE_PERF_REQ_GEN1 &&
3776                                 smu7_get_current_pcie_speed(hwmgr) > 0)
3777                         return 0;
3778
3779                 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
3780                         if (PP_PCIEGen2 == target_link_speed)
3781                                 pr_info("PSPP request to switch to Gen2 from Gen3 Failed!");
3782                         else
3783                                 pr_info("PSPP request to switch to Gen1 from Gen2 Failed!");
3784                 }
3785         }
3786
3787         return 0;
3788 }
3789
3790 static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr)
3791 {
3792         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3793
3794         if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK)
3795                 smum_send_msg_to_smc_with_parameter(hwmgr,
3796                         (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2);
3797         return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ?  0 : -EINVAL;
3798 }
3799
3800 static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
3801 {
3802         int tmp_result, result = 0;
3803         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3804
3805         tmp_result = smu7_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
3806         PP_ASSERT_WITH_CODE((0 == tmp_result),
3807                         "Failed to find DPM states clocks in DPM table!",
3808                         result = tmp_result);
3809
3810         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3811                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
3812                 tmp_result =
3813                         smu7_request_link_speed_change_before_state_change(hwmgr, input);
3814                 PP_ASSERT_WITH_CODE((0 == tmp_result),
3815                                 "Failed to request link speed change before state change!",
3816                                 result = tmp_result);
3817         }
3818
3819         tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr);
3820         PP_ASSERT_WITH_CODE((0 == tmp_result),
3821                         "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
3822
3823         tmp_result = smu7_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
3824         PP_ASSERT_WITH_CODE((0 == tmp_result),
3825                         "Failed to populate and upload SCLK MCLK DPM levels!",
3826                         result = tmp_result);
3827
3828         tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
3829         PP_ASSERT_WITH_CODE((0 == tmp_result),
3830                         "Failed to generate DPM level enabled mask!",
3831                         result = tmp_result);
3832
3833         tmp_result = smum_update_sclk_threshold(hwmgr);
3834         PP_ASSERT_WITH_CODE((0 == tmp_result),
3835                         "Failed to update SCLK threshold!",
3836                         result = tmp_result);
3837
3838         tmp_result = smu7_notify_smc_display(hwmgr);
3839         PP_ASSERT_WITH_CODE((0 == tmp_result),
3840                         "Failed to notify smc display settings!",
3841                         result = tmp_result);
3842
3843         tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr);
3844         PP_ASSERT_WITH_CODE((0 == tmp_result),
3845                         "Failed to unfreeze SCLK MCLK DPM!",
3846                         result = tmp_result);
3847
3848         tmp_result = smu7_upload_dpm_level_enable_mask(hwmgr);
3849         PP_ASSERT_WITH_CODE((0 == tmp_result),
3850                         "Failed to upload DPM level enabled mask!",
3851                         result = tmp_result);
3852
3853         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3854                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
3855                 tmp_result =
3856                         smu7_notify_link_speed_change_after_state_change(hwmgr, input);
3857                 PP_ASSERT_WITH_CODE((0 == tmp_result),
3858                                 "Failed to notify link speed change after state change!",
3859                                 result = tmp_result);
3860         }
3861         data->apply_optimized_settings = false;
3862         return result;
3863 }
3864
3865 static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
3866 {
3867         hwmgr->thermal_controller.
3868         advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
3869
3870         return smum_send_msg_to_smc_with_parameter(hwmgr,
3871                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
3872 }
3873
3874 static int
3875 smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
3876 {
3877         PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
3878
3879         return (smum_send_msg_to_smc(hwmgr, msg) == 0) ?  0 : -1;
3880 }
3881
3882 static int
3883 smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
3884 {
3885         uint32_t num_active_displays = 0;
3886         struct cgs_display_info info = {0};
3887
3888         info.mode_info = NULL;
3889         cgs_get_active_displays_info(hwmgr->device, &info);
3890
3891         num_active_displays = info.display_count;
3892
3893         if (num_active_displays > 1 && hwmgr->display_config.multi_monitor_in_sync != true)
3894                 smu7_notify_smc_display_change(hwmgr, false);
3895
3896         return 0;
3897 }
3898
3899 /**
3900 * Programs the display gap
3901 *
3902 * @param    hwmgr  the address of the powerplay hardware manager.
3903 * @return   always OK
3904 */
3905 static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
3906 {
3907         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3908         uint32_t num_active_displays = 0;
3909         uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
3910         uint32_t display_gap2;
3911         uint32_t pre_vbi_time_in_us;
3912         uint32_t frame_time_in_us;
3913         uint32_t ref_clock;
3914         uint32_t refresh_rate = 0;
3915         struct cgs_display_info info = {0};
3916         struct cgs_mode_info mode_info = {0};
3917
3918         info.mode_info = &mode_info;
3919         cgs_get_active_displays_info(hwmgr->device, &info);
3920         num_active_displays = info.display_count;
3921
3922         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
3923         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
3924
3925         ref_clock = mode_info.ref_clock;
3926         refresh_rate = mode_info.refresh_rate;
3927
3928         if (0 == refresh_rate)
3929                 refresh_rate = 60;
3930
3931         frame_time_in_us = 1000000 / refresh_rate;
3932
3933         pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
3934
3935         data->frame_time_x2 = frame_time_in_us * 2 / 100;
3936
3937         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
3938
3939         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
3940
3941         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3942                         data->soft_regs_start + smum_get_offsetof(hwmgr,
3943                                                         SMU_SoftRegisters,
3944                                                         PreVBlankGap), 0x64);
3945
3946         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3947                         data->soft_regs_start + smum_get_offsetof(hwmgr,
3948                                                         SMU_SoftRegisters,
3949                                                         VBlankTimeout),
3950                                         (frame_time_in_us - pre_vbi_time_in_us));
3951
3952         return 0;
3953 }
3954
3955 static int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
3956 {
3957         return smu7_program_display_gap(hwmgr);
3958 }
3959
3960 /**
3961 *  Set maximum target operating fan output RPM
3962 *
3963 * @param    hwmgr:  the address of the powerplay hardware manager.
3964 * @param    usMaxFanRpm:  max operating fan RPM value.
3965 * @return   The response that came from the SMC.
3966 */
3967 static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
3968 {
3969         hwmgr->thermal_controller.
3970         advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
3971
3972         return smum_send_msg_to_smc_with_parameter(hwmgr,
3973                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
3974 }
3975
3976 static int smu7_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
3977                                         const void *thermal_interrupt_info)
3978 {
3979         return 0;
3980 }
3981
3982 static bool
3983 smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
3984 {
3985         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3986         bool is_update_required = false;
3987         struct cgs_display_info info = {0, 0, NULL};
3988
3989         cgs_get_active_displays_info(hwmgr->device, &info);
3990
3991         if (data->display_timing.num_existing_displays != info.display_count)
3992                 is_update_required = true;
3993
3994         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
3995                 if (data->display_timing.min_clock_in_sr != hwmgr->display_config.min_core_set_clock_in_sr &&
3996                         (data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK ||
3997                         hwmgr->display_config.min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
3998                         is_update_required = true;
3999         }
4000         return is_update_required;
4001 }
4002
4003 static inline bool smu7_are_power_levels_equal(const struct smu7_performance_level *pl1,
4004                                                            const struct smu7_performance_level *pl2)
4005 {
4006         return ((pl1->memory_clock == pl2->memory_clock) &&
4007                   (pl1->engine_clock == pl2->engine_clock) &&
4008                   (pl1->pcie_gen == pl2->pcie_gen) &&
4009                   (pl1->pcie_lane == pl2->pcie_lane));
4010 }
4011
4012 static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
4013                 const struct pp_hw_power_state *pstate1,
4014                 const struct pp_hw_power_state *pstate2, bool *equal)
4015 {
4016         const struct smu7_power_state *psa;
4017         const struct smu7_power_state *psb;
4018         int i;
4019
4020         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4021                 return -EINVAL;
4022
4023         psa = cast_const_phw_smu7_power_state(pstate1);
4024         psb = cast_const_phw_smu7_power_state(pstate2);
4025         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4026         if (psa->performance_level_count != psb->performance_level_count) {
4027                 *equal = false;
4028                 return 0;
4029         }
4030
4031         for (i = 0; i < psa->performance_level_count; i++) {
4032                 if (!smu7_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4033                         /* If we have found even one performance level pair that is different the states are different. */
4034                         *equal = false;
4035                         return 0;
4036                 }
4037         }
4038
4039         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4040         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4041         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4042         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4043
4044         return 0;
4045 }
4046
4047 static int smu7_upload_mc_firmware(struct pp_hwmgr *hwmgr)
4048 {
4049         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4050
4051         uint32_t vbios_version;
4052         uint32_t tmp;
4053
4054         /* Read MC indirect register offset 0x9F bits [3:0] to see
4055          * if VBIOS has already loaded a full version of MC ucode
4056          * or not.
4057          */
4058
4059         smu7_get_mc_microcode_version(hwmgr);
4060         vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4061
4062         data->need_long_memory_training = false;
4063
4064         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX,
4065                                                         ixMC_IO_DEBUG_UP_13);
4066         tmp = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
4067
4068         if (tmp & (1 << 23)) {
4069                 data->mem_latency_high = MEM_LATENCY_HIGH;
4070                 data->mem_latency_low = MEM_LATENCY_LOW;
4071         } else {
4072                 data->mem_latency_high = 330;
4073                 data->mem_latency_low = 330;
4074         }
4075
4076         return 0;
4077 }
4078
4079 static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr)
4080 {
4081         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4082
4083         data->clock_registers.vCG_SPLL_FUNC_CNTL         =
4084                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
4085         data->clock_registers.vCG_SPLL_FUNC_CNTL_2       =
4086                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
4087         data->clock_registers.vCG_SPLL_FUNC_CNTL_3       =
4088                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
4089         data->clock_registers.vCG_SPLL_FUNC_CNTL_4       =
4090                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
4091         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM   =
4092                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
4093         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
4094                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
4095         data->clock_registers.vDLL_CNTL                  =
4096                 cgs_read_register(hwmgr->device, mmDLL_CNTL);
4097         data->clock_registers.vMCLK_PWRMGT_CNTL          =
4098                 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
4099         data->clock_registers.vMPLL_AD_FUNC_CNTL         =
4100                 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
4101         data->clock_registers.vMPLL_DQ_FUNC_CNTL         =
4102                 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
4103         data->clock_registers.vMPLL_FUNC_CNTL            =
4104                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
4105         data->clock_registers.vMPLL_FUNC_CNTL_1          =
4106                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
4107         data->clock_registers.vMPLL_FUNC_CNTL_2          =
4108                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
4109         data->clock_registers.vMPLL_SS1                  =
4110                 cgs_read_register(hwmgr->device, mmMPLL_SS1);
4111         data->clock_registers.vMPLL_SS2                  =
4112                 cgs_read_register(hwmgr->device, mmMPLL_SS2);
4113         return 0;
4114
4115 }
4116
4117 /**
4118  * Find out if memory is GDDR5.
4119  *
4120  * @param    hwmgr  the address of the powerplay hardware manager.
4121  * @return   always 0
4122  */
4123 static int smu7_get_memory_type(struct pp_hwmgr *hwmgr)
4124 {
4125         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4126         uint32_t temp;
4127
4128         temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4129
4130         data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4131                         ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4132                          MC_SEQ_MISC0_GDDR5_SHIFT));
4133
4134         return 0;
4135 }
4136
4137 /**
4138  * Enables Dynamic Power Management by SMC
4139  *
4140  * @param    hwmgr  the address of the powerplay hardware manager.
4141  * @return   always 0
4142  */
4143 static int smu7_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4144 {
4145         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4146                         GENERAL_PWRMGT, STATIC_PM_EN, 1);
4147
4148         return 0;
4149 }
4150
4151 /**
4152  * Initialize PowerGating States for different engines
4153  *
4154  * @param    hwmgr  the address of the powerplay hardware manager.
4155  * @return   always 0
4156  */
4157 static int smu7_init_power_gate_state(struct pp_hwmgr *hwmgr)
4158 {
4159         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4160
4161         data->uvd_power_gated = false;
4162         data->vce_power_gated = false;
4163         data->samu_power_gated = false;
4164
4165         return 0;
4166 }
4167
4168 static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4169 {
4170         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4171
4172         data->low_sclk_interrupt_threshold = 0;
4173         return 0;
4174 }
4175
4176 static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr)
4177 {
4178         int tmp_result, result = 0;
4179
4180         smu7_upload_mc_firmware(hwmgr);
4181
4182         tmp_result = smu7_read_clock_registers(hwmgr);
4183         PP_ASSERT_WITH_CODE((0 == tmp_result),
4184                         "Failed to read clock registers!", result = tmp_result);
4185
4186         tmp_result = smu7_get_memory_type(hwmgr);
4187         PP_ASSERT_WITH_CODE((0 == tmp_result),
4188                         "Failed to get memory type!", result = tmp_result);
4189
4190         tmp_result = smu7_enable_acpi_power_management(hwmgr);
4191         PP_ASSERT_WITH_CODE((0 == tmp_result),
4192                         "Failed to enable ACPI power management!", result = tmp_result);
4193
4194         tmp_result = smu7_init_power_gate_state(hwmgr);
4195         PP_ASSERT_WITH_CODE((0 == tmp_result),
4196                         "Failed to init power gate state!", result = tmp_result);
4197
4198         tmp_result = smu7_get_mc_microcode_version(hwmgr);
4199         PP_ASSERT_WITH_CODE((0 == tmp_result),
4200                         "Failed to get MC microcode version!", result = tmp_result);
4201
4202         tmp_result = smu7_init_sclk_threshold(hwmgr);
4203         PP_ASSERT_WITH_CODE((0 == tmp_result),
4204                         "Failed to init sclk threshold!", result = tmp_result);
4205
4206         return result;
4207 }
4208
4209 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
4210                 enum pp_clock_type type, uint32_t mask)
4211 {
4212         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4213
4214         if (hwmgr->request_dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO |
4215                                         AMD_DPM_FORCED_LEVEL_LOW |
4216                                         AMD_DPM_FORCED_LEVEL_HIGH))
4217                 return -EINVAL;
4218
4219         switch (type) {
4220         case PP_SCLK:
4221                 if (!data->sclk_dpm_key_disabled)
4222                         smum_send_msg_to_smc_with_parameter(hwmgr,
4223                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
4224                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
4225                 break;
4226         case PP_MCLK:
4227                 if (!data->mclk_dpm_key_disabled)
4228                         smum_send_msg_to_smc_with_parameter(hwmgr,
4229                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
4230                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
4231                 break;
4232         case PP_PCIE:
4233         {
4234                 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4235                 uint32_t level = 0;
4236
4237                 while (tmp >>= 1)
4238                         level++;
4239
4240                 if (!data->pcie_dpm_key_disabled)
4241                         smum_send_msg_to_smc_with_parameter(hwmgr,
4242                                         PPSMC_MSG_PCIeDPM_ForceLevel,
4243                                         level);
4244                 break;
4245         }
4246         default:
4247                 break;
4248         }
4249
4250         return 0;
4251 }
4252
4253 static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
4254                 enum pp_clock_type type, char *buf)
4255 {
4256         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4257         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4258         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4259         struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4260         int i, now, size = 0;
4261         uint32_t clock, pcie_speed;
4262
4263         switch (type) {
4264         case PP_SCLK:
4265                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency);
4266                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4267
4268                 for (i = 0; i < sclk_table->count; i++) {
4269                         if (clock > sclk_table->dpm_levels[i].value)
4270                                 continue;
4271                         break;
4272                 }
4273                 now = i;
4274
4275                 for (i = 0; i < sclk_table->count; i++)
4276                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4277                                         i, sclk_table->dpm_levels[i].value / 100,
4278                                         (i == now) ? "*" : "");
4279                 break;
4280         case PP_MCLK:
4281                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
4282                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4283
4284                 for (i = 0; i < mclk_table->count; i++) {
4285                         if (clock > mclk_table->dpm_levels[i].value)
4286                                 continue;
4287                         break;
4288                 }
4289                 now = i;
4290
4291                 for (i = 0; i < mclk_table->count; i++)
4292                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4293                                         i, mclk_table->dpm_levels[i].value / 100,
4294                                         (i == now) ? "*" : "");
4295                 break;
4296         case PP_PCIE:
4297                 pcie_speed = smu7_get_current_pcie_speed(hwmgr);
4298                 for (i = 0; i < pcie_table->count; i++) {
4299                         if (pcie_speed != pcie_table->dpm_levels[i].value)
4300                                 continue;
4301                         break;
4302                 }
4303                 now = i;
4304
4305                 for (i = 0; i < pcie_table->count; i++)
4306                         size += sprintf(buf + size, "%d: %s %s\n", i,
4307                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" :
4308                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" :
4309                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
4310                                         (i == now) ? "*" : "");
4311                 break;
4312         default:
4313                 break;
4314         }
4315         return size;
4316 }
4317
4318 static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4319 {
4320         switch (mode) {
4321         case AMD_FAN_CTRL_NONE:
4322                 smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
4323                 break;
4324         case AMD_FAN_CTRL_MANUAL:
4325                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4326                         PHM_PlatformCaps_MicrocodeFanControl))
4327                         smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
4328                 break;
4329         case AMD_FAN_CTRL_AUTO:
4330                 if (!smu7_fan_ctrl_set_static_mode(hwmgr, mode))
4331                         smu7_fan_ctrl_start_smc_fan_control(hwmgr);
4332                 break;
4333         default:
4334                 break;
4335         }
4336 }
4337
4338 static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4339 {
4340         return hwmgr->fan_ctrl_enabled ? AMD_FAN_CTRL_AUTO : AMD_FAN_CTRL_MANUAL;
4341 }
4342
4343 static int smu7_get_sclk_od(struct pp_hwmgr *hwmgr)
4344 {
4345         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4346         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4347         struct smu7_single_dpm_table *golden_sclk_table =
4348                         &(data->golden_dpm_table.sclk_table);
4349         int value;
4350
4351         value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
4352                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
4353                         100 /
4354                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
4355
4356         return value;
4357 }
4358
4359 static int smu7_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4360 {
4361         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4362         struct smu7_single_dpm_table *golden_sclk_table =
4363                         &(data->golden_dpm_table.sclk_table);
4364         struct pp_power_state  *ps;
4365         struct smu7_power_state  *smu7_ps;
4366
4367         if (value > 20)
4368                 value = 20;
4369
4370         ps = hwmgr->request_ps;
4371
4372         if (ps == NULL)
4373                 return -EINVAL;
4374
4375         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
4376
4377         smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].engine_clock =
4378                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
4379                         value / 100 +
4380                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
4381
4382         return 0;
4383 }
4384
4385 static int smu7_get_mclk_od(struct pp_hwmgr *hwmgr)
4386 {
4387         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4388         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4389         struct smu7_single_dpm_table *golden_mclk_table =
4390                         &(data->golden_dpm_table.mclk_table);
4391         int value;
4392
4393         value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
4394                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
4395                         100 /
4396                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
4397
4398         return value;
4399 }
4400
4401 static int smu7_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4402 {
4403         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4404         struct smu7_single_dpm_table *golden_mclk_table =
4405                         &(data->golden_dpm_table.mclk_table);
4406         struct pp_power_state  *ps;
4407         struct smu7_power_state  *smu7_ps;
4408
4409         if (value > 20)
4410                 value = 20;
4411
4412         ps = hwmgr->request_ps;
4413
4414         if (ps == NULL)
4415                 return -EINVAL;
4416
4417         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
4418
4419         smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].memory_clock =
4420                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
4421                         value / 100 +
4422                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
4423
4424         return 0;
4425 }
4426
4427
4428 static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
4429 {
4430         struct phm_ppt_v1_information *table_info =
4431                         (struct phm_ppt_v1_information *)hwmgr->pptable;
4432         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = NULL;
4433         struct phm_clock_voltage_dependency_table *sclk_table;
4434         int i;
4435
4436         if (hwmgr->pp_table_version == PP_TABLE_V1) {
4437                 if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL)
4438                         return -EINVAL;
4439                 dep_sclk_table = table_info->vdd_dep_on_sclk;
4440                 for (i = 0; i < dep_sclk_table->count; i++)
4441                         clocks->clock[i] = dep_sclk_table->entries[i].clk;
4442                 clocks->count = dep_sclk_table->count;
4443         } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
4444                 sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
4445                 for (i = 0; i < sclk_table->count; i++)
4446                         clocks->clock[i] = sclk_table->entries[i].clk;
4447                 clocks->count = sclk_table->count;
4448         }
4449
4450         return 0;
4451 }
4452
4453 static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk)
4454 {
4455         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4456
4457         if (clk >= MEM_FREQ_LOW_LATENCY && clk < MEM_FREQ_HIGH_LATENCY)
4458                 return data->mem_latency_high;
4459         else if (clk >= MEM_FREQ_HIGH_LATENCY)
4460                 return data->mem_latency_low;
4461         else
4462                 return MEM_LATENCY_ERR;
4463 }
4464
4465 static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
4466 {
4467         struct phm_ppt_v1_information *table_info =
4468                         (struct phm_ppt_v1_information *)hwmgr->pptable;
4469         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
4470         int i;
4471         struct phm_clock_voltage_dependency_table *mclk_table;
4472
4473         if (hwmgr->pp_table_version == PP_TABLE_V1) {
4474                 if (table_info == NULL)
4475                         return -EINVAL;
4476                 dep_mclk_table = table_info->vdd_dep_on_mclk;
4477                 for (i = 0; i < dep_mclk_table->count; i++) {
4478                         clocks->clock[i] = dep_mclk_table->entries[i].clk;
4479                         clocks->latency[i] = smu7_get_mem_latency(hwmgr,
4480                                                 dep_mclk_table->entries[i].clk);
4481                 }
4482                 clocks->count = dep_mclk_table->count;
4483         } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
4484                 mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
4485                 for (i = 0; i < mclk_table->count; i++)
4486                         clocks->clock[i] = mclk_table->entries[i].clk;
4487                 clocks->count = mclk_table->count;
4488         }
4489         return 0;
4490 }
4491
4492 static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
4493                                                 struct amd_pp_clocks *clocks)
4494 {
4495         switch (type) {
4496         case amd_pp_sys_clock:
4497                 smu7_get_sclks(hwmgr, clocks);
4498                 break;
4499         case amd_pp_mem_clock:
4500                 smu7_get_mclks(hwmgr, clocks);
4501                 break;
4502         default:
4503                 return -EINVAL;
4504         }
4505
4506         return 0;
4507 }
4508
4509 static void smu7_find_min_clock_masks(struct pp_hwmgr *hwmgr,
4510                 uint32_t *sclk_mask, uint32_t *mclk_mask,
4511                 uint32_t min_sclk, uint32_t min_mclk)
4512 {
4513         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4514         struct smu7_dpm_table *dpm_table = &(data->dpm_table);
4515         uint32_t i;
4516
4517         for (i = 0; i < dpm_table->sclk_table.count; i++) {
4518                 if (dpm_table->sclk_table.dpm_levels[i].enabled &&
4519                         dpm_table->sclk_table.dpm_levels[i].value >= min_sclk)
4520                         *sclk_mask |= 1 << i;
4521         }
4522
4523         for (i = 0; i < dpm_table->mclk_table.count; i++) {
4524                 if (dpm_table->mclk_table.dpm_levels[i].enabled &&
4525                         dpm_table->mclk_table.dpm_levels[i].value >= min_mclk)
4526                         *mclk_mask |= 1 << i;
4527         }
4528 }
4529
4530 static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
4531                 struct amd_pp_profile *request)
4532 {
4533         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4534         int tmp_result, result = 0;
4535         uint32_t sclk_mask = 0, mclk_mask = 0;
4536
4537         if (hwmgr->chip_id == CHIP_FIJI) {
4538                 if (request->type == AMD_PP_GFX_PROFILE)
4539                         smu7_enable_power_containment(hwmgr);
4540                 else if (request->type == AMD_PP_COMPUTE_PROFILE)
4541                         smu7_disable_power_containment(hwmgr);
4542         }
4543
4544         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO)
4545                 return -EINVAL;
4546
4547         tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr);
4548         PP_ASSERT_WITH_CODE(!tmp_result,
4549                         "Failed to freeze SCLK MCLK DPM!",
4550                         result = tmp_result);
4551
4552         tmp_result = smum_populate_requested_graphic_levels(hwmgr, request);
4553         PP_ASSERT_WITH_CODE(!tmp_result,
4554                         "Failed to populate requested graphic levels!",
4555                         result = tmp_result);
4556
4557         tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr);
4558         PP_ASSERT_WITH_CODE(!tmp_result,
4559                         "Failed to unfreeze SCLK MCLK DPM!",
4560                         result = tmp_result);
4561
4562         smu7_find_min_clock_masks(hwmgr, &sclk_mask, &mclk_mask,
4563                         request->min_sclk, request->min_mclk);
4564
4565         if (sclk_mask) {
4566                 if (!data->sclk_dpm_key_disabled)
4567                         smum_send_msg_to_smc_with_parameter(hwmgr,
4568                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
4569                                 data->dpm_level_enable_mask.
4570                                 sclk_dpm_enable_mask &
4571                                 sclk_mask);
4572         }
4573
4574         if (mclk_mask) {
4575                 if (!data->mclk_dpm_key_disabled)
4576                         smum_send_msg_to_smc_with_parameter(hwmgr,
4577                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4578                                 data->dpm_level_enable_mask.
4579                                 mclk_dpm_enable_mask &
4580                                 mclk_mask);
4581         }
4582
4583         return result;
4584 }
4585
4586 static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
4587 {
4588         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
4589
4590         if (smu_data == NULL)
4591                 return -EINVAL;
4592
4593         if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
4594                 return 0;
4595
4596         if (enable) {
4597                 if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
4598                                 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
4599                         PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
4600                                         hwmgr, PPSMC_MSG_EnableAvfs),
4601                                         "Failed to enable AVFS!",
4602                                         return -EINVAL);
4603         } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
4604                         CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
4605                 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
4606                                 hwmgr, PPSMC_MSG_DisableAvfs),
4607                                 "Failed to disable AVFS!",
4608                                 return -EINVAL);
4609
4610         return 0;
4611 }
4612
4613 static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
4614                                         uint32_t virtual_addr_low,
4615                                         uint32_t virtual_addr_hi,
4616                                         uint32_t mc_addr_low,
4617                                         uint32_t mc_addr_hi,
4618                                         uint32_t size)
4619 {
4620         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4621
4622         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4623                                         data->soft_regs_start +
4624                                         smum_get_offsetof(hwmgr,
4625                                         SMU_SoftRegisters, DRAM_LOG_ADDR_H),
4626                                         mc_addr_hi);
4627
4628         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4629                                         data->soft_regs_start +
4630                                         smum_get_offsetof(hwmgr,
4631                                         SMU_SoftRegisters, DRAM_LOG_ADDR_L),
4632                                         mc_addr_low);
4633
4634         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4635                                         data->soft_regs_start +
4636                                         smum_get_offsetof(hwmgr,
4637                                         SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_H),
4638                                         virtual_addr_hi);
4639
4640         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4641                                         data->soft_regs_start +
4642                                         smum_get_offsetof(hwmgr,
4643                                         SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_L),
4644                                         virtual_addr_low);
4645
4646         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4647                                         data->soft_regs_start +
4648                                         smum_get_offsetof(hwmgr,
4649                                         SMU_SoftRegisters, DRAM_LOG_BUFF_SIZE),
4650                                         size);
4651         return 0;
4652 }
4653
4654 static int smu7_get_max_high_clocks(struct pp_hwmgr *hwmgr,
4655                                         struct amd_pp_simple_clock_info *clocks)
4656 {
4657         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4658         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4659         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4660
4661         if (clocks == NULL)
4662                 return -EINVAL;
4663
4664         clocks->memory_max_clock = mclk_table->count > 1 ?
4665                                 mclk_table->dpm_levels[mclk_table->count-1].value :
4666                                 mclk_table->dpm_levels[0].value;
4667         clocks->engine_max_clock = sclk_table->count > 1 ?
4668                                 sclk_table->dpm_levels[sclk_table->count-1].value :
4669                                 sclk_table->dpm_levels[0].value;
4670         return 0;
4671 }
4672
4673 static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
4674         .backend_init = &smu7_hwmgr_backend_init,
4675         .backend_fini = &smu7_hwmgr_backend_fini,
4676         .asic_setup = &smu7_setup_asic_task,
4677         .dynamic_state_management_enable = &smu7_enable_dpm_tasks,
4678         .apply_state_adjust_rules = smu7_apply_state_adjust_rules,
4679         .force_dpm_level = &smu7_force_dpm_level,
4680         .power_state_set = smu7_set_power_state_tasks,
4681         .get_power_state_size = smu7_get_power_state_size,
4682         .get_mclk = smu7_dpm_get_mclk,
4683         .get_sclk = smu7_dpm_get_sclk,
4684         .patch_boot_state = smu7_dpm_patch_boot_state,
4685         .get_pp_table_entry = smu7_get_pp_table_entry,
4686         .get_num_of_pp_table_entries = smu7_get_number_of_powerplay_table_entries,
4687         .powerdown_uvd = smu7_powerdown_uvd,
4688         .powergate_uvd = smu7_powergate_uvd,
4689         .powergate_vce = smu7_powergate_vce,
4690         .disable_clock_power_gating = smu7_disable_clock_power_gating,
4691         .update_clock_gatings = smu7_update_clock_gatings,
4692         .notify_smc_display_config_after_ps_adjustment = smu7_notify_smc_display_config_after_ps_adjustment,
4693         .display_config_changed = smu7_display_configuration_changed_task,
4694         .set_max_fan_pwm_output = smu7_set_max_fan_pwm_output,
4695         .set_max_fan_rpm_output = smu7_set_max_fan_rpm_output,
4696         .get_temperature = smu7_thermal_get_temperature,
4697         .stop_thermal_controller = smu7_thermal_stop_thermal_controller,
4698         .get_fan_speed_info = smu7_fan_ctrl_get_fan_speed_info,
4699         .get_fan_speed_percent = smu7_fan_ctrl_get_fan_speed_percent,
4700         .set_fan_speed_percent = smu7_fan_ctrl_set_fan_speed_percent,
4701         .reset_fan_speed_to_default = smu7_fan_ctrl_reset_fan_speed_to_default,
4702         .get_fan_speed_rpm = smu7_fan_ctrl_get_fan_speed_rpm,
4703         .set_fan_speed_rpm = smu7_fan_ctrl_set_fan_speed_rpm,
4704         .uninitialize_thermal_controller = smu7_thermal_ctrl_uninitialize_thermal_controller,
4705         .register_internal_thermal_interrupt = smu7_register_internal_thermal_interrupt,
4706         .check_smc_update_required_for_display_configuration = smu7_check_smc_update_required_for_display_configuration,
4707         .check_states_equal = smu7_check_states_equal,
4708         .set_fan_control_mode = smu7_set_fan_control_mode,
4709         .get_fan_control_mode = smu7_get_fan_control_mode,
4710         .force_clock_level = smu7_force_clock_level,
4711         .print_clock_levels = smu7_print_clock_levels,
4712         .enable_per_cu_power_gating = smu7_enable_per_cu_power_gating,
4713         .get_sclk_od = smu7_get_sclk_od,
4714         .set_sclk_od = smu7_set_sclk_od,
4715         .get_mclk_od = smu7_get_mclk_od,
4716         .set_mclk_od = smu7_set_mclk_od,
4717         .get_clock_by_type = smu7_get_clock_by_type,
4718         .read_sensor = smu7_read_sensor,
4719         .dynamic_state_management_disable = smu7_disable_dpm_tasks,
4720         .set_power_profile_state = smu7_set_power_profile_state,
4721         .avfs_control = smu7_avfs_control,
4722         .disable_smc_firmware_ctf = smu7_thermal_disable_alert,
4723         .start_thermal_controller = smu7_start_thermal_controller,
4724         .notify_cac_buffer_info = smu7_notify_cac_buffer_info,
4725         .get_max_high_clocks = smu7_get_max_high_clocks,
4726 };
4727
4728 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
4729                 uint32_t clock_insr)
4730 {
4731         uint8_t i;
4732         uint32_t temp;
4733         uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK);
4734
4735         PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);
4736         for (i = SMU7_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
4737                 temp = clock >> i;
4738
4739                 if (temp >= min || i == 0)
4740                         break;
4741         }
4742         return i;
4743 }
4744
4745 int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)
4746 {
4747         int ret = 0;
4748
4749         hwmgr->hwmgr_func = &smu7_hwmgr_funcs;
4750         if (hwmgr->pp_table_version == PP_TABLE_V0)
4751                 hwmgr->pptable_func = &pptable_funcs;
4752         else if (hwmgr->pp_table_version == PP_TABLE_V1)
4753                 hwmgr->pptable_func = &pptable_v1_0_funcs;
4754
4755         return ret;
4756 }
4757