drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "pp_debug.h"
  24 #include <linux/delay.h>
  25 #include <linux/fb.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 #include <linux/slab.h>
  29 #include <asm/div64.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include "ppatomctrl.h"
  32 #include "atombios.h"
  33 #include "pptable_v1_0.h"
  34 #include "pppcielanes.h"
  35 #include "amd_pcie_helpers.h"
  36 #include "hardwaremanager.h"
  37 #include "process_pptables_v1_0.h"
  38 #include "cgs_common.h"
  39
  40 #include "smu7_common.h"
  41
  42 #include "hwmgr.h"
  43 #include "smu7_hwmgr.h"
  44 #include "smu_ucode_xfer_vi.h"
  45 #include "smu7_powertune.h"
  46 #include "smu7_dyn_defaults.h"
  47 #include "smu7_thermal.h"
  48 #include "smu7_clockpowergating.h"
  49 #include "processpptables.h"
  50 #include "pp_thermal.h"
  51 #include "smu7_baco.h"
  52
  53 #include "ivsrcid/ivsrcid_vislands30.h"
  54
  55 #define MC_CG_ARB_FREQ_F0           0x0a
  56 #define MC_CG_ARB_FREQ_F1           0x0b
  57 #define MC_CG_ARB_FREQ_F2           0x0c
  58 #define MC_CG_ARB_FREQ_F3           0x0d
  59
  60 #define MC_CG_SEQ_DRAMCONF_S0       0x05
  61 #define MC_CG_SEQ_DRAMCONF_S1       0x06
  62 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
  63 #define MC_CG_SEQ_YCLK_RESUME       0x0a
  64
  65 #define SMC_CG_IND_START            0xc0030000
  66 #define SMC_CG_IND_END              0xc0040000
  67
  68 #define MEM_FREQ_LOW_LATENCY        25000
  69 #define MEM_FREQ_HIGH_LATENCY       80000
  70
  71 #define MEM_LATENCY_HIGH            45
  72 #define MEM_LATENCY_LOW             35
  73 #define MEM_LATENCY_ERR             0xFFFF
  74
  75 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  76 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  77 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  78
  79 #define PCIE_BUS_CLK                10000
  80 #define TCLK                        (PCIE_BUS_CLK / 10)
  81
  82 static struct profile_mode_setting smu7_profiling[7] =
  83                                         {{0, 0, 0, 0, 0, 0, 0, 0},
  84                                          {1, 0, 100, 30, 1, 0, 100, 10},
  85                                          {1, 10, 0, 30, 0, 0, 0, 0},
  86                                          {0, 0, 0, 0, 1, 10, 16, 31},
  87                                          {1, 0, 11, 50, 1, 0, 100, 10},
  88                                          {1, 0, 5, 30, 0, 0, 0, 0},
  89                                          {0, 0, 0, 0, 0, 0, 0, 0},
  90                                         };
  91
  92 #define PPSMC_MSG_SetVBITimeout_VEGAM    ((uint16_t) 0x310)
  93
  94 #define ixPWR_SVI2_PLANE1_LOAD                     0xC0200280
  95 #define PWR_SVI2_PLANE1_LOAD__PSI1_MASK                    0x00000020L
  96 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN_MASK                 0x00000040L
  97 #define PWR_SVI2_PLANE1_LOAD__PSI1__SHIFT                  0x00000005
  98 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN__SHIFT               0x00000006
  99
 100 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 101 enum DPM_EVENT_SRC {
 102         DPM_EVENT_SRC_ANALOG = 0,
 103         DPM_EVENT_SRC_EXTERNAL = 1,
 104         DPM_EVENT_SRC_DIGITAL = 2,
 105         DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
 106         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
 107 };
 108
 109 static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
 110 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
 111                 enum pp_clock_type type, uint32_t mask);
 112
 113 static struct smu7_power_state *cast_phw_smu7_power_state(
 114                                   struct pp_hw_power_state *hw_ps)
 115 {
 116         PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
 117                                 "Invalid Powerstate Type!",
 118                                  return NULL);
 119
 120         return (struct smu7_power_state *)hw_ps;
 121 }
 122
 123 static const struct smu7_power_state *cast_const_phw_smu7_power_state(
 124                                  const struct pp_hw_power_state *hw_ps)
 125 {
 126         PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
 127                                 "Invalid Powerstate Type!",
 128                                  return NULL);
 129
 130         return (const struct smu7_power_state *)hw_ps;
 131 }
 132
 133 /**
 134  * Find the MC microcode version and store it in the HwMgr struct
 135  *
 136  * @param    hwmgr  the address of the powerplay hardware manager.
 137  * @return   always 0
 138  */
 139 static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr)
 140 {
 141         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 142
 143         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
 144
 145         return 0;
 146 }
 147
 148 static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 149 {
 150         uint32_t speedCntl = 0;
 151
 152         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 153         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
 154                         ixPCIE_LC_SPEED_CNTL);
 155         return((uint16_t)PHM_GET_FIELD(speedCntl,
 156                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 157 }
 158
 159 static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 160 {
 161         uint32_t link_width;
 162
 163         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 164         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 165                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
 166
 167         PP_ASSERT_WITH_CODE((7 >= link_width),
 168                         "Invalid PCIe lane width!", return 0);
 169
 170         return decode_pcie_lane_width(link_width);
 171 }
 172
 173 /**
 174 * Enable voltage control
 175 *
 176 * @param    pHwMgr  the address of the powerplay hardware manager.
 177 * @return   always PP_Result_OK
 178 */
 179 static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
 180 {
 181         if (hwmgr->chip_id == CHIP_VEGAM) {
 182                 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
 183                                 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI1, 0);
 184                 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
 185                                 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI0_EN, 0);
 186         }
 187
 188         if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
 189                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable, NULL);
 190
 191         return 0;
 192 }
 193
 194 /**
 195 * Checks if we want to support voltage control
 196 *
 197 * @param    hwmgr  the address of the powerplay hardware manager.
 198 */
 199 static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr)
 200 {
 201         const struct smu7_hwmgr *data =
 202                         (const struct smu7_hwmgr *)(hwmgr->backend);
 203
 204         return (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control);
 205 }
 206
 207 /**
 208 * Enable voltage control
 209 *
 210 * @param    hwmgr  the address of the powerplay hardware manager.
 211 * @return   always 0
 212 */
 213 static int smu7_enable_voltage_control(struct pp_hwmgr *hwmgr)
 214 {
 215         /* enable voltage control */
 216         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 217                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 218
 219         return 0;
 220 }
 221
 222 static int phm_get_svi2_voltage_table_v0(pp_atomctrl_voltage_table *voltage_table,
 223                 struct phm_clock_voltage_dependency_table *voltage_dependency_table
 224                 )
 225 {
 226         uint32_t i;
 227
 228         PP_ASSERT_WITH_CODE((NULL != voltage_table),
 229                         "Voltage Dependency Table empty.", return -EINVAL;);
 230
 231         voltage_table->mask_low = 0;
 232         voltage_table->phase_delay = 0;
 233         voltage_table->count = voltage_dependency_table->count;
 234
 235         for (i = 0; i < voltage_dependency_table->count; i++) {
 236                 voltage_table->entries[i].value =
 237                         voltage_dependency_table->entries[i].v;
 238                 voltage_table->entries[i].smio_low = 0;
 239         }
 240
 241         return 0;
 242 }
 243
 244
 245 /**
 246 * Create Voltage Tables.
 247 *
 248 * @param    hwmgr  the address of the powerplay hardware manager.
 249 * @return   always 0
 250 */
 251 static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr)
 252 {
 253         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 254         struct phm_ppt_v1_information *table_info =
 255                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 256         int result = 0;
 257         uint32_t tmp;
 258
 259         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 260                 result = atomctrl_get_voltage_table_v3(hwmgr,
 261                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
 262                                 &(data->mvdd_voltage_table));
 263                 PP_ASSERT_WITH_CODE((0 == result),
 264                                 "Failed to retrieve MVDD table.",
 265                                 return result);
 266         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
 267                 if (hwmgr->pp_table_version == PP_TABLE_V1)
 268                         result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
 269                                         table_info->vdd_dep_on_mclk);
 270                 else if (hwmgr->pp_table_version == PP_TABLE_V0)
 271                         result = phm_get_svi2_voltage_table_v0(&(data->mvdd_voltage_table),
 272                                         hwmgr->dyn_state.mvdd_dependency_on_mclk);
 273
 274                 PP_ASSERT_WITH_CODE((0 == result),
 275                                 "Failed to retrieve SVI2 MVDD table from dependency table.",
 276                                 return result;);
 277         }
 278
 279         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 280                 result = atomctrl_get_voltage_table_v3(hwmgr,
 281                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
 282                                 &(data->vddci_voltage_table));
 283                 PP_ASSERT_WITH_CODE((0 == result),
 284                                 "Failed to retrieve VDDCI table.",
 285                                 return result);
 286         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
 287                 if (hwmgr->pp_table_version == PP_TABLE_V1)
 288                         result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
 289                                         table_info->vdd_dep_on_mclk);
 290                 else if (hwmgr->pp_table_version == PP_TABLE_V0)
 291                         result = phm_get_svi2_voltage_table_v0(&(data->vddci_voltage_table),
 292                                         hwmgr->dyn_state.vddci_dependency_on_mclk);
 293                 PP_ASSERT_WITH_CODE((0 == result),
 294                                 "Failed to retrieve SVI2 VDDCI table from dependency table.",
 295                                 return result);
 296         }
 297
 298         if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
 299                 /* VDDGFX has only SVI2 voltage control */
 300                 result = phm_get_svi2_vdd_voltage_table(&(data->vddgfx_voltage_table),
 301                                         table_info->vddgfx_lookup_table);
 302                 PP_ASSERT_WITH_CODE((0 == result),
 303                         "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
 304         }
 305
 306
 307         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
 308                 result = atomctrl_get_voltage_table_v3(hwmgr,
 309                                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT,
 310                                         &data->vddc_voltage_table);
 311                 PP_ASSERT_WITH_CODE((0 == result),
 312                         "Failed to retrieve VDDC table.", return result;);
 313         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
 314
 315                 if (hwmgr->pp_table_version == PP_TABLE_V0)
 316                         result = phm_get_svi2_voltage_table_v0(&data->vddc_voltage_table,
 317                                         hwmgr->dyn_state.vddc_dependency_on_mclk);
 318                 else if (hwmgr->pp_table_version == PP_TABLE_V1)
 319                         result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
 320                                 table_info->vddc_lookup_table);
 321
 322                 PP_ASSERT_WITH_CODE((0 == result),
 323                         "Failed to retrieve SVI2 VDDC table from dependency table.", return result;);
 324         }
 325
 326         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC);
 327         PP_ASSERT_WITH_CODE(
 328                         (data->vddc_voltage_table.count <= tmp),
 329                 "Too many voltage values for VDDC. Trimming to fit state table.",
 330                         phm_trim_voltage_table_to_fit_state_table(tmp,
 331                                                 &(data->vddc_voltage_table)));
 332
 333         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
 334         PP_ASSERT_WITH_CODE(
 335                         (data->vddgfx_voltage_table.count <= tmp),
 336                 "Too many voltage values for VDDC. Trimming to fit state table.",
 337                         phm_trim_voltage_table_to_fit_state_table(tmp,
 338                                                 &(data->vddgfx_voltage_table)));
 339
 340         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI);
 341         PP_ASSERT_WITH_CODE(
 342                         (data->vddci_voltage_table.count <= tmp),
 343                 "Too many voltage values for VDDCI. Trimming to fit state table.",
 344                         phm_trim_voltage_table_to_fit_state_table(tmp,
 345                                         &(data->vddci_voltage_table)));
 346
 347         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD);
 348         PP_ASSERT_WITH_CODE(
 349                         (data->mvdd_voltage_table.count <= tmp),
 350                 "Too many voltage values for MVDD. Trimming to fit state table.",
 351                         phm_trim_voltage_table_to_fit_state_table(tmp,
 352                                                 &(data->mvdd_voltage_table)));
 353
 354         return 0;
 355 }
 356
 357 /**
 358 * Programs static screed detection parameters
 359 *
 360 * @param    hwmgr  the address of the powerplay hardware manager.
 361 * @return   always 0
 362 */
 363 static int smu7_program_static_screen_threshold_parameters(
 364                                                         struct pp_hwmgr *hwmgr)
 365 {
 366         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 367
 368         /* Set static screen threshold unit */
 369         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 370                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
 371                         data->static_screen_threshold_unit);
 372         /* Set static screen threshold */
 373         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 374                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
 375                         data->static_screen_threshold);
 376
 377         return 0;
 378 }
 379
 380 /**
 381 * Setup display gap for glitch free memory clock switching.
 382 *
 383 * @param    hwmgr  the address of the powerplay hardware manager.
 384 * @return   always  0
 385 */
 386 static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr)
 387 {
 388         uint32_t display_gap =
 389                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 390                                         ixCG_DISPLAY_GAP_CNTL);
 391
 392         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 393                         DISP_GAP, DISPLAY_GAP_IGNORE);
 394
 395         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 396                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
 397
 398         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 399                         ixCG_DISPLAY_GAP_CNTL, display_gap);
 400
 401         return 0;
 402 }
 403
 404 /**
 405 * Programs activity state transition voting clients
 406 *
 407 * @param    hwmgr  the address of the powerplay hardware manager.
 408 * @return   always  0
 409 */
 410 static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr)
 411 {
 412         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 413         int i;
 414
 415         /* Clear reset for voting clients before enabling DPM */
 416         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 417                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
 418         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 419                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
 420
 421         for (i = 0; i < 8; i++)
 422                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 423                                         ixCG_FREQ_TRAN_VOTING_0 + i * 4,
 424                                         data->voting_rights_clients[i]);
 425         return 0;
 426 }
 427
 428 static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr)
 429 {
 430         int i;
 431
 432         /* Reset voting clients before disabling DPM */
 433         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 434                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
 435         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 436                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
 437
 438         for (i = 0; i < 8; i++)
 439                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 440                                 ixCG_FREQ_TRAN_VOTING_0 + i * 4, 0);
 441
 442         return 0;
 443 }
 444
 445 /* Copy one arb setting to another and then switch the active set.
 446  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
 447  */
 448 static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
 449                 uint32_t arb_src, uint32_t arb_dest)
 450 {
 451         uint32_t mc_arb_dram_timing;
 452         uint32_t mc_arb_dram_timing2;
 453         uint32_t burst_time;
 454         uint32_t mc_cg_config;
 455
 456         switch (arb_src) {
 457         case MC_CG_ARB_FREQ_F0:
 458                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
 459                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
 460                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
 461                 break;
 462         case MC_CG_ARB_FREQ_F1:
 463                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
 464                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
 465                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
 466                 break;
 467         default:
 468                 return -EINVAL;
 469         }
 470
 471         switch (arb_dest) {
 472         case MC_CG_ARB_FREQ_F0:
 473                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 474                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 475                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
 476                 break;
 477         case MC_CG_ARB_FREQ_F1:
 478                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 479                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 480                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
 481                 break;
 482         default:
 483                 return -EINVAL;
 484         }
 485
 486         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
 487         mc_cg_config |= 0x0000000F;
 488         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
 489         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
 490
 491         return 0;
 492 }
 493
 494 static int smu7_reset_to_default(struct pp_hwmgr *hwmgr)
 495 {
 496         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults, NULL);
 497 }
 498
 499 /**
 500 * Initial switch from ARB F0->F1
 501 *
 502 * @param    hwmgr  the address of the powerplay hardware manager.
 503 * @return   always 0
 504 * This function is to be called from the SetPowerState table.
 505 */
 506 static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
 507 {
 508         return smu7_copy_and_switch_arb_sets(hwmgr,
 509                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
 510 }
 511
 512 static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
 513 {
 514         uint32_t tmp;
 515
 516         tmp = (cgs_read_ind_register(hwmgr->device,
 517                         CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
 518                         0x0000ff00) >> 8;
 519
 520         if (tmp == MC_CG_ARB_FREQ_F0)
 521                 return 0;
 522
 523         return smu7_copy_and_switch_arb_sets(hwmgr,
 524                         tmp, MC_CG_ARB_FREQ_F0);
 525 }
 526
 527 static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
 528 {
 529         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 530
 531         struct phm_ppt_v1_information *table_info =
 532                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 533         struct phm_ppt_v1_pcie_table *pcie_table = NULL;
 534
 535         uint32_t i, max_entry;
 536         uint32_t tmp;
 537
 538         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
 539                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
 540                         return -EINVAL);
 541
 542         if (table_info != NULL)
 543                 pcie_table = table_info->pcie_table;
 544
 545         if (data->use_pcie_performance_levels &&
 546                         !data->use_pcie_power_saving_levels) {
 547                 data->pcie_gen_power_saving = data->pcie_gen_performance;
 548                 data->pcie_lane_power_saving = data->pcie_lane_performance;
 549         } else if (!data->use_pcie_performance_levels &&
 550                         data->use_pcie_power_saving_levels) {
 551                 data->pcie_gen_performance = data->pcie_gen_power_saving;
 552                 data->pcie_lane_performance = data->pcie_lane_power_saving;
 553         }
 554         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK);
 555         phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
 556                                         tmp,
 557                                         MAX_REGULAR_DPM_NUMBER);
 558
 559         if (pcie_table != NULL) {
 560                 /* max_entry is used to make sure we reserve one PCIE level
 561                  * for boot level (fix for A+A PSPP issue).
 562                  * If PCIE table from PPTable have ULV entry + 8 entries,
 563                  * then ignore the last entry.*/
 564                 max_entry = (tmp < pcie_table->count) ? tmp : pcie_table->count;
 565                 for (i = 1; i < max_entry; i++) {
 566                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
 567                                         get_pcie_gen_support(data->pcie_gen_cap,
 568                                                         pcie_table->entries[i].gen_speed),
 569                                         get_pcie_lane_support(data->pcie_lane_cap,
 570                                                         pcie_table->entries[i].lane_width));
 571                 }
 572                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
 573                 smum_update_smc_table(hwmgr, SMU_BIF_TABLE);
 574         } else {
 575                 /* Hardcode Pcie Table */
 576                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
 577                                 get_pcie_gen_support(data->pcie_gen_cap,
 578                                                 PP_Min_PCIEGen),
 579                                 get_pcie_lane_support(data->pcie_lane_cap,
 580                                                 PP_Max_PCIELane));
 581                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
 582                                 get_pcie_gen_support(data->pcie_gen_cap,
 583                                                 PP_Min_PCIEGen),
 584                                 get_pcie_lane_support(data->pcie_lane_cap,
 585                                                 PP_Max_PCIELane));
 586                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
 587                                 get_pcie_gen_support(data->pcie_gen_cap,
 588                                                 PP_Max_PCIEGen),
 589                                 get_pcie_lane_support(data->pcie_lane_cap,
 590                                                 PP_Max_PCIELane));
 591                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
 592                                 get_pcie_gen_support(data->pcie_gen_cap,
 593                                                 PP_Max_PCIEGen),
 594                                 get_pcie_lane_support(data->pcie_lane_cap,
 595                                                 PP_Max_PCIELane));
 596                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
 597                                 get_pcie_gen_support(data->pcie_gen_cap,
 598                                                 PP_Max_PCIEGen),
 599                                 get_pcie_lane_support(data->pcie_lane_cap,
 600                                                 PP_Max_PCIELane));
 601                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
 602                                 get_pcie_gen_support(data->pcie_gen_cap,
 603                                                 PP_Max_PCIEGen),
 604                                 get_pcie_lane_support(data->pcie_lane_cap,
 605                                                 PP_Max_PCIELane));
 606
 607                 data->dpm_table.pcie_speed_table.count = 6;
 608         }
 609         /* Populate last level for boot PCIE level, but do not increment count. */
 610         if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
 611                 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++)
 612                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i,
 613                                 get_pcie_gen_support(data->pcie_gen_cap,
 614                                                 PP_Max_PCIEGen),
 615                                 data->vbios_boot_state.pcie_lane_bootup_value);
 616         } else {
 617                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
 618                         data->dpm_table.pcie_speed_table.count,
 619                         get_pcie_gen_support(data->pcie_gen_cap,
 620                                         PP_Min_PCIEGen),
 621                         get_pcie_lane_support(data->pcie_lane_cap,
 622                                         PP_Max_PCIELane));
 623         }
 624         return 0;
 625 }
 626
 627 static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr)
 628 {
 629         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 630
 631         memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
 632
 633         phm_reset_single_dpm_table(
 634                         &data->dpm_table.sclk_table,
 635                                 smum_get_mac_definition(hwmgr,
 636                                         SMU_MAX_LEVELS_GRAPHICS),
 637                                         MAX_REGULAR_DPM_NUMBER);
 638         phm_reset_single_dpm_table(
 639                         &data->dpm_table.mclk_table,
 640                         smum_get_mac_definition(hwmgr,
 641                                 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER);
 642
 643         phm_reset_single_dpm_table(
 644                         &data->dpm_table.vddc_table,
 645                                 smum_get_mac_definition(hwmgr,
 646                                         SMU_MAX_LEVELS_VDDC),
 647                                         MAX_REGULAR_DPM_NUMBER);
 648         phm_reset_single_dpm_table(
 649                         &data->dpm_table.vddci_table,
 650                         smum_get_mac_definition(hwmgr,
 651                                 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER);
 652
 653         phm_reset_single_dpm_table(
 654                         &data->dpm_table.mvdd_table,
 655                                 smum_get_mac_definition(hwmgr,
 656                                         SMU_MAX_LEVELS_MVDD),
 657                                         MAX_REGULAR_DPM_NUMBER);
 658         return 0;
 659 }
 660 /*
 661  * This function is to initialize all DPM state tables
 662  * for SMU7 based on the dependency table.
 663  * Dynamic state patching function will then trim these
 664  * state tables to the allowed range based
 665  * on the power policy or external client requests,
 666  * such as UVD request, etc.
 667  */
 668
 669 static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr)
 670 {
 671         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 672         struct phm_clock_voltage_dependency_table *allowed_vdd_sclk_table =
 673                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 674         struct phm_clock_voltage_dependency_table *allowed_vdd_mclk_table =
 675                 hwmgr->dyn_state.vddc_dependency_on_mclk;
 676         struct phm_cac_leakage_table *std_voltage_table =
 677                 hwmgr->dyn_state.cac_leakage_table;
 678         uint32_t i;
 679
 680         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
 681                 "SCLK dependency table is missing. This table is mandatory", return -EINVAL);
 682         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
 683                 "SCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
 684
 685         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
 686                 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
 687         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
 688                 "VMCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
 689
 690
 691         /* Initialize Sclk DPM table based on allow Sclk values*/
 692         data->dpm_table.sclk_table.count = 0;
 693
 694         for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
 695                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
 696                                 allowed_vdd_sclk_table->entries[i].clk) {
 697                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 698                                 allowed_vdd_sclk_table->entries[i].clk;
 699                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0;
 700                         data->dpm_table.sclk_table.count++;
 701                 }
 702         }
 703
 704         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
 705                 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
 706         /* Initialize Mclk DPM table based on allow Mclk values */
 707         data->dpm_table.mclk_table.count = 0;
 708         for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
 709                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
 710                         allowed_vdd_mclk_table->entries[i].clk) {
 711                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 712                                 allowed_vdd_mclk_table->entries[i].clk;
 713                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0;
 714                         data->dpm_table.mclk_table.count++;
 715                 }
 716         }
 717
 718         /* Initialize Vddc DPM table based on allow Vddc values.  And populate corresponding std values. */
 719         for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
 720                 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
 721                 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage;
 722                 /* param1 is for corresponding std voltage */
 723                 data->dpm_table.vddc_table.dpm_levels[i].enabled = true;
 724         }
 725
 726         data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
 727         allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
 728
 729         if (NULL != allowed_vdd_mclk_table) {
 730                 /* Initialize Vddci DPM table based on allow Mclk values */
 731                 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
 732                         data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
 733                         data->dpm_table.vddci_table.dpm_levels[i].enabled = true;
 734                 }
 735                 data->dpm_table.vddci_table.count = allowed_vdd_mclk_table->count;
 736         }
 737
 738         allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk;
 739
 740         if (NULL != allowed_vdd_mclk_table) {
 741                 /*
 742                  * Initialize MVDD DPM table based on allow Mclk
 743                  * values
 744                  */
 745                 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
 746                         data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
 747                         data->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
 748                 }
 749                 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
 750         }
 751
 752         return 0;
 753 }
 754
 755 static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
 756 {
 757         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 758         struct phm_ppt_v1_information *table_info =
 759                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 760         uint32_t i;
 761
 762         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
 763         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
 764
 765         if (table_info == NULL)
 766                 return -EINVAL;
 767
 768         dep_sclk_table = table_info->vdd_dep_on_sclk;
 769         dep_mclk_table = table_info->vdd_dep_on_mclk;
 770
 771         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
 772                         "SCLK dependency table is missing.",
 773                         return -EINVAL);
 774         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
 775                         "SCLK dependency table count is 0.",
 776                         return -EINVAL);
 777
 778         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
 779                         "MCLK dependency table is missing.",
 780                         return -EINVAL);
 781         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
 782                         "MCLK dependency table count is 0",
 783                         return -EINVAL);
 784
 785         /* Initialize Sclk DPM table based on allow Sclk values */
 786         data->dpm_table.sclk_table.count = 0;
 787         for (i = 0; i < dep_sclk_table->count; i++) {
 788                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
 789                                                 dep_sclk_table->entries[i].clk) {
 790
 791                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 792                                         dep_sclk_table->entries[i].clk;
 793
 794                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
 795                                         (i == 0) ? true : false;
 796                         data->dpm_table.sclk_table.count++;
 797                 }
 798         }
 799         if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
 800                 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk;
 801         /* Initialize Mclk DPM table based on allow Mclk values */
 802         data->dpm_table.mclk_table.count = 0;
 803         for (i = 0; i < dep_mclk_table->count; i++) {
 804                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
 805                                 [data->dpm_table.mclk_table.count - 1].value !=
 806                                                 dep_mclk_table->entries[i].clk) {
 807                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 808                                                         dep_mclk_table->entries[i].clk;
 809                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
 810                                                         (i == 0) ? true : false;
 811                         data->dpm_table.mclk_table.count++;
 812                 }
 813         }
 814
 815         if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
 816                 hwmgr->platform_descriptor.overdriveLimit.memoryClock = dep_mclk_table->entries[i-1].clk;
 817         return 0;
 818 }
 819
 820 static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
 821 {
 822         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 823         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
 824         struct phm_ppt_v1_information *table_info =
 825                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 826         uint32_t i;
 827
 828         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
 829         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
 830         struct phm_odn_performance_level *entries;
 831
 832         if (table_info == NULL)
 833                 return -EINVAL;
 834
 835         dep_sclk_table = table_info->vdd_dep_on_sclk;
 836         dep_mclk_table = table_info->vdd_dep_on_mclk;
 837
 838         odn_table->odn_core_clock_dpm_levels.num_of_pl =
 839                                                 data->golden_dpm_table.sclk_table.count;
 840         entries = odn_table->odn_core_clock_dpm_levels.entries;
 841         for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) {
 842                 entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value;
 843                 entries[i].enabled = true;
 844                 entries[i].vddc = dep_sclk_table->entries[i].vddc;
 845         }
 846
 847         smu_get_voltage_dependency_table_ppt_v1(dep_sclk_table,
 848                 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk));
 849
 850         odn_table->odn_memory_clock_dpm_levels.num_of_pl =
 851                                                 data->golden_dpm_table.mclk_table.count;
 852         entries = odn_table->odn_memory_clock_dpm_levels.entries;
 853         for (i=0; i<data->golden_dpm_table.mclk_table.count; i++) {
 854                 entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value;
 855                 entries[i].enabled = true;
 856                 entries[i].vddc = dep_mclk_table->entries[i].vddc;
 857         }
 858
 859         smu_get_voltage_dependency_table_ppt_v1(dep_mclk_table,
 860                 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk));
 861
 862         return 0;
 863 }
 864
 865 static void smu7_setup_voltage_range_from_vbios(struct pp_hwmgr *hwmgr)
 866 {
 867         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 868         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
 869         struct phm_ppt_v1_information *table_info =
 870                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 871         uint32_t min_vddc = 0;
 872         uint32_t max_vddc = 0;
 873
 874         if (!table_info)
 875                 return;
 876
 877         dep_sclk_table = table_info->vdd_dep_on_sclk;
 878
 879         atomctrl_get_voltage_range(hwmgr, &max_vddc, &min_vddc);
 880
 881         if (min_vddc == 0 || min_vddc > 2000
 882                 || min_vddc > dep_sclk_table->entries[0].vddc)
 883                 min_vddc = dep_sclk_table->entries[0].vddc;
 884
 885         if (max_vddc == 0 || max_vddc > 2000
 886                 || max_vddc < dep_sclk_table->entries[dep_sclk_table->count-1].vddc)
 887                 max_vddc = dep_sclk_table->entries[dep_sclk_table->count-1].vddc;
 888
 889         data->odn_dpm_table.min_vddc = min_vddc;
 890         data->odn_dpm_table.max_vddc = max_vddc;
 891 }
 892
 893 static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
 894 {
 895         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 896         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
 897         struct phm_ppt_v1_information *table_info =
 898                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 899         uint32_t i;
 900
 901         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
 902         struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
 903
 904         if (table_info == NULL)
 905                 return;
 906
 907         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
 908                 if (odn_table->odn_core_clock_dpm_levels.entries[i].clock !=
 909                                         data->dpm_table.sclk_table.dpm_levels[i].value) {
 910                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
 911                         break;
 912                 }
 913         }
 914
 915         for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
 916                 if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
 917                                         data->dpm_table.mclk_table.dpm_levels[i].value) {
 918                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
 919                         break;
 920                 }
 921         }
 922
 923         dep_table = table_info->vdd_dep_on_mclk;
 924         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk);
 925
 926         for (i = 0; i < dep_table->count; i++) {
 927                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
 928                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
 929                         return;
 930                 }
 931         }
 932
 933         dep_table = table_info->vdd_dep_on_sclk;
 934         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
 935         for (i = 0; i < dep_table->count; i++) {
 936                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
 937                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
 938                         return;
 939                 }
 940         }
 941         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
 942                 data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
 943                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
 944         }
 945 }
 946
 947 static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 948 {
 949         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 950
 951         smu7_reset_dpm_tables(hwmgr);
 952
 953         if (hwmgr->pp_table_version == PP_TABLE_V1)
 954                 smu7_setup_dpm_tables_v1(hwmgr);
 955         else if (hwmgr->pp_table_version == PP_TABLE_V0)
 956                 smu7_setup_dpm_tables_v0(hwmgr);
 957
 958         smu7_setup_default_pcie_table(hwmgr);
 959
 960         /* save a copy of the default DPM table */
 961         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 962                         sizeof(struct smu7_dpm_table));
 963
 964         /* initialize ODN table */
 965         if (hwmgr->od_enabled) {
 966                 if (data->odn_dpm_table.max_vddc) {
 967                         smu7_check_dpm_table_updated(hwmgr);
 968                 } else {
 969                         smu7_setup_voltage_range_from_vbios(hwmgr);
 970                         smu7_odn_initial_default_setting(hwmgr);
 971                 }
 972         }
 973         return 0;
 974 }
 975
 976 static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
 977 {
 978
 979         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 980                         PHM_PlatformCaps_RegulatorHot))
 981                 return smum_send_msg_to_smc(hwmgr,
 982                                 PPSMC_MSG_EnableVRHotGPIOInterrupt,
 983                                 NULL);
 984
 985         return 0;
 986 }
 987
 988 static int smu7_enable_sclk_control(struct pp_hwmgr *hwmgr)
 989 {
 990         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
 991                         SCLK_PWRMGT_OFF, 0);
 992         return 0;
 993 }
 994
 995 static int smu7_enable_ulv(struct pp_hwmgr *hwmgr)
 996 {
 997         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 998
 999         if (data->ulv_supported)
1000                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV, NULL);
1001
1002         return 0;
1003 }
1004
1005 static int smu7_disable_ulv(struct pp_hwmgr *hwmgr)
1006 {
1007         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1008
1009         if (data->ulv_supported)
1010                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV, NULL);
1011
1012         return 0;
1013 }
1014
1015 static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
1016 {
1017         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1018                         PHM_PlatformCaps_SclkDeepSleep)) {
1019                 if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON, NULL))
1020                         PP_ASSERT_WITH_CODE(false,
1021                                         "Attempt to enable Master Deep Sleep switch failed!",
1022                                         return -EINVAL);
1023         } else {
1024                 if (smum_send_msg_to_smc(hwmgr,
1025                                 PPSMC_MSG_MASTER_DeepSleep_OFF,
1026                                 NULL)) {
1027                         PP_ASSERT_WITH_CODE(false,
1028                                         "Attempt to disable Master Deep Sleep switch failed!",
1029                                         return -EINVAL);
1030                 }
1031         }
1032
1033         return 0;
1034 }
1035
1036 static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
1037 {
1038         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1039                         PHM_PlatformCaps_SclkDeepSleep)) {
1040                 if (smum_send_msg_to_smc(hwmgr,
1041                                 PPSMC_MSG_MASTER_DeepSleep_OFF,
1042                                 NULL)) {
1043                         PP_ASSERT_WITH_CODE(false,
1044                                         "Attempt to disable Master Deep Sleep switch failed!",
1045                                         return -EINVAL);
1046                 }
1047         }
1048
1049         return 0;
1050 }
1051
1052 static int smu7_disable_sclk_vce_handshake(struct pp_hwmgr *hwmgr)
1053 {
1054         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1055         uint32_t soft_register_value = 0;
1056         uint32_t handshake_disables_offset = data->soft_regs_start
1057                                 + smum_get_offsetof(hwmgr,
1058                                         SMU_SoftRegisters, HandshakeDisables);
1059
1060         soft_register_value = cgs_read_ind_register(hwmgr->device,
1061                                 CGS_IND_REG__SMC, handshake_disables_offset);
1062         soft_register_value |= SMU7_VCE_SCLK_HANDSHAKE_DISABLE;
1063         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1064                         handshake_disables_offset, soft_register_value);
1065         return 0;
1066 }
1067
1068 static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr)
1069 {
1070         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1071         uint32_t soft_register_value = 0;
1072         uint32_t handshake_disables_offset = data->soft_regs_start
1073                                 + smum_get_offsetof(hwmgr,
1074                                         SMU_SoftRegisters, HandshakeDisables);
1075
1076         soft_register_value = cgs_read_ind_register(hwmgr->device,
1077                                 CGS_IND_REG__SMC, handshake_disables_offset);
1078         soft_register_value |= smum_get_mac_definition(hwmgr,
1079                                         SMU_UVD_MCLK_HANDSHAKE_DISABLE);
1080         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1081                         handshake_disables_offset, soft_register_value);
1082         return 0;
1083 }
1084
1085 static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1086 {
1087         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1088
1089         /* enable SCLK dpm */
1090         if (!data->sclk_dpm_key_disabled) {
1091                 if (hwmgr->chip_id == CHIP_VEGAM)
1092                         smu7_disable_sclk_vce_handshake(hwmgr);
1093
1094                 PP_ASSERT_WITH_CODE(
1095                 (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable, NULL)),
1096                 "Failed to enable SCLK DPM during DPM Start Function!",
1097                 return -EINVAL);
1098         }
1099
1100         /* enable MCLK dpm */
1101         if (0 == data->mclk_dpm_key_disabled) {
1102                 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK))
1103                         smu7_disable_handshake_uvd(hwmgr);
1104
1105                 PP_ASSERT_WITH_CODE(
1106                                 (0 == smum_send_msg_to_smc(hwmgr,
1107                                                 PPSMC_MSG_MCLKDPM_Enable,
1108                                                 NULL)),
1109                                 "Failed to enable MCLK DPM during DPM Start Function!",
1110                                 return -EINVAL);
1111
1112                 if (hwmgr->chip_family != CHIP_VEGAM)
1113                         PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
1114
1115
1116                 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
1117                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5);
1118                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5);
1119                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005);
1120                         udelay(10);
1121                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005);
1122                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005);
1123                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005);
1124                 } else {
1125                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
1126                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
1127                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
1128                         udelay(10);
1129                         if (hwmgr->chip_id == CHIP_VEGAM) {
1130                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400009);
1131                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400009);
1132                         } else {
1133                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
1134                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
1135                         }
1136                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
1137                 }
1138         }
1139
1140         return 0;
1141 }
1142
1143 static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
1144 {
1145         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1146
1147         /*enable general power management */
1148
1149         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1150                         GLOBAL_PWRMGT_EN, 1);
1151
1152         /* enable sclk deep sleep */
1153
1154         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1155                         DYNAMIC_PM_EN, 1);
1156
1157         /* prepare for PCIE DPM */
1158
1159         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1160                         data->soft_regs_start +
1161                         smum_get_offsetof(hwmgr, SMU_SoftRegisters,
1162                                                 VoltageChangeTimeout), 0x1000);
1163         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
1164                         SWRST_COMMAND_1, RESETLC, 0x0);
1165
1166         if (hwmgr->chip_family == AMDGPU_FAMILY_CI)
1167                 cgs_write_register(hwmgr->device, 0x1488,
1168                         (cgs_read_register(hwmgr->device, 0x1488) & ~0x1));
1169
1170         if (smu7_enable_sclk_mclk_dpm(hwmgr)) {
1171                 pr_err("Failed to enable Sclk DPM and Mclk DPM!");
1172                 return -EINVAL;
1173         }
1174
1175         /* enable PCIE dpm */
1176         if (0 == data->pcie_dpm_key_disabled) {
1177                 PP_ASSERT_WITH_CODE(
1178                                 (0 == smum_send_msg_to_smc(hwmgr,
1179                                                 PPSMC_MSG_PCIeDPM_Enable,
1180                                                 NULL)),
1181                                 "Failed to enable pcie DPM during DPM Start Function!",
1182                                 return -EINVAL);
1183         }
1184
1185         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1186                                 PHM_PlatformCaps_Falcon_QuickTransition)) {
1187                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr,
1188                                 PPSMC_MSG_EnableACDCGPIOInterrupt,
1189                                 NULL)),
1190                                 "Failed to enable AC DC GPIO Interrupt!",
1191                                 );
1192         }
1193
1194         return 0;
1195 }
1196
1197 static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1198 {
1199         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1200
1201         /* disable SCLK dpm */
1202         if (!data->sclk_dpm_key_disabled) {
1203                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1204                                 "Trying to disable SCLK DPM when DPM is disabled",
1205                                 return 0);
1206                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable, NULL);
1207         }
1208
1209         /* disable MCLK dpm */
1210         if (!data->mclk_dpm_key_disabled) {
1211                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1212                                 "Trying to disable MCLK DPM when DPM is disabled",
1213                                 return 0);
1214                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable, NULL);
1215         }
1216
1217         return 0;
1218 }
1219
1220 static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
1221 {
1222         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1223
1224         /* disable general power management */
1225         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1226                         GLOBAL_PWRMGT_EN, 0);
1227         /* disable sclk deep sleep */
1228         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1229                         DYNAMIC_PM_EN, 0);
1230
1231         /* disable PCIE dpm */
1232         if (!data->pcie_dpm_key_disabled) {
1233                 PP_ASSERT_WITH_CODE(
1234                                 (smum_send_msg_to_smc(hwmgr,
1235                                                 PPSMC_MSG_PCIeDPM_Disable,
1236                                                 NULL) == 0),
1237                                 "Failed to disable pcie DPM during DPM Stop Function!",
1238                                 return -EINVAL);
1239         }
1240
1241         smu7_disable_sclk_mclk_dpm(hwmgr);
1242
1243         PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1244                         "Trying to disable voltage DPM when DPM is disabled",
1245                         return 0);
1246
1247         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable, NULL);
1248
1249         return 0;
1250 }
1251
1252 static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
1253 {
1254         bool protection;
1255         enum DPM_EVENT_SRC src;
1256
1257         switch (sources) {
1258         default:
1259                 pr_err("Unknown throttling event sources.");
1260                 fallthrough;
1261         case 0:
1262                 protection = false;
1263                 /* src is unused */
1264                 break;
1265         case (1 << PHM_AutoThrottleSource_Thermal):
1266                 protection = true;
1267                 src = DPM_EVENT_SRC_DIGITAL;
1268                 break;
1269         case (1 << PHM_AutoThrottleSource_External):
1270                 protection = true;
1271                 src = DPM_EVENT_SRC_EXTERNAL;
1272                 break;
1273         case (1 << PHM_AutoThrottleSource_External) |
1274                         (1 << PHM_AutoThrottleSource_Thermal):
1275                 protection = true;
1276                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
1277                 break;
1278         }
1279         /* Order matters - don't enable thermal protection for the wrong source. */
1280         if (protection) {
1281                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
1282                                 DPM_EVENT_SRC, src);
1283                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1284                                 THERMAL_PROTECTION_DIS,
1285                                 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1286                                                 PHM_PlatformCaps_ThermalController));
1287         } else
1288                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1289                                 THERMAL_PROTECTION_DIS, 1);
1290 }
1291
1292 static int smu7_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1293                 PHM_AutoThrottleSource source)
1294 {
1295         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1296
1297         if (!(data->active_auto_throttle_sources & (1 << source))) {
1298                 data->active_auto_throttle_sources |= 1 << source;
1299                 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1300         }
1301         return 0;
1302 }
1303
1304 static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1305 {
1306         return smu7_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1307 }
1308
1309 static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1310                 PHM_AutoThrottleSource source)
1311 {
1312         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1313
1314         if (data->active_auto_throttle_sources & (1 << source)) {
1315                 data->active_auto_throttle_sources &= ~(1 << source);
1316                 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1317         }
1318         return 0;
1319 }
1320
1321 static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1322 {
1323         return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1324 }
1325
1326 static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
1327 {
1328         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1329         data->pcie_performance_request = true;
1330
1331         return 0;
1332 }
1333
1334 static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1335 {
1336         int tmp_result = 0;
1337         int result = 0;
1338
1339         if (smu7_voltage_control(hwmgr)) {
1340                 tmp_result = smu7_enable_voltage_control(hwmgr);
1341                 PP_ASSERT_WITH_CODE(tmp_result == 0,
1342                                 "Failed to enable voltage control!",
1343                                 result = tmp_result);
1344
1345                 tmp_result = smu7_construct_voltage_tables(hwmgr);
1346                 PP_ASSERT_WITH_CODE((0 == tmp_result),
1347                                 "Failed to construct voltage tables!",
1348                                 result = tmp_result);
1349         }
1350         smum_initialize_mc_reg_table(hwmgr);
1351
1352         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1353                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
1354                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1355                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
1356
1357         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1358                         PHM_PlatformCaps_ThermalController))
1359                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1360                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
1361
1362         tmp_result = smu7_program_static_screen_threshold_parameters(hwmgr);
1363         PP_ASSERT_WITH_CODE((0 == tmp_result),
1364                         "Failed to program static screen threshold parameters!",
1365                         result = tmp_result);
1366
1367         tmp_result = smu7_enable_display_gap(hwmgr);
1368         PP_ASSERT_WITH_CODE((0 == tmp_result),
1369                         "Failed to enable display gap!", result = tmp_result);
1370
1371         tmp_result = smu7_program_voting_clients(hwmgr);
1372         PP_ASSERT_WITH_CODE((0 == tmp_result),
1373                         "Failed to program voting clients!", result = tmp_result);
1374
1375         tmp_result = smum_process_firmware_header(hwmgr);
1376         PP_ASSERT_WITH_CODE((0 == tmp_result),
1377                         "Failed to process firmware header!", result = tmp_result);
1378
1379         if (hwmgr->chip_id != CHIP_VEGAM) {
1380                 tmp_result = smu7_initial_switch_from_arbf0_to_f1(hwmgr);
1381                 PP_ASSERT_WITH_CODE((0 == tmp_result),
1382                                 "Failed to initialize switch from ArbF0 to F1!",
1383                                 result = tmp_result);
1384         }
1385
1386         result = smu7_setup_default_dpm_tables(hwmgr);
1387         PP_ASSERT_WITH_CODE(0 == result,
1388                         "Failed to setup default DPM tables!", return result);
1389
1390         tmp_result = smum_init_smc_table(hwmgr);
1391         PP_ASSERT_WITH_CODE((0 == tmp_result),
1392                         "Failed to initialize SMC table!", result = tmp_result);
1393
1394         tmp_result = smu7_enable_vrhot_gpio_interrupt(hwmgr);
1395         PP_ASSERT_WITH_CODE((0 == tmp_result),
1396                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
1397
1398         smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay, NULL);
1399
1400         tmp_result = smu7_enable_sclk_control(hwmgr);
1401         PP_ASSERT_WITH_CODE((0 == tmp_result),
1402                         "Failed to enable SCLK control!", result = tmp_result);
1403
1404         tmp_result = smu7_enable_smc_voltage_controller(hwmgr);
1405         PP_ASSERT_WITH_CODE((0 == tmp_result),
1406                         "Failed to enable voltage control!", result = tmp_result);
1407
1408         tmp_result = smu7_enable_ulv(hwmgr);
1409         PP_ASSERT_WITH_CODE((0 == tmp_result),
1410                         "Failed to enable ULV!", result = tmp_result);
1411
1412         tmp_result = smu7_enable_deep_sleep_master_switch(hwmgr);
1413         PP_ASSERT_WITH_CODE((0 == tmp_result),
1414                         "Failed to enable deep sleep master switch!", result = tmp_result);
1415
1416         tmp_result = smu7_enable_didt_config(hwmgr);
1417         PP_ASSERT_WITH_CODE((tmp_result == 0),
1418                         "Failed to enable deep sleep master switch!", result = tmp_result);
1419
1420         tmp_result = smu7_start_dpm(hwmgr);
1421         PP_ASSERT_WITH_CODE((0 == tmp_result),
1422                         "Failed to start DPM!", result = tmp_result);
1423
1424         tmp_result = smu7_enable_smc_cac(hwmgr);
1425         PP_ASSERT_WITH_CODE((0 == tmp_result),
1426                         "Failed to enable SMC CAC!", result = tmp_result);
1427
1428         tmp_result = smu7_enable_power_containment(hwmgr);
1429         PP_ASSERT_WITH_CODE((0 == tmp_result),
1430                         "Failed to enable power containment!", result = tmp_result);
1431
1432         tmp_result = smu7_power_control_set_level(hwmgr);
1433         PP_ASSERT_WITH_CODE((0 == tmp_result),
1434                         "Failed to power control set level!", result = tmp_result);
1435
1436         tmp_result = smu7_enable_thermal_auto_throttle(hwmgr);
1437         PP_ASSERT_WITH_CODE((0 == tmp_result),
1438                         "Failed to enable thermal auto throttle!", result = tmp_result);
1439
1440         tmp_result = smu7_pcie_performance_request(hwmgr);
1441         PP_ASSERT_WITH_CODE((0 == tmp_result),
1442                         "pcie performance request failed!", result = tmp_result);
1443
1444         return 0;
1445 }
1446
1447 static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
1448 {
1449         if (!hwmgr->avfs_supported)
1450                 return 0;
1451
1452         if (enable) {
1453                 if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
1454                                 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
1455                         PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
1456                                         hwmgr, PPSMC_MSG_EnableAvfs, NULL),
1457                                         "Failed to enable AVFS!",
1458                                         return -EINVAL);
1459                 }
1460         } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
1461                         CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
1462                 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
1463                                 hwmgr, PPSMC_MSG_DisableAvfs, NULL),
1464                                 "Failed to disable AVFS!",
1465                                 return -EINVAL);
1466         }
1467
1468         return 0;
1469 }
1470
1471 static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
1472 {
1473         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1474
1475         if (!hwmgr->avfs_supported)
1476                 return 0;
1477
1478         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
1479                 smu7_avfs_control(hwmgr, false);
1480         } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
1481                 smu7_avfs_control(hwmgr, false);
1482                 smu7_avfs_control(hwmgr, true);
1483         } else {
1484                 smu7_avfs_control(hwmgr, true);
1485         }
1486
1487         return 0;
1488 }
1489
1490 static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
1491 {
1492         int tmp_result, result = 0;
1493
1494         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1495                         PHM_PlatformCaps_ThermalController))
1496                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1497                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
1498
1499         tmp_result = smu7_disable_power_containment(hwmgr);
1500         PP_ASSERT_WITH_CODE((tmp_result == 0),
1501                         "Failed to disable power containment!", result = tmp_result);
1502
1503         tmp_result = smu7_disable_smc_cac(hwmgr);
1504         PP_ASSERT_WITH_CODE((tmp_result == 0),
1505                         "Failed to disable SMC CAC!", result = tmp_result);
1506
1507         tmp_result = smu7_disable_didt_config(hwmgr);
1508         PP_ASSERT_WITH_CODE((tmp_result == 0),
1509                         "Failed to disable DIDT!", result = tmp_result);
1510
1511         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1512                         CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
1513         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1514                         GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
1515
1516         tmp_result = smu7_disable_thermal_auto_throttle(hwmgr);
1517         PP_ASSERT_WITH_CODE((tmp_result == 0),
1518                         "Failed to disable thermal auto throttle!", result = tmp_result);
1519
1520         tmp_result = smu7_avfs_control(hwmgr, false);
1521         PP_ASSERT_WITH_CODE((tmp_result == 0),
1522                         "Failed to disable AVFS!", result = tmp_result);
1523
1524         tmp_result = smu7_stop_dpm(hwmgr);
1525         PP_ASSERT_WITH_CODE((tmp_result == 0),
1526                         "Failed to stop DPM!", result = tmp_result);
1527
1528         tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr);
1529         PP_ASSERT_WITH_CODE((tmp_result == 0),
1530                         "Failed to disable deep sleep master switch!", result = tmp_result);
1531
1532         tmp_result = smu7_disable_ulv(hwmgr);
1533         PP_ASSERT_WITH_CODE((tmp_result == 0),
1534                         "Failed to disable ULV!", result = tmp_result);
1535
1536         tmp_result = smu7_clear_voting_clients(hwmgr);
1537         PP_ASSERT_WITH_CODE((tmp_result == 0),
1538                         "Failed to clear voting clients!", result = tmp_result);
1539
1540         tmp_result = smu7_reset_to_default(hwmgr);
1541         PP_ASSERT_WITH_CODE((tmp_result == 0),
1542                         "Failed to reset to default!", result = tmp_result);
1543
1544         tmp_result = smu7_force_switch_to_arbf0(hwmgr);
1545         PP_ASSERT_WITH_CODE((tmp_result == 0),
1546                         "Failed to force to switch arbf0!", result = tmp_result);
1547
1548         return result;
1549 }
1550
1551 int smu7_reset_asic_tasks(struct pp_hwmgr *hwmgr)
1552 {
1553
1554         return 0;
1555 }
1556
1557 static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
1558 {
1559         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1560         struct phm_ppt_v1_information *table_info =
1561                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1562         struct amdgpu_device *adev = hwmgr->adev;
1563
1564         data->dll_default_on = false;
1565         data->mclk_dpm0_activity_target = 0xa;
1566         data->vddc_vddgfx_delta = 300;
1567         data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT;
1568         data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT;
1569         data->voting_rights_clients[0] = SMU7_VOTINGRIGHTSCLIENTS_DFLT0;
1570         data->voting_rights_clients[1]= SMU7_VOTINGRIGHTSCLIENTS_DFLT1;
1571         data->voting_rights_clients[2] = SMU7_VOTINGRIGHTSCLIENTS_DFLT2;
1572         data->voting_rights_clients[3]= SMU7_VOTINGRIGHTSCLIENTS_DFLT3;
1573         data->voting_rights_clients[4]= SMU7_VOTINGRIGHTSCLIENTS_DFLT4;
1574         data->voting_rights_clients[5]= SMU7_VOTINGRIGHTSCLIENTS_DFLT5;
1575         data->voting_rights_clients[6]= SMU7_VOTINGRIGHTSCLIENTS_DFLT6;
1576         data->voting_rights_clients[7]= SMU7_VOTINGRIGHTSCLIENTS_DFLT7;
1577
1578         data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
1579         data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
1580         data->pcie_dpm_key_disabled = hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
1581         /* need to set voltage control types before EVV patching */
1582         data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;
1583         data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;
1584         data->mvdd_control = SMU7_VOLTAGE_CONTROL_NONE;
1585         data->enable_tdc_limit_feature = true;
1586         data->enable_pkg_pwr_tracking_feature = true;
1587         data->force_pcie_gen = PP_PCIEGenInvalid;
1588         data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
1589         data->current_profile_setting.bupdate_sclk = 1;
1590         data->current_profile_setting.sclk_up_hyst = 0;
1591         data->current_profile_setting.sclk_down_hyst = 100;
1592         data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT;
1593         data->current_profile_setting.bupdate_mclk = 1;
1594         data->current_profile_setting.mclk_up_hyst = 0;
1595         data->current_profile_setting.mclk_down_hyst = 100;
1596         data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT;
1597         hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
1598         hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1599         hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1600
1601         if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) {
1602                 uint8_t tmp1, tmp2;
1603                 uint16_t tmp3 = 0;
1604                 atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2,
1605                                                 &tmp3);
1606                 tmp3 = (tmp3 >> 5) & 0x3;
1607                 data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3;
1608         } else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
1609                 data->vddc_phase_shed_control = 1;
1610         } else {
1611                 data->vddc_phase_shed_control = 0;
1612         }
1613
1614         if (hwmgr->chip_id  == CHIP_HAWAII) {
1615                 data->thermal_temp_setting.temperature_low = 94500;
1616                 data->thermal_temp_setting.temperature_high = 95000;
1617                 data->thermal_temp_setting.temperature_shutdown = 104000;
1618         } else {
1619                 data->thermal_temp_setting.temperature_low = 99500;
1620                 data->thermal_temp_setting.temperature_high = 100000;
1621                 data->thermal_temp_setting.temperature_shutdown = 104000;
1622         }
1623
1624         data->fast_watermark_threshold = 100;
1625         if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1626                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
1627                 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1628         else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1629                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
1630                 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1631
1632         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1633                         PHM_PlatformCaps_ControlVDDGFX)) {
1634                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1635                         VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
1636                         data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1637                 }
1638         }
1639
1640         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1641                         PHM_PlatformCaps_EnableMVDDControl)) {
1642                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1643                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
1644                         data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1645                 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1646                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
1647                         data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1648         }
1649
1650         if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control)
1651                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1652                         PHM_PlatformCaps_ControlVDDGFX);
1653
1654         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1655                         PHM_PlatformCaps_ControlVDDCI)) {
1656                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1657                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
1658                         data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1659                 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1660                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
1661                         data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1662         }
1663
1664         if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE)
1665                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1666                                 PHM_PlatformCaps_EnableMVDDControl);
1667
1668         if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE)
1669                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1670                                 PHM_PlatformCaps_ControlVDDCI);
1671
1672         if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK)
1673                 && (table_info->cac_dtp_table->usClockStretchAmount != 0))
1674                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1675                                         PHM_PlatformCaps_ClockStretcher);
1676
1677         data->pcie_gen_performance.max = PP_PCIEGen1;
1678         data->pcie_gen_performance.min = PP_PCIEGen3;
1679         data->pcie_gen_power_saving.max = PP_PCIEGen1;
1680         data->pcie_gen_power_saving.min = PP_PCIEGen3;
1681         data->pcie_lane_performance.max = 0;
1682         data->pcie_lane_performance.min = 16;
1683         data->pcie_lane_power_saving.max = 0;
1684         data->pcie_lane_power_saving.min = 16;
1685
1686
1687         if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1688                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1689                               PHM_PlatformCaps_UVDPowerGating);
1690         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
1691                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1692                               PHM_PlatformCaps_VCEPowerGating);
1693 }
1694
1695 /**
1696 * Get Leakage VDDC based on leakage ID.
1697 *
1698 * @param    hwmgr  the address of the powerplay hardware manager.
1699 * @return   always 0
1700 */
1701 static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
1702 {
1703         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1704         uint16_t vv_id;
1705         uint16_t vddc = 0;
1706         uint16_t vddgfx = 0;
1707         uint16_t i, j;
1708         uint32_t sclk = 0;
1709         struct phm_ppt_v1_information *table_info =
1710                         (struct phm_ppt_v1_information *)hwmgr->pptable;
1711         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL;
1712
1713
1714         for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
1715                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1716
1717                 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1718                         if ((hwmgr->pp_table_version == PP_TABLE_V1)
1719                             && !phm_get_sclk_for_voltage_evv(hwmgr,
1720                                                 table_info->vddgfx_lookup_table, vv_id, &sclk)) {
1721                                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1722                                                         PHM_PlatformCaps_ClockStretcher)) {
1723                                         sclk_table = table_info->vdd_dep_on_sclk;
1724
1725                                         for (j = 1; j < sclk_table->count; j++) {
1726                                                 if (sclk_table->entries[j].clk == sclk &&
1727                                                                 sclk_table->entries[j].cks_enable == 0) {
1728                                                         sclk += 5000;
1729                                                         break;
1730                                                 }
1731                                         }
1732                                 }
1733                                 if (0 == atomctrl_get_voltage_evv_on_sclk
1734                                     (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
1735                                      vv_id, &vddgfx)) {
1736                                         /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
1737                                         PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -EINVAL);
1738
1739                                         /* the voltage should not be zero nor equal to leakage ID */
1740                                         if (vddgfx != 0 && vddgfx != vv_id) {
1741                                                 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
1742                                                 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = vv_id;
1743                                                 data->vddcgfx_leakage.count++;
1744                                         }
1745                                 } else {
1746                                         pr_info("Error retrieving EVV voltage value!\n");
1747                                 }
1748                         }
1749                 } else {
1750                         if ((hwmgr->pp_table_version == PP_TABLE_V0)
1751                                 || !phm_get_sclk_for_voltage_evv(hwmgr,
1752                                         table_info->vddc_lookup_table, vv_id, &sclk)) {
1753                                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1754                                                 PHM_PlatformCaps_ClockStretcher)) {
1755                                         if (table_info == NULL)
1756                                                 return -EINVAL;
1757                                         sclk_table = table_info->vdd_dep_on_sclk;
1758
1759                                         for (j = 1; j < sclk_table->count; j++) {
1760                                                 if (sclk_table->entries[j].clk == sclk &&
1761                                                                 sclk_table->entries[j].cks_enable == 0) {
1762                                                         sclk += 5000;
1763                                                         break;
1764                                                 }
1765                                         }
1766                                 }
1767
1768                                 if (phm_get_voltage_evv_on_sclk(hwmgr,
1769                                                         VOLTAGE_TYPE_VDDC,
1770                                                         sclk, vv_id, &vddc) == 0) {
1771                                         if (vddc >= 2000 || vddc == 0)
1772                                                 return -EINVAL;
1773                                 } else {
1774                                         pr_debug("failed to retrieving EVV voltage!\n");
1775                                         continue;
1776                                 }
1777
1778                                 /* the voltage should not be zero nor equal to leakage ID */
1779                                 if (vddc != 0 && vddc != vv_id) {
1780                                         data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc);
1781                                         data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
1782                                         data->vddc_leakage.count++;
1783                                 }
1784                         }
1785                 }
1786         }
1787
1788         return 0;
1789 }
1790
1791 /**
1792  * Change virtual leakage voltage to actual value.
1793  *
1794  * @param     hwmgr  the address of the powerplay hardware manager.
1795  * @param     pointer to changing voltage
1796  * @param     pointer to leakage table
1797  */
1798 static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr,
1799                 uint16_t *voltage, struct smu7_leakage_voltage *leakage_table)
1800 {
1801         uint32_t index;
1802
1803         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
1804         for (index = 0; index < leakage_table->count; index++) {
1805                 /* if this voltage matches a leakage voltage ID */
1806                 /* patch with actual leakage voltage */
1807                 if (leakage_table->leakage_id[index] == *voltage) {
1808                         *voltage = leakage_table->actual_voltage[index];
1809                         break;
1810                 }
1811         }
1812
1813         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
1814                 pr_err("Voltage value looks like a Leakage ID but it's not patched \n");
1815 }
1816
1817 /**
1818 * Patch voltage lookup table by EVV leakages.
1819 *
1820 * @param     hwmgr  the address of the powerplay hardware manager.
1821 * @param     pointer to voltage lookup table
1822 * @param     pointer to leakage table
1823 * @return     always 0
1824 */
1825 static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
1826                 phm_ppt_v1_voltage_lookup_table *lookup_table,
1827                 struct smu7_leakage_voltage *leakage_table)
1828 {
1829         uint32_t i;
1830
1831         for (i = 0; i < lookup_table->count; i++)
1832                 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
1833                                 &lookup_table->entries[i].us_vdd, leakage_table);
1834
1835         return 0;
1836 }
1837
1838 static int smu7_patch_clock_voltage_limits_with_vddc_leakage(
1839                 struct pp_hwmgr *hwmgr, struct smu7_leakage_voltage *leakage_table,
1840                 uint16_t *vddc)
1841 {
1842         struct phm_ppt_v1_information *table_info =
1843                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1844         smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
1845         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
1846                         table_info->max_clock_voltage_on_dc.vddc;
1847         return 0;
1848 }
1849
1850 static int smu7_patch_voltage_dependency_tables_with_lookup_table(
1851                 struct pp_hwmgr *hwmgr)
1852 {
1853         uint8_t entry_id;
1854         uint8_t voltage_id;
1855         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1856         struct phm_ppt_v1_information *table_info =
1857                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1858
1859         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1860                         table_info->vdd_dep_on_sclk;
1861         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
1862                         table_info->vdd_dep_on_mclk;
1863         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1864                         table_info->mm_dep_table;
1865
1866         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1867                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1868                         voltage_id = sclk_table->entries[entry_id].vddInd;
1869                         sclk_table->entries[entry_id].vddgfx =
1870                                 table_info->vddgfx_lookup_table->entries[voltage_id].us_vdd;
1871                 }
1872         } else {
1873                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1874                         voltage_id = sclk_table->entries[entry_id].vddInd;
1875                         sclk_table->entries[entry_id].vddc =
1876                                 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1877                 }
1878         }
1879
1880         for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
1881                 voltage_id = mclk_table->entries[entry_id].vddInd;
1882                 mclk_table->entries[entry_id].vddc =
1883                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1884         }
1885
1886         for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
1887                 voltage_id = mm_table->entries[entry_id].vddcInd;
1888                 mm_table->entries[entry_id].vddc =
1889                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1890         }
1891
1892         return 0;
1893
1894 }
1895
1896 static int phm_add_voltage(struct pp_hwmgr *hwmgr,
1897                         phm_ppt_v1_voltage_lookup_table *look_up_table,
1898                         phm_ppt_v1_voltage_lookup_record *record)
1899 {
1900         uint32_t i;
1901
1902         PP_ASSERT_WITH_CODE((NULL != look_up_table),
1903                 "Lookup Table empty.", return -EINVAL);
1904         PP_ASSERT_WITH_CODE((0 != look_up_table->count),
1905                 "Lookup Table empty.", return -EINVAL);
1906
1907         i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
1908         PP_ASSERT_WITH_CODE((i >= look_up_table->count),
1909                 "Lookup Table is full.", return -EINVAL);
1910
1911         /* This is to avoid entering duplicate calculated records. */
1912         for (i = 0; i < look_up_table->count; i++) {
1913                 if (look_up_table->entries[i].us_vdd == record->us_vdd) {
1914                         if (look_up_table->entries[i].us_calculated == 1)
1915                                 return 0;
1916                         break;
1917                 }
1918         }
1919
1920         look_up_table->entries[i].us_calculated = 1;
1921         look_up_table->entries[i].us_vdd = record->us_vdd;
1922         look_up_table->entries[i].us_cac_low = record->us_cac_low;
1923         look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
1924         look_up_table->entries[i].us_cac_high = record->us_cac_high;
1925         /* Only increment the count when we're appending, not replacing duplicate entry. */
1926         if (i == look_up_table->count)
1927                 look_up_table->count++;
1928
1929         return 0;
1930 }
1931
1932
1933 static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
1934 {
1935         uint8_t entry_id;
1936         struct phm_ppt_v1_voltage_lookup_record v_record;
1937         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1938         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1939
1940         phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
1941         phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
1942
1943         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1944                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1945                         if (sclk_table->entries[entry_id].vdd_offset & (1 << 15))
1946                                 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
1947                                         sclk_table->entries[entry_id].vdd_offset - 0xFFFF;
1948                         else
1949                                 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
1950                                         sclk_table->entries[entry_id].vdd_offset;
1951
1952                         sclk_table->entries[entry_id].vddc =
1953                                 v_record.us_cac_low = v_record.us_cac_mid =
1954                                 v_record.us_cac_high = v_record.us_vdd;
1955
1956                         phm_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record);
1957                 }
1958
1959                 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
1960                         if (mclk_table->entries[entry_id].vdd_offset & (1 << 15))
1961                                 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
1962                                         mclk_table->entries[entry_id].vdd_offset - 0xFFFF;
1963                         else
1964                                 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
1965                                         mclk_table->entries[entry_id].vdd_offset;
1966
1967                         mclk_table->entries[entry_id].vddgfx = v_record.us_cac_low =
1968                                 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
1969                         phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
1970                 }
1971         }
1972         return 0;
1973 }
1974
1975 static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
1976 {
1977         uint8_t entry_id;
1978         struct phm_ppt_v1_voltage_lookup_record v_record;
1979         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1980         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1981         phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1982
1983         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1984                 for (entry_id = 0; entry_id < mm_table->count; entry_id++) {
1985                         if (mm_table->entries[entry_id].vddgfx_offset & (1 << 15))
1986                                 v_record.us_vdd = mm_table->entries[entry_id].vddc +
1987                                         mm_table->entries[entry_id].vddgfx_offset - 0xFFFF;
1988                         else
1989                                 v_record.us_vdd = mm_table->entries[entry_id].vddc +
1990                                         mm_table->entries[entry_id].vddgfx_offset;
1991
1992                         /* Add the calculated VDDGFX to the VDDGFX lookup table */
1993                         mm_table->entries[entry_id].vddgfx = v_record.us_cac_low =
1994                                 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
1995                         phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
1996                 }
1997         }
1998         return 0;
1999 }
2000
2001 static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr,
2002                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
2003 {
2004         uint32_t table_size, i, j;
2005         table_size = lookup_table->count;
2006
2007         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2008                 "Lookup table is empty", return -EINVAL);
2009
2010         /* Sorting voltages */
2011         for (i = 0; i < table_size - 1; i++) {
2012                 for (j = i + 1; j > 0; j--) {
2013                         if (lookup_table->entries[j].us_vdd <
2014                                         lookup_table->entries[j - 1].us_vdd) {
2015                                 swap(lookup_table->entries[j - 1],
2016                                      lookup_table->entries[j]);
2017                         }
2018                 }
2019         }
2020
2021         return 0;
2022 }
2023
2024 static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr)
2025 {
2026         int result = 0;
2027         int tmp_result;
2028         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2029         struct phm_ppt_v1_information *table_info =
2030                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2031
2032         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2033                 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
2034                         table_info->vddgfx_lookup_table, &(data->vddcgfx_leakage));
2035                 if (tmp_result != 0)
2036                         result = tmp_result;
2037
2038                 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
2039                         &table_info->max_clock_voltage_on_dc.vddgfx, &(data->vddcgfx_leakage));
2040         } else {
2041
2042                 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
2043                                 table_info->vddc_lookup_table, &(data->vddc_leakage));
2044                 if (tmp_result)
2045                         result = tmp_result;
2046
2047                 tmp_result = smu7_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
2048                                 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2049                 if (tmp_result)
2050                         result = tmp_result;
2051         }
2052
2053         tmp_result = smu7_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
2054         if (tmp_result)
2055                 result = tmp_result;
2056
2057         tmp_result = smu7_calc_voltage_dependency_tables(hwmgr);
2058         if (tmp_result)
2059                 result = tmp_result;
2060
2061         tmp_result = smu7_calc_mm_voltage_dependency_table(hwmgr);
2062         if (tmp_result)
2063                 result = tmp_result;
2064
2065         tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddgfx_lookup_table);
2066         if (tmp_result)
2067                 result = tmp_result;
2068
2069         tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
2070         if (tmp_result)
2071                 result = tmp_result;
2072
2073         return result;
2074 }
2075
2076 static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr)
2077 {
2078         struct phm_ppt_v1_information *table_info =
2079                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2080
2081         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2082                                                 table_info->vdd_dep_on_sclk;
2083         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2084                                                 table_info->vdd_dep_on_mclk;
2085
2086         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2087                 "VDD dependency on SCLK table is missing.",
2088                 return -EINVAL);
2089         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2090                 "VDD dependency on SCLK table has to have is missing.",
2091                 return -EINVAL);
2092
2093         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2094                 "VDD dependency on MCLK table is missing",
2095                 return -EINVAL);
2096         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2097                 "VDD dependency on MCLK table has to have is missing.",
2098                 return -EINVAL);
2099
2100         table_info->max_clock_voltage_on_ac.sclk =
2101                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2102         table_info->max_clock_voltage_on_ac.mclk =
2103                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2104         table_info->max_clock_voltage_on_ac.vddc =
2105                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2106         table_info->max_clock_voltage_on_ac.vddci =
2107                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2108
2109         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2110         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2111         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2112         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = table_info->max_clock_voltage_on_ac.vddci;
2113
2114         return 0;
2115 }
2116
2117 static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
2118 {
2119         struct phm_ppt_v1_information *table_info =
2120                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
2121         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
2122         struct phm_ppt_v1_voltage_lookup_table *lookup_table;
2123         uint32_t i;
2124         uint32_t hw_revision, sub_vendor_id, sub_sys_id;
2125         struct amdgpu_device *adev = hwmgr->adev;
2126
2127         if (table_info != NULL) {
2128                 dep_mclk_table = table_info->vdd_dep_on_mclk;
2129                 lookup_table = table_info->vddc_lookup_table;
2130         } else
2131                 return 0;
2132
2133         hw_revision = adev->pdev->revision;
2134         sub_sys_id = adev->pdev->subsystem_device;
2135         sub_vendor_id = adev->pdev->subsystem_vendor;
2136
2137         if (hwmgr->chip_id == CHIP_POLARIS10 && hw_revision == 0xC7 &&
2138                         ((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) ||
2139                     (sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) ||
2140                     (sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) {
2141                 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
2142                         return 0;
2143
2144                 for (i = 0; i < lookup_table->count; i++) {
2145                         if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) {
2146                                 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;
2147                                 return 0;
2148                         }
2149                 }
2150         }
2151         return 0;
2152 }
2153
2154 static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr)
2155 {
2156         struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2157         uint32_t temp_reg;
2158         struct phm_ppt_v1_information *table_info =
2159                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2160
2161
2162         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
2163                 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
2164                 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
2165                 case 0:
2166                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
2167                         break;
2168                 case 1:
2169                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
2170                         break;
2171                 case 2:
2172                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
2173                         break;
2174                 case 3:
2175                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
2176                         break;
2177                 case 4:
2178                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
2179                         break;
2180                 default:
2181                         break;
2182                 }
2183                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
2184         }
2185
2186         if (table_info == NULL)
2187                 return 0;
2188
2189         if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
2190                 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
2191                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
2192                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
2193
2194                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
2195                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
2196
2197                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
2198
2199                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
2200
2201                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
2202                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
2203
2204                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
2205
2206                 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
2207                                                                 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp - 50) : 0;
2208
2209                 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2210                 table_info->cac_dtp_table->usOperatingTempStep = 1;
2211                 table_info->cac_dtp_table->usOperatingTempHyst = 1;
2212
2213                 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
2214                                hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
2215
2216                 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
2217                                hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
2218
2219                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
2220                                table_info->cac_dtp_table->usOperatingTempMinLimit;
2221
2222                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
2223                                table_info->cac_dtp_table->usOperatingTempMaxLimit;
2224
2225                 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
2226                                table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2227
2228                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
2229                                table_info->cac_dtp_table->usOperatingTempStep;
2230
2231                 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
2232                                table_info->cac_dtp_table->usTargetOperatingTemp;
2233                 if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK)
2234                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2235                                         PHM_PlatformCaps_ODFuzzyFanControlSupport);
2236         }
2237
2238         return 0;
2239 }
2240
2241 /**
2242  * Change virtual leakage voltage to actual value.
2243  *
2244  * @param     hwmgr  the address of the powerplay hardware manager.
2245  * @param     pointer to changing voltage
2246  * @param     pointer to leakage table
2247  */
2248 static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2249                 uint32_t *voltage, struct smu7_leakage_voltage *leakage_table)
2250 {
2251         uint32_t index;
2252
2253         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2254         for (index = 0; index < leakage_table->count; index++) {
2255                 /* if this voltage matches a leakage voltage ID */
2256                 /* patch with actual leakage voltage */
2257                 if (leakage_table->leakage_id[index] == *voltage) {
2258                         *voltage = leakage_table->actual_voltage[index];
2259                         break;
2260                 }
2261         }
2262
2263         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2264                 pr_err("Voltage value looks like a Leakage ID but it's not patched \n");
2265 }
2266
2267
2268 static int smu7_patch_vddc(struct pp_hwmgr *hwmgr,
2269                               struct phm_clock_voltage_dependency_table *tab)
2270 {
2271         uint16_t i;
2272         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2273
2274         if (tab)
2275                 for (i = 0; i < tab->count; i++)
2276                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2277                                                 &data->vddc_leakage);
2278
2279         return 0;
2280 }
2281
2282 static int smu7_patch_vddci(struct pp_hwmgr *hwmgr,
2283                                struct phm_clock_voltage_dependency_table *tab)
2284 {
2285         uint16_t i;
2286         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2287
2288         if (tab)
2289                 for (i = 0; i < tab->count; i++)
2290                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2291                                                         &data->vddci_leakage);
2292
2293         return 0;
2294 }
2295
2296 static int smu7_patch_vce_vddc(struct pp_hwmgr *hwmgr,
2297                                   struct phm_vce_clock_voltage_dependency_table *tab)
2298 {
2299         uint16_t i;
2300         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2301
2302         if (tab)
2303                 for (i = 0; i < tab->count; i++)
2304                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2305                                                         &data->vddc_leakage);
2306
2307         return 0;
2308 }
2309
2310
2311 static int smu7_patch_uvd_vddc(struct pp_hwmgr *hwmgr,
2312                                   struct phm_uvd_clock_voltage_dependency_table *tab)
2313 {
2314         uint16_t i;
2315         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2316
2317         if (tab)
2318                 for (i = 0; i < tab->count; i++)
2319                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2320                                                         &data->vddc_leakage);
2321
2322         return 0;
2323 }
2324
2325 static int smu7_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr,
2326                                          struct phm_phase_shedding_limits_table *tab)
2327 {
2328         uint16_t i;
2329         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2330
2331         if (tab)
2332                 for (i = 0; i < tab->count; i++)
2333                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].Voltage,
2334                                                         &data->vddc_leakage);
2335
2336         return 0;
2337 }
2338
2339 static int smu7_patch_samu_vddc(struct pp_hwmgr *hwmgr,
2340                                    struct phm_samu_clock_voltage_dependency_table *tab)
2341 {
2342         uint16_t i;
2343         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2344
2345         if (tab)
2346                 for (i = 0; i < tab->count; i++)
2347                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2348                                                         &data->vddc_leakage);
2349
2350         return 0;
2351 }
2352
2353 static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr,
2354                                   struct phm_acp_clock_voltage_dependency_table *tab)
2355 {
2356         uint16_t i;
2357         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2358
2359         if (tab)
2360                 for (i = 0; i < tab->count; i++)
2361                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2362                                         &data->vddc_leakage);
2363
2364         return 0;
2365 }
2366
2367 static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr,
2368                                   struct phm_clock_and_voltage_limits *tab)
2369 {
2370         uint32_t vddc, vddci;
2371         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2372
2373         if (tab) {
2374                 vddc = tab->vddc;
2375                 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc,
2376                                                    &data->vddc_leakage);
2377                 tab->vddc = vddc;
2378                 vddci = tab->vddci;
2379                 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci,
2380                                                    &data->vddci_leakage);
2381                 tab->vddci = vddci;
2382         }
2383
2384         return 0;
2385 }
2386
2387 static int smu7_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab)
2388 {
2389         uint32_t i;
2390         uint32_t vddc;
2391         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2392
2393         if (tab) {
2394                 for (i = 0; i < tab->count; i++) {
2395                         vddc = (uint32_t)(tab->entries[i].Vddc);
2396                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, &data->vddc_leakage);
2397                         tab->entries[i].Vddc = (uint16_t)vddc;
2398                 }
2399         }
2400
2401         return 0;
2402 }
2403
2404 static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr)
2405 {
2406         int tmp;
2407
2408         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk);
2409         if (tmp)
2410                 return -EINVAL;
2411
2412         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk);
2413         if (tmp)
2414                 return -EINVAL;
2415
2416         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2417         if (tmp)
2418                 return -EINVAL;
2419
2420         tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk);
2421         if (tmp)
2422                 return -EINVAL;
2423
2424         tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table);
2425         if (tmp)
2426                 return -EINVAL;
2427
2428         tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
2429         if (tmp)
2430                 return -EINVAL;
2431
2432         tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table);
2433         if (tmp)
2434                 return -EINVAL;
2435
2436         tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table);
2437         if (tmp)
2438                 return -EINVAL;
2439
2440         tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table);
2441         if (tmp)
2442                 return -EINVAL;
2443
2444         tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac);
2445         if (tmp)
2446                 return -EINVAL;
2447
2448         tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc);
2449         if (tmp)
2450                 return -EINVAL;
2451
2452         tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table);
2453         if (tmp)
2454                 return -EINVAL;
2455
2456         return 0;
2457 }
2458
2459
2460 static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
2461 {
2462         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2463
2464         struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
2465         struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
2466         struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
2467
2468         PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL,
2469                 "VDDC dependency on SCLK table is missing. This table is mandatory",
2470                 return -EINVAL);
2471         PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1,
2472                 "VDDC dependency on SCLK table has to have is missing. This table is mandatory",
2473                 return -EINVAL);
2474
2475         PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL,
2476                 "VDDC dependency on MCLK table is missing. This table is mandatory",
2477                 return -EINVAL);
2478         PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1,
2479                 "VDD dependency on MCLK table has to have is missing. This table is mandatory",
2480                 return -EINVAL);
2481
2482         data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v;
2483         data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2484
2485         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
2486                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
2487         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
2488                 allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk;
2489         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
2490                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2491
2492         if (allowed_mclk_vddci_table != NULL && allowed_mclk_vddci_table->count >= 1) {
2493                 data->min_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[0].v;
2494                 data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
2495         }
2496
2497         if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1)
2498                 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v;
2499
2500         return 0;
2501 }
2502
2503 static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2504 {
2505         kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2506         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
2507         kfree(hwmgr->backend);
2508         hwmgr->backend = NULL;
2509
2510         return 0;
2511 }
2512
2513 static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr)
2514 {
2515         uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id;
2516         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2517         int i;
2518
2519         if (atomctrl_get_leakage_id_from_efuse(hwmgr, &efuse_voltage_id) == 0) {
2520                 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
2521                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2522                         if (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, &vddc, &vddci,
2523                                                                 virtual_voltage_id,
2524                                                                 efuse_voltage_id) == 0) {
2525                                 if (vddc != 0 && vddc != virtual_voltage_id) {
2526                                         data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
2527                                         data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
2528                                         data->vddc_leakage.count++;
2529                                 }
2530                                 if (vddci != 0 && vddci != virtual_voltage_id) {
2531                                         data->vddci_leakage.actual_voltage[data->vddci_leakage.count] = vddci;
2532                                         data->vddci_leakage.leakage_id[data->vddci_leakage.count] = virtual_voltage_id;
2533                                         data->vddci_leakage.count++;
2534                                 }
2535                         }
2536                 }
2537         }
2538         return 0;
2539 }
2540
2541 static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2542 {
2543         struct smu7_hwmgr *data;
2544         int result = 0;
2545
2546         data = kzalloc(sizeof(struct smu7_hwmgr), GFP_KERNEL);
2547         if (data == NULL)
2548                 return -ENOMEM;
2549
2550         hwmgr->backend = data;
2551         smu7_patch_voltage_workaround(hwmgr);
2552         smu7_init_dpm_defaults(hwmgr);
2553
2554         /* Get leakage voltage based on leakage ID. */
2555         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2556                         PHM_PlatformCaps_EVV)) {
2557                 result = smu7_get_evv_voltages(hwmgr);
2558                 if (result) {
2559                         pr_info("Get EVV Voltage Failed.  Abort Driver loading!\n");
2560                         return -EINVAL;
2561                 }
2562         } else {
2563                 smu7_get_elb_voltages(hwmgr);
2564         }
2565
2566         if (hwmgr->pp_table_version == PP_TABLE_V1) {
2567                 smu7_complete_dependency_tables(hwmgr);
2568                 smu7_set_private_data_based_on_pptable_v1(hwmgr);
2569         } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
2570                 smu7_patch_dependency_tables_with_leakage(hwmgr);
2571                 smu7_set_private_data_based_on_pptable_v0(hwmgr);
2572         }
2573
2574         /* Initalize Dynamic State Adjustment Rule Settings */
2575         result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
2576
2577         if (0 == result) {
2578                 struct amdgpu_device *adev = hwmgr->adev;
2579
2580                 data->is_tlu_enabled = false;
2581
2582                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
2583                                                         SMU7_MAX_HARDWARE_POWERLEVELS;
2584                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
2585                 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
2586
2587                 data->pcie_gen_cap = adev->pm.pcie_gen_mask;
2588                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
2589                         data->pcie_spc_cap = 20;
2590                 data->pcie_lane_cap = adev->pm.pcie_mlw_mask;
2591
2592                 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
2593 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
2594                 hwmgr->platform_descriptor.clockStep.engineClock = 500;
2595                 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
2596                 smu7_thermal_parameter_init(hwmgr);
2597         } else {
2598                 /* Ignore return value in here, we are cleaning up a mess. */
2599                 smu7_hwmgr_backend_fini(hwmgr);
2600         }
2601
2602         return 0;
2603 }
2604
2605 static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
2606 {
2607         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2608         uint32_t level, tmp;
2609
2610         if (!data->pcie_dpm_key_disabled) {
2611                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
2612                         level = 0;
2613                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
2614                         while (tmp >>= 1)
2615                                 level++;
2616
2617                         if (level)
2618                                 smum_send_msg_to_smc_with_parameter(hwmgr,
2619                                                 PPSMC_MSG_PCIeDPM_ForceLevel, level,
2620                                                 NULL);
2621                 }
2622         }
2623
2624         if (!data->sclk_dpm_key_disabled) {
2625                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2626                         level = 0;
2627                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
2628                         while (tmp >>= 1)
2629                                 level++;
2630
2631                         if (level)
2632                                 smum_send_msg_to_smc_with_parameter(hwmgr,
2633                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2634                                                 (1 << level),
2635                                                 NULL);
2636                 }
2637         }
2638
2639         if (!data->mclk_dpm_key_disabled) {
2640                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
2641                         level = 0;
2642                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
2643                         while (tmp >>= 1)
2644                                 level++;
2645
2646                         if (level)
2647                                 smum_send_msg_to_smc_with_parameter(hwmgr,
2648                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
2649                                                 (1 << level),
2650                                                 NULL);
2651                 }
2652         }
2653
2654         return 0;
2655 }
2656
2657 static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
2658 {
2659         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2660
2661         if (hwmgr->pp_table_version == PP_TABLE_V1)
2662                 phm_apply_dal_min_voltage_request(hwmgr);
2663 /* TO DO  for v0 iceland and Ci*/
2664
2665         if (!data->sclk_dpm_key_disabled) {
2666                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
2667                         smum_send_msg_to_smc_with_parameter(hwmgr,
2668                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
2669                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask,
2670                                         NULL);
2671         }
2672
2673         if (!data->mclk_dpm_key_disabled) {
2674                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
2675                         smum_send_msg_to_smc_with_parameter(hwmgr,
2676                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
2677                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask,
2678                                         NULL);
2679         }
2680
2681         return 0;
2682 }
2683
2684 static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2685 {
2686         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2687
2688         if (!smum_is_dpm_running(hwmgr))
2689                 return -EINVAL;
2690
2691         if (!data->pcie_dpm_key_disabled) {
2692                 smum_send_msg_to_smc(hwmgr,
2693                                 PPSMC_MSG_PCIeDPM_UnForceLevel,
2694                                 NULL);
2695         }
2696
2697         return smu7_upload_dpm_level_enable_mask(hwmgr);
2698 }
2699
2700 static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2701 {
2702         struct smu7_hwmgr *data =
2703                         (struct smu7_hwmgr *)(hwmgr->backend);
2704         uint32_t level;
2705
2706         if (!data->sclk_dpm_key_disabled)
2707                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2708                         level = phm_get_lowest_enabled_level(hwmgr,
2709                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
2710                         smum_send_msg_to_smc_with_parameter(hwmgr,
2711                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
2712                                                             (1 << level),
2713                                                             NULL);
2714
2715         }
2716
2717         if (!data->mclk_dpm_key_disabled) {
2718                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
2719                         level = phm_get_lowest_enabled_level(hwmgr,
2720                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
2721                         smum_send_msg_to_smc_with_parameter(hwmgr,
2722                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
2723                                                             (1 << level),
2724                                                             NULL);
2725                 }
2726         }
2727
2728         if (!data->pcie_dpm_key_disabled) {
2729                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
2730                         level = phm_get_lowest_enabled_level(hwmgr,
2731                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
2732                         smum_send_msg_to_smc_with_parameter(hwmgr,
2733                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
2734                                                             (level),
2735                                                             NULL);
2736                 }
2737         }
2738
2739         return 0;
2740 }
2741
2742 static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2743                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask)
2744 {
2745         uint32_t percentage;
2746         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2747         struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
2748         int32_t tmp_mclk;
2749         int32_t tmp_sclk;
2750         int32_t count;
2751
2752         if (golden_dpm_table->mclk_table.count < 1)
2753                 return -EINVAL;
2754
2755         percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value /
2756                         golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
2757
2758         if (golden_dpm_table->mclk_table.count == 1) {
2759                 percentage = 70;
2760                 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
2761                 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
2762         } else {
2763                 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value;
2764                 *mclk_mask = golden_dpm_table->mclk_table.count - 2;
2765         }
2766
2767         tmp_sclk = tmp_mclk * percentage / 100;
2768
2769         if (hwmgr->pp_table_version == PP_TABLE_V0) {
2770                 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
2771                         count >= 0; count--) {
2772                         if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) {
2773                                 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk;
2774                                 *sclk_mask = count;
2775                                 break;
2776                         }
2777                 }
2778                 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2779                         *sclk_mask = 0;
2780                         tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk;
2781                 }
2782
2783                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2784                         *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
2785         } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
2786                 struct phm_ppt_v1_information *table_info =
2787                                 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2788
2789                 for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
2790                         if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) {
2791                                 tmp_sclk = table_info->vdd_dep_on_sclk->entries[count].clk;
2792                                 *sclk_mask = count;
2793                                 break;
2794                         }
2795                 }
2796                 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2797                         *sclk_mask = 0;
2798                         tmp_sclk =  table_info->vdd_dep_on_sclk->entries[0].clk;
2799                 }
2800
2801                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2802                         *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
2803         }
2804
2805         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
2806                 *mclk_mask = 0;
2807         else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2808                 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
2809
2810         *pcie_mask = data->dpm_table.pcie_speed_table.count - 1;
2811         hwmgr->pstate_sclk = tmp_sclk;
2812         hwmgr->pstate_mclk = tmp_mclk;
2813
2814         return 0;
2815 }
2816
2817 static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
2818                                 enum amd_dpm_forced_level level)
2819 {
2820         int ret = 0;
2821         uint32_t sclk_mask = 0;
2822         uint32_t mclk_mask = 0;
2823         uint32_t pcie_mask = 0;
2824
2825         if (hwmgr->pstate_sclk == 0)
2826                 smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
2827
2828         switch (level) {
2829         case AMD_DPM_FORCED_LEVEL_HIGH:
2830                 ret = smu7_force_dpm_highest(hwmgr);
2831                 break;
2832         case AMD_DPM_FORCED_LEVEL_LOW:
2833                 ret = smu7_force_dpm_lowest(hwmgr);
2834                 break;
2835         case AMD_DPM_FORCED_LEVEL_AUTO:
2836                 ret = smu7_unforce_dpm_levels(hwmgr);
2837                 break;
2838         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2839         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2840         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2841         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2842                 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
2843                 if (ret)
2844                         return ret;
2845                 smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
2846                 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
2847                 smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask);
2848                 break;
2849         case AMD_DPM_FORCED_LEVEL_MANUAL:
2850         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2851         default:
2852                 break;
2853         }
2854
2855         if (!ret) {
2856                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2857                         smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
2858                 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2859                         smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
2860         }
2861         return ret;
2862 }
2863
2864 static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr)
2865 {
2866         return sizeof(struct smu7_power_state);
2867 }
2868
2869 static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr,
2870                                  uint32_t vblank_time_us)
2871 {
2872         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2873         uint32_t switch_limit_us;
2874
2875         switch (hwmgr->chip_id) {
2876         case CHIP_POLARIS10:
2877         case CHIP_POLARIS11:
2878         case CHIP_POLARIS12:
2879                 if (hwmgr->is_kicker)
2880                         switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
2881                 else
2882                         switch_limit_us = data->is_memory_gddr5 ? 190 : 150;
2883                 break;
2884         case CHIP_VEGAM:
2885                 switch_limit_us = 30;
2886                 break;
2887         default:
2888                 switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
2889                 break;
2890         }
2891
2892         if (vblank_time_us < switch_limit_us)
2893                 return true;
2894         else
2895                 return false;
2896 }
2897
2898 static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
2899                                 struct pp_power_state *request_ps,
2900                         const struct pp_power_state *current_ps)
2901 {
2902         struct amdgpu_device *adev = hwmgr->adev;
2903         struct smu7_power_state *smu7_ps =
2904                                 cast_phw_smu7_power_state(&request_ps->hardware);
2905         uint32_t sclk;
2906         uint32_t mclk;
2907         struct PP_Clocks minimum_clocks = {0};
2908         bool disable_mclk_switching;
2909         bool disable_mclk_switching_for_frame_lock;
2910         const struct phm_clock_and_voltage_limits *max_limits;
2911         uint32_t i;
2912         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2913         struct phm_ppt_v1_information *table_info =
2914                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2915         int32_t count;
2916         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
2917
2918         data->battery_state = (PP_StateUILabel_Battery ==
2919                         request_ps->classification.ui_label);
2920
2921         PP_ASSERT_WITH_CODE(smu7_ps->performance_level_count == 2,
2922                                  "VI should always have 2 performance levels",
2923                                 );
2924
2925         max_limits = adev->pm.ac_power ?
2926                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
2927                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
2928
2929         /* Cap clock DPM tables at DC MAX if it is in DC. */
2930         if (!adev->pm.ac_power) {
2931                 for (i = 0; i < smu7_ps->performance_level_count; i++) {
2932                         if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk)
2933                                 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk;
2934                         if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk)
2935                                 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk;
2936                 }
2937         }
2938
2939         minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
2940         minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2941
2942         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2943                         PHM_PlatformCaps_StablePState)) {
2944                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
2945                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
2946
2947                 for (count = table_info->vdd_dep_on_sclk->count - 1;
2948                                 count >= 0; count--) {
2949                         if (stable_pstate_sclk >=
2950                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
2951                                 stable_pstate_sclk =
2952                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
2953                                 break;
2954                         }
2955                 }
2956
2957                 if (count < 0)
2958                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
2959
2960                 stable_pstate_mclk = max_limits->mclk;
2961
2962                 minimum_clocks.engineClock = stable_pstate_sclk;
2963                 minimum_clocks.memoryClock = stable_pstate_mclk;
2964         }
2965
2966         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
2967                                     hwmgr->platform_descriptor.platformCaps,
2968                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
2969
2970
2971         if (hwmgr->display_config->num_display == 0)
2972                 disable_mclk_switching = false;
2973         else
2974                 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
2975                                           !hwmgr->display_config->multi_monitor_in_sync) ||
2976                         disable_mclk_switching_for_frame_lock ||
2977                         smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time);
2978
2979         sclk = smu7_ps->performance_levels[0].engine_clock;
2980         mclk = smu7_ps->performance_levels[0].memory_clock;
2981
2982         if (disable_mclk_switching)
2983                 mclk = smu7_ps->performance_levels
2984                 [smu7_ps->performance_level_count - 1].memory_clock;
2985
2986         if (sclk < minimum_clocks.engineClock)
2987                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
2988                                 max_limits->sclk : minimum_clocks.engineClock;
2989
2990         if (mclk < minimum_clocks.memoryClock)
2991                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
2992                                 max_limits->mclk : minimum_clocks.memoryClock;
2993
2994         smu7_ps->performance_levels[0].engine_clock = sclk;
2995         smu7_ps->performance_levels[0].memory_clock = mclk;
2996
2997         smu7_ps->performance_levels[1].engine_clock =
2998                 (smu7_ps->performance_levels[1].engine_clock >=
2999                                 smu7_ps->performance_levels[0].engine_clock) ?
3000                                                 smu7_ps->performance_levels[1].engine_clock :
3001                                                 smu7_ps->performance_levels[0].engine_clock;
3002
3003         if (disable_mclk_switching) {
3004                 if (mclk < smu7_ps->performance_levels[1].memory_clock)
3005                         mclk = smu7_ps->performance_levels[1].memory_clock;
3006
3007                 smu7_ps->performance_levels[0].memory_clock = mclk;
3008                 smu7_ps->performance_levels[1].memory_clock = mclk;
3009         } else {
3010                 if (smu7_ps->performance_levels[1].memory_clock <
3011                                 smu7_ps->performance_levels[0].memory_clock)
3012                         smu7_ps->performance_levels[1].memory_clock =
3013                                         smu7_ps->performance_levels[0].memory_clock;
3014         }
3015
3016         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3017                         PHM_PlatformCaps_StablePState)) {
3018                 for (i = 0; i < smu7_ps->performance_level_count; i++) {
3019                         smu7_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3020                         smu7_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3021                         smu7_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3022                         smu7_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3023                 }
3024         }
3025         return 0;
3026 }
3027
3028
3029 static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3030 {
3031         struct pp_power_state  *ps;
3032         struct smu7_power_state  *smu7_ps;
3033
3034         if (hwmgr == NULL)
3035                 return -EINVAL;
3036
3037         ps = hwmgr->request_ps;
3038
3039         if (ps == NULL)
3040                 return -EINVAL;
3041
3042         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
3043
3044         if (low)
3045                 return smu7_ps->performance_levels[0].memory_clock;
3046         else
3047                 return smu7_ps->performance_levels
3048                                 [smu7_ps->performance_level_count-1].memory_clock;
3049 }
3050
3051 static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3052 {
3053         struct pp_power_state  *ps;
3054         struct smu7_power_state  *smu7_ps;
3055
3056         if (hwmgr == NULL)
3057                 return -EINVAL;
3058
3059         ps = hwmgr->request_ps;
3060
3061         if (ps == NULL)
3062                 return -EINVAL;
3063
3064         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
3065
3066         if (low)
3067                 return smu7_ps->performance_levels[0].engine_clock;
3068         else
3069                 return smu7_ps->performance_levels
3070                                 [smu7_ps->performance_level_count-1].engine_clock;
3071 }
3072
3073 static int smu7_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3074                                         struct pp_hw_power_state *hw_ps)
3075 {
3076         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3077         struct smu7_power_state *ps = (struct smu7_power_state *)hw_ps;
3078         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3079         uint16_t size;
3080         uint8_t frev, crev;
3081         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3082
3083         /* First retrieve the Boot clocks and VDDC from the firmware info table.
3084          * We assume here that fw_info is unchanged if this call fails.
3085          */
3086         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)smu_atom_get_data_table(hwmgr->adev, index,
3087                         &size, &frev, &crev);
3088         if (!fw_info)
3089                 /* During a test, there is no firmware info table. */
3090                 return 0;
3091
3092         /* Patch the state. */
3093         data->vbios_boot_state.sclk_bootup_value =
3094                         le32_to_cpu(fw_info->ulDefaultEngineClock);
3095         data->vbios_boot_state.mclk_bootup_value =
3096                         le32_to_cpu(fw_info->ulDefaultMemoryClock);
3097         data->vbios_boot_state.mvdd_bootup_value =
3098                         le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3099         data->vbios_boot_state.vddc_bootup_value =
3100                         le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3101         data->vbios_boot_state.vddci_bootup_value =
3102                         le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3103         data->vbios_boot_state.pcie_gen_bootup_value =
3104                         smu7_get_current_pcie_speed(hwmgr);
3105
3106         data->vbios_boot_state.pcie_lane_bootup_value =
3107                         (uint16_t)smu7_get_current_pcie_lane_number(hwmgr);
3108
3109         /* set boot power state */
3110         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3111         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3112         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3113         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3114
3115         return 0;
3116 }
3117
3118 static int smu7_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr)
3119 {
3120         int result;
3121         unsigned long ret = 0;
3122
3123         if (hwmgr->pp_table_version == PP_TABLE_V0) {
3124                 result = pp_tables_get_num_of_entries(hwmgr, &ret);
3125                 return result ? 0 : ret;
3126         } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
3127                 result = get_number_of_powerplay_table_entries_v1_0(hwmgr);
3128                 return result;
3129         }
3130         return 0;
3131 }
3132
3133 static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
3134                 void *state, struct pp_power_state *power_state,
3135                 void *pp_table, uint32_t classification_flag)
3136 {
3137         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3138         struct smu7_power_state  *smu7_power_state =
3139                         (struct smu7_power_state *)(&(power_state->hardware));
3140         struct smu7_performance_level *performance_level;
3141         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3142         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3143                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3144         PPTable_Generic_SubTable_Header *sclk_dep_table =
3145                         (PPTable_Generic_SubTable_Header *)
3146                         (((unsigned long)powerplay_table) +
3147                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3148
3149         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3150                         (ATOM_Tonga_MCLK_Dependency_Table *)
3151                         (((unsigned long)powerplay_table) +
3152                                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3153
3154         /* The following fields are not initialized here: id orderedList allStatesList */
3155         power_state->classification.ui_label =
3156                         (le16_to_cpu(state_entry->usClassification) &
3157                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3158                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3159         power_state->classification.flags = classification_flag;
3160         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3161
3162         power_state->classification.temporary_state = false;
3163         power_state->classification.to_be_deleted = false;
3164
3165         power_state->validation.disallowOnDC =
3166                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3167                                         ATOM_Tonga_DISALLOW_ON_DC));
3168
3169         power_state->pcie.lanes = 0;
3170
3171         power_state->display.disableFrameModulation = false;
3172         power_state->display.limitRefreshrate = false;
3173         power_state->display.enableVariBright =
3174                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3175                                         ATOM_Tonga_ENABLE_VARIBRIGHT));
3176
3177         power_state->validation.supportedPowerLevels = 0;
3178         power_state->uvd_clocks.VCLK = 0;
3179         power_state->uvd_clocks.DCLK = 0;
3180         power_state->temperatures.min = 0;
3181         power_state->temperatures.max = 0;
3182
3183         performance_level = &(smu7_power_state->performance_levels
3184                         [smu7_power_state->performance_level_count++]);
3185
3186         PP_ASSERT_WITH_CODE(
3187                         (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
3188                         "Performance levels exceeds SMC limit!",
3189                         return -EINVAL);
3190
3191         PP_ASSERT_WITH_CODE(
3192                         (smu7_power_state->performance_level_count <=
3193                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3194                         "Performance levels exceeds Driver limit!",
3195                         return -EINVAL);
3196
3197         /* Performance levels are arranged from low to high. */
3198         performance_level->memory_clock = mclk_dep_table->entries
3199                         [state_entry->ucMemoryClockIndexLow].ulMclk;
3200         if (sclk_dep_table->ucRevId == 0)
3201                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3202                         [state_entry->ucEngineClockIndexLow].ulSclk;
3203         else if (sclk_dep_table->ucRevId == 1)
3204                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3205                         [state_entry->ucEngineClockIndexLow].ulSclk;
3206         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3207                         state_entry->ucPCIEGenLow);
3208         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3209                         state_entry->ucPCIELaneLow);
3210
3211         performance_level = &(smu7_power_state->performance_levels
3212                         [smu7_power_state->performance_level_count++]);
3213         performance_level->memory_clock = mclk_dep_table->entries
3214                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
3215
3216         if (sclk_dep_table->ucRevId == 0)
3217                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3218                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3219         else if (sclk_dep_table->ucRevId == 1)
3220                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3221                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3222
3223         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3224                         state_entry->ucPCIEGenHigh);
3225         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3226                         state_entry->ucPCIELaneHigh);
3227
3228         return 0;
3229 }
3230
3231 static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr,
3232                 unsigned long entry_index, struct pp_power_state *state)
3233 {
3234         int result;
3235         struct smu7_power_state *ps;
3236         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3237         struct phm_ppt_v1_information *table_info =
3238                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3239         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3240                         table_info->vdd_dep_on_mclk;
3241
3242         state->hardware.magic = PHM_VIslands_Magic;
3243
3244         ps = (struct smu7_power_state *)(&state->hardware);
3245
3246         result = get_powerplay_table_entry_v1_0(hwmgr, entry_index, state,
3247                         smu7_get_pp_table_entry_callback_func_v1);
3248
3249         /* This is the earliest time we have all the dependency table and the VBIOS boot state
3250          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3251          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3252          */
3253         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3254                 if (dep_mclk_table->entries[0].clk !=
3255                                 data->vbios_boot_state.mclk_bootup_value)
3256                         pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
3257                                         "does not match VBIOS boot MCLK level");
3258                 if (dep_mclk_table->entries[0].vddci !=
3259                                 data->vbios_boot_state.vddci_bootup_value)
3260                         pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
3261                                         "does not match VBIOS boot VDDCI level");
3262         }
3263
3264         /* set DC compatible flag if this state supports DC */
3265         if (!state->validation.disallowOnDC)
3266                 ps->dc_compatible = true;
3267
3268         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3269                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3270
3271         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3272         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3273
3274         if (!result) {
3275                 uint32_t i;
3276
3277                 switch (state->classification.ui_label) {
3278                 case PP_StateUILabel_Performance:
3279                         data->use_pcie_performance_levels = true;
3280                         for (i = 0; i < ps->performance_level_count; i++) {
3281                                 if (data->pcie_gen_performance.max <
3282                                                 ps->performance_levels[i].pcie_gen)
3283                                         data->pcie_gen_performance.max =
3284                                                         ps->performance_levels[i].pcie_gen;
3285
3286                                 if (data->pcie_gen_performance.min >
3287                                                 ps->performance_levels[i].pcie_gen)
3288                                         data->pcie_gen_performance.min =
3289                                                         ps->performance_levels[i].pcie_gen;
3290
3291                                 if (data->pcie_lane_performance.max <
3292                                                 ps->performance_levels[i].pcie_lane)
3293                                         data->pcie_lane_performance.max =
3294                                                         ps->performance_levels[i].pcie_lane;
3295                                 if (data->pcie_lane_performance.min >
3296                                                 ps->performance_levels[i].pcie_lane)
3297                                         data->pcie_lane_performance.min =
3298                                                         ps->performance_levels[i].pcie_lane;
3299                         }
3300                         break;
3301                 case PP_StateUILabel_Battery:
3302                         data->use_pcie_power_saving_levels = true;
3303
3304                         for (i = 0; i < ps->performance_level_count; i++) {
3305                                 if (data->pcie_gen_power_saving.max <
3306                                                 ps->performance_levels[i].pcie_gen)
3307                                         data->pcie_gen_power_saving.max =
3308                                                         ps->performance_levels[i].pcie_gen;
3309
3310                                 if (data->pcie_gen_power_saving.min >
3311                                                 ps->performance_levels[i].pcie_gen)
3312                                         data->pcie_gen_power_saving.min =
3313                                                         ps->performance_levels[i].pcie_gen;
3314
3315                                 if (data->pcie_lane_power_saving.max <
3316                                                 ps->performance_levels[i].pcie_lane)
3317                                         data->pcie_lane_power_saving.max =
3318                                                         ps->performance_levels[i].pcie_lane;
3319
3320                                 if (data->pcie_lane_power_saving.min >
3321                                                 ps->performance_levels[i].pcie_lane)
3322                                         data->pcie_lane_power_saving.min =
3323                                                         ps->performance_levels[i].pcie_lane;
3324                         }
3325                         break;
3326                 default:
3327                         break;
3328                 }
3329         }
3330         return 0;
3331 }
3332
3333 static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr,
3334                                         struct pp_hw_power_state *power_state,
3335                                         unsigned int index, const void *clock_info)
3336 {
3337         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3338         struct smu7_power_state  *ps = cast_phw_smu7_power_state(power_state);
3339         const ATOM_PPLIB_CI_CLOCK_INFO *visland_clk_info = clock_info;
3340         struct smu7_performance_level *performance_level;
3341         uint32_t engine_clock, memory_clock;
3342         uint16_t pcie_gen_from_bios;
3343
3344         engine_clock = visland_clk_info->ucEngineClockHigh << 16 | visland_clk_info->usEngineClockLow;
3345         memory_clock = visland_clk_info->ucMemoryClockHigh << 16 | visland_clk_info->usMemoryClockLow;
3346
3347         if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk)
3348                 data->highest_mclk = memory_clock;
3349
3350         PP_ASSERT_WITH_CODE(
3351                         (ps->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
3352                         "Performance levels exceeds SMC limit!",
3353                         return -EINVAL);
3354
3355         PP_ASSERT_WITH_CODE(
3356                         (ps->performance_level_count <
3357                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3358                         "Performance levels exceeds Driver limit, Skip!",
3359                         return 0);
3360
3361         performance_level = &(ps->performance_levels
3362                         [ps->performance_level_count++]);
3363
3364         /* Performance levels are arranged from low to high. */
3365         performance_level->memory_clock = memory_clock;
3366         performance_level->engine_clock = engine_clock;
3367
3368         pcie_gen_from_bios = visland_clk_info->ucPCIEGen;
3369
3370         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, pcie_gen_from_bios);
3371         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, visland_clk_info->usPCIELane);
3372
3373         return 0;
3374 }
3375
3376 static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr,
3377                 unsigned long entry_index, struct pp_power_state *state)
3378 {
3379         int result;
3380         struct smu7_power_state *ps;
3381         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3382         struct phm_clock_voltage_dependency_table *dep_mclk_table =
3383                         hwmgr->dyn_state.vddci_dependency_on_mclk;
3384
3385         memset(&state->hardware, 0x00, sizeof(struct pp_hw_power_state));
3386
3387         state->hardware.magic = PHM_VIslands_Magic;
3388
3389         ps = (struct smu7_power_state *)(&state->hardware);
3390
3391         result = pp_tables_get_entry(hwmgr, entry_index, state,
3392                         smu7_get_pp_table_entry_callback_func_v0);
3393
3394         /*
3395          * This is the earliest time we have all the dependency table
3396          * and the VBIOS boot state as
3397          * PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot
3398          * state if there is only one VDDCI/MCLK level, check if it's
3399          * the same as VBIOS boot state
3400          */
3401         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3402                 if (dep_mclk_table->entries[0].clk !=
3403                                 data->vbios_boot_state.mclk_bootup_value)
3404                         pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
3405                                         "does not match VBIOS boot MCLK level");
3406                 if (dep_mclk_table->entries[0].v !=
3407                                 data->vbios_boot_state.vddci_bootup_value)
3408                         pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
3409                                         "does not match VBIOS boot VDDCI level");
3410         }
3411
3412         /* set DC compatible flag if this state supports DC */
3413         if (!state->validation.disallowOnDC)
3414                 ps->dc_compatible = true;
3415
3416         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3417                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3418
3419         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3420         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3421
3422         if (!result) {
3423                 uint32_t i;
3424
3425                 switch (state->classification.ui_label) {
3426                 case PP_StateUILabel_Performance:
3427                         data->use_pcie_performance_levels = true;
3428
3429                         for (i = 0; i < ps->performance_level_count; i++) {
3430                                 if (data->pcie_gen_performance.max <
3431                                                 ps->performance_levels[i].pcie_gen)
3432                                         data->pcie_gen_performance.max =
3433                                                         ps->performance_levels[i].pcie_gen;
3434
3435                                 if (data->pcie_gen_performance.min >
3436                                                 ps->performance_levels[i].pcie_gen)
3437                                         data->pcie_gen_performance.min =
3438                                                         ps->performance_levels[i].pcie_gen;
3439
3440                                 if (data->pcie_lane_performance.max <
3441                                                 ps->performance_levels[i].pcie_lane)
3442                                         data->pcie_lane_performance.max =
3443                                                         ps->performance_levels[i].pcie_lane;
3444
3445                                 if (data->pcie_lane_performance.min >
3446                                                 ps->performance_levels[i].pcie_lane)
3447                                         data->pcie_lane_performance.min =
3448                                                         ps->performance_levels[i].pcie_lane;
3449                         }
3450                         break;
3451                 case PP_StateUILabel_Battery:
3452                         data->use_pcie_power_saving_levels = true;
3453
3454                         for (i = 0; i < ps->performance_level_count; i++) {
3455                                 if (data->pcie_gen_power_saving.max <
3456                                                 ps->performance_levels[i].pcie_gen)
3457                                         data->pcie_gen_power_saving.max =
3458                                                         ps->performance_levels[i].pcie_gen;
3459
3460                                 if (data->pcie_gen_power_saving.min >
3461                                                 ps->performance_levels[i].pcie_gen)
3462                                         data->pcie_gen_power_saving.min =
3463                                                         ps->performance_levels[i].pcie_gen;
3464
3465                                 if (data->pcie_lane_power_saving.max <
3466                                                 ps->performance_levels[i].pcie_lane)
3467                                         data->pcie_lane_power_saving.max =
3468                                                         ps->performance_levels[i].pcie_lane;
3469
3470                                 if (data->pcie_lane_power_saving.min >
3471                                                 ps->performance_levels[i].pcie_lane)
3472                                         data->pcie_lane_power_saving.min =
3473                                                         ps->performance_levels[i].pcie_lane;
3474                         }
3475                         break;
3476                 default:
3477                         break;
3478                 }
3479         }
3480         return 0;
3481 }
3482
3483 static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3484                 unsigned long entry_index, struct pp_power_state *state)
3485 {
3486         if (hwmgr->pp_table_version == PP_TABLE_V0)
3487                 return smu7_get_pp_table_entry_v0(hwmgr, entry_index, state);
3488         else if (hwmgr->pp_table_version == PP_TABLE_V1)
3489                 return smu7_get_pp_table_entry_v1(hwmgr, entry_index, state);
3490
3491         return 0;
3492 }
3493
3494 static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query)
3495 {
3496         struct amdgpu_device *adev = hwmgr->adev;
3497         int i;
3498         u32 tmp = 0;
3499
3500         if (!query)
3501                 return -EINVAL;
3502
3503         /*
3504          * PPSMC_MSG_GetCurrPkgPwr is not supported on:
3505          *  - Hawaii
3506          *  - Bonaire
3507          *  - Fiji
3508          *  - Tonga
3509          */
3510         if ((adev->asic_type != CHIP_HAWAII) &&
3511             (adev->asic_type != CHIP_BONAIRE) &&
3512             (adev->asic_type != CHIP_FIJI) &&
3513             (adev->asic_type != CHIP_TONGA)) {
3514                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0, &tmp);
3515                 *query = tmp;
3516
3517                 if (tmp != 0)
3518                         return 0;
3519         }
3520
3521         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart, NULL);
3522         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3523                                                         ixSMU_PM_STATUS_95, 0);
3524
3525         for (i = 0; i < 10; i++) {
3526                 msleep(500);
3527                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample, NULL);
3528                 tmp = cgs_read_ind_register(hwmgr->device,
3529                                                 CGS_IND_REG__SMC,
3530                                                 ixSMU_PM_STATUS_95);
3531                 if (tmp != 0)
3532                         break;
3533         }
3534         *query = tmp;
3535
3536         return 0;
3537 }
3538
3539 static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3540                             void *value, int *size)
3541 {
3542         uint32_t sclk, mclk, activity_percent;
3543         uint32_t offset, val_vid;
3544         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3545
3546         /* size must be at least 4 bytes for all sensors */
3547         if (*size < 4)
3548                 return -EINVAL;
3549
3550         switch (idx) {
3551         case AMDGPU_PP_SENSOR_GFX_SCLK:
3552                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, &sclk);
3553                 *((uint32_t *)value) = sclk;
3554                 *size = 4;
3555                 return 0;
3556         case AMDGPU_PP_SENSOR_GFX_MCLK:
3557                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, &mclk);
3558                 *((uint32_t *)value) = mclk;
3559                 *size = 4;
3560                 return 0;
3561         case AMDGPU_PP_SENSOR_GPU_LOAD:
3562         case AMDGPU_PP_SENSOR_MEM_LOAD:
3563                 offset = data->soft_regs_start + smum_get_offsetof(hwmgr,
3564                                                                 SMU_SoftRegisters,
3565                                                                 (idx == AMDGPU_PP_SENSOR_GPU_LOAD) ?
3566                                                                 AverageGraphicsActivity:
3567                                                                 AverageMemoryActivity);
3568
3569                 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3570                 activity_percent += 0x80;
3571                 activity_percent >>= 8;
3572                 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
3573                 *size = 4;
3574                 return 0;
3575         case AMDGPU_PP_SENSOR_GPU_TEMP:
3576                 *((uint32_t *)value) = smu7_thermal_get_temperature(hwmgr);
3577                 *size = 4;
3578                 return 0;
3579         case AMDGPU_PP_SENSOR_UVD_POWER:
3580                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
3581                 *size = 4;
3582                 return 0;
3583         case AMDGPU_PP_SENSOR_VCE_POWER:
3584                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
3585                 *size = 4;
3586                 return 0;
3587         case AMDGPU_PP_SENSOR_GPU_POWER:
3588                 return smu7_get_gpu_power(hwmgr, (uint32_t *)value);
3589         case AMDGPU_PP_SENSOR_VDDGFX:
3590                 if ((data->vr_config & 0xff) == 0x2)
3591                         val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
3592                                         CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE2_VID);
3593                 else
3594                         val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
3595                                         CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE1_VID);
3596
3597                 *((uint32_t *)value) = (uint32_t)convert_to_vddc(val_vid);
3598                 return 0;
3599         default:
3600                 return -EINVAL;
3601         }
3602 }
3603
3604 static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3605 {
3606         const struct phm_set_power_state_input *states =
3607                         (const struct phm_set_power_state_input *)input;
3608         const struct smu7_power_state *smu7_ps =
3609                         cast_const_phw_smu7_power_state(states->pnew_state);
3610         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3611         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3612         uint32_t sclk = smu7_ps->performance_levels
3613                         [smu7_ps->performance_level_count - 1].engine_clock;
3614         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3615         uint32_t mclk = smu7_ps->performance_levels
3616                         [smu7_ps->performance_level_count - 1].memory_clock;
3617         struct PP_Clocks min_clocks = {0};
3618         uint32_t i;
3619
3620         for (i = 0; i < sclk_table->count; i++) {
3621                 if (sclk == sclk_table->dpm_levels[i].value)
3622                         break;
3623         }
3624
3625         if (i >= sclk_table->count) {
3626                 if (sclk > sclk_table->dpm_levels[i-1].value) {
3627                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3628                         sclk_table->dpm_levels[i-1].value = sclk;
3629                 }
3630         } else {
3631         /* TODO: Check SCLK in DAL's minimum clocks
3632          * in case DeepSleep divider update is required.
3633          */
3634                 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3635                         (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK ||
3636                                 data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
3637                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3638         }
3639
3640         for (i = 0; i < mclk_table->count; i++) {
3641                 if (mclk == mclk_table->dpm_levels[i].value)
3642                         break;
3643         }
3644
3645         if (i >= mclk_table->count) {
3646                 if (mclk > mclk_table->dpm_levels[i-1].value) {
3647                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3648                         mclk_table->dpm_levels[i-1].value = mclk;
3649                 }
3650         }
3651
3652         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
3653                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3654
3655         return 0;
3656 }
3657
3658 static uint16_t smu7_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
3659                 const struct smu7_power_state *smu7_ps)
3660 {
3661         uint32_t i;
3662         uint32_t sclk, max_sclk = 0;
3663         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3664         struct smu7_dpm_table *dpm_table = &data->dpm_table;
3665
3666         for (i = 0; i < smu7_ps->performance_level_count; i++) {
3667                 sclk = smu7_ps->performance_levels[i].engine_clock;
3668                 if (max_sclk < sclk)
3669                         max_sclk = sclk;
3670         }
3671
3672         for (i = 0; i < dpm_table->sclk_table.count; i++) {
3673                 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
3674                         return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
3675                                         dpm_table->pcie_speed_table.dpm_levels
3676                                         [dpm_table->pcie_speed_table.count - 1].value :
3677                                         dpm_table->pcie_speed_table.dpm_levels[i].value);
3678         }
3679
3680         return 0;
3681 }
3682
3683 static int smu7_request_link_speed_change_before_state_change(
3684                 struct pp_hwmgr *hwmgr, const void *input)
3685 {
3686         const struct phm_set_power_state_input *states =
3687                         (const struct phm_set_power_state_input *)input;
3688         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3689         const struct smu7_power_state *smu7_nps =
3690                         cast_const_phw_smu7_power_state(states->pnew_state);
3691         const struct smu7_power_state *polaris10_cps =
3692                         cast_const_phw_smu7_power_state(states->pcurrent_state);
3693
3694         uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_nps);
3695         uint16_t current_link_speed;
3696
3697         if (data->force_pcie_gen == PP_PCIEGenInvalid)
3698                 current_link_speed = smu7_get_maximum_link_speed(hwmgr, polaris10_cps);
3699         else
3700                 current_link_speed = data->force_pcie_gen;
3701
3702         data->force_pcie_gen = PP_PCIEGenInvalid;
3703         data->pspp_notify_required = false;
3704
3705         if (target_link_speed > current_link_speed) {
3706                 switch (target_link_speed) {
3707 #ifdef CONFIG_ACPI
3708                 case PP_PCIEGen3:
3709                         if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN3, false))
3710                                 break;
3711                         data->force_pcie_gen = PP_PCIEGen2;
3712                         if (current_link_speed == PP_PCIEGen2)
3713                                 break;
3714                         fallthrough;
3715                 case PP_PCIEGen2:
3716                         if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN2, false))
3717                                 break;
3718                         fallthrough;
3719 #endif
3720                 default:
3721                         data->force_pcie_gen = smu7_get_current_pcie_speed(hwmgr);
3722                         break;
3723                 }
3724         } else {
3725                 if (target_link_speed < current_link_speed)
3726                         data->pspp_notify_required = true;
3727         }
3728
3729         return 0;
3730 }
3731
3732 static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3733 {
3734         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3735
3736         if (0 == data->need_update_smu7_dpm_table)
3737                 return 0;
3738
3739         if ((0 == data->sclk_dpm_key_disabled) &&
3740                 (data->need_update_smu7_dpm_table &
3741                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3742                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3743                                 "Trying to freeze SCLK DPM when DPM is disabled",
3744                                 );
3745                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3746                                 PPSMC_MSG_SCLKDPM_FreezeLevel,
3747                                 NULL),
3748                                 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3749                                 return -EINVAL);
3750         }
3751
3752         if ((0 == data->mclk_dpm_key_disabled) &&
3753                 (data->need_update_smu7_dpm_table &
3754                  DPMTABLE_OD_UPDATE_MCLK)) {
3755                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3756                                 "Trying to freeze MCLK DPM when DPM is disabled",
3757                                 );
3758                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3759                                 PPSMC_MSG_MCLKDPM_FreezeLevel,
3760                                 NULL),
3761                                 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3762                                 return -EINVAL);
3763         }
3764
3765         return 0;
3766 }
3767
3768 static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
3769                 struct pp_hwmgr *hwmgr, const void *input)
3770 {
3771         int result = 0;
3772         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3773         struct smu7_dpm_table *dpm_table = &data->dpm_table;
3774         uint32_t count;
3775         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
3776         struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
3777         struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
3778
3779         if (0 == data->need_update_smu7_dpm_table)
3780                 return 0;
3781
3782         if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3783                 for (count = 0; count < dpm_table->sclk_table.count; count++) {
3784                         dpm_table->sclk_table.dpm_levels[count].enabled = odn_sclk_table->entries[count].enabled;
3785                         dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock;
3786                 }
3787         }
3788
3789         if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3790                 for (count = 0; count < dpm_table->mclk_table.count; count++) {
3791                         dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled;
3792                         dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock;
3793                 }
3794         }
3795
3796         if (data->need_update_smu7_dpm_table &
3797                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
3798                 result = smum_populate_all_graphic_levels(hwmgr);
3799                 PP_ASSERT_WITH_CODE((0 == result),
3800                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
3801                                 return result);
3802         }
3803
3804         if (data->need_update_smu7_dpm_table &
3805                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
3806                 /*populate MCLK dpm table to SMU7 */
3807                 result = smum_populate_all_memory_levels(hwmgr);
3808                 PP_ASSERT_WITH_CODE((0 == result),
3809                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
3810                                 return result);
3811         }
3812
3813         return result;
3814 }
3815
3816 static int smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
3817                           struct smu7_single_dpm_table *dpm_table,
3818                         uint32_t low_limit, uint32_t high_limit)
3819 {
3820         uint32_t i;
3821
3822         /* force the trim if mclk_switching is disabled to prevent flicker */
3823         bool force_trim = (low_limit == high_limit);
3824         for (i = 0; i < dpm_table->count; i++) {
3825         /*skip the trim if od is enabled*/
3826                 if ((!hwmgr->od_enabled || force_trim)
3827                         && (dpm_table->dpm_levels[i].value < low_limit
3828                         || dpm_table->dpm_levels[i].value > high_limit))
3829                         dpm_table->dpm_levels[i].enabled = false;
3830                 else
3831                         dpm_table->dpm_levels[i].enabled = true;
3832         }
3833
3834         return 0;
3835 }
3836
3837 static int smu7_trim_dpm_states(struct pp_hwmgr *hwmgr,
3838                 const struct smu7_power_state *smu7_ps)
3839 {
3840         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3841         uint32_t high_limit_count;
3842
3843         PP_ASSERT_WITH_CODE((smu7_ps->performance_level_count >= 1),
3844                         "power state did not have any performance level",
3845                         return -EINVAL);
3846
3847         high_limit_count = (1 == smu7_ps->performance_level_count) ? 0 : 1;
3848
3849         smu7_trim_single_dpm_states(hwmgr,
3850                         &(data->dpm_table.sclk_table),
3851                         smu7_ps->performance_levels[0].engine_clock,
3852                         smu7_ps->performance_levels[high_limit_count].engine_clock);
3853
3854         smu7_trim_single_dpm_states(hwmgr,
3855                         &(data->dpm_table.mclk_table),
3856                         smu7_ps->performance_levels[0].memory_clock,
3857                         smu7_ps->performance_levels[high_limit_count].memory_clock);
3858
3859         return 0;
3860 }
3861
3862 static int smu7_generate_dpm_level_enable_mask(
3863                 struct pp_hwmgr *hwmgr, const void *input)
3864 {
3865         int result = 0;
3866         const struct phm_set_power_state_input *states =
3867                         (const struct phm_set_power_state_input *)input;
3868         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3869         const struct smu7_power_state *smu7_ps =
3870                         cast_const_phw_smu7_power_state(states->pnew_state);
3871
3872
3873         result = smu7_trim_dpm_states(hwmgr, smu7_ps);
3874         if (result)
3875                 return result;
3876
3877         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
3878                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
3879         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
3880                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
3881         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
3882                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
3883
3884         return 0;
3885 }
3886
3887 static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3888 {
3889         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3890
3891         if (0 == data->need_update_smu7_dpm_table)
3892                 return 0;
3893
3894         if ((0 == data->sclk_dpm_key_disabled) &&
3895                 (data->need_update_smu7_dpm_table &
3896                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3897
3898                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3899                                 "Trying to Unfreeze SCLK DPM when DPM is disabled",
3900                                 );
3901                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3902                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel,
3903                                 NULL),
3904                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
3905                         return -EINVAL);
3906         }
3907
3908         if ((0 == data->mclk_dpm_key_disabled) &&
3909                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
3910
3911                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3912                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",
3913                                 );
3914                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3915                                 PPSMC_MSG_MCLKDPM_UnfreezeLevel,
3916                                 NULL),
3917                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
3918                     return -EINVAL);
3919         }
3920
3921         data->need_update_smu7_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
3922
3923         return 0;
3924 }
3925
3926 static int smu7_notify_link_speed_change_after_state_change(
3927                 struct pp_hwmgr *hwmgr, const void *input)
3928 {
3929         const struct phm_set_power_state_input *states =
3930                         (const struct phm_set_power_state_input *)input;
3931         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3932         const struct smu7_power_state *smu7_ps =
3933                         cast_const_phw_smu7_power_state(states->pnew_state);
3934         uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_ps);
3935         uint8_t  request;
3936
3937         if (data->pspp_notify_required) {
3938                 if (target_link_speed == PP_PCIEGen3)
3939                         request = PCIE_PERF_REQ_GEN3;
3940                 else if (target_link_speed == PP_PCIEGen2)
3941                         request = PCIE_PERF_REQ_GEN2;
3942                 else
3943                         request = PCIE_PERF_REQ_GEN1;
3944
3945                 if (request == PCIE_PERF_REQ_GEN1 &&
3946                                 smu7_get_current_pcie_speed(hwmgr) > 0)
3947                         return 0;
3948
3949 #ifdef CONFIG_ACPI
3950                 if (amdgpu_acpi_pcie_performance_request(hwmgr->adev, request, false)) {
3951                         if (PP_PCIEGen2 == target_link_speed)
3952                                 pr_info("PSPP request to switch to Gen2 from Gen3 Failed!");
3953                         else
3954                                 pr_info("PSPP request to switch to Gen1 from Gen2 Failed!");
3955                 }
3956 #endif
3957         }
3958
3959         return 0;
3960 }
3961
3962 static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr)
3963 {
3964         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3965
3966         if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) {
3967                 if (hwmgr->chip_id == CHIP_VEGAM)
3968                         smum_send_msg_to_smc_with_parameter(hwmgr,
3969                                         (PPSMC_Msg)PPSMC_MSG_SetVBITimeout_VEGAM, data->frame_time_x2,
3970                                         NULL);
3971                 else
3972                         smum_send_msg_to_smc_with_parameter(hwmgr,
3973                                         (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2,
3974                                         NULL);
3975         }
3976         return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_HasDisplay, NULL) == 0) ?  0 : -EINVAL;
3977 }
3978
3979 static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
3980 {
3981         int tmp_result, result = 0;
3982         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3983
3984         tmp_result = smu7_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
3985         PP_ASSERT_WITH_CODE((0 == tmp_result),
3986                         "Failed to find DPM states clocks in DPM table!",
3987                         result = tmp_result);
3988
3989         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3990                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
3991                 tmp_result =
3992                         smu7_request_link_speed_change_before_state_change(hwmgr, input);
3993                 PP_ASSERT_WITH_CODE((0 == tmp_result),
3994                                 "Failed to request link speed change before state change!",
3995                                 result = tmp_result);
3996         }
3997
3998         tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr);
3999         PP_ASSERT_WITH_CODE((0 == tmp_result),
4000                         "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4001
4002         tmp_result = smu7_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4003         PP_ASSERT_WITH_CODE((0 == tmp_result),
4004                         "Failed to populate and upload SCLK MCLK DPM levels!",
4005                         result = tmp_result);
4006
4007         /*
4008          * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag.
4009          * That effectively disables AVFS feature.
4010          */
4011         if (hwmgr->hardcode_pp_table != NULL)
4012                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
4013
4014         tmp_result = smu7_update_avfs(hwmgr);
4015         PP_ASSERT_WITH_CODE((0 == tmp_result),
4016                         "Failed to update avfs voltages!",
4017                         result = tmp_result);
4018
4019         tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
4020         PP_ASSERT_WITH_CODE((0 == tmp_result),
4021                         "Failed to generate DPM level enabled mask!",
4022                         result = tmp_result);
4023
4024         tmp_result = smum_update_sclk_threshold(hwmgr);
4025         PP_ASSERT_WITH_CODE((0 == tmp_result),
4026                         "Failed to update SCLK threshold!",
4027                         result = tmp_result);
4028
4029         tmp_result = smu7_notify_smc_display(hwmgr);
4030         PP_ASSERT_WITH_CODE((0 == tmp_result),
4031                         "Failed to notify smc display settings!",
4032                         result = tmp_result);
4033
4034         tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr);
4035         PP_ASSERT_WITH_CODE((0 == tmp_result),
4036                         "Failed to unfreeze SCLK MCLK DPM!",
4037                         result = tmp_result);
4038
4039         tmp_result = smu7_upload_dpm_level_enable_mask(hwmgr);
4040         PP_ASSERT_WITH_CODE((0 == tmp_result),
4041                         "Failed to upload DPM level enabled mask!",
4042                         result = tmp_result);
4043
4044         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4045                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4046                 tmp_result =
4047                         smu7_notify_link_speed_change_after_state_change(hwmgr, input);
4048                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4049                                 "Failed to notify link speed change after state change!",
4050                                 result = tmp_result);
4051         }
4052         data->apply_optimized_settings = false;
4053         return result;
4054 }
4055
4056 static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4057 {
4058         hwmgr->thermal_controller.
4059         advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4060
4061         return smum_send_msg_to_smc_with_parameter(hwmgr,
4062                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm,
4063                         NULL);
4064 }
4065
4066 static int
4067 smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4068 {
4069         PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4070
4071         return (smum_send_msg_to_smc(hwmgr, msg, NULL) == 0) ?  0 : -1;
4072 }
4073
4074 static int
4075 smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4076 {
4077         if (hwmgr->display_config->num_display > 1 &&
4078                         !hwmgr->display_config->multi_monitor_in_sync)
4079                 smu7_notify_smc_display_change(hwmgr, false);
4080
4081         return 0;
4082 }
4083
4084 /**
4085 * Programs the display gap
4086 *
4087 * @param    hwmgr  the address of the powerplay hardware manager.
4088 * @return   always OK
4089 */
4090 static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
4091 {
4092         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4093         uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4094         uint32_t display_gap2;
4095         uint32_t pre_vbi_time_in_us;
4096         uint32_t frame_time_in_us;
4097         uint32_t ref_clock, refresh_rate;
4098
4099         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4100         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4101
4102         ref_clock =  amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
4103         refresh_rate = hwmgr->display_config->vrefresh;
4104
4105         if (0 == refresh_rate)
4106                 refresh_rate = 60;
4107
4108         frame_time_in_us = 1000000 / refresh_rate;
4109
4110         pre_vbi_time_in_us = frame_time_in_us - 200 - hwmgr->display_config->min_vblank_time;
4111
4112         data->frame_time_x2 = frame_time_in_us * 2 / 100;
4113
4114         if (data->frame_time_x2 < 280) {
4115                 pr_debug("%s: enforce minimal VBITimeout: %d -> 280\n", __func__, data->frame_time_x2);
4116                 data->frame_time_x2 = 280;
4117         }
4118
4119         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4120
4121         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4122
4123         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4124                         data->soft_regs_start + smum_get_offsetof(hwmgr,
4125                                                         SMU_SoftRegisters,
4126                                                         PreVBlankGap), 0x64);
4127
4128         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4129                         data->soft_regs_start + smum_get_offsetof(hwmgr,
4130                                                         SMU_SoftRegisters,
4131                                                         VBlankTimeout),
4132                                         (frame_time_in_us - pre_vbi_time_in_us));
4133
4134         return 0;
4135 }
4136
4137 static int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4138 {
4139         return smu7_program_display_gap(hwmgr);
4140 }
4141
4142 /**
4143 *  Set maximum target operating fan output RPM
4144 *
4145 * @param    hwmgr:  the address of the powerplay hardware manager.
4146 * @param    usMaxFanRpm:  max operating fan RPM value.
4147 * @return   The response that came from the SMC.
4148 */
4149 static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4150 {
4151         hwmgr->thermal_controller.
4152         advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4153
4154         return smum_send_msg_to_smc_with_parameter(hwmgr,
4155                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm,
4156                         NULL);
4157 }
4158
4159 static const struct amdgpu_irq_src_funcs smu7_irq_funcs = {
4160         .process = phm_irq_process,
4161 };
4162
4163 static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr)
4164 {
4165         struct amdgpu_irq_src *source =
4166                 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
4167
4168         if (!source)
4169                 return -ENOMEM;
4170
4171         source->funcs = &smu7_irq_funcs;
4172
4173         amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
4174                         AMDGPU_IRQ_CLIENTID_LEGACY,
4175                         VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH,
4176                         source);
4177         amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
4178                         AMDGPU_IRQ_CLIENTID_LEGACY,
4179                         VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW,
4180                         source);
4181
4182         /* Register CTF(GPIO_19) interrupt */
4183         amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
4184                         AMDGPU_IRQ_CLIENTID_LEGACY,
4185                         VISLANDS30_IV_SRCID_GPIO_19,
4186                         source);
4187
4188         return 0;
4189 }
4190
4191 static bool
4192 smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4193 {
4194         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4195         bool is_update_required = false;
4196
4197         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4198                 is_update_required = true;
4199
4200         if (data->display_timing.vrefresh != hwmgr->display_config->vrefresh)
4201                 is_update_required = true;
4202
4203         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4204                 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr &&
4205                         (data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK ||
4206                         hwmgr->display_config->min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
4207                         is_update_required = true;
4208         }
4209         return is_update_required;
4210 }
4211
4212 static inline bool smu7_are_power_levels_equal(const struct smu7_performance_level *pl1,
4213                                                            const struct smu7_performance_level *pl2)
4214 {
4215         return ((pl1->memory_clock == pl2->memory_clock) &&
4216                   (pl1->engine_clock == pl2->engine_clock) &&
4217                   (pl1->pcie_gen == pl2->pcie_gen) &&
4218                   (pl1->pcie_lane == pl2->pcie_lane));
4219 }
4220
4221 static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
4222                 const struct pp_hw_power_state *pstate1,
4223                 const struct pp_hw_power_state *pstate2, bool *equal)
4224 {
4225         const struct smu7_power_state *psa;
4226         const struct smu7_power_state *psb;
4227         int i;
4228         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4229
4230         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4231                 return -EINVAL;
4232
4233         psa = cast_const_phw_smu7_power_state(pstate1);
4234         psb = cast_const_phw_smu7_power_state(pstate2);
4235         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4236         if (psa->performance_level_count != psb->performance_level_count) {
4237                 *equal = false;
4238                 return 0;
4239         }
4240
4241         for (i = 0; i < psa->performance_level_count; i++) {
4242                 if (!smu7_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4243                         /* If we have found even one performance level pair that is different the states are different. */
4244                         *equal = false;
4245                         return 0;
4246                 }
4247         }
4248
4249         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4250         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4251         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4252         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4253         /* For OD call, set value based on flag */
4254         *equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK |
4255                                                         DPMTABLE_OD_UPDATE_MCLK |
4256                                                         DPMTABLE_OD_UPDATE_VDDC));
4257
4258         return 0;
4259 }
4260
4261 static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr)
4262 {
4263         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4264
4265         uint32_t tmp;
4266
4267         /* Read MC indirect register offset 0x9F bits [3:0] to see
4268          * if VBIOS has already loaded a full version of MC ucode
4269          * or not.
4270          */
4271
4272         smu7_get_mc_microcode_version(hwmgr);
4273
4274         data->need_long_memory_training = false;
4275
4276         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX,
4277                                                         ixMC_IO_DEBUG_UP_13);
4278         tmp = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
4279
4280         if (tmp & (1 << 23)) {
4281                 data->mem_latency_high = MEM_LATENCY_HIGH;
4282                 data->mem_latency_low = MEM_LATENCY_LOW;
4283                 if ((hwmgr->chip_id == CHIP_POLARIS10) ||
4284                     (hwmgr->chip_id == CHIP_POLARIS11) ||
4285                     (hwmgr->chip_id == CHIP_POLARIS12))
4286                         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableFFC, NULL);
4287         } else {
4288                 data->mem_latency_high = 330;
4289                 data->mem_latency_low = 330;
4290                 if ((hwmgr->chip_id == CHIP_POLARIS10) ||
4291                     (hwmgr->chip_id == CHIP_POLARIS11) ||
4292                     (hwmgr->chip_id == CHIP_POLARIS12))
4293                         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableFFC, NULL);
4294         }
4295
4296         return 0;
4297 }
4298
4299 static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr)
4300 {
4301         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4302
4303         data->clock_registers.vCG_SPLL_FUNC_CNTL         =
4304                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
4305         data->clock_registers.vCG_SPLL_FUNC_CNTL_2       =
4306                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
4307         data->clock_registers.vCG_SPLL_FUNC_CNTL_3       =
4308                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
4309         data->clock_registers.vCG_SPLL_FUNC_CNTL_4       =
4310                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
4311         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM   =
4312                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
4313         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
4314                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
4315         data->clock_registers.vDLL_CNTL                  =
4316                 cgs_read_register(hwmgr->device, mmDLL_CNTL);
4317         data->clock_registers.vMCLK_PWRMGT_CNTL          =
4318                 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
4319         data->clock_registers.vMPLL_AD_FUNC_CNTL         =
4320                 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
4321         data->clock_registers.vMPLL_DQ_FUNC_CNTL         =
4322                 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
4323         data->clock_registers.vMPLL_FUNC_CNTL            =
4324                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
4325         data->clock_registers.vMPLL_FUNC_CNTL_1          =
4326                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
4327         data->clock_registers.vMPLL_FUNC_CNTL_2          =
4328                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
4329         data->clock_registers.vMPLL_SS1                  =
4330                 cgs_read_register(hwmgr->device, mmMPLL_SS1);
4331         data->clock_registers.vMPLL_SS2                  =
4332                 cgs_read_register(hwmgr->device, mmMPLL_SS2);
4333         return 0;
4334
4335 }
4336
4337 /**
4338  * Find out if memory is GDDR5.
4339  *
4340  * @param    hwmgr  the address of the powerplay hardware manager.
4341  * @return   always 0
4342  */
4343 static int smu7_get_memory_type(struct pp_hwmgr *hwmgr)
4344 {
4345         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4346         struct amdgpu_device *adev = hwmgr->adev;
4347
4348         data->is_memory_gddr5 = (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5);
4349
4350         return 0;
4351 }
4352
4353 /**
4354  * Enables Dynamic Power Management by SMC
4355  *
4356  * @param    hwmgr  the address of the powerplay hardware manager.
4357  * @return   always 0
4358  */
4359 static int smu7_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4360 {
4361         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4362                         GENERAL_PWRMGT, STATIC_PM_EN, 1);
4363
4364         return 0;
4365 }
4366
4367 /**
4368  * Initialize PowerGating States for different engines
4369  *
4370  * @param    hwmgr  the address of the powerplay hardware manager.
4371  * @return   always 0
4372  */
4373 static int smu7_init_power_gate_state(struct pp_hwmgr *hwmgr)
4374 {
4375         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4376
4377         data->uvd_power_gated = false;
4378         data->vce_power_gated = false;
4379
4380         return 0;
4381 }
4382
4383 static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4384 {
4385         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4386
4387         data->low_sclk_interrupt_threshold = 0;
4388         return 0;
4389 }
4390
4391 static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr)
4392 {
4393         int tmp_result, result = 0;
4394
4395         smu7_check_mc_firmware(hwmgr);
4396
4397         tmp_result = smu7_read_clock_registers(hwmgr);
4398         PP_ASSERT_WITH_CODE((0 == tmp_result),
4399                         "Failed to read clock registers!", result = tmp_result);
4400
4401         tmp_result = smu7_get_memory_type(hwmgr);
4402         PP_ASSERT_WITH_CODE((0 == tmp_result),
4403                         "Failed to get memory type!", result = tmp_result);
4404
4405         tmp_result = smu7_enable_acpi_power_management(hwmgr);
4406         PP_ASSERT_WITH_CODE((0 == tmp_result),
4407                         "Failed to enable ACPI power management!", result = tmp_result);
4408
4409         tmp_result = smu7_init_power_gate_state(hwmgr);
4410         PP_ASSERT_WITH_CODE((0 == tmp_result),
4411                         "Failed to init power gate state!", result = tmp_result);
4412
4413         tmp_result = smu7_get_mc_microcode_version(hwmgr);
4414         PP_ASSERT_WITH_CODE((0 == tmp_result),
4415                         "Failed to get MC microcode version!", result = tmp_result);
4416
4417         tmp_result = smu7_init_sclk_threshold(hwmgr);
4418         PP_ASSERT_WITH_CODE((0 == tmp_result),
4419                         "Failed to init sclk threshold!", result = tmp_result);
4420
4421         return result;
4422 }
4423
4424 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
4425                 enum pp_clock_type type, uint32_t mask)
4426 {
4427         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4428
4429         if (mask == 0)
4430                 return -EINVAL;
4431
4432         switch (type) {
4433         case PP_SCLK:
4434                 if (!data->sclk_dpm_key_disabled)
4435                         smum_send_msg_to_smc_with_parameter(hwmgr,
4436                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
4437                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask,
4438                                         NULL);
4439                 break;
4440         case PP_MCLK:
4441                 if (!data->mclk_dpm_key_disabled)
4442                         smum_send_msg_to_smc_with_parameter(hwmgr,
4443                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
4444                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask,
4445                                         NULL);
4446                 break;
4447         case PP_PCIE:
4448         {
4449                 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4450
4451                 if (!data->pcie_dpm_key_disabled) {
4452                         if (fls(tmp) != ffs(tmp))
4453                                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_UnForceLevel,
4454                                                 NULL);
4455                         else
4456                                 smum_send_msg_to_smc_with_parameter(hwmgr,
4457                                         PPSMC_MSG_PCIeDPM_ForceLevel,
4458                                         fls(tmp) - 1,
4459                                         NULL);
4460                 }
4461                 break;
4462         }
4463         default:
4464                 break;
4465         }
4466
4467         return 0;
4468 }
4469
4470 static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
4471                 enum pp_clock_type type, char *buf)
4472 {
4473         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4474         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4475         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4476         struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4477         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
4478         struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
4479         struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
4480         int i, now, size = 0;
4481         uint32_t clock, pcie_speed;
4482
4483         switch (type) {
4484         case PP_SCLK:
4485                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, &clock);
4486
4487                 for (i = 0; i < sclk_table->count; i++) {
4488                         if (clock > sclk_table->dpm_levels[i].value)
4489                                 continue;
4490                         break;
4491                 }
4492                 now = i;
4493
4494                 for (i = 0; i < sclk_table->count; i++)
4495                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4496                                         i, sclk_table->dpm_levels[i].value / 100,
4497                                         (i == now) ? "*" : "");
4498                 break;
4499         case PP_MCLK:
4500                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, &clock);
4501
4502                 for (i = 0; i < mclk_table->count; i++) {
4503                         if (clock > mclk_table->dpm_levels[i].value)
4504                                 continue;
4505                         break;
4506                 }
4507                 now = i;
4508
4509                 for (i = 0; i < mclk_table->count; i++)
4510                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4511                                         i, mclk_table->dpm_levels[i].value / 100,
4512                                         (i == now) ? "*" : "");
4513                 break;
4514         case PP_PCIE:
4515                 pcie_speed = smu7_get_current_pcie_speed(hwmgr);
4516                 for (i = 0; i < pcie_table->count; i++) {
4517                         if (pcie_speed != pcie_table->dpm_levels[i].value)
4518                                 continue;
4519                         break;
4520                 }
4521                 now = i;
4522
4523                 for (i = 0; i < pcie_table->count; i++)
4524                         size += sprintf(buf + size, "%d: %s %s\n", i,
4525                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" :
4526                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" :
4527                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
4528                                         (i == now) ? "*" : "");
4529                 break;
4530         case OD_SCLK:
4531                 if (hwmgr->od_enabled) {
4532                         size = sprintf(buf, "%s:\n", "OD_SCLK");
4533                         for (i = 0; i < odn_sclk_table->num_of_pl; i++)
4534                                 size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
4535                                         i, odn_sclk_table->entries[i].clock/100,
4536                                         odn_sclk_table->entries[i].vddc);
4537                 }
4538                 break;
4539         case OD_MCLK:
4540                 if (hwmgr->od_enabled) {
4541                         size = sprintf(buf, "%s:\n", "OD_MCLK");
4542                         for (i = 0; i < odn_mclk_table->num_of_pl; i++)
4543                                 size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
4544                                         i, odn_mclk_table->entries[i].clock/100,
4545                                         odn_mclk_table->entries[i].vddc);
4546                 }
4547                 break;
4548         case OD_RANGE:
4549                 if (hwmgr->od_enabled) {
4550                         size = sprintf(buf, "%s:\n", "OD_RANGE");
4551                         size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
4552                                 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100,
4553                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4554                         size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
4555                                 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100,
4556                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4557                         size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
4558                                 data->odn_dpm_table.min_vddc,
4559                                 data->odn_dpm_table.max_vddc);
4560                 }
4561                 break;
4562         default:
4563                 break;
4564         }
4565         return size;
4566 }
4567
4568 static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4569 {
4570         switch (mode) {
4571         case AMD_FAN_CTRL_NONE:
4572                 smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
4573                 break;
4574         case AMD_FAN_CTRL_MANUAL:
4575                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4576                         PHM_PlatformCaps_MicrocodeFanControl))
4577                         smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
4578                 break;
4579         case AMD_FAN_CTRL_AUTO:
4580                 if (!smu7_fan_ctrl_set_static_mode(hwmgr, mode))
4581                         smu7_fan_ctrl_start_smc_fan_control(hwmgr);
4582                 break;
4583         default:
4584                 break;
4585         }
4586 }
4587
4588 static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4589 {
4590         return hwmgr->fan_ctrl_enabled ? AMD_FAN_CTRL_AUTO : AMD_FAN_CTRL_MANUAL;
4591 }
4592
4593 static int smu7_get_sclk_od(struct pp_hwmgr *hwmgr)
4594 {
4595         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4596         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4597         struct smu7_single_dpm_table *golden_sclk_table =
4598                         &(data->golden_dpm_table.sclk_table);
4599         int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
4600         int golden_value = golden_sclk_table->dpm_levels
4601                         [golden_sclk_table->count - 1].value;
4602
4603         value -= golden_value;
4604         value = DIV_ROUND_UP(value * 100, golden_value);
4605
4606         return value;
4607 }
4608
4609 static int smu7_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4610 {
4611         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4612         struct smu7_single_dpm_table *golden_sclk_table =
4613                         &(data->golden_dpm_table.sclk_table);
4614         struct pp_power_state  *ps;
4615         struct smu7_power_state  *smu7_ps;
4616
4617         if (value > 20)
4618                 value = 20;
4619
4620         ps = hwmgr->request_ps;
4621
4622         if (ps == NULL)
4623                 return -EINVAL;
4624
4625         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
4626
4627         smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].engine_clock =
4628                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
4629                         value / 100 +
4630                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
4631
4632         return 0;
4633 }
4634
4635 static int smu7_get_mclk_od(struct pp_hwmgr *hwmgr)
4636 {
4637         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4638         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4639         struct smu7_single_dpm_table *golden_mclk_table =
4640                         &(data->golden_dpm_table.mclk_table);
4641         int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
4642         int golden_value = golden_mclk_table->dpm_levels
4643                         [golden_mclk_table->count - 1].value;
4644
4645         value -= golden_value;
4646         value = DIV_ROUND_UP(value * 100, golden_value);
4647
4648         return value;
4649 }
4650
4651 static int smu7_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4652 {
4653         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4654         struct smu7_single_dpm_table *golden_mclk_table =
4655                         &(data->golden_dpm_table.mclk_table);
4656         struct pp_power_state  *ps;
4657         struct smu7_power_state  *smu7_ps;
4658
4659         if (value > 20)
4660                 value = 20;
4661
4662         ps = hwmgr->request_ps;
4663
4664         if (ps == NULL)
4665                 return -EINVAL;
4666
4667         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
4668
4669         smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].memory_clock =
4670                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
4671                         value / 100 +
4672                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
4673
4674         return 0;
4675 }
4676
4677
4678 static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
4679 {
4680         struct phm_ppt_v1_information *table_info =
4681                         (struct phm_ppt_v1_information *)hwmgr->pptable;
4682         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = NULL;
4683         struct phm_clock_voltage_dependency_table *sclk_table;
4684         int i;
4685
4686         if (hwmgr->pp_table_version == PP_TABLE_V1) {
4687                 if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL)
4688                         return -EINVAL;
4689                 dep_sclk_table = table_info->vdd_dep_on_sclk;
4690                 for (i = 0; i < dep_sclk_table->count; i++)
4691                         clocks->clock[i] = dep_sclk_table->entries[i].clk * 10;
4692                 clocks->count = dep_sclk_table->count;
4693         } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
4694                 sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
4695                 for (i = 0; i < sclk_table->count; i++)
4696                         clocks->clock[i] = sclk_table->entries[i].clk * 10;
4697                 clocks->count = sclk_table->count;
4698         }
4699
4700         return 0;
4701 }
4702
4703 static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk)
4704 {
4705         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4706
4707         if (clk >= MEM_FREQ_LOW_LATENCY && clk < MEM_FREQ_HIGH_LATENCY)
4708                 return data->mem_latency_high;
4709         else if (clk >= MEM_FREQ_HIGH_LATENCY)
4710                 return data->mem_latency_low;
4711         else
4712                 return MEM_LATENCY_ERR;
4713 }
4714
4715 static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
4716 {
4717         struct phm_ppt_v1_information *table_info =
4718                         (struct phm_ppt_v1_information *)hwmgr->pptable;
4719         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
4720         int i;
4721         struct phm_clock_voltage_dependency_table *mclk_table;
4722
4723         if (hwmgr->pp_table_version == PP_TABLE_V1) {
4724                 if (table_info == NULL)
4725                         return -EINVAL;
4726                 dep_mclk_table = table_info->vdd_dep_on_mclk;
4727                 for (i = 0; i < dep_mclk_table->count; i++) {
4728                         clocks->clock[i] = dep_mclk_table->entries[i].clk * 10;
4729                         clocks->latency[i] = smu7_get_mem_latency(hwmgr,
4730                                                 dep_mclk_table->entries[i].clk);
4731                 }
4732                 clocks->count = dep_mclk_table->count;
4733         } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
4734                 mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
4735                 for (i = 0; i < mclk_table->count; i++)
4736                         clocks->clock[i] = mclk_table->entries[i].clk * 10;
4737                 clocks->count = mclk_table->count;
4738         }
4739         return 0;
4740 }
4741
4742 static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
4743                                                 struct amd_pp_clocks *clocks)
4744 {
4745         switch (type) {
4746         case amd_pp_sys_clock:
4747                 smu7_get_sclks(hwmgr, clocks);
4748                 break;
4749         case amd_pp_mem_clock:
4750                 smu7_get_mclks(hwmgr, clocks);
4751                 break;
4752         default:
4753                 return -EINVAL;
4754         }
4755
4756         return 0;
4757 }
4758
4759 static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
4760                                         uint32_t virtual_addr_low,
4761                                         uint32_t virtual_addr_hi,
4762                                         uint32_t mc_addr_low,
4763                                         uint32_t mc_addr_hi,
4764                                         uint32_t size)
4765 {
4766         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4767
4768         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4769                                         data->soft_regs_start +
4770                                         smum_get_offsetof(hwmgr,
4771                                         SMU_SoftRegisters, DRAM_LOG_ADDR_H),
4772                                         mc_addr_hi);
4773
4774         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4775                                         data->soft_regs_start +
4776                                         smum_get_offsetof(hwmgr,
4777                                         SMU_SoftRegisters, DRAM_LOG_ADDR_L),
4778                                         mc_addr_low);
4779
4780         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4781                                         data->soft_regs_start +
4782                                         smum_get_offsetof(hwmgr,
4783                                         SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_H),
4784                                         virtual_addr_hi);
4785
4786         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4787                                         data->soft_regs_start +
4788                                         smum_get_offsetof(hwmgr,
4789                                         SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_L),
4790                                         virtual_addr_low);
4791
4792         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4793                                         data->soft_regs_start +
4794                                         smum_get_offsetof(hwmgr,
4795                                         SMU_SoftRegisters, DRAM_LOG_BUFF_SIZE),
4796                                         size);
4797         return 0;
4798 }
4799
4800 static int smu7_get_max_high_clocks(struct pp_hwmgr *hwmgr,
4801                                         struct amd_pp_simple_clock_info *clocks)
4802 {
4803         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4804         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4805         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4806
4807         if (clocks == NULL)
4808                 return -EINVAL;
4809
4810         clocks->memory_max_clock = mclk_table->count > 1 ?
4811                                 mclk_table->dpm_levels[mclk_table->count-1].value :
4812                                 mclk_table->dpm_levels[0].value;
4813         clocks->engine_max_clock = sclk_table->count > 1 ?
4814                                 sclk_table->dpm_levels[sclk_table->count-1].value :
4815                                 sclk_table->dpm_levels[0].value;
4816         return 0;
4817 }
4818
4819 static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
4820                 struct PP_TemperatureRange *thermal_data)
4821 {
4822         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4823         struct phm_ppt_v1_information *table_info =
4824                         (struct phm_ppt_v1_information *)hwmgr->pptable;
4825
4826         memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange));
4827
4828         if (hwmgr->pp_table_version == PP_TABLE_V1)
4829                 thermal_data->max = table_info->cac_dtp_table->usSoftwareShutdownTemp *
4830                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4831         else if (hwmgr->pp_table_version == PP_TABLE_V0)
4832                 thermal_data->max = data->thermal_temp_setting.temperature_shutdown *
4833                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4834
4835         return 0;
4836 }
4837
4838 static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
4839                                         enum PP_OD_DPM_TABLE_COMMAND type,
4840                                         uint32_t clk,
4841                                         uint32_t voltage)
4842 {
4843         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4844
4845         if (voltage < data->odn_dpm_table.min_vddc || voltage > data->odn_dpm_table.max_vddc) {
4846                 pr_info("OD voltage is out of range [%d - %d] mV\n",
4847                                                 data->odn_dpm_table.min_vddc,
4848                                                 data->odn_dpm_table.max_vddc);
4849                 return false;
4850         }
4851
4852         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
4853                 if (data->golden_dpm_table.sclk_table.dpm_levels[0].value > clk ||
4854                         hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
4855                         pr_info("OD engine clock is out of range [%d - %d] MHz\n",
4856                                 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100,
4857                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4858                         return false;
4859                 }
4860         } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
4861                 if (data->golden_dpm_table.mclk_table.dpm_levels[0].value > clk ||
4862                         hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
4863                         pr_info("OD memory clock is out of range [%d - %d] MHz\n",
4864                                 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100,
4865                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4866                         return false;
4867                 }
4868         } else {
4869                 return false;
4870         }
4871
4872         return true;
4873 }
4874
4875 static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
4876                                         enum PP_OD_DPM_TABLE_COMMAND type,
4877                                         long *input, uint32_t size)
4878 {
4879         uint32_t i;
4880         struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL;
4881         struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL;
4882         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4883
4884         uint32_t input_clk;
4885         uint32_t input_vol;
4886         uint32_t input_level;
4887
4888         PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
4889                                 return -EINVAL);
4890
4891         if (!hwmgr->od_enabled) {
4892                 pr_info("OverDrive feature not enabled\n");
4893                 return -EINVAL;
4894         }
4895
4896         if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
4897                 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels;
4898                 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk;
4899                 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
4900                                 "Failed to get ODN SCLK and Voltage tables",
4901                                 return -EINVAL);
4902         } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
4903                 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels;
4904                 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk;
4905
4906                 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
4907                         "Failed to get ODN MCLK and Voltage tables",
4908                         return -EINVAL);
4909         } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
4910                 smu7_odn_initial_default_setting(hwmgr);
4911                 return 0;
4912         } else if (PP_OD_COMMIT_DPM_TABLE == type) {
4913                 smu7_check_dpm_table_updated(hwmgr);
4914                 return 0;
4915         } else {
4916                 return -EINVAL;
4917         }
4918
4919         for (i = 0; i < size; i += 3) {
4920                 if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) {
4921                         pr_info("invalid clock voltage input \n");
4922                         return 0;
4923                 }
4924                 input_level = input[i];
4925                 input_clk = input[i+1] * 100;
4926                 input_vol = input[i+2];
4927
4928                 if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
4929                         podn_dpm_table_in_backend->entries[input_level].clock = input_clk;
4930                         podn_vdd_dep_in_backend->entries[input_level].clk = input_clk;
4931                         podn_dpm_table_in_backend->entries[input_level].vddc = input_vol;
4932                         podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol;
4933                         podn_vdd_dep_in_backend->entries[input_level].vddgfx = input_vol;
4934                 } else {
4935                         return -EINVAL;
4936                 }
4937         }
4938
4939         return 0;
4940 }
4941
4942 static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
4943 {
4944         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4945         uint32_t i, size = 0;
4946         uint32_t len;
4947
4948         static const char *profile_name[7] = {"BOOTUP_DEFAULT",
4949                                         "3D_FULL_SCREEN",
4950                                         "POWER_SAVING",
4951                                         "VIDEO",
4952                                         "VR",
4953                                         "COMPUTE",
4954                                         "CUSTOM"};
4955
4956         static const char *title[8] = {"NUM",
4957                         "MODE_NAME",
4958                         "SCLK_UP_HYST",
4959                         "SCLK_DOWN_HYST",
4960                         "SCLK_ACTIVE_LEVEL",
4961                         "MCLK_UP_HYST",
4962                         "MCLK_DOWN_HYST",
4963                         "MCLK_ACTIVE_LEVEL"};
4964
4965         if (!buf)
4966                 return -EINVAL;
4967
4968         size += sprintf(buf + size, "%s %16s %16s %16s %16s %16s %16s %16s\n",
4969                         title[0], title[1], title[2], title[3],
4970                         title[4], title[5], title[6], title[7]);
4971
4972         len = ARRAY_SIZE(smu7_profiling);
4973
4974         for (i = 0; i < len; i++) {
4975                 if (i == hwmgr->power_profile_mode) {
4976                         size += sprintf(buf + size, "%3d %14s %s: %8d %16d %16d %16d %16d %16d\n",
4977                         i, profile_name[i], "*",
4978                         data->current_profile_setting.sclk_up_hyst,
4979                         data->current_profile_setting.sclk_down_hyst,
4980                         data->current_profile_setting.sclk_activity,
4981                         data->current_profile_setting.mclk_up_hyst,
4982                         data->current_profile_setting.mclk_down_hyst,
4983                         data->current_profile_setting.mclk_activity);
4984                         continue;
4985                 }
4986                 if (smu7_profiling[i].bupdate_sclk)
4987                         size += sprintf(buf + size, "%3d %16s: %8d %16d %16d ",
4988                         i, profile_name[i], smu7_profiling[i].sclk_up_hyst,
4989                         smu7_profiling[i].sclk_down_hyst,
4990                         smu7_profiling[i].sclk_activity);
4991                 else
4992                         size += sprintf(buf + size, "%3d %16s: %8s %16s %16s ",
4993                         i, profile_name[i], "-", "-", "-");
4994
4995                 if (smu7_profiling[i].bupdate_mclk)
4996                         size += sprintf(buf + size, "%16d %16d %16d\n",
4997                         smu7_profiling[i].mclk_up_hyst,
4998                         smu7_profiling[i].mclk_down_hyst,
4999                         smu7_profiling[i].mclk_activity);
5000                 else
5001                         size += sprintf(buf + size, "%16s %16s %16s\n",
5002                         "-", "-", "-");
5003         }
5004
5005         return size;
5006 }
5007
5008 static void smu7_patch_compute_profile_mode(struct pp_hwmgr *hwmgr,
5009                                         enum PP_SMC_POWER_PROFILE requst)
5010 {
5011         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5012         uint32_t tmp, level;
5013
5014         if (requst == PP_SMC_POWER_PROFILE_COMPUTE) {
5015                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
5016                         level = 0;
5017                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
5018                         while (tmp >>= 1)
5019                                 level++;
5020                         if (level > 0)
5021                                 smu7_force_clock_level(hwmgr, PP_SCLK, 3 << (level-1));
5022                 }
5023         } else if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) {
5024                 smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask);
5025         }
5026 }
5027
5028 static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
5029 {
5030         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5031         struct profile_mode_setting tmp;
5032         enum PP_SMC_POWER_PROFILE mode;
5033
5034         if (input == NULL)
5035                 return -EINVAL;
5036
5037         mode = input[size];
5038         switch (mode) {
5039         case PP_SMC_POWER_PROFILE_CUSTOM:
5040                 if (size < 8 && size != 0)
5041                         return -EINVAL;
5042                 /* If only CUSTOM is passed in, use the saved values. Check
5043                  * that we actually have a CUSTOM profile by ensuring that
5044                  * the "use sclk" or the "use mclk" bits are set
5045                  */
5046                 tmp = smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM];
5047                 if (size == 0) {
5048                         if (tmp.bupdate_sclk == 0 && tmp.bupdate_mclk == 0)
5049                                 return -EINVAL;
5050                 } else {
5051                         tmp.bupdate_sclk = input[0];
5052                         tmp.sclk_up_hyst = input[1];
5053                         tmp.sclk_down_hyst = input[2];
5054                         tmp.sclk_activity = input[3];
5055                         tmp.bupdate_mclk = input[4];
5056                         tmp.mclk_up_hyst = input[5];
5057                         tmp.mclk_down_hyst = input[6];
5058                         tmp.mclk_activity = input[7];
5059                         smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM] = tmp;
5060                 }
5061                 if (!smum_update_dpm_settings(hwmgr, &tmp)) {
5062                         memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting));
5063                         hwmgr->power_profile_mode = mode;
5064                 }
5065                 break;
5066         case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
5067         case PP_SMC_POWER_PROFILE_POWERSAVING:
5068         case PP_SMC_POWER_PROFILE_VIDEO:
5069         case PP_SMC_POWER_PROFILE_VR:
5070         case PP_SMC_POWER_PROFILE_COMPUTE:
5071                 if (mode == hwmgr->power_profile_mode)
5072                         return 0;
5073
5074                 memcpy(&tmp, &smu7_profiling[mode], sizeof(struct profile_mode_setting));
5075                 if (!smum_update_dpm_settings(hwmgr, &tmp)) {
5076                         if (tmp.bupdate_sclk) {
5077                                 data->current_profile_setting.bupdate_sclk = tmp.bupdate_sclk;
5078                                 data->current_profile_setting.sclk_up_hyst = tmp.sclk_up_hyst;
5079                                 data->current_profile_setting.sclk_down_hyst = tmp.sclk_down_hyst;
5080                                 data->current_profile_setting.sclk_activity = tmp.sclk_activity;
5081                         }
5082                         if (tmp.bupdate_mclk) {
5083                                 data->current_profile_setting.bupdate_mclk = tmp.bupdate_mclk;
5084                                 data->current_profile_setting.mclk_up_hyst = tmp.mclk_up_hyst;
5085                                 data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst;
5086                                 data->current_profile_setting.mclk_activity = tmp.mclk_activity;
5087                         }
5088                         smu7_patch_compute_profile_mode(hwmgr, mode);
5089                         hwmgr->power_profile_mode = mode;
5090                 }
5091                 break;
5092         default:
5093                 return -EINVAL;
5094         }
5095
5096         return 0;
5097 }
5098
5099 static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
5100                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
5101                                 PHM_PerformanceLevel *level)
5102 {
5103         const struct smu7_power_state *ps;
5104         uint32_t i;
5105
5106         if (level == NULL || hwmgr == NULL || state == NULL)
5107                 return -EINVAL;
5108
5109         ps = cast_const_phw_smu7_power_state(state);
5110
5111         i = index > ps->performance_level_count - 1 ?
5112                         ps->performance_level_count - 1 : index;
5113
5114         level->coreClock = ps->performance_levels[i].engine_clock;
5115         level->memory_clock = ps->performance_levels[i].memory_clock;
5116
5117         return 0;
5118 }
5119
5120 static int smu7_power_off_asic(struct pp_hwmgr *hwmgr)
5121 {
5122         int result;
5123
5124         result = smu7_disable_dpm_tasks(hwmgr);
5125         PP_ASSERT_WITH_CODE((0 == result),
5126                         "[disable_dpm_tasks] Failed to disable DPM!",
5127                         );
5128
5129         return result;
5130 }
5131
5132 static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
5133         .backend_init = &smu7_hwmgr_backend_init,
5134         .backend_fini = &smu7_hwmgr_backend_fini,
5135         .asic_setup = &smu7_setup_asic_task,
5136         .dynamic_state_management_enable = &smu7_enable_dpm_tasks,
5137         .apply_state_adjust_rules = smu7_apply_state_adjust_rules,
5138         .force_dpm_level = &smu7_force_dpm_level,
5139         .power_state_set = smu7_set_power_state_tasks,
5140         .get_power_state_size = smu7_get_power_state_size,
5141         .get_mclk = smu7_dpm_get_mclk,
5142         .get_sclk = smu7_dpm_get_sclk,
5143         .patch_boot_state = smu7_dpm_patch_boot_state,
5144         .get_pp_table_entry = smu7_get_pp_table_entry,
5145         .get_num_of_pp_table_entries = smu7_get_number_of_powerplay_table_entries,
5146         .powerdown_uvd = smu7_powerdown_uvd,
5147         .powergate_uvd = smu7_powergate_uvd,
5148         .powergate_vce = smu7_powergate_vce,
5149         .disable_clock_power_gating = smu7_disable_clock_power_gating,
5150         .update_clock_gatings = smu7_update_clock_gatings,
5151         .notify_smc_display_config_after_ps_adjustment = smu7_notify_smc_display_config_after_ps_adjustment,
5152         .display_config_changed = smu7_display_configuration_changed_task,
5153         .set_max_fan_pwm_output = smu7_set_max_fan_pwm_output,
5154         .set_max_fan_rpm_output = smu7_set_max_fan_rpm_output,
5155         .stop_thermal_controller = smu7_thermal_stop_thermal_controller,
5156         .get_fan_speed_info = smu7_fan_ctrl_get_fan_speed_info,
5157         .get_fan_speed_percent = smu7_fan_ctrl_get_fan_speed_percent,
5158         .set_fan_speed_percent = smu7_fan_ctrl_set_fan_speed_percent,
5159         .reset_fan_speed_to_default = smu7_fan_ctrl_reset_fan_speed_to_default,
5160         .get_fan_speed_rpm = smu7_fan_ctrl_get_fan_speed_rpm,
5161         .set_fan_speed_rpm = smu7_fan_ctrl_set_fan_speed_rpm,
5162         .uninitialize_thermal_controller = smu7_thermal_ctrl_uninitialize_thermal_controller,
5163         .register_irq_handlers = smu7_register_irq_handlers,
5164         .check_smc_update_required_for_display_configuration = smu7_check_smc_update_required_for_display_configuration,
5165         .check_states_equal = smu7_check_states_equal,
5166         .set_fan_control_mode = smu7_set_fan_control_mode,
5167         .get_fan_control_mode = smu7_get_fan_control_mode,
5168         .force_clock_level = smu7_force_clock_level,
5169         .print_clock_levels = smu7_print_clock_levels,
5170         .powergate_gfx = smu7_powergate_gfx,
5171         .get_sclk_od = smu7_get_sclk_od,
5172         .set_sclk_od = smu7_set_sclk_od,
5173         .get_mclk_od = smu7_get_mclk_od,
5174         .set_mclk_od = smu7_set_mclk_od,
5175         .get_clock_by_type = smu7_get_clock_by_type,
5176         .read_sensor = smu7_read_sensor,
5177         .dynamic_state_management_disable = smu7_disable_dpm_tasks,
5178         .avfs_control = smu7_avfs_control,
5179         .disable_smc_firmware_ctf = smu7_thermal_disable_alert,
5180         .start_thermal_controller = smu7_start_thermal_controller,
5181         .notify_cac_buffer_info = smu7_notify_cac_buffer_info,
5182         .get_max_high_clocks = smu7_get_max_high_clocks,
5183         .get_thermal_temperature_range = smu7_get_thermal_temperature_range,
5184         .odn_edit_dpm_table = smu7_odn_edit_dpm_table,
5185         .set_power_limit = smu7_set_power_limit,
5186         .get_power_profile_mode = smu7_get_power_profile_mode,
5187         .set_power_profile_mode = smu7_set_power_profile_mode,
5188         .get_performance_level = smu7_get_performance_level,
5189         .get_asic_baco_capability = smu7_baco_get_capability,
5190         .get_asic_baco_state = smu7_baco_get_state,
5191         .set_asic_baco_state = smu7_baco_set_state,
5192         .power_off_asic = smu7_power_off_asic,
5193 };
5194
5195 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
5196                 uint32_t clock_insr)
5197 {
5198         uint8_t i;
5199         uint32_t temp;
5200         uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK);
5201
5202         PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);
5203         for (i = SMU7_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
5204                 temp = clock >> i;
5205
5206                 if (temp >= min || i == 0)
5207                         break;
5208         }
5209         return i;
5210 }
5211
5212 int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)
5213 {
5214         hwmgr->hwmgr_func = &smu7_hwmgr_funcs;
5215         if (hwmgr->pp_table_version == PP_TABLE_V0)
5216                 hwmgr->pptable_func = &pptable_funcs;
5217         else if (hwmgr->pp_table_version == PP_TABLE_V1)
5218                 hwmgr->pptable_func = &pptable_v1_0_funcs;
5219
5220         return 0;
5221 }