2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
27 #include "processpptables.h"
28 #include <atom-types.h>
31 #include "power_state.h"
33 #include "hardwaremanager.h"
36 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
37 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
38 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
39 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
40 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
41 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
42 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V8 24
43 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V9 26
45 #define NUM_BITS_CLOCK_INFO_ARRAY_INDEX 6
47 static uint16_t get_vce_table_offset(struct pp_hwmgr *hwmgr,
48 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
50 uint16_t vce_table_offset = 0;
52 if (le16_to_cpu(powerplay_table->usTableSize) >=
53 sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) {
54 const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 =
55 (const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table;
57 if (powerplay_table3->usExtendendedHeaderOffset > 0) {
58 const ATOM_PPLIB_EXTENDEDHEADER *extended_header =
59 (const ATOM_PPLIB_EXTENDEDHEADER *)
60 (((unsigned long)powerplay_table3) +
61 le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset));
62 if (le16_to_cpu(extended_header->usSize) >=
63 SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2)
64 vce_table_offset = le16_to_cpu(extended_header->usVCETableOffset);
68 return vce_table_offset;
71 static uint16_t get_vce_clock_info_array_offset(struct pp_hwmgr *hwmgr,
72 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
74 uint16_t table_offset = get_vce_table_offset(hwmgr,
78 return table_offset + 1;
83 static uint16_t get_vce_clock_info_array_size(struct pp_hwmgr *hwmgr,
84 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
86 uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr,
88 uint16_t table_size = 0;
90 if (table_offset > 0) {
91 const VCEClockInfoArray *p = (const VCEClockInfoArray *)
92 (((unsigned long) powerplay_table) + table_offset);
93 table_size = sizeof(uint8_t) + p->ucNumEntries * sizeof(VCEClockInfo);
99 static uint16_t get_vce_clock_voltage_limit_table_offset(struct pp_hwmgr *hwmgr,
100 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
102 uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr,
105 if (table_offset > 0)
106 return table_offset + get_vce_clock_info_array_size(hwmgr,
112 static uint16_t get_vce_clock_voltage_limit_table_size(struct pp_hwmgr *hwmgr,
113 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
115 uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table);
116 uint16_t table_size = 0;
118 if (table_offset > 0) {
119 const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *ptable =
120 (const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *)(((unsigned long) powerplay_table) + table_offset);
122 table_size = sizeof(uint8_t) + ptable->numEntries * sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record);
127 static uint16_t get_vce_state_table_offset(struct pp_hwmgr *hwmgr, const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
129 uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table);
131 if (table_offset > 0)
132 return table_offset + get_vce_clock_voltage_limit_table_size(hwmgr, powerplay_table);
137 static const ATOM_PPLIB_VCE_State_Table *get_vce_state_table(
138 struct pp_hwmgr *hwmgr,
139 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
141 uint16_t table_offset = get_vce_state_table_offset(hwmgr, powerplay_table);
143 if (table_offset > 0)
144 return (const ATOM_PPLIB_VCE_State_Table *)(((unsigned long) powerplay_table) + table_offset);
149 static uint16_t get_uvd_table_offset(struct pp_hwmgr *hwmgr,
150 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
152 uint16_t uvd_table_offset = 0;
154 if (le16_to_cpu(powerplay_table->usTableSize) >=
155 sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) {
156 const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 =
157 (const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table;
158 if (powerplay_table3->usExtendendedHeaderOffset > 0) {
159 const ATOM_PPLIB_EXTENDEDHEADER *extended_header =
160 (const ATOM_PPLIB_EXTENDEDHEADER *)
161 (((unsigned long)powerplay_table3) +
162 le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset));
163 if (le16_to_cpu(extended_header->usSize) >=
164 SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3)
165 uvd_table_offset = le16_to_cpu(extended_header->usUVDTableOffset);
168 return uvd_table_offset;
171 static uint16_t get_uvd_clock_info_array_offset(struct pp_hwmgr *hwmgr,
172 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
174 uint16_t table_offset = get_uvd_table_offset(hwmgr,
177 if (table_offset > 0)
178 return table_offset + 1;
182 static uint16_t get_uvd_clock_info_array_size(struct pp_hwmgr *hwmgr,
183 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
185 uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr,
187 uint16_t table_size = 0;
189 if (table_offset > 0) {
190 const UVDClockInfoArray *p = (const UVDClockInfoArray *)
191 (((unsigned long) powerplay_table)
193 table_size = sizeof(UCHAR) +
194 p->ucNumEntries * sizeof(UVDClockInfo);
200 static uint16_t get_uvd_clock_voltage_limit_table_offset(
201 struct pp_hwmgr *hwmgr,
202 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
204 uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr,
207 if (table_offset > 0)
208 return table_offset +
209 get_uvd_clock_info_array_size(hwmgr, powerplay_table);
214 static uint16_t get_samu_table_offset(struct pp_hwmgr *hwmgr,
215 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
217 uint16_t samu_table_offset = 0;
219 if (le16_to_cpu(powerplay_table->usTableSize) >=
220 sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) {
221 const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 =
222 (const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table;
223 if (powerplay_table3->usExtendendedHeaderOffset > 0) {
224 const ATOM_PPLIB_EXTENDEDHEADER *extended_header =
225 (const ATOM_PPLIB_EXTENDEDHEADER *)
226 (((unsigned long)powerplay_table3) +
227 le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset));
228 if (le16_to_cpu(extended_header->usSize) >=
229 SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4)
230 samu_table_offset = le16_to_cpu(extended_header->usSAMUTableOffset);
234 return samu_table_offset;
237 static uint16_t get_samu_clock_voltage_limit_table_offset(
238 struct pp_hwmgr *hwmgr,
239 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
241 uint16_t table_offset = get_samu_table_offset(hwmgr,
244 if (table_offset > 0)
245 return table_offset + 1;
250 static uint16_t get_acp_table_offset(struct pp_hwmgr *hwmgr,
251 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
253 uint16_t acp_table_offset = 0;
255 if (le16_to_cpu(powerplay_table->usTableSize) >=
256 sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) {
257 const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 =
258 (const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table;
259 if (powerplay_table3->usExtendendedHeaderOffset > 0) {
260 const ATOM_PPLIB_EXTENDEDHEADER *pExtendedHeader =
261 (const ATOM_PPLIB_EXTENDEDHEADER *)
262 (((unsigned long)powerplay_table3) +
263 le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset));
264 if (le16_to_cpu(pExtendedHeader->usSize) >=
265 SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6)
266 acp_table_offset = le16_to_cpu(pExtendedHeader->usACPTableOffset);
270 return acp_table_offset;
273 static uint16_t get_acp_clock_voltage_limit_table_offset(
274 struct pp_hwmgr *hwmgr,
275 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
277 uint16_t tableOffset = get_acp_table_offset(hwmgr, powerplay_table);
280 return tableOffset + 1;
285 static uint16_t get_cacp_tdp_table_offset(
286 struct pp_hwmgr *hwmgr,
287 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
289 uint16_t cacTdpTableOffset = 0;
291 if (le16_to_cpu(powerplay_table->usTableSize) >=
292 sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) {
293 const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 =
294 (const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table;
295 if (powerplay_table3->usExtendendedHeaderOffset > 0) {
296 const ATOM_PPLIB_EXTENDEDHEADER *pExtendedHeader =
297 (const ATOM_PPLIB_EXTENDEDHEADER *)
298 (((unsigned long)powerplay_table3) +
299 le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset));
300 if (le16_to_cpu(pExtendedHeader->usSize) >=
301 SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7)
302 cacTdpTableOffset = le16_to_cpu(pExtendedHeader->usPowerTuneTableOffset);
306 return cacTdpTableOffset;
309 static int get_cac_tdp_table(struct pp_hwmgr *hwmgr,
310 struct phm_cac_tdp_table **ptable,
311 const ATOM_PowerTune_Table *table,
312 uint16_t us_maximum_power_delivery_limit)
314 unsigned long table_size;
315 struct phm_cac_tdp_table *tdp_table;
317 table_size = sizeof(unsigned long) + sizeof(struct phm_cac_tdp_table);
319 tdp_table = kzalloc(table_size, GFP_KERNEL);
320 if (NULL == tdp_table)
323 tdp_table->usTDP = le16_to_cpu(table->usTDP);
324 tdp_table->usConfigurableTDP = le16_to_cpu(table->usConfigurableTDP);
325 tdp_table->usTDC = le16_to_cpu(table->usTDC);
326 tdp_table->usBatteryPowerLimit = le16_to_cpu(table->usBatteryPowerLimit);
327 tdp_table->usSmallPowerLimit = le16_to_cpu(table->usSmallPowerLimit);
328 tdp_table->usLowCACLeakage = le16_to_cpu(table->usLowCACLeakage);
329 tdp_table->usHighCACLeakage = le16_to_cpu(table->usHighCACLeakage);
330 tdp_table->usMaximumPowerDeliveryLimit = us_maximum_power_delivery_limit;
337 static uint16_t get_sclk_vdd_gfx_table_offset(struct pp_hwmgr *hwmgr,
338 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
340 uint16_t sclk_vdd_gfx_table_offset = 0;
342 if (le16_to_cpu(powerplay_table->usTableSize) >=
343 sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) {
344 const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 =
345 (const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table;
346 if (powerplay_table3->usExtendendedHeaderOffset > 0) {
347 const ATOM_PPLIB_EXTENDEDHEADER *pExtendedHeader =
348 (const ATOM_PPLIB_EXTENDEDHEADER *)
349 (((unsigned long)powerplay_table3) +
350 le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset));
351 if (le16_to_cpu(pExtendedHeader->usSize) >=
352 SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V8)
353 sclk_vdd_gfx_table_offset =
354 le16_to_cpu(pExtendedHeader->usSclkVddgfxTableOffset);
358 return sclk_vdd_gfx_table_offset;
361 static uint16_t get_sclk_vdd_gfx_clock_voltage_dependency_table_offset(
362 struct pp_hwmgr *hwmgr,
363 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
365 uint16_t tableOffset = get_sclk_vdd_gfx_table_offset(hwmgr, powerplay_table);
374 static int get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
375 struct phm_clock_voltage_dependency_table **ptable,
376 const ATOM_PPLIB_Clock_Voltage_Dependency_Table *table)
379 unsigned long table_size, i;
380 struct phm_clock_voltage_dependency_table *dep_table;
382 table_size = sizeof(unsigned long) +
383 sizeof(struct phm_clock_voltage_dependency_table)
384 * table->ucNumEntries;
386 dep_table = kzalloc(table_size, GFP_KERNEL);
387 if (NULL == dep_table)
390 dep_table->count = (unsigned long)table->ucNumEntries;
392 for (i = 0; i < dep_table->count; i++) {
393 dep_table->entries[i].clk =
394 ((unsigned long)table->entries[i].ucClockHigh << 16) |
395 le16_to_cpu(table->entries[i].usClockLow);
396 dep_table->entries[i].v =
397 (unsigned long)le16_to_cpu(table->entries[i].usVoltage);
405 static int get_valid_clk(struct pp_hwmgr *hwmgr,
406 struct phm_clock_array **ptable,
407 const struct phm_clock_voltage_dependency_table *table)
409 unsigned long table_size, i;
410 struct phm_clock_array *clock_table;
412 table_size = sizeof(unsigned long) + sizeof(unsigned long) * table->count;
413 clock_table = kzalloc(table_size, GFP_KERNEL);
414 if (NULL == clock_table)
417 clock_table->count = (unsigned long)table->count;
419 for (i = 0; i < clock_table->count; i++)
420 clock_table->values[i] = (unsigned long)table->entries[i].clk;
422 *ptable = clock_table;
427 static int get_clock_voltage_limit(struct pp_hwmgr *hwmgr,
428 struct phm_clock_and_voltage_limits *limits,
429 const ATOM_PPLIB_Clock_Voltage_Limit_Table *table)
431 limits->sclk = ((unsigned long)table->entries[0].ucSclkHigh << 16) |
432 le16_to_cpu(table->entries[0].usSclkLow);
433 limits->mclk = ((unsigned long)table->entries[0].ucMclkHigh << 16) |
434 le16_to_cpu(table->entries[0].usMclkLow);
435 limits->vddc = (unsigned long)le16_to_cpu(table->entries[0].usVddc);
436 limits->vddci = (unsigned long)le16_to_cpu(table->entries[0].usVddci);
442 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
443 enum phm_platform_caps cap)
446 phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
448 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
451 static int set_platform_caps(struct pp_hwmgr *hwmgr,
452 unsigned long powerplay_caps)
456 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_POWERPLAY),
457 PHM_PlatformCaps_PowerPlaySupport
462 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE),
463 PHM_PlatformCaps_BiosPowerSourceControl
468 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s),
469 PHM_PlatformCaps_EnableASPML0s
474 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1),
475 PHM_PlatformCaps_EnableASPML1
480 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS),
481 PHM_PlatformCaps_EnableBackbias
486 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC),
487 PHM_PlatformCaps_AutomaticDCTransition
492 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY),
493 PHM_PlatformCaps_GeminiPrimary
498 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC),
499 PHM_PlatformCaps_StepVddc
504 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL),
505 PHM_PlatformCaps_EnableVoltageControl
510 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL),
511 PHM_PlatformCaps_EnableSideportControl
516 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1),
517 PHM_PlatformCaps_TurnOffPll_ASPML1
522 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_HTLINKCONTROL),
523 PHM_PlatformCaps_EnableHTLinkControl
528 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL),
529 PHM_PlatformCaps_EnableMVDDControl
534 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL),
535 PHM_PlatformCaps_ControlVDDCI
540 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT),
541 PHM_PlatformCaps_RegulatorHot
546 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT),
547 PHM_PlatformCaps_BootStateOnAlert
552 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT),
553 PHM_PlatformCaps_DontWaitForVBlankOnAlert
558 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_BACO),
559 PHM_PlatformCaps_BACO
564 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE),
565 PHM_PlatformCaps_NewCACVoltage
570 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY),
571 PHM_PlatformCaps_RevertGPIO5Polarity
576 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17),
577 PHM_PlatformCaps_Thermal2GPIO17
582 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE),
583 PHM_PlatformCaps_VRHotGPIOConfigurable
588 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_TEMP_INVERSION),
589 PHM_PlatformCaps_TempInversion
594 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_EVV),
600 0 != (powerplay_caps & ATOM_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL),
601 PHM_PlatformCaps_CombinePCCWithThermalSignal
606 0 != (powerplay_caps & ATOM_PP_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE),
607 PHM_PlatformCaps_LoadPostProductionFirmware
612 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_DISABLE_USING_ACTUAL_TEMPERATURE_FOR_POWER_CALC),
613 PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc
619 static PP_StateClassificationFlags make_classification_flags(
620 struct pp_hwmgr *hwmgr,
621 USHORT classification,
622 USHORT classification2)
624 PP_StateClassificationFlags result = 0;
626 if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT)
627 result |= PP_StateClassificationFlag_Boot;
629 if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL)
630 result |= PP_StateClassificationFlag_Thermal;
633 ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
634 result |= PP_StateClassificationFlag_LimitedPowerSource;
636 if (classification & ATOM_PPLIB_CLASSIFICATION_REST)
637 result |= PP_StateClassificationFlag_Rest;
639 if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED)
640 result |= PP_StateClassificationFlag_Forced;
642 if (classification & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
643 result |= PP_StateClassificationFlag_3DPerformance;
646 if (classification & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE)
647 result |= PP_StateClassificationFlag_ACOverdriveTemplate;
649 if (classification & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
650 result |= PP_StateClassificationFlag_Uvd;
652 if (classification & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
653 result |= PP_StateClassificationFlag_UvdHD;
655 if (classification & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
656 result |= PP_StateClassificationFlag_UvdSD;
658 if (classification & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
659 result |= PP_StateClassificationFlag_HD2;
661 if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI)
662 result |= PP_StateClassificationFlag_ACPI;
664 if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
665 result |= PP_StateClassificationFlag_LimitedPowerSource_2;
668 if (classification2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
669 result |= PP_StateClassificationFlag_ULV;
671 if (classification2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
672 result |= PP_StateClassificationFlag_UvdMVC;
677 static int init_non_clock_fields(struct pp_hwmgr *hwmgr,
678 struct pp_power_state *ps,
680 const ATOM_PPLIB_NONCLOCK_INFO *pnon_clock_info) {
681 unsigned long rrr_index;
684 ps->classification.ui_label = (le16_to_cpu(pnon_clock_info->usClassification) &
685 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
686 ps->classification.flags = make_classification_flags(hwmgr,
687 le16_to_cpu(pnon_clock_info->usClassification),
688 le16_to_cpu(pnon_clock_info->usClassification2));
690 ps->classification.temporary_state = false;
691 ps->classification.to_be_deleted = false;
692 tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
693 ATOM_PPLIB_SINGLE_DISPLAY_ONLY;
695 ps->validation.singleDisplayOnly = (0 != tmp);
697 tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
698 ATOM_PPLIB_DISALLOW_ON_DC;
700 ps->validation.disallowOnDC = (0 != tmp);
702 ps->pcie.lanes = ((le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
703 ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
704 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
708 ps->display.disableFrameModulation = false;
710 rrr_index = (le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
711 ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK) >>
712 ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT;
714 if (rrr_index != ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED) {
715 static const uint8_t look_up[(ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK >> ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT) + 1] = \
718 ps->display.refreshrateSource = PP_RefreshrateSource_Explicit;
719 ps->display.explicitRefreshrate = look_up[rrr_index];
720 ps->display.limitRefreshrate = true;
722 if (ps->display.explicitRefreshrate == 0)
723 ps->display.limitRefreshrate = false;
725 ps->display.limitRefreshrate = false;
727 tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
728 ATOM_PPLIB_ENABLE_VARIBRIGHT;
730 ps->display.enableVariBright = (0 != tmp);
732 tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
733 ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF;
735 ps->memory.dllOff = (0 != tmp);
737 ps->memory.m3arb = (uint8_t)(le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
738 ATOM_PPLIB_M3ARB_MASK) >> ATOM_PPLIB_M3ARB_SHIFT;
740 ps->temperatures.min = PP_TEMPERATURE_UNITS_PER_CENTIGRADES *
741 pnon_clock_info->ucMinTemperature;
743 ps->temperatures.max = PP_TEMPERATURE_UNITS_PER_CENTIGRADES *
744 pnon_clock_info->ucMaxTemperature;
746 tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
747 ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING;
749 ps->software.disableLoadBalancing = tmp;
751 tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
752 ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS;
754 ps->software.enableSleepForTimestamps = (0 != tmp);
756 ps->validation.supportedPowerLevels = pnon_clock_info->ucRequiredPower;
758 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < version) {
759 ps->uvd_clocks.VCLK = pnon_clock_info->ulVCLK;
760 ps->uvd_clocks.DCLK = pnon_clock_info->ulDCLK;
762 ps->uvd_clocks.VCLK = 0;
763 ps->uvd_clocks.DCLK = 0;
769 static ULONG size_of_entry_v2(ULONG num_dpm_levels)
771 return (sizeof(UCHAR) + sizeof(UCHAR) +
772 (num_dpm_levels * sizeof(UCHAR)));
775 static const ATOM_PPLIB_STATE_V2 *get_state_entry_v2(
776 const StateArray * pstate_arrays,
780 const ATOM_PPLIB_STATE_V2 *pstate;
782 pstate = pstate_arrays->states;
783 if (entry_index <= pstate_arrays->ucNumEntries) {
784 for (i = 0; i < entry_index; i++)
785 pstate = (ATOM_PPLIB_STATE_V2 *)(
786 (unsigned long)pstate +
787 size_of_entry_v2(pstate->ucNumDPMLevels));
793 static const ATOM_PPLIB_POWERPLAYTABLE *get_powerplay_table(
794 struct pp_hwmgr *hwmgr)
796 const void *table_addr = NULL;
800 table_addr = cgs_atom_get_data_table(hwmgr->device,
801 GetIndexIntoMasterTable(DATA, PowerPlayInfo),
802 &size, &frev, &crev);
804 hwmgr->soft_pp_table = table_addr;
806 return (const ATOM_PPLIB_POWERPLAYTABLE *)table_addr;
810 int pp_tables_get_num_of_entries(struct pp_hwmgr *hwmgr,
811 unsigned long *num_of_entries)
813 const StateArray *pstate_arrays;
814 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr);
816 if (powerplay_table == NULL)
819 if (powerplay_table->sHeader.ucTableFormatRevision >= 6) {
820 pstate_arrays = (StateArray *)(((unsigned long)powerplay_table) +
821 le16_to_cpu(powerplay_table->usStateArrayOffset));
823 *num_of_entries = (unsigned long)(pstate_arrays->ucNumEntries);
825 *num_of_entries = (unsigned long)(powerplay_table->ucNumStates);
830 int pp_tables_get_entry(struct pp_hwmgr *hwmgr,
831 unsigned long entry_index,
832 struct pp_power_state *ps,
833 pp_tables_hw_clock_info_callback func)
836 const StateArray *pstate_arrays;
837 const ATOM_PPLIB_STATE_V2 *pstate_entry_v2;
838 const ATOM_PPLIB_NONCLOCK_INFO *pnon_clock_info;
839 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr);
843 const ClockInfoArray *pclock_arrays;
845 const NonClockInfoArray *pnon_clock_arrays;
847 const ATOM_PPLIB_STATE *pstate_entry;
849 if (powerplay_table == NULL)
852 ps->classification.bios_index = entry_index;
854 if (powerplay_table->sHeader.ucTableFormatRevision >= 6) {
855 pstate_arrays = (StateArray *)(((unsigned long)powerplay_table) +
856 le16_to_cpu(powerplay_table->usStateArrayOffset));
858 if (entry_index > pstate_arrays->ucNumEntries)
861 pstate_entry_v2 = get_state_entry_v2(pstate_arrays, entry_index);
862 pclock_arrays = (ClockInfoArray *)(((unsigned long)powerplay_table) +
863 le16_to_cpu(powerplay_table->usClockInfoArrayOffset));
865 pnon_clock_arrays = (NonClockInfoArray *)(((unsigned long)powerplay_table) +
866 le16_to_cpu(powerplay_table->usNonClockInfoArrayOffset));
868 pnon_clock_info = (ATOM_PPLIB_NONCLOCK_INFO *)((unsigned long)(pnon_clock_arrays->nonClockInfo) +
869 (pstate_entry_v2->nonClockInfoIndex * pnon_clock_arrays->ucEntrySize));
871 result = init_non_clock_fields(hwmgr, ps, pnon_clock_arrays->ucEntrySize, pnon_clock_info);
873 for (i = 0; i < pstate_entry_v2->ucNumDPMLevels; i++) {
874 const void *pclock_info = (const void *)(
875 (unsigned long)(pclock_arrays->clockInfo) +
876 (pstate_entry_v2->clockInfoIndex[i] * pclock_arrays->ucEntrySize));
877 res = func(hwmgr, &ps->hardware, i, pclock_info);
878 if ((0 == result) && (0 != res))
882 if (entry_index > powerplay_table->ucNumStates)
885 pstate_entry = (ATOM_PPLIB_STATE *)((unsigned long)powerplay_table + powerplay_table->usStateArrayOffset +
886 entry_index * powerplay_table->ucStateEntrySize);
888 pnon_clock_info = (ATOM_PPLIB_NONCLOCK_INFO *)((unsigned long)powerplay_table +
889 le16_to_cpu(powerplay_table->usNonClockInfoArrayOffset) +
890 pstate_entry->ucNonClockStateIndex *
891 powerplay_table->ucNonClockSize);
893 result = init_non_clock_fields(hwmgr, ps,
894 powerplay_table->ucNonClockSize,
897 for (i = 0; i < powerplay_table->ucStateEntrySize-1; i++) {
898 const void *pclock_info = (const void *)((unsigned long)powerplay_table +
899 le16_to_cpu(powerplay_table->usClockInfoArrayOffset) +
900 pstate_entry->ucClockStateIndices[i] *
901 powerplay_table->ucClockInfoSize);
903 int res = func(hwmgr, &ps->hardware, i, pclock_info);
905 if ((0 == result) && (0 != res))
911 (0 != (ps->classification.flags & PP_StateClassificationFlag_Boot)))
912 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(ps->hardware));
919 static int init_powerplay_tables(
920 struct pp_hwmgr *hwmgr,
921 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table
928 static int init_thermal_controller(
929 struct pp_hwmgr *hwmgr,
930 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
935 static int init_overdrive_limits_V1_4(struct pp_hwmgr *hwmgr,
936 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table,
937 const ATOM_FIRMWARE_INFO_V1_4 *fw_info)
939 hwmgr->platform_descriptor.overdriveLimit.engineClock =
940 le32_to_cpu(fw_info->ulASICMaxEngineClock);
942 hwmgr->platform_descriptor.overdriveLimit.memoryClock =
943 le32_to_cpu(fw_info->ulASICMaxMemoryClock);
945 hwmgr->platform_descriptor.maxOverdriveVDDC =
946 le32_to_cpu(fw_info->ul3DAccelerationEngineClock) & 0x7FF;
948 hwmgr->platform_descriptor.minOverdriveVDDC =
949 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
951 hwmgr->platform_descriptor.maxOverdriveVDDC =
952 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
954 hwmgr->platform_descriptor.overdriveVDDCStep = 0;
958 static int init_overdrive_limits_V2_1(struct pp_hwmgr *hwmgr,
959 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table,
960 const ATOM_FIRMWARE_INFO_V2_1 *fw_info)
962 const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3;
963 const ATOM_PPLIB_EXTENDEDHEADER *header;
965 if (le16_to_cpu(powerplay_table->usTableSize) <
966 sizeof(ATOM_PPLIB_POWERPLAYTABLE3))
969 powerplay_table3 = (const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table;
971 if (0 == powerplay_table3->usExtendendedHeaderOffset)
974 header = (ATOM_PPLIB_EXTENDEDHEADER *)(((unsigned long) powerplay_table) +
975 le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset));
977 hwmgr->platform_descriptor.overdriveLimit.engineClock = le32_to_cpu(header->ulMaxEngineClock);
978 hwmgr->platform_descriptor.overdriveLimit.memoryClock = le32_to_cpu(header->ulMaxMemoryClock);
981 hwmgr->platform_descriptor.minOverdriveVDDC = 0;
982 hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
983 hwmgr->platform_descriptor.overdriveVDDCStep = 0;
988 static int init_overdrive_limits(struct pp_hwmgr *hwmgr,
989 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
995 const ATOM_COMMON_TABLE_HEADER *fw_info = NULL;
997 hwmgr->platform_descriptor.overdriveLimit.engineClock = 0;
998 hwmgr->platform_descriptor.overdriveLimit.memoryClock = 0;
999 hwmgr->platform_descriptor.minOverdriveVDDC = 0;
1000 hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
1002 /* We assume here that fw_info is unchanged if this call fails.*/
1003 fw_info = cgs_atom_get_data_table(hwmgr->device,
1004 GetIndexIntoMasterTable(DATA, FirmwareInfo),
1005 &size, &frev, &crev);
1007 if ((fw_info->ucTableFormatRevision == 1)
1008 && (fw_info->usStructureSize >= sizeof(ATOM_FIRMWARE_INFO_V1_4)))
1009 result = init_overdrive_limits_V1_4(hwmgr,
1011 (const ATOM_FIRMWARE_INFO_V1_4 *)fw_info);
1013 else if ((fw_info->ucTableFormatRevision == 2)
1014 && (fw_info->usStructureSize >= sizeof(ATOM_FIRMWARE_INFO_V2_1)))
1015 result = init_overdrive_limits_V2_1(hwmgr,
1017 (const ATOM_FIRMWARE_INFO_V2_1 *)fw_info);
1019 if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0
1020 && hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0
1021 && !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1022 PHM_PlatformCaps_OverdriveDisabledByPowerBudget))
1023 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1024 PHM_PlatformCaps_ACOverdriveSupport);
1029 static int get_uvd_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
1030 struct phm_uvd_clock_voltage_dependency_table **ptable,
1031 const ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *table,
1032 const UVDClockInfoArray *array)
1034 unsigned long table_size, i;
1035 struct phm_uvd_clock_voltage_dependency_table *uvd_table;
1037 table_size = sizeof(unsigned long) +
1038 sizeof(struct phm_uvd_clock_voltage_dependency_table) *
1041 uvd_table = kzalloc(table_size, GFP_KERNEL);
1042 if (NULL == uvd_table)
1045 uvd_table->count = table->numEntries;
1047 for (i = 0; i < table->numEntries; i++) {
1048 const UVDClockInfo *entry =
1049 &array->entries[table->entries[i].ucUVDClockInfoIndex];
1050 uvd_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage);
1051 uvd_table->entries[i].vclk = ((unsigned long)entry->ucVClkHigh << 16)
1052 | le16_to_cpu(entry->usVClkLow);
1053 uvd_table->entries[i].dclk = ((unsigned long)entry->ucDClkHigh << 16)
1054 | le16_to_cpu(entry->usDClkLow);
1057 *ptable = uvd_table;
1062 static int get_vce_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
1063 struct phm_vce_clock_voltage_dependency_table **ptable,
1064 const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *table,
1065 const VCEClockInfoArray *array)
1067 unsigned long table_size, i;
1068 struct phm_vce_clock_voltage_dependency_table *vce_table = NULL;
1070 table_size = sizeof(unsigned long) +
1071 sizeof(struct phm_vce_clock_voltage_dependency_table)
1072 * table->numEntries;
1074 vce_table = kzalloc(table_size, GFP_KERNEL);
1075 if (NULL == vce_table)
1078 vce_table->count = table->numEntries;
1079 for (i = 0; i < table->numEntries; i++) {
1080 const VCEClockInfo *entry = &array->entries[table->entries[i].ucVCEClockInfoIndex];
1082 vce_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage);
1083 vce_table->entries[i].evclk = ((unsigned long)entry->ucEVClkHigh << 16)
1084 | le16_to_cpu(entry->usEVClkLow);
1085 vce_table->entries[i].ecclk = ((unsigned long)entry->ucECClkHigh << 16)
1086 | le16_to_cpu(entry->usECClkLow);
1089 *ptable = vce_table;
1094 static int get_samu_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
1095 struct phm_samu_clock_voltage_dependency_table **ptable,
1096 const ATOM_PPLIB_SAMClk_Voltage_Limit_Table *table)
1098 unsigned long table_size, i;
1099 struct phm_samu_clock_voltage_dependency_table *samu_table;
1101 table_size = sizeof(unsigned long) +
1102 sizeof(struct phm_samu_clock_voltage_dependency_table) *
1105 samu_table = kzalloc(table_size, GFP_KERNEL);
1106 if (NULL == samu_table)
1109 samu_table->count = table->numEntries;
1111 for (i = 0; i < table->numEntries; i++) {
1112 samu_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage);
1113 samu_table->entries[i].samclk = ((unsigned long)table->entries[i].ucSAMClockHigh << 16)
1114 | le16_to_cpu(table->entries[i].usSAMClockLow);
1117 *ptable = samu_table;
1122 static int get_acp_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
1123 struct phm_acp_clock_voltage_dependency_table **ptable,
1124 const ATOM_PPLIB_ACPClk_Voltage_Limit_Table *table)
1126 unsigned table_size, i;
1127 struct phm_acp_clock_voltage_dependency_table *acp_table;
1129 table_size = sizeof(unsigned long) +
1130 sizeof(struct phm_acp_clock_voltage_dependency_table) *
1133 acp_table = kzalloc(table_size, GFP_KERNEL);
1134 if (NULL == acp_table)
1137 acp_table->count = (unsigned long)table->numEntries;
1139 for (i = 0; i < table->numEntries; i++) {
1140 acp_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage);
1141 acp_table->entries[i].acpclk = ((unsigned long)table->entries[i].ucACPClockHigh << 16)
1142 | le16_to_cpu(table->entries[i].usACPClockLow);
1145 *ptable = acp_table;
1150 static int init_clock_voltage_dependency(struct pp_hwmgr *hwmgr,
1151 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
1153 ATOM_PPLIB_Clock_Voltage_Dependency_Table *table;
1154 ATOM_PPLIB_Clock_Voltage_Limit_Table *limit_table;
1157 uint16_t vce_clock_info_array_offset;
1158 uint16_t uvd_clock_info_array_offset;
1159 uint16_t table_offset;
1161 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL;
1162 hwmgr->dyn_state.vddci_dependency_on_mclk = NULL;
1163 hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
1164 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
1165 hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
1166 hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL;
1167 hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL;
1168 hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL;
1169 hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL;
1170 hwmgr->dyn_state.ppm_parameter_table = NULL;
1171 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL;
1173 vce_clock_info_array_offset = get_vce_clock_info_array_offset(
1174 hwmgr, powerplay_table);
1175 table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr,
1177 if (vce_clock_info_array_offset > 0 && table_offset > 0) {
1178 const VCEClockInfoArray *array = (const VCEClockInfoArray *)
1179 (((unsigned long) powerplay_table) +
1180 vce_clock_info_array_offset);
1181 const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *table =
1182 (const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *)
1183 (((unsigned long) powerplay_table) + table_offset);
1184 result = get_vce_clock_voltage_limit_table(hwmgr,
1185 &hwmgr->dyn_state.vce_clock_voltage_dependency_table,
1189 uvd_clock_info_array_offset = get_uvd_clock_info_array_offset(hwmgr, powerplay_table);
1190 table_offset = get_uvd_clock_voltage_limit_table_offset(hwmgr, powerplay_table);
1192 if (uvd_clock_info_array_offset > 0 && table_offset > 0) {
1193 const UVDClockInfoArray *array = (const UVDClockInfoArray *)
1194 (((unsigned long) powerplay_table) +
1195 uvd_clock_info_array_offset);
1196 const ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *ptable =
1197 (const ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *)
1198 (((unsigned long) powerplay_table) + table_offset);
1199 result = get_uvd_clock_voltage_limit_table(hwmgr,
1200 &hwmgr->dyn_state.uvd_clock_voltage_dependency_table, ptable, array);
1203 table_offset = get_samu_clock_voltage_limit_table_offset(hwmgr,
1206 if (table_offset > 0) {
1207 const ATOM_PPLIB_SAMClk_Voltage_Limit_Table *ptable =
1208 (const ATOM_PPLIB_SAMClk_Voltage_Limit_Table *)
1209 (((unsigned long) powerplay_table) + table_offset);
1210 result = get_samu_clock_voltage_limit_table(hwmgr,
1211 &hwmgr->dyn_state.samu_clock_voltage_dependency_table, ptable);
1214 table_offset = get_acp_clock_voltage_limit_table_offset(hwmgr,
1217 if (table_offset > 0) {
1218 const ATOM_PPLIB_ACPClk_Voltage_Limit_Table *ptable =
1219 (const ATOM_PPLIB_ACPClk_Voltage_Limit_Table *)
1220 (((unsigned long) powerplay_table) + table_offset);
1221 result = get_acp_clock_voltage_limit_table(hwmgr,
1222 &hwmgr->dyn_state.acp_clock_voltage_dependency_table, ptable);
1225 table_offset = get_cacp_tdp_table_offset(hwmgr, powerplay_table);
1226 if (table_offset > 0) {
1227 UCHAR rev_id = *(UCHAR *)(((unsigned long)powerplay_table) + table_offset);
1230 const ATOM_PPLIB_POWERTUNE_Table_V1 *tune_table =
1231 (const ATOM_PPLIB_POWERTUNE_Table_V1 *)
1232 (((unsigned long) powerplay_table) + table_offset);
1233 result = get_cac_tdp_table(hwmgr, &hwmgr->dyn_state.cac_dtp_table,
1234 &tune_table->power_tune_table,
1235 le16_to_cpu(tune_table->usMaximumPowerDeliveryLimit));
1236 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
1237 le16_to_cpu(tune_table->usTjMax);
1239 const ATOM_PPLIB_POWERTUNE_Table *tune_table =
1240 (const ATOM_PPLIB_POWERTUNE_Table *)
1241 (((unsigned long) powerplay_table) + table_offset);
1242 result = get_cac_tdp_table(hwmgr,
1243 &hwmgr->dyn_state.cac_dtp_table,
1244 &tune_table->power_tune_table, 255);
1248 if (le16_to_cpu(powerplay_table->usTableSize) >=
1249 sizeof(ATOM_PPLIB_POWERPLAYTABLE4)) {
1250 const ATOM_PPLIB_POWERPLAYTABLE4 *powerplay_table4 =
1251 (const ATOM_PPLIB_POWERPLAYTABLE4 *)powerplay_table;
1252 if (0 != powerplay_table4->usVddcDependencyOnSCLKOffset) {
1253 table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
1254 (((unsigned long) powerplay_table4) +
1255 powerplay_table4->usVddcDependencyOnSCLKOffset);
1256 result = get_clock_voltage_dependency_table(hwmgr,
1257 &hwmgr->dyn_state.vddc_dependency_on_sclk, table);
1260 if (result == 0 && (0 != powerplay_table4->usVddciDependencyOnMCLKOffset)) {
1261 table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
1262 (((unsigned long) powerplay_table4) +
1263 powerplay_table4->usVddciDependencyOnMCLKOffset);
1264 result = get_clock_voltage_dependency_table(hwmgr,
1265 &hwmgr->dyn_state.vddci_dependency_on_mclk, table);
1268 if (result == 0 && (0 != powerplay_table4->usVddcDependencyOnMCLKOffset)) {
1269 table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
1270 (((unsigned long) powerplay_table4) +
1271 powerplay_table4->usVddcDependencyOnMCLKOffset);
1272 result = get_clock_voltage_dependency_table(hwmgr,
1273 &hwmgr->dyn_state.vddc_dependency_on_mclk, table);
1276 if (result == 0 && (0 != powerplay_table4->usMaxClockVoltageOnDCOffset)) {
1277 limit_table = (ATOM_PPLIB_Clock_Voltage_Limit_Table *)
1278 (((unsigned long) powerplay_table4) +
1279 powerplay_table4->usMaxClockVoltageOnDCOffset);
1280 result = get_clock_voltage_limit(hwmgr,
1281 &hwmgr->dyn_state.max_clock_voltage_on_dc, limit_table);
1284 if (result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) &&
1285 (0 != hwmgr->dyn_state.vddc_dependency_on_mclk->count))
1286 result = get_valid_clk(hwmgr, &hwmgr->dyn_state.valid_mclk_values,
1287 hwmgr->dyn_state.vddc_dependency_on_mclk);
1289 if(result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) &&
1290 (0 != hwmgr->dyn_state.vddc_dependency_on_sclk->count))
1291 result = get_valid_clk(hwmgr,
1292 &hwmgr->dyn_state.valid_sclk_values,
1293 hwmgr->dyn_state.vddc_dependency_on_sclk);
1295 if (result == 0 && (0 != powerplay_table4->usMvddDependencyOnMCLKOffset)) {
1296 table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
1297 (((unsigned long) powerplay_table4) +
1298 powerplay_table4->usMvddDependencyOnMCLKOffset);
1299 result = get_clock_voltage_dependency_table(hwmgr,
1300 &hwmgr->dyn_state.mvdd_dependency_on_mclk, table);
1304 table_offset = get_sclk_vdd_gfx_clock_voltage_dependency_table_offset(hwmgr,
1307 if (table_offset > 0) {
1308 table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
1309 (((unsigned long) powerplay_table) + table_offset);
1310 result = get_clock_voltage_dependency_table(hwmgr,
1311 &hwmgr->dyn_state.vdd_gfx_dependency_on_sclk, table);
1317 static int get_cac_leakage_table(struct pp_hwmgr *hwmgr,
1318 struct phm_cac_leakage_table **ptable,
1319 const ATOM_PPLIB_CAC_Leakage_Table *table)
1321 struct phm_cac_leakage_table *cac_leakage_table;
1322 unsigned long table_size, i;
1324 table_size = sizeof(ULONG) +
1325 (sizeof(struct phm_cac_leakage_table) * table->ucNumEntries);
1327 cac_leakage_table = kzalloc(table_size, GFP_KERNEL);
1329 cac_leakage_table->count = (ULONG)table->ucNumEntries;
1331 for (i = 0; i < cac_leakage_table->count; i++) {
1332 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1333 PHM_PlatformCaps_EVV)) {
1334 cac_leakage_table->entries[i].Vddc1 = le16_to_cpu(table->entries[i].usVddc1);
1335 cac_leakage_table->entries[i].Vddc2 = le16_to_cpu(table->entries[i].usVddc2);
1336 cac_leakage_table->entries[i].Vddc3 = le16_to_cpu(table->entries[i].usVddc3);
1338 cac_leakage_table->entries[i].Vddc = le16_to_cpu(table->entries[i].usVddc);
1339 cac_leakage_table->entries[i].Leakage = le32_to_cpu(table->entries[i].ulLeakageValue);
1343 *ptable = cac_leakage_table;
1348 static int get_platform_power_management_table(struct pp_hwmgr *hwmgr,
1349 ATOM_PPLIB_PPM_Table *atom_ppm_table)
1351 struct phm_ppm_table *ptr = kzalloc(sizeof(ATOM_PPLIB_PPM_Table), GFP_KERNEL);
1356 ptr->ppm_design = atom_ppm_table->ucPpmDesign;
1357 ptr->cpu_core_number = le16_to_cpu(atom_ppm_table->usCpuCoreNumber);
1358 ptr->platform_tdp = le32_to_cpu(atom_ppm_table->ulPlatformTDP);
1359 ptr->small_ac_platform_tdp = le32_to_cpu(atom_ppm_table->ulSmallACPlatformTDP);
1360 ptr->platform_tdc = le32_to_cpu(atom_ppm_table->ulPlatformTDC);
1361 ptr->small_ac_platform_tdc = le32_to_cpu(atom_ppm_table->ulSmallACPlatformTDC);
1362 ptr->apu_tdp = le32_to_cpu(atom_ppm_table->ulApuTDP);
1363 ptr->dgpu_tdp = le32_to_cpu(atom_ppm_table->ulDGpuTDP);
1364 ptr->dgpu_ulv_power = le32_to_cpu(atom_ppm_table->ulDGpuUlvPower);
1365 ptr->tj_max = le32_to_cpu(atom_ppm_table->ulTjmax);
1366 hwmgr->dyn_state.ppm_parameter_table = ptr;
1371 static int init_dpm2_parameters(struct pp_hwmgr *hwmgr,
1372 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
1376 if (le16_to_cpu(powerplay_table->usTableSize) >=
1377 sizeof(ATOM_PPLIB_POWERPLAYTABLE5)) {
1378 const ATOM_PPLIB_POWERPLAYTABLE5 *ptable5 =
1379 (const ATOM_PPLIB_POWERPLAYTABLE5 *)powerplay_table;
1380 const ATOM_PPLIB_POWERPLAYTABLE4 *ptable4 =
1381 (const ATOM_PPLIB_POWERPLAYTABLE4 *)
1382 (&ptable5->basicTable4);
1383 const ATOM_PPLIB_POWERPLAYTABLE3 *ptable3 =
1384 (const ATOM_PPLIB_POWERPLAYTABLE3 *)
1385 (&ptable4->basicTable3);
1386 const ATOM_PPLIB_EXTENDEDHEADER *extended_header;
1387 uint16_t table_offset;
1388 ATOM_PPLIB_PPM_Table *atom_ppm_table;
1390 hwmgr->platform_descriptor.TDPLimit = le32_to_cpu(ptable5->ulTDPLimit);
1391 hwmgr->platform_descriptor.nearTDPLimit = le32_to_cpu(ptable5->ulNearTDPLimit);
1393 hwmgr->platform_descriptor.TDPODLimit = le16_to_cpu(ptable5->usTDPODLimit);
1394 hwmgr->platform_descriptor.TDPAdjustment = 0;
1396 hwmgr->platform_descriptor.VidAdjustment = 0;
1397 hwmgr->platform_descriptor.VidAdjustmentPolarity = 0;
1398 hwmgr->platform_descriptor.VidMinLimit = 0;
1399 hwmgr->platform_descriptor.VidMaxLimit = 1500000;
1400 hwmgr->platform_descriptor.VidStep = 6250;
1402 hwmgr->platform_descriptor.nearTDPLimitAdjusted = le32_to_cpu(ptable5->ulNearTDPLimit);
1404 if (hwmgr->platform_descriptor.TDPODLimit != 0)
1405 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1406 PHM_PlatformCaps_PowerControl);
1408 hwmgr->platform_descriptor.SQRampingThreshold = le32_to_cpu(ptable5->ulSQRampingThreshold);
1410 hwmgr->platform_descriptor.CACLeakage = le32_to_cpu(ptable5->ulCACLeakage);
1412 hwmgr->dyn_state.cac_leakage_table = NULL;
1414 if (0 != ptable5->usCACLeakageTableOffset) {
1415 const ATOM_PPLIB_CAC_Leakage_Table *pCAC_leakage_table =
1416 (ATOM_PPLIB_CAC_Leakage_Table *)(((unsigned long)ptable5) +
1417 le16_to_cpu(ptable5->usCACLeakageTableOffset));
1418 result = get_cac_leakage_table(hwmgr,
1419 &hwmgr->dyn_state.cac_leakage_table, pCAC_leakage_table);
1422 hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(ptable5->usLoadLineSlope);
1424 hwmgr->dyn_state.ppm_parameter_table = NULL;
1426 if (0 != ptable3->usExtendendedHeaderOffset) {
1427 extended_header = (const ATOM_PPLIB_EXTENDEDHEADER *)
1428 (((unsigned long)powerplay_table) +
1429 le16_to_cpu(ptable3->usExtendendedHeaderOffset));
1430 if ((extended_header->usPPMTableOffset > 0) &&
1431 le16_to_cpu(extended_header->usSize) >=
1432 SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5) {
1433 table_offset = le16_to_cpu(extended_header->usPPMTableOffset);
1434 atom_ppm_table = (ATOM_PPLIB_PPM_Table *)
1435 (((unsigned long)powerplay_table) + table_offset);
1436 if (0 == get_platform_power_management_table(hwmgr, atom_ppm_table))
1437 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1438 PHM_PlatformCaps_EnablePlatformPowerManagement);
1445 static int init_phase_shedding_table(struct pp_hwmgr *hwmgr,
1446 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
1448 if (le16_to_cpu(powerplay_table->usTableSize) >=
1449 sizeof(ATOM_PPLIB_POWERPLAYTABLE4)) {
1450 const ATOM_PPLIB_POWERPLAYTABLE4 *powerplay_table4 =
1451 (const ATOM_PPLIB_POWERPLAYTABLE4 *)powerplay_table;
1453 if (0 != powerplay_table4->usVddcPhaseShedLimitsTableOffset) {
1454 const ATOM_PPLIB_PhaseSheddingLimits_Table *ptable =
1455 (ATOM_PPLIB_PhaseSheddingLimits_Table *)
1456 (((unsigned long)powerplay_table4) +
1457 le16_to_cpu(powerplay_table4->usVddcPhaseShedLimitsTableOffset));
1458 struct phm_phase_shedding_limits_table *table;
1459 unsigned long size, i;
1462 size = sizeof(unsigned long) +
1463 (sizeof(struct phm_phase_shedding_limits_table) *
1464 ptable->ucNumEntries);
1466 table = kzalloc(size, GFP_KERNEL);
1468 table->count = (unsigned long)ptable->ucNumEntries;
1470 for (i = 0; i < table->count; i++) {
1471 table->entries[i].Voltage = (unsigned long)le16_to_cpu(ptable->entries[i].usVoltage);
1472 table->entries[i].Sclk = ((unsigned long)ptable->entries[i].ucSclkHigh << 16)
1473 | le16_to_cpu(ptable->entries[i].usSclkLow);
1474 table->entries[i].Mclk = ((unsigned long)ptable->entries[i].ucMclkHigh << 16)
1475 | le16_to_cpu(ptable->entries[i].usMclkLow);
1477 hwmgr->dyn_state.vddc_phase_shed_limits_table = table;
1484 int get_number_of_vce_state_table_entries(
1485 struct pp_hwmgr *hwmgr)
1487 const ATOM_PPLIB_POWERPLAYTABLE *table =
1488 get_powerplay_table(hwmgr);
1489 const ATOM_PPLIB_VCE_State_Table *vce_table =
1490 get_vce_state_table(hwmgr, table);
1493 return vce_table->numEntries;
1498 int get_vce_state_table_entry(struct pp_hwmgr *hwmgr,
1500 struct PP_VCEState *vce_state,
1502 unsigned long *flag)
1504 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr);
1506 const ATOM_PPLIB_VCE_State_Table *vce_state_table = get_vce_state_table(hwmgr, powerplay_table);
1508 unsigned short vce_clock_info_array_offset = get_vce_clock_info_array_offset(hwmgr, powerplay_table);
1510 const VCEClockInfoArray *vce_clock_info_array = (const VCEClockInfoArray *)(((unsigned long) powerplay_table) + vce_clock_info_array_offset);
1512 const ClockInfoArray *clock_arrays = (ClockInfoArray *)(((unsigned long)powerplay_table) + powerplay_table->usClockInfoArrayOffset);
1514 const ATOM_PPLIB_VCE_State_Record *record = &vce_state_table->entries[i];
1516 const VCEClockInfo *vce_clock_info = &vce_clock_info_array->entries[record->ucVCEClockInfoIndex];
1518 unsigned long clockInfoIndex = record->ucClockInfoIndex & 0x3F;
1520 *flag = (record->ucClockInfoIndex >> NUM_BITS_CLOCK_INFO_ARRAY_INDEX);
1522 vce_state->evclk = ((uint32_t)vce_clock_info->ucEVClkHigh << 16) | vce_clock_info->usEVClkLow;
1523 vce_state->ecclk = ((uint32_t)vce_clock_info->ucECClkHigh << 16) | vce_clock_info->usECClkLow;
1525 *clock_info = (void *)((unsigned long)(clock_arrays->clockInfo) + (clockInfoIndex * clock_arrays->ucEntrySize));
1531 static int pp_tables_initialize(struct pp_hwmgr *hwmgr)
1534 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table;
1536 hwmgr->need_pp_table_upload = true;
1538 powerplay_table = get_powerplay_table(hwmgr);
1540 result = init_powerplay_tables(hwmgr, powerplay_table);
1543 result = set_platform_caps(hwmgr,
1544 le32_to_cpu(powerplay_table->ulPlatformCaps));
1547 result = init_thermal_controller(hwmgr, powerplay_table);
1550 result = init_overdrive_limits(hwmgr, powerplay_table);
1553 result = init_clock_voltage_dependency(hwmgr,
1557 result = init_dpm2_parameters(hwmgr, powerplay_table);
1560 result = init_phase_shedding_table(hwmgr, powerplay_table);
1565 static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
1567 if (NULL != hwmgr->soft_pp_table) {
1568 kfree(hwmgr->soft_pp_table);
1569 hwmgr->soft_pp_table = NULL;
1572 if (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) {
1573 kfree(hwmgr->dyn_state.vddc_dependency_on_sclk);
1574 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL;
1577 if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {
1578 kfree(hwmgr->dyn_state.vddci_dependency_on_mclk);
1579 hwmgr->dyn_state.vddci_dependency_on_mclk = NULL;
1582 if (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) {
1583 kfree(hwmgr->dyn_state.vddc_dependency_on_mclk);
1584 hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
1587 if (NULL != hwmgr->dyn_state.mvdd_dependency_on_mclk) {
1588 kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk);
1589 hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
1592 if (NULL != hwmgr->dyn_state.valid_mclk_values) {
1593 kfree(hwmgr->dyn_state.valid_mclk_values);
1594 hwmgr->dyn_state.valid_mclk_values = NULL;
1597 if (NULL != hwmgr->dyn_state.valid_sclk_values) {
1598 kfree(hwmgr->dyn_state.valid_sclk_values);
1599 hwmgr->dyn_state.valid_sclk_values = NULL;
1602 if (NULL != hwmgr->dyn_state.cac_leakage_table) {
1603 kfree(hwmgr->dyn_state.cac_leakage_table);
1604 hwmgr->dyn_state.cac_leakage_table = NULL;
1607 if (NULL != hwmgr->dyn_state.vddc_phase_shed_limits_table) {
1608 kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table);
1609 hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL;
1612 if (NULL != hwmgr->dyn_state.vce_clock_voltage_dependency_table) {
1613 kfree(hwmgr->dyn_state.vce_clock_voltage_dependency_table);
1614 hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL;
1617 if (NULL != hwmgr->dyn_state.uvd_clock_voltage_dependency_table) {
1618 kfree(hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
1619 hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL;
1622 if (NULL != hwmgr->dyn_state.samu_clock_voltage_dependency_table) {
1623 kfree(hwmgr->dyn_state.samu_clock_voltage_dependency_table);
1624 hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL;
1627 if (NULL != hwmgr->dyn_state.acp_clock_voltage_dependency_table) {
1628 kfree(hwmgr->dyn_state.acp_clock_voltage_dependency_table);
1629 hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL;
1632 if (NULL != hwmgr->dyn_state.cac_dtp_table) {
1633 kfree(hwmgr->dyn_state.cac_dtp_table);
1634 hwmgr->dyn_state.cac_dtp_table = NULL;
1637 if (NULL != hwmgr->dyn_state.ppm_parameter_table) {
1638 kfree(hwmgr->dyn_state.ppm_parameter_table);
1639 hwmgr->dyn_state.ppm_parameter_table = NULL;
1642 if (NULL != hwmgr->dyn_state.vdd_gfx_dependency_on_sclk) {
1643 kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk);
1644 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL;
1647 if (NULL != hwmgr->dyn_state.vq_budgeting_table) {
1648 kfree(hwmgr->dyn_state.vq_budgeting_table);
1649 hwmgr->dyn_state.vq_budgeting_table = NULL;
1655 const struct pp_table_func pptable_funcs = {
1656 .pptable_init = pp_tables_initialize,
1657 .pptable_fini = pp_tables_uninitialize,
1658 .pptable_get_number_of_vce_state_table_entries =
1659 get_number_of_vce_state_table_entries,
1660 .pptable_get_vce_state_table_entry =
1661 get_vce_state_table_entry,