drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/fb.h>
  26 #include <asm/div64.h>
  27 #include "linux/delay.h"
  28 #include "pp_acpi.h"
  29 #include "hwmgr.h"
  30 #include "polaris10_hwmgr.h"
  31 #include "polaris10_powertune.h"
  32 #include "polaris10_dyn_defaults.h"
  33 #include "polaris10_smumgr.h"
  34 #include "pp_debug.h"
  35 #include "ppatomctrl.h"
  36 #include "atombios.h"
  37 #include "tonga_pptable.h"
  38 #include "pppcielanes.h"
  39 #include "amd_pcie_helpers.h"
  40 #include "hardwaremanager.h"
  41 #include "tonga_processpptables.h"
  42 #include "cgs_common.h"
  43 #include "smu74.h"
  44 #include "smu_ucode_xfer_vi.h"
  45 #include "smu74_discrete.h"
  46 #include "smu/smu_7_1_3_d.h"
  47 #include "smu/smu_7_1_3_sh_mask.h"
  48 #include "gmc/gmc_8_1_d.h"
  49 #include "gmc/gmc_8_1_sh_mask.h"
  50 #include "oss/oss_3_0_d.h"
  51 #include "gca/gfx_8_0_d.h"
  52 #include "bif/bif_5_0_d.h"
  53 #include "bif/bif_5_0_sh_mask.h"
  54 #include "gmc/gmc_8_1_d.h"
  55 #include "gmc/gmc_8_1_sh_mask.h"
  56 #include "bif/bif_5_0_d.h"
  57 #include "bif/bif_5_0_sh_mask.h"
  58 #include "dce/dce_10_0_d.h"
  59 #include "dce/dce_10_0_sh_mask.h"
  60
  61 #include "polaris10_thermal.h"
  62 #include "polaris10_clockpowergating.h"
  63
  64 #define MC_CG_ARB_FREQ_F0           0x0a
  65 #define MC_CG_ARB_FREQ_F1           0x0b
  66 #define MC_CG_ARB_FREQ_F2           0x0c
  67 #define MC_CG_ARB_FREQ_F3           0x0d
  68
  69 #define MC_CG_SEQ_DRAMCONF_S0       0x05
  70 #define MC_CG_SEQ_DRAMCONF_S1       0x06
  71 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
  72 #define MC_CG_SEQ_YCLK_RESUME       0x0a
  73
  74
  75 #define SMC_RAM_END 0x40000
  76
  77 #define SMC_CG_IND_START            0xc0030000
  78 #define SMC_CG_IND_END              0xc0040000
  79
  80 #define VOLTAGE_SCALE               4
  81 #define VOLTAGE_VID_OFFSET_SCALE1   625
  82 #define VOLTAGE_VID_OFFSET_SCALE2   100
  83
  84 #define VDDC_VDDCI_DELTA            200
  85
  86 #define MEM_FREQ_LOW_LATENCY        25000
  87 #define MEM_FREQ_HIGH_LATENCY       80000
  88
  89 #define MEM_LATENCY_HIGH            45
  90 #define MEM_LATENCY_LOW             35
  91 #define MEM_LATENCY_ERR             0xFFFF
  92
  93 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  94 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  95 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  96
  97
  98 #define PCIE_BUS_CLK                10000
  99 #define TCLK                        (PCIE_BUS_CLK / 10)
 100
 101
 102 uint16_t polaris10_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0},
 103                                                           {600, 1050, 6, 1} };
 104
 105 /*  [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
 106 uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] = { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
 107                                                         { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
 108
 109 /*  [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
 110 uint8_t polaris10_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5},
 111                                                             {0, 2, 4, 5, 6, 5} };
 112
 113 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 114 enum DPM_EVENT_SRC {
 115         DPM_EVENT_SRC_ANALOG = 0,
 116         DPM_EVENT_SRC_EXTERNAL = 1,
 117         DPM_EVENT_SRC_DIGITAL = 2,
 118         DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
 119         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
 120 };
 121
 122 const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
 123
 124 struct polaris10_power_state *cast_phw_polaris10_power_state(
 125                                   struct pp_hw_power_state *hw_ps)
 126 {
 127         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 128                                 "Invalid Powerstate Type!",
 129                                  return NULL);
 130
 131         return (struct polaris10_power_state *)hw_ps;
 132 }
 133
 134 const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
 135                                  const struct pp_hw_power_state *hw_ps)
 136 {
 137         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 138                                 "Invalid Powerstate Type!",
 139                                  return NULL);
 140
 141         return (const struct polaris10_power_state *)hw_ps;
 142 }
 143
 144 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
 145 {
 146         return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
 147                         CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
 148                         ? true : false;
 149 }
 150
 151 /**
 152  * Find the MC microcode version and store it in the HwMgr struct
 153  *
 154  * @param    hwmgr  the address of the powerplay hardware manager.
 155  * @return   always 0
 156  */
 157 int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
 158 {
 159         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 160
 161         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
 162
 163         return 0;
 164 }
 165
 166 uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 167 {
 168         uint32_t speedCntl = 0;
 169
 170         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 171         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
 172                         ixPCIE_LC_SPEED_CNTL);
 173         return((uint16_t)PHM_GET_FIELD(speedCntl,
 174                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 175 }
 176
 177 int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 178 {
 179         uint32_t link_width;
 180
 181         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 182         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 183                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
 184
 185         PP_ASSERT_WITH_CODE((7 >= link_width),
 186                         "Invalid PCIe lane width!", return 0);
 187
 188         return decode_pcie_lane_width(link_width);
 189 }
 190
 191 void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
 192 {
 193         struct phm_ppt_v1_information *table_info =
 194                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 195         struct phm_clock_voltage_dependency_table *table =
 196                                 table_info->vddc_dep_on_dal_pwrl;
 197         struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
 198         enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
 199         uint32_t req_vddc = 0, req_volt, i;
 200
 201         if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW &&
 202                         dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE))
 203                 return;
 204
 205         for (i = 0; i < table->count; i++) {
 206                 if (dal_power_level == table->entries[i].clk) {
 207                         req_vddc = table->entries[i].v;
 208                         break;
 209                 }
 210         }
 211
 212         vddc_table = table_info->vdd_dep_on_sclk;
 213         for (i = 0; i < vddc_table->count; i++) {
 214                 if (req_vddc <= vddc_table->entries[i].vddc) {
 215                         req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE)
 216                                         << VDDC_SHIFT;
 217                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 218                                         PPSMC_MSG_VddC_Request, req_volt);
 219                         return;
 220                 }
 221         }
 222         printk(KERN_ERR "DAL requested level can not"
 223                         " found a available voltage in VDDC DPM Table \n");
 224 }
 225
 226 /**
 227 * Enable voltage control
 228 *
 229 * @param    pHwMgr  the address of the powerplay hardware manager.
 230 * @return   always PP_Result_OK
 231 */
 232 int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
 233 {
 234         PP_ASSERT_WITH_CODE(
 235                 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
 236                 "Failed to enable voltage DPM during DPM Start Function!",
 237                 return 1;
 238         );
 239
 240         return 0;
 241 }
 242
 243 /**
 244 * Checks if we want to support voltage control
 245 *
 246 * @param    hwmgr  the address of the powerplay hardware manager.
 247 */
 248 static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
 249 {
 250         const struct polaris10_hwmgr *data =
 251                         (const struct polaris10_hwmgr *)(hwmgr->backend);
 252
 253         return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
 254 }
 255
 256 /**
 257 * Enable voltage control
 258 *
 259 * @param    hwmgr  the address of the powerplay hardware manager.
 260 * @return   always 0
 261 */
 262 static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
 263 {
 264         /* enable voltage control */
 265         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 266                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 267
 268         return 0;
 269 }
 270
 271 /**
 272 * Create Voltage Tables.
 273 *
 274 * @param    hwmgr  the address of the powerplay hardware manager.
 275 * @return   always 0
 276 */
 277 static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
 278 {
 279         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 280         struct phm_ppt_v1_information *table_info =
 281                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 282         int result;
 283
 284         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 285                 result = atomctrl_get_voltage_table_v3(hwmgr,
 286                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
 287                                 &(data->mvdd_voltage_table));
 288                 PP_ASSERT_WITH_CODE((0 == result),
 289                                 "Failed to retrieve MVDD table.",
 290                                 return result);
 291         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
 292                 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
 293                                 table_info->vdd_dep_on_mclk);
 294                 PP_ASSERT_WITH_CODE((0 == result),
 295                                 "Failed to retrieve SVI2 MVDD table from dependancy table.",
 296                                 return result;);
 297         }
 298
 299         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 300                 result = atomctrl_get_voltage_table_v3(hwmgr,
 301                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
 302                                 &(data->vddci_voltage_table));
 303                 PP_ASSERT_WITH_CODE((0 == result),
 304                                 "Failed to retrieve VDDCI table.",
 305                                 return result);
 306         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
 307                 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
 308                                 table_info->vdd_dep_on_mclk);
 309                 PP_ASSERT_WITH_CODE((0 == result),
 310                                 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
 311                                 return result);
 312         }
 313
 314         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
 315                 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
 316                                 table_info->vddc_lookup_table);
 317                 PP_ASSERT_WITH_CODE((0 == result),
 318                                 "Failed to retrieve SVI2 VDDC table from lookup table.",
 319                                 return result);
 320         }
 321
 322         PP_ASSERT_WITH_CODE(
 323                         (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
 324                         "Too many voltage values for VDDC. Trimming to fit state table.",
 325                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
 326                                                                 &(data->vddc_voltage_table)));
 327
 328         PP_ASSERT_WITH_CODE(
 329                         (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
 330                         "Too many voltage values for VDDCI. Trimming to fit state table.",
 331                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
 332                                         &(data->vddci_voltage_table)));
 333
 334         PP_ASSERT_WITH_CODE(
 335                         (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
 336                         "Too many voltage values for MVDD. Trimming to fit state table.",
 337                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
 338                                                            &(data->mvdd_voltage_table)));
 339
 340         return 0;
 341 }
 342
 343 /**
 344 * Programs static screed detection parameters
 345 *
 346 * @param    hwmgr  the address of the powerplay hardware manager.
 347 * @return   always 0
 348 */
 349 static int polaris10_program_static_screen_threshold_parameters(
 350                                                         struct pp_hwmgr *hwmgr)
 351 {
 352         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 353
 354         /* Set static screen threshold unit */
 355         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 356                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
 357                         data->static_screen_threshold_unit);
 358         /* Set static screen threshold */
 359         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 360                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
 361                         data->static_screen_threshold);
 362
 363         return 0;
 364 }
 365
 366 /**
 367 * Setup display gap for glitch free memory clock switching.
 368 *
 369 * @param    hwmgr  the address of the powerplay hardware manager.
 370 * @return   always  0
 371 */
 372 static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
 373 {
 374         uint32_t display_gap =
 375                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 376                                         ixCG_DISPLAY_GAP_CNTL);
 377
 378         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 379                         DISP_GAP, DISPLAY_GAP_IGNORE);
 380
 381         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 382                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
 383
 384         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 385                         ixCG_DISPLAY_GAP_CNTL, display_gap);
 386
 387         return 0;
 388 }
 389
 390 /**
 391 * Programs activity state transition voting clients
 392 *
 393 * @param    hwmgr  the address of the powerplay hardware manager.
 394 * @return   always  0
 395 */
 396 static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
 397 {
 398         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 399
 400         /* Clear reset for voting clients before enabling DPM */
 401         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 402                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
 403         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 404                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
 405
 406         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 407                         ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
 408         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 409                         ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
 410         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 411                         ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
 412         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 413                         ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
 414         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 415                         ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
 416         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 417                         ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
 418         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 419                         ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
 420         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 421                         ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
 422
 423         return 0;
 424 }
 425
 426 /**
 427 * Get the location of various tables inside the FW image.
 428 *
 429 * @param    hwmgr  the address of the powerplay hardware manager.
 430 * @return   always  0
 431 */
 432 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
 433 {
 434         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 435         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
 436         uint32_t tmp;
 437         int result;
 438         bool error = false;
 439
 440         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 441                         SMU7_FIRMWARE_HEADER_LOCATION +
 442                         offsetof(SMU74_Firmware_Header, DpmTable),
 443                         &tmp, data->sram_end);
 444
 445         if (0 == result)
 446                 data->dpm_table_start = tmp;
 447
 448         error |= (0 != result);
 449
 450         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 451                         SMU7_FIRMWARE_HEADER_LOCATION +
 452                         offsetof(SMU74_Firmware_Header, SoftRegisters),
 453                         &tmp, data->sram_end);
 454
 455         if (!result) {
 456                 data->soft_regs_start = tmp;
 457                 smu_data->soft_regs_start = tmp;
 458         }
 459
 460         error |= (0 != result);
 461
 462         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 463                         SMU7_FIRMWARE_HEADER_LOCATION +
 464                         offsetof(SMU74_Firmware_Header, mcRegisterTable),
 465                         &tmp, data->sram_end);
 466
 467         if (!result)
 468                 data->mc_reg_table_start = tmp;
 469
 470         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 471                         SMU7_FIRMWARE_HEADER_LOCATION +
 472                         offsetof(SMU74_Firmware_Header, FanTable),
 473                         &tmp, data->sram_end);
 474
 475         if (!result)
 476                 data->fan_table_start = tmp;
 477
 478         error |= (0 != result);
 479
 480         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 481                         SMU7_FIRMWARE_HEADER_LOCATION +
 482                         offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
 483                         &tmp, data->sram_end);
 484
 485         if (!result)
 486                 data->arb_table_start = tmp;
 487
 488         error |= (0 != result);
 489
 490         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 491                         SMU7_FIRMWARE_HEADER_LOCATION +
 492                         offsetof(SMU74_Firmware_Header, Version),
 493                         &tmp, data->sram_end);
 494
 495         if (!result)
 496                 hwmgr->microcode_version_info.SMC = tmp;
 497
 498         error |= (0 != result);
 499
 500         return error ? -1 : 0;
 501 }
 502
 503 /* Copy one arb setting to another and then switch the active set.
 504  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
 505  */
 506 static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
 507                 uint32_t arb_src, uint32_t arb_dest)
 508 {
 509         uint32_t mc_arb_dram_timing;
 510         uint32_t mc_arb_dram_timing2;
 511         uint32_t burst_time;
 512         uint32_t mc_cg_config;
 513
 514         switch (arb_src) {
 515         case MC_CG_ARB_FREQ_F0:
 516                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
 517                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
 518                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
 519                 break;
 520         case MC_CG_ARB_FREQ_F1:
 521                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
 522                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
 523                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
 524                 break;
 525         default:
 526                 return -EINVAL;
 527         }
 528
 529         switch (arb_dest) {
 530         case MC_CG_ARB_FREQ_F0:
 531                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 532                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 533                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
 534                 break;
 535         case MC_CG_ARB_FREQ_F1:
 536                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 537                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 538                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
 539                 break;
 540         default:
 541                 return -EINVAL;
 542         }
 543
 544         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
 545         mc_cg_config |= 0x0000000F;
 546         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
 547         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
 548
 549         return 0;
 550 }
 551
 552 /**
 553 * Initial switch from ARB F0->F1
 554 *
 555 * @param    hwmgr  the address of the powerplay hardware manager.
 556 * @return   always 0
 557 * This function is to be called from the SetPowerState table.
 558 */
 559 static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
 560 {
 561         return polaris10_copy_and_switch_arb_sets(hwmgr,
 562                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
 563 }
 564
 565 static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
 566 {
 567         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 568         struct phm_ppt_v1_information *table_info =
 569                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 570         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
 571         uint32_t i, max_entry;
 572
 573         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
 574                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
 575                         return -EINVAL);
 576
 577         if (data->use_pcie_performance_levels &&
 578                         !data->use_pcie_power_saving_levels) {
 579                 data->pcie_gen_power_saving = data->pcie_gen_performance;
 580                 data->pcie_lane_power_saving = data->pcie_lane_performance;
 581         } else if (!data->use_pcie_performance_levels &&
 582                         data->use_pcie_power_saving_levels) {
 583                 data->pcie_gen_performance = data->pcie_gen_power_saving;
 584                 data->pcie_lane_performance = data->pcie_lane_power_saving;
 585         }
 586
 587         phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
 588                                         SMU74_MAX_LEVELS_LINK,
 589                                         MAX_REGULAR_DPM_NUMBER);
 590
 591         if (pcie_table != NULL) {
 592                 /* max_entry is used to make sure we reserve one PCIE level
 593                  * for boot level (fix for A+A PSPP issue).
 594                  * If PCIE table from PPTable have ULV entry + 8 entries,
 595                  * then ignore the last entry.*/
 596                 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
 597                                 SMU74_MAX_LEVELS_LINK : pcie_table->count;
 598                 for (i = 1; i < max_entry; i++) {
 599                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
 600                                         get_pcie_gen_support(data->pcie_gen_cap,
 601                                                         pcie_table->entries[i].gen_speed),
 602                                         get_pcie_lane_support(data->pcie_lane_cap,
 603                                                         pcie_table->entries[i].lane_width));
 604                 }
 605                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
 606
 607                 /* Setup BIF_SCLK levels */
 608                 for (i = 0; i < max_entry; i++)
 609                         data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
 610         } else {
 611                 /* Hardcode Pcie Table */
 612                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
 613                                 get_pcie_gen_support(data->pcie_gen_cap,
 614                                                 PP_Min_PCIEGen),
 615                                 get_pcie_lane_support(data->pcie_lane_cap,
 616                                                 PP_Max_PCIELane));
 617                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
 618                                 get_pcie_gen_support(data->pcie_gen_cap,
 619                                                 PP_Min_PCIEGen),
 620                                 get_pcie_lane_support(data->pcie_lane_cap,
 621                                                 PP_Max_PCIELane));
 622                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
 623                                 get_pcie_gen_support(data->pcie_gen_cap,
 624                                                 PP_Max_PCIEGen),
 625                                 get_pcie_lane_support(data->pcie_lane_cap,
 626                                                 PP_Max_PCIELane));
 627                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
 628                                 get_pcie_gen_support(data->pcie_gen_cap,
 629                                                 PP_Max_PCIEGen),
 630                                 get_pcie_lane_support(data->pcie_lane_cap,
 631                                                 PP_Max_PCIELane));
 632                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
 633                                 get_pcie_gen_support(data->pcie_gen_cap,
 634                                                 PP_Max_PCIEGen),
 635                                 get_pcie_lane_support(data->pcie_lane_cap,
 636                                                 PP_Max_PCIELane));
 637                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
 638                                 get_pcie_gen_support(data->pcie_gen_cap,
 639                                                 PP_Max_PCIEGen),
 640                                 get_pcie_lane_support(data->pcie_lane_cap,
 641                                                 PP_Max_PCIELane));
 642
 643                 data->dpm_table.pcie_speed_table.count = 6;
 644         }
 645         /* Populate last level for boot PCIE level, but do not increment count. */
 646         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
 647                         data->dpm_table.pcie_speed_table.count,
 648                         get_pcie_gen_support(data->pcie_gen_cap,
 649                                         PP_Min_PCIEGen),
 650                         get_pcie_lane_support(data->pcie_lane_cap,
 651                                         PP_Max_PCIELane));
 652
 653         return 0;
 654 }
 655
 656 /*
 657  * This function is to initalize all DPM state tables
 658  * for SMU7 based on the dependency table.
 659  * Dynamic state patching function will then trim these
 660  * state tables to the allowed range based
 661  * on the power policy or external client requests,
 662  * such as UVD request, etc.
 663  */
 664 int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 665 {
 666         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 667         struct phm_ppt_v1_information *table_info =
 668                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 669         uint32_t i;
 670
 671         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
 672                         table_info->vdd_dep_on_sclk;
 673         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
 674                         table_info->vdd_dep_on_mclk;
 675
 676         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
 677                         "SCLK dependency table is missing. This table is mandatory",
 678                         return -EINVAL);
 679         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
 680                         "SCLK dependency table has to have is missing."
 681                         "This table is mandatory",
 682                         return -EINVAL);
 683
 684         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
 685                         "MCLK dependency table is missing. This table is mandatory",
 686                         return -EINVAL);
 687         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
 688                         "MCLK dependency table has to have is missing."
 689                         "This table is mandatory",
 690                         return -EINVAL);
 691
 692         /* clear the state table to reset everything to default */
 693         phm_reset_single_dpm_table(
 694                         &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
 695         phm_reset_single_dpm_table(
 696                         &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
 697
 698
 699         /* Initialize Sclk DPM table based on allow Sclk values */
 700         data->dpm_table.sclk_table.count = 0;
 701         for (i = 0; i < dep_sclk_table->count; i++) {
 702                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
 703                                                 dep_sclk_table->entries[i].clk) {
 704
 705                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 706                                         dep_sclk_table->entries[i].clk;
 707
 708                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
 709                                         (i == 0) ? true : false;
 710                         data->dpm_table.sclk_table.count++;
 711                 }
 712         }
 713
 714         /* Initialize Mclk DPM table based on allow Mclk values */
 715         data->dpm_table.mclk_table.count = 0;
 716         for (i = 0; i < dep_mclk_table->count; i++) {
 717                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
 718                                 [data->dpm_table.mclk_table.count - 1].value !=
 719                                                 dep_mclk_table->entries[i].clk) {
 720                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 721                                                         dep_mclk_table->entries[i].clk;
 722                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
 723                                                         (i == 0) ? true : false;
 724                         data->dpm_table.mclk_table.count++;
 725                 }
 726         }
 727
 728         /* setup PCIE gen speed levels */
 729         polaris10_setup_default_pcie_table(hwmgr);
 730
 731         /* save a copy of the default DPM table */
 732         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 733                         sizeof(struct polaris10_dpm_table));
 734
 735         return 0;
 736 }
 737
 738 uint8_t convert_to_vid(uint16_t vddc)
 739 {
 740         return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
 741 }
 742
 743 /**
 744  * Mvdd table preparation for SMC.
 745  *
 746  * @param    *hwmgr The address of the hardware manager.
 747  * @param    *table The SMC DPM table structure to be populated.
 748  * @return   0
 749  */
 750 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
 751                         SMU74_Discrete_DpmTable *table)
 752 {
 753         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 754         uint32_t count, level;
 755
 756         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 757                 count = data->mvdd_voltage_table.count;
 758                 if (count > SMU_MAX_SMIO_LEVELS)
 759                         count = SMU_MAX_SMIO_LEVELS;
 760                 for (level = 0; level < count; level++) {
 761                         table->SmioTable2.Pattern[level].Voltage =
 762                                 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
 763                         /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
 764                         table->SmioTable2.Pattern[level].Smio =
 765                                 (uint8_t) level;
 766                         table->Smio[level] |=
 767                                 data->mvdd_voltage_table.entries[level].smio_low;
 768                 }
 769                 table->SmioMask2 = data->vddci_voltage_table.mask_low;
 770
 771                 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
 772         }
 773
 774         return 0;
 775 }
 776
 777 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
 778                                         struct SMU74_Discrete_DpmTable *table)
 779 {
 780         uint32_t count, level;
 781         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 782
 783         count = data->vddci_voltage_table.count;
 784
 785         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 786                 if (count > SMU_MAX_SMIO_LEVELS)
 787                         count = SMU_MAX_SMIO_LEVELS;
 788                 for (level = 0; level < count; ++level) {
 789                         table->SmioTable1.Pattern[level].Voltage =
 790                                 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
 791                         table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
 792
 793                         table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
 794                 }
 795         }
 796
 797         table->SmioMask1 = data->vddci_voltage_table.mask_low;
 798
 799         return 0;
 800 }
 801
 802 /**
 803 * Preparation of vddc and vddgfx CAC tables for SMC.
 804 *
 805 * @param    hwmgr  the address of the hardware manager
 806 * @param    table  the SMC DPM table structure to be populated
 807 * @return   always 0
 808 */
 809 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
 810                 struct SMU74_Discrete_DpmTable *table)
 811 {
 812         uint32_t count;
 813         uint8_t index;
 814         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 815         struct phm_ppt_v1_information *table_info =
 816                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 817         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
 818                         table_info->vddc_lookup_table;
 819         /* tables is already swapped, so in order to use the value from it,
 820          * we need to swap it back.
 821          * We are populating vddc CAC data to BapmVddc table
 822          * in split and merged mode
 823          */
 824         for (count = 0; count < lookup_table->count; count++) {
 825                 index = phm_get_voltage_index(lookup_table,
 826                                 data->vddc_voltage_table.entries[count].value);
 827                 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
 828                 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
 829                 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
 830         }
 831
 832         return 0;
 833 }
 834
 835 /**
 836 * Preparation of voltage tables for SMC.
 837 *
 838 * @param    hwmgr   the address of the hardware manager
 839 * @param    table   the SMC DPM table structure to be populated
 840 * @return   always  0
 841 */
 842
 843 int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
 844                 struct SMU74_Discrete_DpmTable *table)
 845 {
 846         polaris10_populate_smc_vddci_table(hwmgr, table);
 847         polaris10_populate_smc_mvdd_table(hwmgr, table);
 848         polaris10_populate_cac_table(hwmgr, table);
 849
 850         return 0;
 851 }
 852
 853 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
 854                 struct SMU74_Discrete_Ulv *state)
 855 {
 856         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 857         struct phm_ppt_v1_information *table_info =
 858                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 859
 860         state->CcPwrDynRm = 0;
 861         state->CcPwrDynRm1 = 0;
 862
 863         state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
 864         state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
 865                         VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
 866
 867         state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
 868
 869         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
 870         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
 871         CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
 872
 873         return 0;
 874 }
 875
 876 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
 877                 struct SMU74_Discrete_DpmTable *table)
 878 {
 879         return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
 880 }
 881
 882 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
 883                 struct SMU74_Discrete_DpmTable *table)
 884 {
 885         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 886         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
 887         int i;
 888
 889         /* Index (dpm_table->pcie_speed_table.count)
 890          * is reserved for PCIE boot level. */
 891         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
 892                 table->LinkLevel[i].PcieGenSpeed  =
 893                                 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
 894                 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
 895                                 dpm_table->pcie_speed_table.dpm_levels[i].param1);
 896                 table->LinkLevel[i].EnabledForActivity = 1;
 897                 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
 898                 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
 899                 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
 900         }
 901
 902         data->smc_state_table.LinkLevelCount =
 903                         (uint8_t)dpm_table->pcie_speed_table.count;
 904         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
 905                         phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
 906
 907         return 0;
 908 }
 909
 910 static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
 911 {
 912         uint32_t reference_clock, tmp;
 913         struct cgs_display_info info = {0};
 914         struct cgs_mode_info mode_info;
 915
 916         info.mode_info = &mode_info;
 917
 918         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
 919
 920         if (tmp)
 921                 return TCLK;
 922
 923         cgs_get_active_displays_info(hwmgr->device, &info);
 924         reference_clock = mode_info.ref_clock;
 925
 926         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
 927
 928         if (0 != tmp)
 929                 return reference_clock / 4;
 930
 931         return reference_clock;
 932 }
 933
 934 /**
 935 * Calculates the SCLK dividers using the provided engine clock
 936 *
 937 * @param    hwmgr  the address of the hardware manager
 938 * @param    clock  the engine clock to use to populate the structure
 939 * @param    sclk   the SMC SCLK structure to be populated
 940 */
 941 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
 942                 uint32_t clock, SMU_SclkSetting *sclk_setting)
 943 {
 944         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 945         const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
 946         struct pp_atomctrl_clock_dividers_ai dividers;
 947
 948         uint32_t ref_clock;
 949         uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
 950         uint8_t i;
 951         int result;
 952         uint64_t temp;
 953
 954         sclk_setting->SclkFrequency = clock;
 955         /* get the engine clock dividers for this clock value */
 956         result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
 957         if (result == 0) {
 958                 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
 959                 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
 960                 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
 961                 sclk_setting->PllRange = dividers.ucSclkPllRange;
 962                 sclk_setting->Sclk_slew_rate = 0x400;
 963                 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
 964                 sclk_setting->Pcc_down_slew_rate = 0xffff;
 965                 sclk_setting->SSc_En = dividers.ucSscEnable;
 966                 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
 967                 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
 968                 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
 969                 return result;
 970         }
 971
 972         ref_clock = polaris10_get_xclk(hwmgr);
 973
 974         for (i = 0; i < NUM_SCLK_RANGE; i++) {
 975                 if (clock > data->range_table[i].trans_lower_frequency
 976                 && clock <= data->range_table[i].trans_upper_frequency) {
 977                         sclk_setting->PllRange = i;
 978                         break;
 979                 }
 980         }
 981
 982         sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 983         temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 984         temp <<= 0x10;
 985         do_div(temp, ref_clock);
 986         sclk_setting->Fcw_frac = temp & 0xffff;
 987
 988         pcc_target_percent = 10; /*  Hardcode 10% for now. */
 989         pcc_target_freq = clock - (clock * pcc_target_percent / 100);
 990         sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 991
 992         ss_target_percent = 2; /*  Hardcode 2% for now. */
 993         sclk_setting->SSc_En = 0;
 994         if (ss_target_percent) {
 995                 sclk_setting->SSc_En = 1;
 996                 ss_target_freq = clock - (clock * ss_target_percent / 100);
 997                 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 998                 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 999                 temp <<= 0x10;
1000                 do_div(temp, ref_clock);
1001                 sclk_setting->Fcw1_frac = temp & 0xffff;
1002         }
1003
1004         return 0;
1005 }
1006
1007 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
1008                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1009                 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1010 {
1011         uint32_t i;
1012         uint16_t vddci;
1013         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1014
1015         *voltage = *mvdd = 0;
1016
1017         /* clock - voltage dependency table is empty table */
1018         if (dep_table->count == 0)
1019                 return -EINVAL;
1020
1021         for (i = 0; i < dep_table->count; i++) {
1022                 /* find first sclk bigger than request */
1023                 if (dep_table->entries[i].clk >= clock) {
1024                         *voltage |= (dep_table->entries[i].vddc *
1025                                         VOLTAGE_SCALE) << VDDC_SHIFT;
1026                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1027                                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1028                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1029                         else if (dep_table->entries[i].vddci)
1030                                 *voltage |= (dep_table->entries[i].vddci *
1031                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1032                         else {
1033                                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1034                                                 (dep_table->entries[i].vddc -
1035                                                                 (uint16_t)data->vddc_vddci_delta));
1036                                 *voltage |= (vddci * VOLTAGE_SCALE) <<  VDDCI_SHIFT;
1037                         }
1038
1039                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1040                                 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1041                                         VOLTAGE_SCALE;
1042                         else if (dep_table->entries[i].mvdd)
1043                                 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1044                                         VOLTAGE_SCALE;
1045
1046                         *voltage |= 1 << PHASES_SHIFT;
1047                         return 0;
1048                 }
1049         }
1050
1051         /* sclk is bigger than max sclk in the dependence table */
1052         *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1053
1054         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1055                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1056                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1057         else if (dep_table->entries[i-1].vddci) {
1058                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1059                                 (dep_table->entries[i].vddc -
1060                                                 (uint16_t)data->vddc_vddci_delta));
1061                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1062         }
1063
1064         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1065                 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1066         else if (dep_table->entries[i].mvdd)
1067                 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1068
1069         return 0;
1070 }
1071
1072 sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = { {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
1073                                                 {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1074                                                 {VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
1075                                                 {VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
1076                                                 {VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
1077                                                 {VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
1078                                                 {VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
1079                                                 {VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
1080
1081 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
1082 {
1083         uint32_t i, ref_clk;
1084         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1085         SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
1086         struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1087
1088         ref_clk = polaris10_get_xclk(hwmgr);
1089
1090         if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1091                 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1092                         table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1093                         table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1094                         table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1095
1096                         table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1097                         table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1098
1099                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1100                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1101                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1102                 }
1103                 return;
1104         }
1105
1106         for (i = 0; i < NUM_SCLK_RANGE; i++) {
1107
1108                 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1109                 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1110
1111                 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1112                 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1113                 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1114
1115                 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1116                 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1117
1118                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1119                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1120                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1121         }
1122 }
1123
1124 /**
1125 * Populates single SMC SCLK structure using the provided engine clock
1126 *
1127 * @param    hwmgr      the address of the hardware manager
1128 * @param    clock the engine clock to use to populate the structure
1129 * @param    sclk        the SMC SCLK structure to be populated
1130 */
1131
1132 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1133                 uint32_t clock, uint16_t sclk_al_threshold,
1134                 struct SMU74_Discrete_GraphicsLevel *level)
1135 {
1136         int result, i, temp;
1137         /* PP_Clocks minClocks; */
1138         uint32_t mvdd;
1139         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1140         struct phm_ppt_v1_information *table_info =
1141                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1142         SMU_SclkSetting curr_sclk_setting = { 0 };
1143
1144         result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
1145
1146         /* populate graphics levels */
1147         result = polaris10_get_dependency_volt_by_clk(hwmgr,
1148                         table_info->vdd_dep_on_sclk, clock,
1149                         &level->MinVoltage, &mvdd);
1150
1151         PP_ASSERT_WITH_CODE((0 == result),
1152                         "can not find VDDC voltage value for "
1153                         "VDDC engine clock dependency table",
1154                         return result);
1155         level->ActivityLevel = sclk_al_threshold;
1156
1157         level->CcPwrDynRm = 0;
1158         level->CcPwrDynRm1 = 0;
1159         level->EnabledForActivity = 0;
1160         level->EnabledForThrottle = 1;
1161         level->UpHyst = 10;
1162         level->DownHyst = 0;
1163         level->VoltageDownHyst = 0;
1164         level->PowerThrottle = 0;
1165
1166         /*
1167         * TODO: get minimum clocks from dal configaration
1168         * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1169         */
1170         /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1171
1172         /* get level->DeepSleepDivId
1173         if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1174                 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1175         */
1176         PP_ASSERT_WITH_CODE((clock >= 2500), "Engine clock can't satisfy stutter requirement!", return 0);
1177         for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
1178                 temp = clock / (1UL << i);
1179
1180                 if (temp >= 2500 || i == 0)
1181                         break;
1182         }
1183
1184         level->DeepSleepDivId = i;
1185
1186         /* Default to slow, highest DPM level will be
1187          * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1188          */
1189         if (data->update_up_hyst)
1190                 level->UpHyst = (uint8_t)data->up_hyst;
1191         if (data->update_down_hyst)
1192                 level->DownHyst = (uint8_t)data->down_hyst;
1193
1194         level->SclkSetting = curr_sclk_setting;
1195
1196         CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1197         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1198         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1199         CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1200         CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1201         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1202         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1203         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1204         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1205         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1206         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1207         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1208         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1209         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1210         return 0;
1211 }
1212
1213 /**
1214 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1215 *
1216 * @param    hwmgr      the address of the hardware manager
1217 */
1218 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1219 {
1220         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1221         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1222         struct phm_ppt_v1_information *table_info =
1223                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1224         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1225         uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1226         int result = 0;
1227         uint32_t array = data->dpm_table_start +
1228                         offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1229         uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1230                         SMU74_MAX_LEVELS_GRAPHICS;
1231         struct SMU74_Discrete_GraphicsLevel *levels =
1232                         data->smc_state_table.GraphicsLevel;
1233         uint32_t i, max_entry;
1234         uint8_t hightest_pcie_level_enabled = 0,
1235                 lowest_pcie_level_enabled = 0,
1236                 mid_pcie_level_enabled = 0,
1237                 count = 0;
1238
1239         polaris10_get_sclk_range_table(hwmgr);
1240
1241         for (i = 0; i < dpm_table->sclk_table.count; i++) {
1242
1243                 result = polaris10_populate_single_graphic_level(hwmgr,
1244                                 dpm_table->sclk_table.dpm_levels[i].value,
1245                                 (uint16_t)data->activity_target[i],
1246                                 &(data->smc_state_table.GraphicsLevel[i]));
1247                 if (result)
1248                         return result;
1249
1250                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1251                 if (i > 1)
1252                         levels[i].DeepSleepDivId = 0;
1253         }
1254         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1255                                         PHM_PlatformCaps_SPLLShutdownSupport))
1256                 data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1257
1258         data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1259         data->smc_state_table.GraphicsDpmLevelCount =
1260                         (uint8_t)dpm_table->sclk_table.count;
1261         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1262                         phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1263
1264
1265         if (pcie_table != NULL) {
1266                 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1267                                 "There must be 1 or more PCIE levels defined in PPTable.",
1268                                 return -EINVAL);
1269                 max_entry = pcie_entry_cnt - 1;
1270                 for (i = 0; i < dpm_table->sclk_table.count; i++)
1271                         levels[i].pcieDpmLevel =
1272                                         (uint8_t) ((i < max_entry) ? i : max_entry);
1273         } else {
1274                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1275                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1276                                                 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1277                         hightest_pcie_level_enabled++;
1278
1279                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1280                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1281                                                 (1 << lowest_pcie_level_enabled)) == 0))
1282                         lowest_pcie_level_enabled++;
1283
1284                 while ((count < hightest_pcie_level_enabled) &&
1285                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1286                                                 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1287                         count++;
1288
1289                 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1290                                 hightest_pcie_level_enabled ?
1291                                                 (lowest_pcie_level_enabled + 1 + count) :
1292                                                 hightest_pcie_level_enabled;
1293
1294                 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1295                 for (i = 2; i < dpm_table->sclk_table.count; i++)
1296                         levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1297
1298                 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1299                 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1300
1301                 /* set pcieDpmLevel to mid_pcie_level_enabled */
1302                 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1303         }
1304         /* level count will send to smc once at init smc table and never change */
1305         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1306                         (uint32_t)array_size, data->sram_end);
1307
1308         return result;
1309 }
1310
1311 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1312                 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1313 {
1314         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1315         struct phm_ppt_v1_information *table_info =
1316                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1317         int result = 0;
1318         struct cgs_display_info info = {0, 0, NULL};
1319
1320         cgs_get_active_displays_info(hwmgr->device, &info);
1321
1322         if (table_info->vdd_dep_on_mclk) {
1323                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1324                                 table_info->vdd_dep_on_mclk, clock,
1325                                 &mem_level->MinVoltage, &mem_level->MinMvdd);
1326                 PP_ASSERT_WITH_CODE((0 == result),
1327                                 "can not find MinVddc voltage value from memory "
1328                                 "VDDC voltage dependency table", return result);
1329         }
1330
1331         mem_level->MclkFrequency = clock;
1332         mem_level->StutterEnable = 0;
1333         mem_level->EnabledForThrottle = 1;
1334         mem_level->EnabledForActivity = 0;
1335         mem_level->UpHyst = 0;
1336         mem_level->DownHyst = 100;
1337         mem_level->VoltageDownHyst = 0;
1338         mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1339         mem_level->StutterEnable = false;
1340
1341         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1342
1343         data->display_timing.num_existing_displays = info.display_count;
1344
1345         if ((data->mclk_stutter_mode_threshold) &&
1346                 (clock <= data->mclk_stutter_mode_threshold) &&
1347                 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1348                                 STUTTER_ENABLE) & 0x1))
1349                 mem_level->StutterEnable = true;
1350
1351         if (!result) {
1352                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1353                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1354                 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1355                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1356         }
1357         return result;
1358 }
1359
1360 /**
1361 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1362 *
1363 * @param    hwmgr      the address of the hardware manager
1364 */
1365 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1366 {
1367         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1368         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1369         int result;
1370         /* populate MCLK dpm table to SMU7 */
1371         uint32_t array = data->dpm_table_start +
1372                         offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1373         uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1374                         SMU74_MAX_LEVELS_MEMORY;
1375         struct SMU74_Discrete_MemoryLevel *levels =
1376                         data->smc_state_table.MemoryLevel;
1377         uint32_t i;
1378
1379         for (i = 0; i < dpm_table->mclk_table.count; i++) {
1380                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1381                                 "can not populate memory level as memory clock is zero",
1382                                 return -EINVAL);
1383                 result = polaris10_populate_single_memory_level(hwmgr,
1384                                 dpm_table->mclk_table.dpm_levels[i].value,
1385                                 &levels[i]);
1386                 if (i == dpm_table->mclk_table.count - 1) {
1387                         levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1388                         levels[i].EnabledForActivity = 1;
1389                 }
1390                 if (result)
1391                         return result;
1392         }
1393
1394         /* in order to prevent MC activity from stutter mode to push DPM up.
1395          * the UVD change complements this by putting the MCLK in
1396          * a higher state by default such that we are not effected by
1397          * up threshold or and MCLK DPM latency.
1398          */
1399         levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
1400         CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1401
1402         data->smc_state_table.MemoryDpmLevelCount =
1403                         (uint8_t)dpm_table->mclk_table.count;
1404         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1405                         phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1406
1407         /* level count will send to smc once at init smc table and never change */
1408         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1409                         (uint32_t)array_size, data->sram_end);
1410
1411         return result;
1412 }
1413
1414 /**
1415 * Populates the SMC MVDD structure using the provided memory clock.
1416 *
1417 * @param    hwmgr      the address of the hardware manager
1418 * @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
1419 * @param    voltage     the SMC VOLTAGE structure to be populated
1420 */
1421 int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1422                 uint32_t mclk, SMIO_Pattern *smio_pat)
1423 {
1424         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1425         struct phm_ppt_v1_information *table_info =
1426                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1427         uint32_t i = 0;
1428
1429         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1430                 /* find mvdd value which clock is more than request */
1431                 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1432                         if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1433                                 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1434                                 break;
1435                         }
1436                 }
1437                 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1438                                 "MVDD Voltage is outside the supported range.",
1439                                 return -EINVAL);
1440         } else
1441                 return -EINVAL;
1442
1443         return 0;
1444 }
1445
1446 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1447                 SMU74_Discrete_DpmTable *table)
1448 {
1449         int result = 0;
1450         uint32_t sclk_frequency;
1451         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1452         struct phm_ppt_v1_information *table_info =
1453                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1454         SMIO_Pattern vol_level;
1455         uint32_t mvdd;
1456         uint16_t us_mvdd;
1457
1458         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1459
1460         if (!data->sclk_dpm_key_disabled) {
1461                 /* Get MinVoltage and Frequency from DPM0,
1462                  * already converted to SMC_UL */
1463                 sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
1464                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1465                                 table_info->vdd_dep_on_sclk,
1466                                 table->ACPILevel.SclkFrequency,
1467                                 &table->ACPILevel.MinVoltage, &mvdd);
1468                 PP_ASSERT_WITH_CODE((0 == result),
1469                                 "Cannot find ACPI VDDC voltage value "
1470                                 "in Clock Dependency Table", );
1471         } else {
1472                 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1473                 table->ACPILevel.MinVoltage =
1474                                 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
1475         }
1476
1477         result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency,  &(table->ACPILevel.SclkSetting));
1478         PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1479
1480         table->ACPILevel.DeepSleepDivId = 0;
1481         table->ACPILevel.CcPwrDynRm = 0;
1482         table->ACPILevel.CcPwrDynRm1 = 0;
1483
1484         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1485         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1486         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1487         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1488
1489         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1490         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1491         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1492         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1493         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1494         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1495         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1496         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1497         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1498         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1499
1500         if (!data->mclk_dpm_key_disabled) {
1501                 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1502                 table->MemoryACPILevel.MclkFrequency =
1503                                 data->dpm_table.mclk_table.dpm_levels[0].value;
1504                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1505                                 table_info->vdd_dep_on_mclk,
1506                                 table->MemoryACPILevel.MclkFrequency,
1507                                 &table->MemoryACPILevel.MinVoltage, &mvdd);
1508                 PP_ASSERT_WITH_CODE((0 == result),
1509                                 "Cannot find ACPI VDDCI voltage value "
1510                                 "in Clock Dependency Table",
1511                                 );
1512         } else {
1513                 table->MemoryACPILevel.MclkFrequency =
1514                                 data->vbios_boot_state.mclk_bootup_value;
1515                 table->MemoryACPILevel.MinVoltage =
1516                                 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
1517         }
1518
1519         us_mvdd = 0;
1520         if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1521                         (data->mclk_dpm_key_disabled))
1522                 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1523         else {
1524                 if (!polaris10_populate_mvdd_value(hwmgr,
1525                                 data->dpm_table.mclk_table.dpm_levels[0].value,
1526                                 &vol_level))
1527                         us_mvdd = vol_level.Voltage;
1528         }
1529
1530         if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1531                 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1532         else
1533                 table->MemoryACPILevel.MinMvdd = 0;
1534
1535         table->MemoryACPILevel.StutterEnable = false;
1536
1537         table->MemoryACPILevel.EnabledForThrottle = 0;
1538         table->MemoryACPILevel.EnabledForActivity = 0;
1539         table->MemoryACPILevel.UpHyst = 0;
1540         table->MemoryACPILevel.DownHyst = 100;
1541         table->MemoryACPILevel.VoltageDownHyst = 0;
1542         table->MemoryACPILevel.ActivityLevel =
1543                         PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1544
1545         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1546         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1547
1548         return result;
1549 }
1550
1551 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1552                 SMU74_Discrete_DpmTable *table)
1553 {
1554         int result = -EINVAL;
1555         uint8_t count;
1556         struct pp_atomctrl_clock_dividers_vi dividers;
1557         struct phm_ppt_v1_information *table_info =
1558                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1559         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1560                         table_info->mm_dep_table;
1561         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1562
1563         table->VceLevelCount = (uint8_t)(mm_table->count);
1564         table->VceBootLevel = 0;
1565
1566         for (count = 0; count < table->VceLevelCount; count++) {
1567                 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1568                 table->VceLevel[count].MinVoltage |=
1569                                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1570                 table->VceLevel[count].MinVoltage |=
1571                                 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
1572                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1573                 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1574
1575                 /*retrieve divider value for VBIOS */
1576                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1577                                 table->VceLevel[count].Frequency, &dividers);
1578                 PP_ASSERT_WITH_CODE((0 == result),
1579                                 "can not find divide id for VCE engine clock",
1580                                 return result);
1581
1582                 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1583
1584                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1585                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1586         }
1587         return result;
1588 }
1589
1590 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1591                 SMU74_Discrete_DpmTable *table)
1592 {
1593         int result = -EINVAL;
1594         uint8_t count;
1595         struct pp_atomctrl_clock_dividers_vi dividers;
1596         struct phm_ppt_v1_information *table_info =
1597                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1598         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1599                         table_info->mm_dep_table;
1600         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1601
1602         table->SamuBootLevel = 0;
1603         table->SamuLevelCount = (uint8_t)(mm_table->count);
1604
1605         for (count = 0; count < table->SamuLevelCount; count++) {
1606                 /* not sure whether we need evclk or not */
1607                 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1608                 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1609                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1610                 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1611                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1612                 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1613
1614                 /* retrieve divider value for VBIOS */
1615                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1616                                 table->SamuLevel[count].Frequency, &dividers);
1617                 PP_ASSERT_WITH_CODE((0 == result),
1618                                 "can not find divide id for samu clock", return result);
1619
1620                 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1621
1622                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1623                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1624         }
1625         return result;
1626 }
1627
1628 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1629                 int32_t eng_clock, int32_t mem_clock,
1630                 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1631 {
1632         uint32_t dram_timing;
1633         uint32_t dram_timing2;
1634         uint32_t burst_time;
1635         int result;
1636
1637         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1638                         eng_clock, mem_clock);
1639         PP_ASSERT_WITH_CODE(result == 0,
1640                         "Error calling VBIOS to set DRAM_TIMING.", return result);
1641
1642         dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1643         dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1644         burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1645
1646
1647         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
1648         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1649         arb_regs->McArbBurstTime   = (uint8_t)burst_time;
1650
1651         return 0;
1652 }
1653
1654 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1655 {
1656         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1657         struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1658         uint32_t i, j;
1659         int result = 0;
1660
1661         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1662                 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1663                         result = polaris10_populate_memory_timing_parameters(hwmgr,
1664                                         data->dpm_table.sclk_table.dpm_levels[i].value,
1665                                         data->dpm_table.mclk_table.dpm_levels[j].value,
1666                                         &arb_regs.entries[i][j]);
1667                         if (result == 0)
1668                                 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1669                         if (result != 0)
1670                                 return result;
1671                 }
1672         }
1673
1674         result = polaris10_copy_bytes_to_smc(
1675                         hwmgr->smumgr,
1676                         data->arb_table_start,
1677                         (uint8_t *)&arb_regs,
1678                         sizeof(SMU74_Discrete_MCArbDramTimingTable),
1679                         data->sram_end);
1680         return result;
1681 }
1682
1683 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1684                 struct SMU74_Discrete_DpmTable *table)
1685 {
1686         int result = -EINVAL;
1687         uint8_t count;
1688         struct pp_atomctrl_clock_dividers_vi dividers;
1689         struct phm_ppt_v1_information *table_info =
1690                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1691         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1692                         table_info->mm_dep_table;
1693         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1694
1695         table->UvdLevelCount = (uint8_t)(mm_table->count);
1696         table->UvdBootLevel = 0;
1697
1698         for (count = 0; count < table->UvdLevelCount; count++) {
1699                 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1700                 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1701                 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1702                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1703                 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1704                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1705                 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1706
1707                 /* retrieve divider value for VBIOS */
1708                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1709                                 table->UvdLevel[count].VclkFrequency, &dividers);
1710                 PP_ASSERT_WITH_CODE((0 == result),
1711                                 "can not find divide id for Vclk clock", return result);
1712
1713                 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1714
1715                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1716                                 table->UvdLevel[count].DclkFrequency, &dividers);
1717                 PP_ASSERT_WITH_CODE((0 == result),
1718                                 "can not find divide id for Dclk clock", return result);
1719
1720                 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1721
1722                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1723                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1724                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1725
1726         }
1727         return result;
1728 }
1729
1730 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1731                 struct SMU74_Discrete_DpmTable *table)
1732 {
1733         int result = 0;
1734         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1735
1736         table->GraphicsBootLevel = 0;
1737         table->MemoryBootLevel = 0;
1738
1739         /* find boot level from dpm table */
1740         result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1741                         data->vbios_boot_state.sclk_bootup_value,
1742                         (uint32_t *)&(table->GraphicsBootLevel));
1743
1744         result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1745                         data->vbios_boot_state.mclk_bootup_value,
1746                         (uint32_t *)&(table->MemoryBootLevel));
1747
1748         table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
1749                         VOLTAGE_SCALE;
1750         table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1751                         VOLTAGE_SCALE;
1752         table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
1753                         VOLTAGE_SCALE;
1754
1755         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1756         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1757         CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1758
1759         return 0;
1760 }
1761
1762
1763 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1764 {
1765         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1766         struct phm_ppt_v1_information *table_info =
1767                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1768         uint8_t count, level;
1769
1770         count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1771
1772         for (level = 0; level < count; level++) {
1773                 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1774                                 data->vbios_boot_state.sclk_bootup_value) {
1775                         data->smc_state_table.GraphicsBootLevel = level;
1776                         break;
1777                 }
1778         }
1779
1780         count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1781         for (level = 0; level < count; level++) {
1782                 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1783                                 data->vbios_boot_state.mclk_bootup_value) {
1784                         data->smc_state_table.MemoryBootLevel = level;
1785                         break;
1786                 }
1787         }
1788
1789         return 0;
1790 }
1791
1792 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1793 {
1794         uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
1795                         volt_with_cks, value;
1796         uint16_t clock_freq_u16;
1797         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1798         uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
1799                         volt_offset = 0;
1800         struct phm_ppt_v1_information *table_info =
1801                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1802         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1803                         table_info->vdd_dep_on_sclk;
1804
1805         stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1806
1807         /* Read SMU_Eefuse to read and calculate RO and determine
1808          * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1809          */
1810         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1811                         ixSMU_EFUSE_0 + (146 * 4));
1812         efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1813                         ixSMU_EFUSE_0 + (148 * 4));
1814         efuse &= 0xFF000000;
1815         efuse = efuse >> 24;
1816         efuse2 &= 0xF;
1817
1818         if (efuse2 == 1)
1819                 ro = (2300 - 1350) * efuse / 255 + 1350;
1820         else
1821                 ro = (2500 - 1000) * efuse / 255 + 1000;
1822
1823         if (ro >= 1660)
1824                 type = 0;
1825         else
1826                 type = 1;
1827
1828         /* Populate Stretch amount */
1829         data->smc_state_table.ClockStretcherAmount = stretch_amount;
1830
1831         /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1832         for (i = 0; i < sclk_table->count; i++) {
1833                 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1834                                 sclk_table->entries[i].cks_enable << i;
1835                 volt_without_cks = (uint32_t)((14041 *
1836                         (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
1837                         (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
1838                 volt_with_cks = (uint32_t)((13946 *
1839                         (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
1840                         (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
1841                 if (volt_without_cks >= volt_with_cks)
1842                         volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1843                                         sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
1844                 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1845         }
1846
1847         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1848                         STRETCH_ENABLE, 0x0);
1849         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1850                         masterReset, 0x1);
1851         /* PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, staticEnable, 0x1); */
1852         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1853                         masterReset, 0x0);
1854
1855         /* Populate CKS Lookup Table */
1856         if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1857                 stretch_amount2 = 0;
1858         else if (stretch_amount == 3 || stretch_amount == 4)
1859                 stretch_amount2 = 1;
1860         else {
1861                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1862                                 PHM_PlatformCaps_ClockStretcher);
1863                 PP_ASSERT_WITH_CODE(false,
1864                                 "Stretch Amount in PPTable not supported\n",
1865                                 return -EINVAL);
1866         }
1867
1868         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1869                         ixPWR_CKS_CNTL);
1870         value &= 0xFFC2FF87;
1871         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
1872                         polaris10_clock_stretcher_lookup_table[stretch_amount2][0];
1873         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
1874                         polaris10_clock_stretcher_lookup_table[stretch_amount2][1];
1875         clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
1876                         GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].SclkSetting.SclkFrequency) / 100);
1877         if (polaris10_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16
1878         && polaris10_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) {
1879                 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
1880                 value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
1881                 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
1882                 value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
1883                 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
1884                 value |= (polaris10_clock_stretch_amount_conversion
1885                                 [polaris10_clock_stretcher_lookup_table[stretch_amount2][3]]
1886                                  [stretch_amount]) << 3;
1887         }
1888         CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq);
1889         CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq);
1890         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
1891                         polaris10_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
1892         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
1893                         (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
1894
1895         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1896                         ixPWR_CKS_CNTL, value);
1897
1898         /* Populate DDT Lookup Table */
1899         for (i = 0; i < 4; i++) {
1900                 /* Assign the minimum and maximum VID stored
1901                  * in the last row of Clock Stretcher Voltage Table.
1902                  */
1903                 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].minVID =
1904                                 (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][2];
1905                 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].maxVID =
1906                                 (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][3];
1907                 /* Loop through each SCLK and check the frequency
1908                  * to see if it lies within the frequency for clock stretcher.
1909                  */
1910                 for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
1911                         cks_setting = 0;
1912                         clock_freq = PP_SMC_TO_HOST_UL(
1913                                         data->smc_state_table.GraphicsLevel[j].SclkSetting.SclkFrequency);
1914                         /* Check the allowed frequency against the sclk level[j].
1915                          *  Sclk's endianness has already been converted,
1916                          *  and it's in 10Khz unit,
1917                          *  as opposed to Data table, which is in Mhz unit.
1918                          */
1919                         if (clock_freq >= (polaris10_clock_stretcher_ddt_table[type][i][0]) * 100) {
1920                                 cks_setting |= 0x2;
1921                                 if (clock_freq < (polaris10_clock_stretcher_ddt_table[type][i][1]) * 100)
1922                                         cks_setting |= 0x1;
1923                         }
1924                         data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting
1925                                                         |= cks_setting << (j * 2);
1926                 }
1927                 CONVERT_FROM_HOST_TO_SMC_US(
1928                         data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting);
1929         }
1930
1931         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1932         value &= 0xFFFFFFFE;
1933         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1934
1935         return 0;
1936 }
1937
1938 /**
1939 * Populates the SMC VRConfig field in DPM table.
1940 *
1941 * @param    hwmgr   the address of the hardware manager
1942 * @param    table   the SMC DPM table structure to be populated
1943 * @return   always 0
1944 */
1945 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1946                 struct SMU74_Discrete_DpmTable *table)
1947 {
1948         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1949         uint16_t config;
1950
1951         config = VR_MERGED_WITH_VDDC;
1952         table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1953
1954         /* Set Vddc Voltage Controller */
1955         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1956                 config = VR_SVI2_PLANE_1;
1957                 table->VRConfig |= config;
1958         } else {
1959                 PP_ASSERT_WITH_CODE(false,
1960                                 "VDDC should be on SVI2 control in merged mode!",
1961                                 );
1962         }
1963         /* Set Vddci Voltage Controller */
1964         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1965                 config = VR_SVI2_PLANE_2;  /* only in merged mode */
1966                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1967         } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1968                 config = VR_SMIO_PATTERN_1;
1969                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1970         } else {
1971                 config = VR_STATIC_VOLTAGE;
1972                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1973         }
1974         /* Set Mvdd Voltage Controller */
1975         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1976                 config = VR_SVI2_PLANE_2;
1977                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1978         } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1979                 config = VR_SMIO_PATTERN_2;
1980                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1981         } else {
1982                 config = VR_STATIC_VOLTAGE;
1983                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1984         }
1985
1986         return 0;
1987 }
1988
1989 /**
1990 * Initializes the SMC table and uploads it
1991 *
1992 * @param    hwmgr  the address of the powerplay hardware manager.
1993 * @return   always 0
1994 */
1995 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1996 {
1997         int result;
1998         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1999         struct phm_ppt_v1_information *table_info =
2000                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2001         struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
2002         const struct polaris10_ulv_parm *ulv = &(data->ulv);
2003         uint8_t i;
2004         struct pp_atomctrl_gpio_pin_assignment gpio_pin;
2005         pp_atomctrl_clock_dividers_vi dividers;
2006
2007         result = polaris10_setup_default_dpm_tables(hwmgr);
2008         PP_ASSERT_WITH_CODE(0 == result,
2009                         "Failed to setup default DPM tables!", return result);
2010
2011         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
2012                 polaris10_populate_smc_voltage_tables(hwmgr, table);
2013
2014         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2015                         PHM_PlatformCaps_AutomaticDCTransition))
2016                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2017
2018         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2019                         PHM_PlatformCaps_StepVddc))
2020                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2021
2022         if (data->is_memory_gddr5)
2023                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2024
2025         if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2026                 result = polaris10_populate_ulv_state(hwmgr, table);
2027                 PP_ASSERT_WITH_CODE(0 == result,
2028                                 "Failed to initialize ULV state!", return result);
2029                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2030                                 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
2031         }
2032
2033         result = polaris10_populate_smc_link_level(hwmgr, table);
2034         PP_ASSERT_WITH_CODE(0 == result,
2035                         "Failed to initialize Link Level!", return result);
2036
2037         result = polaris10_populate_all_graphic_levels(hwmgr);
2038         PP_ASSERT_WITH_CODE(0 == result,
2039                         "Failed to initialize Graphics Level!", return result);
2040
2041         result = polaris10_populate_all_memory_levels(hwmgr);
2042         PP_ASSERT_WITH_CODE(0 == result,
2043                         "Failed to initialize Memory Level!", return result);
2044
2045         result = polaris10_populate_smc_acpi_level(hwmgr, table);
2046         PP_ASSERT_WITH_CODE(0 == result,
2047                         "Failed to initialize ACPI Level!", return result);
2048
2049         result = polaris10_populate_smc_vce_level(hwmgr, table);
2050         PP_ASSERT_WITH_CODE(0 == result,
2051                         "Failed to initialize VCE Level!", return result);
2052
2053         result = polaris10_populate_smc_samu_level(hwmgr, table);
2054         PP_ASSERT_WITH_CODE(0 == result,
2055                         "Failed to initialize SAMU Level!", return result);
2056
2057         /* Since only the initial state is completely set up at this point
2058          * (the other states are just copies of the boot state) we only
2059          * need to populate the  ARB settings for the initial state.
2060          */
2061         result = polaris10_program_memory_timing_parameters(hwmgr);
2062         PP_ASSERT_WITH_CODE(0 == result,
2063                         "Failed to Write ARB settings for the initial state.", return result);
2064
2065         result = polaris10_populate_smc_uvd_level(hwmgr, table);
2066         PP_ASSERT_WITH_CODE(0 == result,
2067                         "Failed to initialize UVD Level!", return result);
2068
2069         result = polaris10_populate_smc_boot_level(hwmgr, table);
2070         PP_ASSERT_WITH_CODE(0 == result,
2071                         "Failed to initialize Boot Level!", return result);
2072
2073         result = polaris10_populate_smc_initailial_state(hwmgr);
2074         PP_ASSERT_WITH_CODE(0 == result,
2075                         "Failed to initialize Boot State!", return result);
2076
2077         result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
2078         PP_ASSERT_WITH_CODE(0 == result,
2079                         "Failed to populate BAPM Parameters!", return result);
2080
2081         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2082                         PHM_PlatformCaps_ClockStretcher)) {
2083                 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
2084                 PP_ASSERT_WITH_CODE(0 == result,
2085                                 "Failed to populate Clock Stretcher Data Table!",
2086                                 return result);
2087         }
2088
2089         table->GraphicsVoltageChangeEnable  = 1;
2090         table->GraphicsThermThrottleEnable  = 1;
2091         table->GraphicsInterval = 1;
2092         table->VoltageInterval  = 1;
2093         table->ThermalInterval  = 1;
2094         table->TemperatureLimitHigh =
2095                         table_info->cac_dtp_table->usTargetOperatingTemp *
2096                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2097         table->TemperatureLimitLow  =
2098                         (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2099                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2100         table->MemoryVoltageChangeEnable = 1;
2101         table->MemoryInterval = 1;
2102         table->VoltageResponseTime = 0;
2103         table->PhaseResponseTime = 0;
2104         table->MemoryThermThrottleEnable = 1;
2105         table->PCIeBootLinkLevel = 0;
2106         table->PCIeGenInterval = 1;
2107
2108         result = polaris10_populate_vr_config(hwmgr, table);
2109         PP_ASSERT_WITH_CODE(0 == result,
2110                         "Failed to populate VRConfig setting!", return result);
2111
2112         table->ThermGpio = 17;
2113         table->SclkStepSize = 0x4000;
2114
2115         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2116                 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2117         } else {
2118                 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
2119                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2120                                 PHM_PlatformCaps_RegulatorHot);
2121         }
2122
2123         if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2124                         &gpio_pin)) {
2125                 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2126                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2127                                 PHM_PlatformCaps_AutomaticDCTransition);
2128         } else {
2129                 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
2130                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2131                                 PHM_PlatformCaps_AutomaticDCTransition);
2132         }
2133
2134         /* Thermal Output GPIO */
2135         if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2136                         &gpio_pin)) {
2137                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2138                                 PHM_PlatformCaps_ThermalOutGPIO);
2139
2140                 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2141
2142                 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2143                  * since VBIOS will program this register to set 'inactive state',
2144                  * driver can then determine 'active state' from this and
2145                  * program SMU with correct polarity
2146                  */
2147                 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2148                                         & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2149                 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2150
2151                 /* if required, combine VRHot/PCC with thermal out GPIO */
2152                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2153                 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2154                         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2155         } else {
2156                 table->ThermOutGpio = 17;
2157                 table->ThermOutPolarity = 1;
2158                 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2159         }
2160
2161         /* Populate BIF_SCLK levels into SMC DPM table */
2162         for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2163                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], &dividers);
2164                 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2165
2166                 if (i == 0)
2167                         table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2168                 else
2169                         table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2170         }
2171
2172         for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2173                 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2174
2175         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2176         CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2177         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2178         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2179         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2180         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2181         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2182         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2183         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2184
2185         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2186         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
2187                         data->dpm_table_start +
2188                         offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2189                         (uint8_t *)&(table->SystemFlags),
2190                         sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2191                         data->sram_end);
2192         PP_ASSERT_WITH_CODE(0 == result,
2193                         "Failed to upload dpm data to SMC memory!", return result);
2194
2195         return 0;
2196 }
2197
2198 /**
2199 * Initialize the ARB DRAM timing table's index field.
2200 *
2201 * @param    hwmgr  the address of the powerplay hardware manager.
2202 * @return   always 0
2203 */
2204 static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
2205 {
2206         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2207         uint32_t tmp;
2208         int result;
2209
2210         /* This is a read-modify-write on the first byte of the ARB table.
2211          * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2212          * is the field 'current'.
2213          * This solution is ugly, but we never write the whole table only
2214          * individual fields in it.
2215          * In reality this field should not be in that structure
2216          * but in a soft register.
2217          */
2218         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
2219                         data->arb_table_start, &tmp, data->sram_end);
2220
2221         if (result)
2222                 return result;
2223
2224         tmp &= 0x00FFFFFF;
2225         tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2226
2227         return polaris10_write_smc_sram_dword(hwmgr->smumgr,
2228                         data->arb_table_start, tmp, data->sram_end);
2229 }
2230
2231 static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
2232 {
2233         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2234                         PHM_PlatformCaps_RegulatorHot))
2235                 return smum_send_msg_to_smc(hwmgr->smumgr,
2236                                 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2237
2238         return 0;
2239 }
2240
2241 static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
2242 {
2243         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2244                         SCLK_PWRMGT_OFF, 0);
2245         return 0;
2246 }
2247
2248 static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
2249 {
2250         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2251         struct polaris10_ulv_parm *ulv = &(data->ulv);
2252
2253         if (ulv->ulv_supported)
2254                 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2255
2256         return 0;
2257 }
2258
2259 static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2260 {
2261         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2262                         PHM_PlatformCaps_SclkDeepSleep)) {
2263                 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2264                         PP_ASSERT_WITH_CODE(false,
2265                                         "Attempt to enable Master Deep Sleep switch failed!",
2266                                         return -1);
2267         } else {
2268                 if (smum_send_msg_to_smc(hwmgr->smumgr,
2269                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2270                         PP_ASSERT_WITH_CODE(false,
2271                                         "Attempt to disable Master Deep Sleep switch failed!",
2272                                         return -1);
2273                 }
2274         }
2275
2276         return 0;
2277 }
2278
2279 static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2280 {
2281         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2282
2283         /* enable SCLK dpm */
2284         if (!data->sclk_dpm_key_disabled)
2285                 PP_ASSERT_WITH_CODE(
2286                 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2287                 "Failed to enable SCLK DPM during DPM Start Function!",
2288                 return -1);
2289
2290         /* enable MCLK dpm */
2291         if (0 == data->mclk_dpm_key_disabled) {
2292
2293                 PP_ASSERT_WITH_CODE(
2294                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2295                                                 PPSMC_MSG_MCLKDPM_Enable)),
2296                                 "Failed to enable MCLK DPM during DPM Start Function!",
2297                                 return -1);
2298
2299
2300                 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2301
2302                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2303                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2304                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2305                 udelay(10);
2306                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2307                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2308                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2309         }
2310
2311         return 0;
2312 }
2313
2314 static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
2315 {
2316         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2317
2318         /*enable general power management */
2319
2320         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2321                         GLOBAL_PWRMGT_EN, 1);
2322
2323         /* enable sclk deep sleep */
2324
2325         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2326                         DYNAMIC_PM_EN, 1);
2327
2328         /* prepare for PCIE DPM */
2329
2330         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2331                         data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2332                                         VoltageChangeTimeout), 0x1000);
2333         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2334                         SWRST_COMMAND_1, RESETLC, 0x0);
2335 /*
2336         PP_ASSERT_WITH_CODE(
2337                         (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2338                                         PPSMC_MSG_Voltage_Cntl_Enable)),
2339                         "Failed to enable voltage DPM during DPM Start Function!",
2340                         return -1);
2341 */
2342
2343         if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
2344                 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2345                 return -1;
2346         }
2347
2348         /* enable PCIE dpm */
2349         if (0 == data->pcie_dpm_key_disabled) {
2350                 PP_ASSERT_WITH_CODE(
2351                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2352                                                 PPSMC_MSG_PCIeDPM_Enable)),
2353                                 "Failed to enable pcie DPM during DPM Start Function!",
2354                                 return -1);
2355         }
2356
2357         PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2358                                         PPSMC_MSG_EnableACDCGPIOInterrupt)),
2359                                         "Failed to enable AC DC GPIO Interrupt!",
2360                         );
2361
2362         return 0;
2363 }
2364
2365 static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
2366 {
2367         bool protection;
2368         enum DPM_EVENT_SRC src;
2369
2370         switch (sources) {
2371         default:
2372                 printk(KERN_ERR "Unknown throttling event sources.");
2373                 /* fall through */
2374         case 0:
2375                 protection = false;
2376                 /* src is unused */
2377                 break;
2378         case (1 << PHM_AutoThrottleSource_Thermal):
2379                 protection = true;
2380                 src = DPM_EVENT_SRC_DIGITAL;
2381                 break;
2382         case (1 << PHM_AutoThrottleSource_External):
2383                 protection = true;
2384                 src = DPM_EVENT_SRC_EXTERNAL;
2385                 break;
2386         case (1 << PHM_AutoThrottleSource_External) |
2387                         (1 << PHM_AutoThrottleSource_Thermal):
2388                 protection = true;
2389                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2390                 break;
2391         }
2392         /* Order matters - don't enable thermal protection for the wrong source. */
2393         if (protection) {
2394                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2395                                 DPM_EVENT_SRC, src);
2396                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2397                                 THERMAL_PROTECTION_DIS,
2398                                 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2399                                                 PHM_PlatformCaps_ThermalController));
2400         } else
2401                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2402                                 THERMAL_PROTECTION_DIS, 1);
2403 }
2404
2405 static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2406                 PHM_AutoThrottleSource source)
2407 {
2408         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2409
2410         if (!(data->active_auto_throttle_sources & (1 << source))) {
2411                 data->active_auto_throttle_sources |= 1 << source;
2412                 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2413         }
2414         return 0;
2415 }
2416
2417 static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2418 {
2419         return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2420 }
2421
2422 int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
2423 {
2424         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2425         data->pcie_performance_request = true;
2426
2427         return 0;
2428 }
2429
2430 int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2431 {
2432         int tmp_result, result = 0;
2433         tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2434         PP_ASSERT_WITH_CODE(result == 0,
2435                         "DPM is already running right now, no need to enable DPM!",
2436                         return 0);
2437
2438         if (polaris10_voltage_control(hwmgr)) {
2439                 tmp_result = polaris10_enable_voltage_control(hwmgr);
2440                 PP_ASSERT_WITH_CODE(tmp_result == 0,
2441                                 "Failed to enable voltage control!",
2442                                 result = tmp_result);
2443
2444                 tmp_result = polaris10_construct_voltage_tables(hwmgr);
2445                 PP_ASSERT_WITH_CODE((0 == tmp_result),
2446                                 "Failed to contruct voltage tables!",
2447                                 result = tmp_result);
2448         }
2449
2450         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2451                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2452                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2453                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2454
2455         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2456                         PHM_PlatformCaps_ThermalController))
2457                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2458                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2459
2460         tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
2461         PP_ASSERT_WITH_CODE((0 == tmp_result),
2462                         "Failed to program static screen threshold parameters!",
2463                         result = tmp_result);
2464
2465         tmp_result = polaris10_enable_display_gap(hwmgr);
2466         PP_ASSERT_WITH_CODE((0 == tmp_result),
2467                         "Failed to enable display gap!", result = tmp_result);
2468
2469         tmp_result = polaris10_program_voting_clients(hwmgr);
2470         PP_ASSERT_WITH_CODE((0 == tmp_result),
2471                         "Failed to program voting clients!", result = tmp_result);
2472
2473         tmp_result = polaris10_process_firmware_header(hwmgr);
2474         PP_ASSERT_WITH_CODE((0 == tmp_result),
2475                         "Failed to process firmware header!", result = tmp_result);
2476
2477         tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
2478         PP_ASSERT_WITH_CODE((0 == tmp_result),
2479                         "Failed to initialize switch from ArbF0 to F1!",
2480                         result = tmp_result);
2481
2482         tmp_result = polaris10_init_smc_table(hwmgr);
2483         PP_ASSERT_WITH_CODE((0 == tmp_result),
2484                         "Failed to initialize SMC table!", result = tmp_result);
2485
2486         tmp_result = polaris10_init_arb_table_index(hwmgr);
2487         PP_ASSERT_WITH_CODE((0 == tmp_result),
2488                         "Failed to initialize ARB table index!", result = tmp_result);
2489
2490         tmp_result = polaris10_populate_pm_fuses(hwmgr);
2491         PP_ASSERT_WITH_CODE((0 == tmp_result),
2492                         "Failed to populate PM fuses!", result = tmp_result);
2493
2494         tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
2495         PP_ASSERT_WITH_CODE((0 == tmp_result),
2496                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2497
2498         tmp_result = polaris10_enable_sclk_control(hwmgr);
2499         PP_ASSERT_WITH_CODE((0 == tmp_result),
2500                         "Failed to enable SCLK control!", result = tmp_result);
2501
2502         tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
2503         PP_ASSERT_WITH_CODE((0 == tmp_result),
2504                         "Failed to enable voltage control!", result = tmp_result);
2505
2506         tmp_result = polaris10_enable_ulv(hwmgr);
2507         PP_ASSERT_WITH_CODE((0 == tmp_result),
2508                         "Failed to enable ULV!", result = tmp_result);
2509
2510         tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
2511         PP_ASSERT_WITH_CODE((0 == tmp_result),
2512                         "Failed to enable deep sleep master switch!", result = tmp_result);
2513
2514         tmp_result = polaris10_start_dpm(hwmgr);
2515         PP_ASSERT_WITH_CODE((0 == tmp_result),
2516                         "Failed to start DPM!", result = tmp_result);
2517
2518         tmp_result = polaris10_enable_smc_cac(hwmgr);
2519         PP_ASSERT_WITH_CODE((0 == tmp_result),
2520                         "Failed to enable SMC CAC!", result = tmp_result);
2521
2522         tmp_result = polaris10_enable_power_containment(hwmgr);
2523         PP_ASSERT_WITH_CODE((0 == tmp_result),
2524                         "Failed to enable power containment!", result = tmp_result);
2525
2526         tmp_result = polaris10_power_control_set_level(hwmgr);
2527         PP_ASSERT_WITH_CODE((0 == tmp_result),
2528                         "Failed to power control set level!", result = tmp_result);
2529
2530         tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
2531         PP_ASSERT_WITH_CODE((0 == tmp_result),
2532                         "Failed to enable thermal auto throttle!", result = tmp_result);
2533
2534         tmp_result = polaris10_pcie_performance_request(hwmgr);
2535         PP_ASSERT_WITH_CODE((0 == tmp_result),
2536                         "Failed to enable thermal auto throttle!", result = tmp_result);
2537
2538         return result;
2539 }
2540
2541 int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2542 {
2543
2544         return 0;
2545 }
2546
2547 int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
2548 {
2549
2550         return 0;
2551 }
2552
2553 int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2554 {
2555         return phm_hwmgr_backend_fini(hwmgr);
2556 }
2557
2558 int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
2559 {
2560         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2561
2562         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2563                         PHM_PlatformCaps_SclkDeepSleep);
2564
2565         if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2566                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2567                                 PHM_PlatformCaps_EnableMVDDControl);
2568
2569         if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2570                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2571                                 PHM_PlatformCaps_ControlVDDCI);
2572
2573         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2574                          PHM_PlatformCaps_TablelessHardwareInterface);
2575
2576         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2577                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
2578
2579         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2580                         PHM_PlatformCaps_DynamicPowerManagement);
2581
2582         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2583                         PHM_PlatformCaps_TablelessHardwareInterface);
2584
2585         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2586                                         PHM_PlatformCaps_SMC);
2587
2588         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2589                                         PHM_PlatformCaps_NonABMSupportInPPLib);
2590
2591         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2592                                         PHM_PlatformCaps_DynamicUVDState);
2593
2594         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2595                                 PHM_PlatformCaps_SclkThrottleLowNotification);
2596
2597         /* power tune caps Assume disabled */
2598         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2599                                         PHM_PlatformCaps_PowerContainment);
2600         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2601                                                         PHM_PlatformCaps_CAC);
2602         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2603                                                 PHM_PlatformCaps_SQRamping);
2604         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2605                                                 PHM_PlatformCaps_DBRamping);
2606         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2607                                                 PHM_PlatformCaps_TDRamping);
2608         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2609                                                 PHM_PlatformCaps_TCPRamping);
2610
2611         if (hwmgr->chip_id == CHIP_POLARIS11)
2612                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2613                                         PHM_PlatformCaps_SPLLShutdownSupport);
2614         return 0;
2615 }
2616
2617 static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
2618 {
2619         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2620
2621         polaris10_initialize_power_tune_defaults(hwmgr);
2622
2623         data->pcie_gen_performance.max = PP_PCIEGen1;
2624         data->pcie_gen_performance.min = PP_PCIEGen3;
2625         data->pcie_gen_power_saving.max = PP_PCIEGen1;
2626         data->pcie_gen_power_saving.min = PP_PCIEGen3;
2627         data->pcie_lane_performance.max = 0;
2628         data->pcie_lane_performance.min = 16;
2629         data->pcie_lane_power_saving.max = 0;
2630         data->pcie_lane_power_saving.min = 16;
2631 }
2632
2633 /**
2634 * Get Leakage VDDC based on leakage ID.
2635 *
2636 * @param    hwmgr  the address of the powerplay hardware manager.
2637 * @return   always 0
2638 */
2639 static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
2640 {
2641         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2642         uint16_t vv_id;
2643         uint16_t vddc = 0;
2644         uint16_t i, j;
2645         uint32_t sclk = 0;
2646         struct phm_ppt_v1_information *table_info =
2647                         (struct phm_ppt_v1_information *)hwmgr->pptable;
2648         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2649                         table_info->vdd_dep_on_sclk;
2650         int result;
2651
2652         for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
2653                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2654                 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2655                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
2656                         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2657                                         PHM_PlatformCaps_ClockStretcher)) {
2658                                 for (j = 1; j < sclk_table->count; j++) {
2659                                         if (sclk_table->entries[j].clk == sclk &&
2660                                                         sclk_table->entries[j].cks_enable == 0) {
2661                                                 sclk += 5000;
2662                                                 break;
2663                                         }
2664                                 }
2665                         }
2666
2667
2668                         PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2669                                                         VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
2670                                                 "Error retrieving EVV voltage value!",
2671                                                 continue);
2672
2673
2674                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
2675                         PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
2676                                         "Invalid VDDC value", result = -EINVAL;);
2677
2678                         /* the voltage should not be zero nor equal to leakage ID */
2679                         if (vddc != 0 && vddc != vv_id) {
2680                                 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2681                                 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2682                                 data->vddc_leakage.count++;
2683                         }
2684                 }
2685         }
2686
2687         return 0;
2688 }
2689
2690 /**
2691  * Change virtual leakage voltage to actual value.
2692  *
2693  * @param     hwmgr  the address of the powerplay hardware manager.
2694  * @param     pointer to changing voltage
2695  * @param     pointer to leakage table
2696  */
2697 static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2698                 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
2699 {
2700         uint32_t index;
2701
2702         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2703         for (index = 0; index < leakage_table->count; index++) {
2704                 /* if this voltage matches a leakage voltage ID */
2705                 /* patch with actual leakage voltage */
2706                 if (leakage_table->leakage_id[index] == *voltage) {
2707                         *voltage = leakage_table->actual_voltage[index];
2708                         break;
2709                 }
2710         }
2711
2712         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2713                 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2714 }
2715
2716 /**
2717 * Patch voltage lookup table by EVV leakages.
2718 *
2719 * @param     hwmgr  the address of the powerplay hardware manager.
2720 * @param     pointer to voltage lookup table
2721 * @param     pointer to leakage table
2722 * @return     always 0
2723 */
2724 static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
2725                 phm_ppt_v1_voltage_lookup_table *lookup_table,
2726                 struct polaris10_leakage_voltage *leakage_table)
2727 {
2728         uint32_t i;
2729
2730         for (i = 0; i < lookup_table->count; i++)
2731                 polaris10_patch_with_vdd_leakage(hwmgr,
2732                                 &lookup_table->entries[i].us_vdd, leakage_table);
2733
2734         return 0;
2735 }
2736
2737 static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2738                 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
2739                 uint16_t *vddc)
2740 {
2741         struct phm_ppt_v1_information *table_info =
2742                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2743         polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
2744         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2745                         table_info->max_clock_voltage_on_dc.vddc;
2746         return 0;
2747 }
2748
2749 static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
2750                 struct pp_hwmgr *hwmgr)
2751 {
2752         uint8_t entryId;
2753         uint8_t voltageId;
2754         struct phm_ppt_v1_information *table_info =
2755                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2756
2757         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2758                         table_info->vdd_dep_on_sclk;
2759         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2760                         table_info->vdd_dep_on_mclk;
2761         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2762                         table_info->mm_dep_table;
2763
2764         for (entryId = 0; entryId < sclk_table->count; ++entryId) {
2765                 voltageId = sclk_table->entries[entryId].vddInd;
2766                 sclk_table->entries[entryId].vddc =
2767                                 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2768         }
2769
2770         for (entryId = 0; entryId < mclk_table->count; ++entryId) {
2771                 voltageId = mclk_table->entries[entryId].vddInd;
2772                 mclk_table->entries[entryId].vddc =
2773                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2774         }
2775
2776         for (entryId = 0; entryId < mm_table->count; ++entryId) {
2777                 voltageId = mm_table->entries[entryId].vddcInd;
2778                 mm_table->entries[entryId].vddc =
2779                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2780         }
2781
2782         return 0;
2783
2784 }
2785
2786 static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
2787 {
2788         /* Need to determine if we need calculated voltage. */
2789         return 0;
2790 }
2791
2792 static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
2793 {
2794         /* Need to determine if we need calculated voltage from mm table. */
2795         return 0;
2796 }
2797
2798 static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
2799                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
2800 {
2801         uint32_t table_size, i, j;
2802         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
2803         table_size = lookup_table->count;
2804
2805         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2806                 "Lookup table is empty", return -EINVAL);
2807
2808         /* Sorting voltages */
2809         for (i = 0; i < table_size - 1; i++) {
2810                 for (j = i + 1; j > 0; j--) {
2811                         if (lookup_table->entries[j].us_vdd <
2812                                         lookup_table->entries[j - 1].us_vdd) {
2813                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
2814                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
2815                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
2816                         }
2817                 }
2818         }
2819
2820         return 0;
2821 }
2822
2823 static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
2824 {
2825         int result = 0;
2826         int tmp_result;
2827         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2828         struct phm_ppt_v1_information *table_info =
2829                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2830
2831         tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
2832                         table_info->vddc_lookup_table, &(data->vddc_leakage));
2833         if (tmp_result)
2834                 result = tmp_result;
2835
2836         tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
2837                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2838         if (tmp_result)
2839                 result = tmp_result;
2840
2841         tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
2842         if (tmp_result)
2843                 result = tmp_result;
2844
2845         tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
2846         if (tmp_result)
2847                 result = tmp_result;
2848
2849         tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
2850         if (tmp_result)
2851                 result = tmp_result;
2852
2853         tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
2854         if (tmp_result)
2855                 result = tmp_result;
2856
2857         return result;
2858 }
2859
2860 static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
2861 {
2862         struct phm_ppt_v1_information *table_info =
2863                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2864
2865         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2866                                                 table_info->vdd_dep_on_sclk;
2867         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2868                                                 table_info->vdd_dep_on_mclk;
2869
2870         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2871                 "VDD dependency on SCLK table is missing.       \
2872                 This table is mandatory", return -EINVAL);
2873         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2874                 "VDD dependency on SCLK table has to have is missing.   \
2875                 This table is mandatory", return -EINVAL);
2876
2877         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2878                 "VDD dependency on MCLK table is missing.       \
2879                 This table is mandatory", return -EINVAL);
2880         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2881                 "VDD dependency on MCLK table has to have is missing.    \
2882                 This table is mandatory", return -EINVAL);
2883
2884         table_info->max_clock_voltage_on_ac.sclk =
2885                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2886         table_info->max_clock_voltage_on_ac.mclk =
2887                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2888         table_info->max_clock_voltage_on_ac.vddc =
2889                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2890         table_info->max_clock_voltage_on_ac.vddci =
2891                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2892
2893         return 0;
2894 }
2895
2896 int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2897 {
2898         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2899         struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2900         uint32_t temp_reg;
2901         int result;
2902
2903         data->dll_default_on = false;
2904         data->sram_end = SMC_RAM_END;
2905
2906         data->disable_dpm_mask = 0xFF;
2907         data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2908         data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2909         data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2910         data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2911         data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2912         data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2913         data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2914         data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2915         data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2916         data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2917
2918         data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
2919         data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
2920         data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
2921         data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
2922         data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
2923         data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
2924         data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
2925         data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
2926
2927         data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
2928
2929         data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
2930
2931         /* need to set voltage control types before EVV patching */
2932         data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2933         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2934         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2935
2936         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2937                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
2938                 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2939
2940         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2941                 PHM_PlatformCaps_DynamicPatchPowerState);
2942
2943         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2944                         PHM_PlatformCaps_EnableMVDDControl)) {
2945                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2946                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
2947                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
2948                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2949                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
2950                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2951         }
2952
2953         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2954                         PHM_PlatformCaps_ControlVDDCI)) {
2955                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2956                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
2957                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
2958                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2959                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
2960                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2961         }
2962
2963         polaris10_set_features_platform_caps(hwmgr);
2964
2965         polaris10_init_dpm_defaults(hwmgr);
2966
2967         /* Get leakage voltage based on leakage ID. */
2968         result = polaris10_get_evv_voltages(hwmgr);
2969
2970         if (result) {
2971                 printk("Get EVV Voltage Failed.  Abort Driver loading!\n");
2972                 return -1;
2973         }
2974
2975         polaris10_complete_dependency_tables(hwmgr);
2976         polaris10_set_private_data_based_on_pptable(hwmgr);
2977
2978         /* Initalize Dynamic State Adjustment Rule Settings */
2979         result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
2980
2981         if (0 == result) {
2982                 struct cgs_system_info sys_info = {0};
2983
2984                 data->is_tlu_enabled = 0;
2985
2986                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
2987                                                         POLARIS10_MAX_HARDWARE_POWERLEVELS;
2988                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
2989                 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
2990                 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
2991 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
2992                 hwmgr->platform_descriptor.clockStep.engineClock = 500;
2993                 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
2994
2995                 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
2996                         temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
2997                         switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
2998                         case 0:
2999                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3000                                 break;
3001                         case 1:
3002                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3003                                 break;
3004                         case 2:
3005                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3006                                 break;
3007                         case 3:
3008                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3009                                 break;
3010                         case 4:
3011                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3012                                 break;
3013                         default:
3014                                 PP_ASSERT_WITH_CODE(0,
3015                                 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3016                                 );
3017                                 break;
3018                         }
3019                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3020                 }
3021
3022                 sys_info.size = sizeof(struct cgs_system_info);
3023                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3024                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3025                 if (result)
3026                         data->pcie_gen_cap = 0x30007;
3027                 else
3028                         data->pcie_gen_cap = (uint32_t)sys_info.value;
3029                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3030                         data->pcie_spc_cap = 20;
3031                 sys_info.size = sizeof(struct cgs_system_info);
3032                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3033                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3034                 if (result)
3035                         data->pcie_lane_cap = 0x2f0000;
3036                 else
3037                         data->pcie_lane_cap = (uint32_t)sys_info.value;
3038         } else {
3039                 /* Ignore return value in here, we are cleaning up a mess. */
3040                 polaris10_hwmgr_backend_fini(hwmgr);
3041         }
3042
3043         return 0;
3044 }
3045
3046 static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3047 {
3048         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3049         uint32_t level, tmp;
3050
3051         if (!data->pcie_dpm_key_disabled) {
3052                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3053                         level = 0;
3054                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3055                         while (tmp >>= 1)
3056                                 level++;
3057
3058                         if (level)
3059                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3060                                                 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3061                 }
3062         }
3063
3064         if (!data->sclk_dpm_key_disabled) {
3065                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3066                         level = 0;
3067                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3068                         while (tmp >>= 1)
3069                                 level++;
3070
3071                         if (level)
3072                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3073                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3074                                                 (1 << level));
3075                 }
3076         }
3077
3078         if (!data->mclk_dpm_key_disabled) {
3079                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3080                         level = 0;
3081                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3082                         while (tmp >>= 1)
3083                                 level++;
3084
3085                         if (level)
3086                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3087                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3088                                                 (1 << level));
3089                 }
3090         }
3091
3092         return 0;
3093 }
3094
3095 static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3096 {
3097         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3098
3099         phm_apply_dal_min_voltage_request(hwmgr);
3100
3101         if (!data->sclk_dpm_key_disabled) {
3102                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3103                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3104                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
3105                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3106         }
3107
3108         if (!data->mclk_dpm_key_disabled) {
3109                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3110                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3111                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
3112                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3113         }
3114
3115         return 0;
3116 }
3117
3118 static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3119 {
3120         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3121
3122         if (!polaris10_is_dpm_running(hwmgr))
3123                 return -EINVAL;
3124
3125         if (!data->pcie_dpm_key_disabled) {
3126                 smum_send_msg_to_smc(hwmgr->smumgr,
3127                                 PPSMC_MSG_PCIeDPM_UnForceLevel);
3128         }
3129
3130         return polaris10_upload_dpm_level_enable_mask(hwmgr);
3131 }
3132
3133 static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3134 {
3135         struct polaris10_hwmgr *data =
3136                         (struct polaris10_hwmgr *)(hwmgr->backend);
3137         uint32_t level;
3138
3139         if (!data->sclk_dpm_key_disabled)
3140                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3141                         level = phm_get_lowest_enabled_level(hwmgr,
3142                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3143                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3144                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
3145                                                             (1 << level));
3146
3147         }
3148
3149         if (!data->mclk_dpm_key_disabled) {
3150                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3151                         level = phm_get_lowest_enabled_level(hwmgr,
3152                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3153                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3154                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
3155                                                             (1 << level));
3156                 }
3157         }
3158
3159         if (!data->pcie_dpm_key_disabled) {
3160                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3161                         level = phm_get_lowest_enabled_level(hwmgr,
3162                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3163                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3164                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
3165                                                             (level));
3166                 }
3167         }
3168
3169         return 0;
3170
3171 }
3172 static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
3173                                 enum amd_dpm_forced_level level)
3174 {
3175         int ret = 0;
3176
3177         switch (level) {
3178         case AMD_DPM_FORCED_LEVEL_HIGH:
3179                 ret = polaris10_force_dpm_highest(hwmgr);
3180                 if (ret)
3181                         return ret;
3182                 break;
3183         case AMD_DPM_FORCED_LEVEL_LOW:
3184                 ret = polaris10_force_dpm_lowest(hwmgr);
3185                 if (ret)
3186                         return ret;
3187                 break;
3188         case AMD_DPM_FORCED_LEVEL_AUTO:
3189                 ret = polaris10_unforce_dpm_levels(hwmgr);
3190                 if (ret)
3191                         return ret;
3192                 break;
3193         default:
3194                 break;
3195         }
3196
3197         hwmgr->dpm_level = level;
3198
3199         return ret;
3200 }
3201
3202 static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
3203 {
3204         return sizeof(struct polaris10_power_state);
3205 }
3206
3207
3208 static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3209                                 struct pp_power_state *request_ps,
3210                         const struct pp_power_state *current_ps)
3211 {
3212
3213         struct polaris10_power_state *polaris10_ps =
3214                                 cast_phw_polaris10_power_state(&request_ps->hardware);
3215         uint32_t sclk;
3216         uint32_t mclk;
3217         struct PP_Clocks minimum_clocks = {0};
3218         bool disable_mclk_switching;
3219         bool disable_mclk_switching_for_frame_lock;
3220         struct cgs_display_info info = {0};
3221         const struct phm_clock_and_voltage_limits *max_limits;
3222         uint32_t i;
3223         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3224         struct phm_ppt_v1_information *table_info =
3225                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3226         int32_t count;
3227         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3228
3229         data->battery_state = (PP_StateUILabel_Battery ==
3230                         request_ps->classification.ui_label);
3231
3232         PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
3233                                  "VI should always have 2 performance levels",
3234                                 );
3235
3236         max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3237                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3238                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3239
3240         /* Cap clock DPM tables at DC MAX if it is in DC. */
3241         if (PP_PowerSource_DC == hwmgr->power_source) {
3242                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3243                         if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3244                                 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3245                         if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3246                                 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
3247                 }
3248         }
3249
3250         polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3251         polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3252
3253         cgs_get_active_displays_info(hwmgr->device, &info);
3254
3255         /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3256
3257         /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3258
3259         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3260                         PHM_PlatformCaps_StablePState)) {
3261                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3262                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3263
3264                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3265                                 count >= 0; count--) {
3266                         if (stable_pstate_sclk >=
3267                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3268                                 stable_pstate_sclk =
3269                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3270                                 break;
3271                         }
3272                 }
3273
3274                 if (count < 0)
3275                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3276
3277                 stable_pstate_mclk = max_limits->mclk;
3278
3279                 minimum_clocks.engineClock = stable_pstate_sclk;
3280                 minimum_clocks.memoryClock = stable_pstate_mclk;
3281         }
3282
3283         if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3284                 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3285
3286         if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3287                 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3288
3289         polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3290
3291         if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3292                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3293                                 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3294                                 "Overdrive sclk exceeds limit",
3295                                 hwmgr->gfx_arbiter.sclk_over_drive =
3296                                                 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3297
3298                 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3299                         polaris10_ps->performance_levels[1].engine_clock =
3300                                         hwmgr->gfx_arbiter.sclk_over_drive;
3301         }
3302
3303         if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3304                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3305                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3306                                 "Overdrive mclk exceeds limit",
3307                                 hwmgr->gfx_arbiter.mclk_over_drive =
3308                                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3309
3310                 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3311                         polaris10_ps->performance_levels[1].memory_clock =
3312                                         hwmgr->gfx_arbiter.mclk_over_drive;
3313         }
3314
3315         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3316                                     hwmgr->platform_descriptor.platformCaps,
3317                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3318
3319         disable_mclk_switching = (1 < info.display_count) ||
3320                                     disable_mclk_switching_for_frame_lock;
3321
3322         sclk = polaris10_ps->performance_levels[0].engine_clock;
3323         mclk = polaris10_ps->performance_levels[0].memory_clock;
3324
3325         if (disable_mclk_switching)
3326                 mclk = polaris10_ps->performance_levels
3327                 [polaris10_ps->performance_level_count - 1].memory_clock;
3328
3329         if (sclk < minimum_clocks.engineClock)
3330                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3331                                 max_limits->sclk : minimum_clocks.engineClock;
3332
3333         if (mclk < minimum_clocks.memoryClock)
3334                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3335                                 max_limits->mclk : minimum_clocks.memoryClock;
3336
3337         polaris10_ps->performance_levels[0].engine_clock = sclk;
3338         polaris10_ps->performance_levels[0].memory_clock = mclk;
3339
3340         polaris10_ps->performance_levels[1].engine_clock =
3341                 (polaris10_ps->performance_levels[1].engine_clock >=
3342                                 polaris10_ps->performance_levels[0].engine_clock) ?
3343                                                 polaris10_ps->performance_levels[1].engine_clock :
3344                                                 polaris10_ps->performance_levels[0].engine_clock;
3345
3346         if (disable_mclk_switching) {
3347                 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3348                         mclk = polaris10_ps->performance_levels[1].memory_clock;
3349
3350                 polaris10_ps->performance_levels[0].memory_clock = mclk;
3351                 polaris10_ps->performance_levels[1].memory_clock = mclk;
3352         } else {
3353                 if (polaris10_ps->performance_levels[1].memory_clock <
3354                                 polaris10_ps->performance_levels[0].memory_clock)
3355                         polaris10_ps->performance_levels[1].memory_clock =
3356                                         polaris10_ps->performance_levels[0].memory_clock;
3357         }
3358
3359         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3360                         PHM_PlatformCaps_StablePState)) {
3361                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3362                         polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3363                         polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3364                         polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3365                         polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3366                 }
3367         }
3368         return 0;
3369 }
3370
3371
3372 static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3373 {
3374         struct pp_power_state  *ps;
3375         struct polaris10_power_state  *polaris10_ps;
3376
3377         if (hwmgr == NULL)
3378                 return -EINVAL;
3379
3380         ps = hwmgr->request_ps;
3381
3382         if (ps == NULL)
3383                 return -EINVAL;
3384
3385         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3386
3387         if (low)
3388                 return polaris10_ps->performance_levels[0].memory_clock;
3389         else
3390                 return polaris10_ps->performance_levels
3391                                 [polaris10_ps->performance_level_count-1].memory_clock;
3392 }
3393
3394 static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3395 {
3396         struct pp_power_state  *ps;
3397         struct polaris10_power_state  *polaris10_ps;
3398
3399         if (hwmgr == NULL)
3400                 return -EINVAL;
3401
3402         ps = hwmgr->request_ps;
3403
3404         if (ps == NULL)
3405                 return -EINVAL;
3406
3407         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3408
3409         if (low)
3410                 return polaris10_ps->performance_levels[0].engine_clock;
3411         else
3412                 return polaris10_ps->performance_levels
3413                                 [polaris10_ps->performance_level_count-1].engine_clock;
3414 }
3415
3416 static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3417                                         struct pp_hw_power_state *hw_ps)
3418 {
3419         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3420         struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
3421         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3422         uint16_t size;
3423         uint8_t frev, crev;
3424         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3425
3426         /* First retrieve the Boot clocks and VDDC from the firmware info table.
3427          * We assume here that fw_info is unchanged if this call fails.
3428          */
3429         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3430                         hwmgr->device, index,
3431                         &size, &frev, &crev);
3432         if (!fw_info)
3433                 /* During a test, there is no firmware info table. */
3434                 return 0;
3435
3436         /* Patch the state. */
3437         data->vbios_boot_state.sclk_bootup_value =
3438                         le32_to_cpu(fw_info->ulDefaultEngineClock);
3439         data->vbios_boot_state.mclk_bootup_value =
3440                         le32_to_cpu(fw_info->ulDefaultMemoryClock);
3441         data->vbios_boot_state.mvdd_bootup_value =
3442                         le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3443         data->vbios_boot_state.vddc_bootup_value =
3444                         le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3445         data->vbios_boot_state.vddci_bootup_value =
3446                         le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3447         data->vbios_boot_state.pcie_gen_bootup_value =
3448                         phm_get_current_pcie_speed(hwmgr);
3449
3450         data->vbios_boot_state.pcie_lane_bootup_value =
3451                         (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3452
3453         /* set boot power state */
3454         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3455         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3456         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3457         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3458
3459         return 0;
3460 }
3461
3462 static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3463                 void *state, struct pp_power_state *power_state,
3464                 void *pp_table, uint32_t classification_flag)
3465 {
3466         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3467         struct polaris10_power_state  *polaris10_power_state =
3468                         (struct polaris10_power_state *)(&(power_state->hardware));
3469         struct polaris10_performance_level *performance_level;
3470         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3471         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3472                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3473         ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
3474                         (ATOM_Tonga_SCLK_Dependency_Table *)
3475                         (((unsigned long)powerplay_table) +
3476                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3477         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3478                         (ATOM_Tonga_MCLK_Dependency_Table *)
3479                         (((unsigned long)powerplay_table) +
3480                                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3481
3482         /* The following fields are not initialized here: id orderedList allStatesList */
3483         power_state->classification.ui_label =
3484                         (le16_to_cpu(state_entry->usClassification) &
3485                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3486                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3487         power_state->classification.flags = classification_flag;
3488         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3489
3490         power_state->classification.temporary_state = false;
3491         power_state->classification.to_be_deleted = false;
3492
3493         power_state->validation.disallowOnDC =
3494                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3495                                         ATOM_Tonga_DISALLOW_ON_DC));
3496
3497         power_state->pcie.lanes = 0;
3498
3499         power_state->display.disableFrameModulation = false;
3500         power_state->display.limitRefreshrate = false;
3501         power_state->display.enableVariBright =
3502                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3503                                         ATOM_Tonga_ENABLE_VARIBRIGHT));
3504
3505         power_state->validation.supportedPowerLevels = 0;
3506         power_state->uvd_clocks.VCLK = 0;
3507         power_state->uvd_clocks.DCLK = 0;
3508         power_state->temperatures.min = 0;
3509         power_state->temperatures.max = 0;
3510
3511         performance_level = &(polaris10_power_state->performance_levels
3512                         [polaris10_power_state->performance_level_count++]);
3513
3514         PP_ASSERT_WITH_CODE(
3515                         (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
3516                         "Performance levels exceeds SMC limit!",
3517                         return -1);
3518
3519         PP_ASSERT_WITH_CODE(
3520                         (polaris10_power_state->performance_level_count <=
3521                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3522                         "Performance levels exceeds Driver limit!",
3523                         return -1);
3524
3525         /* Performance levels are arranged from low to high. */
3526         performance_level->memory_clock = mclk_dep_table->entries
3527                         [state_entry->ucMemoryClockIndexLow].ulMclk;
3528         performance_level->engine_clock = sclk_dep_table->entries
3529                         [state_entry->ucEngineClockIndexLow].ulSclk;
3530         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3531                         state_entry->ucPCIEGenLow);
3532         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3533                         state_entry->ucPCIELaneHigh);
3534
3535         performance_level = &(polaris10_power_state->performance_levels
3536                         [polaris10_power_state->performance_level_count++]);
3537         performance_level->memory_clock = mclk_dep_table->entries
3538                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
3539         performance_level->engine_clock = sclk_dep_table->entries
3540                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3541         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3542                         state_entry->ucPCIEGenHigh);
3543         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3544                         state_entry->ucPCIELaneHigh);
3545
3546         return 0;
3547 }
3548
3549 static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3550                 unsigned long entry_index, struct pp_power_state *state)
3551 {
3552         int result;
3553         struct polaris10_power_state *ps;
3554         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3555         struct phm_ppt_v1_information *table_info =
3556                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3557         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3558                         table_info->vdd_dep_on_mclk;
3559
3560         state->hardware.magic = PHM_VIslands_Magic;
3561
3562         ps = (struct polaris10_power_state *)(&state->hardware);
3563
3564         result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3565                         polaris10_get_pp_table_entry_callback_func);
3566
3567         /* This is the earliest time we have all the dependency table and the VBIOS boot state
3568          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3569          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3570          */
3571         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3572                 if (dep_mclk_table->entries[0].clk !=
3573                                 data->vbios_boot_state.mclk_bootup_value)
3574                         printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3575                                         "does not match VBIOS boot MCLK level");
3576                 if (dep_mclk_table->entries[0].vddci !=
3577                                 data->vbios_boot_state.vddci_bootup_value)
3578                         printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3579                                         "does not match VBIOS boot VDDCI level");
3580         }
3581
3582         /* set DC compatible flag if this state supports DC */
3583         if (!state->validation.disallowOnDC)
3584                 ps->dc_compatible = true;
3585
3586         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3587                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3588
3589         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3590         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3591
3592         if (!result) {
3593                 uint32_t i;
3594
3595                 switch (state->classification.ui_label) {
3596                 case PP_StateUILabel_Performance:
3597                         data->use_pcie_performance_levels = true;
3598
3599                         for (i = 0; i < ps->performance_level_count; i++) {
3600                                 if (data->pcie_gen_performance.max <
3601                                                 ps->performance_levels[i].pcie_gen)
3602                                         data->pcie_gen_performance.max =
3603                                                         ps->performance_levels[i].pcie_gen;
3604
3605                                 if (data->pcie_gen_performance.min >
3606                                                 ps->performance_levels[i].pcie_gen)
3607                                         data->pcie_gen_performance.min =
3608                                                         ps->performance_levels[i].pcie_gen;
3609
3610                                 if (data->pcie_lane_performance.max <
3611                                                 ps->performance_levels[i].pcie_lane)
3612                                         data->pcie_lane_performance.max =
3613                                                         ps->performance_levels[i].pcie_lane;
3614
3615                                 if (data->pcie_lane_performance.min >
3616                                                 ps->performance_levels[i].pcie_lane)
3617                                         data->pcie_lane_performance.min =
3618                                                         ps->performance_levels[i].pcie_lane;
3619                         }
3620                         break;
3621                 case PP_StateUILabel_Battery:
3622                         data->use_pcie_power_saving_levels = true;
3623
3624                         for (i = 0; i < ps->performance_level_count; i++) {
3625                                 if (data->pcie_gen_power_saving.max <
3626                                                 ps->performance_levels[i].pcie_gen)
3627                                         data->pcie_gen_power_saving.max =
3628                                                         ps->performance_levels[i].pcie_gen;
3629
3630                                 if (data->pcie_gen_power_saving.min >
3631                                                 ps->performance_levels[i].pcie_gen)
3632                                         data->pcie_gen_power_saving.min =
3633                                                         ps->performance_levels[i].pcie_gen;
3634
3635                                 if (data->pcie_lane_power_saving.max <
3636                                                 ps->performance_levels[i].pcie_lane)
3637                                         data->pcie_lane_power_saving.max =
3638                                                         ps->performance_levels[i].pcie_lane;
3639
3640                                 if (data->pcie_lane_power_saving.min >
3641                                                 ps->performance_levels[i].pcie_lane)
3642                                         data->pcie_lane_power_saving.min =
3643                                                         ps->performance_levels[i].pcie_lane;
3644                         }
3645                         break;
3646                 default:
3647                         break;
3648                 }
3649         }
3650         return 0;
3651 }
3652
3653 static void
3654 polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
3655 {
3656         uint32_t sclk, mclk, activity_percent;
3657         uint32_t offset;
3658         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3659
3660         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3661
3662         sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3663
3664         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
3665
3666         mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3667         seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
3668                         mclk / 100, sclk / 100);
3669
3670         offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
3671         activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3672         activity_percent += 0x80;
3673         activity_percent >>= 8;
3674
3675         seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
3676
3677         seq_printf(m, "uvd    %sabled\n", data->uvd_power_gated ? "dis" : "en");
3678
3679         seq_printf(m, "vce    %sabled\n", data->vce_power_gated ? "dis" : "en");
3680 }
3681
3682 static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3683 {
3684         const struct phm_set_power_state_input *states =
3685                         (const struct phm_set_power_state_input *)input;
3686         const struct polaris10_power_state *polaris10_ps =
3687                         cast_const_phw_polaris10_power_state(states->pnew_state);
3688         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3689         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3690         uint32_t sclk = polaris10_ps->performance_levels
3691                         [polaris10_ps->performance_level_count - 1].engine_clock;
3692         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3693         uint32_t mclk = polaris10_ps->performance_levels
3694                         [polaris10_ps->performance_level_count - 1].memory_clock;
3695         struct PP_Clocks min_clocks = {0};
3696         uint32_t i;
3697         struct cgs_display_info info = {0};
3698
3699         data->need_update_smu7_dpm_table = 0;
3700
3701         for (i = 0; i < sclk_table->count; i++) {
3702                 if (sclk == sclk_table->dpm_levels[i].value)
3703                         break;
3704         }
3705
3706         if (i >= sclk_table->count)
3707                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3708         else {
3709         /* TODO: Check SCLK in DAL's minimum clocks
3710          * in case DeepSleep divider update is required.
3711          */
3712                 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3713                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
3714                                 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
3715                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3716         }
3717
3718         for (i = 0; i < mclk_table->count; i++) {
3719                 if (mclk == mclk_table->dpm_levels[i].value)
3720                         break;
3721         }
3722
3723         if (i >= mclk_table->count)
3724                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3725
3726         cgs_get_active_displays_info(hwmgr->device, &info);
3727
3728         if (data->display_timing.num_existing_displays != info.display_count)
3729                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3730
3731         return 0;
3732 }
3733
3734 static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
3735                 const struct polaris10_power_state *polaris10_ps)
3736 {
3737         uint32_t i;
3738         uint32_t sclk, max_sclk = 0;
3739         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3740         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3741
3742         for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3743                 sclk = polaris10_ps->performance_levels[i].engine_clock;
3744                 if (max_sclk < sclk)
3745                         max_sclk = sclk;
3746         }
3747
3748         for (i = 0; i < dpm_table->sclk_table.count; i++) {
3749                 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
3750                         return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
3751                                         dpm_table->pcie_speed_table.dpm_levels
3752                                         [dpm_table->pcie_speed_table.count - 1].value :
3753                                         dpm_table->pcie_speed_table.dpm_levels[i].value);
3754         }
3755
3756         return 0;
3757 }
3758
3759 static int polaris10_request_link_speed_change_before_state_change(
3760                 struct pp_hwmgr *hwmgr, const void *input)
3761 {
3762         const struct phm_set_power_state_input *states =
3763                         (const struct phm_set_power_state_input *)input;
3764         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3765         const struct polaris10_power_state *polaris10_nps =
3766                         cast_const_phw_polaris10_power_state(states->pnew_state);
3767         const struct polaris10_power_state *polaris10_cps =
3768                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
3769
3770         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
3771         uint16_t current_link_speed;
3772
3773         if (data->force_pcie_gen == PP_PCIEGenInvalid)
3774                 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
3775         else
3776                 current_link_speed = data->force_pcie_gen;
3777
3778         data->force_pcie_gen = PP_PCIEGenInvalid;
3779         data->pspp_notify_required = false;
3780
3781         if (target_link_speed > current_link_speed) {
3782                 switch (target_link_speed) {
3783                 case PP_PCIEGen3:
3784                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
3785                                 break;
3786                         data->force_pcie_gen = PP_PCIEGen2;
3787                         if (current_link_speed == PP_PCIEGen2)
3788                                 break;
3789                 case PP_PCIEGen2:
3790                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
3791                                 break;
3792                 default:
3793                         data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
3794                         break;
3795                 }
3796         } else {
3797                 if (target_link_speed < current_link_speed)
3798                         data->pspp_notify_required = true;
3799         }
3800
3801         return 0;
3802 }
3803
3804 static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3805 {
3806         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3807
3808         if (0 == data->need_update_smu7_dpm_table)
3809                 return 0;
3810
3811         if ((0 == data->sclk_dpm_key_disabled) &&
3812                 (data->need_update_smu7_dpm_table &
3813                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3814                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3815                                 "Trying to freeze SCLK DPM when DPM is disabled",
3816                                 );
3817                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3818                                 PPSMC_MSG_SCLKDPM_FreezeLevel),
3819                                 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3820                                 return -1);
3821         }
3822
3823         if ((0 == data->mclk_dpm_key_disabled) &&
3824                 (data->need_update_smu7_dpm_table &
3825                  DPMTABLE_OD_UPDATE_MCLK)) {
3826                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3827                                 "Trying to freeze MCLK DPM when DPM is disabled",
3828                                 );
3829                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3830                                 PPSMC_MSG_MCLKDPM_FreezeLevel),
3831                                 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3832                                 return -1);
3833         }
3834
3835         return 0;
3836 }
3837
3838 static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
3839                 struct pp_hwmgr *hwmgr, const void *input)
3840 {
3841         int result = 0;
3842         const struct phm_set_power_state_input *states =
3843                         (const struct phm_set_power_state_input *)input;
3844         const struct polaris10_power_state *polaris10_ps =
3845                         cast_const_phw_polaris10_power_state(states->pnew_state);
3846         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3847         uint32_t sclk = polaris10_ps->performance_levels
3848                         [polaris10_ps->performance_level_count - 1].engine_clock;
3849         uint32_t mclk = polaris10_ps->performance_levels
3850                         [polaris10_ps->performance_level_count - 1].memory_clock;
3851         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3852
3853         struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
3854         uint32_t dpm_count, clock_percent;
3855         uint32_t i;
3856
3857         if (0 == data->need_update_smu7_dpm_table)
3858                 return 0;
3859
3860         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3861                 dpm_table->sclk_table.dpm_levels
3862                 [dpm_table->sclk_table.count - 1].value = sclk;
3863
3864                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3865                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3866                 /* Need to do calculation based on the golden DPM table
3867                  * as the Heatmap GPU Clock axis is also based on the default values
3868                  */
3869                         PP_ASSERT_WITH_CODE(
3870                                 (golden_dpm_table->sclk_table.dpm_levels
3871                                                 [golden_dpm_table->sclk_table.count - 1].value != 0),
3872                                 "Divide by 0!",
3873                                 return -1);
3874                         dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
3875
3876                         for (i = dpm_count; i > 1; i--) {
3877                                 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
3878                                         clock_percent =
3879                                               ((sclk
3880                                                 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
3881                                                 ) * 100)
3882                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3883
3884                                         dpm_table->sclk_table.dpm_levels[i].value =
3885                                                         golden_dpm_table->sclk_table.dpm_levels[i].value +
3886                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
3887                                                                 clock_percent)/100;
3888
3889                                 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
3890                                         clock_percent =
3891                                                 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
3892                                                 - sclk) * 100)
3893                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3894
3895                                         dpm_table->sclk_table.dpm_levels[i].value =
3896                                                         golden_dpm_table->sclk_table.dpm_levels[i].value -
3897                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
3898                                                                         clock_percent) / 100;
3899                                 } else
3900                                         dpm_table->sclk_table.dpm_levels[i].value =
3901                                                         golden_dpm_table->sclk_table.dpm_levels[i].value;
3902                         }
3903                 }
3904         }
3905
3906         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3907                 dpm_table->mclk_table.dpm_levels
3908                         [dpm_table->mclk_table.count - 1].value = mclk;
3909
3910                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3911                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3912
3913                         PP_ASSERT_WITH_CODE(
3914                                         (golden_dpm_table->mclk_table.dpm_levels
3915                                                 [golden_dpm_table->mclk_table.count-1].value != 0),
3916                                         "Divide by 0!",
3917                                         return -1);
3918                         dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
3919                         for (i = dpm_count; i > 1; i--) {
3920                                 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
3921                                         clock_percent = ((mclk -
3922                                         golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
3923                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
3924
3925                                         dpm_table->mclk_table.dpm_levels[i].value =
3926                                                         golden_dpm_table->mclk_table.dpm_levels[i].value +
3927                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
3928                                                         clock_percent) / 100;
3929
3930                                 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
3931                                         clock_percent = (
3932                                          (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
3933                                         * 100)
3934                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
3935
3936                                         dpm_table->mclk_table.dpm_levels[i].value =
3937                                                         golden_dpm_table->mclk_table.dpm_levels[i].value -
3938                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
3939                                                                         clock_percent) / 100;
3940                                 } else
3941                                         dpm_table->mclk_table.dpm_levels[i].value =
3942                                                         golden_dpm_table->mclk_table.dpm_levels[i].value;
3943                         }
3944                 }
3945         }
3946
3947         if (data->need_update_smu7_dpm_table &
3948                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
3949                 result = polaris10_populate_all_graphic_levels(hwmgr);
3950                 PP_ASSERT_WITH_CODE((0 == result),
3951                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
3952                                 return result);
3953         }
3954
3955         if (data->need_update_smu7_dpm_table &
3956                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
3957                 /*populate MCLK dpm table to SMU7 */
3958                 result = polaris10_populate_all_memory_levels(hwmgr);
3959                 PP_ASSERT_WITH_CODE((0 == result),
3960                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
3961                                 return result);
3962         }
3963
3964         return result;
3965 }
3966
3967 static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
3968                           struct polaris10_single_dpm_table *dpm_table,
3969                         uint32_t low_limit, uint32_t high_limit)
3970 {
3971         uint32_t i;
3972
3973         for (i = 0; i < dpm_table->count; i++) {
3974                 if ((dpm_table->dpm_levels[i].value < low_limit)
3975                 || (dpm_table->dpm_levels[i].value > high_limit))
3976                         dpm_table->dpm_levels[i].enabled = false;
3977                 else
3978                         dpm_table->dpm_levels[i].enabled = true;
3979         }
3980
3981         return 0;
3982 }
3983
3984 static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
3985                 const struct polaris10_power_state *polaris10_ps)
3986 {
3987         int result = 0;
3988         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3989         uint32_t high_limit_count;
3990
3991         PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
3992                         "power state did not have any performance level",
3993                         return -1);
3994
3995         high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
3996
3997         polaris10_trim_single_dpm_states(hwmgr,
3998                         &(data->dpm_table.sclk_table),
3999                         polaris10_ps->performance_levels[0].engine_clock,
4000                         polaris10_ps->performance_levels[high_limit_count].engine_clock);
4001
4002         polaris10_trim_single_dpm_states(hwmgr,
4003                         &(data->dpm_table.mclk_table),
4004                         polaris10_ps->performance_levels[0].memory_clock,
4005                         polaris10_ps->performance_levels[high_limit_count].memory_clock);
4006
4007         return result;
4008 }
4009
4010 static int polaris10_generate_dpm_level_enable_mask(
4011                 struct pp_hwmgr *hwmgr, const void *input)
4012 {
4013         int result;
4014         const struct phm_set_power_state_input *states =
4015                         (const struct phm_set_power_state_input *)input;
4016         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4017         const struct polaris10_power_state *polaris10_ps =
4018                         cast_const_phw_polaris10_power_state(states->pnew_state);
4019
4020         result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
4021         if (result)
4022                 return result;
4023
4024         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4025                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4026         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4027                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4028         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4029                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4030
4031         return 0;
4032 }
4033
4034 int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4035 {
4036         return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4037                         PPSMC_MSG_UVDDPM_Enable :
4038                         PPSMC_MSG_UVDDPM_Disable);
4039 }
4040
4041 int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4042 {
4043         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4044                         PPSMC_MSG_VCEDPM_Enable :
4045                         PPSMC_MSG_VCEDPM_Disable);
4046 }
4047
4048 int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4049 {
4050         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4051                         PPSMC_MSG_SAMUDPM_Enable :
4052                         PPSMC_MSG_SAMUDPM_Disable);
4053 }
4054
4055 int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4056 {
4057         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4058         uint32_t mm_boot_level_offset, mm_boot_level_value;
4059         struct phm_ppt_v1_information *table_info =
4060                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4061
4062         if (!bgate) {
4063                 data->smc_state_table.UvdBootLevel = 0;
4064                 if (table_info->mm_dep_table->count > 0)
4065                         data->smc_state_table.UvdBootLevel =
4066                                         (uint8_t) (table_info->mm_dep_table->count - 1);
4067                 mm_boot_level_offset = data->dpm_table_start +
4068                                 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4069                 mm_boot_level_offset /= 4;
4070                 mm_boot_level_offset *= 4;
4071                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4072                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4073                 mm_boot_level_value &= 0x00FFFFFF;
4074                 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4075                 cgs_write_ind_register(hwmgr->device,
4076                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4077
4078                 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4079                                 PHM_PlatformCaps_UVDDPM) ||
4080                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4081                                 PHM_PlatformCaps_StablePState))
4082                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4083                                         PPSMC_MSG_UVDDPM_SetEnabledMask,
4084                                         (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4085         }
4086
4087         return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
4088 }
4089
4090 static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4091 {
4092         const struct phm_set_power_state_input *states =
4093                         (const struct phm_set_power_state_input *)input;
4094         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4095         const struct polaris10_power_state *polaris10_nps =
4096                         cast_const_phw_polaris10_power_state(states->pnew_state);
4097         const struct polaris10_power_state *polaris10_cps =
4098                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
4099
4100         uint32_t mm_boot_level_offset, mm_boot_level_value;
4101         struct phm_ppt_v1_information *table_info =
4102                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4103
4104         if (polaris10_nps->vce_clks.evclk > 0 &&
4105         (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
4106
4107                 data->smc_state_table.VceBootLevel =
4108                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4109
4110                 mm_boot_level_offset = data->dpm_table_start +
4111                                 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4112                 mm_boot_level_offset /= 4;
4113                 mm_boot_level_offset *= 4;
4114                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4115                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4116                 mm_boot_level_value &= 0xFF00FFFF;
4117                 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4118                 cgs_write_ind_register(hwmgr->device,
4119                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4120
4121                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4122                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4123                                         PPSMC_MSG_VCEDPM_SetEnabledMask,
4124                                         (uint32_t)1 << data->smc_state_table.VceBootLevel);
4125
4126                         polaris10_enable_disable_vce_dpm(hwmgr, true);
4127                 } else if (polaris10_nps->vce_clks.evclk == 0 &&
4128                                 polaris10_cps != NULL &&
4129                                 polaris10_cps->vce_clks.evclk > 0)
4130                         polaris10_enable_disable_vce_dpm(hwmgr, false);
4131         }
4132
4133         return 0;
4134 }
4135
4136 int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4137 {
4138         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4139         uint32_t mm_boot_level_offset, mm_boot_level_value;
4140         struct phm_ppt_v1_information *table_info =
4141                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4142
4143         if (!bgate) {
4144                 data->smc_state_table.SamuBootLevel =
4145                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4146                 mm_boot_level_offset = data->dpm_table_start +
4147                                 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4148                 mm_boot_level_offset /= 4;
4149                 mm_boot_level_offset *= 4;
4150                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4151                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4152                 mm_boot_level_value &= 0xFFFFFF00;
4153                 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4154                 cgs_write_ind_register(hwmgr->device,
4155                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4156
4157                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4158                                 PHM_PlatformCaps_StablePState))
4159                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4160                                         PPSMC_MSG_SAMUDPM_SetEnabledMask,
4161                                         (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4162         }
4163
4164         return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
4165 }
4166
4167 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4168 {
4169         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4170
4171         int result = 0;
4172         uint32_t low_sclk_interrupt_threshold = 0;
4173
4174         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4175                         PHM_PlatformCaps_SclkThrottleLowNotification)
4176                 && (hwmgr->gfx_arbiter.sclk_threshold !=
4177                                 data->low_sclk_interrupt_threshold)) {
4178                 data->low_sclk_interrupt_threshold =
4179                                 hwmgr->gfx_arbiter.sclk_threshold;
4180                 low_sclk_interrupt_threshold =
4181                                 data->low_sclk_interrupt_threshold;
4182
4183                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4184
4185                 result = polaris10_copy_bytes_to_smc(
4186                                 hwmgr->smumgr,
4187                                 data->dpm_table_start +
4188                                 offsetof(SMU74_Discrete_DpmTable,
4189                                         LowSclkInterruptThreshold),
4190                                 (uint8_t *)&low_sclk_interrupt_threshold,
4191                                 sizeof(uint32_t),
4192                                 data->sram_end);
4193         }
4194
4195         return result;
4196 }
4197
4198 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4199 {
4200         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4201
4202         if (data->need_update_smu7_dpm_table &
4203                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4204                 return polaris10_program_memory_timing_parameters(hwmgr);
4205
4206         return 0;
4207 }
4208
4209 static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4210 {
4211         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4212
4213         if (0 == data->need_update_smu7_dpm_table)
4214                 return 0;
4215
4216         if ((0 == data->sclk_dpm_key_disabled) &&
4217                 (data->need_update_smu7_dpm_table &
4218                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4219
4220                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4221                                 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4222                                 );
4223                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4224                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4225                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4226                         return -1);
4227         }
4228
4229         if ((0 == data->mclk_dpm_key_disabled) &&
4230                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4231
4232                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4233                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4234                                 );
4235                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4236                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4237                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4238                     return -1);
4239         }
4240
4241         data->need_update_smu7_dpm_table = 0;
4242
4243         return 0;
4244 }
4245
4246 static int polaris10_notify_link_speed_change_after_state_change(
4247                 struct pp_hwmgr *hwmgr, const void *input)
4248 {
4249         const struct phm_set_power_state_input *states =
4250                         (const struct phm_set_power_state_input *)input;
4251         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4252         const struct polaris10_power_state *polaris10_ps =
4253                         cast_const_phw_polaris10_power_state(states->pnew_state);
4254         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
4255         uint8_t  request;
4256
4257         if (data->pspp_notify_required) {
4258                 if (target_link_speed == PP_PCIEGen3)
4259                         request = PCIE_PERF_REQ_GEN3;
4260                 else if (target_link_speed == PP_PCIEGen2)
4261                         request = PCIE_PERF_REQ_GEN2;
4262                 else
4263                         request = PCIE_PERF_REQ_GEN1;
4264
4265                 if (request == PCIE_PERF_REQ_GEN1 &&
4266                                 phm_get_current_pcie_speed(hwmgr) > 0)
4267                         return 0;
4268
4269                 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4270                         if (PP_PCIEGen2 == target_link_speed)
4271                                 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4272                         else
4273                                 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4274                 }
4275         }
4276
4277         return 0;
4278 }
4279
4280 static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4281 {
4282         int tmp_result, result = 0;
4283         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4284
4285         tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4286         PP_ASSERT_WITH_CODE((0 == tmp_result),
4287                         "Failed to find DPM states clocks in DPM table!",
4288                         result = tmp_result);
4289
4290         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4291                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4292                 tmp_result =
4293                         polaris10_request_link_speed_change_before_state_change(hwmgr, input);
4294                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4295                                 "Failed to request link speed change before state change!",
4296                                 result = tmp_result);
4297         }
4298
4299         tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
4300         PP_ASSERT_WITH_CODE((0 == tmp_result),
4301                         "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4302
4303         tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4304         PP_ASSERT_WITH_CODE((0 == tmp_result),
4305                         "Failed to populate and upload SCLK MCLK DPM levels!",
4306                         result = tmp_result);
4307
4308         tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
4309         PP_ASSERT_WITH_CODE((0 == tmp_result),
4310                         "Failed to generate DPM level enabled mask!",
4311                         result = tmp_result);
4312
4313         tmp_result = polaris10_update_vce_dpm(hwmgr, input);
4314         PP_ASSERT_WITH_CODE((0 == tmp_result),
4315                         "Failed to update VCE DPM!",
4316                         result = tmp_result);
4317
4318         tmp_result = polaris10_update_sclk_threshold(hwmgr);
4319         PP_ASSERT_WITH_CODE((0 == tmp_result),
4320                         "Failed to update SCLK threshold!",
4321                         result = tmp_result);
4322
4323         tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
4324         PP_ASSERT_WITH_CODE((0 == tmp_result),
4325                         "Failed to program memory timing parameters!",
4326                         result = tmp_result);
4327
4328         tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
4329         PP_ASSERT_WITH_CODE((0 == tmp_result),
4330                         "Failed to unfreeze SCLK MCLK DPM!",
4331                         result = tmp_result);
4332
4333         tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
4334         PP_ASSERT_WITH_CODE((0 == tmp_result),
4335                         "Failed to upload DPM level enabled mask!",
4336                         result = tmp_result);
4337
4338         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4339                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4340                 tmp_result =
4341                         polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
4342                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4343                                 "Failed to notify link speed change after state change!",
4344                                 result = tmp_result);
4345         }
4346         data->apply_optimized_settings = false;
4347         return result;
4348 }
4349
4350 static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4351 {
4352         hwmgr->thermal_controller.
4353         advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4354
4355         if (phm_is_hw_access_blocked(hwmgr))
4356                 return 0;
4357
4358         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4359                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4360 }
4361
4362 int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4363 {
4364         PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4365
4366         return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
4367 }
4368
4369 int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4370 {
4371         uint32_t num_active_displays = 0;
4372         struct cgs_display_info info = {0};
4373         info.mode_info = NULL;
4374
4375         cgs_get_active_displays_info(hwmgr->device, &info);
4376
4377         num_active_displays = info.display_count;
4378
4379         if (num_active_displays > 1)  /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
4380                 polaris10_notify_smc_display_change(hwmgr, false);
4381         else
4382                 polaris10_notify_smc_display_change(hwmgr, true);
4383
4384         return 0;
4385 }
4386
4387 /**
4388 * Programs the display gap
4389 *
4390 * @param    hwmgr  the address of the powerplay hardware manager.
4391 * @return   always OK
4392 */
4393 int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
4394 {
4395         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4396         uint32_t num_active_displays = 0;
4397         uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4398         uint32_t display_gap2;
4399         uint32_t pre_vbi_time_in_us;
4400         uint32_t frame_time_in_us;
4401         uint32_t ref_clock;
4402         uint32_t refresh_rate = 0;
4403         struct cgs_display_info info = {0};
4404         struct cgs_mode_info mode_info;
4405
4406         info.mode_info = &mode_info;
4407
4408         cgs_get_active_displays_info(hwmgr->device, &info);
4409         num_active_displays = info.display_count;
4410
4411         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4412         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4413
4414         ref_clock = mode_info.ref_clock;
4415         refresh_rate = mode_info.refresh_rate;
4416
4417         if (0 == refresh_rate)
4418                 refresh_rate = 60;
4419
4420         frame_time_in_us = 1000000 / refresh_rate;
4421
4422         pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4423         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4424
4425         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4426
4427         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4428
4429         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4430
4431         polaris10_notify_smc_display_change(hwmgr, num_active_displays != 0);
4432
4433         return 0;
4434 }
4435
4436
4437 int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4438 {
4439         return polaris10_program_display_gap(hwmgr);
4440 }
4441
4442 /**
4443 *  Set maximum target operating fan output RPM
4444 *
4445 * @param    hwmgr:  the address of the powerplay hardware manager.
4446 * @param    usMaxFanRpm:  max operating fan RPM value.
4447 * @return   The response that came from the SMC.
4448 */
4449 static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4450 {
4451         hwmgr->thermal_controller.
4452         advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4453
4454         if (phm_is_hw_access_blocked(hwmgr))
4455                 return 0;
4456
4457         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4458                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4459 }
4460
4461 int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
4462                                         const void *thermal_interrupt_info)
4463 {
4464         return 0;
4465 }
4466
4467 bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4468 {
4469         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4470         bool is_update_required = false;
4471         struct cgs_display_info info = {0, 0, NULL};
4472
4473         cgs_get_active_displays_info(hwmgr->device, &info);
4474
4475         if (data->display_timing.num_existing_displays != info.display_count)
4476                 is_update_required = true;
4477 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4478         if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4479                 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
4480                 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4481                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4482                                 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4483                         is_update_required = true;
4484 */
4485         return is_update_required;
4486 }
4487
4488 static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4489                                                            const struct polaris10_performance_level *pl2)
4490 {
4491         return ((pl1->memory_clock == pl2->memory_clock) &&
4492                   (pl1->engine_clock == pl2->engine_clock) &&
4493                   (pl1->pcie_gen == pl2->pcie_gen) &&
4494                   (pl1->pcie_lane == pl2->pcie_lane));
4495 }
4496
4497 int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
4498 {
4499         const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4500         const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
4501         int i;
4502
4503         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4504                 return -EINVAL;
4505
4506         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4507         if (psa->performance_level_count != psb->performance_level_count) {
4508                 *equal = false;
4509                 return 0;
4510         }
4511
4512         for (i = 0; i < psa->performance_level_count; i++) {
4513                 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4514                         /* If we have found even one performance level pair that is different the states are different. */
4515                         *equal = false;
4516                         return 0;
4517                 }
4518         }
4519
4520         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4521         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4522         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4523         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4524
4525         return 0;
4526 }
4527
4528 int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
4529 {
4530         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4531
4532         uint32_t vbios_version;
4533
4534         /*  Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4535
4536         phm_get_mc_microcode_version(hwmgr);
4537         vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4538         /*  Full version of MC ucode has already been loaded. */
4539         if (vbios_version == 0) {
4540                 data->need_long_memory_training = false;
4541                 return 0;
4542         }
4543
4544         data->need_long_memory_training = true;
4545
4546 /*
4547  *      PPMCME_FirmwareDescriptorEntry *pfd = NULL;
4548         pfd = &tonga_mcmeFirmware;
4549         if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
4550                 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
4551                                         pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4552                                         pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4553 */
4554         return 0;
4555 }
4556
4557 /**
4558  * Read clock related registers.
4559  *
4560  * @param    hwmgr  the address of the powerplay hardware manager.
4561  * @return   always 0
4562  */
4563 static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
4564 {
4565         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4566
4567         data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4568                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4569                                                 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4570
4571         data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4572                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4573                                                 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4574
4575         data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4576                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4577                                                 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4578
4579         return 0;
4580 }
4581
4582 /**
4583  * Find out if memory is GDDR5.
4584  *
4585  * @param    hwmgr  the address of the powerplay hardware manager.
4586  * @return   always 0
4587  */
4588 static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
4589 {
4590         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4591         uint32_t temp;
4592
4593         temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4594
4595         data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4596                         ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4597                          MC_SEQ_MISC0_GDDR5_SHIFT));
4598
4599         return 0;
4600 }
4601
4602 /**
4603  * Enables Dynamic Power Management by SMC
4604  *
4605  * @param    hwmgr  the address of the powerplay hardware manager.
4606  * @return   always 0
4607  */
4608 static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4609 {
4610         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4611                         GENERAL_PWRMGT, STATIC_PM_EN, 1);
4612
4613         return 0;
4614 }
4615
4616 /**
4617  * Initialize PowerGating States for different engines
4618  *
4619  * @param    hwmgr  the address of the powerplay hardware manager.
4620  * @return   always 0
4621  */
4622 static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
4623 {
4624         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4625
4626         data->uvd_power_gated = false;
4627         data->vce_power_gated = false;
4628         data->samu_power_gated = false;
4629
4630         return 0;
4631 }
4632
4633 static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4634 {
4635         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4636         data->low_sclk_interrupt_threshold = 0;
4637
4638         return 0;
4639 }
4640
4641 int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
4642 {
4643         int tmp_result, result = 0;
4644
4645         polaris10_upload_mc_firmware(hwmgr);
4646
4647         tmp_result = polaris10_read_clock_registers(hwmgr);
4648         PP_ASSERT_WITH_CODE((0 == tmp_result),
4649                         "Failed to read clock registers!", result = tmp_result);
4650
4651         tmp_result = polaris10_get_memory_type(hwmgr);
4652         PP_ASSERT_WITH_CODE((0 == tmp_result),
4653                         "Failed to get memory type!", result = tmp_result);
4654
4655         tmp_result = polaris10_enable_acpi_power_management(hwmgr);
4656         PP_ASSERT_WITH_CODE((0 == tmp_result),
4657                         "Failed to enable ACPI power management!", result = tmp_result);
4658
4659         tmp_result = polaris10_init_power_gate_state(hwmgr);
4660         PP_ASSERT_WITH_CODE((0 == tmp_result),
4661                         "Failed to init power gate state!", result = tmp_result);
4662
4663         tmp_result = phm_get_mc_microcode_version(hwmgr);
4664         PP_ASSERT_WITH_CODE((0 == tmp_result),
4665                         "Failed to get MC microcode version!", result = tmp_result);
4666
4667         tmp_result = polaris10_init_sclk_threshold(hwmgr);
4668         PP_ASSERT_WITH_CODE((0 == tmp_result),
4669                         "Failed to init sclk threshold!", result = tmp_result);
4670
4671         return result;
4672 }
4673
4674 static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
4675 {
4676         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4677
4678         *table = (char *)&data->smc_state_table;
4679
4680         return sizeof(struct SMU74_Discrete_DpmTable);
4681 }
4682
4683 static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
4684 {
4685         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4686
4687         void *table = (void *)&data->smc_state_table;
4688
4689         memcpy(table, buf, size);
4690
4691         return 0;
4692 }
4693
4694 static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
4695                 enum pp_clock_type type, int level)
4696 {
4697         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4698
4699         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
4700                 return -EINVAL;
4701
4702         switch (type) {
4703         case PP_SCLK:
4704                 if (!data->sclk_dpm_key_disabled)
4705                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4706                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
4707                                         (1 << level));
4708                 break;
4709         case PP_MCLK:
4710                 if (!data->mclk_dpm_key_disabled)
4711                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4712                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
4713                                         (1 << level));
4714                 break;
4715         case PP_PCIE:
4716                 if (!data->pcie_dpm_key_disabled)
4717                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4718                                         PPSMC_MSG_PCIeDPM_ForceLevel,
4719                                         (1 << level));
4720                 break;
4721         default:
4722                 break;
4723         }
4724
4725         return 0;
4726 }
4727
4728 static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
4729 {
4730         uint32_t speedCntl = 0;
4731
4732         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
4733         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
4734                         ixPCIE_LC_SPEED_CNTL);
4735         return((uint16_t)PHM_GET_FIELD(speedCntl,
4736                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4737 }
4738
4739 static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
4740                 enum pp_clock_type type, char *buf)
4741 {
4742         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4743         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4744         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4745         struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4746         int i, now, size = 0;
4747         uint32_t clock, pcie_speed;
4748
4749         switch (type) {
4750         case PP_SCLK:
4751                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4752                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4753
4754                 for (i = 0; i < sclk_table->count; i++) {
4755                         if (clock > sclk_table->dpm_levels[i].value)
4756                                 continue;
4757                         break;
4758                 }
4759                 now = i;
4760
4761                 for (i = 0; i < sclk_table->count; i++)
4762                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4763                                         i, sclk_table->dpm_levels[i].value / 100,
4764                                         (i == now) ? "*" : "");
4765                 break;
4766         case PP_MCLK:
4767                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4768                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4769
4770                 for (i = 0; i < mclk_table->count; i++) {
4771                         if (clock > mclk_table->dpm_levels[i].value)
4772                                 continue;
4773                         break;
4774                 }
4775                 now = i;
4776
4777                 for (i = 0; i < mclk_table->count; i++)
4778                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4779                                         i, mclk_table->dpm_levels[i].value / 100,
4780                                         (i == now) ? "*" : "");
4781                 break;
4782         case PP_PCIE:
4783                 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
4784                 for (i = 0; i < pcie_table->count; i++) {
4785                         if (pcie_speed != pcie_table->dpm_levels[i].value)
4786                                 continue;
4787                         break;
4788                 }
4789                 now = i;
4790
4791                 for (i = 0; i < pcie_table->count; i++)
4792                         size += sprintf(buf + size, "%d: %s %s\n", i,
4793                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
4794                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
4795                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
4796                                         (i == now) ? "*" : "");
4797                 break;
4798         default:
4799                 break;
4800         }
4801         return size;
4802 }
4803
4804 static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
4805         .backend_init = &polaris10_hwmgr_backend_init,
4806         .backend_fini = &polaris10_hwmgr_backend_fini,
4807         .asic_setup = &polaris10_setup_asic_task,
4808         .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
4809         .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
4810         .force_dpm_level = &polaris10_force_dpm_level,
4811         .power_state_set = polaris10_set_power_state_tasks,
4812         .get_power_state_size = polaris10_get_power_state_size,
4813         .get_mclk = polaris10_dpm_get_mclk,
4814         .get_sclk = polaris10_dpm_get_sclk,
4815         .patch_boot_state = polaris10_dpm_patch_boot_state,
4816         .get_pp_table_entry = polaris10_get_pp_table_entry,
4817         .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
4818         .print_current_perforce_level = polaris10_print_current_perforce_level,
4819         .powerdown_uvd = polaris10_phm_powerdown_uvd,
4820         .powergate_uvd = polaris10_phm_powergate_uvd,
4821         .powergate_vce = polaris10_phm_powergate_vce,
4822         .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
4823         .update_clock_gatings = polaris10_phm_update_clock_gatings,
4824         .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
4825         .display_config_changed = polaris10_display_configuration_changed_task,
4826         .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
4827         .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
4828         .get_temperature = polaris10_thermal_get_temperature,
4829         .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
4830         .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
4831         .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
4832         .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
4833         .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
4834         .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
4835         .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
4836         .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
4837         .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
4838         .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
4839         .check_states_equal = polaris10_check_states_equal,
4840         .get_pp_table = polaris10_get_pp_table,
4841         .set_pp_table = polaris10_set_pp_table,
4842         .force_clock_level = polaris10_force_clock_level,
4843         .print_clock_levels = polaris10_print_clock_levels,
4844         .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
4845 };
4846
4847 int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
4848 {
4849         struct polaris10_hwmgr  *data;
4850
4851         data = kzalloc (sizeof(struct polaris10_hwmgr), GFP_KERNEL);
4852         if (data == NULL)
4853                 return -ENOMEM;
4854
4855         hwmgr->backend = data;
4856         hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
4857         hwmgr->pptable_func = &tonga_pptable_funcs;
4858         pp_polaris10_thermal_initialize(hwmgr);
4859
4860         return 0;
4861 }