drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/fb.h>
  26 #include <asm/div64.h>
  27 #include "linux/delay.h"
  28 #include "pp_acpi.h"
  29 #include "hwmgr.h"
  30 #include "polaris10_hwmgr.h"
  31 #include "polaris10_powertune.h"
  32 #include "polaris10_dyn_defaults.h"
  33 #include "polaris10_smumgr.h"
  34 #include "pp_debug.h"
  35 #include "ppatomctrl.h"
  36 #include "atombios.h"
  37 #include "tonga_pptable.h"
  38 #include "pppcielanes.h"
  39 #include "amd_pcie_helpers.h"
  40 #include "hardwaremanager.h"
  41 #include "tonga_processpptables.h"
  42 #include "cgs_common.h"
  43 #include "smu74.h"
  44 #include "smu_ucode_xfer_vi.h"
  45 #include "smu74_discrete.h"
  46 #include "smu/smu_7_1_3_d.h"
  47 #include "smu/smu_7_1_3_sh_mask.h"
  48 #include "gmc/gmc_8_1_d.h"
  49 #include "gmc/gmc_8_1_sh_mask.h"
  50 #include "oss/oss_3_0_d.h"
  51 #include "gca/gfx_8_0_d.h"
  52 #include "bif/bif_5_0_d.h"
  53 #include "bif/bif_5_0_sh_mask.h"
  54 #include "gmc/gmc_8_1_d.h"
  55 #include "gmc/gmc_8_1_sh_mask.h"
  56 #include "bif/bif_5_0_d.h"
  57 #include "bif/bif_5_0_sh_mask.h"
  58 #include "dce/dce_10_0_d.h"
  59 #include "dce/dce_10_0_sh_mask.h"
  60
  61 #include "polaris10_thermal.h"
  62 #include "polaris10_clockpowergating.h"
  63
  64 #define MC_CG_ARB_FREQ_F0           0x0a
  65 #define MC_CG_ARB_FREQ_F1           0x0b
  66 #define MC_CG_ARB_FREQ_F2           0x0c
  67 #define MC_CG_ARB_FREQ_F3           0x0d
  68
  69 #define MC_CG_SEQ_DRAMCONF_S0       0x05
  70 #define MC_CG_SEQ_DRAMCONF_S1       0x06
  71 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
  72 #define MC_CG_SEQ_YCLK_RESUME       0x0a
  73
  74
  75 #define SMC_RAM_END 0x40000
  76
  77 #define SMC_CG_IND_START            0xc0030000
  78 #define SMC_CG_IND_END              0xc0040000
  79
  80 #define VOLTAGE_SCALE               4
  81 #define VOLTAGE_VID_OFFSET_SCALE1   625
  82 #define VOLTAGE_VID_OFFSET_SCALE2   100
  83
  84 #define VDDC_VDDCI_DELTA            200
  85
  86 #define MEM_FREQ_LOW_LATENCY        25000
  87 #define MEM_FREQ_HIGH_LATENCY       80000
  88
  89 #define MEM_LATENCY_HIGH            45
  90 #define MEM_LATENCY_LOW             35
  91 #define MEM_LATENCY_ERR             0xFFFF
  92
  93 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  94 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  95 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  96
  97
  98 #define PCIE_BUS_CLK                10000
  99 #define TCLK                        (PCIE_BUS_CLK / 10)
 100
 101
 102 static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
 103 { {600, 1050, 3, 0}, {600, 1050, 6, 1} };
 104
 105 /*  [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
 106 static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] =
 107 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
 108   { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
 109
 110 /*  [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
 111 static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] =
 112 { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
 113
 114 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 115 enum DPM_EVENT_SRC {
 116         DPM_EVENT_SRC_ANALOG = 0,
 117         DPM_EVENT_SRC_EXTERNAL = 1,
 118         DPM_EVENT_SRC_DIGITAL = 2,
 119         DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
 120         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
 121 };
 122
 123 static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
 124
 125 struct polaris10_power_state *cast_phw_polaris10_power_state(
 126                                   struct pp_hw_power_state *hw_ps)
 127 {
 128         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 129                                 "Invalid Powerstate Type!",
 130                                  return NULL);
 131
 132         return (struct polaris10_power_state *)hw_ps;
 133 }
 134
 135 const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
 136                                  const struct pp_hw_power_state *hw_ps)
 137 {
 138         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 139                                 "Invalid Powerstate Type!",
 140                                  return NULL);
 141
 142         return (const struct polaris10_power_state *)hw_ps;
 143 }
 144
 145 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
 146 {
 147         return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
 148                         CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
 149                         ? true : false;
 150 }
 151
 152 /**
 153  * Find the MC microcode version and store it in the HwMgr struct
 154  *
 155  * @param    hwmgr  the address of the powerplay hardware manager.
 156  * @return   always 0
 157  */
 158 int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
 159 {
 160         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 161
 162         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
 163
 164         return 0;
 165 }
 166
 167 uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 168 {
 169         uint32_t speedCntl = 0;
 170
 171         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 172         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
 173                         ixPCIE_LC_SPEED_CNTL);
 174         return((uint16_t)PHM_GET_FIELD(speedCntl,
 175                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 176 }
 177
 178 int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 179 {
 180         uint32_t link_width;
 181
 182         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 183         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 184                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
 185
 186         PP_ASSERT_WITH_CODE((7 >= link_width),
 187                         "Invalid PCIe lane width!", return 0);
 188
 189         return decode_pcie_lane_width(link_width);
 190 }
 191
 192 void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
 193 {
 194         struct phm_ppt_v1_information *table_info =
 195                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 196         struct phm_clock_voltage_dependency_table *table =
 197                                 table_info->vddc_dep_on_dal_pwrl;
 198         struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
 199         enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
 200         uint32_t req_vddc = 0, req_volt, i;
 201
 202         if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW &&
 203                         dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE))
 204                 return;
 205
 206         for (i = 0; i < table->count; i++) {
 207                 if (dal_power_level == table->entries[i].clk) {
 208                         req_vddc = table->entries[i].v;
 209                         break;
 210                 }
 211         }
 212
 213         vddc_table = table_info->vdd_dep_on_sclk;
 214         for (i = 0; i < vddc_table->count; i++) {
 215                 if (req_vddc <= vddc_table->entries[i].vddc) {
 216                         req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE)
 217                                         << VDDC_SHIFT;
 218                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 219                                         PPSMC_MSG_VddC_Request, req_volt);
 220                         return;
 221                 }
 222         }
 223         printk(KERN_ERR "DAL requested level can not"
 224                         " found a available voltage in VDDC DPM Table \n");
 225 }
 226
 227 /**
 228 * Enable voltage control
 229 *
 230 * @param    pHwMgr  the address of the powerplay hardware manager.
 231 * @return   always PP_Result_OK
 232 */
 233 int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
 234 {
 235         PP_ASSERT_WITH_CODE(
 236                 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
 237                 "Failed to enable voltage DPM during DPM Start Function!",
 238                 return 1;
 239         );
 240
 241         return 0;
 242 }
 243
 244 /**
 245 * Checks if we want to support voltage control
 246 *
 247 * @param    hwmgr  the address of the powerplay hardware manager.
 248 */
 249 static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
 250 {
 251         const struct polaris10_hwmgr *data =
 252                         (const struct polaris10_hwmgr *)(hwmgr->backend);
 253
 254         return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
 255 }
 256
 257 /**
 258 * Enable voltage control
 259 *
 260 * @param    hwmgr  the address of the powerplay hardware manager.
 261 * @return   always 0
 262 */
 263 static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
 264 {
 265         /* enable voltage control */
 266         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 267                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 268
 269         return 0;
 270 }
 271
 272 /**
 273 * Create Voltage Tables.
 274 *
 275 * @param    hwmgr  the address of the powerplay hardware manager.
 276 * @return   always 0
 277 */
 278 static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
 279 {
 280         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 281         struct phm_ppt_v1_information *table_info =
 282                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 283         int result;
 284
 285         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 286                 result = atomctrl_get_voltage_table_v3(hwmgr,
 287                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
 288                                 &(data->mvdd_voltage_table));
 289                 PP_ASSERT_WITH_CODE((0 == result),
 290                                 "Failed to retrieve MVDD table.",
 291                                 return result);
 292         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
 293                 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
 294                                 table_info->vdd_dep_on_mclk);
 295                 PP_ASSERT_WITH_CODE((0 == result),
 296                                 "Failed to retrieve SVI2 MVDD table from dependancy table.",
 297                                 return result;);
 298         }
 299
 300         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 301                 result = atomctrl_get_voltage_table_v3(hwmgr,
 302                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
 303                                 &(data->vddci_voltage_table));
 304                 PP_ASSERT_WITH_CODE((0 == result),
 305                                 "Failed to retrieve VDDCI table.",
 306                                 return result);
 307         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
 308                 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
 309                                 table_info->vdd_dep_on_mclk);
 310                 PP_ASSERT_WITH_CODE((0 == result),
 311                                 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
 312                                 return result);
 313         }
 314
 315         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
 316                 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
 317                                 table_info->vddc_lookup_table);
 318                 PP_ASSERT_WITH_CODE((0 == result),
 319                                 "Failed to retrieve SVI2 VDDC table from lookup table.",
 320                                 return result);
 321         }
 322
 323         PP_ASSERT_WITH_CODE(
 324                         (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
 325                         "Too many voltage values for VDDC. Trimming to fit state table.",
 326                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
 327                                                                 &(data->vddc_voltage_table)));
 328
 329         PP_ASSERT_WITH_CODE(
 330                         (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
 331                         "Too many voltage values for VDDCI. Trimming to fit state table.",
 332                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
 333                                         &(data->vddci_voltage_table)));
 334
 335         PP_ASSERT_WITH_CODE(
 336                         (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
 337                         "Too many voltage values for MVDD. Trimming to fit state table.",
 338                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
 339                                                            &(data->mvdd_voltage_table)));
 340
 341         return 0;
 342 }
 343
 344 /**
 345 * Programs static screed detection parameters
 346 *
 347 * @param    hwmgr  the address of the powerplay hardware manager.
 348 * @return   always 0
 349 */
 350 static int polaris10_program_static_screen_threshold_parameters(
 351                                                         struct pp_hwmgr *hwmgr)
 352 {
 353         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 354
 355         /* Set static screen threshold unit */
 356         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 357                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
 358                         data->static_screen_threshold_unit);
 359         /* Set static screen threshold */
 360         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 361                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
 362                         data->static_screen_threshold);
 363
 364         return 0;
 365 }
 366
 367 /**
 368 * Setup display gap for glitch free memory clock switching.
 369 *
 370 * @param    hwmgr  the address of the powerplay hardware manager.
 371 * @return   always  0
 372 */
 373 static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
 374 {
 375         uint32_t display_gap =
 376                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 377                                         ixCG_DISPLAY_GAP_CNTL);
 378
 379         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 380                         DISP_GAP, DISPLAY_GAP_IGNORE);
 381
 382         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 383                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
 384
 385         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 386                         ixCG_DISPLAY_GAP_CNTL, display_gap);
 387
 388         return 0;
 389 }
 390
 391 /**
 392 * Programs activity state transition voting clients
 393 *
 394 * @param    hwmgr  the address of the powerplay hardware manager.
 395 * @return   always  0
 396 */
 397 static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
 398 {
 399         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 400
 401         /* Clear reset for voting clients before enabling DPM */
 402         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 403                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
 404         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 405                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
 406
 407         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 408                         ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
 409         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 410                         ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
 411         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 412                         ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
 413         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 414                         ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
 415         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 416                         ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
 417         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 418                         ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
 419         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 420                         ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
 421         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 422                         ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
 423
 424         return 0;
 425 }
 426
 427 /**
 428 * Get the location of various tables inside the FW image.
 429 *
 430 * @param    hwmgr  the address of the powerplay hardware manager.
 431 * @return   always  0
 432 */
 433 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
 434 {
 435         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 436         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
 437         uint32_t tmp;
 438         int result;
 439         bool error = false;
 440
 441         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 442                         SMU7_FIRMWARE_HEADER_LOCATION +
 443                         offsetof(SMU74_Firmware_Header, DpmTable),
 444                         &tmp, data->sram_end);
 445
 446         if (0 == result)
 447                 data->dpm_table_start = tmp;
 448
 449         error |= (0 != result);
 450
 451         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 452                         SMU7_FIRMWARE_HEADER_LOCATION +
 453                         offsetof(SMU74_Firmware_Header, SoftRegisters),
 454                         &tmp, data->sram_end);
 455
 456         if (!result) {
 457                 data->soft_regs_start = tmp;
 458                 smu_data->soft_regs_start = tmp;
 459         }
 460
 461         error |= (0 != result);
 462
 463         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 464                         SMU7_FIRMWARE_HEADER_LOCATION +
 465                         offsetof(SMU74_Firmware_Header, mcRegisterTable),
 466                         &tmp, data->sram_end);
 467
 468         if (!result)
 469                 data->mc_reg_table_start = tmp;
 470
 471         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 472                         SMU7_FIRMWARE_HEADER_LOCATION +
 473                         offsetof(SMU74_Firmware_Header, FanTable),
 474                         &tmp, data->sram_end);
 475
 476         if (!result)
 477                 data->fan_table_start = tmp;
 478
 479         error |= (0 != result);
 480
 481         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 482                         SMU7_FIRMWARE_HEADER_LOCATION +
 483                         offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
 484                         &tmp, data->sram_end);
 485
 486         if (!result)
 487                 data->arb_table_start = tmp;
 488
 489         error |= (0 != result);
 490
 491         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 492                         SMU7_FIRMWARE_HEADER_LOCATION +
 493                         offsetof(SMU74_Firmware_Header, Version),
 494                         &tmp, data->sram_end);
 495
 496         if (!result)
 497                 hwmgr->microcode_version_info.SMC = tmp;
 498
 499         error |= (0 != result);
 500
 501         return error ? -1 : 0;
 502 }
 503
 504 /* Copy one arb setting to another and then switch the active set.
 505  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
 506  */
 507 static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
 508                 uint32_t arb_src, uint32_t arb_dest)
 509 {
 510         uint32_t mc_arb_dram_timing;
 511         uint32_t mc_arb_dram_timing2;
 512         uint32_t burst_time;
 513         uint32_t mc_cg_config;
 514
 515         switch (arb_src) {
 516         case MC_CG_ARB_FREQ_F0:
 517                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
 518                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
 519                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
 520                 break;
 521         case MC_CG_ARB_FREQ_F1:
 522                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
 523                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
 524                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
 525                 break;
 526         default:
 527                 return -EINVAL;
 528         }
 529
 530         switch (arb_dest) {
 531         case MC_CG_ARB_FREQ_F0:
 532                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 533                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 534                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
 535                 break;
 536         case MC_CG_ARB_FREQ_F1:
 537                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 538                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 539                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
 540                 break;
 541         default:
 542                 return -EINVAL;
 543         }
 544
 545         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
 546         mc_cg_config |= 0x0000000F;
 547         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
 548         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
 549
 550         return 0;
 551 }
 552
 553 /**
 554 * Initial switch from ARB F0->F1
 555 *
 556 * @param    hwmgr  the address of the powerplay hardware manager.
 557 * @return   always 0
 558 * This function is to be called from the SetPowerState table.
 559 */
 560 static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
 561 {
 562         return polaris10_copy_and_switch_arb_sets(hwmgr,
 563                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
 564 }
 565
 566 static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
 567 {
 568         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 569         struct phm_ppt_v1_information *table_info =
 570                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 571         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
 572         uint32_t i, max_entry;
 573
 574         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
 575                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
 576                         return -EINVAL);
 577
 578         if (data->use_pcie_performance_levels &&
 579                         !data->use_pcie_power_saving_levels) {
 580                 data->pcie_gen_power_saving = data->pcie_gen_performance;
 581                 data->pcie_lane_power_saving = data->pcie_lane_performance;
 582         } else if (!data->use_pcie_performance_levels &&
 583                         data->use_pcie_power_saving_levels) {
 584                 data->pcie_gen_performance = data->pcie_gen_power_saving;
 585                 data->pcie_lane_performance = data->pcie_lane_power_saving;
 586         }
 587
 588         phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
 589                                         SMU74_MAX_LEVELS_LINK,
 590                                         MAX_REGULAR_DPM_NUMBER);
 591
 592         if (pcie_table != NULL) {
 593                 /* max_entry is used to make sure we reserve one PCIE level
 594                  * for boot level (fix for A+A PSPP issue).
 595                  * If PCIE table from PPTable have ULV entry + 8 entries,
 596                  * then ignore the last entry.*/
 597                 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
 598                                 SMU74_MAX_LEVELS_LINK : pcie_table->count;
 599                 for (i = 1; i < max_entry; i++) {
 600                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
 601                                         get_pcie_gen_support(data->pcie_gen_cap,
 602                                                         pcie_table->entries[i].gen_speed),
 603                                         get_pcie_lane_support(data->pcie_lane_cap,
 604                                                         pcie_table->entries[i].lane_width));
 605                 }
 606                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
 607
 608                 /* Setup BIF_SCLK levels */
 609                 for (i = 0; i < max_entry; i++)
 610                         data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
 611         } else {
 612                 /* Hardcode Pcie Table */
 613                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
 614                                 get_pcie_gen_support(data->pcie_gen_cap,
 615                                                 PP_Min_PCIEGen),
 616                                 get_pcie_lane_support(data->pcie_lane_cap,
 617                                                 PP_Max_PCIELane));
 618                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
 619                                 get_pcie_gen_support(data->pcie_gen_cap,
 620                                                 PP_Min_PCIEGen),
 621                                 get_pcie_lane_support(data->pcie_lane_cap,
 622                                                 PP_Max_PCIELane));
 623                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
 624                                 get_pcie_gen_support(data->pcie_gen_cap,
 625                                                 PP_Max_PCIEGen),
 626                                 get_pcie_lane_support(data->pcie_lane_cap,
 627                                                 PP_Max_PCIELane));
 628                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
 629                                 get_pcie_gen_support(data->pcie_gen_cap,
 630                                                 PP_Max_PCIEGen),
 631                                 get_pcie_lane_support(data->pcie_lane_cap,
 632                                                 PP_Max_PCIELane));
 633                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
 634                                 get_pcie_gen_support(data->pcie_gen_cap,
 635                                                 PP_Max_PCIEGen),
 636                                 get_pcie_lane_support(data->pcie_lane_cap,
 637                                                 PP_Max_PCIELane));
 638                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
 639                                 get_pcie_gen_support(data->pcie_gen_cap,
 640                                                 PP_Max_PCIEGen),
 641                                 get_pcie_lane_support(data->pcie_lane_cap,
 642                                                 PP_Max_PCIELane));
 643
 644                 data->dpm_table.pcie_speed_table.count = 6;
 645         }
 646         /* Populate last level for boot PCIE level, but do not increment count. */
 647         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
 648                         data->dpm_table.pcie_speed_table.count,
 649                         get_pcie_gen_support(data->pcie_gen_cap,
 650                                         PP_Min_PCIEGen),
 651                         get_pcie_lane_support(data->pcie_lane_cap,
 652                                         PP_Max_PCIELane));
 653
 654         return 0;
 655 }
 656
 657 /*
 658  * This function is to initalize all DPM state tables
 659  * for SMU7 based on the dependency table.
 660  * Dynamic state patching function will then trim these
 661  * state tables to the allowed range based
 662  * on the power policy or external client requests,
 663  * such as UVD request, etc.
 664  */
 665 int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 666 {
 667         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 668         struct phm_ppt_v1_information *table_info =
 669                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 670         uint32_t i;
 671
 672         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
 673                         table_info->vdd_dep_on_sclk;
 674         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
 675                         table_info->vdd_dep_on_mclk;
 676
 677         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
 678                         "SCLK dependency table is missing. This table is mandatory",
 679                         return -EINVAL);
 680         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
 681                         "SCLK dependency table has to have is missing."
 682                         "This table is mandatory",
 683                         return -EINVAL);
 684
 685         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
 686                         "MCLK dependency table is missing. This table is mandatory",
 687                         return -EINVAL);
 688         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
 689                         "MCLK dependency table has to have is missing."
 690                         "This table is mandatory",
 691                         return -EINVAL);
 692
 693         /* clear the state table to reset everything to default */
 694         phm_reset_single_dpm_table(
 695                         &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
 696         phm_reset_single_dpm_table(
 697                         &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
 698
 699
 700         /* Initialize Sclk DPM table based on allow Sclk values */
 701         data->dpm_table.sclk_table.count = 0;
 702         for (i = 0; i < dep_sclk_table->count; i++) {
 703                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
 704                                                 dep_sclk_table->entries[i].clk) {
 705
 706                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 707                                         dep_sclk_table->entries[i].clk;
 708
 709                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
 710                                         (i == 0) ? true : false;
 711                         data->dpm_table.sclk_table.count++;
 712                 }
 713         }
 714
 715         /* Initialize Mclk DPM table based on allow Mclk values */
 716         data->dpm_table.mclk_table.count = 0;
 717         for (i = 0; i < dep_mclk_table->count; i++) {
 718                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
 719                                 [data->dpm_table.mclk_table.count - 1].value !=
 720                                                 dep_mclk_table->entries[i].clk) {
 721                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 722                                                         dep_mclk_table->entries[i].clk;
 723                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
 724                                                         (i == 0) ? true : false;
 725                         data->dpm_table.mclk_table.count++;
 726                 }
 727         }
 728
 729         /* setup PCIE gen speed levels */
 730         polaris10_setup_default_pcie_table(hwmgr);
 731
 732         /* save a copy of the default DPM table */
 733         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 734                         sizeof(struct polaris10_dpm_table));
 735
 736         return 0;
 737 }
 738
 739 uint8_t convert_to_vid(uint16_t vddc)
 740 {
 741         return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
 742 }
 743
 744 /**
 745  * Mvdd table preparation for SMC.
 746  *
 747  * @param    *hwmgr The address of the hardware manager.
 748  * @param    *table The SMC DPM table structure to be populated.
 749  * @return   0
 750  */
 751 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
 752                         SMU74_Discrete_DpmTable *table)
 753 {
 754         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 755         uint32_t count, level;
 756
 757         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 758                 count = data->mvdd_voltage_table.count;
 759                 if (count > SMU_MAX_SMIO_LEVELS)
 760                         count = SMU_MAX_SMIO_LEVELS;
 761                 for (level = 0; level < count; level++) {
 762                         table->SmioTable2.Pattern[level].Voltage =
 763                                 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
 764                         /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
 765                         table->SmioTable2.Pattern[level].Smio =
 766                                 (uint8_t) level;
 767                         table->Smio[level] |=
 768                                 data->mvdd_voltage_table.entries[level].smio_low;
 769                 }
 770                 table->SmioMask2 = data->vddci_voltage_table.mask_low;
 771
 772                 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
 773         }
 774
 775         return 0;
 776 }
 777
 778 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
 779                                         struct SMU74_Discrete_DpmTable *table)
 780 {
 781         uint32_t count, level;
 782         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 783
 784         count = data->vddci_voltage_table.count;
 785
 786         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 787                 if (count > SMU_MAX_SMIO_LEVELS)
 788                         count = SMU_MAX_SMIO_LEVELS;
 789                 for (level = 0; level < count; ++level) {
 790                         table->SmioTable1.Pattern[level].Voltage =
 791                                 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
 792                         table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
 793
 794                         table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
 795                 }
 796         }
 797
 798         table->SmioMask1 = data->vddci_voltage_table.mask_low;
 799
 800         return 0;
 801 }
 802
 803 /**
 804 * Preparation of vddc and vddgfx CAC tables for SMC.
 805 *
 806 * @param    hwmgr  the address of the hardware manager
 807 * @param    table  the SMC DPM table structure to be populated
 808 * @return   always 0
 809 */
 810 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
 811                 struct SMU74_Discrete_DpmTable *table)
 812 {
 813         uint32_t count;
 814         uint8_t index;
 815         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 816         struct phm_ppt_v1_information *table_info =
 817                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 818         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
 819                         table_info->vddc_lookup_table;
 820         /* tables is already swapped, so in order to use the value from it,
 821          * we need to swap it back.
 822          * We are populating vddc CAC data to BapmVddc table
 823          * in split and merged mode
 824          */
 825         for (count = 0; count < lookup_table->count; count++) {
 826                 index = phm_get_voltage_index(lookup_table,
 827                                 data->vddc_voltage_table.entries[count].value);
 828                 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
 829                 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
 830                 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
 831         }
 832
 833         return 0;
 834 }
 835
 836 /**
 837 * Preparation of voltage tables for SMC.
 838 *
 839 * @param    hwmgr   the address of the hardware manager
 840 * @param    table   the SMC DPM table structure to be populated
 841 * @return   always  0
 842 */
 843
 844 int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
 845                 struct SMU74_Discrete_DpmTable *table)
 846 {
 847         polaris10_populate_smc_vddci_table(hwmgr, table);
 848         polaris10_populate_smc_mvdd_table(hwmgr, table);
 849         polaris10_populate_cac_table(hwmgr, table);
 850
 851         return 0;
 852 }
 853
 854 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
 855                 struct SMU74_Discrete_Ulv *state)
 856 {
 857         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 858         struct phm_ppt_v1_information *table_info =
 859                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 860
 861         state->CcPwrDynRm = 0;
 862         state->CcPwrDynRm1 = 0;
 863
 864         state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
 865         state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
 866                         VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
 867
 868         state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
 869
 870         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
 871         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
 872         CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
 873
 874         return 0;
 875 }
 876
 877 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
 878                 struct SMU74_Discrete_DpmTable *table)
 879 {
 880         return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
 881 }
 882
 883 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
 884                 struct SMU74_Discrete_DpmTable *table)
 885 {
 886         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 887         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
 888         int i;
 889
 890         /* Index (dpm_table->pcie_speed_table.count)
 891          * is reserved for PCIE boot level. */
 892         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
 893                 table->LinkLevel[i].PcieGenSpeed  =
 894                                 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
 895                 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
 896                                 dpm_table->pcie_speed_table.dpm_levels[i].param1);
 897                 table->LinkLevel[i].EnabledForActivity = 1;
 898                 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
 899                 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
 900                 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
 901         }
 902
 903         data->smc_state_table.LinkLevelCount =
 904                         (uint8_t)dpm_table->pcie_speed_table.count;
 905         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
 906                         phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
 907
 908         return 0;
 909 }
 910
 911 static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
 912 {
 913         uint32_t reference_clock, tmp;
 914         struct cgs_display_info info = {0};
 915         struct cgs_mode_info mode_info;
 916
 917         info.mode_info = &mode_info;
 918
 919         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
 920
 921         if (tmp)
 922                 return TCLK;
 923
 924         cgs_get_active_displays_info(hwmgr->device, &info);
 925         reference_clock = mode_info.ref_clock;
 926
 927         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
 928
 929         if (0 != tmp)
 930                 return reference_clock / 4;
 931
 932         return reference_clock;
 933 }
 934
 935 /**
 936 * Calculates the SCLK dividers using the provided engine clock
 937 *
 938 * @param    hwmgr  the address of the hardware manager
 939 * @param    clock  the engine clock to use to populate the structure
 940 * @param    sclk   the SMC SCLK structure to be populated
 941 */
 942 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
 943                 uint32_t clock, SMU_SclkSetting *sclk_setting)
 944 {
 945         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 946         const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
 947         struct pp_atomctrl_clock_dividers_ai dividers;
 948
 949         uint32_t ref_clock;
 950         uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
 951         uint8_t i;
 952         int result;
 953         uint64_t temp;
 954
 955         sclk_setting->SclkFrequency = clock;
 956         /* get the engine clock dividers for this clock value */
 957         result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
 958         if (result == 0) {
 959                 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
 960                 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
 961                 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
 962                 sclk_setting->PllRange = dividers.ucSclkPllRange;
 963                 sclk_setting->Sclk_slew_rate = 0x400;
 964                 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
 965                 sclk_setting->Pcc_down_slew_rate = 0xffff;
 966                 sclk_setting->SSc_En = dividers.ucSscEnable;
 967                 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
 968                 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
 969                 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
 970                 return result;
 971         }
 972
 973         ref_clock = polaris10_get_xclk(hwmgr);
 974
 975         for (i = 0; i < NUM_SCLK_RANGE; i++) {
 976                 if (clock > data->range_table[i].trans_lower_frequency
 977                 && clock <= data->range_table[i].trans_upper_frequency) {
 978                         sclk_setting->PllRange = i;
 979                         break;
 980                 }
 981         }
 982
 983         sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 984         temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 985         temp <<= 0x10;
 986         do_div(temp, ref_clock);
 987         sclk_setting->Fcw_frac = temp & 0xffff;
 988
 989         pcc_target_percent = 10; /*  Hardcode 10% for now. */
 990         pcc_target_freq = clock - (clock * pcc_target_percent / 100);
 991         sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 992
 993         ss_target_percent = 2; /*  Hardcode 2% for now. */
 994         sclk_setting->SSc_En = 0;
 995         if (ss_target_percent) {
 996                 sclk_setting->SSc_En = 1;
 997                 ss_target_freq = clock - (clock * ss_target_percent / 100);
 998                 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 999                 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
1000                 temp <<= 0x10;
1001                 do_div(temp, ref_clock);
1002                 sclk_setting->Fcw1_frac = temp & 0xffff;
1003         }
1004
1005         return 0;
1006 }
1007
1008 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
1009                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1010                 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1011 {
1012         uint32_t i;
1013         uint16_t vddci;
1014         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1015
1016         *voltage = *mvdd = 0;
1017
1018         /* clock - voltage dependency table is empty table */
1019         if (dep_table->count == 0)
1020                 return -EINVAL;
1021
1022         for (i = 0; i < dep_table->count; i++) {
1023                 /* find first sclk bigger than request */
1024                 if (dep_table->entries[i].clk >= clock) {
1025                         *voltage |= (dep_table->entries[i].vddc *
1026                                         VOLTAGE_SCALE) << VDDC_SHIFT;
1027                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1028                                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1029                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1030                         else if (dep_table->entries[i].vddci)
1031                                 *voltage |= (dep_table->entries[i].vddci *
1032                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1033                         else {
1034                                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1035                                                 (dep_table->entries[i].vddc -
1036                                                                 (uint16_t)data->vddc_vddci_delta));
1037                                 *voltage |= (vddci * VOLTAGE_SCALE) <<  VDDCI_SHIFT;
1038                         }
1039
1040                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1041                                 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1042                                         VOLTAGE_SCALE;
1043                         else if (dep_table->entries[i].mvdd)
1044                                 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1045                                         VOLTAGE_SCALE;
1046
1047                         *voltage |= 1 << PHASES_SHIFT;
1048                         return 0;
1049                 }
1050         }
1051
1052         /* sclk is bigger than max sclk in the dependence table */
1053         *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1054
1055         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1056                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1057                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1058         else if (dep_table->entries[i-1].vddci) {
1059                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1060                                 (dep_table->entries[i].vddc -
1061                                                 (uint16_t)data->vddc_vddci_delta));
1062                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1063         }
1064
1065         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1066                 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1067         else if (dep_table->entries[i].mvdd)
1068                 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1069
1070         return 0;
1071 }
1072
1073 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] =
1074 { {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
1075   {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1076   {VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
1077   {VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
1078   {VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
1079   {VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
1080   {VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
1081   {VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
1082
1083 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
1084 {
1085         uint32_t i, ref_clk;
1086         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1087         SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
1088         struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1089
1090         ref_clk = polaris10_get_xclk(hwmgr);
1091
1092         if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1093                 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1094                         table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1095                         table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1096                         table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1097
1098                         table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1099                         table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1100
1101                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1102                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1103                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1104                 }
1105                 return;
1106         }
1107
1108         for (i = 0; i < NUM_SCLK_RANGE; i++) {
1109
1110                 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1111                 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1112
1113                 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1114                 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1115                 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1116
1117                 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1118                 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1119
1120                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1121                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1122                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1123         }
1124 }
1125
1126 /**
1127 * Populates single SMC SCLK structure using the provided engine clock
1128 *
1129 * @param    hwmgr      the address of the hardware manager
1130 * @param    clock the engine clock to use to populate the structure
1131 * @param    sclk        the SMC SCLK structure to be populated
1132 */
1133
1134 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1135                 uint32_t clock, uint16_t sclk_al_threshold,
1136                 struct SMU74_Discrete_GraphicsLevel *level)
1137 {
1138         int result, i, temp;
1139         /* PP_Clocks minClocks; */
1140         uint32_t mvdd;
1141         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1142         struct phm_ppt_v1_information *table_info =
1143                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1144         SMU_SclkSetting curr_sclk_setting = { 0 };
1145
1146         result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
1147
1148         /* populate graphics levels */
1149         result = polaris10_get_dependency_volt_by_clk(hwmgr,
1150                         table_info->vdd_dep_on_sclk, clock,
1151                         &level->MinVoltage, &mvdd);
1152
1153         PP_ASSERT_WITH_CODE((0 == result),
1154                         "can not find VDDC voltage value for "
1155                         "VDDC engine clock dependency table",
1156                         return result);
1157         level->ActivityLevel = sclk_al_threshold;
1158
1159         level->CcPwrDynRm = 0;
1160         level->CcPwrDynRm1 = 0;
1161         level->EnabledForActivity = 0;
1162         level->EnabledForThrottle = 1;
1163         level->UpHyst = 10;
1164         level->DownHyst = 0;
1165         level->VoltageDownHyst = 0;
1166         level->PowerThrottle = 0;
1167
1168         /*
1169         * TODO: get minimum clocks from dal configaration
1170         * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1171         */
1172         /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1173
1174         /* get level->DeepSleepDivId
1175         if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1176                 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1177         */
1178         PP_ASSERT_WITH_CODE((clock >= POLARIS10_MINIMUM_ENGINE_CLOCK), "Engine clock can't satisfy stutter requirement!", return 0);
1179         for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
1180                 temp = clock >> i;
1181
1182                 if (temp >= POLARIS10_MINIMUM_ENGINE_CLOCK || i == 0)
1183                         break;
1184         }
1185
1186         level->DeepSleepDivId = i;
1187
1188         /* Default to slow, highest DPM level will be
1189          * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1190          */
1191         if (data->update_up_hyst)
1192                 level->UpHyst = (uint8_t)data->up_hyst;
1193         if (data->update_down_hyst)
1194                 level->DownHyst = (uint8_t)data->down_hyst;
1195
1196         level->SclkSetting = curr_sclk_setting;
1197
1198         CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1199         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1200         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1201         CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1202         CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1203         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1204         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1205         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1206         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1207         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1208         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1209         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1210         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1211         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1212         return 0;
1213 }
1214
1215 /**
1216 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1217 *
1218 * @param    hwmgr      the address of the hardware manager
1219 */
1220 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1221 {
1222         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1223         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1224         struct phm_ppt_v1_information *table_info =
1225                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1226         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1227         uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1228         int result = 0;
1229         uint32_t array = data->dpm_table_start +
1230                         offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1231         uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1232                         SMU74_MAX_LEVELS_GRAPHICS;
1233         struct SMU74_Discrete_GraphicsLevel *levels =
1234                         data->smc_state_table.GraphicsLevel;
1235         uint32_t i, max_entry;
1236         uint8_t hightest_pcie_level_enabled = 0,
1237                 lowest_pcie_level_enabled = 0,
1238                 mid_pcie_level_enabled = 0,
1239                 count = 0;
1240
1241         polaris10_get_sclk_range_table(hwmgr);
1242
1243         for (i = 0; i < dpm_table->sclk_table.count; i++) {
1244
1245                 result = polaris10_populate_single_graphic_level(hwmgr,
1246                                 dpm_table->sclk_table.dpm_levels[i].value,
1247                                 (uint16_t)data->activity_target[i],
1248                                 &(data->smc_state_table.GraphicsLevel[i]));
1249                 if (result)
1250                         return result;
1251
1252                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1253                 if (i > 1)
1254                         levels[i].DeepSleepDivId = 0;
1255         }
1256         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1257                                         PHM_PlatformCaps_SPLLShutdownSupport))
1258                 data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1259
1260         data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1261         data->smc_state_table.GraphicsDpmLevelCount =
1262                         (uint8_t)dpm_table->sclk_table.count;
1263         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1264                         phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1265
1266
1267         if (pcie_table != NULL) {
1268                 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1269                                 "There must be 1 or more PCIE levels defined in PPTable.",
1270                                 return -EINVAL);
1271                 max_entry = pcie_entry_cnt - 1;
1272                 for (i = 0; i < dpm_table->sclk_table.count; i++)
1273                         levels[i].pcieDpmLevel =
1274                                         (uint8_t) ((i < max_entry) ? i : max_entry);
1275         } else {
1276                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1277                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1278                                                 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1279                         hightest_pcie_level_enabled++;
1280
1281                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1282                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1283                                                 (1 << lowest_pcie_level_enabled)) == 0))
1284                         lowest_pcie_level_enabled++;
1285
1286                 while ((count < hightest_pcie_level_enabled) &&
1287                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1288                                                 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1289                         count++;
1290
1291                 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1292                                 hightest_pcie_level_enabled ?
1293                                                 (lowest_pcie_level_enabled + 1 + count) :
1294                                                 hightest_pcie_level_enabled;
1295
1296                 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1297                 for (i = 2; i < dpm_table->sclk_table.count; i++)
1298                         levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1299
1300                 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1301                 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1302
1303                 /* set pcieDpmLevel to mid_pcie_level_enabled */
1304                 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1305         }
1306         /* level count will send to smc once at init smc table and never change */
1307         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1308                         (uint32_t)array_size, data->sram_end);
1309
1310         return result;
1311 }
1312
1313 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1314                 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1315 {
1316         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1317         struct phm_ppt_v1_information *table_info =
1318                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1319         int result = 0;
1320         struct cgs_display_info info = {0, 0, NULL};
1321
1322         cgs_get_active_displays_info(hwmgr->device, &info);
1323
1324         if (table_info->vdd_dep_on_mclk) {
1325                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1326                                 table_info->vdd_dep_on_mclk, clock,
1327                                 &mem_level->MinVoltage, &mem_level->MinMvdd);
1328                 PP_ASSERT_WITH_CODE((0 == result),
1329                                 "can not find MinVddc voltage value from memory "
1330                                 "VDDC voltage dependency table", return result);
1331         }
1332
1333         mem_level->MclkFrequency = clock;
1334         mem_level->StutterEnable = 0;
1335         mem_level->EnabledForThrottle = 1;
1336         mem_level->EnabledForActivity = 0;
1337         mem_level->UpHyst = 0;
1338         mem_level->DownHyst = 100;
1339         mem_level->VoltageDownHyst = 0;
1340         mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1341         mem_level->StutterEnable = false;
1342
1343         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1344
1345         data->display_timing.num_existing_displays = info.display_count;
1346
1347         if ((data->mclk_stutter_mode_threshold) &&
1348                 (clock <= data->mclk_stutter_mode_threshold) &&
1349                 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1350                                 STUTTER_ENABLE) & 0x1))
1351                 mem_level->StutterEnable = true;
1352
1353         if (!result) {
1354                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1355                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1356                 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1357                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1358         }
1359         return result;
1360 }
1361
1362 /**
1363 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1364 *
1365 * @param    hwmgr      the address of the hardware manager
1366 */
1367 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1368 {
1369         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1370         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1371         int result;
1372         /* populate MCLK dpm table to SMU7 */
1373         uint32_t array = data->dpm_table_start +
1374                         offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1375         uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1376                         SMU74_MAX_LEVELS_MEMORY;
1377         struct SMU74_Discrete_MemoryLevel *levels =
1378                         data->smc_state_table.MemoryLevel;
1379         uint32_t i;
1380
1381         for (i = 0; i < dpm_table->mclk_table.count; i++) {
1382                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1383                                 "can not populate memory level as memory clock is zero",
1384                                 return -EINVAL);
1385                 result = polaris10_populate_single_memory_level(hwmgr,
1386                                 dpm_table->mclk_table.dpm_levels[i].value,
1387                                 &levels[i]);
1388                 if (i == dpm_table->mclk_table.count - 1) {
1389                         levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1390                         levels[i].EnabledForActivity = 1;
1391                 }
1392                 if (result)
1393                         return result;
1394         }
1395
1396         /* in order to prevent MC activity from stutter mode to push DPM up.
1397          * the UVD change complements this by putting the MCLK in
1398          * a higher state by default such that we are not effected by
1399          * up threshold or and MCLK DPM latency.
1400          */
1401         levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
1402         CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1403
1404         data->smc_state_table.MemoryDpmLevelCount =
1405                         (uint8_t)dpm_table->mclk_table.count;
1406         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1407                         phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1408
1409         /* level count will send to smc once at init smc table and never change */
1410         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1411                         (uint32_t)array_size, data->sram_end);
1412
1413         return result;
1414 }
1415
1416 /**
1417 * Populates the SMC MVDD structure using the provided memory clock.
1418 *
1419 * @param    hwmgr      the address of the hardware manager
1420 * @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
1421 * @param    voltage     the SMC VOLTAGE structure to be populated
1422 */
1423 int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1424                 uint32_t mclk, SMIO_Pattern *smio_pat)
1425 {
1426         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1427         struct phm_ppt_v1_information *table_info =
1428                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1429         uint32_t i = 0;
1430
1431         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1432                 /* find mvdd value which clock is more than request */
1433                 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1434                         if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1435                                 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1436                                 break;
1437                         }
1438                 }
1439                 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1440                                 "MVDD Voltage is outside the supported range.",
1441                                 return -EINVAL);
1442         } else
1443                 return -EINVAL;
1444
1445         return 0;
1446 }
1447
1448 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1449                 SMU74_Discrete_DpmTable *table)
1450 {
1451         int result = 0;
1452         uint32_t sclk_frequency;
1453         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1454         struct phm_ppt_v1_information *table_info =
1455                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1456         SMIO_Pattern vol_level;
1457         uint32_t mvdd;
1458         uint16_t us_mvdd;
1459
1460         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1461
1462         if (!data->sclk_dpm_key_disabled) {
1463                 /* Get MinVoltage and Frequency from DPM0,
1464                  * already converted to SMC_UL */
1465                 sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
1466                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1467                                 table_info->vdd_dep_on_sclk,
1468                                 table->ACPILevel.SclkFrequency,
1469                                 &table->ACPILevel.MinVoltage, &mvdd);
1470                 PP_ASSERT_WITH_CODE((0 == result),
1471                                 "Cannot find ACPI VDDC voltage value "
1472                                 "in Clock Dependency Table", );
1473         } else {
1474                 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1475                 table->ACPILevel.MinVoltage =
1476                                 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
1477         }
1478
1479         result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency,  &(table->ACPILevel.SclkSetting));
1480         PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1481
1482         table->ACPILevel.DeepSleepDivId = 0;
1483         table->ACPILevel.CcPwrDynRm = 0;
1484         table->ACPILevel.CcPwrDynRm1 = 0;
1485
1486         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1487         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1488         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1489         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1490
1491         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1492         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1493         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1494         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1495         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1496         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1497         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1498         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1499         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1500         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1501
1502         if (!data->mclk_dpm_key_disabled) {
1503                 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1504                 table->MemoryACPILevel.MclkFrequency =
1505                                 data->dpm_table.mclk_table.dpm_levels[0].value;
1506                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1507                                 table_info->vdd_dep_on_mclk,
1508                                 table->MemoryACPILevel.MclkFrequency,
1509                                 &table->MemoryACPILevel.MinVoltage, &mvdd);
1510                 PP_ASSERT_WITH_CODE((0 == result),
1511                                 "Cannot find ACPI VDDCI voltage value "
1512                                 "in Clock Dependency Table",
1513                                 );
1514         } else {
1515                 table->MemoryACPILevel.MclkFrequency =
1516                                 data->vbios_boot_state.mclk_bootup_value;
1517                 table->MemoryACPILevel.MinVoltage =
1518                                 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
1519         }
1520
1521         us_mvdd = 0;
1522         if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1523                         (data->mclk_dpm_key_disabled))
1524                 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1525         else {
1526                 if (!polaris10_populate_mvdd_value(hwmgr,
1527                                 data->dpm_table.mclk_table.dpm_levels[0].value,
1528                                 &vol_level))
1529                         us_mvdd = vol_level.Voltage;
1530         }
1531
1532         if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1533                 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1534         else
1535                 table->MemoryACPILevel.MinMvdd = 0;
1536
1537         table->MemoryACPILevel.StutterEnable = false;
1538
1539         table->MemoryACPILevel.EnabledForThrottle = 0;
1540         table->MemoryACPILevel.EnabledForActivity = 0;
1541         table->MemoryACPILevel.UpHyst = 0;
1542         table->MemoryACPILevel.DownHyst = 100;
1543         table->MemoryACPILevel.VoltageDownHyst = 0;
1544         table->MemoryACPILevel.ActivityLevel =
1545                         PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1546
1547         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1548         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1549
1550         return result;
1551 }
1552
1553 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1554                 SMU74_Discrete_DpmTable *table)
1555 {
1556         int result = -EINVAL;
1557         uint8_t count;
1558         struct pp_atomctrl_clock_dividers_vi dividers;
1559         struct phm_ppt_v1_information *table_info =
1560                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1561         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1562                         table_info->mm_dep_table;
1563         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1564
1565         table->VceLevelCount = (uint8_t)(mm_table->count);
1566         table->VceBootLevel = 0;
1567
1568         for (count = 0; count < table->VceLevelCount; count++) {
1569                 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1570                 table->VceLevel[count].MinVoltage = 0;
1571                 table->VceLevel[count].MinVoltage |=
1572                                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1573                 table->VceLevel[count].MinVoltage |=
1574                                 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
1575                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1576                 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1577
1578                 /*retrieve divider value for VBIOS */
1579                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1580                                 table->VceLevel[count].Frequency, &dividers);
1581                 PP_ASSERT_WITH_CODE((0 == result),
1582                                 "can not find divide id for VCE engine clock",
1583                                 return result);
1584
1585                 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1586
1587                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1588                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1589         }
1590         return result;
1591 }
1592
1593 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1594                 SMU74_Discrete_DpmTable *table)
1595 {
1596         int result = -EINVAL;
1597         uint8_t count;
1598         struct pp_atomctrl_clock_dividers_vi dividers;
1599         struct phm_ppt_v1_information *table_info =
1600                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1601         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1602                         table_info->mm_dep_table;
1603         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1604
1605         table->SamuBootLevel = 0;
1606         table->SamuLevelCount = (uint8_t)(mm_table->count);
1607
1608         for (count = 0; count < table->SamuLevelCount; count++) {
1609                 /* not sure whether we need evclk or not */
1610                 table->SamuLevel[count].MinVoltage = 0;
1611                 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1612                 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1613                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1614                 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1615                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1616                 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1617
1618                 /* retrieve divider value for VBIOS */
1619                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1620                                 table->SamuLevel[count].Frequency, &dividers);
1621                 PP_ASSERT_WITH_CODE((0 == result),
1622                                 "can not find divide id for samu clock", return result);
1623
1624                 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1625
1626                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1627                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1628         }
1629         return result;
1630 }
1631
1632 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1633                 int32_t eng_clock, int32_t mem_clock,
1634                 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1635 {
1636         uint32_t dram_timing;
1637         uint32_t dram_timing2;
1638         uint32_t burst_time;
1639         int result;
1640
1641         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1642                         eng_clock, mem_clock);
1643         PP_ASSERT_WITH_CODE(result == 0,
1644                         "Error calling VBIOS to set DRAM_TIMING.", return result);
1645
1646         dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1647         dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1648         burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1649
1650
1651         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
1652         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1653         arb_regs->McArbBurstTime   = (uint8_t)burst_time;
1654
1655         return 0;
1656 }
1657
1658 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1659 {
1660         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1661         struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1662         uint32_t i, j;
1663         int result = 0;
1664
1665         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1666                 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1667                         result = polaris10_populate_memory_timing_parameters(hwmgr,
1668                                         data->dpm_table.sclk_table.dpm_levels[i].value,
1669                                         data->dpm_table.mclk_table.dpm_levels[j].value,
1670                                         &arb_regs.entries[i][j]);
1671                         if (result == 0)
1672                                 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1673                         if (result != 0)
1674                                 return result;
1675                 }
1676         }
1677
1678         result = polaris10_copy_bytes_to_smc(
1679                         hwmgr->smumgr,
1680                         data->arb_table_start,
1681                         (uint8_t *)&arb_regs,
1682                         sizeof(SMU74_Discrete_MCArbDramTimingTable),
1683                         data->sram_end);
1684         return result;
1685 }
1686
1687 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1688                 struct SMU74_Discrete_DpmTable *table)
1689 {
1690         int result = -EINVAL;
1691         uint8_t count;
1692         struct pp_atomctrl_clock_dividers_vi dividers;
1693         struct phm_ppt_v1_information *table_info =
1694                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1695         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1696                         table_info->mm_dep_table;
1697         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1698
1699         table->UvdLevelCount = (uint8_t)(mm_table->count);
1700         table->UvdBootLevel = 0;
1701
1702         for (count = 0; count < table->UvdLevelCount; count++) {
1703                 table->UvdLevel[count].MinVoltage = 0;
1704                 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1705                 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1706                 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1707                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1708                 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1709                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1710                 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1711
1712                 /* retrieve divider value for VBIOS */
1713                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1714                                 table->UvdLevel[count].VclkFrequency, &dividers);
1715                 PP_ASSERT_WITH_CODE((0 == result),
1716                                 "can not find divide id for Vclk clock", return result);
1717
1718                 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1719
1720                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1721                                 table->UvdLevel[count].DclkFrequency, &dividers);
1722                 PP_ASSERT_WITH_CODE((0 == result),
1723                                 "can not find divide id for Dclk clock", return result);
1724
1725                 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1726
1727                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1728                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1729                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1730
1731         }
1732         return result;
1733 }
1734
1735 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1736                 struct SMU74_Discrete_DpmTable *table)
1737 {
1738         int result = 0;
1739         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1740
1741         table->GraphicsBootLevel = 0;
1742         table->MemoryBootLevel = 0;
1743
1744         /* find boot level from dpm table */
1745         result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1746                         data->vbios_boot_state.sclk_bootup_value,
1747                         (uint32_t *)&(table->GraphicsBootLevel));
1748
1749         result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1750                         data->vbios_boot_state.mclk_bootup_value,
1751                         (uint32_t *)&(table->MemoryBootLevel));
1752
1753         table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
1754                         VOLTAGE_SCALE;
1755         table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1756                         VOLTAGE_SCALE;
1757         table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
1758                         VOLTAGE_SCALE;
1759
1760         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1761         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1762         CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1763
1764         return 0;
1765 }
1766
1767
1768 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1769 {
1770         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1771         struct phm_ppt_v1_information *table_info =
1772                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1773         uint8_t count, level;
1774
1775         count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1776
1777         for (level = 0; level < count; level++) {
1778                 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1779                                 data->vbios_boot_state.sclk_bootup_value) {
1780                         data->smc_state_table.GraphicsBootLevel = level;
1781                         break;
1782                 }
1783         }
1784
1785         count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1786         for (level = 0; level < count; level++) {
1787                 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1788                                 data->vbios_boot_state.mclk_bootup_value) {
1789                         data->smc_state_table.MemoryBootLevel = level;
1790                         break;
1791                 }
1792         }
1793
1794         return 0;
1795 }
1796
1797 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1798 {
1799         uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
1800                         volt_with_cks, value;
1801         uint16_t clock_freq_u16;
1802         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1803         uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
1804                         volt_offset = 0;
1805         struct phm_ppt_v1_information *table_info =
1806                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1807         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1808                         table_info->vdd_dep_on_sclk;
1809
1810         stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1811
1812         /* Read SMU_Eefuse to read and calculate RO and determine
1813          * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1814          */
1815         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1816                         ixSMU_EFUSE_0 + (146 * 4));
1817         efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1818                         ixSMU_EFUSE_0 + (148 * 4));
1819         efuse &= 0xFF000000;
1820         efuse = efuse >> 24;
1821         efuse2 &= 0xF;
1822
1823         if (efuse2 == 1)
1824                 ro = (2300 - 1350) * efuse / 255 + 1350;
1825         else
1826                 ro = (2500 - 1000) * efuse / 255 + 1000;
1827
1828         if (ro >= 1660)
1829                 type = 0;
1830         else
1831                 type = 1;
1832
1833         /* Populate Stretch amount */
1834         data->smc_state_table.ClockStretcherAmount = stretch_amount;
1835
1836         /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1837         for (i = 0; i < sclk_table->count; i++) {
1838                 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1839                                 sclk_table->entries[i].cks_enable << i;
1840                 volt_without_cks = (uint32_t)((14041 *
1841                         (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
1842                         (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
1843                 volt_with_cks = (uint32_t)((13946 *
1844                         (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
1845                         (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
1846                 if (volt_without_cks >= volt_with_cks)
1847                         volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1848                                         sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
1849                 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1850         }
1851
1852         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1853                         STRETCH_ENABLE, 0x0);
1854         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1855                         masterReset, 0x1);
1856         /* PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, staticEnable, 0x1); */
1857         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1858                         masterReset, 0x0);
1859
1860         /* Populate CKS Lookup Table */
1861         if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1862                 stretch_amount2 = 0;
1863         else if (stretch_amount == 3 || stretch_amount == 4)
1864                 stretch_amount2 = 1;
1865         else {
1866                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1867                                 PHM_PlatformCaps_ClockStretcher);
1868                 PP_ASSERT_WITH_CODE(false,
1869                                 "Stretch Amount in PPTable not supported\n",
1870                                 return -EINVAL);
1871         }
1872
1873         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1874                         ixPWR_CKS_CNTL);
1875         value &= 0xFFC2FF87;
1876         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
1877                         polaris10_clock_stretcher_lookup_table[stretch_amount2][0];
1878         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
1879                         polaris10_clock_stretcher_lookup_table[stretch_amount2][1];
1880         clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
1881                         GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].SclkSetting.SclkFrequency) / 100);
1882         if (polaris10_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16
1883         && polaris10_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) {
1884                 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
1885                 value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
1886                 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
1887                 value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
1888                 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
1889                 value |= (polaris10_clock_stretch_amount_conversion
1890                                 [polaris10_clock_stretcher_lookup_table[stretch_amount2][3]]
1891                                  [stretch_amount]) << 3;
1892         }
1893         CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq);
1894         CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq);
1895         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
1896                         polaris10_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
1897         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
1898                         (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
1899
1900         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1901                         ixPWR_CKS_CNTL, value);
1902
1903         /* Populate DDT Lookup Table */
1904         for (i = 0; i < 4; i++) {
1905                 /* Assign the minimum and maximum VID stored
1906                  * in the last row of Clock Stretcher Voltage Table.
1907                  */
1908                 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].minVID =
1909                                 (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][2];
1910                 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].maxVID =
1911                                 (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][3];
1912                 /* Loop through each SCLK and check the frequency
1913                  * to see if it lies within the frequency for clock stretcher.
1914                  */
1915                 for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
1916                         cks_setting = 0;
1917                         clock_freq = PP_SMC_TO_HOST_UL(
1918                                         data->smc_state_table.GraphicsLevel[j].SclkSetting.SclkFrequency);
1919                         /* Check the allowed frequency against the sclk level[j].
1920                          *  Sclk's endianness has already been converted,
1921                          *  and it's in 10Khz unit,
1922                          *  as opposed to Data table, which is in Mhz unit.
1923                          */
1924                         if (clock_freq >= (polaris10_clock_stretcher_ddt_table[type][i][0]) * 100) {
1925                                 cks_setting |= 0x2;
1926                                 if (clock_freq < (polaris10_clock_stretcher_ddt_table[type][i][1]) * 100)
1927                                         cks_setting |= 0x1;
1928                         }
1929                         data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting
1930                                                         |= cks_setting << (j * 2);
1931                 }
1932                 CONVERT_FROM_HOST_TO_SMC_US(
1933                         data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting);
1934         }
1935
1936         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1937         value &= 0xFFFFFFFE;
1938         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1939
1940         return 0;
1941 }
1942
1943 /**
1944 * Populates the SMC VRConfig field in DPM table.
1945 *
1946 * @param    hwmgr   the address of the hardware manager
1947 * @param    table   the SMC DPM table structure to be populated
1948 * @return   always 0
1949 */
1950 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1951                 struct SMU74_Discrete_DpmTable *table)
1952 {
1953         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1954         uint16_t config;
1955
1956         config = VR_MERGED_WITH_VDDC;
1957         table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1958
1959         /* Set Vddc Voltage Controller */
1960         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1961                 config = VR_SVI2_PLANE_1;
1962                 table->VRConfig |= config;
1963         } else {
1964                 PP_ASSERT_WITH_CODE(false,
1965                                 "VDDC should be on SVI2 control in merged mode!",
1966                                 );
1967         }
1968         /* Set Vddci Voltage Controller */
1969         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1970                 config = VR_SVI2_PLANE_2;  /* only in merged mode */
1971                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1972         } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1973                 config = VR_SMIO_PATTERN_1;
1974                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1975         } else {
1976                 config = VR_STATIC_VOLTAGE;
1977                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1978         }
1979         /* Set Mvdd Voltage Controller */
1980         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1981                 config = VR_SVI2_PLANE_2;
1982                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1983         } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1984                 config = VR_SMIO_PATTERN_2;
1985                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1986         } else {
1987                 config = VR_STATIC_VOLTAGE;
1988                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1989         }
1990
1991         return 0;
1992 }
1993
1994 /**
1995 * Initializes the SMC table and uploads it
1996 *
1997 * @param    hwmgr  the address of the powerplay hardware manager.
1998 * @return   always 0
1999 */
2000 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
2001 {
2002         int result;
2003         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2004         struct phm_ppt_v1_information *table_info =
2005                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2006         struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
2007         const struct polaris10_ulv_parm *ulv = &(data->ulv);
2008         uint8_t i;
2009         struct pp_atomctrl_gpio_pin_assignment gpio_pin;
2010         pp_atomctrl_clock_dividers_vi dividers;
2011
2012         result = polaris10_setup_default_dpm_tables(hwmgr);
2013         PP_ASSERT_WITH_CODE(0 == result,
2014                         "Failed to setup default DPM tables!", return result);
2015
2016         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
2017                 polaris10_populate_smc_voltage_tables(hwmgr, table);
2018
2019         table->SystemFlags = 0;
2020         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2021                         PHM_PlatformCaps_AutomaticDCTransition))
2022                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2023
2024         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2025                         PHM_PlatformCaps_StepVddc))
2026                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2027
2028         if (data->is_memory_gddr5)
2029                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2030
2031         if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2032                 result = polaris10_populate_ulv_state(hwmgr, table);
2033                 PP_ASSERT_WITH_CODE(0 == result,
2034                                 "Failed to initialize ULV state!", return result);
2035                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2036                                 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
2037         }
2038
2039         result = polaris10_populate_smc_link_level(hwmgr, table);
2040         PP_ASSERT_WITH_CODE(0 == result,
2041                         "Failed to initialize Link Level!", return result);
2042
2043         result = polaris10_populate_all_graphic_levels(hwmgr);
2044         PP_ASSERT_WITH_CODE(0 == result,
2045                         "Failed to initialize Graphics Level!", return result);
2046
2047         result = polaris10_populate_all_memory_levels(hwmgr);
2048         PP_ASSERT_WITH_CODE(0 == result,
2049                         "Failed to initialize Memory Level!", return result);
2050
2051         result = polaris10_populate_smc_acpi_level(hwmgr, table);
2052         PP_ASSERT_WITH_CODE(0 == result,
2053                         "Failed to initialize ACPI Level!", return result);
2054
2055         result = polaris10_populate_smc_vce_level(hwmgr, table);
2056         PP_ASSERT_WITH_CODE(0 == result,
2057                         "Failed to initialize VCE Level!", return result);
2058
2059         result = polaris10_populate_smc_samu_level(hwmgr, table);
2060         PP_ASSERT_WITH_CODE(0 == result,
2061                         "Failed to initialize SAMU Level!", return result);
2062
2063         /* Since only the initial state is completely set up at this point
2064          * (the other states are just copies of the boot state) we only
2065          * need to populate the  ARB settings for the initial state.
2066          */
2067         result = polaris10_program_memory_timing_parameters(hwmgr);
2068         PP_ASSERT_WITH_CODE(0 == result,
2069                         "Failed to Write ARB settings for the initial state.", return result);
2070
2071         result = polaris10_populate_smc_uvd_level(hwmgr, table);
2072         PP_ASSERT_WITH_CODE(0 == result,
2073                         "Failed to initialize UVD Level!", return result);
2074
2075         result = polaris10_populate_smc_boot_level(hwmgr, table);
2076         PP_ASSERT_WITH_CODE(0 == result,
2077                         "Failed to initialize Boot Level!", return result);
2078
2079         result = polaris10_populate_smc_initailial_state(hwmgr);
2080         PP_ASSERT_WITH_CODE(0 == result,
2081                         "Failed to initialize Boot State!", return result);
2082
2083         result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
2084         PP_ASSERT_WITH_CODE(0 == result,
2085                         "Failed to populate BAPM Parameters!", return result);
2086
2087         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2088                         PHM_PlatformCaps_ClockStretcher)) {
2089                 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
2090                 PP_ASSERT_WITH_CODE(0 == result,
2091                                 "Failed to populate Clock Stretcher Data Table!",
2092                                 return result);
2093         }
2094
2095         table->GraphicsVoltageChangeEnable  = 1;
2096         table->GraphicsThermThrottleEnable  = 1;
2097         table->GraphicsInterval = 1;
2098         table->VoltageInterval  = 1;
2099         table->ThermalInterval  = 1;
2100         table->TemperatureLimitHigh =
2101                         table_info->cac_dtp_table->usTargetOperatingTemp *
2102                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2103         table->TemperatureLimitLow  =
2104                         (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2105                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2106         table->MemoryVoltageChangeEnable = 1;
2107         table->MemoryInterval = 1;
2108         table->VoltageResponseTime = 0;
2109         table->PhaseResponseTime = 0;
2110         table->MemoryThermThrottleEnable = 1;
2111         table->PCIeBootLinkLevel = 0;
2112         table->PCIeGenInterval = 1;
2113         table->VRConfig = 0;
2114
2115         result = polaris10_populate_vr_config(hwmgr, table);
2116         PP_ASSERT_WITH_CODE(0 == result,
2117                         "Failed to populate VRConfig setting!", return result);
2118
2119         table->ThermGpio = 17;
2120         table->SclkStepSize = 0x4000;
2121
2122         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2123                 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2124         } else {
2125                 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
2126                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2127                                 PHM_PlatformCaps_RegulatorHot);
2128         }
2129
2130         if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2131                         &gpio_pin)) {
2132                 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2133                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2134                                 PHM_PlatformCaps_AutomaticDCTransition);
2135         } else {
2136                 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
2137                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2138                                 PHM_PlatformCaps_AutomaticDCTransition);
2139         }
2140
2141         /* Thermal Output GPIO */
2142         if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2143                         &gpio_pin)) {
2144                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2145                                 PHM_PlatformCaps_ThermalOutGPIO);
2146
2147                 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2148
2149                 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2150                  * since VBIOS will program this register to set 'inactive state',
2151                  * driver can then determine 'active state' from this and
2152                  * program SMU with correct polarity
2153                  */
2154                 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2155                                         & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2156                 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2157
2158                 /* if required, combine VRHot/PCC with thermal out GPIO */
2159                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2160                 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2161                         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2162         } else {
2163                 table->ThermOutGpio = 17;
2164                 table->ThermOutPolarity = 1;
2165                 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2166         }
2167
2168         /* Populate BIF_SCLK levels into SMC DPM table */
2169         for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2170                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], &dividers);
2171                 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2172
2173                 if (i == 0)
2174                         table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2175                 else
2176                         table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2177         }
2178
2179         for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2180                 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2181
2182         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2183         CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2184         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2185         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2186         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2187         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2188         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2189         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2190         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2191
2192         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2193         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
2194                         data->dpm_table_start +
2195                         offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2196                         (uint8_t *)&(table->SystemFlags),
2197                         sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2198                         data->sram_end);
2199         PP_ASSERT_WITH_CODE(0 == result,
2200                         "Failed to upload dpm data to SMC memory!", return result);
2201
2202         return 0;
2203 }
2204
2205 /**
2206 * Initialize the ARB DRAM timing table's index field.
2207 *
2208 * @param    hwmgr  the address of the powerplay hardware manager.
2209 * @return   always 0
2210 */
2211 static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
2212 {
2213         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2214         uint32_t tmp;
2215         int result;
2216
2217         /* This is a read-modify-write on the first byte of the ARB table.
2218          * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2219          * is the field 'current'.
2220          * This solution is ugly, but we never write the whole table only
2221          * individual fields in it.
2222          * In reality this field should not be in that structure
2223          * but in a soft register.
2224          */
2225         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
2226                         data->arb_table_start, &tmp, data->sram_end);
2227
2228         if (result)
2229                 return result;
2230
2231         tmp &= 0x00FFFFFF;
2232         tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2233
2234         return polaris10_write_smc_sram_dword(hwmgr->smumgr,
2235                         data->arb_table_start, tmp, data->sram_end);
2236 }
2237
2238 static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
2239 {
2240         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2241                         PHM_PlatformCaps_RegulatorHot))
2242                 return smum_send_msg_to_smc(hwmgr->smumgr,
2243                                 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2244
2245         return 0;
2246 }
2247
2248 static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
2249 {
2250         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2251                         SCLK_PWRMGT_OFF, 0);
2252         return 0;
2253 }
2254
2255 static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
2256 {
2257         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2258         struct polaris10_ulv_parm *ulv = &(data->ulv);
2259
2260         if (ulv->ulv_supported)
2261                 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2262
2263         return 0;
2264 }
2265
2266 static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2267 {
2268         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2269                         PHM_PlatformCaps_SclkDeepSleep)) {
2270                 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2271                         PP_ASSERT_WITH_CODE(false,
2272                                         "Attempt to enable Master Deep Sleep switch failed!",
2273                                         return -1);
2274         } else {
2275                 if (smum_send_msg_to_smc(hwmgr->smumgr,
2276                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2277                         PP_ASSERT_WITH_CODE(false,
2278                                         "Attempt to disable Master Deep Sleep switch failed!",
2279                                         return -1);
2280                 }
2281         }
2282
2283         return 0;
2284 }
2285
2286 static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2287 {
2288         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2289
2290         /* enable SCLK dpm */
2291         if (!data->sclk_dpm_key_disabled)
2292                 PP_ASSERT_WITH_CODE(
2293                 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2294                 "Failed to enable SCLK DPM during DPM Start Function!",
2295                 return -1);
2296
2297         /* enable MCLK dpm */
2298         if (0 == data->mclk_dpm_key_disabled) {
2299
2300                 PP_ASSERT_WITH_CODE(
2301                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2302                                                 PPSMC_MSG_MCLKDPM_Enable)),
2303                                 "Failed to enable MCLK DPM during DPM Start Function!",
2304                                 return -1);
2305
2306
2307                 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2308
2309                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2310                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2311                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2312                 udelay(10);
2313                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2314                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2315                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2316         }
2317
2318         return 0;
2319 }
2320
2321 static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
2322 {
2323         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2324
2325         /*enable general power management */
2326
2327         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2328                         GLOBAL_PWRMGT_EN, 1);
2329
2330         /* enable sclk deep sleep */
2331
2332         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2333                         DYNAMIC_PM_EN, 1);
2334
2335         /* prepare for PCIE DPM */
2336
2337         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2338                         data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2339                                         VoltageChangeTimeout), 0x1000);
2340         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2341                         SWRST_COMMAND_1, RESETLC, 0x0);
2342 /*
2343         PP_ASSERT_WITH_CODE(
2344                         (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2345                                         PPSMC_MSG_Voltage_Cntl_Enable)),
2346                         "Failed to enable voltage DPM during DPM Start Function!",
2347                         return -1);
2348 */
2349
2350         if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
2351                 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2352                 return -1;
2353         }
2354
2355         /* enable PCIE dpm */
2356         if (0 == data->pcie_dpm_key_disabled) {
2357                 PP_ASSERT_WITH_CODE(
2358                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2359                                                 PPSMC_MSG_PCIeDPM_Enable)),
2360                                 "Failed to enable pcie DPM during DPM Start Function!",
2361                                 return -1);
2362         }
2363
2364         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2365                                 PHM_PlatformCaps_Falcon_QuickTransition)) {
2366                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2367                                 PPSMC_MSG_EnableACDCGPIOInterrupt)),
2368                                 "Failed to enable AC DC GPIO Interrupt!",
2369                                 );
2370         }
2371
2372         return 0;
2373 }
2374
2375 static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
2376 {
2377         bool protection;
2378         enum DPM_EVENT_SRC src;
2379
2380         switch (sources) {
2381         default:
2382                 printk(KERN_ERR "Unknown throttling event sources.");
2383                 /* fall through */
2384         case 0:
2385                 protection = false;
2386                 /* src is unused */
2387                 break;
2388         case (1 << PHM_AutoThrottleSource_Thermal):
2389                 protection = true;
2390                 src = DPM_EVENT_SRC_DIGITAL;
2391                 break;
2392         case (1 << PHM_AutoThrottleSource_External):
2393                 protection = true;
2394                 src = DPM_EVENT_SRC_EXTERNAL;
2395                 break;
2396         case (1 << PHM_AutoThrottleSource_External) |
2397                         (1 << PHM_AutoThrottleSource_Thermal):
2398                 protection = true;
2399                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2400                 break;
2401         }
2402         /* Order matters - don't enable thermal protection for the wrong source. */
2403         if (protection) {
2404                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2405                                 DPM_EVENT_SRC, src);
2406                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2407                                 THERMAL_PROTECTION_DIS,
2408                                 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2409                                                 PHM_PlatformCaps_ThermalController));
2410         } else
2411                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2412                                 THERMAL_PROTECTION_DIS, 1);
2413 }
2414
2415 static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2416                 PHM_AutoThrottleSource source)
2417 {
2418         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2419
2420         if (!(data->active_auto_throttle_sources & (1 << source))) {
2421                 data->active_auto_throttle_sources |= 1 << source;
2422                 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2423         }
2424         return 0;
2425 }
2426
2427 static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2428 {
2429         return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2430 }
2431
2432 int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
2433 {
2434         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2435         data->pcie_performance_request = true;
2436
2437         return 0;
2438 }
2439
2440 int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2441 {
2442         int tmp_result, result = 0;
2443         tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2444         PP_ASSERT_WITH_CODE(result == 0,
2445                         "DPM is already running right now, no need to enable DPM!",
2446                         return 0);
2447
2448         if (polaris10_voltage_control(hwmgr)) {
2449                 tmp_result = polaris10_enable_voltage_control(hwmgr);
2450                 PP_ASSERT_WITH_CODE(tmp_result == 0,
2451                                 "Failed to enable voltage control!",
2452                                 result = tmp_result);
2453
2454                 tmp_result = polaris10_construct_voltage_tables(hwmgr);
2455                 PP_ASSERT_WITH_CODE((0 == tmp_result),
2456                                 "Failed to contruct voltage tables!",
2457                                 result = tmp_result);
2458         }
2459
2460         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2461                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2462                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2463                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2464
2465         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2466                         PHM_PlatformCaps_ThermalController))
2467                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2468                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2469
2470         tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
2471         PP_ASSERT_WITH_CODE((0 == tmp_result),
2472                         "Failed to program static screen threshold parameters!",
2473                         result = tmp_result);
2474
2475         tmp_result = polaris10_enable_display_gap(hwmgr);
2476         PP_ASSERT_WITH_CODE((0 == tmp_result),
2477                         "Failed to enable display gap!", result = tmp_result);
2478
2479         tmp_result = polaris10_program_voting_clients(hwmgr);
2480         PP_ASSERT_WITH_CODE((0 == tmp_result),
2481                         "Failed to program voting clients!", result = tmp_result);
2482
2483         tmp_result = polaris10_process_firmware_header(hwmgr);
2484         PP_ASSERT_WITH_CODE((0 == tmp_result),
2485                         "Failed to process firmware header!", result = tmp_result);
2486
2487         tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
2488         PP_ASSERT_WITH_CODE((0 == tmp_result),
2489                         "Failed to initialize switch from ArbF0 to F1!",
2490                         result = tmp_result);
2491
2492         tmp_result = polaris10_init_smc_table(hwmgr);
2493         PP_ASSERT_WITH_CODE((0 == tmp_result),
2494                         "Failed to initialize SMC table!", result = tmp_result);
2495
2496         tmp_result = polaris10_init_arb_table_index(hwmgr);
2497         PP_ASSERT_WITH_CODE((0 == tmp_result),
2498                         "Failed to initialize ARB table index!", result = tmp_result);
2499
2500         tmp_result = polaris10_populate_pm_fuses(hwmgr);
2501         PP_ASSERT_WITH_CODE((0 == tmp_result),
2502                         "Failed to populate PM fuses!", result = tmp_result);
2503
2504         tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
2505         PP_ASSERT_WITH_CODE((0 == tmp_result),
2506                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2507
2508         tmp_result = polaris10_enable_sclk_control(hwmgr);
2509         PP_ASSERT_WITH_CODE((0 == tmp_result),
2510                         "Failed to enable SCLK control!", result = tmp_result);
2511
2512         tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
2513         PP_ASSERT_WITH_CODE((0 == tmp_result),
2514                         "Failed to enable voltage control!", result = tmp_result);
2515
2516         tmp_result = polaris10_enable_ulv(hwmgr);
2517         PP_ASSERT_WITH_CODE((0 == tmp_result),
2518                         "Failed to enable ULV!", result = tmp_result);
2519
2520         tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
2521         PP_ASSERT_WITH_CODE((0 == tmp_result),
2522                         "Failed to enable deep sleep master switch!", result = tmp_result);
2523
2524         tmp_result = polaris10_start_dpm(hwmgr);
2525         PP_ASSERT_WITH_CODE((0 == tmp_result),
2526                         "Failed to start DPM!", result = tmp_result);
2527
2528         tmp_result = polaris10_enable_smc_cac(hwmgr);
2529         PP_ASSERT_WITH_CODE((0 == tmp_result),
2530                         "Failed to enable SMC CAC!", result = tmp_result);
2531
2532         tmp_result = polaris10_enable_power_containment(hwmgr);
2533         PP_ASSERT_WITH_CODE((0 == tmp_result),
2534                         "Failed to enable power containment!", result = tmp_result);
2535
2536         tmp_result = polaris10_power_control_set_level(hwmgr);
2537         PP_ASSERT_WITH_CODE((0 == tmp_result),
2538                         "Failed to power control set level!", result = tmp_result);
2539
2540         tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
2541         PP_ASSERT_WITH_CODE((0 == tmp_result),
2542                         "Failed to enable thermal auto throttle!", result = tmp_result);
2543
2544         tmp_result = polaris10_pcie_performance_request(hwmgr);
2545         PP_ASSERT_WITH_CODE((0 == tmp_result),
2546                         "pcie performance request failed!", result = tmp_result);
2547
2548         return result;
2549 }
2550
2551 int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2552 {
2553
2554         return 0;
2555 }
2556
2557 int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
2558 {
2559
2560         return 0;
2561 }
2562
2563 int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2564 {
2565         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2566
2567         if (data->soft_pp_table) {
2568                 kfree(data->soft_pp_table);
2569                 data->soft_pp_table = NULL;
2570         }
2571
2572         return phm_hwmgr_backend_fini(hwmgr);
2573 }
2574
2575 int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
2576 {
2577         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2578
2579         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2580                         PHM_PlatformCaps_SclkDeepSleep);
2581
2582         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2583                 PHM_PlatformCaps_DynamicPatchPowerState);
2584
2585         if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2586                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2587                                 PHM_PlatformCaps_EnableMVDDControl);
2588
2589         if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2590                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2591                                 PHM_PlatformCaps_ControlVDDCI);
2592
2593         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2594                          PHM_PlatformCaps_TablelessHardwareInterface);
2595
2596         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2597                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
2598
2599         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2600                         PHM_PlatformCaps_DynamicPowerManagement);
2601
2602         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2603                         PHM_PlatformCaps_UnTabledHardwareInterface);
2604
2605         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2606                         PHM_PlatformCaps_TablelessHardwareInterface);
2607
2608         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2609                                         PHM_PlatformCaps_SMC);
2610
2611         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2612                                         PHM_PlatformCaps_NonABMSupportInPPLib);
2613
2614         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2615                                         PHM_PlatformCaps_DynamicUVDState);
2616
2617         /* power tune caps Assume disabled */
2618         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2619                                                 PHM_PlatformCaps_SQRamping);
2620         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2621                                                 PHM_PlatformCaps_DBRamping);
2622         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2623                                                 PHM_PlatformCaps_TDRamping);
2624         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2625                                                 PHM_PlatformCaps_TCPRamping);
2626
2627         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2628                                         PHM_PlatformCaps_PowerContainment);
2629         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2630                                                         PHM_PlatformCaps_CAC);
2631
2632         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2633                                                 PHM_PlatformCaps_RegulatorHot);
2634
2635         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2636                                                 PHM_PlatformCaps_AutomaticDCTransition);
2637
2638         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2639                                                 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2640
2641         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2642                                                 PHM_PlatformCaps_FanSpeedInTableIsRPM);
2643         if (hwmgr->chip_id == CHIP_POLARIS11)
2644                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2645                                         PHM_PlatformCaps_SPLLShutdownSupport);
2646         return 0;
2647 }
2648
2649 static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
2650 {
2651         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2652
2653         polaris10_initialize_power_tune_defaults(hwmgr);
2654
2655         data->pcie_gen_performance.max = PP_PCIEGen1;
2656         data->pcie_gen_performance.min = PP_PCIEGen3;
2657         data->pcie_gen_power_saving.max = PP_PCIEGen1;
2658         data->pcie_gen_power_saving.min = PP_PCIEGen3;
2659         data->pcie_lane_performance.max = 0;
2660         data->pcie_lane_performance.min = 16;
2661         data->pcie_lane_power_saving.max = 0;
2662         data->pcie_lane_power_saving.min = 16;
2663 }
2664
2665 /**
2666 * Get Leakage VDDC based on leakage ID.
2667 *
2668 * @param    hwmgr  the address of the powerplay hardware manager.
2669 * @return   always 0
2670 */
2671 static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
2672 {
2673         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2674         uint16_t vv_id;
2675         uint16_t vddc = 0;
2676         uint16_t i, j;
2677         uint32_t sclk = 0;
2678         struct phm_ppt_v1_information *table_info =
2679                         (struct phm_ppt_v1_information *)hwmgr->pptable;
2680         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2681                         table_info->vdd_dep_on_sclk;
2682         int result;
2683
2684         for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
2685                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2686                 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2687                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
2688                         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2689                                         PHM_PlatformCaps_ClockStretcher)) {
2690                                 for (j = 1; j < sclk_table->count; j++) {
2691                                         if (sclk_table->entries[j].clk == sclk &&
2692                                                         sclk_table->entries[j].cks_enable == 0) {
2693                                                 sclk += 5000;
2694                                                 break;
2695                                         }
2696                                 }
2697                         }
2698
2699
2700                         PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2701                                                         VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
2702                                                 "Error retrieving EVV voltage value!",
2703                                                 continue);
2704
2705
2706                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
2707                         PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
2708                                         "Invalid VDDC value", result = -EINVAL;);
2709
2710                         /* the voltage should not be zero nor equal to leakage ID */
2711                         if (vddc != 0 && vddc != vv_id) {
2712                                 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2713                                 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2714                                 data->vddc_leakage.count++;
2715                         }
2716                 }
2717         }
2718
2719         return 0;
2720 }
2721
2722 /**
2723  * Change virtual leakage voltage to actual value.
2724  *
2725  * @param     hwmgr  the address of the powerplay hardware manager.
2726  * @param     pointer to changing voltage
2727  * @param     pointer to leakage table
2728  */
2729 static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2730                 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
2731 {
2732         uint32_t index;
2733
2734         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2735         for (index = 0; index < leakage_table->count; index++) {
2736                 /* if this voltage matches a leakage voltage ID */
2737                 /* patch with actual leakage voltage */
2738                 if (leakage_table->leakage_id[index] == *voltage) {
2739                         *voltage = leakage_table->actual_voltage[index];
2740                         break;
2741                 }
2742         }
2743
2744         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2745                 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2746 }
2747
2748 /**
2749 * Patch voltage lookup table by EVV leakages.
2750 *
2751 * @param     hwmgr  the address of the powerplay hardware manager.
2752 * @param     pointer to voltage lookup table
2753 * @param     pointer to leakage table
2754 * @return     always 0
2755 */
2756 static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
2757                 phm_ppt_v1_voltage_lookup_table *lookup_table,
2758                 struct polaris10_leakage_voltage *leakage_table)
2759 {
2760         uint32_t i;
2761
2762         for (i = 0; i < lookup_table->count; i++)
2763                 polaris10_patch_with_vdd_leakage(hwmgr,
2764                                 &lookup_table->entries[i].us_vdd, leakage_table);
2765
2766         return 0;
2767 }
2768
2769 static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2770                 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
2771                 uint16_t *vddc)
2772 {
2773         struct phm_ppt_v1_information *table_info =
2774                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2775         polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
2776         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2777                         table_info->max_clock_voltage_on_dc.vddc;
2778         return 0;
2779 }
2780
2781 static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
2782                 struct pp_hwmgr *hwmgr)
2783 {
2784         uint8_t entryId;
2785         uint8_t voltageId;
2786         struct phm_ppt_v1_information *table_info =
2787                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2788
2789         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2790                         table_info->vdd_dep_on_sclk;
2791         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2792                         table_info->vdd_dep_on_mclk;
2793         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2794                         table_info->mm_dep_table;
2795
2796         for (entryId = 0; entryId < sclk_table->count; ++entryId) {
2797                 voltageId = sclk_table->entries[entryId].vddInd;
2798                 sclk_table->entries[entryId].vddc =
2799                                 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2800         }
2801
2802         for (entryId = 0; entryId < mclk_table->count; ++entryId) {
2803                 voltageId = mclk_table->entries[entryId].vddInd;
2804                 mclk_table->entries[entryId].vddc =
2805                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2806         }
2807
2808         for (entryId = 0; entryId < mm_table->count; ++entryId) {
2809                 voltageId = mm_table->entries[entryId].vddcInd;
2810                 mm_table->entries[entryId].vddc =
2811                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2812         }
2813
2814         return 0;
2815
2816 }
2817
2818 static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
2819 {
2820         /* Need to determine if we need calculated voltage. */
2821         return 0;
2822 }
2823
2824 static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
2825 {
2826         /* Need to determine if we need calculated voltage from mm table. */
2827         return 0;
2828 }
2829
2830 static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
2831                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
2832 {
2833         uint32_t table_size, i, j;
2834         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
2835         table_size = lookup_table->count;
2836
2837         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2838                 "Lookup table is empty", return -EINVAL);
2839
2840         /* Sorting voltages */
2841         for (i = 0; i < table_size - 1; i++) {
2842                 for (j = i + 1; j > 0; j--) {
2843                         if (lookup_table->entries[j].us_vdd <
2844                                         lookup_table->entries[j - 1].us_vdd) {
2845                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
2846                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
2847                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
2848                         }
2849                 }
2850         }
2851
2852         return 0;
2853 }
2854
2855 static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
2856 {
2857         int result = 0;
2858         int tmp_result;
2859         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2860         struct phm_ppt_v1_information *table_info =
2861                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2862
2863         tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
2864                         table_info->vddc_lookup_table, &(data->vddc_leakage));
2865         if (tmp_result)
2866                 result = tmp_result;
2867
2868         tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
2869                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2870         if (tmp_result)
2871                 result = tmp_result;
2872
2873         tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
2874         if (tmp_result)
2875                 result = tmp_result;
2876
2877         tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
2878         if (tmp_result)
2879                 result = tmp_result;
2880
2881         tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
2882         if (tmp_result)
2883                 result = tmp_result;
2884
2885         tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
2886         if (tmp_result)
2887                 result = tmp_result;
2888
2889         return result;
2890 }
2891
2892 static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
2893 {
2894         struct phm_ppt_v1_information *table_info =
2895                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2896
2897         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2898                                                 table_info->vdd_dep_on_sclk;
2899         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2900                                                 table_info->vdd_dep_on_mclk;
2901
2902         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2903                 "VDD dependency on SCLK table is missing.       \
2904                 This table is mandatory", return -EINVAL);
2905         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2906                 "VDD dependency on SCLK table has to have is missing.   \
2907                 This table is mandatory", return -EINVAL);
2908
2909         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2910                 "VDD dependency on MCLK table is missing.       \
2911                 This table is mandatory", return -EINVAL);
2912         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2913                 "VDD dependency on MCLK table has to have is missing.    \
2914                 This table is mandatory", return -EINVAL);
2915
2916         table_info->max_clock_voltage_on_ac.sclk =
2917                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2918         table_info->max_clock_voltage_on_ac.mclk =
2919                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2920         table_info->max_clock_voltage_on_ac.vddc =
2921                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2922         table_info->max_clock_voltage_on_ac.vddci =
2923                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2924
2925         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2926         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2927         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2928         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
2929
2930         return 0;
2931 }
2932
2933 int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2934 {
2935         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2936         struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2937         uint32_t temp_reg;
2938         int result;
2939         struct phm_ppt_v1_information *table_info =
2940                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2941
2942         data->dll_default_on = false;
2943         data->sram_end = SMC_RAM_END;
2944         data->mclk_dpm0_activity_target = 0xa;
2945         data->disable_dpm_mask = 0xFF;
2946         data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2947         data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2948         data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2949         data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2950         data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2951         data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2952         data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2953         data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2954         data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2955         data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2956
2957         data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
2958         data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
2959         data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
2960         data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
2961         data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
2962         data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
2963         data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
2964         data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
2965
2966         data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
2967
2968         data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
2969
2970         /* need to set voltage control types before EVV patching */
2971         data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2972         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2973         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2974
2975         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2976                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
2977                 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2978
2979         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2980                         PHM_PlatformCaps_EnableMVDDControl)) {
2981                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2982                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
2983                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
2984                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2985                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
2986                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2987         }
2988
2989         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2990                         PHM_PlatformCaps_ControlVDDCI)) {
2991                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2992                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
2993                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
2994                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2995                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
2996                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2997         }
2998
2999         polaris10_set_features_platform_caps(hwmgr);
3000
3001         polaris10_init_dpm_defaults(hwmgr);
3002
3003         /* Get leakage voltage based on leakage ID. */
3004         result = polaris10_get_evv_voltages(hwmgr);
3005
3006         if (result) {
3007                 printk("Get EVV Voltage Failed.  Abort Driver loading!\n");
3008                 return -1;
3009         }
3010
3011         polaris10_complete_dependency_tables(hwmgr);
3012         polaris10_set_private_data_based_on_pptable(hwmgr);
3013
3014         /* Initalize Dynamic State Adjustment Rule Settings */
3015         result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
3016
3017         if (0 == result) {
3018                 struct cgs_system_info sys_info = {0};
3019
3020                 data->is_tlu_enabled = 0;
3021
3022                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
3023                                                         POLARIS10_MAX_HARDWARE_POWERLEVELS;
3024                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3025                 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
3026
3027
3028                 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
3029                         temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
3030                         switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
3031                         case 0:
3032                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3033                                 break;
3034                         case 1:
3035                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3036                                 break;
3037                         case 2:
3038                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3039                                 break;
3040                         case 3:
3041                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3042                                 break;
3043                         case 4:
3044                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3045                                 break;
3046                         default:
3047                                 PP_ASSERT_WITH_CODE(0,
3048                                 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3049                                 );
3050                                 break;
3051                         }
3052                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3053                 }
3054
3055                 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
3056                         hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
3057                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
3058                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3059
3060                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
3061                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3062
3063                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
3064
3065                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
3066
3067                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
3068                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3069
3070                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
3071
3072                         table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
3073                                                                         (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
3074
3075                         table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3076                         table_info->cac_dtp_table->usOperatingTempStep = 1;
3077                         table_info->cac_dtp_table->usOperatingTempHyst = 1;
3078
3079                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
3080                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3081
3082                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
3083                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
3084
3085                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
3086                                        table_info->cac_dtp_table->usOperatingTempMinLimit;
3087
3088                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
3089                                        table_info->cac_dtp_table->usOperatingTempMaxLimit;
3090
3091                         hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
3092                                        table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3093
3094                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
3095                                        table_info->cac_dtp_table->usOperatingTempStep;
3096
3097                         hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
3098                                        table_info->cac_dtp_table->usTargetOperatingTemp;
3099                 }
3100
3101                 sys_info.size = sizeof(struct cgs_system_info);
3102                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3103                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3104                 if (result)
3105                         data->pcie_gen_cap = 0x30007;
3106                 else
3107                         data->pcie_gen_cap = (uint32_t)sys_info.value;
3108                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3109                         data->pcie_spc_cap = 20;
3110                 sys_info.size = sizeof(struct cgs_system_info);
3111                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3112                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3113                 if (result)
3114                         data->pcie_lane_cap = 0x2f0000;
3115                 else
3116                         data->pcie_lane_cap = (uint32_t)sys_info.value;
3117
3118                 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3119 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3120                 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3121                 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
3122         } else {
3123                 /* Ignore return value in here, we are cleaning up a mess. */
3124                 polaris10_hwmgr_backend_fini(hwmgr);
3125         }
3126
3127         return 0;
3128 }
3129
3130 static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3131 {
3132         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3133         uint32_t level, tmp;
3134
3135         if (!data->pcie_dpm_key_disabled) {
3136                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3137                         level = 0;
3138                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3139                         while (tmp >>= 1)
3140                                 level++;
3141
3142                         if (level)
3143                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3144                                                 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3145                 }
3146         }
3147
3148         if (!data->sclk_dpm_key_disabled) {
3149                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3150                         level = 0;
3151                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3152                         while (tmp >>= 1)
3153                                 level++;
3154
3155                         if (level)
3156                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3157                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3158                                                 (1 << level));
3159                 }
3160         }
3161
3162         if (!data->mclk_dpm_key_disabled) {
3163                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3164                         level = 0;
3165                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3166                         while (tmp >>= 1)
3167                                 level++;
3168
3169                         if (level)
3170                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3171                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3172                                                 (1 << level));
3173                 }
3174         }
3175
3176         return 0;
3177 }
3178
3179 static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3180 {
3181         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3182
3183         phm_apply_dal_min_voltage_request(hwmgr);
3184
3185         if (!data->sclk_dpm_key_disabled) {
3186                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3187                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3188                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
3189                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3190         }
3191
3192         if (!data->mclk_dpm_key_disabled) {
3193                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3194                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3195                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
3196                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3197         }
3198
3199         return 0;
3200 }
3201
3202 static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3203 {
3204         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3205
3206         if (!polaris10_is_dpm_running(hwmgr))
3207                 return -EINVAL;
3208
3209         if (!data->pcie_dpm_key_disabled) {
3210                 smum_send_msg_to_smc(hwmgr->smumgr,
3211                                 PPSMC_MSG_PCIeDPM_UnForceLevel);
3212         }
3213
3214         return polaris10_upload_dpm_level_enable_mask(hwmgr);
3215 }
3216
3217 static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3218 {
3219         struct polaris10_hwmgr *data =
3220                         (struct polaris10_hwmgr *)(hwmgr->backend);
3221         uint32_t level;
3222
3223         if (!data->sclk_dpm_key_disabled)
3224                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3225                         level = phm_get_lowest_enabled_level(hwmgr,
3226                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3227                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3228                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
3229                                                             (1 << level));
3230
3231         }
3232
3233         if (!data->mclk_dpm_key_disabled) {
3234                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3235                         level = phm_get_lowest_enabled_level(hwmgr,
3236                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3237                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3238                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
3239                                                             (1 << level));
3240                 }
3241         }
3242
3243         if (!data->pcie_dpm_key_disabled) {
3244                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3245                         level = phm_get_lowest_enabled_level(hwmgr,
3246                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3247                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3248                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
3249                                                             (level));
3250                 }
3251         }
3252
3253         return 0;
3254
3255 }
3256 static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
3257                                 enum amd_dpm_forced_level level)
3258 {
3259         int ret = 0;
3260
3261         switch (level) {
3262         case AMD_DPM_FORCED_LEVEL_HIGH:
3263                 ret = polaris10_force_dpm_highest(hwmgr);
3264                 if (ret)
3265                         return ret;
3266                 break;
3267         case AMD_DPM_FORCED_LEVEL_LOW:
3268                 ret = polaris10_force_dpm_lowest(hwmgr);
3269                 if (ret)
3270                         return ret;
3271                 break;
3272         case AMD_DPM_FORCED_LEVEL_AUTO:
3273                 ret = polaris10_unforce_dpm_levels(hwmgr);
3274                 if (ret)
3275                         return ret;
3276                 break;
3277         default:
3278                 break;
3279         }
3280
3281         hwmgr->dpm_level = level;
3282
3283         return ret;
3284 }
3285
3286 static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
3287 {
3288         return sizeof(struct polaris10_power_state);
3289 }
3290
3291
3292 static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3293                                 struct pp_power_state *request_ps,
3294                         const struct pp_power_state *current_ps)
3295 {
3296
3297         struct polaris10_power_state *polaris10_ps =
3298                                 cast_phw_polaris10_power_state(&request_ps->hardware);
3299         uint32_t sclk;
3300         uint32_t mclk;
3301         struct PP_Clocks minimum_clocks = {0};
3302         bool disable_mclk_switching;
3303         bool disable_mclk_switching_for_frame_lock;
3304         struct cgs_display_info info = {0};
3305         const struct phm_clock_and_voltage_limits *max_limits;
3306         uint32_t i;
3307         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3308         struct phm_ppt_v1_information *table_info =
3309                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3310         int32_t count;
3311         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3312
3313         data->battery_state = (PP_StateUILabel_Battery ==
3314                         request_ps->classification.ui_label);
3315
3316         PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
3317                                  "VI should always have 2 performance levels",
3318                                 );
3319
3320         max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3321                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3322                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3323
3324         /* Cap clock DPM tables at DC MAX if it is in DC. */
3325         if (PP_PowerSource_DC == hwmgr->power_source) {
3326                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3327                         if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3328                                 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3329                         if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3330                                 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
3331                 }
3332         }
3333
3334         polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3335         polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3336
3337         cgs_get_active_displays_info(hwmgr->device, &info);
3338
3339         /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3340
3341         /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3342
3343         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3344                         PHM_PlatformCaps_StablePState)) {
3345                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3346                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3347
3348                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3349                                 count >= 0; count--) {
3350                         if (stable_pstate_sclk >=
3351                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3352                                 stable_pstate_sclk =
3353                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3354                                 break;
3355                         }
3356                 }
3357
3358                 if (count < 0)
3359                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3360
3361                 stable_pstate_mclk = max_limits->mclk;
3362
3363                 minimum_clocks.engineClock = stable_pstate_sclk;
3364                 minimum_clocks.memoryClock = stable_pstate_mclk;
3365         }
3366
3367         if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3368                 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3369
3370         if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3371                 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3372
3373         polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3374
3375         if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3376                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3377                                 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3378                                 "Overdrive sclk exceeds limit",
3379                                 hwmgr->gfx_arbiter.sclk_over_drive =
3380                                                 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3381
3382                 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3383                         polaris10_ps->performance_levels[1].engine_clock =
3384                                         hwmgr->gfx_arbiter.sclk_over_drive;
3385         }
3386
3387         if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3388                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3389                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3390                                 "Overdrive mclk exceeds limit",
3391                                 hwmgr->gfx_arbiter.mclk_over_drive =
3392                                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3393
3394                 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3395                         polaris10_ps->performance_levels[1].memory_clock =
3396                                         hwmgr->gfx_arbiter.mclk_over_drive;
3397         }
3398
3399         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3400                                     hwmgr->platform_descriptor.platformCaps,
3401                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3402
3403         disable_mclk_switching = (1 < info.display_count) ||
3404                                     disable_mclk_switching_for_frame_lock;
3405
3406         sclk = polaris10_ps->performance_levels[0].engine_clock;
3407         mclk = polaris10_ps->performance_levels[0].memory_clock;
3408
3409         if (disable_mclk_switching)
3410                 mclk = polaris10_ps->performance_levels
3411                 [polaris10_ps->performance_level_count - 1].memory_clock;
3412
3413         if (sclk < minimum_clocks.engineClock)
3414                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3415                                 max_limits->sclk : minimum_clocks.engineClock;
3416
3417         if (mclk < minimum_clocks.memoryClock)
3418                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3419                                 max_limits->mclk : minimum_clocks.memoryClock;
3420
3421         polaris10_ps->performance_levels[0].engine_clock = sclk;
3422         polaris10_ps->performance_levels[0].memory_clock = mclk;
3423
3424         polaris10_ps->performance_levels[1].engine_clock =
3425                 (polaris10_ps->performance_levels[1].engine_clock >=
3426                                 polaris10_ps->performance_levels[0].engine_clock) ?
3427                                                 polaris10_ps->performance_levels[1].engine_clock :
3428                                                 polaris10_ps->performance_levels[0].engine_clock;
3429
3430         if (disable_mclk_switching) {
3431                 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3432                         mclk = polaris10_ps->performance_levels[1].memory_clock;
3433
3434                 polaris10_ps->performance_levels[0].memory_clock = mclk;
3435                 polaris10_ps->performance_levels[1].memory_clock = mclk;
3436         } else {
3437                 if (polaris10_ps->performance_levels[1].memory_clock <
3438                                 polaris10_ps->performance_levels[0].memory_clock)
3439                         polaris10_ps->performance_levels[1].memory_clock =
3440                                         polaris10_ps->performance_levels[0].memory_clock;
3441         }
3442
3443         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3444                         PHM_PlatformCaps_StablePState)) {
3445                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3446                         polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3447                         polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3448                         polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3449                         polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3450                 }
3451         }
3452         return 0;
3453 }
3454
3455
3456 static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3457 {
3458         struct pp_power_state  *ps;
3459         struct polaris10_power_state  *polaris10_ps;
3460
3461         if (hwmgr == NULL)
3462                 return -EINVAL;
3463
3464         ps = hwmgr->request_ps;
3465
3466         if (ps == NULL)
3467                 return -EINVAL;
3468
3469         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3470
3471         if (low)
3472                 return polaris10_ps->performance_levels[0].memory_clock;
3473         else
3474                 return polaris10_ps->performance_levels
3475                                 [polaris10_ps->performance_level_count-1].memory_clock;
3476 }
3477
3478 static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3479 {
3480         struct pp_power_state  *ps;
3481         struct polaris10_power_state  *polaris10_ps;
3482
3483         if (hwmgr == NULL)
3484                 return -EINVAL;
3485
3486         ps = hwmgr->request_ps;
3487
3488         if (ps == NULL)
3489                 return -EINVAL;
3490
3491         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3492
3493         if (low)
3494                 return polaris10_ps->performance_levels[0].engine_clock;
3495         else
3496                 return polaris10_ps->performance_levels
3497                                 [polaris10_ps->performance_level_count-1].engine_clock;
3498 }
3499
3500 static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3501                                         struct pp_hw_power_state *hw_ps)
3502 {
3503         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3504         struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
3505         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3506         uint16_t size;
3507         uint8_t frev, crev;
3508         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3509
3510         /* First retrieve the Boot clocks and VDDC from the firmware info table.
3511          * We assume here that fw_info is unchanged if this call fails.
3512          */
3513         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3514                         hwmgr->device, index,
3515                         &size, &frev, &crev);
3516         if (!fw_info)
3517                 /* During a test, there is no firmware info table. */
3518                 return 0;
3519
3520         /* Patch the state. */
3521         data->vbios_boot_state.sclk_bootup_value =
3522                         le32_to_cpu(fw_info->ulDefaultEngineClock);
3523         data->vbios_boot_state.mclk_bootup_value =
3524                         le32_to_cpu(fw_info->ulDefaultMemoryClock);
3525         data->vbios_boot_state.mvdd_bootup_value =
3526                         le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3527         data->vbios_boot_state.vddc_bootup_value =
3528                         le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3529         data->vbios_boot_state.vddci_bootup_value =
3530                         le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3531         data->vbios_boot_state.pcie_gen_bootup_value =
3532                         phm_get_current_pcie_speed(hwmgr);
3533
3534         data->vbios_boot_state.pcie_lane_bootup_value =
3535                         (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3536
3537         /* set boot power state */
3538         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3539         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3540         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3541         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3542
3543         return 0;
3544 }
3545
3546 static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3547                 void *state, struct pp_power_state *power_state,
3548                 void *pp_table, uint32_t classification_flag)
3549 {
3550         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3551         struct polaris10_power_state  *polaris10_power_state =
3552                         (struct polaris10_power_state *)(&(power_state->hardware));
3553         struct polaris10_performance_level *performance_level;
3554         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3555         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3556                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3557         ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
3558                         (ATOM_Tonga_SCLK_Dependency_Table *)
3559                         (((unsigned long)powerplay_table) +
3560                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3561         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3562                         (ATOM_Tonga_MCLK_Dependency_Table *)
3563                         (((unsigned long)powerplay_table) +
3564                                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3565
3566         /* The following fields are not initialized here: id orderedList allStatesList */
3567         power_state->classification.ui_label =
3568                         (le16_to_cpu(state_entry->usClassification) &
3569                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3570                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3571         power_state->classification.flags = classification_flag;
3572         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3573
3574         power_state->classification.temporary_state = false;
3575         power_state->classification.to_be_deleted = false;
3576
3577         power_state->validation.disallowOnDC =
3578                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3579                                         ATOM_Tonga_DISALLOW_ON_DC));
3580
3581         power_state->pcie.lanes = 0;
3582
3583         power_state->display.disableFrameModulation = false;
3584         power_state->display.limitRefreshrate = false;
3585         power_state->display.enableVariBright =
3586                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3587                                         ATOM_Tonga_ENABLE_VARIBRIGHT));
3588
3589         power_state->validation.supportedPowerLevels = 0;
3590         power_state->uvd_clocks.VCLK = 0;
3591         power_state->uvd_clocks.DCLK = 0;
3592         power_state->temperatures.min = 0;
3593         power_state->temperatures.max = 0;
3594
3595         performance_level = &(polaris10_power_state->performance_levels
3596                         [polaris10_power_state->performance_level_count++]);
3597
3598         PP_ASSERT_WITH_CODE(
3599                         (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
3600                         "Performance levels exceeds SMC limit!",
3601                         return -1);
3602
3603         PP_ASSERT_WITH_CODE(
3604                         (polaris10_power_state->performance_level_count <=
3605                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3606                         "Performance levels exceeds Driver limit!",
3607                         return -1);
3608
3609         /* Performance levels are arranged from low to high. */
3610         performance_level->memory_clock = mclk_dep_table->entries
3611                         [state_entry->ucMemoryClockIndexLow].ulMclk;
3612         performance_level->engine_clock = sclk_dep_table->entries
3613                         [state_entry->ucEngineClockIndexLow].ulSclk;
3614         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3615                         state_entry->ucPCIEGenLow);
3616         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3617                         state_entry->ucPCIELaneHigh);
3618
3619         performance_level = &(polaris10_power_state->performance_levels
3620                         [polaris10_power_state->performance_level_count++]);
3621         performance_level->memory_clock = mclk_dep_table->entries
3622                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
3623         performance_level->engine_clock = sclk_dep_table->entries
3624                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3625         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3626                         state_entry->ucPCIEGenHigh);
3627         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3628                         state_entry->ucPCIELaneHigh);
3629
3630         return 0;
3631 }
3632
3633 static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3634                 unsigned long entry_index, struct pp_power_state *state)
3635 {
3636         int result;
3637         struct polaris10_power_state *ps;
3638         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3639         struct phm_ppt_v1_information *table_info =
3640                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3641         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3642                         table_info->vdd_dep_on_mclk;
3643
3644         state->hardware.magic = PHM_VIslands_Magic;
3645
3646         ps = (struct polaris10_power_state *)(&state->hardware);
3647
3648         result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3649                         polaris10_get_pp_table_entry_callback_func);
3650
3651         /* This is the earliest time we have all the dependency table and the VBIOS boot state
3652          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3653          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3654          */
3655         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3656                 if (dep_mclk_table->entries[0].clk !=
3657                                 data->vbios_boot_state.mclk_bootup_value)
3658                         printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3659                                         "does not match VBIOS boot MCLK level");
3660                 if (dep_mclk_table->entries[0].vddci !=
3661                                 data->vbios_boot_state.vddci_bootup_value)
3662                         printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3663                                         "does not match VBIOS boot VDDCI level");
3664         }
3665
3666         /* set DC compatible flag if this state supports DC */
3667         if (!state->validation.disallowOnDC)
3668                 ps->dc_compatible = true;
3669
3670         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3671                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3672
3673         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3674         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3675
3676         if (!result) {
3677                 uint32_t i;
3678
3679                 switch (state->classification.ui_label) {
3680                 case PP_StateUILabel_Performance:
3681                         data->use_pcie_performance_levels = true;
3682
3683                         for (i = 0; i < ps->performance_level_count; i++) {
3684                                 if (data->pcie_gen_performance.max <
3685                                                 ps->performance_levels[i].pcie_gen)
3686                                         data->pcie_gen_performance.max =
3687                                                         ps->performance_levels[i].pcie_gen;
3688
3689                                 if (data->pcie_gen_performance.min >
3690                                                 ps->performance_levels[i].pcie_gen)
3691                                         data->pcie_gen_performance.min =
3692                                                         ps->performance_levels[i].pcie_gen;
3693
3694                                 if (data->pcie_lane_performance.max <
3695                                                 ps->performance_levels[i].pcie_lane)
3696                                         data->pcie_lane_performance.max =
3697                                                         ps->performance_levels[i].pcie_lane;
3698
3699                                 if (data->pcie_lane_performance.min >
3700                                                 ps->performance_levels[i].pcie_lane)
3701                                         data->pcie_lane_performance.min =
3702                                                         ps->performance_levels[i].pcie_lane;
3703                         }
3704                         break;
3705                 case PP_StateUILabel_Battery:
3706                         data->use_pcie_power_saving_levels = true;
3707
3708                         for (i = 0; i < ps->performance_level_count; i++) {
3709                                 if (data->pcie_gen_power_saving.max <
3710                                                 ps->performance_levels[i].pcie_gen)
3711                                         data->pcie_gen_power_saving.max =
3712                                                         ps->performance_levels[i].pcie_gen;
3713
3714                                 if (data->pcie_gen_power_saving.min >
3715                                                 ps->performance_levels[i].pcie_gen)
3716                                         data->pcie_gen_power_saving.min =
3717                                                         ps->performance_levels[i].pcie_gen;
3718
3719                                 if (data->pcie_lane_power_saving.max <
3720                                                 ps->performance_levels[i].pcie_lane)
3721                                         data->pcie_lane_power_saving.max =
3722                                                         ps->performance_levels[i].pcie_lane;
3723
3724                                 if (data->pcie_lane_power_saving.min >
3725                                                 ps->performance_levels[i].pcie_lane)
3726                                         data->pcie_lane_power_saving.min =
3727                                                         ps->performance_levels[i].pcie_lane;
3728                         }
3729                         break;
3730                 default:
3731                         break;
3732                 }
3733         }
3734         return 0;
3735 }
3736
3737 static void
3738 polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
3739 {
3740         uint32_t sclk, mclk, activity_percent;
3741         uint32_t offset;
3742         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3743
3744         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3745
3746         sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3747
3748         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
3749
3750         mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3751         seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
3752                         mclk / 100, sclk / 100);
3753
3754         offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
3755         activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3756         activity_percent += 0x80;
3757         activity_percent >>= 8;
3758
3759         seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
3760
3761         seq_printf(m, "uvd    %sabled\n", data->uvd_power_gated ? "dis" : "en");
3762
3763         seq_printf(m, "vce    %sabled\n", data->vce_power_gated ? "dis" : "en");
3764 }
3765
3766 static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3767 {
3768         const struct phm_set_power_state_input *states =
3769                         (const struct phm_set_power_state_input *)input;
3770         const struct polaris10_power_state *polaris10_ps =
3771                         cast_const_phw_polaris10_power_state(states->pnew_state);
3772         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3773         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3774         uint32_t sclk = polaris10_ps->performance_levels
3775                         [polaris10_ps->performance_level_count - 1].engine_clock;
3776         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3777         uint32_t mclk = polaris10_ps->performance_levels
3778                         [polaris10_ps->performance_level_count - 1].memory_clock;
3779         struct PP_Clocks min_clocks = {0};
3780         uint32_t i;
3781         struct cgs_display_info info = {0};
3782
3783         data->need_update_smu7_dpm_table = 0;
3784
3785         for (i = 0; i < sclk_table->count; i++) {
3786                 if (sclk == sclk_table->dpm_levels[i].value)
3787                         break;
3788         }
3789
3790         if (i >= sclk_table->count)
3791                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3792         else {
3793         /* TODO: Check SCLK in DAL's minimum clocks
3794          * in case DeepSleep divider update is required.
3795          */
3796                 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3797                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
3798                                 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
3799                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3800         }
3801
3802         for (i = 0; i < mclk_table->count; i++) {
3803                 if (mclk == mclk_table->dpm_levels[i].value)
3804                         break;
3805         }
3806
3807         if (i >= mclk_table->count)
3808                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3809
3810         cgs_get_active_displays_info(hwmgr->device, &info);
3811
3812         if (data->display_timing.num_existing_displays != info.display_count)
3813                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3814
3815         return 0;
3816 }
3817
3818 static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
3819                 const struct polaris10_power_state *polaris10_ps)
3820 {
3821         uint32_t i;
3822         uint32_t sclk, max_sclk = 0;
3823         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3824         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3825
3826         for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3827                 sclk = polaris10_ps->performance_levels[i].engine_clock;
3828                 if (max_sclk < sclk)
3829                         max_sclk = sclk;
3830         }
3831
3832         for (i = 0; i < dpm_table->sclk_table.count; i++) {
3833                 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
3834                         return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
3835                                         dpm_table->pcie_speed_table.dpm_levels
3836                                         [dpm_table->pcie_speed_table.count - 1].value :
3837                                         dpm_table->pcie_speed_table.dpm_levels[i].value);
3838         }
3839
3840         return 0;
3841 }
3842
3843 static int polaris10_request_link_speed_change_before_state_change(
3844                 struct pp_hwmgr *hwmgr, const void *input)
3845 {
3846         const struct phm_set_power_state_input *states =
3847                         (const struct phm_set_power_state_input *)input;
3848         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3849         const struct polaris10_power_state *polaris10_nps =
3850                         cast_const_phw_polaris10_power_state(states->pnew_state);
3851         const struct polaris10_power_state *polaris10_cps =
3852                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
3853
3854         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
3855         uint16_t current_link_speed;
3856
3857         if (data->force_pcie_gen == PP_PCIEGenInvalid)
3858                 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
3859         else
3860                 current_link_speed = data->force_pcie_gen;
3861
3862         data->force_pcie_gen = PP_PCIEGenInvalid;
3863         data->pspp_notify_required = false;
3864
3865         if (target_link_speed > current_link_speed) {
3866                 switch (target_link_speed) {
3867                 case PP_PCIEGen3:
3868                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
3869                                 break;
3870                         data->force_pcie_gen = PP_PCIEGen2;
3871                         if (current_link_speed == PP_PCIEGen2)
3872                                 break;
3873                 case PP_PCIEGen2:
3874                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
3875                                 break;
3876                 default:
3877                         data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
3878                         break;
3879                 }
3880         } else {
3881                 if (target_link_speed < current_link_speed)
3882                         data->pspp_notify_required = true;
3883         }
3884
3885         return 0;
3886 }
3887
3888 static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3889 {
3890         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3891
3892         if (0 == data->need_update_smu7_dpm_table)
3893                 return 0;
3894
3895         if ((0 == data->sclk_dpm_key_disabled) &&
3896                 (data->need_update_smu7_dpm_table &
3897                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3898                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3899                                 "Trying to freeze SCLK DPM when DPM is disabled",
3900                                 );
3901                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3902                                 PPSMC_MSG_SCLKDPM_FreezeLevel),
3903                                 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3904                                 return -1);
3905         }
3906
3907         if ((0 == data->mclk_dpm_key_disabled) &&
3908                 (data->need_update_smu7_dpm_table &
3909                  DPMTABLE_OD_UPDATE_MCLK)) {
3910                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3911                                 "Trying to freeze MCLK DPM when DPM is disabled",
3912                                 );
3913                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3914                                 PPSMC_MSG_MCLKDPM_FreezeLevel),
3915                                 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3916                                 return -1);
3917         }
3918
3919         return 0;
3920 }
3921
3922 static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
3923                 struct pp_hwmgr *hwmgr, const void *input)
3924 {
3925         int result = 0;
3926         const struct phm_set_power_state_input *states =
3927                         (const struct phm_set_power_state_input *)input;
3928         const struct polaris10_power_state *polaris10_ps =
3929                         cast_const_phw_polaris10_power_state(states->pnew_state);
3930         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3931         uint32_t sclk = polaris10_ps->performance_levels
3932                         [polaris10_ps->performance_level_count - 1].engine_clock;
3933         uint32_t mclk = polaris10_ps->performance_levels
3934                         [polaris10_ps->performance_level_count - 1].memory_clock;
3935         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3936
3937         struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
3938         uint32_t dpm_count, clock_percent;
3939         uint32_t i;
3940
3941         if (0 == data->need_update_smu7_dpm_table)
3942                 return 0;
3943
3944         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3945                 dpm_table->sclk_table.dpm_levels
3946                 [dpm_table->sclk_table.count - 1].value = sclk;
3947
3948                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3949                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3950                 /* Need to do calculation based on the golden DPM table
3951                  * as the Heatmap GPU Clock axis is also based on the default values
3952                  */
3953                         PP_ASSERT_WITH_CODE(
3954                                 (golden_dpm_table->sclk_table.dpm_levels
3955                                                 [golden_dpm_table->sclk_table.count - 1].value != 0),
3956                                 "Divide by 0!",
3957                                 return -1);
3958                         dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
3959
3960                         for (i = dpm_count; i > 1; i--) {
3961                                 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
3962                                         clock_percent =
3963                                               ((sclk
3964                                                 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
3965                                                 ) * 100)
3966                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3967
3968                                         dpm_table->sclk_table.dpm_levels[i].value =
3969                                                         golden_dpm_table->sclk_table.dpm_levels[i].value +
3970                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
3971                                                                 clock_percent)/100;
3972
3973                                 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
3974                                         clock_percent =
3975                                                 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
3976                                                 - sclk) * 100)
3977                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3978
3979                                         dpm_table->sclk_table.dpm_levels[i].value =
3980                                                         golden_dpm_table->sclk_table.dpm_levels[i].value -
3981                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
3982                                                                         clock_percent) / 100;
3983                                 } else
3984                                         dpm_table->sclk_table.dpm_levels[i].value =
3985                                                         golden_dpm_table->sclk_table.dpm_levels[i].value;
3986                         }
3987                 }
3988         }
3989
3990         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3991                 dpm_table->mclk_table.dpm_levels
3992                         [dpm_table->mclk_table.count - 1].value = mclk;
3993
3994                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3995                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3996
3997                         PP_ASSERT_WITH_CODE(
3998                                         (golden_dpm_table->mclk_table.dpm_levels
3999                                                 [golden_dpm_table->mclk_table.count-1].value != 0),
4000                                         "Divide by 0!",
4001                                         return -1);
4002                         dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
4003                         for (i = dpm_count; i > 1; i--) {
4004                                 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
4005                                         clock_percent = ((mclk -
4006                                         golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
4007                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4008
4009                                         dpm_table->mclk_table.dpm_levels[i].value =
4010                                                         golden_dpm_table->mclk_table.dpm_levels[i].value +
4011                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4012                                                         clock_percent) / 100;
4013
4014                                 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
4015                                         clock_percent = (
4016                                          (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
4017                                         * 100)
4018                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4019
4020                                         dpm_table->mclk_table.dpm_levels[i].value =
4021                                                         golden_dpm_table->mclk_table.dpm_levels[i].value -
4022                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4023                                                                         clock_percent) / 100;
4024                                 } else
4025                                         dpm_table->mclk_table.dpm_levels[i].value =
4026                                                         golden_dpm_table->mclk_table.dpm_levels[i].value;
4027                         }
4028                 }
4029         }
4030
4031         if (data->need_update_smu7_dpm_table &
4032                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4033                 result = polaris10_populate_all_graphic_levels(hwmgr);
4034                 PP_ASSERT_WITH_CODE((0 == result),
4035                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4036                                 return result);
4037         }
4038
4039         if (data->need_update_smu7_dpm_table &
4040                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4041                 /*populate MCLK dpm table to SMU7 */
4042                 result = polaris10_populate_all_memory_levels(hwmgr);
4043                 PP_ASSERT_WITH_CODE((0 == result),
4044                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4045                                 return result);
4046         }
4047
4048         return result;
4049 }
4050
4051 static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4052                           struct polaris10_single_dpm_table *dpm_table,
4053                         uint32_t low_limit, uint32_t high_limit)
4054 {
4055         uint32_t i;
4056
4057         for (i = 0; i < dpm_table->count; i++) {
4058                 if ((dpm_table->dpm_levels[i].value < low_limit)
4059                 || (dpm_table->dpm_levels[i].value > high_limit))
4060                         dpm_table->dpm_levels[i].enabled = false;
4061                 else
4062                         dpm_table->dpm_levels[i].enabled = true;
4063         }
4064
4065         return 0;
4066 }
4067
4068 static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
4069                 const struct polaris10_power_state *polaris10_ps)
4070 {
4071         int result = 0;
4072         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4073         uint32_t high_limit_count;
4074
4075         PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
4076                         "power state did not have any performance level",
4077                         return -1);
4078
4079         high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
4080
4081         polaris10_trim_single_dpm_states(hwmgr,
4082                         &(data->dpm_table.sclk_table),
4083                         polaris10_ps->performance_levels[0].engine_clock,
4084                         polaris10_ps->performance_levels[high_limit_count].engine_clock);
4085
4086         polaris10_trim_single_dpm_states(hwmgr,
4087                         &(data->dpm_table.mclk_table),
4088                         polaris10_ps->performance_levels[0].memory_clock,
4089                         polaris10_ps->performance_levels[high_limit_count].memory_clock);
4090
4091         return result;
4092 }
4093
4094 static int polaris10_generate_dpm_level_enable_mask(
4095                 struct pp_hwmgr *hwmgr, const void *input)
4096 {
4097         int result;
4098         const struct phm_set_power_state_input *states =
4099                         (const struct phm_set_power_state_input *)input;
4100         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4101         const struct polaris10_power_state *polaris10_ps =
4102                         cast_const_phw_polaris10_power_state(states->pnew_state);
4103
4104         result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
4105         if (result)
4106                 return result;
4107
4108         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4109                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4110         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4111                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4112         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4113                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4114
4115         return 0;
4116 }
4117
4118 int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4119 {
4120         return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4121                         PPSMC_MSG_UVDDPM_Enable :
4122                         PPSMC_MSG_UVDDPM_Disable);
4123 }
4124
4125 int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4126 {
4127         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4128                         PPSMC_MSG_VCEDPM_Enable :
4129                         PPSMC_MSG_VCEDPM_Disable);
4130 }
4131
4132 int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4133 {
4134         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4135                         PPSMC_MSG_SAMUDPM_Enable :
4136                         PPSMC_MSG_SAMUDPM_Disable);
4137 }
4138
4139 int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4140 {
4141         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4142         uint32_t mm_boot_level_offset, mm_boot_level_value;
4143         struct phm_ppt_v1_information *table_info =
4144                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4145
4146         if (!bgate) {
4147                 data->smc_state_table.UvdBootLevel = 0;
4148                 if (table_info->mm_dep_table->count > 0)
4149                         data->smc_state_table.UvdBootLevel =
4150                                         (uint8_t) (table_info->mm_dep_table->count - 1);
4151                 mm_boot_level_offset = data->dpm_table_start +
4152                                 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4153                 mm_boot_level_offset /= 4;
4154                 mm_boot_level_offset *= 4;
4155                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4156                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4157                 mm_boot_level_value &= 0x00FFFFFF;
4158                 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4159                 cgs_write_ind_register(hwmgr->device,
4160                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4161
4162                 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4163                                 PHM_PlatformCaps_UVDDPM) ||
4164                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4165                                 PHM_PlatformCaps_StablePState))
4166                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4167                                         PPSMC_MSG_UVDDPM_SetEnabledMask,
4168                                         (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4169         }
4170
4171         return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
4172 }
4173
4174 static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4175 {
4176         const struct phm_set_power_state_input *states =
4177                         (const struct phm_set_power_state_input *)input;
4178         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4179         const struct polaris10_power_state *polaris10_nps =
4180                         cast_const_phw_polaris10_power_state(states->pnew_state);
4181         const struct polaris10_power_state *polaris10_cps =
4182                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
4183
4184         uint32_t mm_boot_level_offset, mm_boot_level_value;
4185         struct phm_ppt_v1_information *table_info =
4186                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4187
4188         if (polaris10_nps->vce_clks.evclk > 0 &&
4189         (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
4190
4191                 data->smc_state_table.VceBootLevel =
4192                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4193
4194                 mm_boot_level_offset = data->dpm_table_start +
4195                                 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4196                 mm_boot_level_offset /= 4;
4197                 mm_boot_level_offset *= 4;
4198                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4199                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4200                 mm_boot_level_value &= 0xFF00FFFF;
4201                 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4202                 cgs_write_ind_register(hwmgr->device,
4203                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4204
4205                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4206                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4207                                         PPSMC_MSG_VCEDPM_SetEnabledMask,
4208                                         (uint32_t)1 << data->smc_state_table.VceBootLevel);
4209
4210                         polaris10_enable_disable_vce_dpm(hwmgr, true);
4211                 } else if (polaris10_nps->vce_clks.evclk == 0 &&
4212                                 polaris10_cps != NULL &&
4213                                 polaris10_cps->vce_clks.evclk > 0)
4214                         polaris10_enable_disable_vce_dpm(hwmgr, false);
4215         }
4216
4217         return 0;
4218 }
4219
4220 int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4221 {
4222         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4223         uint32_t mm_boot_level_offset, mm_boot_level_value;
4224         struct phm_ppt_v1_information *table_info =
4225                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4226
4227         if (!bgate) {
4228                 data->smc_state_table.SamuBootLevel =
4229                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4230                 mm_boot_level_offset = data->dpm_table_start +
4231                                 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4232                 mm_boot_level_offset /= 4;
4233                 mm_boot_level_offset *= 4;
4234                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4235                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4236                 mm_boot_level_value &= 0xFFFFFF00;
4237                 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4238                 cgs_write_ind_register(hwmgr->device,
4239                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4240
4241                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4242                                 PHM_PlatformCaps_StablePState))
4243                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4244                                         PPSMC_MSG_SAMUDPM_SetEnabledMask,
4245                                         (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4246         }
4247
4248         return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
4249 }
4250
4251 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4252 {
4253         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4254
4255         int result = 0;
4256         uint32_t low_sclk_interrupt_threshold = 0;
4257
4258         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4259                         PHM_PlatformCaps_SclkThrottleLowNotification)
4260                 && (hwmgr->gfx_arbiter.sclk_threshold !=
4261                                 data->low_sclk_interrupt_threshold)) {
4262                 data->low_sclk_interrupt_threshold =
4263                                 hwmgr->gfx_arbiter.sclk_threshold;
4264                 low_sclk_interrupt_threshold =
4265                                 data->low_sclk_interrupt_threshold;
4266
4267                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4268
4269                 result = polaris10_copy_bytes_to_smc(
4270                                 hwmgr->smumgr,
4271                                 data->dpm_table_start +
4272                                 offsetof(SMU74_Discrete_DpmTable,
4273                                         LowSclkInterruptThreshold),
4274                                 (uint8_t *)&low_sclk_interrupt_threshold,
4275                                 sizeof(uint32_t),
4276                                 data->sram_end);
4277         }
4278
4279         return result;
4280 }
4281
4282 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4283 {
4284         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4285
4286         if (data->need_update_smu7_dpm_table &
4287                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4288                 return polaris10_program_memory_timing_parameters(hwmgr);
4289
4290         return 0;
4291 }
4292
4293 static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4294 {
4295         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4296
4297         if (0 == data->need_update_smu7_dpm_table)
4298                 return 0;
4299
4300         if ((0 == data->sclk_dpm_key_disabled) &&
4301                 (data->need_update_smu7_dpm_table &
4302                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4303
4304                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4305                                 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4306                                 );
4307                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4308                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4309                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4310                         return -1);
4311         }
4312
4313         if ((0 == data->mclk_dpm_key_disabled) &&
4314                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4315
4316                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4317                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4318                                 );
4319                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4320                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4321                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4322                     return -1);
4323         }
4324
4325         data->need_update_smu7_dpm_table = 0;
4326
4327         return 0;
4328 }
4329
4330 static int polaris10_notify_link_speed_change_after_state_change(
4331                 struct pp_hwmgr *hwmgr, const void *input)
4332 {
4333         const struct phm_set_power_state_input *states =
4334                         (const struct phm_set_power_state_input *)input;
4335         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4336         const struct polaris10_power_state *polaris10_ps =
4337                         cast_const_phw_polaris10_power_state(states->pnew_state);
4338         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
4339         uint8_t  request;
4340
4341         if (data->pspp_notify_required) {
4342                 if (target_link_speed == PP_PCIEGen3)
4343                         request = PCIE_PERF_REQ_GEN3;
4344                 else if (target_link_speed == PP_PCIEGen2)
4345                         request = PCIE_PERF_REQ_GEN2;
4346                 else
4347                         request = PCIE_PERF_REQ_GEN1;
4348
4349                 if (request == PCIE_PERF_REQ_GEN1 &&
4350                                 phm_get_current_pcie_speed(hwmgr) > 0)
4351                         return 0;
4352
4353                 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4354                         if (PP_PCIEGen2 == target_link_speed)
4355                                 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4356                         else
4357                                 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4358                 }
4359         }
4360
4361         return 0;
4362 }
4363
4364 static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4365 {
4366         int tmp_result, result = 0;
4367         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4368
4369         tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4370         PP_ASSERT_WITH_CODE((0 == tmp_result),
4371                         "Failed to find DPM states clocks in DPM table!",
4372                         result = tmp_result);
4373
4374         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4375                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4376                 tmp_result =
4377                         polaris10_request_link_speed_change_before_state_change(hwmgr, input);
4378                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4379                                 "Failed to request link speed change before state change!",
4380                                 result = tmp_result);
4381         }
4382
4383         tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
4384         PP_ASSERT_WITH_CODE((0 == tmp_result),
4385                         "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4386
4387         tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4388         PP_ASSERT_WITH_CODE((0 == tmp_result),
4389                         "Failed to populate and upload SCLK MCLK DPM levels!",
4390                         result = tmp_result);
4391
4392         tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
4393         PP_ASSERT_WITH_CODE((0 == tmp_result),
4394                         "Failed to generate DPM level enabled mask!",
4395                         result = tmp_result);
4396
4397         tmp_result = polaris10_update_vce_dpm(hwmgr, input);
4398         PP_ASSERT_WITH_CODE((0 == tmp_result),
4399                         "Failed to update VCE DPM!",
4400                         result = tmp_result);
4401
4402         tmp_result = polaris10_update_sclk_threshold(hwmgr);
4403         PP_ASSERT_WITH_CODE((0 == tmp_result),
4404                         "Failed to update SCLK threshold!",
4405                         result = tmp_result);
4406
4407         tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
4408         PP_ASSERT_WITH_CODE((0 == tmp_result),
4409                         "Failed to program memory timing parameters!",
4410                         result = tmp_result);
4411
4412         tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
4413         PP_ASSERT_WITH_CODE((0 == tmp_result),
4414                         "Failed to unfreeze SCLK MCLK DPM!",
4415                         result = tmp_result);
4416
4417         tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
4418         PP_ASSERT_WITH_CODE((0 == tmp_result),
4419                         "Failed to upload DPM level enabled mask!",
4420                         result = tmp_result);
4421
4422         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4423                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4424                 tmp_result =
4425                         polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
4426                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4427                                 "Failed to notify link speed change after state change!",
4428                                 result = tmp_result);
4429         }
4430         data->apply_optimized_settings = false;
4431         return result;
4432 }
4433
4434 static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4435 {
4436         hwmgr->thermal_controller.
4437         advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4438
4439         if (phm_is_hw_access_blocked(hwmgr))
4440                 return 0;
4441
4442         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4443                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4444 }
4445
4446 int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4447 {
4448         PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4449
4450         return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
4451 }
4452
4453 int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4454 {
4455         uint32_t num_active_displays = 0;
4456         struct cgs_display_info info = {0};
4457         info.mode_info = NULL;
4458
4459         cgs_get_active_displays_info(hwmgr->device, &info);
4460
4461         num_active_displays = info.display_count;
4462
4463         if (num_active_displays > 1)  /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
4464                 polaris10_notify_smc_display_change(hwmgr, false);
4465         else
4466                 polaris10_notify_smc_display_change(hwmgr, true);
4467
4468         return 0;
4469 }
4470
4471 /**
4472 * Programs the display gap
4473 *
4474 * @param    hwmgr  the address of the powerplay hardware manager.
4475 * @return   always OK
4476 */
4477 int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
4478 {
4479         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4480         uint32_t num_active_displays = 0;
4481         uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4482         uint32_t display_gap2;
4483         uint32_t pre_vbi_time_in_us;
4484         uint32_t frame_time_in_us;
4485         uint32_t ref_clock;
4486         uint32_t refresh_rate = 0;
4487         struct cgs_display_info info = {0};
4488         struct cgs_mode_info mode_info;
4489
4490         info.mode_info = &mode_info;
4491
4492         cgs_get_active_displays_info(hwmgr->device, &info);
4493         num_active_displays = info.display_count;
4494
4495         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4496         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4497
4498         ref_clock = mode_info.ref_clock;
4499         refresh_rate = mode_info.refresh_rate;
4500
4501         if (0 == refresh_rate)
4502                 refresh_rate = 60;
4503
4504         frame_time_in_us = 1000000 / refresh_rate;
4505
4506         pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4507         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4508
4509         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4510
4511         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4512
4513         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4514
4515         polaris10_notify_smc_display_change(hwmgr, num_active_displays != 0);
4516
4517         return 0;
4518 }
4519
4520
4521 int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4522 {
4523         return polaris10_program_display_gap(hwmgr);
4524 }
4525
4526 /**
4527 *  Set maximum target operating fan output RPM
4528 *
4529 * @param    hwmgr:  the address of the powerplay hardware manager.
4530 * @param    usMaxFanRpm:  max operating fan RPM value.
4531 * @return   The response that came from the SMC.
4532 */
4533 static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4534 {
4535         hwmgr->thermal_controller.
4536         advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4537
4538         if (phm_is_hw_access_blocked(hwmgr))
4539                 return 0;
4540
4541         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4542                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4543 }
4544
4545 int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
4546                                         const void *thermal_interrupt_info)
4547 {
4548         return 0;
4549 }
4550
4551 bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4552 {
4553         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4554         bool is_update_required = false;
4555         struct cgs_display_info info = {0, 0, NULL};
4556
4557         cgs_get_active_displays_info(hwmgr->device, &info);
4558
4559         if (data->display_timing.num_existing_displays != info.display_count)
4560                 is_update_required = true;
4561 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4562         if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4563                 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
4564                 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4565                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4566                                 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4567                         is_update_required = true;
4568 */
4569         return is_update_required;
4570 }
4571
4572 static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4573                                                            const struct polaris10_performance_level *pl2)
4574 {
4575         return ((pl1->memory_clock == pl2->memory_clock) &&
4576                   (pl1->engine_clock == pl2->engine_clock) &&
4577                   (pl1->pcie_gen == pl2->pcie_gen) &&
4578                   (pl1->pcie_lane == pl2->pcie_lane));
4579 }
4580
4581 int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
4582 {
4583         const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4584         const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
4585         int i;
4586
4587         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4588                 return -EINVAL;
4589
4590         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4591         if (psa->performance_level_count != psb->performance_level_count) {
4592                 *equal = false;
4593                 return 0;
4594         }
4595
4596         for (i = 0; i < psa->performance_level_count; i++) {
4597                 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4598                         /* If we have found even one performance level pair that is different the states are different. */
4599                         *equal = false;
4600                         return 0;
4601                 }
4602         }
4603
4604         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4605         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4606         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4607         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4608
4609         return 0;
4610 }
4611
4612 int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
4613 {
4614         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4615
4616         uint32_t vbios_version;
4617
4618         /*  Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4619
4620         phm_get_mc_microcode_version(hwmgr);
4621         vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4622         /*  Full version of MC ucode has already been loaded. */
4623         if (vbios_version == 0) {
4624                 data->need_long_memory_training = false;
4625                 return 0;
4626         }
4627
4628         data->need_long_memory_training = true;
4629
4630 /*
4631  *      PPMCME_FirmwareDescriptorEntry *pfd = NULL;
4632         pfd = &tonga_mcmeFirmware;
4633         if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
4634                 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
4635                                         pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4636                                         pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4637 */
4638         return 0;
4639 }
4640
4641 /**
4642  * Read clock related registers.
4643  *
4644  * @param    hwmgr  the address of the powerplay hardware manager.
4645  * @return   always 0
4646  */
4647 static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
4648 {
4649         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4650
4651         data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4652                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4653                                                 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4654
4655         data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4656                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4657                                                 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4658
4659         data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4660                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4661                                                 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4662
4663         return 0;
4664 }
4665
4666 /**
4667  * Find out if memory is GDDR5.
4668  *
4669  * @param    hwmgr  the address of the powerplay hardware manager.
4670  * @return   always 0
4671  */
4672 static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
4673 {
4674         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4675         uint32_t temp;
4676
4677         temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4678
4679         data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4680                         ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4681                          MC_SEQ_MISC0_GDDR5_SHIFT));
4682
4683         return 0;
4684 }
4685
4686 /**
4687  * Enables Dynamic Power Management by SMC
4688  *
4689  * @param    hwmgr  the address of the powerplay hardware manager.
4690  * @return   always 0
4691  */
4692 static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4693 {
4694         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4695                         GENERAL_PWRMGT, STATIC_PM_EN, 1);
4696
4697         return 0;
4698 }
4699
4700 /**
4701  * Initialize PowerGating States for different engines
4702  *
4703  * @param    hwmgr  the address of the powerplay hardware manager.
4704  * @return   always 0
4705  */
4706 static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
4707 {
4708         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4709
4710         data->uvd_power_gated = false;
4711         data->vce_power_gated = false;
4712         data->samu_power_gated = false;
4713
4714         return 0;
4715 }
4716
4717 static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4718 {
4719         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4720         data->low_sclk_interrupt_threshold = 0;
4721
4722         return 0;
4723 }
4724
4725 int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
4726 {
4727         int tmp_result, result = 0;
4728
4729         polaris10_upload_mc_firmware(hwmgr);
4730
4731         tmp_result = polaris10_read_clock_registers(hwmgr);
4732         PP_ASSERT_WITH_CODE((0 == tmp_result),
4733                         "Failed to read clock registers!", result = tmp_result);
4734
4735         tmp_result = polaris10_get_memory_type(hwmgr);
4736         PP_ASSERT_WITH_CODE((0 == tmp_result),
4737                         "Failed to get memory type!", result = tmp_result);
4738
4739         tmp_result = polaris10_enable_acpi_power_management(hwmgr);
4740         PP_ASSERT_WITH_CODE((0 == tmp_result),
4741                         "Failed to enable ACPI power management!", result = tmp_result);
4742
4743         tmp_result = polaris10_init_power_gate_state(hwmgr);
4744         PP_ASSERT_WITH_CODE((0 == tmp_result),
4745                         "Failed to init power gate state!", result = tmp_result);
4746
4747         tmp_result = phm_get_mc_microcode_version(hwmgr);
4748         PP_ASSERT_WITH_CODE((0 == tmp_result),
4749                         "Failed to get MC microcode version!", result = tmp_result);
4750
4751         tmp_result = polaris10_init_sclk_threshold(hwmgr);
4752         PP_ASSERT_WITH_CODE((0 == tmp_result),
4753                         "Failed to init sclk threshold!", result = tmp_result);
4754
4755         return result;
4756 }
4757
4758 static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
4759 {
4760         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4761
4762         if (!data->soft_pp_table) {
4763                 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
4764                 if (!data->soft_pp_table)
4765                         return -ENOMEM;
4766                 memcpy(data->soft_pp_table, hwmgr->soft_pp_table,
4767                                 hwmgr->soft_pp_table_size);
4768         }
4769
4770         *table = (char *)&data->soft_pp_table;
4771
4772         return hwmgr->soft_pp_table_size;
4773 }
4774
4775 static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
4776 {
4777         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4778
4779         if (!data->soft_pp_table) {
4780                 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
4781                 if (!data->soft_pp_table)
4782                         return -ENOMEM;
4783         }
4784
4785         memcpy(data->soft_pp_table, buf, size);
4786
4787         hwmgr->soft_pp_table = data->soft_pp_table;
4788
4789         /* TODO: re-init powerplay to implement modified pptable */
4790
4791         return 0;
4792 }
4793
4794 static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
4795                 enum pp_clock_type type, uint32_t mask)
4796 {
4797         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4798
4799         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
4800                 return -EINVAL;
4801
4802         switch (type) {
4803         case PP_SCLK:
4804                 if (!data->sclk_dpm_key_disabled)
4805                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4806                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
4807                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
4808                 break;
4809         case PP_MCLK:
4810                 if (!data->mclk_dpm_key_disabled)
4811                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4812                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
4813                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
4814                 break;
4815         case PP_PCIE:
4816         {
4817                 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4818                 uint32_t level = 0;
4819
4820                 while (tmp >>= 1)
4821                         level++;
4822
4823                 if (!data->pcie_dpm_key_disabled)
4824                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4825                                         PPSMC_MSG_PCIeDPM_ForceLevel,
4826                                         level);
4827                 break;
4828         }
4829         default:
4830                 break;
4831         }
4832
4833         return 0;
4834 }
4835
4836 static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
4837 {
4838         uint32_t speedCntl = 0;
4839
4840         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
4841         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
4842                         ixPCIE_LC_SPEED_CNTL);
4843         return((uint16_t)PHM_GET_FIELD(speedCntl,
4844                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4845 }
4846
4847 static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
4848                 enum pp_clock_type type, char *buf)
4849 {
4850         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4851         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4852         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4853         struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4854         int i, now, size = 0;
4855         uint32_t clock, pcie_speed;
4856
4857         switch (type) {
4858         case PP_SCLK:
4859                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4860                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4861
4862                 for (i = 0; i < sclk_table->count; i++) {
4863                         if (clock > sclk_table->dpm_levels[i].value)
4864                                 continue;
4865                         break;
4866                 }
4867                 now = i;
4868
4869                 for (i = 0; i < sclk_table->count; i++)
4870                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4871                                         i, sclk_table->dpm_levels[i].value / 100,
4872                                         (i == now) ? "*" : "");
4873                 break;
4874         case PP_MCLK:
4875                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4876                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4877
4878                 for (i = 0; i < mclk_table->count; i++) {
4879                         if (clock > mclk_table->dpm_levels[i].value)
4880                                 continue;
4881                         break;
4882                 }
4883                 now = i;
4884
4885                 for (i = 0; i < mclk_table->count; i++)
4886                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4887                                         i, mclk_table->dpm_levels[i].value / 100,
4888                                         (i == now) ? "*" : "");
4889                 break;
4890         case PP_PCIE:
4891                 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
4892                 for (i = 0; i < pcie_table->count; i++) {
4893                         if (pcie_speed != pcie_table->dpm_levels[i].value)
4894                                 continue;
4895                         break;
4896                 }
4897                 now = i;
4898
4899                 for (i = 0; i < pcie_table->count; i++)
4900                         size += sprintf(buf + size, "%d: %s %s\n", i,
4901                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
4902                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
4903                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
4904                                         (i == now) ? "*" : "");
4905                 break;
4906         default:
4907                 break;
4908         }
4909         return size;
4910 }
4911
4912 static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4913 {
4914         if (mode) {
4915                 /* stop auto-manage */
4916                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4917                                 PHM_PlatformCaps_MicrocodeFanControl))
4918                         polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
4919                 polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
4920         } else
4921                 /* restart auto-manage */
4922                 polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
4923
4924         return 0;
4925 }
4926
4927 static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4928 {
4929         if (hwmgr->fan_ctrl_is_in_default_mode)
4930                 return hwmgr->fan_ctrl_default_mode;
4931         else
4932                 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4933                                 CG_FDO_CTRL2, FDO_PWM_MODE);
4934 }
4935
4936 static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
4937         .backend_init = &polaris10_hwmgr_backend_init,
4938         .backend_fini = &polaris10_hwmgr_backend_fini,
4939         .asic_setup = &polaris10_setup_asic_task,
4940         .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
4941         .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
4942         .force_dpm_level = &polaris10_force_dpm_level,
4943         .power_state_set = polaris10_set_power_state_tasks,
4944         .get_power_state_size = polaris10_get_power_state_size,
4945         .get_mclk = polaris10_dpm_get_mclk,
4946         .get_sclk = polaris10_dpm_get_sclk,
4947         .patch_boot_state = polaris10_dpm_patch_boot_state,
4948         .get_pp_table_entry = polaris10_get_pp_table_entry,
4949         .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
4950         .print_current_perforce_level = polaris10_print_current_perforce_level,
4951         .powerdown_uvd = polaris10_phm_powerdown_uvd,
4952         .powergate_uvd = polaris10_phm_powergate_uvd,
4953         .powergate_vce = polaris10_phm_powergate_vce,
4954         .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
4955         .update_clock_gatings = polaris10_phm_update_clock_gatings,
4956         .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
4957         .display_config_changed = polaris10_display_configuration_changed_task,
4958         .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
4959         .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
4960         .get_temperature = polaris10_thermal_get_temperature,
4961         .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
4962         .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
4963         .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
4964         .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
4965         .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
4966         .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
4967         .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
4968         .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
4969         .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
4970         .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
4971         .check_states_equal = polaris10_check_states_equal,
4972         .set_fan_control_mode = polaris10_set_fan_control_mode,
4973         .get_fan_control_mode = polaris10_get_fan_control_mode,
4974         .get_pp_table = polaris10_get_pp_table,
4975         .set_pp_table = polaris10_set_pp_table,
4976         .force_clock_level = polaris10_force_clock_level,
4977         .print_clock_levels = polaris10_print_clock_levels,
4978         .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
4979 };
4980
4981 int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
4982 {
4983         struct polaris10_hwmgr  *data;
4984
4985         data = kzalloc (sizeof(struct polaris10_hwmgr), GFP_KERNEL);
4986         if (data == NULL)
4987                 return -ENOMEM;
4988
4989         hwmgr->backend = data;
4990         hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
4991         hwmgr->pptable_func = &tonga_pptable_funcs;
4992         pp_polaris10_thermal_initialize(hwmgr);
4993
4994         return 0;
4995 }