drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/fb.h>
  26 #include <asm/div64.h>
  27 #include "linux/delay.h"
  28 #include "pp_acpi.h"
  29 #include "hwmgr.h"
  30 #include "polaris10_hwmgr.h"
  31 #include "polaris10_powertune.h"
  32 #include "polaris10_dyn_defaults.h"
  33 #include "polaris10_smumgr.h"
  34 #include "pp_debug.h"
  35 #include "ppatomctrl.h"
  36 #include "atombios.h"
  37 #include "tonga_pptable.h"
  38 #include "pppcielanes.h"
  39 #include "amd_pcie_helpers.h"
  40 #include "hardwaremanager.h"
  41 #include "tonga_processpptables.h"
  42 #include "cgs_common.h"
  43 #include "smu74.h"
  44 #include "smu_ucode_xfer_vi.h"
  45 #include "smu74_discrete.h"
  46 #include "smu/smu_7_1_3_d.h"
  47 #include "smu/smu_7_1_3_sh_mask.h"
  48 #include "gmc/gmc_8_1_d.h"
  49 #include "gmc/gmc_8_1_sh_mask.h"
  50 #include "oss/oss_3_0_d.h"
  51 #include "gca/gfx_8_0_d.h"
  52 #include "bif/bif_5_0_d.h"
  53 #include "bif/bif_5_0_sh_mask.h"
  54 #include "gmc/gmc_8_1_d.h"
  55 #include "gmc/gmc_8_1_sh_mask.h"
  56 #include "bif/bif_5_0_d.h"
  57 #include "bif/bif_5_0_sh_mask.h"
  58 #include "dce/dce_10_0_d.h"
  59 #include "dce/dce_10_0_sh_mask.h"
  60
  61 #include "polaris10_thermal.h"
  62 #include "polaris10_clockpowergating.h"
  63
  64 #define MC_CG_ARB_FREQ_F0           0x0a
  65 #define MC_CG_ARB_FREQ_F1           0x0b
  66 #define MC_CG_ARB_FREQ_F2           0x0c
  67 #define MC_CG_ARB_FREQ_F3           0x0d
  68
  69 #define MC_CG_SEQ_DRAMCONF_S0       0x05
  70 #define MC_CG_SEQ_DRAMCONF_S1       0x06
  71 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
  72 #define MC_CG_SEQ_YCLK_RESUME       0x0a
  73
  74
  75 #define SMC_RAM_END 0x40000
  76
  77 #define SMC_CG_IND_START            0xc0030000
  78 #define SMC_CG_IND_END              0xc0040000
  79
  80 #define VOLTAGE_SCALE               4
  81 #define VOLTAGE_VID_OFFSET_SCALE1   625
  82 #define VOLTAGE_VID_OFFSET_SCALE2   100
  83
  84 #define VDDC_VDDCI_DELTA            200
  85
  86 #define MEM_FREQ_LOW_LATENCY        25000
  87 #define MEM_FREQ_HIGH_LATENCY       80000
  88
  89 #define MEM_LATENCY_HIGH            45
  90 #define MEM_LATENCY_LOW             35
  91 #define MEM_LATENCY_ERR             0xFFFF
  92
  93 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  94 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  95 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  96
  97
  98 #define PCIE_BUS_CLK                10000
  99 #define TCLK                        (PCIE_BUS_CLK / 10)
 100
 101
 102 static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
 103 { {600, 1050, 3, 0}, {600, 1050, 6, 1} };
 104
 105 /*  [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
 106 static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] =
 107 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
 108   { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
 109
 110 /*  [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
 111 static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] =
 112 { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
 113
 114 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 115 enum DPM_EVENT_SRC {
 116         DPM_EVENT_SRC_ANALOG = 0,
 117         DPM_EVENT_SRC_EXTERNAL = 1,
 118         DPM_EVENT_SRC_DIGITAL = 2,
 119         DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
 120         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
 121 };
 122
 123 static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
 124
 125 struct polaris10_power_state *cast_phw_polaris10_power_state(
 126                                   struct pp_hw_power_state *hw_ps)
 127 {
 128         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 129                                 "Invalid Powerstate Type!",
 130                                  return NULL);
 131
 132         return (struct polaris10_power_state *)hw_ps;
 133 }
 134
 135 const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
 136                                  const struct pp_hw_power_state *hw_ps)
 137 {
 138         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 139                                 "Invalid Powerstate Type!",
 140                                  return NULL);
 141
 142         return (const struct polaris10_power_state *)hw_ps;
 143 }
 144
 145 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
 146 {
 147         return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
 148                         CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
 149                         ? true : false;
 150 }
 151
 152 /**
 153  * Find the MC microcode version and store it in the HwMgr struct
 154  *
 155  * @param    hwmgr  the address of the powerplay hardware manager.
 156  * @return   always 0
 157  */
 158 int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
 159 {
 160         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 161
 162         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
 163
 164         return 0;
 165 }
 166
 167 uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 168 {
 169         uint32_t speedCntl = 0;
 170
 171         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 172         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
 173                         ixPCIE_LC_SPEED_CNTL);
 174         return((uint16_t)PHM_GET_FIELD(speedCntl,
 175                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 176 }
 177
 178 int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 179 {
 180         uint32_t link_width;
 181
 182         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 183         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 184                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
 185
 186         PP_ASSERT_WITH_CODE((7 >= link_width),
 187                         "Invalid PCIe lane width!", return 0);
 188
 189         return decode_pcie_lane_width(link_width);
 190 }
 191
 192 /**
 193 * Enable voltage control
 194 *
 195 * @param    pHwMgr  the address of the powerplay hardware manager.
 196 * @return   always PP_Result_OK
 197 */
 198 int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
 199 {
 200         PP_ASSERT_WITH_CODE(
 201                 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
 202                 "Failed to enable voltage DPM during DPM Start Function!",
 203                 return 1;
 204         );
 205
 206         return 0;
 207 }
 208
 209 /**
 210 * Checks if we want to support voltage control
 211 *
 212 * @param    hwmgr  the address of the powerplay hardware manager.
 213 */
 214 static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
 215 {
 216         const struct polaris10_hwmgr *data =
 217                         (const struct polaris10_hwmgr *)(hwmgr->backend);
 218
 219         return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
 220 }
 221
 222 /**
 223 * Enable voltage control
 224 *
 225 * @param    hwmgr  the address of the powerplay hardware manager.
 226 * @return   always 0
 227 */
 228 static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
 229 {
 230         /* enable voltage control */
 231         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 232                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 233
 234         return 0;
 235 }
 236
 237 /**
 238 * Create Voltage Tables.
 239 *
 240 * @param    hwmgr  the address of the powerplay hardware manager.
 241 * @return   always 0
 242 */
 243 static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
 244 {
 245         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 246         struct phm_ppt_v1_information *table_info =
 247                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 248         int result;
 249
 250         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 251                 result = atomctrl_get_voltage_table_v3(hwmgr,
 252                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
 253                                 &(data->mvdd_voltage_table));
 254                 PP_ASSERT_WITH_CODE((0 == result),
 255                                 "Failed to retrieve MVDD table.",
 256                                 return result);
 257         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
 258                 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
 259                                 table_info->vdd_dep_on_mclk);
 260                 PP_ASSERT_WITH_CODE((0 == result),
 261                                 "Failed to retrieve SVI2 MVDD table from dependancy table.",
 262                                 return result;);
 263         }
 264
 265         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 266                 result = atomctrl_get_voltage_table_v3(hwmgr,
 267                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
 268                                 &(data->vddci_voltage_table));
 269                 PP_ASSERT_WITH_CODE((0 == result),
 270                                 "Failed to retrieve VDDCI table.",
 271                                 return result);
 272         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
 273                 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
 274                                 table_info->vdd_dep_on_mclk);
 275                 PP_ASSERT_WITH_CODE((0 == result),
 276                                 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
 277                                 return result);
 278         }
 279
 280         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
 281                 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
 282                                 table_info->vddc_lookup_table);
 283                 PP_ASSERT_WITH_CODE((0 == result),
 284                                 "Failed to retrieve SVI2 VDDC table from lookup table.",
 285                                 return result);
 286         }
 287
 288         PP_ASSERT_WITH_CODE(
 289                         (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
 290                         "Too many voltage values for VDDC. Trimming to fit state table.",
 291                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
 292                                                                 &(data->vddc_voltage_table)));
 293
 294         PP_ASSERT_WITH_CODE(
 295                         (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
 296                         "Too many voltage values for VDDCI. Trimming to fit state table.",
 297                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
 298                                         &(data->vddci_voltage_table)));
 299
 300         PP_ASSERT_WITH_CODE(
 301                         (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
 302                         "Too many voltage values for MVDD. Trimming to fit state table.",
 303                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
 304                                                            &(data->mvdd_voltage_table)));
 305
 306         return 0;
 307 }
 308
 309 /**
 310 * Programs static screed detection parameters
 311 *
 312 * @param    hwmgr  the address of the powerplay hardware manager.
 313 * @return   always 0
 314 */
 315 static int polaris10_program_static_screen_threshold_parameters(
 316                                                         struct pp_hwmgr *hwmgr)
 317 {
 318         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 319
 320         /* Set static screen threshold unit */
 321         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 322                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
 323                         data->static_screen_threshold_unit);
 324         /* Set static screen threshold */
 325         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 326                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
 327                         data->static_screen_threshold);
 328
 329         return 0;
 330 }
 331
 332 /**
 333 * Setup display gap for glitch free memory clock switching.
 334 *
 335 * @param    hwmgr  the address of the powerplay hardware manager.
 336 * @return   always  0
 337 */
 338 static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
 339 {
 340         uint32_t display_gap =
 341                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 342                                         ixCG_DISPLAY_GAP_CNTL);
 343
 344         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 345                         DISP_GAP, DISPLAY_GAP_IGNORE);
 346
 347         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 348                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
 349
 350         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 351                         ixCG_DISPLAY_GAP_CNTL, display_gap);
 352
 353         return 0;
 354 }
 355
 356 /**
 357 * Programs activity state transition voting clients
 358 *
 359 * @param    hwmgr  the address of the powerplay hardware manager.
 360 * @return   always  0
 361 */
 362 static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
 363 {
 364         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 365
 366         /* Clear reset for voting clients before enabling DPM */
 367         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 368                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
 369         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 370                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
 371
 372         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 373                         ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
 374         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 375                         ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
 376         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 377                         ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
 378         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 379                         ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
 380         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 381                         ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
 382         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 383                         ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
 384         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 385                         ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
 386         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 387                         ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
 388
 389         return 0;
 390 }
 391
 392 static int polaris10_clear_voting_clients(struct pp_hwmgr *hwmgr)
 393 {
 394         /* Reset voting clients before disabling DPM */
 395         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 396                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
 397         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 398                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
 399
 400         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 401                         ixCG_FREQ_TRAN_VOTING_0, 0);
 402         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 403                         ixCG_FREQ_TRAN_VOTING_1, 0);
 404         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 405                         ixCG_FREQ_TRAN_VOTING_2, 0);
 406         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 407                         ixCG_FREQ_TRAN_VOTING_3, 0);
 408         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 409                         ixCG_FREQ_TRAN_VOTING_4, 0);
 410         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 411                         ixCG_FREQ_TRAN_VOTING_5, 0);
 412         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 413                         ixCG_FREQ_TRAN_VOTING_6, 0);
 414         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 415                         ixCG_FREQ_TRAN_VOTING_7, 0);
 416
 417         return 0;
 418 }
 419
 420 /**
 421 * Get the location of various tables inside the FW image.
 422 *
 423 * @param    hwmgr  the address of the powerplay hardware manager.
 424 * @return   always  0
 425 */
 426 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
 427 {
 428         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 429         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
 430         uint32_t tmp;
 431         int result;
 432         bool error = false;
 433
 434         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 435                         SMU7_FIRMWARE_HEADER_LOCATION +
 436                         offsetof(SMU74_Firmware_Header, DpmTable),
 437                         &tmp, data->sram_end);
 438
 439         if (0 == result)
 440                 data->dpm_table_start = tmp;
 441
 442         error |= (0 != result);
 443
 444         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 445                         SMU7_FIRMWARE_HEADER_LOCATION +
 446                         offsetof(SMU74_Firmware_Header, SoftRegisters),
 447                         &tmp, data->sram_end);
 448
 449         if (!result) {
 450                 data->soft_regs_start = tmp;
 451                 smu_data->soft_regs_start = tmp;
 452         }
 453
 454         error |= (0 != result);
 455
 456         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 457                         SMU7_FIRMWARE_HEADER_LOCATION +
 458                         offsetof(SMU74_Firmware_Header, mcRegisterTable),
 459                         &tmp, data->sram_end);
 460
 461         if (!result)
 462                 data->mc_reg_table_start = tmp;
 463
 464         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 465                         SMU7_FIRMWARE_HEADER_LOCATION +
 466                         offsetof(SMU74_Firmware_Header, FanTable),
 467                         &tmp, data->sram_end);
 468
 469         if (!result)
 470                 data->fan_table_start = tmp;
 471
 472         error |= (0 != result);
 473
 474         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 475                         SMU7_FIRMWARE_HEADER_LOCATION +
 476                         offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
 477                         &tmp, data->sram_end);
 478
 479         if (!result)
 480                 data->arb_table_start = tmp;
 481
 482         error |= (0 != result);
 483
 484         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 485                         SMU7_FIRMWARE_HEADER_LOCATION +
 486                         offsetof(SMU74_Firmware_Header, Version),
 487                         &tmp, data->sram_end);
 488
 489         if (!result)
 490                 hwmgr->microcode_version_info.SMC = tmp;
 491
 492         error |= (0 != result);
 493
 494         return error ? -1 : 0;
 495 }
 496
 497 /* Copy one arb setting to another and then switch the active set.
 498  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
 499  */
 500 static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
 501                 uint32_t arb_src, uint32_t arb_dest)
 502 {
 503         uint32_t mc_arb_dram_timing;
 504         uint32_t mc_arb_dram_timing2;
 505         uint32_t burst_time;
 506         uint32_t mc_cg_config;
 507
 508         switch (arb_src) {
 509         case MC_CG_ARB_FREQ_F0:
 510                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
 511                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
 512                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
 513                 break;
 514         case MC_CG_ARB_FREQ_F1:
 515                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
 516                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
 517                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
 518                 break;
 519         default:
 520                 return -EINVAL;
 521         }
 522
 523         switch (arb_dest) {
 524         case MC_CG_ARB_FREQ_F0:
 525                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 526                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 527                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
 528                 break;
 529         case MC_CG_ARB_FREQ_F1:
 530                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 531                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 532                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
 533                 break;
 534         default:
 535                 return -EINVAL;
 536         }
 537
 538         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
 539         mc_cg_config |= 0x0000000F;
 540         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
 541         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
 542
 543         return 0;
 544 }
 545
 546 static int polaris10_reset_to_default(struct pp_hwmgr *hwmgr)
 547 {
 548         return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults);
 549 }
 550
 551 /**
 552 * Initial switch from ARB F0->F1
 553 *
 554 * @param    hwmgr  the address of the powerplay hardware manager.
 555 * @return   always 0
 556 * This function is to be called from the SetPowerState table.
 557 */
 558 static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
 559 {
 560         return polaris10_copy_and_switch_arb_sets(hwmgr,
 561                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
 562 }
 563
 564 static int polaris10_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
 565 {
 566         uint32_t tmp;
 567
 568         tmp = (cgs_read_ind_register(hwmgr->device,
 569                         CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
 570                         0x0000ff00) >> 8;
 571
 572         if (tmp == MC_CG_ARB_FREQ_F0)
 573                 return 0;
 574
 575         return polaris10_copy_and_switch_arb_sets(hwmgr,
 576                         tmp, MC_CG_ARB_FREQ_F0);
 577 }
 578
 579 static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
 580 {
 581         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 582         struct phm_ppt_v1_information *table_info =
 583                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 584         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
 585         uint32_t i, max_entry;
 586
 587         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
 588                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
 589                         return -EINVAL);
 590
 591         if (data->use_pcie_performance_levels &&
 592                         !data->use_pcie_power_saving_levels) {
 593                 data->pcie_gen_power_saving = data->pcie_gen_performance;
 594                 data->pcie_lane_power_saving = data->pcie_lane_performance;
 595         } else if (!data->use_pcie_performance_levels &&
 596                         data->use_pcie_power_saving_levels) {
 597                 data->pcie_gen_performance = data->pcie_gen_power_saving;
 598                 data->pcie_lane_performance = data->pcie_lane_power_saving;
 599         }
 600
 601         phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
 602                                         SMU74_MAX_LEVELS_LINK,
 603                                         MAX_REGULAR_DPM_NUMBER);
 604
 605         if (pcie_table != NULL) {
 606                 /* max_entry is used to make sure we reserve one PCIE level
 607                  * for boot level (fix for A+A PSPP issue).
 608                  * If PCIE table from PPTable have ULV entry + 8 entries,
 609                  * then ignore the last entry.*/
 610                 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
 611                                 SMU74_MAX_LEVELS_LINK : pcie_table->count;
 612                 for (i = 1; i < max_entry; i++) {
 613                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
 614                                         get_pcie_gen_support(data->pcie_gen_cap,
 615                                                         pcie_table->entries[i].gen_speed),
 616                                         get_pcie_lane_support(data->pcie_lane_cap,
 617                                                         pcie_table->entries[i].lane_width));
 618                 }
 619                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
 620
 621                 /* Setup BIF_SCLK levels */
 622                 for (i = 0; i < max_entry; i++)
 623                         data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
 624         } else {
 625                 /* Hardcode Pcie Table */
 626                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
 627                                 get_pcie_gen_support(data->pcie_gen_cap,
 628                                                 PP_Min_PCIEGen),
 629                                 get_pcie_lane_support(data->pcie_lane_cap,
 630                                                 PP_Max_PCIELane));
 631                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
 632                                 get_pcie_gen_support(data->pcie_gen_cap,
 633                                                 PP_Min_PCIEGen),
 634                                 get_pcie_lane_support(data->pcie_lane_cap,
 635                                                 PP_Max_PCIELane));
 636                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
 637                                 get_pcie_gen_support(data->pcie_gen_cap,
 638                                                 PP_Max_PCIEGen),
 639                                 get_pcie_lane_support(data->pcie_lane_cap,
 640                                                 PP_Max_PCIELane));
 641                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
 642                                 get_pcie_gen_support(data->pcie_gen_cap,
 643                                                 PP_Max_PCIEGen),
 644                                 get_pcie_lane_support(data->pcie_lane_cap,
 645                                                 PP_Max_PCIELane));
 646                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
 647                                 get_pcie_gen_support(data->pcie_gen_cap,
 648                                                 PP_Max_PCIEGen),
 649                                 get_pcie_lane_support(data->pcie_lane_cap,
 650                                                 PP_Max_PCIELane));
 651                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
 652                                 get_pcie_gen_support(data->pcie_gen_cap,
 653                                                 PP_Max_PCIEGen),
 654                                 get_pcie_lane_support(data->pcie_lane_cap,
 655                                                 PP_Max_PCIELane));
 656
 657                 data->dpm_table.pcie_speed_table.count = 6;
 658         }
 659         /* Populate last level for boot PCIE level, but do not increment count. */
 660         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
 661                         data->dpm_table.pcie_speed_table.count,
 662                         get_pcie_gen_support(data->pcie_gen_cap,
 663                                         PP_Min_PCIEGen),
 664                         get_pcie_lane_support(data->pcie_lane_cap,
 665                                         PP_Max_PCIELane));
 666
 667         return 0;
 668 }
 669
 670 /*
 671  * This function is to initalize all DPM state tables
 672  * for SMU7 based on the dependency table.
 673  * Dynamic state patching function will then trim these
 674  * state tables to the allowed range based
 675  * on the power policy or external client requests,
 676  * such as UVD request, etc.
 677  */
 678 int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 679 {
 680         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 681         struct phm_ppt_v1_information *table_info =
 682                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 683         uint32_t i;
 684
 685         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
 686                         table_info->vdd_dep_on_sclk;
 687         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
 688                         table_info->vdd_dep_on_mclk;
 689
 690         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
 691                         "SCLK dependency table is missing. This table is mandatory",
 692                         return -EINVAL);
 693         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
 694                         "SCLK dependency table has to have is missing."
 695                         "This table is mandatory",
 696                         return -EINVAL);
 697
 698         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
 699                         "MCLK dependency table is missing. This table is mandatory",
 700                         return -EINVAL);
 701         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
 702                         "MCLK dependency table has to have is missing."
 703                         "This table is mandatory",
 704                         return -EINVAL);
 705
 706         /* clear the state table to reset everything to default */
 707         phm_reset_single_dpm_table(
 708                         &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
 709         phm_reset_single_dpm_table(
 710                         &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
 711
 712
 713         /* Initialize Sclk DPM table based on allow Sclk values */
 714         data->dpm_table.sclk_table.count = 0;
 715         for (i = 0; i < dep_sclk_table->count; i++) {
 716                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
 717                                                 dep_sclk_table->entries[i].clk) {
 718
 719                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 720                                         dep_sclk_table->entries[i].clk;
 721
 722                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
 723                                         (i == 0) ? true : false;
 724                         data->dpm_table.sclk_table.count++;
 725                 }
 726         }
 727
 728         /* Initialize Mclk DPM table based on allow Mclk values */
 729         data->dpm_table.mclk_table.count = 0;
 730         for (i = 0; i < dep_mclk_table->count; i++) {
 731                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
 732                                 [data->dpm_table.mclk_table.count - 1].value !=
 733                                                 dep_mclk_table->entries[i].clk) {
 734                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 735                                                         dep_mclk_table->entries[i].clk;
 736                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
 737                                                         (i == 0) ? true : false;
 738                         data->dpm_table.mclk_table.count++;
 739                 }
 740         }
 741
 742         /* setup PCIE gen speed levels */
 743         polaris10_setup_default_pcie_table(hwmgr);
 744
 745         /* save a copy of the default DPM table */
 746         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 747                         sizeof(struct polaris10_dpm_table));
 748
 749         return 0;
 750 }
 751
 752 uint8_t convert_to_vid(uint16_t vddc)
 753 {
 754         return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
 755 }
 756
 757 /**
 758  * Mvdd table preparation for SMC.
 759  *
 760  * @param    *hwmgr The address of the hardware manager.
 761  * @param    *table The SMC DPM table structure to be populated.
 762  * @return   0
 763  */
 764 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
 765                         SMU74_Discrete_DpmTable *table)
 766 {
 767         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 768         uint32_t count, level;
 769
 770         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 771                 count = data->mvdd_voltage_table.count;
 772                 if (count > SMU_MAX_SMIO_LEVELS)
 773                         count = SMU_MAX_SMIO_LEVELS;
 774                 for (level = 0; level < count; level++) {
 775                         table->SmioTable2.Pattern[level].Voltage =
 776                                 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
 777                         /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
 778                         table->SmioTable2.Pattern[level].Smio =
 779                                 (uint8_t) level;
 780                         table->Smio[level] |=
 781                                 data->mvdd_voltage_table.entries[level].smio_low;
 782                 }
 783                 table->SmioMask2 = data->mvdd_voltage_table.mask_low;
 784
 785                 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
 786         }
 787
 788         return 0;
 789 }
 790
 791 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
 792                                         struct SMU74_Discrete_DpmTable *table)
 793 {
 794         uint32_t count, level;
 795         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 796
 797         count = data->vddci_voltage_table.count;
 798
 799         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 800                 if (count > SMU_MAX_SMIO_LEVELS)
 801                         count = SMU_MAX_SMIO_LEVELS;
 802                 for (level = 0; level < count; ++level) {
 803                         table->SmioTable1.Pattern[level].Voltage =
 804                                 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
 805                         table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
 806
 807                         table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
 808                 }
 809         }
 810
 811         table->SmioMask1 = data->vddci_voltage_table.mask_low;
 812
 813         return 0;
 814 }
 815
 816 /**
 817 * Preparation of vddc and vddgfx CAC tables for SMC.
 818 *
 819 * @param    hwmgr  the address of the hardware manager
 820 * @param    table  the SMC DPM table structure to be populated
 821 * @return   always 0
 822 */
 823 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
 824                 struct SMU74_Discrete_DpmTable *table)
 825 {
 826         uint32_t count;
 827         uint8_t index;
 828         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 829         struct phm_ppt_v1_information *table_info =
 830                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 831         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
 832                         table_info->vddc_lookup_table;
 833         /* tables is already swapped, so in order to use the value from it,
 834          * we need to swap it back.
 835          * We are populating vddc CAC data to BapmVddc table
 836          * in split and merged mode
 837          */
 838         for (count = 0; count < lookup_table->count; count++) {
 839                 index = phm_get_voltage_index(lookup_table,
 840                                 data->vddc_voltage_table.entries[count].value);
 841                 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
 842                 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
 843                 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
 844         }
 845
 846         return 0;
 847 }
 848
 849 /**
 850 * Preparation of voltage tables for SMC.
 851 *
 852 * @param    hwmgr   the address of the hardware manager
 853 * @param    table   the SMC DPM table structure to be populated
 854 * @return   always  0
 855 */
 856
 857 int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
 858                 struct SMU74_Discrete_DpmTable *table)
 859 {
 860         polaris10_populate_smc_vddci_table(hwmgr, table);
 861         polaris10_populate_smc_mvdd_table(hwmgr, table);
 862         polaris10_populate_cac_table(hwmgr, table);
 863
 864         return 0;
 865 }
 866
 867 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
 868                 struct SMU74_Discrete_Ulv *state)
 869 {
 870         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 871         struct phm_ppt_v1_information *table_info =
 872                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 873
 874         state->CcPwrDynRm = 0;
 875         state->CcPwrDynRm1 = 0;
 876
 877         state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
 878         state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
 879                         VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
 880
 881         state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
 882
 883         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
 884         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
 885         CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
 886
 887         return 0;
 888 }
 889
 890 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
 891                 struct SMU74_Discrete_DpmTable *table)
 892 {
 893         return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
 894 }
 895
 896 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
 897                 struct SMU74_Discrete_DpmTable *table)
 898 {
 899         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 900         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
 901         int i;
 902
 903         /* Index (dpm_table->pcie_speed_table.count)
 904          * is reserved for PCIE boot level. */
 905         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
 906                 table->LinkLevel[i].PcieGenSpeed  =
 907                                 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
 908                 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
 909                                 dpm_table->pcie_speed_table.dpm_levels[i].param1);
 910                 table->LinkLevel[i].EnabledForActivity = 1;
 911                 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
 912                 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
 913                 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
 914         }
 915
 916         data->smc_state_table.LinkLevelCount =
 917                         (uint8_t)dpm_table->pcie_speed_table.count;
 918         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
 919                         phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
 920
 921         return 0;
 922 }
 923
 924 static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
 925 {
 926         uint32_t reference_clock, tmp;
 927         struct cgs_display_info info = {0};
 928         struct cgs_mode_info mode_info;
 929
 930         info.mode_info = &mode_info;
 931
 932         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
 933
 934         if (tmp)
 935                 return TCLK;
 936
 937         cgs_get_active_displays_info(hwmgr->device, &info);
 938         reference_clock = mode_info.ref_clock;
 939
 940         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
 941
 942         if (0 != tmp)
 943                 return reference_clock / 4;
 944
 945         return reference_clock;
 946 }
 947
 948 /**
 949 * Calculates the SCLK dividers using the provided engine clock
 950 *
 951 * @param    hwmgr  the address of the hardware manager
 952 * @param    clock  the engine clock to use to populate the structure
 953 * @param    sclk   the SMC SCLK structure to be populated
 954 */
 955 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
 956                 uint32_t clock, SMU_SclkSetting *sclk_setting)
 957 {
 958         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 959         const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
 960         struct pp_atomctrl_clock_dividers_ai dividers;
 961
 962         uint32_t ref_clock;
 963         uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
 964         uint8_t i;
 965         int result;
 966         uint64_t temp;
 967
 968         sclk_setting->SclkFrequency = clock;
 969         /* get the engine clock dividers for this clock value */
 970         result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
 971         if (result == 0) {
 972                 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
 973                 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
 974                 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
 975                 sclk_setting->PllRange = dividers.ucSclkPllRange;
 976                 sclk_setting->Sclk_slew_rate = 0x400;
 977                 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
 978                 sclk_setting->Pcc_down_slew_rate = 0xffff;
 979                 sclk_setting->SSc_En = dividers.ucSscEnable;
 980                 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
 981                 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
 982                 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
 983                 return result;
 984         }
 985
 986         ref_clock = polaris10_get_xclk(hwmgr);
 987
 988         for (i = 0; i < NUM_SCLK_RANGE; i++) {
 989                 if (clock > data->range_table[i].trans_lower_frequency
 990                 && clock <= data->range_table[i].trans_upper_frequency) {
 991                         sclk_setting->PllRange = i;
 992                         break;
 993                 }
 994         }
 995
 996         sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 997         temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 998         temp <<= 0x10;
 999         do_div(temp, ref_clock);
1000         sclk_setting->Fcw_frac = temp & 0xffff;
1001
1002         pcc_target_percent = 10; /*  Hardcode 10% for now. */
1003         pcc_target_freq = clock - (clock * pcc_target_percent / 100);
1004         sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
1005
1006         ss_target_percent = 2; /*  Hardcode 2% for now. */
1007         sclk_setting->SSc_En = 0;
1008         if (ss_target_percent) {
1009                 sclk_setting->SSc_En = 1;
1010                 ss_target_freq = clock - (clock * ss_target_percent / 100);
1011                 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
1012                 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
1013                 temp <<= 0x10;
1014                 do_div(temp, ref_clock);
1015                 sclk_setting->Fcw1_frac = temp & 0xffff;
1016         }
1017
1018         return 0;
1019 }
1020
1021 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
1022                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1023                 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1024 {
1025         uint32_t i;
1026         uint16_t vddci;
1027         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1028
1029         *voltage = *mvdd = 0;
1030
1031         /* clock - voltage dependency table is empty table */
1032         if (dep_table->count == 0)
1033                 return -EINVAL;
1034
1035         for (i = 0; i < dep_table->count; i++) {
1036                 /* find first sclk bigger than request */
1037                 if (dep_table->entries[i].clk >= clock) {
1038                         *voltage |= (dep_table->entries[i].vddc *
1039                                         VOLTAGE_SCALE) << VDDC_SHIFT;
1040                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1041                                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1042                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1043                         else if (dep_table->entries[i].vddci)
1044                                 *voltage |= (dep_table->entries[i].vddci *
1045                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1046                         else {
1047                                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1048                                                 (dep_table->entries[i].vddc -
1049                                                                 (uint16_t)data->vddc_vddci_delta));
1050                                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1051                         }
1052
1053                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1054                                 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1055                                         VOLTAGE_SCALE;
1056                         else if (dep_table->entries[i].mvdd)
1057                                 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1058                                         VOLTAGE_SCALE;
1059
1060                         *voltage |= 1 << PHASES_SHIFT;
1061                         return 0;
1062                 }
1063         }
1064
1065         /* sclk is bigger than max sclk in the dependence table */
1066         *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1067
1068         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1069                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1070                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1071         else if (dep_table->entries[i-1].vddci) {
1072                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1073                                 (dep_table->entries[i].vddc -
1074                                                 (uint16_t)data->vddc_vddci_delta));
1075                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1076         }
1077
1078         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1079                 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1080         else if (dep_table->entries[i].mvdd)
1081                 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1082
1083         return 0;
1084 }
1085
1086 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] =
1087 { {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
1088   {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1089   {VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
1090   {VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
1091   {VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
1092   {VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
1093   {VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
1094   {VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
1095
1096 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
1097 {
1098         uint32_t i, ref_clk;
1099         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1100         SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
1101         struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1102
1103         ref_clk = polaris10_get_xclk(hwmgr);
1104
1105         if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1106                 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1107                         table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1108                         table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1109                         table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1110
1111                         table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1112                         table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1113
1114                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1115                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1116                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1117                 }
1118                 return;
1119         }
1120
1121         for (i = 0; i < NUM_SCLK_RANGE; i++) {
1122
1123                 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1124                 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1125
1126                 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1127                 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1128                 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1129
1130                 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1131                 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1132
1133                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1134                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1135                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1136         }
1137 }
1138
1139 /**
1140 * Populates single SMC SCLK structure using the provided engine clock
1141 *
1142 * @param    hwmgr      the address of the hardware manager
1143 * @param    clock the engine clock to use to populate the structure
1144 * @param    sclk        the SMC SCLK structure to be populated
1145 */
1146
1147 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1148                 uint32_t clock, uint16_t sclk_al_threshold,
1149                 struct SMU74_Discrete_GraphicsLevel *level)
1150 {
1151         int result, i, temp;
1152         /* PP_Clocks minClocks; */
1153         uint32_t mvdd;
1154         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1155         struct phm_ppt_v1_information *table_info =
1156                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1157         SMU_SclkSetting curr_sclk_setting = { 0 };
1158
1159         result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
1160
1161         /* populate graphics levels */
1162         result = polaris10_get_dependency_volt_by_clk(hwmgr,
1163                         table_info->vdd_dep_on_sclk, clock,
1164                         &level->MinVoltage, &mvdd);
1165
1166         PP_ASSERT_WITH_CODE((0 == result),
1167                         "can not find VDDC voltage value for "
1168                         "VDDC engine clock dependency table",
1169                         return result);
1170         level->ActivityLevel = sclk_al_threshold;
1171
1172         level->CcPwrDynRm = 0;
1173         level->CcPwrDynRm1 = 0;
1174         level->EnabledForActivity = 0;
1175         level->EnabledForThrottle = 1;
1176         level->UpHyst = 10;
1177         level->DownHyst = 0;
1178         level->VoltageDownHyst = 0;
1179         level->PowerThrottle = 0;
1180
1181         /*
1182         * TODO: get minimum clocks from dal configaration
1183         * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1184         */
1185         /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1186
1187         /* get level->DeepSleepDivId
1188         if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1189                 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1190         */
1191         PP_ASSERT_WITH_CODE((clock >= POLARIS10_MINIMUM_ENGINE_CLOCK), "Engine clock can't satisfy stutter requirement!", return 0);
1192         for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
1193                 temp = clock >> i;
1194
1195                 if (temp >= POLARIS10_MINIMUM_ENGINE_CLOCK || i == 0)
1196                         break;
1197         }
1198
1199         level->DeepSleepDivId = i;
1200
1201         /* Default to slow, highest DPM level will be
1202          * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1203          */
1204         if (data->update_up_hyst)
1205                 level->UpHyst = (uint8_t)data->up_hyst;
1206         if (data->update_down_hyst)
1207                 level->DownHyst = (uint8_t)data->down_hyst;
1208
1209         level->SclkSetting = curr_sclk_setting;
1210
1211         CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1212         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1213         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1214         CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1215         CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1216         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1217         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1218         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1219         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1220         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1221         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1222         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1223         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1224         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1225         return 0;
1226 }
1227
1228 /**
1229 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1230 *
1231 * @param    hwmgr      the address of the hardware manager
1232 */
1233 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1234 {
1235         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1236         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1237         struct phm_ppt_v1_information *table_info =
1238                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1239         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1240         uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1241         int result = 0;
1242         uint32_t array = data->dpm_table_start +
1243                         offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1244         uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1245                         SMU74_MAX_LEVELS_GRAPHICS;
1246         struct SMU74_Discrete_GraphicsLevel *levels =
1247                         data->smc_state_table.GraphicsLevel;
1248         uint32_t i, max_entry;
1249         uint8_t hightest_pcie_level_enabled = 0,
1250                 lowest_pcie_level_enabled = 0,
1251                 mid_pcie_level_enabled = 0,
1252                 count = 0;
1253
1254         polaris10_get_sclk_range_table(hwmgr);
1255
1256         for (i = 0; i < dpm_table->sclk_table.count; i++) {
1257
1258                 result = polaris10_populate_single_graphic_level(hwmgr,
1259                                 dpm_table->sclk_table.dpm_levels[i].value,
1260                                 (uint16_t)data->activity_target[i],
1261                                 &(data->smc_state_table.GraphicsLevel[i]));
1262                 if (result)
1263                         return result;
1264
1265                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1266                 if (i > 1)
1267                         levels[i].DeepSleepDivId = 0;
1268         }
1269         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1270                                         PHM_PlatformCaps_SPLLShutdownSupport))
1271                 data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1272
1273         data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1274         data->smc_state_table.GraphicsDpmLevelCount =
1275                         (uint8_t)dpm_table->sclk_table.count;
1276         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1277                         phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1278
1279
1280         if (pcie_table != NULL) {
1281                 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1282                                 "There must be 1 or more PCIE levels defined in PPTable.",
1283                                 return -EINVAL);
1284                 max_entry = pcie_entry_cnt - 1;
1285                 for (i = 0; i < dpm_table->sclk_table.count; i++)
1286                         levels[i].pcieDpmLevel =
1287                                         (uint8_t) ((i < max_entry) ? i : max_entry);
1288         } else {
1289                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1290                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1291                                                 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1292                         hightest_pcie_level_enabled++;
1293
1294                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1295                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1296                                                 (1 << lowest_pcie_level_enabled)) == 0))
1297                         lowest_pcie_level_enabled++;
1298
1299                 while ((count < hightest_pcie_level_enabled) &&
1300                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1301                                                 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1302                         count++;
1303
1304                 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1305                                 hightest_pcie_level_enabled ?
1306                                                 (lowest_pcie_level_enabled + 1 + count) :
1307                                                 hightest_pcie_level_enabled;
1308
1309                 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1310                 for (i = 2; i < dpm_table->sclk_table.count; i++)
1311                         levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1312
1313                 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1314                 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1315
1316                 /* set pcieDpmLevel to mid_pcie_level_enabled */
1317                 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1318         }
1319         /* level count will send to smc once at init smc table and never change */
1320         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1321                         (uint32_t)array_size, data->sram_end);
1322
1323         return result;
1324 }
1325
1326 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1327                 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1328 {
1329         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1330         struct phm_ppt_v1_information *table_info =
1331                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1332         int result = 0;
1333         struct cgs_display_info info = {0, 0, NULL};
1334
1335         cgs_get_active_displays_info(hwmgr->device, &info);
1336
1337         if (table_info->vdd_dep_on_mclk) {
1338                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1339                                 table_info->vdd_dep_on_mclk, clock,
1340                                 &mem_level->MinVoltage, &mem_level->MinMvdd);
1341                 PP_ASSERT_WITH_CODE((0 == result),
1342                                 "can not find MinVddc voltage value from memory "
1343                                 "VDDC voltage dependency table", return result);
1344         }
1345
1346         mem_level->MclkFrequency = clock;
1347         mem_level->EnabledForThrottle = 1;
1348         mem_level->EnabledForActivity = 0;
1349         mem_level->UpHyst = 0;
1350         mem_level->DownHyst = 100;
1351         mem_level->VoltageDownHyst = 0;
1352         mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1353         mem_level->StutterEnable = false;
1354         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1355
1356         data->display_timing.num_existing_displays = info.display_count;
1357
1358         if ((data->mclk_stutter_mode_threshold) &&
1359                 (clock <= data->mclk_stutter_mode_threshold) &&
1360                 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1361                                 STUTTER_ENABLE) & 0x1))
1362                 mem_level->StutterEnable = true;
1363
1364         if (!result) {
1365                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1366                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1367                 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1368                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1369         }
1370         return result;
1371 }
1372
1373 /**
1374 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1375 *
1376 * @param    hwmgr      the address of the hardware manager
1377 */
1378 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1379 {
1380         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1381         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1382         int result;
1383         /* populate MCLK dpm table to SMU7 */
1384         uint32_t array = data->dpm_table_start +
1385                         offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1386         uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1387                         SMU74_MAX_LEVELS_MEMORY;
1388         struct SMU74_Discrete_MemoryLevel *levels =
1389                         data->smc_state_table.MemoryLevel;
1390         uint32_t i;
1391
1392         for (i = 0; i < dpm_table->mclk_table.count; i++) {
1393                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1394                                 "can not populate memory level as memory clock is zero",
1395                                 return -EINVAL);
1396                 result = polaris10_populate_single_memory_level(hwmgr,
1397                                 dpm_table->mclk_table.dpm_levels[i].value,
1398                                 &levels[i]);
1399                 if (i == dpm_table->mclk_table.count - 1) {
1400                         levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1401                         levels[i].EnabledForActivity = 1;
1402                 }
1403                 if (result)
1404                         return result;
1405         }
1406
1407         /* In order to prevent MC activity from stutter mode to push DPM up,
1408          * the UVD change complements this by putting the MCLK in
1409          * a higher state by default such that we are not affected by
1410          * up threshold or and MCLK DPM latency.
1411          */
1412         levels[0].ActivityLevel = 0x1f;
1413         CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1414
1415         data->smc_state_table.MemoryDpmLevelCount =
1416                         (uint8_t)dpm_table->mclk_table.count;
1417         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1418                         phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1419
1420         /* level count will send to smc once at init smc table and never change */
1421         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1422                         (uint32_t)array_size, data->sram_end);
1423
1424         return result;
1425 }
1426
1427 /**
1428 * Populates the SMC MVDD structure using the provided memory clock.
1429 *
1430 * @param    hwmgr      the address of the hardware manager
1431 * @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
1432 * @param    voltage     the SMC VOLTAGE structure to be populated
1433 */
1434 int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1435                 uint32_t mclk, SMIO_Pattern *smio_pat)
1436 {
1437         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1438         struct phm_ppt_v1_information *table_info =
1439                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1440         uint32_t i = 0;
1441
1442         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1443                 /* find mvdd value which clock is more than request */
1444                 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1445                         if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1446                                 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1447                                 break;
1448                         }
1449                 }
1450                 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1451                                 "MVDD Voltage is outside the supported range.",
1452                                 return -EINVAL);
1453         } else
1454                 return -EINVAL;
1455
1456         return 0;
1457 }
1458
1459 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1460                 SMU74_Discrete_DpmTable *table)
1461 {
1462         int result = 0;
1463         uint32_t sclk_frequency;
1464         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1465         struct phm_ppt_v1_information *table_info =
1466                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1467         SMIO_Pattern vol_level;
1468         uint32_t mvdd;
1469         uint16_t us_mvdd;
1470
1471         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1472
1473
1474         /* Get MinVoltage and Frequency from DPM0,
1475          * already converted to SMC_UL */
1476         sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
1477         result = polaris10_get_dependency_volt_by_clk(hwmgr,
1478                         table_info->vdd_dep_on_sclk,
1479                         sclk_frequency,
1480                         &table->ACPILevel.MinVoltage, &mvdd);
1481         PP_ASSERT_WITH_CODE((0 == result),
1482                         "Cannot find ACPI VDDC voltage value "
1483                         "in Clock Dependency Table",
1484                         );
1485
1486
1487         result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency,  &(table->ACPILevel.SclkSetting));
1488         PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1489
1490         table->ACPILevel.DeepSleepDivId = 0;
1491         table->ACPILevel.CcPwrDynRm = 0;
1492         table->ACPILevel.CcPwrDynRm1 = 0;
1493
1494         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1495         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1496         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1497         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1498
1499         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1500         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1501         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1502         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1503         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1504         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1505         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1506         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1507         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1508         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1509
1510
1511         /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1512         table->MemoryACPILevel.MclkFrequency =
1513                         data->dpm_table.mclk_table.dpm_levels[0].value;
1514         result = polaris10_get_dependency_volt_by_clk(hwmgr,
1515                         table_info->vdd_dep_on_mclk,
1516                         table->MemoryACPILevel.MclkFrequency,
1517                         &table->MemoryACPILevel.MinVoltage, &mvdd);
1518         PP_ASSERT_WITH_CODE((0 == result),
1519                         "Cannot find ACPI VDDCI voltage value "
1520                         "in Clock Dependency Table",
1521                         );
1522
1523         us_mvdd = 0;
1524         if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1525                         (data->mclk_dpm_key_disabled))
1526                 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1527         else {
1528                 if (!polaris10_populate_mvdd_value(hwmgr,
1529                                 data->dpm_table.mclk_table.dpm_levels[0].value,
1530                                 &vol_level))
1531                         us_mvdd = vol_level.Voltage;
1532         }
1533
1534         if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1535                 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1536         else
1537                 table->MemoryACPILevel.MinMvdd = 0;
1538
1539         table->MemoryACPILevel.StutterEnable = false;
1540
1541         table->MemoryACPILevel.EnabledForThrottle = 0;
1542         table->MemoryACPILevel.EnabledForActivity = 0;
1543         table->MemoryACPILevel.UpHyst = 0;
1544         table->MemoryACPILevel.DownHyst = 100;
1545         table->MemoryACPILevel.VoltageDownHyst = 0;
1546         table->MemoryACPILevel.ActivityLevel =
1547                         PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1548
1549         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1550         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1551
1552         return result;
1553 }
1554
1555 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1556                 SMU74_Discrete_DpmTable *table)
1557 {
1558         int result = -EINVAL;
1559         uint8_t count;
1560         struct pp_atomctrl_clock_dividers_vi dividers;
1561         struct phm_ppt_v1_information *table_info =
1562                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1563         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1564                         table_info->mm_dep_table;
1565         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1566         uint32_t vddci;
1567
1568         table->VceLevelCount = (uint8_t)(mm_table->count);
1569         table->VceBootLevel = 0;
1570
1571         for (count = 0; count < table->VceLevelCount; count++) {
1572                 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1573                 table->VceLevel[count].MinVoltage = 0;
1574                 table->VceLevel[count].MinVoltage |=
1575                                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1576
1577                 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1578                         vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1579                                                 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1580                 else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1581                         vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1582                 else
1583                         vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1584
1585
1586                 table->VceLevel[count].MinVoltage |=
1587                                 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1588                 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1589
1590                 /*retrieve divider value for VBIOS */
1591                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1592                                 table->VceLevel[count].Frequency, &dividers);
1593                 PP_ASSERT_WITH_CODE((0 == result),
1594                                 "can not find divide id for VCE engine clock",
1595                                 return result);
1596
1597                 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1598
1599                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1600                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1601         }
1602         return result;
1603 }
1604
1605 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1606                 SMU74_Discrete_DpmTable *table)
1607 {
1608         int result = -EINVAL;
1609         uint8_t count;
1610         struct pp_atomctrl_clock_dividers_vi dividers;
1611         struct phm_ppt_v1_information *table_info =
1612                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1613         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1614                         table_info->mm_dep_table;
1615         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1616         uint32_t vddci;
1617
1618         table->SamuBootLevel = 0;
1619         table->SamuLevelCount = (uint8_t)(mm_table->count);
1620
1621         for (count = 0; count < table->SamuLevelCount; count++) {
1622                 /* not sure whether we need evclk or not */
1623                 table->SamuLevel[count].MinVoltage = 0;
1624                 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1625                 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1626                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1627
1628                 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1629                         vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1630                                                 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1631                 else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1632                         vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1633                 else
1634                         vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1635
1636                 table->SamuLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1637                 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1638
1639                 /* retrieve divider value for VBIOS */
1640                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1641                                 table->SamuLevel[count].Frequency, &dividers);
1642                 PP_ASSERT_WITH_CODE((0 == result),
1643                                 "can not find divide id for samu clock", return result);
1644
1645                 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1646
1647                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1648                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1649         }
1650         return result;
1651 }
1652
1653 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1654                 int32_t eng_clock, int32_t mem_clock,
1655                 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1656 {
1657         uint32_t dram_timing;
1658         uint32_t dram_timing2;
1659         uint32_t burst_time;
1660         int result;
1661
1662         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1663                         eng_clock, mem_clock);
1664         PP_ASSERT_WITH_CODE(result == 0,
1665                         "Error calling VBIOS to set DRAM_TIMING.", return result);
1666
1667         dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1668         dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1669         burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1670
1671
1672         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
1673         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1674         arb_regs->McArbBurstTime   = (uint8_t)burst_time;
1675
1676         return 0;
1677 }
1678
1679 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1680 {
1681         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1682         struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1683         uint32_t i, j;
1684         int result = 0;
1685
1686         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1687                 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1688                         result = polaris10_populate_memory_timing_parameters(hwmgr,
1689                                         data->dpm_table.sclk_table.dpm_levels[i].value,
1690                                         data->dpm_table.mclk_table.dpm_levels[j].value,
1691                                         &arb_regs.entries[i][j]);
1692                         if (result == 0)
1693                                 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1694                         if (result != 0)
1695                                 return result;
1696                 }
1697         }
1698
1699         result = polaris10_copy_bytes_to_smc(
1700                         hwmgr->smumgr,
1701                         data->arb_table_start,
1702                         (uint8_t *)&arb_regs,
1703                         sizeof(SMU74_Discrete_MCArbDramTimingTable),
1704                         data->sram_end);
1705         return result;
1706 }
1707
1708 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1709                 struct SMU74_Discrete_DpmTable *table)
1710 {
1711         int result = -EINVAL;
1712         uint8_t count;
1713         struct pp_atomctrl_clock_dividers_vi dividers;
1714         struct phm_ppt_v1_information *table_info =
1715                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1716         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1717                         table_info->mm_dep_table;
1718         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1719         uint32_t vddci;
1720
1721         table->UvdLevelCount = (uint8_t)(mm_table->count);
1722         table->UvdBootLevel = 0;
1723
1724         for (count = 0; count < table->UvdLevelCount; count++) {
1725                 table->UvdLevel[count].MinVoltage = 0;
1726                 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1727                 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1728                 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1729                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1730
1731                 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1732                         vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1733                                                 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1734                 else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1735                         vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1736                 else
1737                         vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1738
1739                 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1740                 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1741
1742                 /* retrieve divider value for VBIOS */
1743                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1744                                 table->UvdLevel[count].VclkFrequency, &dividers);
1745                 PP_ASSERT_WITH_CODE((0 == result),
1746                                 "can not find divide id for Vclk clock", return result);
1747
1748                 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1749
1750                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1751                                 table->UvdLevel[count].DclkFrequency, &dividers);
1752                 PP_ASSERT_WITH_CODE((0 == result),
1753                                 "can not find divide id for Dclk clock", return result);
1754
1755                 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1756
1757                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1758                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1759                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1760         }
1761
1762         return result;
1763 }
1764
1765 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1766                 struct SMU74_Discrete_DpmTable *table)
1767 {
1768         int result = 0;
1769         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1770
1771         table->GraphicsBootLevel = 0;
1772         table->MemoryBootLevel = 0;
1773
1774         /* find boot level from dpm table */
1775         result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1776                         data->vbios_boot_state.sclk_bootup_value,
1777                         (uint32_t *)&(table->GraphicsBootLevel));
1778
1779         result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1780                         data->vbios_boot_state.mclk_bootup_value,
1781                         (uint32_t *)&(table->MemoryBootLevel));
1782
1783         table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
1784                         VOLTAGE_SCALE;
1785         table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1786                         VOLTAGE_SCALE;
1787         table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
1788                         VOLTAGE_SCALE;
1789
1790         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1791         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1792         CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1793
1794         return 0;
1795 }
1796
1797
1798 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1799 {
1800         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1801         struct phm_ppt_v1_information *table_info =
1802                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1803         uint8_t count, level;
1804
1805         count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1806
1807         for (level = 0; level < count; level++) {
1808                 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1809                                 data->vbios_boot_state.sclk_bootup_value) {
1810                         data->smc_state_table.GraphicsBootLevel = level;
1811                         break;
1812                 }
1813         }
1814
1815         count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1816         for (level = 0; level < count; level++) {
1817                 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1818                                 data->vbios_boot_state.mclk_bootup_value) {
1819                         data->smc_state_table.MemoryBootLevel = level;
1820                         break;
1821                 }
1822         }
1823
1824         return 0;
1825 }
1826
1827 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1828 {
1829         uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1830         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1831         uint8_t i, stretch_amount, volt_offset = 0;
1832         struct phm_ppt_v1_information *table_info =
1833                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1834         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1835                         table_info->vdd_dep_on_sclk;
1836
1837         stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1838
1839         /* Read SMU_Eefuse to read and calculate RO and determine
1840          * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1841          */
1842         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1843                         ixSMU_EFUSE_0 + (67 * 4));
1844         efuse &= 0xFF000000;
1845         efuse = efuse >> 24;
1846
1847         if (hwmgr->chip_id == CHIP_POLARIS10) {
1848                 min = 1000;
1849                 max = 2300;
1850         } else {
1851                 min = 1100;
1852                 max = 2100;
1853         }
1854
1855         ro = efuse * (max -min)/255 + min;
1856
1857         /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1858         for (i = 0; i < sclk_table->count; i++) {
1859                 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1860                                 sclk_table->entries[i].cks_enable << i;
1861                 if (hwmgr->chip_id == CHIP_POLARIS10) {
1862                         volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 -(ro - 70) * 1000000) / \
1863                                                 (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1864                         volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \
1865                                         (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
1866                 } else {
1867                         volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 -(ro - 50) * 1000000) / \
1868                                                 (2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));
1869                         volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \
1870                                         (3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));
1871                 }
1872
1873                 if (volt_without_cks >= volt_with_cks)
1874                         volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1875                                         sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
1876
1877                 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1878         }
1879
1880         data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
1881         /* Populate CKS Lookup Table */
1882         if (stretch_amount != 1 && stretch_amount != 2 && stretch_amount != 3 &&
1883                         stretch_amount != 4 && stretch_amount != 5) {
1884                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1885                                 PHM_PlatformCaps_ClockStretcher);
1886                 PP_ASSERT_WITH_CODE(false,
1887                                 "Stretch Amount in PPTable not supported\n",
1888                                 return -EINVAL);
1889         }
1890
1891         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1892         value &= 0xFFFFFFFE;
1893         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1894
1895         return 0;
1896 }
1897
1898 /**
1899 * Populates the SMC VRConfig field in DPM table.
1900 *
1901 * @param    hwmgr   the address of the hardware manager
1902 * @param    table   the SMC DPM table structure to be populated
1903 * @return   always 0
1904 */
1905 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1906                 struct SMU74_Discrete_DpmTable *table)
1907 {
1908         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1909         uint16_t config;
1910
1911         config = VR_MERGED_WITH_VDDC;
1912         table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1913
1914         /* Set Vddc Voltage Controller */
1915         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1916                 config = VR_SVI2_PLANE_1;
1917                 table->VRConfig |= config;
1918         } else {
1919                 PP_ASSERT_WITH_CODE(false,
1920                                 "VDDC should be on SVI2 control in merged mode!",
1921                                 );
1922         }
1923         /* Set Vddci Voltage Controller */
1924         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1925                 config = VR_SVI2_PLANE_2;  /* only in merged mode */
1926                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1927         } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1928                 config = VR_SMIO_PATTERN_1;
1929                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1930         } else {
1931                 config = VR_STATIC_VOLTAGE;
1932                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1933         }
1934         /* Set Mvdd Voltage Controller */
1935         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1936                 config = VR_SVI2_PLANE_2;
1937                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1938                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start +
1939                         offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
1940         } else {
1941                 config = VR_STATIC_VOLTAGE;
1942                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1943         }
1944
1945         return 0;
1946 }
1947
1948
1949 int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1950 {
1951         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1952         SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
1953         int result = 0;
1954         struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1955         AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1956         AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1957         uint32_t tmp, i;
1958         struct pp_smumgr *smumgr = hwmgr->smumgr;
1959         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
1960
1961         struct phm_ppt_v1_information *table_info =
1962                         (struct phm_ppt_v1_information *)hwmgr->pptable;
1963         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1964                         table_info->vdd_dep_on_sclk;
1965
1966
1967         if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
1968                 return result;
1969
1970         result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1971
1972         if (0 == result) {
1973                 table->BTCGB_VDROOP_TABLE[0].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1974                 table->BTCGB_VDROOP_TABLE[0].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1975                 table->BTCGB_VDROOP_TABLE[0].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1976                 table->BTCGB_VDROOP_TABLE[1].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1977                 table->BTCGB_VDROOP_TABLE[1].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1978                 table->BTCGB_VDROOP_TABLE[1].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1979                 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1980                 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1981                 table->AVFSGB_VDROOP_TABLE[0].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1982                 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1983                 table->AVFSGB_VDROOP_TABLE[0].m2_shift  = 12;
1984                 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1985                 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1986                 table->AVFSGB_VDROOP_TABLE[1].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1987                 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1988                 table->AVFSGB_VDROOP_TABLE[1].m2_shift  = 12;
1989                 table->MaxVoltage                = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1990                 AVFS_meanNsigma.Aconstant[0]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1991                 AVFS_meanNsigma.Aconstant[1]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1992                 AVFS_meanNsigma.Aconstant[2]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1993                 AVFS_meanNsigma.DC_tol_sigma      = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1994                 AVFS_meanNsigma.Platform_mean     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1995                 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1996                 AVFS_meanNsigma.Platform_sigma     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1997
1998                 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1999                         AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
2000                         AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
2001                 }
2002
2003                 result = polaris10_read_smc_sram_dword(smumgr,
2004                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
2005                                 &tmp, data->sram_end);
2006
2007                 polaris10_copy_bytes_to_smc(smumgr,
2008                                         tmp,
2009                                         (uint8_t *)&AVFS_meanNsigma,
2010                                         sizeof(AVFS_meanNsigma_t),
2011                                         data->sram_end);
2012
2013                 result = polaris10_read_smc_sram_dword(smumgr,
2014                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
2015                                 &tmp, data->sram_end);
2016                 polaris10_copy_bytes_to_smc(smumgr,
2017                                         tmp,
2018                                         (uint8_t *)&AVFS_SclkOffset,
2019                                         sizeof(AVFS_Sclk_Offset_t),
2020                                         data->sram_end);
2021
2022                 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
2023                                                 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
2024                                                 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
2025                                                 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
2026                 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
2027         }
2028         return result;
2029 }
2030
2031
2032 /**
2033 * Initializes the SMC table and uploads it
2034 *
2035 * @param    hwmgr  the address of the powerplay hardware manager.
2036 * @return   always 0
2037 */
2038 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
2039 {
2040         int result;
2041         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2042         struct phm_ppt_v1_information *table_info =
2043                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2044         struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
2045         const struct polaris10_ulv_parm *ulv = &(data->ulv);
2046         uint8_t i;
2047         struct pp_atomctrl_gpio_pin_assignment gpio_pin;
2048         pp_atomctrl_clock_dividers_vi dividers;
2049
2050         result = polaris10_setup_default_dpm_tables(hwmgr);
2051         PP_ASSERT_WITH_CODE(0 == result,
2052                         "Failed to setup default DPM tables!", return result);
2053
2054         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
2055                 polaris10_populate_smc_voltage_tables(hwmgr, table);
2056
2057         table->SystemFlags = 0;
2058         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2059                         PHM_PlatformCaps_AutomaticDCTransition))
2060                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2061
2062         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2063                         PHM_PlatformCaps_StepVddc))
2064                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2065
2066         if (data->is_memory_gddr5)
2067                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2068
2069         if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2070                 result = polaris10_populate_ulv_state(hwmgr, table);
2071                 PP_ASSERT_WITH_CODE(0 == result,
2072                                 "Failed to initialize ULV state!", return result);
2073                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2074                                 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
2075         }
2076
2077         result = polaris10_populate_smc_link_level(hwmgr, table);
2078         PP_ASSERT_WITH_CODE(0 == result,
2079                         "Failed to initialize Link Level!", return result);
2080
2081         result = polaris10_populate_all_graphic_levels(hwmgr);
2082         PP_ASSERT_WITH_CODE(0 == result,
2083                         "Failed to initialize Graphics Level!", return result);
2084
2085         result = polaris10_populate_all_memory_levels(hwmgr);
2086         PP_ASSERT_WITH_CODE(0 == result,
2087                         "Failed to initialize Memory Level!", return result);
2088
2089         result = polaris10_populate_smc_acpi_level(hwmgr, table);
2090         PP_ASSERT_WITH_CODE(0 == result,
2091                         "Failed to initialize ACPI Level!", return result);
2092
2093         result = polaris10_populate_smc_vce_level(hwmgr, table);
2094         PP_ASSERT_WITH_CODE(0 == result,
2095                         "Failed to initialize VCE Level!", return result);
2096
2097         result = polaris10_populate_smc_samu_level(hwmgr, table);
2098         PP_ASSERT_WITH_CODE(0 == result,
2099                         "Failed to initialize SAMU Level!", return result);
2100
2101         /* Since only the initial state is completely set up at this point
2102          * (the other states are just copies of the boot state) we only
2103          * need to populate the  ARB settings for the initial state.
2104          */
2105         result = polaris10_program_memory_timing_parameters(hwmgr);
2106         PP_ASSERT_WITH_CODE(0 == result,
2107                         "Failed to Write ARB settings for the initial state.", return result);
2108
2109         result = polaris10_populate_smc_uvd_level(hwmgr, table);
2110         PP_ASSERT_WITH_CODE(0 == result,
2111                         "Failed to initialize UVD Level!", return result);
2112
2113         result = polaris10_populate_smc_boot_level(hwmgr, table);
2114         PP_ASSERT_WITH_CODE(0 == result,
2115                         "Failed to initialize Boot Level!", return result);
2116
2117         result = polaris10_populate_smc_initailial_state(hwmgr);
2118         PP_ASSERT_WITH_CODE(0 == result,
2119                         "Failed to initialize Boot State!", return result);
2120
2121         result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
2122         PP_ASSERT_WITH_CODE(0 == result,
2123                         "Failed to populate BAPM Parameters!", return result);
2124
2125         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2126                         PHM_PlatformCaps_ClockStretcher)) {
2127                 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
2128                 PP_ASSERT_WITH_CODE(0 == result,
2129                                 "Failed to populate Clock Stretcher Data Table!",
2130                                 return result);
2131         }
2132
2133         result = polaris10_populate_avfs_parameters(hwmgr);
2134         PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
2135
2136         table->CurrSclkPllRange = 0xff;
2137         table->GraphicsVoltageChangeEnable  = 1;
2138         table->GraphicsThermThrottleEnable  = 1;
2139         table->GraphicsInterval = 1;
2140         table->VoltageInterval  = 1;
2141         table->ThermalInterval  = 1;
2142         table->TemperatureLimitHigh =
2143                         table_info->cac_dtp_table->usTargetOperatingTemp *
2144                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2145         table->TemperatureLimitLow  =
2146                         (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2147                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2148         table->MemoryVoltageChangeEnable = 1;
2149         table->MemoryInterval = 1;
2150         table->VoltageResponseTime = 0;
2151         table->PhaseResponseTime = 0;
2152         table->MemoryThermThrottleEnable = 1;
2153         table->PCIeBootLinkLevel = 0;
2154         table->PCIeGenInterval = 1;
2155         table->VRConfig = 0;
2156
2157         result = polaris10_populate_vr_config(hwmgr, table);
2158         PP_ASSERT_WITH_CODE(0 == result,
2159                         "Failed to populate VRConfig setting!", return result);
2160
2161         table->ThermGpio = 17;
2162         table->SclkStepSize = 0x4000;
2163
2164         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2165                 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2166         } else {
2167                 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
2168                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2169                                 PHM_PlatformCaps_RegulatorHot);
2170         }
2171
2172         if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2173                         &gpio_pin)) {
2174                 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2175                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2176                                 PHM_PlatformCaps_AutomaticDCTransition);
2177         } else {
2178                 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
2179                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2180                                 PHM_PlatformCaps_AutomaticDCTransition);
2181         }
2182
2183         /* Thermal Output GPIO */
2184         if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2185                         &gpio_pin)) {
2186                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2187                                 PHM_PlatformCaps_ThermalOutGPIO);
2188
2189                 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2190
2191                 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2192                  * since VBIOS will program this register to set 'inactive state',
2193                  * driver can then determine 'active state' from this and
2194                  * program SMU with correct polarity
2195                  */
2196                 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2197                                         & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2198                 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2199
2200                 /* if required, combine VRHot/PCC with thermal out GPIO */
2201                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2202                 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2203                         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2204         } else {
2205                 table->ThermOutGpio = 17;
2206                 table->ThermOutPolarity = 1;
2207                 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2208         }
2209
2210         /* Populate BIF_SCLK levels into SMC DPM table */
2211         for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2212                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], &dividers);
2213                 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2214
2215                 if (i == 0)
2216                         table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2217                 else
2218                         table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2219         }
2220
2221         for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2222                 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2223
2224         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2225         CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2226         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2227         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2228         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2229         CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2230         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2231         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2232         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2233         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2234
2235         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2236         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
2237                         data->dpm_table_start +
2238                         offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2239                         (uint8_t *)&(table->SystemFlags),
2240                         sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2241                         data->sram_end);
2242         PP_ASSERT_WITH_CODE(0 == result,
2243                         "Failed to upload dpm data to SMC memory!", return result);
2244
2245         return 0;
2246 }
2247
2248 /**
2249 * Initialize the ARB DRAM timing table's index field.
2250 *
2251 * @param    hwmgr  the address of the powerplay hardware manager.
2252 * @return   always 0
2253 */
2254 static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
2255 {
2256         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2257         uint32_t tmp;
2258         int result;
2259
2260         /* This is a read-modify-write on the first byte of the ARB table.
2261          * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2262          * is the field 'current'.
2263          * This solution is ugly, but we never write the whole table only
2264          * individual fields in it.
2265          * In reality this field should not be in that structure
2266          * but in a soft register.
2267          */
2268         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
2269                         data->arb_table_start, &tmp, data->sram_end);
2270
2271         if (result)
2272                 return result;
2273
2274         tmp &= 0x00FFFFFF;
2275         tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2276
2277         return polaris10_write_smc_sram_dword(hwmgr->smumgr,
2278                         data->arb_table_start, tmp, data->sram_end);
2279 }
2280
2281 static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
2282 {
2283         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2284                         PHM_PlatformCaps_RegulatorHot))
2285                 return smum_send_msg_to_smc(hwmgr->smumgr,
2286                                 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2287
2288         return 0;
2289 }
2290
2291 static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
2292 {
2293         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2294                         SCLK_PWRMGT_OFF, 0);
2295         return 0;
2296 }
2297
2298 static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
2299 {
2300         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2301         struct polaris10_ulv_parm *ulv = &(data->ulv);
2302
2303         if (ulv->ulv_supported)
2304                 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2305
2306         return 0;
2307 }
2308
2309 static int polaris10_disable_ulv(struct pp_hwmgr *hwmgr)
2310 {
2311         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2312         struct polaris10_ulv_parm *ulv = &(data->ulv);
2313
2314         if (ulv->ulv_supported)
2315                 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableULV);
2316
2317         return 0;
2318 }
2319
2320 static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2321 {
2322         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2323                         PHM_PlatformCaps_SclkDeepSleep)) {
2324                 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2325                         PP_ASSERT_WITH_CODE(false,
2326                                         "Attempt to enable Master Deep Sleep switch failed!",
2327                                         return -1);
2328         } else {
2329                 if (smum_send_msg_to_smc(hwmgr->smumgr,
2330                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2331                         PP_ASSERT_WITH_CODE(false,
2332                                         "Attempt to disable Master Deep Sleep switch failed!",
2333                                         return -1);
2334                 }
2335         }
2336
2337         return 0;
2338 }
2339
2340 static int polaris10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2341 {
2342         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2343                         PHM_PlatformCaps_SclkDeepSleep)) {
2344                 if (smum_send_msg_to_smc(hwmgr->smumgr,
2345                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2346                         PP_ASSERT_WITH_CODE(false,
2347                                         "Attempt to disable Master Deep Sleep switch failed!",
2348                                         return -1);
2349                 }
2350         }
2351
2352         return 0;
2353 }
2354
2355 static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2356 {
2357         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2358         uint32_t soft_register_value = 0;
2359         uint32_t handshake_disables_offset = data->soft_regs_start
2360                                 + offsetof(SMU74_SoftRegisters, HandshakeDisables);
2361
2362         /* enable SCLK dpm */
2363         if (!data->sclk_dpm_key_disabled)
2364                 PP_ASSERT_WITH_CODE(
2365                 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2366                 "Failed to enable SCLK DPM during DPM Start Function!",
2367                 return -1);
2368
2369         /* enable MCLK dpm */
2370         if (0 == data->mclk_dpm_key_disabled) {
2371 /* Disable UVD - SMU handshake for MCLK. */
2372                 soft_register_value = cgs_read_ind_register(hwmgr->device,
2373                                         CGS_IND_REG__SMC, handshake_disables_offset);
2374                 soft_register_value |= SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2375                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2376                                 handshake_disables_offset, soft_register_value);
2377
2378                 PP_ASSERT_WITH_CODE(
2379                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2380                                                 PPSMC_MSG_MCLKDPM_Enable)),
2381                                 "Failed to enable MCLK DPM during DPM Start Function!",
2382                                 return -1);
2383
2384                 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2385
2386                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2387                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2388                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2389                 udelay(10);
2390                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2391                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2392                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2393         }
2394
2395         return 0;
2396 }
2397
2398 static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
2399 {
2400         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2401
2402         /*enable general power management */
2403
2404         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2405                         GLOBAL_PWRMGT_EN, 1);
2406
2407         /* enable sclk deep sleep */
2408
2409         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2410                         DYNAMIC_PM_EN, 1);
2411
2412         /* prepare for PCIE DPM */
2413
2414         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2415                         data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2416                                         VoltageChangeTimeout), 0x1000);
2417         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2418                         SWRST_COMMAND_1, RESETLC, 0x0);
2419 /*
2420         PP_ASSERT_WITH_CODE(
2421                         (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2422                                         PPSMC_MSG_Voltage_Cntl_Enable)),
2423                         "Failed to enable voltage DPM during DPM Start Function!",
2424                         return -1);
2425 */
2426
2427         if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
2428                 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2429                 return -1;
2430         }
2431
2432         /* enable PCIE dpm */
2433         if (0 == data->pcie_dpm_key_disabled) {
2434                 PP_ASSERT_WITH_CODE(
2435                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2436                                                 PPSMC_MSG_PCIeDPM_Enable)),
2437                                 "Failed to enable pcie DPM during DPM Start Function!",
2438                                 return -1);
2439         }
2440
2441         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2442                                 PHM_PlatformCaps_Falcon_QuickTransition)) {
2443                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2444                                 PPSMC_MSG_EnableACDCGPIOInterrupt)),
2445                                 "Failed to enable AC DC GPIO Interrupt!",
2446                                 );
2447         }
2448
2449         return 0;
2450 }
2451
2452 static int polaris10_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2453 {
2454         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2455
2456         /* disable SCLK dpm */
2457         if (!data->sclk_dpm_key_disabled)
2458                 PP_ASSERT_WITH_CODE(
2459                                 (smum_send_msg_to_smc(hwmgr->smumgr,
2460                                                 PPSMC_MSG_DPM_Disable) == 0),
2461                                 "Failed to disable SCLK DPM!",
2462                                 return -1);
2463
2464         /* disable MCLK dpm */
2465         if (!data->mclk_dpm_key_disabled) {
2466                 PP_ASSERT_WITH_CODE(
2467                                 (smum_send_msg_to_smc(hwmgr->smumgr,
2468                                                 PPSMC_MSG_MCLKDPM_Disable) == 0),
2469                                 "Failed to disable MCLK DPM!",
2470                                 return -1);
2471         }
2472
2473         return 0;
2474 }
2475
2476 static int polaris10_stop_dpm(struct pp_hwmgr *hwmgr)
2477 {
2478         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2479
2480         /* disable general power management */
2481         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2482                         GLOBAL_PWRMGT_EN, 0);
2483         /* disable sclk deep sleep */
2484         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2485                         DYNAMIC_PM_EN, 0);
2486
2487         /* disable PCIE dpm */
2488         if (!data->pcie_dpm_key_disabled) {
2489                 PP_ASSERT_WITH_CODE(
2490                                 (smum_send_msg_to_smc(hwmgr->smumgr,
2491                                                 PPSMC_MSG_PCIeDPM_Disable) == 0),
2492                                 "Failed to disable pcie DPM during DPM Stop Function!",
2493                                 return -1);
2494         }
2495
2496         if (polaris10_disable_sclk_mclk_dpm(hwmgr)) {
2497                 printk(KERN_ERR "Failed to disable Sclk DPM and Mclk DPM!");
2498                 return -1;
2499         }
2500
2501         return 0;
2502 }
2503
2504 static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
2505 {
2506         bool protection;
2507         enum DPM_EVENT_SRC src;
2508
2509         switch (sources) {
2510         default:
2511                 printk(KERN_ERR "Unknown throttling event sources.");
2512                 /* fall through */
2513         case 0:
2514                 protection = false;
2515                 /* src is unused */
2516                 break;
2517         case (1 << PHM_AutoThrottleSource_Thermal):
2518                 protection = true;
2519                 src = DPM_EVENT_SRC_DIGITAL;
2520                 break;
2521         case (1 << PHM_AutoThrottleSource_External):
2522                 protection = true;
2523                 src = DPM_EVENT_SRC_EXTERNAL;
2524                 break;
2525         case (1 << PHM_AutoThrottleSource_External) |
2526                         (1 << PHM_AutoThrottleSource_Thermal):
2527                 protection = true;
2528                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2529                 break;
2530         }
2531         /* Order matters - don't enable thermal protection for the wrong source. */
2532         if (protection) {
2533                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2534                                 DPM_EVENT_SRC, src);
2535                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2536                                 THERMAL_PROTECTION_DIS,
2537                                 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2538                                                 PHM_PlatformCaps_ThermalController));
2539         } else
2540                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2541                                 THERMAL_PROTECTION_DIS, 1);
2542 }
2543
2544 static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2545                 PHM_AutoThrottleSource source)
2546 {
2547         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2548
2549         if (!(data->active_auto_throttle_sources & (1 << source))) {
2550                 data->active_auto_throttle_sources |= 1 << source;
2551                 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2552         }
2553         return 0;
2554 }
2555
2556 static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2557 {
2558         return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2559 }
2560
2561 static int polaris10_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2562                 PHM_AutoThrottleSource source)
2563 {
2564         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2565
2566         if (data->active_auto_throttle_sources & (1 << source)) {
2567                 data->active_auto_throttle_sources &= ~(1 << source);
2568                 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2569         }
2570         return 0;
2571 }
2572
2573 static int polaris10_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2574 {
2575         return polaris10_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2576 }
2577
2578 int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
2579 {
2580         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2581         data->pcie_performance_request = true;
2582
2583         return 0;
2584 }
2585
2586 int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2587 {
2588         int tmp_result, result = 0;
2589         tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2590         PP_ASSERT_WITH_CODE(result == 0,
2591                         "DPM is already running right now, no need to enable DPM!",
2592                         return 0);
2593
2594         if (polaris10_voltage_control(hwmgr)) {
2595                 tmp_result = polaris10_enable_voltage_control(hwmgr);
2596                 PP_ASSERT_WITH_CODE(tmp_result == 0,
2597                                 "Failed to enable voltage control!",
2598                                 result = tmp_result);
2599
2600                 tmp_result = polaris10_construct_voltage_tables(hwmgr);
2601                 PP_ASSERT_WITH_CODE((0 == tmp_result),
2602                                 "Failed to contruct voltage tables!",
2603                                 result = tmp_result);
2604         }
2605
2606         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2607                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2608                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2609                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2610
2611         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2612                         PHM_PlatformCaps_ThermalController))
2613                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2614                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2615
2616         tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
2617         PP_ASSERT_WITH_CODE((0 == tmp_result),
2618                         "Failed to program static screen threshold parameters!",
2619                         result = tmp_result);
2620
2621         tmp_result = polaris10_enable_display_gap(hwmgr);
2622         PP_ASSERT_WITH_CODE((0 == tmp_result),
2623                         "Failed to enable display gap!", result = tmp_result);
2624
2625         tmp_result = polaris10_program_voting_clients(hwmgr);
2626         PP_ASSERT_WITH_CODE((0 == tmp_result),
2627                         "Failed to program voting clients!", result = tmp_result);
2628
2629         tmp_result = polaris10_process_firmware_header(hwmgr);
2630         PP_ASSERT_WITH_CODE((0 == tmp_result),
2631                         "Failed to process firmware header!", result = tmp_result);
2632
2633         tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
2634         PP_ASSERT_WITH_CODE((0 == tmp_result),
2635                         "Failed to initialize switch from ArbF0 to F1!",
2636                         result = tmp_result);
2637
2638         tmp_result = polaris10_init_smc_table(hwmgr);
2639         PP_ASSERT_WITH_CODE((0 == tmp_result),
2640                         "Failed to initialize SMC table!", result = tmp_result);
2641
2642         tmp_result = polaris10_init_arb_table_index(hwmgr);
2643         PP_ASSERT_WITH_CODE((0 == tmp_result),
2644                         "Failed to initialize ARB table index!", result = tmp_result);
2645
2646         tmp_result = polaris10_populate_pm_fuses(hwmgr);
2647         PP_ASSERT_WITH_CODE((0 == tmp_result),
2648                         "Failed to populate PM fuses!", result = tmp_result);
2649
2650         tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
2651         PP_ASSERT_WITH_CODE((0 == tmp_result),
2652                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2653
2654         smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay);
2655
2656         tmp_result = polaris10_enable_sclk_control(hwmgr);
2657         PP_ASSERT_WITH_CODE((0 == tmp_result),
2658                         "Failed to enable SCLK control!", result = tmp_result);
2659
2660         tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
2661         PP_ASSERT_WITH_CODE((0 == tmp_result),
2662                         "Failed to enable voltage control!", result = tmp_result);
2663
2664         tmp_result = polaris10_enable_ulv(hwmgr);
2665         PP_ASSERT_WITH_CODE((0 == tmp_result),
2666                         "Failed to enable ULV!", result = tmp_result);
2667
2668         tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
2669         PP_ASSERT_WITH_CODE((0 == tmp_result),
2670                         "Failed to enable deep sleep master switch!", result = tmp_result);
2671
2672         tmp_result = polaris10_start_dpm(hwmgr);
2673         PP_ASSERT_WITH_CODE((0 == tmp_result),
2674                         "Failed to start DPM!", result = tmp_result);
2675
2676         tmp_result = polaris10_enable_smc_cac(hwmgr);
2677         PP_ASSERT_WITH_CODE((0 == tmp_result),
2678                         "Failed to enable SMC CAC!", result = tmp_result);
2679
2680         tmp_result = polaris10_enable_power_containment(hwmgr);
2681         PP_ASSERT_WITH_CODE((0 == tmp_result),
2682                         "Failed to enable power containment!", result = tmp_result);
2683
2684         tmp_result = polaris10_power_control_set_level(hwmgr);
2685         PP_ASSERT_WITH_CODE((0 == tmp_result),
2686                         "Failed to power control set level!", result = tmp_result);
2687
2688         tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
2689         PP_ASSERT_WITH_CODE((0 == tmp_result),
2690                         "Failed to enable thermal auto throttle!", result = tmp_result);
2691
2692         tmp_result = polaris10_pcie_performance_request(hwmgr);
2693         PP_ASSERT_WITH_CODE((0 == tmp_result),
2694                         "pcie performance request failed!", result = tmp_result);
2695
2696         return result;
2697 }
2698
2699 int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2700 {
2701         int tmp_result, result = 0;
2702
2703         tmp_result = (polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2704         PP_ASSERT_WITH_CODE(tmp_result == 0,
2705                         "DPM is not running right now, no need to disable DPM!",
2706                         return 0);
2707
2708         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2709                         PHM_PlatformCaps_ThermalController))
2710                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2711                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
2712
2713         tmp_result = polaris10_disable_power_containment(hwmgr);
2714         PP_ASSERT_WITH_CODE((tmp_result == 0),
2715                         "Failed to disable power containment!", result = tmp_result);
2716
2717         tmp_result = polaris10_disable_smc_cac(hwmgr);
2718         PP_ASSERT_WITH_CODE((tmp_result == 0),
2719                         "Failed to disable SMC CAC!", result = tmp_result);
2720
2721         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2722                         CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
2723         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2724                         GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
2725
2726         tmp_result = polaris10_disable_thermal_auto_throttle(hwmgr);
2727         PP_ASSERT_WITH_CODE((tmp_result == 0),
2728                         "Failed to disable thermal auto throttle!", result = tmp_result);
2729
2730         tmp_result = polaris10_stop_dpm(hwmgr);
2731         PP_ASSERT_WITH_CODE((tmp_result == 0),
2732                         "Failed to stop DPM!", result = tmp_result);
2733
2734         tmp_result = polaris10_disable_deep_sleep_master_switch(hwmgr);
2735         PP_ASSERT_WITH_CODE((tmp_result == 0),
2736                         "Failed to disable deep sleep master switch!", result = tmp_result);
2737
2738         tmp_result = polaris10_disable_ulv(hwmgr);
2739         PP_ASSERT_WITH_CODE((tmp_result == 0),
2740                         "Failed to disable ULV!", result = tmp_result);
2741
2742         tmp_result = polaris10_clear_voting_clients(hwmgr);
2743         PP_ASSERT_WITH_CODE((tmp_result == 0),
2744                         "Failed to clear voting clients!", result = tmp_result);
2745
2746         tmp_result = polaris10_reset_to_default(hwmgr);
2747         PP_ASSERT_WITH_CODE((tmp_result == 0),
2748                         "Failed to reset to default!", result = tmp_result);
2749
2750         tmp_result = polaris10_force_switch_to_arbf0(hwmgr);
2751         PP_ASSERT_WITH_CODE((tmp_result == 0),
2752                         "Failed to force to switch arbf0!", result = tmp_result);
2753
2754         return result;
2755 }
2756
2757 int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
2758 {
2759
2760         return 0;
2761 }
2762
2763 int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2764 {
2765         return phm_hwmgr_backend_fini(hwmgr);
2766 }
2767
2768 int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
2769 {
2770         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2771
2772         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2773                         PHM_PlatformCaps_SclkDeepSleep);
2774
2775         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2776                 PHM_PlatformCaps_DynamicPatchPowerState);
2777
2778         if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2779                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2780                                 PHM_PlatformCaps_EnableMVDDControl);
2781
2782         if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2783                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2784                                 PHM_PlatformCaps_ControlVDDCI);
2785
2786         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2787                          PHM_PlatformCaps_TablelessHardwareInterface);
2788
2789         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2790                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
2791
2792         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2793                         PHM_PlatformCaps_DynamicPowerManagement);
2794
2795         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2796                         PHM_PlatformCaps_UnTabledHardwareInterface);
2797
2798         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2799                         PHM_PlatformCaps_TablelessHardwareInterface);
2800
2801         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2802                                         PHM_PlatformCaps_SMC);
2803
2804         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2805                                         PHM_PlatformCaps_NonABMSupportInPPLib);
2806
2807         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2808                                         PHM_PlatformCaps_DynamicUVDState);
2809
2810         /* power tune caps Assume disabled */
2811         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2812                                                 PHM_PlatformCaps_SQRamping);
2813         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2814                                                 PHM_PlatformCaps_DBRamping);
2815         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2816                                                 PHM_PlatformCaps_TDRamping);
2817         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2818                                                 PHM_PlatformCaps_TCPRamping);
2819
2820         if (hwmgr->powercontainment_enabled)
2821                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2822                             PHM_PlatformCaps_PowerContainment);
2823         else
2824                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2825                             PHM_PlatformCaps_PowerContainment);
2826
2827         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2828                                                         PHM_PlatformCaps_CAC);
2829
2830         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2831                                                 PHM_PlatformCaps_RegulatorHot);
2832
2833         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2834                                                 PHM_PlatformCaps_AutomaticDCTransition);
2835
2836         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2837                                                 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2838
2839         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2840                                                 PHM_PlatformCaps_FanSpeedInTableIsRPM);
2841
2842         if (hwmgr->chip_id == CHIP_POLARIS11)
2843                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2844                                         PHM_PlatformCaps_SPLLShutdownSupport);
2845         return 0;
2846 }
2847
2848 static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
2849 {
2850         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2851
2852         polaris10_initialize_power_tune_defaults(hwmgr);
2853
2854         data->pcie_gen_performance.max = PP_PCIEGen1;
2855         data->pcie_gen_performance.min = PP_PCIEGen3;
2856         data->pcie_gen_power_saving.max = PP_PCIEGen1;
2857         data->pcie_gen_power_saving.min = PP_PCIEGen3;
2858         data->pcie_lane_performance.max = 0;
2859         data->pcie_lane_performance.min = 16;
2860         data->pcie_lane_power_saving.max = 0;
2861         data->pcie_lane_power_saving.min = 16;
2862 }
2863
2864 /**
2865 * Get Leakage VDDC based on leakage ID.
2866 *
2867 * @param    hwmgr  the address of the powerplay hardware manager.
2868 * @return   always 0
2869 */
2870 static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
2871 {
2872         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2873         uint16_t vv_id;
2874         uint32_t vddc = 0;
2875         uint16_t i, j;
2876         uint32_t sclk = 0;
2877         struct phm_ppt_v1_information *table_info =
2878                         (struct phm_ppt_v1_information *)hwmgr->pptable;
2879         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2880                         table_info->vdd_dep_on_sclk;
2881         int result;
2882
2883         for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
2884                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2885                 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2886                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
2887                         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2888                                         PHM_PlatformCaps_ClockStretcher)) {
2889                                 for (j = 1; j < sclk_table->count; j++) {
2890                                         if (sclk_table->entries[j].clk == sclk &&
2891                                                         sclk_table->entries[j].cks_enable == 0) {
2892                                                 sclk += 5000;
2893                                                 break;
2894                                         }
2895                                 }
2896                         }
2897
2898                         if (atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2899                                                 VOLTAGE_TYPE_VDDC,
2900                                                 sclk, vv_id, &vddc) != 0) {
2901                                 printk(KERN_WARNING "failed to retrieving EVV voltage!\n");
2902                                 continue;
2903                         }
2904
2905                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC.
2906                          * real voltage level in unit of 0.01mv */
2907                         PP_ASSERT_WITH_CODE((vddc < 200000 && vddc != 0),
2908                                         "Invalid VDDC value", result = -EINVAL;);
2909
2910                         /* the voltage should not be zero nor equal to leakage ID */
2911                         if (vddc != 0 && vddc != vv_id) {
2912                                 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2913                                 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2914                                 data->vddc_leakage.count++;
2915                         }
2916                 }
2917         }
2918
2919         return 0;
2920 }
2921
2922 /**
2923  * Change virtual leakage voltage to actual value.
2924  *
2925  * @param     hwmgr  the address of the powerplay hardware manager.
2926  * @param     pointer to changing voltage
2927  * @param     pointer to leakage table
2928  */
2929 static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2930                 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
2931 {
2932         uint32_t index;
2933
2934         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2935         for (index = 0; index < leakage_table->count; index++) {
2936                 /* if this voltage matches a leakage voltage ID */
2937                 /* patch with actual leakage voltage */
2938                 if (leakage_table->leakage_id[index] == *voltage) {
2939                         *voltage = leakage_table->actual_voltage[index];
2940                         break;
2941                 }
2942         }
2943
2944         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2945                 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2946 }
2947
2948 /**
2949 * Patch voltage lookup table by EVV leakages.
2950 *
2951 * @param     hwmgr  the address of the powerplay hardware manager.
2952 * @param     pointer to voltage lookup table
2953 * @param     pointer to leakage table
2954 * @return     always 0
2955 */
2956 static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
2957                 phm_ppt_v1_voltage_lookup_table *lookup_table,
2958                 struct polaris10_leakage_voltage *leakage_table)
2959 {
2960         uint32_t i;
2961
2962         for (i = 0; i < lookup_table->count; i++)
2963                 polaris10_patch_with_vdd_leakage(hwmgr,
2964                                 &lookup_table->entries[i].us_vdd, leakage_table);
2965
2966         return 0;
2967 }
2968
2969 static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2970                 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
2971                 uint16_t *vddc)
2972 {
2973         struct phm_ppt_v1_information *table_info =
2974                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2975         polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
2976         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2977                         table_info->max_clock_voltage_on_dc.vddc;
2978         return 0;
2979 }
2980
2981 static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
2982                 struct pp_hwmgr *hwmgr)
2983 {
2984         uint8_t entryId;
2985         uint8_t voltageId;
2986         struct phm_ppt_v1_information *table_info =
2987                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2988
2989         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2990                         table_info->vdd_dep_on_sclk;
2991         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2992                         table_info->vdd_dep_on_mclk;
2993         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2994                         table_info->mm_dep_table;
2995
2996         for (entryId = 0; entryId < sclk_table->count; ++entryId) {
2997                 voltageId = sclk_table->entries[entryId].vddInd;
2998                 sclk_table->entries[entryId].vddc =
2999                                 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
3000         }
3001
3002         for (entryId = 0; entryId < mclk_table->count; ++entryId) {
3003                 voltageId = mclk_table->entries[entryId].vddInd;
3004                 mclk_table->entries[entryId].vddc =
3005                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
3006         }
3007
3008         for (entryId = 0; entryId < mm_table->count; ++entryId) {
3009                 voltageId = mm_table->entries[entryId].vddcInd;
3010                 mm_table->entries[entryId].vddc =
3011                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
3012         }
3013
3014         return 0;
3015
3016 }
3017
3018 static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
3019 {
3020         /* Need to determine if we need calculated voltage. */
3021         return 0;
3022 }
3023
3024 static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
3025 {
3026         /* Need to determine if we need calculated voltage from mm table. */
3027         return 0;
3028 }
3029
3030 static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
3031                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
3032 {
3033         uint32_t table_size, i, j;
3034         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
3035         table_size = lookup_table->count;
3036
3037         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
3038                 "Lookup table is empty", return -EINVAL);
3039
3040         /* Sorting voltages */
3041         for (i = 0; i < table_size - 1; i++) {
3042                 for (j = i + 1; j > 0; j--) {
3043                         if (lookup_table->entries[j].us_vdd <
3044                                         lookup_table->entries[j - 1].us_vdd) {
3045                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
3046                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
3047                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
3048                         }
3049                 }
3050         }
3051
3052         return 0;
3053 }
3054
3055 static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
3056 {
3057         int result = 0;
3058         int tmp_result;
3059         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3060         struct phm_ppt_v1_information *table_info =
3061                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3062
3063         tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
3064                         table_info->vddc_lookup_table, &(data->vddc_leakage));
3065         if (tmp_result)
3066                 result = tmp_result;
3067
3068         tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
3069                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
3070         if (tmp_result)
3071                 result = tmp_result;
3072
3073         tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
3074         if (tmp_result)
3075                 result = tmp_result;
3076
3077         tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
3078         if (tmp_result)
3079                 result = tmp_result;
3080
3081         tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
3082         if (tmp_result)
3083                 result = tmp_result;
3084
3085         tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
3086         if (tmp_result)
3087                 result = tmp_result;
3088
3089         return result;
3090 }
3091
3092 static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
3093 {
3094         struct phm_ppt_v1_information *table_info =
3095                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3096
3097         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
3098                                                 table_info->vdd_dep_on_sclk;
3099         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
3100                                                 table_info->vdd_dep_on_mclk;
3101
3102         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
3103                 "VDD dependency on SCLK table is missing.       \
3104                 This table is mandatory", return -EINVAL);
3105         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
3106                 "VDD dependency on SCLK table has to have is missing.   \
3107                 This table is mandatory", return -EINVAL);
3108
3109         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
3110                 "VDD dependency on MCLK table is missing.       \
3111                 This table is mandatory", return -EINVAL);
3112         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
3113                 "VDD dependency on MCLK table has to have is missing.    \
3114                 This table is mandatory", return -EINVAL);
3115
3116         table_info->max_clock_voltage_on_ac.sclk =
3117                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
3118         table_info->max_clock_voltage_on_ac.mclk =
3119                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
3120         table_info->max_clock_voltage_on_ac.vddc =
3121                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3122         table_info->max_clock_voltage_on_ac.vddci =
3123                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
3124
3125         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
3126         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
3127         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
3128         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
3129
3130         return 0;
3131 }
3132
3133 int polaris10_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
3134 {
3135         struct phm_ppt_v1_information *table_info =
3136                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
3137         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3138                         table_info->vdd_dep_on_mclk;
3139         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
3140                         table_info->vddc_lookup_table;
3141         uint32_t i;
3142
3143         if (hwmgr->chip_id == CHIP_POLARIS10 && hwmgr->hw_revision == 0xC7) {
3144                 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
3145                         return 0;
3146
3147                 for (i = 0; i < lookup_table->count; i++) {
3148                         if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) {
3149                                 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;
3150                                 return 0;
3151                         }
3152                 }
3153         }
3154         return 0;
3155 }
3156
3157
3158 int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
3159 {
3160         struct polaris10_hwmgr *data;
3161         struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
3162         uint32_t temp_reg;
3163         int result;
3164         struct phm_ppt_v1_information *table_info =
3165                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3166
3167         data = kzalloc(sizeof(struct polaris10_hwmgr), GFP_KERNEL);
3168         if (data == NULL)
3169                 return -ENOMEM;
3170
3171         hwmgr->backend = data;
3172
3173         data->dll_default_on = false;
3174         data->sram_end = SMC_RAM_END;
3175         data->mclk_dpm0_activity_target = 0xa;
3176         data->disable_dpm_mask = 0xFF;
3177         data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
3178         data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
3179         data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3180         data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3181         data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3182         data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3183         data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3184         data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3185         data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3186         data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3187
3188         data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
3189         data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
3190         data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
3191         data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
3192         data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
3193         data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
3194         data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
3195         data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
3196
3197         data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
3198
3199         data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
3200
3201         /* need to set voltage control types before EVV patching */
3202         data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3203         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3204         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3205
3206         data->enable_tdc_limit_feature = true;
3207         data->enable_pkg_pwr_tracking_feature = true;
3208         data->force_pcie_gen = PP_PCIEGenInvalid;
3209         data->mclk_stutter_mode_threshold = 40000;
3210
3211         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3212                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
3213                 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3214
3215         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3216                         PHM_PlatformCaps_EnableMVDDControl)) {
3217                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3218                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
3219                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
3220                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3221                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
3222                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3223         }
3224
3225         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3226                         PHM_PlatformCaps_ControlVDDCI)) {
3227                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3228                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
3229                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
3230                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3231                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
3232                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3233         }
3234
3235         if (table_info->cac_dtp_table->usClockStretchAmount != 0)
3236                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3237                                         PHM_PlatformCaps_ClockStretcher);
3238
3239         polaris10_set_features_platform_caps(hwmgr);
3240
3241         polaris10_patch_voltage_workaround(hwmgr);
3242         polaris10_init_dpm_defaults(hwmgr);
3243
3244         /* Get leakage voltage based on leakage ID. */
3245         result = polaris10_get_evv_voltages(hwmgr);
3246
3247         if (result) {
3248                 printk("Get EVV Voltage Failed.  Abort Driver loading!\n");
3249                 return -1;
3250         }
3251
3252         polaris10_complete_dependency_tables(hwmgr);
3253         polaris10_set_private_data_based_on_pptable(hwmgr);
3254
3255         /* Initalize Dynamic State Adjustment Rule Settings */
3256         result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
3257
3258         if (0 == result) {
3259                 struct cgs_system_info sys_info = {0};
3260
3261                 data->is_tlu_enabled = 0;
3262
3263                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
3264                                                         POLARIS10_MAX_HARDWARE_POWERLEVELS;
3265                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3266                 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
3267
3268
3269                 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
3270                         temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
3271                         switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
3272                         case 0:
3273                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3274                                 break;
3275                         case 1:
3276                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3277                                 break;
3278                         case 2:
3279                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3280                                 break;
3281                         case 3:
3282                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3283                                 break;
3284                         case 4:
3285                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3286                                 break;
3287                         default:
3288                                 PP_ASSERT_WITH_CODE(0,
3289                                 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3290                                 );
3291                                 break;
3292                         }
3293                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3294                 }
3295
3296                 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
3297                         hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
3298                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
3299                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3300
3301                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
3302                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3303
3304                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
3305
3306                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
3307
3308                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
3309                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3310
3311                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
3312
3313                         table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
3314                                                                         (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
3315
3316                         table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3317                         table_info->cac_dtp_table->usOperatingTempStep = 1;
3318                         table_info->cac_dtp_table->usOperatingTempHyst = 1;
3319
3320                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
3321                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3322
3323                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
3324                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
3325
3326                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
3327                                        table_info->cac_dtp_table->usOperatingTempMinLimit;
3328
3329                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
3330                                        table_info->cac_dtp_table->usOperatingTempMaxLimit;
3331
3332                         hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
3333                                        table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3334
3335                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
3336                                        table_info->cac_dtp_table->usOperatingTempStep;
3337
3338                         hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
3339                                        table_info->cac_dtp_table->usTargetOperatingTemp;
3340                 }
3341
3342                 sys_info.size = sizeof(struct cgs_system_info);
3343                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3344                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3345                 if (result)
3346                         data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3347                 else
3348                         data->pcie_gen_cap = (uint32_t)sys_info.value;
3349                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3350                         data->pcie_spc_cap = 20;
3351                 sys_info.size = sizeof(struct cgs_system_info);
3352                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3353                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3354                 if (result)
3355                         data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3356                 else
3357                         data->pcie_lane_cap = (uint32_t)sys_info.value;
3358
3359                 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3360 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3361                 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3362                 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
3363         } else {
3364                 /* Ignore return value in here, we are cleaning up a mess. */
3365                 polaris10_hwmgr_backend_fini(hwmgr);
3366         }
3367
3368         return 0;
3369 }
3370
3371 static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3372 {
3373         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3374         uint32_t level, tmp;
3375
3376         if (!data->pcie_dpm_key_disabled) {
3377                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3378                         level = 0;
3379                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3380                         while (tmp >>= 1)
3381                                 level++;
3382
3383                         if (level)
3384                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3385                                                 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3386                 }
3387         }
3388
3389         if (!data->sclk_dpm_key_disabled) {
3390                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3391                         level = 0;
3392                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3393                         while (tmp >>= 1)
3394                                 level++;
3395
3396                         if (level)
3397                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3398                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3399                                                 (1 << level));
3400                 }
3401         }
3402
3403         if (!data->mclk_dpm_key_disabled) {
3404                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3405                         level = 0;
3406                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3407                         while (tmp >>= 1)
3408                                 level++;
3409
3410                         if (level)
3411                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3412                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3413                                                 (1 << level));
3414                 }
3415         }
3416
3417         return 0;
3418 }
3419
3420 static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3421 {
3422         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3423
3424         phm_apply_dal_min_voltage_request(hwmgr);
3425
3426         if (!data->sclk_dpm_key_disabled) {
3427                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3428                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3429                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
3430                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3431         }
3432
3433         if (!data->mclk_dpm_key_disabled) {
3434                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3435                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3436                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
3437                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3438         }
3439
3440         return 0;
3441 }
3442
3443 static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3444 {
3445         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3446
3447         if (!polaris10_is_dpm_running(hwmgr))
3448                 return -EINVAL;
3449
3450         if (!data->pcie_dpm_key_disabled) {
3451                 smum_send_msg_to_smc(hwmgr->smumgr,
3452                                 PPSMC_MSG_PCIeDPM_UnForceLevel);
3453         }
3454
3455         return polaris10_upload_dpm_level_enable_mask(hwmgr);
3456 }
3457
3458 static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3459 {
3460         struct polaris10_hwmgr *data =
3461                         (struct polaris10_hwmgr *)(hwmgr->backend);
3462         uint32_t level;
3463
3464         if (!data->sclk_dpm_key_disabled)
3465                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3466                         level = phm_get_lowest_enabled_level(hwmgr,
3467                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3468                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3469                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
3470                                                             (1 << level));
3471
3472         }
3473
3474         if (!data->mclk_dpm_key_disabled) {
3475                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3476                         level = phm_get_lowest_enabled_level(hwmgr,
3477                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3478                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3479                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
3480                                                             (1 << level));
3481                 }
3482         }
3483
3484         if (!data->pcie_dpm_key_disabled) {
3485                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3486                         level = phm_get_lowest_enabled_level(hwmgr,
3487                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3488                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3489                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
3490                                                             (level));
3491                 }
3492         }
3493
3494         return 0;
3495
3496 }
3497 static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
3498                                 enum amd_dpm_forced_level level)
3499 {
3500         int ret = 0;
3501
3502         switch (level) {
3503         case AMD_DPM_FORCED_LEVEL_HIGH:
3504                 ret = polaris10_force_dpm_highest(hwmgr);
3505                 if (ret)
3506                         return ret;
3507                 break;
3508         case AMD_DPM_FORCED_LEVEL_LOW:
3509                 ret = polaris10_force_dpm_lowest(hwmgr);
3510                 if (ret)
3511                         return ret;
3512                 break;
3513         case AMD_DPM_FORCED_LEVEL_AUTO:
3514                 ret = polaris10_unforce_dpm_levels(hwmgr);
3515                 if (ret)
3516                         return ret;
3517                 break;
3518         default:
3519                 break;
3520         }
3521
3522         hwmgr->dpm_level = level;
3523
3524         return ret;
3525 }
3526
3527 static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
3528 {
3529         return sizeof(struct polaris10_power_state);
3530 }
3531
3532
3533 static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3534                                 struct pp_power_state *request_ps,
3535                         const struct pp_power_state *current_ps)
3536 {
3537
3538         struct polaris10_power_state *polaris10_ps =
3539                                 cast_phw_polaris10_power_state(&request_ps->hardware);
3540         uint32_t sclk;
3541         uint32_t mclk;
3542         struct PP_Clocks minimum_clocks = {0};
3543         bool disable_mclk_switching;
3544         bool disable_mclk_switching_for_frame_lock;
3545         struct cgs_display_info info = {0};
3546         const struct phm_clock_and_voltage_limits *max_limits;
3547         uint32_t i;
3548         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3549         struct phm_ppt_v1_information *table_info =
3550                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3551         int32_t count;
3552         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3553
3554         data->battery_state = (PP_StateUILabel_Battery ==
3555                         request_ps->classification.ui_label);
3556
3557         PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
3558                                  "VI should always have 2 performance levels",
3559                                 );
3560
3561         max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3562                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3563                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3564
3565         /* Cap clock DPM tables at DC MAX if it is in DC. */
3566         if (PP_PowerSource_DC == hwmgr->power_source) {
3567                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3568                         if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3569                                 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3570                         if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3571                                 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
3572                 }
3573         }
3574
3575         polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3576         polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3577
3578         cgs_get_active_displays_info(hwmgr->device, &info);
3579
3580         /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3581
3582         /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3583
3584         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3585                         PHM_PlatformCaps_StablePState)) {
3586                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3587                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3588
3589                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3590                                 count >= 0; count--) {
3591                         if (stable_pstate_sclk >=
3592                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3593                                 stable_pstate_sclk =
3594                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3595                                 break;
3596                         }
3597                 }
3598
3599                 if (count < 0)
3600                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3601
3602                 stable_pstate_mclk = max_limits->mclk;
3603
3604                 minimum_clocks.engineClock = stable_pstate_sclk;
3605                 minimum_clocks.memoryClock = stable_pstate_mclk;
3606         }
3607
3608         if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3609                 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3610
3611         if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3612                 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3613
3614         polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3615
3616         if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3617                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3618                                 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3619                                 "Overdrive sclk exceeds limit",
3620                                 hwmgr->gfx_arbiter.sclk_over_drive =
3621                                                 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3622
3623                 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3624                         polaris10_ps->performance_levels[1].engine_clock =
3625                                         hwmgr->gfx_arbiter.sclk_over_drive;
3626         }
3627
3628         if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3629                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3630                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3631                                 "Overdrive mclk exceeds limit",
3632                                 hwmgr->gfx_arbiter.mclk_over_drive =
3633                                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3634
3635                 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3636                         polaris10_ps->performance_levels[1].memory_clock =
3637                                         hwmgr->gfx_arbiter.mclk_over_drive;
3638         }
3639
3640         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3641                                     hwmgr->platform_descriptor.platformCaps,
3642                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3643
3644         disable_mclk_switching = (1 < info.display_count) ||
3645                                     disable_mclk_switching_for_frame_lock;
3646
3647         sclk = polaris10_ps->performance_levels[0].engine_clock;
3648         mclk = polaris10_ps->performance_levels[0].memory_clock;
3649
3650         if (disable_mclk_switching)
3651                 mclk = polaris10_ps->performance_levels
3652                 [polaris10_ps->performance_level_count - 1].memory_clock;
3653
3654         if (sclk < minimum_clocks.engineClock)
3655                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3656                                 max_limits->sclk : minimum_clocks.engineClock;
3657
3658         if (mclk < minimum_clocks.memoryClock)
3659                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3660                                 max_limits->mclk : minimum_clocks.memoryClock;
3661
3662         polaris10_ps->performance_levels[0].engine_clock = sclk;
3663         polaris10_ps->performance_levels[0].memory_clock = mclk;
3664
3665         polaris10_ps->performance_levels[1].engine_clock =
3666                 (polaris10_ps->performance_levels[1].engine_clock >=
3667                                 polaris10_ps->performance_levels[0].engine_clock) ?
3668                                                 polaris10_ps->performance_levels[1].engine_clock :
3669                                                 polaris10_ps->performance_levels[0].engine_clock;
3670
3671         if (disable_mclk_switching) {
3672                 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3673                         mclk = polaris10_ps->performance_levels[1].memory_clock;
3674
3675                 polaris10_ps->performance_levels[0].memory_clock = mclk;
3676                 polaris10_ps->performance_levels[1].memory_clock = mclk;
3677         } else {
3678                 if (polaris10_ps->performance_levels[1].memory_clock <
3679                                 polaris10_ps->performance_levels[0].memory_clock)
3680                         polaris10_ps->performance_levels[1].memory_clock =
3681                                         polaris10_ps->performance_levels[0].memory_clock;
3682         }
3683
3684         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3685                         PHM_PlatformCaps_StablePState)) {
3686                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3687                         polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3688                         polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3689                         polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3690                         polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3691                 }
3692         }
3693         return 0;
3694 }
3695
3696
3697 static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3698 {
3699         struct pp_power_state  *ps;
3700         struct polaris10_power_state  *polaris10_ps;
3701
3702         if (hwmgr == NULL)
3703                 return -EINVAL;
3704
3705         ps = hwmgr->request_ps;
3706
3707         if (ps == NULL)
3708                 return -EINVAL;
3709
3710         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3711
3712         if (low)
3713                 return polaris10_ps->performance_levels[0].memory_clock;
3714         else
3715                 return polaris10_ps->performance_levels
3716                                 [polaris10_ps->performance_level_count-1].memory_clock;
3717 }
3718
3719 static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3720 {
3721         struct pp_power_state  *ps;
3722         struct polaris10_power_state  *polaris10_ps;
3723
3724         if (hwmgr == NULL)
3725                 return -EINVAL;
3726
3727         ps = hwmgr->request_ps;
3728
3729         if (ps == NULL)
3730                 return -EINVAL;
3731
3732         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3733
3734         if (low)
3735                 return polaris10_ps->performance_levels[0].engine_clock;
3736         else
3737                 return polaris10_ps->performance_levels
3738                                 [polaris10_ps->performance_level_count-1].engine_clock;
3739 }
3740
3741 static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3742                                         struct pp_hw_power_state *hw_ps)
3743 {
3744         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3745         struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
3746         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3747         uint16_t size;
3748         uint8_t frev, crev;
3749         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3750
3751         /* First retrieve the Boot clocks and VDDC from the firmware info table.
3752          * We assume here that fw_info is unchanged if this call fails.
3753          */
3754         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3755                         hwmgr->device, index,
3756                         &size, &frev, &crev);
3757         if (!fw_info)
3758                 /* During a test, there is no firmware info table. */
3759                 return 0;
3760
3761         /* Patch the state. */
3762         data->vbios_boot_state.sclk_bootup_value =
3763                         le32_to_cpu(fw_info->ulDefaultEngineClock);
3764         data->vbios_boot_state.mclk_bootup_value =
3765                         le32_to_cpu(fw_info->ulDefaultMemoryClock);
3766         data->vbios_boot_state.mvdd_bootup_value =
3767                         le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3768         data->vbios_boot_state.vddc_bootup_value =
3769                         le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3770         data->vbios_boot_state.vddci_bootup_value =
3771                         le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3772         data->vbios_boot_state.pcie_gen_bootup_value =
3773                         phm_get_current_pcie_speed(hwmgr);
3774
3775         data->vbios_boot_state.pcie_lane_bootup_value =
3776                         (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3777
3778         /* set boot power state */
3779         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3780         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3781         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3782         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3783
3784         return 0;
3785 }
3786
3787 static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3788                 void *state, struct pp_power_state *power_state,
3789                 void *pp_table, uint32_t classification_flag)
3790 {
3791         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3792         struct polaris10_power_state  *polaris10_power_state =
3793                         (struct polaris10_power_state *)(&(power_state->hardware));
3794         struct polaris10_performance_level *performance_level;
3795         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3796         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3797                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3798         PPTable_Generic_SubTable_Header *sclk_dep_table =
3799                         (PPTable_Generic_SubTable_Header *)
3800                         (((unsigned long)powerplay_table) +
3801                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3802
3803         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3804                         (ATOM_Tonga_MCLK_Dependency_Table *)
3805                         (((unsigned long)powerplay_table) +
3806                                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3807
3808         /* The following fields are not initialized here: id orderedList allStatesList */
3809         power_state->classification.ui_label =
3810                         (le16_to_cpu(state_entry->usClassification) &
3811                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3812                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3813         power_state->classification.flags = classification_flag;
3814         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3815
3816         power_state->classification.temporary_state = false;
3817         power_state->classification.to_be_deleted = false;
3818
3819         power_state->validation.disallowOnDC =
3820                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3821                                         ATOM_Tonga_DISALLOW_ON_DC));
3822
3823         power_state->pcie.lanes = 0;
3824
3825         power_state->display.disableFrameModulation = false;
3826         power_state->display.limitRefreshrate = false;
3827         power_state->display.enableVariBright =
3828                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3829                                         ATOM_Tonga_ENABLE_VARIBRIGHT));
3830
3831         power_state->validation.supportedPowerLevels = 0;
3832         power_state->uvd_clocks.VCLK = 0;
3833         power_state->uvd_clocks.DCLK = 0;
3834         power_state->temperatures.min = 0;
3835         power_state->temperatures.max = 0;
3836
3837         performance_level = &(polaris10_power_state->performance_levels
3838                         [polaris10_power_state->performance_level_count++]);
3839
3840         PP_ASSERT_WITH_CODE(
3841                         (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
3842                         "Performance levels exceeds SMC limit!",
3843                         return -1);
3844
3845         PP_ASSERT_WITH_CODE(
3846                         (polaris10_power_state->performance_level_count <=
3847                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3848                         "Performance levels exceeds Driver limit!",
3849                         return -1);
3850
3851         /* Performance levels are arranged from low to high. */
3852         performance_level->memory_clock = mclk_dep_table->entries
3853                         [state_entry->ucMemoryClockIndexLow].ulMclk;
3854         if (sclk_dep_table->ucRevId == 0)
3855                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3856                         [state_entry->ucEngineClockIndexLow].ulSclk;
3857         else if (sclk_dep_table->ucRevId == 1)
3858                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3859                         [state_entry->ucEngineClockIndexLow].ulSclk;
3860         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3861                         state_entry->ucPCIEGenLow);
3862         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3863                         state_entry->ucPCIELaneHigh);
3864
3865         performance_level = &(polaris10_power_state->performance_levels
3866                         [polaris10_power_state->performance_level_count++]);
3867         performance_level->memory_clock = mclk_dep_table->entries
3868                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
3869
3870         if (sclk_dep_table->ucRevId == 0)
3871                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3872                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3873         else if (sclk_dep_table->ucRevId == 1)
3874                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3875                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3876
3877         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3878                         state_entry->ucPCIEGenHigh);
3879         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3880                         state_entry->ucPCIELaneHigh);
3881
3882         return 0;
3883 }
3884
3885 static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3886                 unsigned long entry_index, struct pp_power_state *state)
3887 {
3888         int result;
3889         struct polaris10_power_state *ps;
3890         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3891         struct phm_ppt_v1_information *table_info =
3892                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3893         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3894                         table_info->vdd_dep_on_mclk;
3895
3896         state->hardware.magic = PHM_VIslands_Magic;
3897
3898         ps = (struct polaris10_power_state *)(&state->hardware);
3899
3900         result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3901                         polaris10_get_pp_table_entry_callback_func);
3902
3903         /* This is the earliest time we have all the dependency table and the VBIOS boot state
3904          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3905          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3906          */
3907         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3908                 if (dep_mclk_table->entries[0].clk !=
3909                                 data->vbios_boot_state.mclk_bootup_value)
3910                         printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3911                                         "does not match VBIOS boot MCLK level");
3912                 if (dep_mclk_table->entries[0].vddci !=
3913                                 data->vbios_boot_state.vddci_bootup_value)
3914                         printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3915                                         "does not match VBIOS boot VDDCI level");
3916         }
3917
3918         /* set DC compatible flag if this state supports DC */
3919         if (!state->validation.disallowOnDC)
3920                 ps->dc_compatible = true;
3921
3922         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3923                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3924
3925         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3926         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3927
3928         if (!result) {
3929                 uint32_t i;
3930
3931                 switch (state->classification.ui_label) {
3932                 case PP_StateUILabel_Performance:
3933                         data->use_pcie_performance_levels = true;
3934                         for (i = 0; i < ps->performance_level_count; i++) {
3935                                 if (data->pcie_gen_performance.max <
3936                                                 ps->performance_levels[i].pcie_gen)
3937                                         data->pcie_gen_performance.max =
3938                                                         ps->performance_levels[i].pcie_gen;
3939
3940                                 if (data->pcie_gen_performance.min >
3941                                                 ps->performance_levels[i].pcie_gen)
3942                                         data->pcie_gen_performance.min =
3943                                                         ps->performance_levels[i].pcie_gen;
3944
3945                                 if (data->pcie_lane_performance.max <
3946                                                 ps->performance_levels[i].pcie_lane)
3947                                         data->pcie_lane_performance.max =
3948                                                         ps->performance_levels[i].pcie_lane;
3949                                 if (data->pcie_lane_performance.min >
3950                                                 ps->performance_levels[i].pcie_lane)
3951                                         data->pcie_lane_performance.min =
3952                                                         ps->performance_levels[i].pcie_lane;
3953                         }
3954                         break;
3955                 case PP_StateUILabel_Battery:
3956                         data->use_pcie_power_saving_levels = true;
3957
3958                         for (i = 0; i < ps->performance_level_count; i++) {
3959                                 if (data->pcie_gen_power_saving.max <
3960                                                 ps->performance_levels[i].pcie_gen)
3961                                         data->pcie_gen_power_saving.max =
3962                                                         ps->performance_levels[i].pcie_gen;
3963
3964                                 if (data->pcie_gen_power_saving.min >
3965                                                 ps->performance_levels[i].pcie_gen)
3966                                         data->pcie_gen_power_saving.min =
3967                                                         ps->performance_levels[i].pcie_gen;
3968
3969                                 if (data->pcie_lane_power_saving.max <
3970                                                 ps->performance_levels[i].pcie_lane)
3971                                         data->pcie_lane_power_saving.max =
3972                                                         ps->performance_levels[i].pcie_lane;
3973
3974                                 if (data->pcie_lane_power_saving.min >
3975                                                 ps->performance_levels[i].pcie_lane)
3976                                         data->pcie_lane_power_saving.min =
3977                                                         ps->performance_levels[i].pcie_lane;
3978                         }
3979                         break;
3980                 default:
3981                         break;
3982                 }
3983         }
3984         return 0;
3985 }
3986
3987 static void
3988 polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
3989 {
3990         uint32_t sclk, mclk, activity_percent;
3991         uint32_t offset;
3992         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3993
3994         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3995
3996         sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3997
3998         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
3999
4000         mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4001         seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
4002                         mclk / 100, sclk / 100);
4003
4004         offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
4005         activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
4006         activity_percent += 0x80;
4007         activity_percent >>= 8;
4008
4009         seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
4010
4011         seq_printf(m, "uvd    %sabled\n", data->uvd_power_gated ? "dis" : "en");
4012
4013         seq_printf(m, "vce    %sabled\n", data->vce_power_gated ? "dis" : "en");
4014 }
4015
4016 static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
4017 {
4018         const struct phm_set_power_state_input *states =
4019                         (const struct phm_set_power_state_input *)input;
4020         const struct polaris10_power_state *polaris10_ps =
4021                         cast_const_phw_polaris10_power_state(states->pnew_state);
4022         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4023         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4024         uint32_t sclk = polaris10_ps->performance_levels
4025                         [polaris10_ps->performance_level_count - 1].engine_clock;
4026         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4027         uint32_t mclk = polaris10_ps->performance_levels
4028                         [polaris10_ps->performance_level_count - 1].memory_clock;
4029         struct PP_Clocks min_clocks = {0};
4030         uint32_t i;
4031         struct cgs_display_info info = {0};
4032
4033         data->need_update_smu7_dpm_table = 0;
4034
4035         for (i = 0; i < sclk_table->count; i++) {
4036                 if (sclk == sclk_table->dpm_levels[i].value)
4037                         break;
4038         }
4039
4040         if (i >= sclk_table->count)
4041                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4042         else {
4043         /* TODO: Check SCLK in DAL's minimum clocks
4044          * in case DeepSleep divider update is required.
4045          */
4046                 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
4047                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4048                                 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4049                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4050         }
4051
4052         for (i = 0; i < mclk_table->count; i++) {
4053                 if (mclk == mclk_table->dpm_levels[i].value)
4054                         break;
4055         }
4056
4057         if (i >= mclk_table->count)
4058                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4059
4060         cgs_get_active_displays_info(hwmgr->device, &info);
4061
4062         if (data->display_timing.num_existing_displays != info.display_count)
4063                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4064
4065         return 0;
4066 }
4067
4068 static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
4069                 const struct polaris10_power_state *polaris10_ps)
4070 {
4071         uint32_t i;
4072         uint32_t sclk, max_sclk = 0;
4073         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4074         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
4075
4076         for (i = 0; i < polaris10_ps->performance_level_count; i++) {
4077                 sclk = polaris10_ps->performance_levels[i].engine_clock;
4078                 if (max_sclk < sclk)
4079                         max_sclk = sclk;
4080         }
4081
4082         for (i = 0; i < dpm_table->sclk_table.count; i++) {
4083                 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
4084                         return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
4085                                         dpm_table->pcie_speed_table.dpm_levels
4086                                         [dpm_table->pcie_speed_table.count - 1].value :
4087                                         dpm_table->pcie_speed_table.dpm_levels[i].value);
4088         }
4089
4090         return 0;
4091 }
4092
4093 static int polaris10_request_link_speed_change_before_state_change(
4094                 struct pp_hwmgr *hwmgr, const void *input)
4095 {
4096         const struct phm_set_power_state_input *states =
4097                         (const struct phm_set_power_state_input *)input;
4098         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4099         const struct polaris10_power_state *polaris10_nps =
4100                         cast_const_phw_polaris10_power_state(states->pnew_state);
4101         const struct polaris10_power_state *polaris10_cps =
4102                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
4103
4104         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
4105         uint16_t current_link_speed;
4106
4107         if (data->force_pcie_gen == PP_PCIEGenInvalid)
4108                 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
4109         else
4110                 current_link_speed = data->force_pcie_gen;
4111
4112         data->force_pcie_gen = PP_PCIEGenInvalid;
4113         data->pspp_notify_required = false;
4114
4115         if (target_link_speed > current_link_speed) {
4116                 switch (target_link_speed) {
4117                 case PP_PCIEGen3:
4118                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
4119                                 break;
4120                         data->force_pcie_gen = PP_PCIEGen2;
4121                         if (current_link_speed == PP_PCIEGen2)
4122                                 break;
4123                 case PP_PCIEGen2:
4124                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
4125                                 break;
4126                 default:
4127                         data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
4128                         break;
4129                 }
4130         } else {
4131                 if (target_link_speed < current_link_speed)
4132                         data->pspp_notify_required = true;
4133         }
4134
4135         return 0;
4136 }
4137
4138 static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4139 {
4140         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4141
4142         if (0 == data->need_update_smu7_dpm_table)
4143                 return 0;
4144
4145         if ((0 == data->sclk_dpm_key_disabled) &&
4146                 (data->need_update_smu7_dpm_table &
4147                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4148                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4149                                 "Trying to freeze SCLK DPM when DPM is disabled",
4150                                 );
4151                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4152                                 PPSMC_MSG_SCLKDPM_FreezeLevel),
4153                                 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4154                                 return -1);
4155         }
4156
4157         if ((0 == data->mclk_dpm_key_disabled) &&
4158                 (data->need_update_smu7_dpm_table &
4159                  DPMTABLE_OD_UPDATE_MCLK)) {
4160                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4161                                 "Trying to freeze MCLK DPM when DPM is disabled",
4162                                 );
4163                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4164                                 PPSMC_MSG_MCLKDPM_FreezeLevel),
4165                                 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4166                                 return -1);
4167         }
4168
4169         return 0;
4170 }
4171
4172 static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
4173                 struct pp_hwmgr *hwmgr, const void *input)
4174 {
4175         int result = 0;
4176         const struct phm_set_power_state_input *states =
4177                         (const struct phm_set_power_state_input *)input;
4178         const struct polaris10_power_state *polaris10_ps =
4179                         cast_const_phw_polaris10_power_state(states->pnew_state);
4180         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4181         uint32_t sclk = polaris10_ps->performance_levels
4182                         [polaris10_ps->performance_level_count - 1].engine_clock;
4183         uint32_t mclk = polaris10_ps->performance_levels
4184                         [polaris10_ps->performance_level_count - 1].memory_clock;
4185         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
4186
4187         struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
4188         uint32_t dpm_count, clock_percent;
4189         uint32_t i;
4190
4191         if (0 == data->need_update_smu7_dpm_table)
4192                 return 0;
4193
4194         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4195                 dpm_table->sclk_table.dpm_levels
4196                 [dpm_table->sclk_table.count - 1].value = sclk;
4197
4198                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4199                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4200                 /* Need to do calculation based on the golden DPM table
4201                  * as the Heatmap GPU Clock axis is also based on the default values
4202                  */
4203                         PP_ASSERT_WITH_CODE(
4204                                 (golden_dpm_table->sclk_table.dpm_levels
4205                                                 [golden_dpm_table->sclk_table.count - 1].value != 0),
4206                                 "Divide by 0!",
4207                                 return -1);
4208                         dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
4209
4210                         for (i = dpm_count; i > 1; i--) {
4211                                 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
4212                                         clock_percent =
4213                                               ((sclk
4214                                                 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
4215                                                 ) * 100)
4216                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4217
4218                                         dpm_table->sclk_table.dpm_levels[i].value =
4219                                                         golden_dpm_table->sclk_table.dpm_levels[i].value +
4220                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
4221                                                                 clock_percent)/100;
4222
4223                                 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
4224                                         clock_percent =
4225                                                 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
4226                                                 - sclk) * 100)
4227                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4228
4229                                         dpm_table->sclk_table.dpm_levels[i].value =
4230                                                         golden_dpm_table->sclk_table.dpm_levels[i].value -
4231                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
4232                                                                         clock_percent) / 100;
4233                                 } else
4234                                         dpm_table->sclk_table.dpm_levels[i].value =
4235                                                         golden_dpm_table->sclk_table.dpm_levels[i].value;
4236                         }
4237                 }
4238         }
4239
4240         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4241                 dpm_table->mclk_table.dpm_levels
4242                         [dpm_table->mclk_table.count - 1].value = mclk;
4243
4244                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4245                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4246
4247                         PP_ASSERT_WITH_CODE(
4248                                         (golden_dpm_table->mclk_table.dpm_levels
4249                                                 [golden_dpm_table->mclk_table.count-1].value != 0),
4250                                         "Divide by 0!",
4251                                         return -1);
4252                         dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
4253                         for (i = dpm_count; i > 1; i--) {
4254                                 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
4255                                         clock_percent = ((mclk -
4256                                         golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
4257                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4258
4259                                         dpm_table->mclk_table.dpm_levels[i].value =
4260                                                         golden_dpm_table->mclk_table.dpm_levels[i].value +
4261                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4262                                                         clock_percent) / 100;
4263
4264                                 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
4265                                         clock_percent = (
4266                                          (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
4267                                         * 100)
4268                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4269
4270                                         dpm_table->mclk_table.dpm_levels[i].value =
4271                                                         golden_dpm_table->mclk_table.dpm_levels[i].value -
4272                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4273                                                                         clock_percent) / 100;
4274                                 } else
4275                                         dpm_table->mclk_table.dpm_levels[i].value =
4276                                                         golden_dpm_table->mclk_table.dpm_levels[i].value;
4277                         }
4278                 }
4279         }
4280
4281         if (data->need_update_smu7_dpm_table &
4282                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4283                 result = polaris10_populate_all_graphic_levels(hwmgr);
4284                 PP_ASSERT_WITH_CODE((0 == result),
4285                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4286                                 return result);
4287         }
4288
4289         if (data->need_update_smu7_dpm_table &
4290                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4291                 /*populate MCLK dpm table to SMU7 */
4292                 result = polaris10_populate_all_memory_levels(hwmgr);
4293                 PP_ASSERT_WITH_CODE((0 == result),
4294                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4295                                 return result);
4296         }
4297
4298         return result;
4299 }
4300
4301 static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4302                           struct polaris10_single_dpm_table *dpm_table,
4303                         uint32_t low_limit, uint32_t high_limit)
4304 {
4305         uint32_t i;
4306
4307         for (i = 0; i < dpm_table->count; i++) {
4308                 if ((dpm_table->dpm_levels[i].value < low_limit)
4309                 || (dpm_table->dpm_levels[i].value > high_limit))
4310                         dpm_table->dpm_levels[i].enabled = false;
4311                 else
4312                         dpm_table->dpm_levels[i].enabled = true;
4313         }
4314
4315         return 0;
4316 }
4317
4318 static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
4319                 const struct polaris10_power_state *polaris10_ps)
4320 {
4321         int result = 0;
4322         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4323         uint32_t high_limit_count;
4324
4325         PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
4326                         "power state did not have any performance level",
4327                         return -1);
4328
4329         high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
4330
4331         polaris10_trim_single_dpm_states(hwmgr,
4332                         &(data->dpm_table.sclk_table),
4333                         polaris10_ps->performance_levels[0].engine_clock,
4334                         polaris10_ps->performance_levels[high_limit_count].engine_clock);
4335
4336         polaris10_trim_single_dpm_states(hwmgr,
4337                         &(data->dpm_table.mclk_table),
4338                         polaris10_ps->performance_levels[0].memory_clock,
4339                         polaris10_ps->performance_levels[high_limit_count].memory_clock);
4340
4341         return result;
4342 }
4343
4344 static int polaris10_generate_dpm_level_enable_mask(
4345                 struct pp_hwmgr *hwmgr, const void *input)
4346 {
4347         int result;
4348         const struct phm_set_power_state_input *states =
4349                         (const struct phm_set_power_state_input *)input;
4350         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4351         const struct polaris10_power_state *polaris10_ps =
4352                         cast_const_phw_polaris10_power_state(states->pnew_state);
4353
4354         result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
4355         if (result)
4356                 return result;
4357
4358         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4359                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4360         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4361                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4362         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4363                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4364
4365         return 0;
4366 }
4367
4368 int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4369 {
4370         return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4371                         PPSMC_MSG_UVDDPM_Enable :
4372                         PPSMC_MSG_UVDDPM_Disable);
4373 }
4374
4375 int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4376 {
4377         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4378                         PPSMC_MSG_VCEDPM_Enable :
4379                         PPSMC_MSG_VCEDPM_Disable);
4380 }
4381
4382 int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4383 {
4384         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4385                         PPSMC_MSG_SAMUDPM_Enable :
4386                         PPSMC_MSG_SAMUDPM_Disable);
4387 }
4388
4389 int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4390 {
4391         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4392         uint32_t mm_boot_level_offset, mm_boot_level_value;
4393         struct phm_ppt_v1_information *table_info =
4394                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4395
4396         if (!bgate) {
4397                 data->smc_state_table.UvdBootLevel = 0;
4398                 if (table_info->mm_dep_table->count > 0)
4399                         data->smc_state_table.UvdBootLevel =
4400                                         (uint8_t) (table_info->mm_dep_table->count - 1);
4401                 mm_boot_level_offset = data->dpm_table_start +
4402                                 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4403                 mm_boot_level_offset /= 4;
4404                 mm_boot_level_offset *= 4;
4405                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4406                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4407                 mm_boot_level_value &= 0x00FFFFFF;
4408                 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4409                 cgs_write_ind_register(hwmgr->device,
4410                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4411
4412                 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4413                                 PHM_PlatformCaps_UVDDPM) ||
4414                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4415                                 PHM_PlatformCaps_StablePState))
4416                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4417                                         PPSMC_MSG_UVDDPM_SetEnabledMask,
4418                                         (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4419         }
4420
4421         return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
4422 }
4423
4424 static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4425 {
4426         const struct phm_set_power_state_input *states =
4427                         (const struct phm_set_power_state_input *)input;
4428         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4429         const struct polaris10_power_state *polaris10_nps =
4430                         cast_const_phw_polaris10_power_state(states->pnew_state);
4431         const struct polaris10_power_state *polaris10_cps =
4432                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
4433
4434         uint32_t mm_boot_level_offset, mm_boot_level_value;
4435         struct phm_ppt_v1_information *table_info =
4436                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4437
4438         if (polaris10_nps->vce_clks.evclk > 0 &&
4439         (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
4440
4441                 data->smc_state_table.VceBootLevel =
4442                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4443
4444                 mm_boot_level_offset = data->dpm_table_start +
4445                                 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4446                 mm_boot_level_offset /= 4;
4447                 mm_boot_level_offset *= 4;
4448                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4449                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4450                 mm_boot_level_value &= 0xFF00FFFF;
4451                 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4452                 cgs_write_ind_register(hwmgr->device,
4453                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4454
4455                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4456                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4457                                         PPSMC_MSG_VCEDPM_SetEnabledMask,
4458                                         (uint32_t)1 << data->smc_state_table.VceBootLevel);
4459
4460                         polaris10_enable_disable_vce_dpm(hwmgr, true);
4461                 } else if (polaris10_nps->vce_clks.evclk == 0 &&
4462                                 polaris10_cps != NULL &&
4463                                 polaris10_cps->vce_clks.evclk > 0)
4464                         polaris10_enable_disable_vce_dpm(hwmgr, false);
4465         }
4466
4467         return 0;
4468 }
4469
4470 int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4471 {
4472         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4473         uint32_t mm_boot_level_offset, mm_boot_level_value;
4474
4475         if (!bgate) {
4476                 data->smc_state_table.SamuBootLevel = 0;
4477                 mm_boot_level_offset = data->dpm_table_start +
4478                                 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4479                 mm_boot_level_offset /= 4;
4480                 mm_boot_level_offset *= 4;
4481                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4482                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4483                 mm_boot_level_value &= 0xFFFFFF00;
4484                 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4485                 cgs_write_ind_register(hwmgr->device,
4486                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4487
4488                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4489                                 PHM_PlatformCaps_StablePState))
4490                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4491                                         PPSMC_MSG_SAMUDPM_SetEnabledMask,
4492                                         (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4493         }
4494
4495         return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
4496 }
4497
4498 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4499 {
4500         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4501
4502         int result = 0;
4503         uint32_t low_sclk_interrupt_threshold = 0;
4504
4505         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4506                         PHM_PlatformCaps_SclkThrottleLowNotification)
4507                 && (hwmgr->gfx_arbiter.sclk_threshold !=
4508                                 data->low_sclk_interrupt_threshold)) {
4509                 data->low_sclk_interrupt_threshold =
4510                                 hwmgr->gfx_arbiter.sclk_threshold;
4511                 low_sclk_interrupt_threshold =
4512                                 data->low_sclk_interrupt_threshold;
4513
4514                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4515
4516                 result = polaris10_copy_bytes_to_smc(
4517                                 hwmgr->smumgr,
4518                                 data->dpm_table_start +
4519                                 offsetof(SMU74_Discrete_DpmTable,
4520                                         LowSclkInterruptThreshold),
4521                                 (uint8_t *)&low_sclk_interrupt_threshold,
4522                                 sizeof(uint32_t),
4523                                 data->sram_end);
4524         }
4525
4526         return result;
4527 }
4528
4529 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4530 {
4531         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4532
4533         if (data->need_update_smu7_dpm_table &
4534                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4535                 return polaris10_program_memory_timing_parameters(hwmgr);
4536
4537         return 0;
4538 }
4539
4540 static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4541 {
4542         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4543
4544         if (0 == data->need_update_smu7_dpm_table)
4545                 return 0;
4546
4547         if ((0 == data->sclk_dpm_key_disabled) &&
4548                 (data->need_update_smu7_dpm_table &
4549                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4550
4551                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4552                                 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4553                                 );
4554                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4555                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4556                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4557                         return -1);
4558         }
4559
4560         if ((0 == data->mclk_dpm_key_disabled) &&
4561                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4562
4563                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4564                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4565                                 );
4566                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4567                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4568                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4569                     return -1);
4570         }
4571
4572         data->need_update_smu7_dpm_table = 0;
4573
4574         return 0;
4575 }
4576
4577 static int polaris10_notify_link_speed_change_after_state_change(
4578                 struct pp_hwmgr *hwmgr, const void *input)
4579 {
4580         const struct phm_set_power_state_input *states =
4581                         (const struct phm_set_power_state_input *)input;
4582         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4583         const struct polaris10_power_state *polaris10_ps =
4584                         cast_const_phw_polaris10_power_state(states->pnew_state);
4585         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
4586         uint8_t  request;
4587
4588         if (data->pspp_notify_required) {
4589                 if (target_link_speed == PP_PCIEGen3)
4590                         request = PCIE_PERF_REQ_GEN3;
4591                 else if (target_link_speed == PP_PCIEGen2)
4592                         request = PCIE_PERF_REQ_GEN2;
4593                 else
4594                         request = PCIE_PERF_REQ_GEN1;
4595
4596                 if (request == PCIE_PERF_REQ_GEN1 &&
4597                                 phm_get_current_pcie_speed(hwmgr) > 0)
4598                         return 0;
4599
4600                 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4601                         if (PP_PCIEGen2 == target_link_speed)
4602                                 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4603                         else
4604                                 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4605                 }
4606         }
4607
4608         return 0;
4609 }
4610
4611 static int polaris10_notify_smc_display(struct pp_hwmgr *hwmgr)
4612 {
4613         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4614
4615         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4616                 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2);
4617         return (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ?  0 : -EINVAL;
4618 }
4619
4620 static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4621 {
4622         int tmp_result, result = 0;
4623         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4624
4625         tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4626         PP_ASSERT_WITH_CODE((0 == tmp_result),
4627                         "Failed to find DPM states clocks in DPM table!",
4628                         result = tmp_result);
4629
4630         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4631                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4632                 tmp_result =
4633                         polaris10_request_link_speed_change_before_state_change(hwmgr, input);
4634                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4635                                 "Failed to request link speed change before state change!",
4636                                 result = tmp_result);
4637         }
4638
4639         tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
4640         PP_ASSERT_WITH_CODE((0 == tmp_result),
4641                         "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4642
4643         tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4644         PP_ASSERT_WITH_CODE((0 == tmp_result),
4645                         "Failed to populate and upload SCLK MCLK DPM levels!",
4646                         result = tmp_result);
4647
4648         tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
4649         PP_ASSERT_WITH_CODE((0 == tmp_result),
4650                         "Failed to generate DPM level enabled mask!",
4651                         result = tmp_result);
4652
4653         tmp_result = polaris10_update_vce_dpm(hwmgr, input);
4654         PP_ASSERT_WITH_CODE((0 == tmp_result),
4655                         "Failed to update VCE DPM!",
4656                         result = tmp_result);
4657
4658         tmp_result = polaris10_update_sclk_threshold(hwmgr);
4659         PP_ASSERT_WITH_CODE((0 == tmp_result),
4660                         "Failed to update SCLK threshold!",
4661                         result = tmp_result);
4662
4663         tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
4664         PP_ASSERT_WITH_CODE((0 == tmp_result),
4665                         "Failed to program memory timing parameters!",
4666                         result = tmp_result);
4667
4668         tmp_result = polaris10_notify_smc_display(hwmgr);
4669         PP_ASSERT_WITH_CODE((0 == tmp_result),
4670                         "Failed to notify smc display settings!",
4671                         result = tmp_result);
4672
4673         tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
4674         PP_ASSERT_WITH_CODE((0 == tmp_result),
4675                         "Failed to unfreeze SCLK MCLK DPM!",
4676                         result = tmp_result);
4677
4678         tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
4679         PP_ASSERT_WITH_CODE((0 == tmp_result),
4680                         "Failed to upload DPM level enabled mask!",
4681                         result = tmp_result);
4682
4683         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4684                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4685                 tmp_result =
4686                         polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
4687                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4688                                 "Failed to notify link speed change after state change!",
4689                                 result = tmp_result);
4690         }
4691         data->apply_optimized_settings = false;
4692         return result;
4693 }
4694
4695 static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4696 {
4697         hwmgr->thermal_controller.
4698         advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4699
4700         if (phm_is_hw_access_blocked(hwmgr))
4701                 return 0;
4702
4703         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4704                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4705 }
4706
4707
4708 int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4709 {
4710         PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4711
4712         return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
4713 }
4714
4715 int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4716 {
4717         uint32_t num_active_displays = 0;
4718         struct cgs_display_info info = {0};
4719         info.mode_info = NULL;
4720
4721         cgs_get_active_displays_info(hwmgr->device, &info);
4722
4723         num_active_displays = info.display_count;
4724
4725         if (num_active_displays > 1)  /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
4726                 polaris10_notify_smc_display_change(hwmgr, false);
4727
4728         return 0;
4729 }
4730
4731 /**
4732 * Programs the display gap
4733 *
4734 * @param    hwmgr  the address of the powerplay hardware manager.
4735 * @return   always OK
4736 */
4737 int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
4738 {
4739         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4740         uint32_t num_active_displays = 0;
4741         uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4742         uint32_t display_gap2;
4743         uint32_t pre_vbi_time_in_us;
4744         uint32_t frame_time_in_us;
4745         uint32_t ref_clock;
4746         uint32_t refresh_rate = 0;
4747         struct cgs_display_info info = {0};
4748         struct cgs_mode_info mode_info;
4749
4750         info.mode_info = &mode_info;
4751
4752         cgs_get_active_displays_info(hwmgr->device, &info);
4753         num_active_displays = info.display_count;
4754
4755         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4756         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4757
4758         ref_clock = mode_info.ref_clock;
4759         refresh_rate = mode_info.refresh_rate;
4760
4761         if (0 == refresh_rate)
4762                 refresh_rate = 60;
4763
4764         frame_time_in_us = 1000000 / refresh_rate;
4765
4766         pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4767         data->frame_time_x2 = frame_time_in_us * 2 / 100;
4768
4769         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4770
4771         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4772
4773         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4774
4775         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4776
4777         return 0;
4778 }
4779
4780
4781 int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4782 {
4783         return polaris10_program_display_gap(hwmgr);
4784 }
4785
4786 /**
4787 *  Set maximum target operating fan output RPM
4788 *
4789 * @param    hwmgr:  the address of the powerplay hardware manager.
4790 * @param    usMaxFanRpm:  max operating fan RPM value.
4791 * @return   The response that came from the SMC.
4792 */
4793 static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4794 {
4795         hwmgr->thermal_controller.
4796         advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4797
4798         if (phm_is_hw_access_blocked(hwmgr))
4799                 return 0;
4800
4801         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4802                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4803 }
4804
4805 int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
4806                                         const void *thermal_interrupt_info)
4807 {
4808         return 0;
4809 }
4810
4811 bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4812 {
4813         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4814         bool is_update_required = false;
4815         struct cgs_display_info info = {0, 0, NULL};
4816
4817         cgs_get_active_displays_info(hwmgr->device, &info);
4818
4819         if (data->display_timing.num_existing_displays != info.display_count)
4820                 is_update_required = true;
4821 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4822         if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4823                 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
4824                 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4825                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4826                                 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4827                         is_update_required = true;
4828 */
4829         return is_update_required;
4830 }
4831
4832 static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4833                                                            const struct polaris10_performance_level *pl2)
4834 {
4835         return ((pl1->memory_clock == pl2->memory_clock) &&
4836                   (pl1->engine_clock == pl2->engine_clock) &&
4837                   (pl1->pcie_gen == pl2->pcie_gen) &&
4838                   (pl1->pcie_lane == pl2->pcie_lane));
4839 }
4840
4841 int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
4842 {
4843         const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4844         const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
4845         int i;
4846
4847         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4848                 return -EINVAL;
4849
4850         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4851         if (psa->performance_level_count != psb->performance_level_count) {
4852                 *equal = false;
4853                 return 0;
4854         }
4855
4856         for (i = 0; i < psa->performance_level_count; i++) {
4857                 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4858                         /* If we have found even one performance level pair that is different the states are different. */
4859                         *equal = false;
4860                         return 0;
4861                 }
4862         }
4863
4864         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4865         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4866         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4867         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4868
4869         return 0;
4870 }
4871
4872 int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
4873 {
4874         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4875
4876         uint32_t vbios_version;
4877
4878         /*  Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4879
4880         phm_get_mc_microcode_version(hwmgr);
4881         vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4882         /*  Full version of MC ucode has already been loaded. */
4883         if (vbios_version == 0) {
4884                 data->need_long_memory_training = false;
4885                 return 0;
4886         }
4887
4888         data->need_long_memory_training = false;
4889
4890 /*
4891  *      PPMCME_FirmwareDescriptorEntry *pfd = NULL;
4892         pfd = &tonga_mcmeFirmware;
4893         if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
4894                 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
4895                                         pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4896                                         pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4897 */
4898         return 0;
4899 }
4900
4901 /**
4902  * Read clock related registers.
4903  *
4904  * @param    hwmgr  the address of the powerplay hardware manager.
4905  * @return   always 0
4906  */
4907 static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
4908 {
4909         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4910
4911         data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4912                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4913                                                 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4914
4915         data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4916                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4917                                                 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4918
4919         data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4920                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4921                                                 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4922
4923         return 0;
4924 }
4925
4926 /**
4927  * Find out if memory is GDDR5.
4928  *
4929  * @param    hwmgr  the address of the powerplay hardware manager.
4930  * @return   always 0
4931  */
4932 static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
4933 {
4934         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4935         uint32_t temp;
4936
4937         temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4938
4939         data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4940                         ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4941                          MC_SEQ_MISC0_GDDR5_SHIFT));
4942
4943         return 0;
4944 }
4945
4946 /**
4947  * Enables Dynamic Power Management by SMC
4948  *
4949  * @param    hwmgr  the address of the powerplay hardware manager.
4950  * @return   always 0
4951  */
4952 static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4953 {
4954         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4955                         GENERAL_PWRMGT, STATIC_PM_EN, 1);
4956
4957         return 0;
4958 }
4959
4960 /**
4961  * Initialize PowerGating States for different engines
4962  *
4963  * @param    hwmgr  the address of the powerplay hardware manager.
4964  * @return   always 0
4965  */
4966 static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
4967 {
4968         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4969
4970         data->uvd_power_gated = false;
4971         data->vce_power_gated = false;
4972         data->samu_power_gated = false;
4973
4974         return 0;
4975 }
4976
4977 static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4978 {
4979         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4980         data->low_sclk_interrupt_threshold = 0;
4981
4982         return 0;
4983 }
4984
4985 int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
4986 {
4987         int tmp_result, result = 0;
4988
4989         polaris10_upload_mc_firmware(hwmgr);
4990
4991         tmp_result = polaris10_read_clock_registers(hwmgr);
4992         PP_ASSERT_WITH_CODE((0 == tmp_result),
4993                         "Failed to read clock registers!", result = tmp_result);
4994
4995         tmp_result = polaris10_get_memory_type(hwmgr);
4996         PP_ASSERT_WITH_CODE((0 == tmp_result),
4997                         "Failed to get memory type!", result = tmp_result);
4998
4999         tmp_result = polaris10_enable_acpi_power_management(hwmgr);
5000         PP_ASSERT_WITH_CODE((0 == tmp_result),
5001                         "Failed to enable ACPI power management!", result = tmp_result);
5002
5003         tmp_result = polaris10_init_power_gate_state(hwmgr);
5004         PP_ASSERT_WITH_CODE((0 == tmp_result),
5005                         "Failed to init power gate state!", result = tmp_result);
5006
5007         tmp_result = phm_get_mc_microcode_version(hwmgr);
5008         PP_ASSERT_WITH_CODE((0 == tmp_result),
5009                         "Failed to get MC microcode version!", result = tmp_result);
5010
5011         tmp_result = polaris10_init_sclk_threshold(hwmgr);
5012         PP_ASSERT_WITH_CODE((0 == tmp_result),
5013                         "Failed to init sclk threshold!", result = tmp_result);
5014
5015         return result;
5016 }
5017
5018 static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
5019                 enum pp_clock_type type, uint32_t mask)
5020 {
5021         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5022
5023         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
5024                 return -EINVAL;
5025
5026         switch (type) {
5027         case PP_SCLK:
5028                 if (!data->sclk_dpm_key_disabled)
5029                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5030                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
5031                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
5032                 break;
5033         case PP_MCLK:
5034                 if (!data->mclk_dpm_key_disabled)
5035                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5036                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
5037                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
5038                 break;
5039         case PP_PCIE:
5040         {
5041                 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
5042                 uint32_t level = 0;
5043
5044                 while (tmp >>= 1)
5045                         level++;
5046
5047                 if (!data->pcie_dpm_key_disabled)
5048                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5049                                         PPSMC_MSG_PCIeDPM_ForceLevel,
5050                                         level);
5051                 break;
5052         }
5053         default:
5054                 break;
5055         }
5056
5057         return 0;
5058 }
5059
5060 static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
5061 {
5062         uint32_t speedCntl = 0;
5063
5064         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
5065         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
5066                         ixPCIE_LC_SPEED_CNTL);
5067         return((uint16_t)PHM_GET_FIELD(speedCntl,
5068                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
5069 }
5070
5071 static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
5072                 enum pp_clock_type type, char *buf)
5073 {
5074         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5075         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5076         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5077         struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
5078         int i, now, size = 0;
5079         uint32_t clock, pcie_speed;
5080
5081         switch (type) {
5082         case PP_SCLK:
5083                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
5084                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5085
5086                 for (i = 0; i < sclk_table->count; i++) {
5087                         if (clock > sclk_table->dpm_levels[i].value)
5088                                 continue;
5089                         break;
5090                 }
5091                 now = i;
5092
5093                 for (i = 0; i < sclk_table->count; i++)
5094                         size += sprintf(buf + size, "%d: %uMhz %s\n",
5095                                         i, sclk_table->dpm_levels[i].value / 100,
5096                                         (i == now) ? "*" : "");
5097                 break;
5098         case PP_MCLK:
5099                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
5100                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5101
5102                 for (i = 0; i < mclk_table->count; i++) {
5103                         if (clock > mclk_table->dpm_levels[i].value)
5104                                 continue;
5105                         break;
5106                 }
5107                 now = i;
5108
5109                 for (i = 0; i < mclk_table->count; i++)
5110                         size += sprintf(buf + size, "%d: %uMhz %s\n",
5111                                         i, mclk_table->dpm_levels[i].value / 100,
5112                                         (i == now) ? "*" : "");
5113                 break;
5114         case PP_PCIE:
5115                 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
5116                 for (i = 0; i < pcie_table->count; i++) {
5117                         if (pcie_speed != pcie_table->dpm_levels[i].value)
5118                                 continue;
5119                         break;
5120                 }
5121                 now = i;
5122
5123                 for (i = 0; i < pcie_table->count; i++)
5124                         size += sprintf(buf + size, "%d: %s %s\n", i,
5125                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
5126                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
5127                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
5128                                         (i == now) ? "*" : "");
5129                 break;
5130         default:
5131                 break;
5132         }
5133         return size;
5134 }
5135
5136 static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
5137 {
5138         if (mode) {
5139                 /* stop auto-manage */
5140                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
5141                                 PHM_PlatformCaps_MicrocodeFanControl))
5142                         polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
5143                 polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
5144         } else
5145                 /* restart auto-manage */
5146                 polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
5147
5148         return 0;
5149 }
5150
5151 static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
5152 {
5153         if (hwmgr->fan_ctrl_is_in_default_mode)
5154                 return hwmgr->fan_ctrl_default_mode;
5155         else
5156                 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
5157                                 CG_FDO_CTRL2, FDO_PWM_MODE);
5158 }
5159
5160 static int polaris10_get_sclk_od(struct pp_hwmgr *hwmgr)
5161 {
5162         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5163         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5164         struct polaris10_single_dpm_table *golden_sclk_table =
5165                         &(data->golden_dpm_table.sclk_table);
5166         int value;
5167
5168         value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
5169                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
5170                         100 /
5171                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5172
5173         return value;
5174 }
5175
5176 static int polaris10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5177 {
5178         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5179         struct polaris10_single_dpm_table *golden_sclk_table =
5180                         &(data->golden_dpm_table.sclk_table);
5181         struct pp_power_state  *ps;
5182         struct polaris10_power_state  *polaris10_ps;
5183
5184         if (value > 20)
5185                 value = 20;
5186
5187         ps = hwmgr->request_ps;
5188
5189         if (ps == NULL)
5190                 return -EINVAL;
5191
5192         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
5193
5194         polaris10_ps->performance_levels[polaris10_ps->performance_level_count - 1].engine_clock =
5195                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
5196                         value / 100 +
5197                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5198
5199         return 0;
5200 }
5201
5202 static int polaris10_get_mclk_od(struct pp_hwmgr *hwmgr)
5203 {
5204         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5205         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5206         struct polaris10_single_dpm_table *golden_mclk_table =
5207                         &(data->golden_dpm_table.mclk_table);
5208         int value;
5209
5210         value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
5211                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
5212                         100 /
5213                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5214
5215         return value;
5216 }
5217
5218 static int polaris10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5219 {
5220         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5221         struct polaris10_single_dpm_table *golden_mclk_table =
5222                         &(data->golden_dpm_table.mclk_table);
5223         struct pp_power_state  *ps;
5224         struct polaris10_power_state  *polaris10_ps;
5225
5226         if (value > 20)
5227                 value = 20;
5228
5229         ps = hwmgr->request_ps;
5230
5231         if (ps == NULL)
5232                 return -EINVAL;
5233
5234         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
5235
5236         polaris10_ps->performance_levels[polaris10_ps->performance_level_count - 1].memory_clock =
5237                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
5238                         value / 100 +
5239                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5240
5241         return 0;
5242 }
5243 static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
5244         .backend_init = &polaris10_hwmgr_backend_init,
5245         .backend_fini = &polaris10_hwmgr_backend_fini,
5246         .asic_setup = &polaris10_setup_asic_task,
5247         .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
5248         .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
5249         .force_dpm_level = &polaris10_force_dpm_level,
5250         .power_state_set = polaris10_set_power_state_tasks,
5251         .get_power_state_size = polaris10_get_power_state_size,
5252         .get_mclk = polaris10_dpm_get_mclk,
5253         .get_sclk = polaris10_dpm_get_sclk,
5254         .patch_boot_state = polaris10_dpm_patch_boot_state,
5255         .get_pp_table_entry = polaris10_get_pp_table_entry,
5256         .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
5257         .print_current_perforce_level = polaris10_print_current_perforce_level,
5258         .powerdown_uvd = polaris10_phm_powerdown_uvd,
5259         .powergate_uvd = polaris10_phm_powergate_uvd,
5260         .powergate_vce = polaris10_phm_powergate_vce,
5261         .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
5262         .update_clock_gatings = polaris10_phm_update_clock_gatings,
5263         .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
5264         .display_config_changed = polaris10_display_configuration_changed_task,
5265         .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
5266         .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
5267         .get_temperature = polaris10_thermal_get_temperature,
5268         .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
5269         .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
5270         .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
5271         .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
5272         .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
5273         .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
5274         .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
5275         .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
5276         .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
5277         .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
5278         .check_states_equal = polaris10_check_states_equal,
5279         .set_fan_control_mode = polaris10_set_fan_control_mode,
5280         .get_fan_control_mode = polaris10_get_fan_control_mode,
5281         .force_clock_level = polaris10_force_clock_level,
5282         .print_clock_levels = polaris10_print_clock_levels,
5283         .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
5284         .get_sclk_od = polaris10_get_sclk_od,
5285         .set_sclk_od = polaris10_set_sclk_od,
5286         .get_mclk_od = polaris10_get_mclk_od,
5287         .set_mclk_od = polaris10_set_mclk_od,
5288 };
5289
5290 int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
5291 {
5292         hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
5293         hwmgr->pptable_func = &tonga_pptable_funcs;
5294         pp_polaris10_thermal_initialize(hwmgr);
5295
5296         return 0;
5297 }