2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/module.h>
24 #include <linux/slab.h>
26 #include <asm/div64.h>
27 #include "linux/delay.h"
30 #include "polaris10_hwmgr.h"
31 #include "polaris10_powertune.h"
32 #include "polaris10_dyn_defaults.h"
33 #include "polaris10_smumgr.h"
35 #include "ppatomctrl.h"
37 #include "tonga_pptable.h"
38 #include "pppcielanes.h"
39 #include "amd_pcie_helpers.h"
40 #include "hardwaremanager.h"
41 #include "tonga_processpptables.h"
42 #include "cgs_common.h"
44 #include "smu_ucode_xfer_vi.h"
45 #include "smu74_discrete.h"
46 #include "smu/smu_7_1_3_d.h"
47 #include "smu/smu_7_1_3_sh_mask.h"
48 #include "gmc/gmc_8_1_d.h"
49 #include "gmc/gmc_8_1_sh_mask.h"
50 #include "oss/oss_3_0_d.h"
51 #include "gca/gfx_8_0_d.h"
52 #include "bif/bif_5_0_d.h"
53 #include "bif/bif_5_0_sh_mask.h"
54 #include "gmc/gmc_8_1_d.h"
55 #include "gmc/gmc_8_1_sh_mask.h"
56 #include "bif/bif_5_0_d.h"
57 #include "bif/bif_5_0_sh_mask.h"
58 #include "dce/dce_10_0_d.h"
59 #include "dce/dce_10_0_sh_mask.h"
61 #include "polaris10_thermal.h"
62 #include "polaris10_clockpowergating.h"
64 #define MC_CG_ARB_FREQ_F0 0x0a
65 #define MC_CG_ARB_FREQ_F1 0x0b
66 #define MC_CG_ARB_FREQ_F2 0x0c
67 #define MC_CG_ARB_FREQ_F3 0x0d
69 #define MC_CG_SEQ_DRAMCONF_S0 0x05
70 #define MC_CG_SEQ_DRAMCONF_S1 0x06
71 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
72 #define MC_CG_SEQ_YCLK_RESUME 0x0a
75 #define SMC_RAM_END 0x40000
77 #define SMC_CG_IND_START 0xc0030000
78 #define SMC_CG_IND_END 0xc0040000
80 #define VOLTAGE_SCALE 4
81 #define VOLTAGE_VID_OFFSET_SCALE1 625
82 #define VOLTAGE_VID_OFFSET_SCALE2 100
84 #define VDDC_VDDCI_DELTA 200
86 #define MEM_FREQ_LOW_LATENCY 25000
87 #define MEM_FREQ_HIGH_LATENCY 80000
89 #define MEM_LATENCY_HIGH 45
90 #define MEM_LATENCY_LOW 35
91 #define MEM_LATENCY_ERR 0xFFFF
93 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
94 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
95 #define MC_SEQ_MISC0_GDDR5_VALUE 5
98 #define PCIE_BUS_CLK 10000
99 #define TCLK (PCIE_BUS_CLK / 10)
102 static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
103 { {600, 1050, 3, 0}, {600, 1050, 6, 1} };
105 /* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
106 static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] =
107 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
108 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
110 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
111 static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] =
112 { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
114 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
116 DPM_EVENT_SRC_ANALOG = 0,
117 DPM_EVENT_SRC_EXTERNAL = 1,
118 DPM_EVENT_SRC_DIGITAL = 2,
119 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
120 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
123 static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
125 struct polaris10_power_state *cast_phw_polaris10_power_state(
126 struct pp_hw_power_state *hw_ps)
128 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
129 "Invalid Powerstate Type!",
132 return (struct polaris10_power_state *)hw_ps;
135 const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
136 const struct pp_hw_power_state *hw_ps)
138 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
139 "Invalid Powerstate Type!",
142 return (const struct polaris10_power_state *)hw_ps;
145 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
147 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
148 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
153 * Find the MC microcode version and store it in the HwMgr struct
155 * @param hwmgr the address of the powerplay hardware manager.
158 int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
160 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
162 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
167 uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
169 uint32_t speedCntl = 0;
171 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
172 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
173 ixPCIE_LC_SPEED_CNTL);
174 return((uint16_t)PHM_GET_FIELD(speedCntl,
175 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
178 int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
182 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
183 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
184 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
186 PP_ASSERT_WITH_CODE((7 >= link_width),
187 "Invalid PCIe lane width!", return 0);
189 return decode_pcie_lane_width(link_width);
193 * Enable voltage control
195 * @param pHwMgr the address of the powerplay hardware manager.
196 * @return always PP_Result_OK
198 int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
201 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
202 "Failed to enable voltage DPM during DPM Start Function!",
210 * Checks if we want to support voltage control
212 * @param hwmgr the address of the powerplay hardware manager.
214 static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
216 const struct polaris10_hwmgr *data =
217 (const struct polaris10_hwmgr *)(hwmgr->backend);
219 return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
223 * Enable voltage control
225 * @param hwmgr the address of the powerplay hardware manager.
228 static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
230 /* enable voltage control */
231 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
232 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
238 * Create Voltage Tables.
240 * @param hwmgr the address of the powerplay hardware manager.
243 static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
245 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
246 struct phm_ppt_v1_information *table_info =
247 (struct phm_ppt_v1_information *)hwmgr->pptable;
250 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
251 result = atomctrl_get_voltage_table_v3(hwmgr,
252 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
253 &(data->mvdd_voltage_table));
254 PP_ASSERT_WITH_CODE((0 == result),
255 "Failed to retrieve MVDD table.",
257 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
258 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
259 table_info->vdd_dep_on_mclk);
260 PP_ASSERT_WITH_CODE((0 == result),
261 "Failed to retrieve SVI2 MVDD table from dependancy table.",
265 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
266 result = atomctrl_get_voltage_table_v3(hwmgr,
267 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
268 &(data->vddci_voltage_table));
269 PP_ASSERT_WITH_CODE((0 == result),
270 "Failed to retrieve VDDCI table.",
272 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
273 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
274 table_info->vdd_dep_on_mclk);
275 PP_ASSERT_WITH_CODE((0 == result),
276 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
280 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
281 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
282 table_info->vddc_lookup_table);
283 PP_ASSERT_WITH_CODE((0 == result),
284 "Failed to retrieve SVI2 VDDC table from lookup table.",
289 (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
290 "Too many voltage values for VDDC. Trimming to fit state table.",
291 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
292 &(data->vddc_voltage_table)));
295 (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
296 "Too many voltage values for VDDCI. Trimming to fit state table.",
297 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
298 &(data->vddci_voltage_table)));
301 (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
302 "Too many voltage values for MVDD. Trimming to fit state table.",
303 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
304 &(data->mvdd_voltage_table)));
310 * Programs static screed detection parameters
312 * @param hwmgr the address of the powerplay hardware manager.
315 static int polaris10_program_static_screen_threshold_parameters(
316 struct pp_hwmgr *hwmgr)
318 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
320 /* Set static screen threshold unit */
321 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
322 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
323 data->static_screen_threshold_unit);
324 /* Set static screen threshold */
325 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
326 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
327 data->static_screen_threshold);
333 * Setup display gap for glitch free memory clock switching.
335 * @param hwmgr the address of the powerplay hardware manager.
338 static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
340 uint32_t display_gap =
341 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
342 ixCG_DISPLAY_GAP_CNTL);
344 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
345 DISP_GAP, DISPLAY_GAP_IGNORE);
347 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
348 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
350 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
351 ixCG_DISPLAY_GAP_CNTL, display_gap);
357 * Programs activity state transition voting clients
359 * @param hwmgr the address of the powerplay hardware manager.
362 static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
364 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
366 /* Clear reset for voting clients before enabling DPM */
367 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
368 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
369 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
370 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
372 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
373 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
374 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
375 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
376 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
377 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
378 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
379 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
380 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
381 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
382 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
383 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
384 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
385 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
386 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
387 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
392 static int polaris10_clear_voting_clients(struct pp_hwmgr *hwmgr)
394 /* Reset voting clients before disabling DPM */
395 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
396 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
397 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
398 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
400 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
401 ixCG_FREQ_TRAN_VOTING_0, 0);
402 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
403 ixCG_FREQ_TRAN_VOTING_1, 0);
404 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
405 ixCG_FREQ_TRAN_VOTING_2, 0);
406 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
407 ixCG_FREQ_TRAN_VOTING_3, 0);
408 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
409 ixCG_FREQ_TRAN_VOTING_4, 0);
410 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
411 ixCG_FREQ_TRAN_VOTING_5, 0);
412 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
413 ixCG_FREQ_TRAN_VOTING_6, 0);
414 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
415 ixCG_FREQ_TRAN_VOTING_7, 0);
421 * Get the location of various tables inside the FW image.
423 * @param hwmgr the address of the powerplay hardware manager.
426 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
428 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
429 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
434 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
435 SMU7_FIRMWARE_HEADER_LOCATION +
436 offsetof(SMU74_Firmware_Header, DpmTable),
437 &tmp, data->sram_end);
440 data->dpm_table_start = tmp;
442 error |= (0 != result);
444 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
445 SMU7_FIRMWARE_HEADER_LOCATION +
446 offsetof(SMU74_Firmware_Header, SoftRegisters),
447 &tmp, data->sram_end);
450 data->soft_regs_start = tmp;
451 smu_data->soft_regs_start = tmp;
454 error |= (0 != result);
456 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
457 SMU7_FIRMWARE_HEADER_LOCATION +
458 offsetof(SMU74_Firmware_Header, mcRegisterTable),
459 &tmp, data->sram_end);
462 data->mc_reg_table_start = tmp;
464 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
465 SMU7_FIRMWARE_HEADER_LOCATION +
466 offsetof(SMU74_Firmware_Header, FanTable),
467 &tmp, data->sram_end);
470 data->fan_table_start = tmp;
472 error |= (0 != result);
474 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
475 SMU7_FIRMWARE_HEADER_LOCATION +
476 offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
477 &tmp, data->sram_end);
480 data->arb_table_start = tmp;
482 error |= (0 != result);
484 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
485 SMU7_FIRMWARE_HEADER_LOCATION +
486 offsetof(SMU74_Firmware_Header, Version),
487 &tmp, data->sram_end);
490 hwmgr->microcode_version_info.SMC = tmp;
492 error |= (0 != result);
494 return error ? -1 : 0;
497 /* Copy one arb setting to another and then switch the active set.
498 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
500 static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
501 uint32_t arb_src, uint32_t arb_dest)
503 uint32_t mc_arb_dram_timing;
504 uint32_t mc_arb_dram_timing2;
506 uint32_t mc_cg_config;
509 case MC_CG_ARB_FREQ_F0:
510 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
511 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
512 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
514 case MC_CG_ARB_FREQ_F1:
515 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
516 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
517 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
524 case MC_CG_ARB_FREQ_F0:
525 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
526 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
527 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
529 case MC_CG_ARB_FREQ_F1:
530 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
531 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
532 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
538 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
539 mc_cg_config |= 0x0000000F;
540 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
541 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
546 static int polaris10_reset_to_default(struct pp_hwmgr *hwmgr)
548 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults);
552 * Initial switch from ARB F0->F1
554 * @param hwmgr the address of the powerplay hardware manager.
556 * This function is to be called from the SetPowerState table.
558 static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
560 return polaris10_copy_and_switch_arb_sets(hwmgr,
561 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
564 static int polaris10_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
568 tmp = (cgs_read_ind_register(hwmgr->device,
569 CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
572 if (tmp == MC_CG_ARB_FREQ_F0)
575 return polaris10_copy_and_switch_arb_sets(hwmgr,
576 tmp, MC_CG_ARB_FREQ_F0);
579 static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
581 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
582 struct phm_ppt_v1_information *table_info =
583 (struct phm_ppt_v1_information *)(hwmgr->pptable);
584 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
585 uint32_t i, max_entry;
587 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
588 data->use_pcie_power_saving_levels), "No pcie performance levels!",
591 if (data->use_pcie_performance_levels &&
592 !data->use_pcie_power_saving_levels) {
593 data->pcie_gen_power_saving = data->pcie_gen_performance;
594 data->pcie_lane_power_saving = data->pcie_lane_performance;
595 } else if (!data->use_pcie_performance_levels &&
596 data->use_pcie_power_saving_levels) {
597 data->pcie_gen_performance = data->pcie_gen_power_saving;
598 data->pcie_lane_performance = data->pcie_lane_power_saving;
601 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
602 SMU74_MAX_LEVELS_LINK,
603 MAX_REGULAR_DPM_NUMBER);
605 if (pcie_table != NULL) {
606 /* max_entry is used to make sure we reserve one PCIE level
607 * for boot level (fix for A+A PSPP issue).
608 * If PCIE table from PPTable have ULV entry + 8 entries,
609 * then ignore the last entry.*/
610 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
611 SMU74_MAX_LEVELS_LINK : pcie_table->count;
612 for (i = 1; i < max_entry; i++) {
613 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
614 get_pcie_gen_support(data->pcie_gen_cap,
615 pcie_table->entries[i].gen_speed),
616 get_pcie_lane_support(data->pcie_lane_cap,
617 pcie_table->entries[i].lane_width));
619 data->dpm_table.pcie_speed_table.count = max_entry - 1;
621 /* Setup BIF_SCLK levels */
622 for (i = 0; i < max_entry; i++)
623 data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
625 /* Hardcode Pcie Table */
626 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
627 get_pcie_gen_support(data->pcie_gen_cap,
629 get_pcie_lane_support(data->pcie_lane_cap,
631 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
632 get_pcie_gen_support(data->pcie_gen_cap,
634 get_pcie_lane_support(data->pcie_lane_cap,
636 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
637 get_pcie_gen_support(data->pcie_gen_cap,
639 get_pcie_lane_support(data->pcie_lane_cap,
641 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
642 get_pcie_gen_support(data->pcie_gen_cap,
644 get_pcie_lane_support(data->pcie_lane_cap,
646 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
647 get_pcie_gen_support(data->pcie_gen_cap,
649 get_pcie_lane_support(data->pcie_lane_cap,
651 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
652 get_pcie_gen_support(data->pcie_gen_cap,
654 get_pcie_lane_support(data->pcie_lane_cap,
657 data->dpm_table.pcie_speed_table.count = 6;
659 /* Populate last level for boot PCIE level, but do not increment count. */
660 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
661 data->dpm_table.pcie_speed_table.count,
662 get_pcie_gen_support(data->pcie_gen_cap,
664 get_pcie_lane_support(data->pcie_lane_cap,
671 * This function is to initalize all DPM state tables
672 * for SMU7 based on the dependency table.
673 * Dynamic state patching function will then trim these
674 * state tables to the allowed range based
675 * on the power policy or external client requests,
676 * such as UVD request, etc.
678 int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
680 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
681 struct phm_ppt_v1_information *table_info =
682 (struct phm_ppt_v1_information *)(hwmgr->pptable);
685 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
686 table_info->vdd_dep_on_sclk;
687 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
688 table_info->vdd_dep_on_mclk;
690 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
691 "SCLK dependency table is missing. This table is mandatory",
693 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
694 "SCLK dependency table has to have is missing."
695 "This table is mandatory",
698 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
699 "MCLK dependency table is missing. This table is mandatory",
701 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
702 "MCLK dependency table has to have is missing."
703 "This table is mandatory",
706 /* clear the state table to reset everything to default */
707 phm_reset_single_dpm_table(
708 &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
709 phm_reset_single_dpm_table(
710 &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
713 /* Initialize Sclk DPM table based on allow Sclk values */
714 data->dpm_table.sclk_table.count = 0;
715 for (i = 0; i < dep_sclk_table->count; i++) {
716 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
717 dep_sclk_table->entries[i].clk) {
719 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
720 dep_sclk_table->entries[i].clk;
722 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
723 (i == 0) ? true : false;
724 data->dpm_table.sclk_table.count++;
728 /* Initialize Mclk DPM table based on allow Mclk values */
729 data->dpm_table.mclk_table.count = 0;
730 for (i = 0; i < dep_mclk_table->count; i++) {
731 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
732 [data->dpm_table.mclk_table.count - 1].value !=
733 dep_mclk_table->entries[i].clk) {
734 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
735 dep_mclk_table->entries[i].clk;
736 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
737 (i == 0) ? true : false;
738 data->dpm_table.mclk_table.count++;
742 /* setup PCIE gen speed levels */
743 polaris10_setup_default_pcie_table(hwmgr);
745 /* save a copy of the default DPM table */
746 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
747 sizeof(struct polaris10_dpm_table));
752 uint8_t convert_to_vid(uint16_t vddc)
754 return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
758 * Mvdd table preparation for SMC.
760 * @param *hwmgr The address of the hardware manager.
761 * @param *table The SMC DPM table structure to be populated.
764 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
765 SMU74_Discrete_DpmTable *table)
767 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
768 uint32_t count, level;
770 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
771 count = data->mvdd_voltage_table.count;
772 if (count > SMU_MAX_SMIO_LEVELS)
773 count = SMU_MAX_SMIO_LEVELS;
774 for (level = 0; level < count; level++) {
775 table->SmioTable2.Pattern[level].Voltage =
776 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
777 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
778 table->SmioTable2.Pattern[level].Smio =
780 table->Smio[level] |=
781 data->mvdd_voltage_table.entries[level].smio_low;
783 table->SmioMask2 = data->mvdd_voltage_table.mask_low;
785 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
791 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
792 struct SMU74_Discrete_DpmTable *table)
794 uint32_t count, level;
795 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
797 count = data->vddci_voltage_table.count;
799 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
800 if (count > SMU_MAX_SMIO_LEVELS)
801 count = SMU_MAX_SMIO_LEVELS;
802 for (level = 0; level < count; ++level) {
803 table->SmioTable1.Pattern[level].Voltage =
804 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
805 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
807 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
811 table->SmioMask1 = data->vddci_voltage_table.mask_low;
817 * Preparation of vddc and vddgfx CAC tables for SMC.
819 * @param hwmgr the address of the hardware manager
820 * @param table the SMC DPM table structure to be populated
823 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
824 struct SMU74_Discrete_DpmTable *table)
828 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
829 struct phm_ppt_v1_information *table_info =
830 (struct phm_ppt_v1_information *)(hwmgr->pptable);
831 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
832 table_info->vddc_lookup_table;
833 /* tables is already swapped, so in order to use the value from it,
834 * we need to swap it back.
835 * We are populating vddc CAC data to BapmVddc table
836 * in split and merged mode
838 for (count = 0; count < lookup_table->count; count++) {
839 index = phm_get_voltage_index(lookup_table,
840 data->vddc_voltage_table.entries[count].value);
841 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
842 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
843 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
850 * Preparation of voltage tables for SMC.
852 * @param hwmgr the address of the hardware manager
853 * @param table the SMC DPM table structure to be populated
857 int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
858 struct SMU74_Discrete_DpmTable *table)
860 polaris10_populate_smc_vddci_table(hwmgr, table);
861 polaris10_populate_smc_mvdd_table(hwmgr, table);
862 polaris10_populate_cac_table(hwmgr, table);
867 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
868 struct SMU74_Discrete_Ulv *state)
870 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
871 struct phm_ppt_v1_information *table_info =
872 (struct phm_ppt_v1_information *)(hwmgr->pptable);
874 state->CcPwrDynRm = 0;
875 state->CcPwrDynRm1 = 0;
877 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
878 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
879 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
881 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
883 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
884 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
885 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
890 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
891 struct SMU74_Discrete_DpmTable *table)
893 return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
896 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
897 struct SMU74_Discrete_DpmTable *table)
899 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
900 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
903 /* Index (dpm_table->pcie_speed_table.count)
904 * is reserved for PCIE boot level. */
905 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
906 table->LinkLevel[i].PcieGenSpeed =
907 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
908 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
909 dpm_table->pcie_speed_table.dpm_levels[i].param1);
910 table->LinkLevel[i].EnabledForActivity = 1;
911 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
912 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
913 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
916 data->smc_state_table.LinkLevelCount =
917 (uint8_t)dpm_table->pcie_speed_table.count;
918 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
919 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
924 static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
926 uint32_t reference_clock, tmp;
927 struct cgs_display_info info = {0};
928 struct cgs_mode_info mode_info;
930 info.mode_info = &mode_info;
932 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
937 cgs_get_active_displays_info(hwmgr->device, &info);
938 reference_clock = mode_info.ref_clock;
940 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
943 return reference_clock / 4;
945 return reference_clock;
949 * Calculates the SCLK dividers using the provided engine clock
951 * @param hwmgr the address of the hardware manager
952 * @param clock the engine clock to use to populate the structure
953 * @param sclk the SMC SCLK structure to be populated
955 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
956 uint32_t clock, SMU_SclkSetting *sclk_setting)
958 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
959 const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
960 struct pp_atomctrl_clock_dividers_ai dividers;
963 uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
968 sclk_setting->SclkFrequency = clock;
969 /* get the engine clock dividers for this clock value */
970 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs);
972 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
973 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
974 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
975 sclk_setting->PllRange = dividers.ucSclkPllRange;
976 sclk_setting->Sclk_slew_rate = 0x400;
977 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
978 sclk_setting->Pcc_down_slew_rate = 0xffff;
979 sclk_setting->SSc_En = dividers.ucSscEnable;
980 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
981 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
982 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
986 ref_clock = polaris10_get_xclk(hwmgr);
988 for (i = 0; i < NUM_SCLK_RANGE; i++) {
989 if (clock > data->range_table[i].trans_lower_frequency
990 && clock <= data->range_table[i].trans_upper_frequency) {
991 sclk_setting->PllRange = i;
996 sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
997 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
999 do_div(temp, ref_clock);
1000 sclk_setting->Fcw_frac = temp & 0xffff;
1002 pcc_target_percent = 10; /* Hardcode 10% for now. */
1003 pcc_target_freq = clock - (clock * pcc_target_percent / 100);
1004 sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
1006 ss_target_percent = 2; /* Hardcode 2% for now. */
1007 sclk_setting->SSc_En = 0;
1008 if (ss_target_percent) {
1009 sclk_setting->SSc_En = 1;
1010 ss_target_freq = clock - (clock * ss_target_percent / 100);
1011 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
1012 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
1014 do_div(temp, ref_clock);
1015 sclk_setting->Fcw1_frac = temp & 0xffff;
1021 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
1022 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1023 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1027 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1029 *voltage = *mvdd = 0;
1031 /* clock - voltage dependency table is empty table */
1032 if (dep_table->count == 0)
1035 for (i = 0; i < dep_table->count; i++) {
1036 /* find first sclk bigger than request */
1037 if (dep_table->entries[i].clk >= clock) {
1038 *voltage |= (dep_table->entries[i].vddc *
1039 VOLTAGE_SCALE) << VDDC_SHIFT;
1040 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1041 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1042 VOLTAGE_SCALE) << VDDCI_SHIFT;
1043 else if (dep_table->entries[i].vddci)
1044 *voltage |= (dep_table->entries[i].vddci *
1045 VOLTAGE_SCALE) << VDDCI_SHIFT;
1047 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1048 (dep_table->entries[i].vddc -
1049 (uint16_t)data->vddc_vddci_delta));
1050 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1053 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1054 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1056 else if (dep_table->entries[i].mvdd)
1057 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1060 *voltage |= 1 << PHASES_SHIFT;
1065 /* sclk is bigger than max sclk in the dependence table */
1066 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1068 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1069 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1070 VOLTAGE_SCALE) << VDDCI_SHIFT;
1071 else if (dep_table->entries[i-1].vddci) {
1072 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1073 (dep_table->entries[i].vddc -
1074 (uint16_t)data->vddc_vddci_delta));
1075 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1078 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1079 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1080 else if (dep_table->entries[i].mvdd)
1081 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1086 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] =
1087 { {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
1088 {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1089 {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
1090 {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
1091 {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
1092 {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
1093 {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
1094 {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
1096 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
1098 uint32_t i, ref_clk;
1099 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1100 SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1101 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1103 ref_clk = polaris10_get_xclk(hwmgr);
1105 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1106 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1107 table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1108 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1109 table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1111 table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1112 table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1114 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1115 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1116 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1121 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1123 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1124 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1126 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1127 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1128 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1130 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1131 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1133 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1134 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1135 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1140 * Populates single SMC SCLK structure using the provided engine clock
1142 * @param hwmgr the address of the hardware manager
1143 * @param clock the engine clock to use to populate the structure
1144 * @param sclk the SMC SCLK structure to be populated
1147 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1148 uint32_t clock, uint16_t sclk_al_threshold,
1149 struct SMU74_Discrete_GraphicsLevel *level)
1151 int result, i, temp;
1152 /* PP_Clocks minClocks; */
1154 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1155 struct phm_ppt_v1_information *table_info =
1156 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1157 SMU_SclkSetting curr_sclk_setting = { 0 };
1159 result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
1161 /* populate graphics levels */
1162 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1163 table_info->vdd_dep_on_sclk, clock,
1164 &level->MinVoltage, &mvdd);
1166 PP_ASSERT_WITH_CODE((0 == result),
1167 "can not find VDDC voltage value for "
1168 "VDDC engine clock dependency table",
1170 level->ActivityLevel = sclk_al_threshold;
1172 level->CcPwrDynRm = 0;
1173 level->CcPwrDynRm1 = 0;
1174 level->EnabledForActivity = 0;
1175 level->EnabledForThrottle = 1;
1177 level->DownHyst = 0;
1178 level->VoltageDownHyst = 0;
1179 level->PowerThrottle = 0;
1182 * TODO: get minimum clocks from dal configaration
1183 * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1185 /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1187 /* get level->DeepSleepDivId
1188 if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1189 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1191 PP_ASSERT_WITH_CODE((clock >= POLARIS10_MINIMUM_ENGINE_CLOCK), "Engine clock can't satisfy stutter requirement!", return 0);
1192 for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
1195 if (temp >= POLARIS10_MINIMUM_ENGINE_CLOCK || i == 0)
1199 level->DeepSleepDivId = i;
1201 /* Default to slow, highest DPM level will be
1202 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1204 if (data->update_up_hyst)
1205 level->UpHyst = (uint8_t)data->up_hyst;
1206 if (data->update_down_hyst)
1207 level->DownHyst = (uint8_t)data->down_hyst;
1209 level->SclkSetting = curr_sclk_setting;
1211 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1212 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1213 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1214 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1215 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1216 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1217 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1218 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1219 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1220 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1221 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1222 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1223 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1224 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1229 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1231 * @param hwmgr the address of the hardware manager
1233 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1235 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1236 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1237 struct phm_ppt_v1_information *table_info =
1238 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1239 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1240 uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1242 uint32_t array = data->dpm_table_start +
1243 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1244 uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1245 SMU74_MAX_LEVELS_GRAPHICS;
1246 struct SMU74_Discrete_GraphicsLevel *levels =
1247 data->smc_state_table.GraphicsLevel;
1248 uint32_t i, max_entry;
1249 uint8_t hightest_pcie_level_enabled = 0,
1250 lowest_pcie_level_enabled = 0,
1251 mid_pcie_level_enabled = 0,
1254 polaris10_get_sclk_range_table(hwmgr);
1256 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1258 result = polaris10_populate_single_graphic_level(hwmgr,
1259 dpm_table->sclk_table.dpm_levels[i].value,
1260 (uint16_t)data->activity_target[i],
1261 &(data->smc_state_table.GraphicsLevel[i]));
1265 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1267 levels[i].DeepSleepDivId = 0;
1269 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1270 PHM_PlatformCaps_SPLLShutdownSupport))
1271 data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1273 data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1274 data->smc_state_table.GraphicsDpmLevelCount =
1275 (uint8_t)dpm_table->sclk_table.count;
1276 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1277 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1280 if (pcie_table != NULL) {
1281 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1282 "There must be 1 or more PCIE levels defined in PPTable.",
1284 max_entry = pcie_entry_cnt - 1;
1285 for (i = 0; i < dpm_table->sclk_table.count; i++)
1286 levels[i].pcieDpmLevel =
1287 (uint8_t) ((i < max_entry) ? i : max_entry);
1289 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1290 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1291 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1292 hightest_pcie_level_enabled++;
1294 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1295 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1296 (1 << lowest_pcie_level_enabled)) == 0))
1297 lowest_pcie_level_enabled++;
1299 while ((count < hightest_pcie_level_enabled) &&
1300 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1301 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1304 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1305 hightest_pcie_level_enabled ?
1306 (lowest_pcie_level_enabled + 1 + count) :
1307 hightest_pcie_level_enabled;
1309 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1310 for (i = 2; i < dpm_table->sclk_table.count; i++)
1311 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1313 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1314 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1316 /* set pcieDpmLevel to mid_pcie_level_enabled */
1317 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1319 /* level count will send to smc once at init smc table and never change */
1320 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1321 (uint32_t)array_size, data->sram_end);
1326 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1327 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1329 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1330 struct phm_ppt_v1_information *table_info =
1331 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1333 struct cgs_display_info info = {0, 0, NULL};
1335 cgs_get_active_displays_info(hwmgr->device, &info);
1337 if (table_info->vdd_dep_on_mclk) {
1338 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1339 table_info->vdd_dep_on_mclk, clock,
1340 &mem_level->MinVoltage, &mem_level->MinMvdd);
1341 PP_ASSERT_WITH_CODE((0 == result),
1342 "can not find MinVddc voltage value from memory "
1343 "VDDC voltage dependency table", return result);
1346 mem_level->MclkFrequency = clock;
1347 mem_level->EnabledForThrottle = 1;
1348 mem_level->EnabledForActivity = 0;
1349 mem_level->UpHyst = 0;
1350 mem_level->DownHyst = 100;
1351 mem_level->VoltageDownHyst = 0;
1352 mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1353 mem_level->StutterEnable = false;
1354 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1356 data->display_timing.num_existing_displays = info.display_count;
1358 if ((data->mclk_stutter_mode_threshold) &&
1359 (clock <= data->mclk_stutter_mode_threshold) &&
1360 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1361 STUTTER_ENABLE) & 0x1))
1362 mem_level->StutterEnable = true;
1365 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1366 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1367 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1368 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1374 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1376 * @param hwmgr the address of the hardware manager
1378 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1380 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1381 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1383 /* populate MCLK dpm table to SMU7 */
1384 uint32_t array = data->dpm_table_start +
1385 offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1386 uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1387 SMU74_MAX_LEVELS_MEMORY;
1388 struct SMU74_Discrete_MemoryLevel *levels =
1389 data->smc_state_table.MemoryLevel;
1392 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1393 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1394 "can not populate memory level as memory clock is zero",
1396 result = polaris10_populate_single_memory_level(hwmgr,
1397 dpm_table->mclk_table.dpm_levels[i].value,
1399 if (i == dpm_table->mclk_table.count - 1) {
1400 levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1401 levels[i].EnabledForActivity = 1;
1407 /* In order to prevent MC activity from stutter mode to push DPM up,
1408 * the UVD change complements this by putting the MCLK in
1409 * a higher state by default such that we are not affected by
1410 * up threshold or and MCLK DPM latency.
1412 levels[0].ActivityLevel = 0x1f;
1413 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1415 data->smc_state_table.MemoryDpmLevelCount =
1416 (uint8_t)dpm_table->mclk_table.count;
1417 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1418 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1420 /* level count will send to smc once at init smc table and never change */
1421 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1422 (uint32_t)array_size, data->sram_end);
1428 * Populates the SMC MVDD structure using the provided memory clock.
1430 * @param hwmgr the address of the hardware manager
1431 * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
1432 * @param voltage the SMC VOLTAGE structure to be populated
1434 int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1435 uint32_t mclk, SMIO_Pattern *smio_pat)
1437 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1438 struct phm_ppt_v1_information *table_info =
1439 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1442 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1443 /* find mvdd value which clock is more than request */
1444 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1445 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1446 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1450 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1451 "MVDD Voltage is outside the supported range.",
1459 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1460 SMU74_Discrete_DpmTable *table)
1463 uint32_t sclk_frequency;
1464 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1465 struct phm_ppt_v1_information *table_info =
1466 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1467 SMIO_Pattern vol_level;
1471 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1474 /* Get MinVoltage and Frequency from DPM0,
1475 * already converted to SMC_UL */
1476 sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
1477 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1478 table_info->vdd_dep_on_sclk,
1480 &table->ACPILevel.MinVoltage, &mvdd);
1481 PP_ASSERT_WITH_CODE((0 == result),
1482 "Cannot find ACPI VDDC voltage value "
1483 "in Clock Dependency Table",
1487 result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
1488 PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1490 table->ACPILevel.DeepSleepDivId = 0;
1491 table->ACPILevel.CcPwrDynRm = 0;
1492 table->ACPILevel.CcPwrDynRm1 = 0;
1494 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1495 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1496 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1497 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1499 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1500 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1501 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1502 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1503 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1504 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1505 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1506 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1507 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1508 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1511 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1512 table->MemoryACPILevel.MclkFrequency =
1513 data->dpm_table.mclk_table.dpm_levels[0].value;
1514 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1515 table_info->vdd_dep_on_mclk,
1516 table->MemoryACPILevel.MclkFrequency,
1517 &table->MemoryACPILevel.MinVoltage, &mvdd);
1518 PP_ASSERT_WITH_CODE((0 == result),
1519 "Cannot find ACPI VDDCI voltage value "
1520 "in Clock Dependency Table",
1524 if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1525 (data->mclk_dpm_key_disabled))
1526 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1528 if (!polaris10_populate_mvdd_value(hwmgr,
1529 data->dpm_table.mclk_table.dpm_levels[0].value,
1531 us_mvdd = vol_level.Voltage;
1534 if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1535 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1537 table->MemoryACPILevel.MinMvdd = 0;
1539 table->MemoryACPILevel.StutterEnable = false;
1541 table->MemoryACPILevel.EnabledForThrottle = 0;
1542 table->MemoryACPILevel.EnabledForActivity = 0;
1543 table->MemoryACPILevel.UpHyst = 0;
1544 table->MemoryACPILevel.DownHyst = 100;
1545 table->MemoryACPILevel.VoltageDownHyst = 0;
1546 table->MemoryACPILevel.ActivityLevel =
1547 PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1549 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1550 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1555 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1556 SMU74_Discrete_DpmTable *table)
1558 int result = -EINVAL;
1560 struct pp_atomctrl_clock_dividers_vi dividers;
1561 struct phm_ppt_v1_information *table_info =
1562 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1563 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1564 table_info->mm_dep_table;
1565 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1568 table->VceLevelCount = (uint8_t)(mm_table->count);
1569 table->VceBootLevel = 0;
1571 for (count = 0; count < table->VceLevelCount; count++) {
1572 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1573 table->VceLevel[count].MinVoltage = 0;
1574 table->VceLevel[count].MinVoltage |=
1575 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1577 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1578 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1579 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1580 else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1581 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1583 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1586 table->VceLevel[count].MinVoltage |=
1587 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1588 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1590 /*retrieve divider value for VBIOS */
1591 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1592 table->VceLevel[count].Frequency, ÷rs);
1593 PP_ASSERT_WITH_CODE((0 == result),
1594 "can not find divide id for VCE engine clock",
1597 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1599 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1600 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1605 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1606 SMU74_Discrete_DpmTable *table)
1608 int result = -EINVAL;
1610 struct pp_atomctrl_clock_dividers_vi dividers;
1611 struct phm_ppt_v1_information *table_info =
1612 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1613 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1614 table_info->mm_dep_table;
1615 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1618 table->SamuBootLevel = 0;
1619 table->SamuLevelCount = (uint8_t)(mm_table->count);
1621 for (count = 0; count < table->SamuLevelCount; count++) {
1622 /* not sure whether we need evclk or not */
1623 table->SamuLevel[count].MinVoltage = 0;
1624 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1625 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1626 VOLTAGE_SCALE) << VDDC_SHIFT;
1628 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1629 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1630 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1631 else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1632 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1634 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1636 table->SamuLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1637 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1639 /* retrieve divider value for VBIOS */
1640 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1641 table->SamuLevel[count].Frequency, ÷rs);
1642 PP_ASSERT_WITH_CODE((0 == result),
1643 "can not find divide id for samu clock", return result);
1645 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1647 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1648 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1653 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1654 int32_t eng_clock, int32_t mem_clock,
1655 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1657 uint32_t dram_timing;
1658 uint32_t dram_timing2;
1659 uint32_t burst_time;
1662 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1663 eng_clock, mem_clock);
1664 PP_ASSERT_WITH_CODE(result == 0,
1665 "Error calling VBIOS to set DRAM_TIMING.", return result);
1667 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1668 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1669 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1672 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1673 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1674 arb_regs->McArbBurstTime = (uint8_t)burst_time;
1679 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1681 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1682 struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1686 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1687 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1688 result = polaris10_populate_memory_timing_parameters(hwmgr,
1689 data->dpm_table.sclk_table.dpm_levels[i].value,
1690 data->dpm_table.mclk_table.dpm_levels[j].value,
1691 &arb_regs.entries[i][j]);
1693 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1699 result = polaris10_copy_bytes_to_smc(
1701 data->arb_table_start,
1702 (uint8_t *)&arb_regs,
1703 sizeof(SMU74_Discrete_MCArbDramTimingTable),
1708 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1709 struct SMU74_Discrete_DpmTable *table)
1711 int result = -EINVAL;
1713 struct pp_atomctrl_clock_dividers_vi dividers;
1714 struct phm_ppt_v1_information *table_info =
1715 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1716 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1717 table_info->mm_dep_table;
1718 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1721 table->UvdLevelCount = (uint8_t)(mm_table->count);
1722 table->UvdBootLevel = 0;
1724 for (count = 0; count < table->UvdLevelCount; count++) {
1725 table->UvdLevel[count].MinVoltage = 0;
1726 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1727 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1728 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1729 VOLTAGE_SCALE) << VDDC_SHIFT;
1731 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1732 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1733 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1734 else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1735 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1737 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1739 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1740 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1742 /* retrieve divider value for VBIOS */
1743 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1744 table->UvdLevel[count].VclkFrequency, ÷rs);
1745 PP_ASSERT_WITH_CODE((0 == result),
1746 "can not find divide id for Vclk clock", return result);
1748 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1750 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1751 table->UvdLevel[count].DclkFrequency, ÷rs);
1752 PP_ASSERT_WITH_CODE((0 == result),
1753 "can not find divide id for Dclk clock", return result);
1755 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1757 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1758 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1759 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1765 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1766 struct SMU74_Discrete_DpmTable *table)
1769 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1771 table->GraphicsBootLevel = 0;
1772 table->MemoryBootLevel = 0;
1774 /* find boot level from dpm table */
1775 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1776 data->vbios_boot_state.sclk_bootup_value,
1777 (uint32_t *)&(table->GraphicsBootLevel));
1779 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1780 data->vbios_boot_state.mclk_bootup_value,
1781 (uint32_t *)&(table->MemoryBootLevel));
1783 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1785 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1787 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1790 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1791 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1792 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1798 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1800 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1801 struct phm_ppt_v1_information *table_info =
1802 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1803 uint8_t count, level;
1805 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1807 for (level = 0; level < count; level++) {
1808 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1809 data->vbios_boot_state.sclk_bootup_value) {
1810 data->smc_state_table.GraphicsBootLevel = level;
1815 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1816 for (level = 0; level < count; level++) {
1817 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1818 data->vbios_boot_state.mclk_bootup_value) {
1819 data->smc_state_table.MemoryBootLevel = level;
1827 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1829 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1830 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1831 uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
1832 struct phm_ppt_v1_information *table_info =
1833 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1834 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1835 table_info->vdd_dep_on_sclk;
1837 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1839 /* Read SMU_Eefuse to read and calculate RO and determine
1840 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1842 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1843 ixSMU_EFUSE_0 + (67 * 4));
1844 efuse &= 0xFF000000;
1845 efuse = efuse >> 24;
1847 if (hwmgr->chip_id == CHIP_POLARIS10) {
1855 ro = efuse * (max -min)/255 + min;
1857 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1858 for (i = 0; i < sclk_table->count; i++) {
1859 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1860 sclk_table->entries[i].cks_enable << i;
1861 if (hwmgr->chip_id == CHIP_POLARIS10) {
1862 volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 -(ro - 70) * 1000000) / \
1863 (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1864 volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \
1865 (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
1867 volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 -(ro - 50) * 1000000) / \
1868 (2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));
1869 volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \
1870 (3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));
1873 if (volt_without_cks >= volt_with_cks)
1874 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1875 sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
1877 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1880 data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
1881 /* Populate CKS Lookup Table */
1882 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1883 stretch_amount2 = 0;
1884 else if (stretch_amount == 3 || stretch_amount == 4)
1885 stretch_amount2 = 1;
1887 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1888 PHM_PlatformCaps_ClockStretcher);
1889 PP_ASSERT_WITH_CODE(false,
1890 "Stretch Amount in PPTable not supported\n",
1894 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1895 value &= 0xFFFFFFFE;
1896 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1902 * Populates the SMC VRConfig field in DPM table.
1904 * @param hwmgr the address of the hardware manager
1905 * @param table the SMC DPM table structure to be populated
1908 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1909 struct SMU74_Discrete_DpmTable *table)
1911 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1914 config = VR_MERGED_WITH_VDDC;
1915 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1917 /* Set Vddc Voltage Controller */
1918 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1919 config = VR_SVI2_PLANE_1;
1920 table->VRConfig |= config;
1922 PP_ASSERT_WITH_CODE(false,
1923 "VDDC should be on SVI2 control in merged mode!",
1926 /* Set Vddci Voltage Controller */
1927 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1928 config = VR_SVI2_PLANE_2; /* only in merged mode */
1929 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1930 } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1931 config = VR_SMIO_PATTERN_1;
1932 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1934 config = VR_STATIC_VOLTAGE;
1935 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1937 /* Set Mvdd Voltage Controller */
1938 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1939 config = VR_SVI2_PLANE_2;
1940 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1941 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start +
1942 offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
1944 config = VR_STATIC_VOLTAGE;
1945 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1952 int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1954 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1955 SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1957 struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1958 AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1959 AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1961 struct pp_smumgr *smumgr = hwmgr->smumgr;
1962 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
1964 struct phm_ppt_v1_information *table_info =
1965 (struct phm_ppt_v1_information *)hwmgr->pptable;
1966 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1967 table_info->vdd_dep_on_sclk;
1970 if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
1973 result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1976 table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1977 table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1978 table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1979 table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1980 table->BTCGB_VDROOP_TABLE[1].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1981 table->BTCGB_VDROOP_TABLE[1].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1982 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1983 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1984 table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1985 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1986 table->AVFSGB_VDROOP_TABLE[0].m2_shift = 12;
1987 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1988 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1989 table->AVFSGB_VDROOP_TABLE[1].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1990 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1991 table->AVFSGB_VDROOP_TABLE[1].m2_shift = 12;
1992 table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1993 AVFS_meanNsigma.Aconstant[0] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1994 AVFS_meanNsigma.Aconstant[1] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1995 AVFS_meanNsigma.Aconstant[2] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1996 AVFS_meanNsigma.DC_tol_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1997 AVFS_meanNsigma.Platform_mean = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1998 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1999 AVFS_meanNsigma.Platform_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
2001 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
2002 AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
2003 AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
2006 result = polaris10_read_smc_sram_dword(smumgr,
2007 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
2008 &tmp, data->sram_end);
2010 polaris10_copy_bytes_to_smc(smumgr,
2012 (uint8_t *)&AVFS_meanNsigma,
2013 sizeof(AVFS_meanNsigma_t),
2016 result = polaris10_read_smc_sram_dword(smumgr,
2017 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
2018 &tmp, data->sram_end);
2019 polaris10_copy_bytes_to_smc(smumgr,
2021 (uint8_t *)&AVFS_SclkOffset,
2022 sizeof(AVFS_Sclk_Offset_t),
2025 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
2026 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
2027 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
2028 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
2029 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
2036 * Initializes the SMC table and uploads it
2038 * @param hwmgr the address of the powerplay hardware manager.
2041 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
2044 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2045 struct phm_ppt_v1_information *table_info =
2046 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2047 struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
2048 const struct polaris10_ulv_parm *ulv = &(data->ulv);
2050 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
2051 pp_atomctrl_clock_dividers_vi dividers;
2053 result = polaris10_setup_default_dpm_tables(hwmgr);
2054 PP_ASSERT_WITH_CODE(0 == result,
2055 "Failed to setup default DPM tables!", return result);
2057 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
2058 polaris10_populate_smc_voltage_tables(hwmgr, table);
2060 table->SystemFlags = 0;
2061 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2062 PHM_PlatformCaps_AutomaticDCTransition))
2063 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2065 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2066 PHM_PlatformCaps_StepVddc))
2067 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2069 if (data->is_memory_gddr5)
2070 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2072 if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2073 result = polaris10_populate_ulv_state(hwmgr, table);
2074 PP_ASSERT_WITH_CODE(0 == result,
2075 "Failed to initialize ULV state!", return result);
2076 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2077 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
2080 result = polaris10_populate_smc_link_level(hwmgr, table);
2081 PP_ASSERT_WITH_CODE(0 == result,
2082 "Failed to initialize Link Level!", return result);
2084 result = polaris10_populate_all_graphic_levels(hwmgr);
2085 PP_ASSERT_WITH_CODE(0 == result,
2086 "Failed to initialize Graphics Level!", return result);
2088 result = polaris10_populate_all_memory_levels(hwmgr);
2089 PP_ASSERT_WITH_CODE(0 == result,
2090 "Failed to initialize Memory Level!", return result);
2092 result = polaris10_populate_smc_acpi_level(hwmgr, table);
2093 PP_ASSERT_WITH_CODE(0 == result,
2094 "Failed to initialize ACPI Level!", return result);
2096 result = polaris10_populate_smc_vce_level(hwmgr, table);
2097 PP_ASSERT_WITH_CODE(0 == result,
2098 "Failed to initialize VCE Level!", return result);
2100 result = polaris10_populate_smc_samu_level(hwmgr, table);
2101 PP_ASSERT_WITH_CODE(0 == result,
2102 "Failed to initialize SAMU Level!", return result);
2104 /* Since only the initial state is completely set up at this point
2105 * (the other states are just copies of the boot state) we only
2106 * need to populate the ARB settings for the initial state.
2108 result = polaris10_program_memory_timing_parameters(hwmgr);
2109 PP_ASSERT_WITH_CODE(0 == result,
2110 "Failed to Write ARB settings for the initial state.", return result);
2112 result = polaris10_populate_smc_uvd_level(hwmgr, table);
2113 PP_ASSERT_WITH_CODE(0 == result,
2114 "Failed to initialize UVD Level!", return result);
2116 result = polaris10_populate_smc_boot_level(hwmgr, table);
2117 PP_ASSERT_WITH_CODE(0 == result,
2118 "Failed to initialize Boot Level!", return result);
2120 result = polaris10_populate_smc_initailial_state(hwmgr);
2121 PP_ASSERT_WITH_CODE(0 == result,
2122 "Failed to initialize Boot State!", return result);
2124 result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
2125 PP_ASSERT_WITH_CODE(0 == result,
2126 "Failed to populate BAPM Parameters!", return result);
2128 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2129 PHM_PlatformCaps_ClockStretcher)) {
2130 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
2131 PP_ASSERT_WITH_CODE(0 == result,
2132 "Failed to populate Clock Stretcher Data Table!",
2136 result = polaris10_populate_avfs_parameters(hwmgr);
2137 PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
2139 table->CurrSclkPllRange = 0xff;
2140 table->GraphicsVoltageChangeEnable = 1;
2141 table->GraphicsThermThrottleEnable = 1;
2142 table->GraphicsInterval = 1;
2143 table->VoltageInterval = 1;
2144 table->ThermalInterval = 1;
2145 table->TemperatureLimitHigh =
2146 table_info->cac_dtp_table->usTargetOperatingTemp *
2147 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2148 table->TemperatureLimitLow =
2149 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2150 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2151 table->MemoryVoltageChangeEnable = 1;
2152 table->MemoryInterval = 1;
2153 table->VoltageResponseTime = 0;
2154 table->PhaseResponseTime = 0;
2155 table->MemoryThermThrottleEnable = 1;
2156 table->PCIeBootLinkLevel = 0;
2157 table->PCIeGenInterval = 1;
2158 table->VRConfig = 0;
2160 result = polaris10_populate_vr_config(hwmgr, table);
2161 PP_ASSERT_WITH_CODE(0 == result,
2162 "Failed to populate VRConfig setting!", return result);
2164 table->ThermGpio = 17;
2165 table->SclkStepSize = 0x4000;
2167 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2168 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2170 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
2171 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2172 PHM_PlatformCaps_RegulatorHot);
2175 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2177 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2178 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2179 PHM_PlatformCaps_AutomaticDCTransition);
2181 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
2182 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2183 PHM_PlatformCaps_AutomaticDCTransition);
2186 /* Thermal Output GPIO */
2187 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2189 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2190 PHM_PlatformCaps_ThermalOutGPIO);
2192 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2194 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2195 * since VBIOS will program this register to set 'inactive state',
2196 * driver can then determine 'active state' from this and
2197 * program SMU with correct polarity
2199 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2200 & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2201 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2203 /* if required, combine VRHot/PCC with thermal out GPIO */
2204 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2205 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2206 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2208 table->ThermOutGpio = 17;
2209 table->ThermOutPolarity = 1;
2210 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2213 /* Populate BIF_SCLK levels into SMC DPM table */
2214 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2215 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], ÷rs);
2216 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2219 table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2221 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2224 for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2225 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2227 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2228 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2229 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2230 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2231 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2232 CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2233 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2234 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2235 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2236 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2238 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2239 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
2240 data->dpm_table_start +
2241 offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2242 (uint8_t *)&(table->SystemFlags),
2243 sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2245 PP_ASSERT_WITH_CODE(0 == result,
2246 "Failed to upload dpm data to SMC memory!", return result);
2252 * Initialize the ARB DRAM timing table's index field.
2254 * @param hwmgr the address of the powerplay hardware manager.
2257 static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
2259 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2263 /* This is a read-modify-write on the first byte of the ARB table.
2264 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2265 * is the field 'current'.
2266 * This solution is ugly, but we never write the whole table only
2267 * individual fields in it.
2268 * In reality this field should not be in that structure
2269 * but in a soft register.
2271 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
2272 data->arb_table_start, &tmp, data->sram_end);
2278 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2280 return polaris10_write_smc_sram_dword(hwmgr->smumgr,
2281 data->arb_table_start, tmp, data->sram_end);
2284 static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
2286 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2287 PHM_PlatformCaps_RegulatorHot))
2288 return smum_send_msg_to_smc(hwmgr->smumgr,
2289 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2294 static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
2296 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2297 SCLK_PWRMGT_OFF, 0);
2301 static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
2303 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2304 struct polaris10_ulv_parm *ulv = &(data->ulv);
2306 if (ulv->ulv_supported)
2307 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2312 static int polaris10_disable_ulv(struct pp_hwmgr *hwmgr)
2314 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2315 struct polaris10_ulv_parm *ulv = &(data->ulv);
2317 if (ulv->ulv_supported)
2318 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableULV);
2323 static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2325 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2326 PHM_PlatformCaps_SclkDeepSleep)) {
2327 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2328 PP_ASSERT_WITH_CODE(false,
2329 "Attempt to enable Master Deep Sleep switch failed!",
2332 if (smum_send_msg_to_smc(hwmgr->smumgr,
2333 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2334 PP_ASSERT_WITH_CODE(false,
2335 "Attempt to disable Master Deep Sleep switch failed!",
2343 static int polaris10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2345 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2346 PHM_PlatformCaps_SclkDeepSleep)) {
2347 if (smum_send_msg_to_smc(hwmgr->smumgr,
2348 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2349 PP_ASSERT_WITH_CODE(false,
2350 "Attempt to disable Master Deep Sleep switch failed!",
2358 static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2360 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2361 uint32_t soft_register_value = 0;
2362 uint32_t handshake_disables_offset = data->soft_regs_start
2363 + offsetof(SMU74_SoftRegisters, HandshakeDisables);
2365 /* enable SCLK dpm */
2366 if (!data->sclk_dpm_key_disabled)
2367 PP_ASSERT_WITH_CODE(
2368 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2369 "Failed to enable SCLK DPM during DPM Start Function!",
2372 /* enable MCLK dpm */
2373 if (0 == data->mclk_dpm_key_disabled) {
2374 /* Disable UVD - SMU handshake for MCLK. */
2375 soft_register_value = cgs_read_ind_register(hwmgr->device,
2376 CGS_IND_REG__SMC, handshake_disables_offset);
2377 soft_register_value |= SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2378 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2379 handshake_disables_offset, soft_register_value);
2381 PP_ASSERT_WITH_CODE(
2382 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2383 PPSMC_MSG_MCLKDPM_Enable)),
2384 "Failed to enable MCLK DPM during DPM Start Function!",
2387 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2389 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2390 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2391 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2393 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2394 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2395 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2401 static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
2403 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2405 /*enable general power management */
2407 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2408 GLOBAL_PWRMGT_EN, 1);
2410 /* enable sclk deep sleep */
2412 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2415 /* prepare for PCIE DPM */
2417 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2418 data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2419 VoltageChangeTimeout), 0x1000);
2420 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2421 SWRST_COMMAND_1, RESETLC, 0x0);
2423 PP_ASSERT_WITH_CODE(
2424 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2425 PPSMC_MSG_Voltage_Cntl_Enable)),
2426 "Failed to enable voltage DPM during DPM Start Function!",
2430 if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
2431 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2435 /* enable PCIE dpm */
2436 if (0 == data->pcie_dpm_key_disabled) {
2437 PP_ASSERT_WITH_CODE(
2438 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2439 PPSMC_MSG_PCIeDPM_Enable)),
2440 "Failed to enable pcie DPM during DPM Start Function!",
2444 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2445 PHM_PlatformCaps_Falcon_QuickTransition)) {
2446 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2447 PPSMC_MSG_EnableACDCGPIOInterrupt)),
2448 "Failed to enable AC DC GPIO Interrupt!",
2455 static int polaris10_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2457 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2459 /* disable SCLK dpm */
2460 if (!data->sclk_dpm_key_disabled)
2461 PP_ASSERT_WITH_CODE(
2462 (smum_send_msg_to_smc(hwmgr->smumgr,
2463 PPSMC_MSG_DPM_Disable) == 0),
2464 "Failed to disable SCLK DPM!",
2467 /* disable MCLK dpm */
2468 if (!data->mclk_dpm_key_disabled) {
2469 PP_ASSERT_WITH_CODE(
2470 (smum_send_msg_to_smc(hwmgr->smumgr,
2471 PPSMC_MSG_MCLKDPM_Disable) == 0),
2472 "Failed to disable MCLK DPM!",
2479 static int polaris10_stop_dpm(struct pp_hwmgr *hwmgr)
2481 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2483 /* disable general power management */
2484 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2485 GLOBAL_PWRMGT_EN, 0);
2486 /* disable sclk deep sleep */
2487 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2490 /* disable PCIE dpm */
2491 if (!data->pcie_dpm_key_disabled) {
2492 PP_ASSERT_WITH_CODE(
2493 (smum_send_msg_to_smc(hwmgr->smumgr,
2494 PPSMC_MSG_PCIeDPM_Disable) == 0),
2495 "Failed to disable pcie DPM during DPM Stop Function!",
2499 if (polaris10_disable_sclk_mclk_dpm(hwmgr)) {
2500 printk(KERN_ERR "Failed to disable Sclk DPM and Mclk DPM!");
2507 static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
2510 enum DPM_EVENT_SRC src;
2514 printk(KERN_ERR "Unknown throttling event sources.");
2520 case (1 << PHM_AutoThrottleSource_Thermal):
2522 src = DPM_EVENT_SRC_DIGITAL;
2524 case (1 << PHM_AutoThrottleSource_External):
2526 src = DPM_EVENT_SRC_EXTERNAL;
2528 case (1 << PHM_AutoThrottleSource_External) |
2529 (1 << PHM_AutoThrottleSource_Thermal):
2531 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2534 /* Order matters - don't enable thermal protection for the wrong source. */
2536 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2537 DPM_EVENT_SRC, src);
2538 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2539 THERMAL_PROTECTION_DIS,
2540 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2541 PHM_PlatformCaps_ThermalController));
2543 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2544 THERMAL_PROTECTION_DIS, 1);
2547 static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2548 PHM_AutoThrottleSource source)
2550 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2552 if (!(data->active_auto_throttle_sources & (1 << source))) {
2553 data->active_auto_throttle_sources |= 1 << source;
2554 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2559 static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2561 return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2564 static int polaris10_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2565 PHM_AutoThrottleSource source)
2567 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2569 if (data->active_auto_throttle_sources & (1 << source)) {
2570 data->active_auto_throttle_sources &= ~(1 << source);
2571 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2576 static int polaris10_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2578 return polaris10_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2581 int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
2583 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2584 data->pcie_performance_request = true;
2589 int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2591 int tmp_result, result = 0;
2592 tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2593 PP_ASSERT_WITH_CODE(result == 0,
2594 "DPM is already running right now, no need to enable DPM!",
2597 if (polaris10_voltage_control(hwmgr)) {
2598 tmp_result = polaris10_enable_voltage_control(hwmgr);
2599 PP_ASSERT_WITH_CODE(tmp_result == 0,
2600 "Failed to enable voltage control!",
2601 result = tmp_result);
2603 tmp_result = polaris10_construct_voltage_tables(hwmgr);
2604 PP_ASSERT_WITH_CODE((0 == tmp_result),
2605 "Failed to contruct voltage tables!",
2606 result = tmp_result);
2609 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2610 PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2611 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2612 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2614 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2615 PHM_PlatformCaps_ThermalController))
2616 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2617 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2619 tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
2620 PP_ASSERT_WITH_CODE((0 == tmp_result),
2621 "Failed to program static screen threshold parameters!",
2622 result = tmp_result);
2624 tmp_result = polaris10_enable_display_gap(hwmgr);
2625 PP_ASSERT_WITH_CODE((0 == tmp_result),
2626 "Failed to enable display gap!", result = tmp_result);
2628 tmp_result = polaris10_program_voting_clients(hwmgr);
2629 PP_ASSERT_WITH_CODE((0 == tmp_result),
2630 "Failed to program voting clients!", result = tmp_result);
2632 tmp_result = polaris10_process_firmware_header(hwmgr);
2633 PP_ASSERT_WITH_CODE((0 == tmp_result),
2634 "Failed to process firmware header!", result = tmp_result);
2636 tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
2637 PP_ASSERT_WITH_CODE((0 == tmp_result),
2638 "Failed to initialize switch from ArbF0 to F1!",
2639 result = tmp_result);
2641 tmp_result = polaris10_init_smc_table(hwmgr);
2642 PP_ASSERT_WITH_CODE((0 == tmp_result),
2643 "Failed to initialize SMC table!", result = tmp_result);
2645 tmp_result = polaris10_init_arb_table_index(hwmgr);
2646 PP_ASSERT_WITH_CODE((0 == tmp_result),
2647 "Failed to initialize ARB table index!", result = tmp_result);
2649 tmp_result = polaris10_populate_pm_fuses(hwmgr);
2650 PP_ASSERT_WITH_CODE((0 == tmp_result),
2651 "Failed to populate PM fuses!", result = tmp_result);
2653 tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
2654 PP_ASSERT_WITH_CODE((0 == tmp_result),
2655 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2657 smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay);
2659 tmp_result = polaris10_enable_sclk_control(hwmgr);
2660 PP_ASSERT_WITH_CODE((0 == tmp_result),
2661 "Failed to enable SCLK control!", result = tmp_result);
2663 tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
2664 PP_ASSERT_WITH_CODE((0 == tmp_result),
2665 "Failed to enable voltage control!", result = tmp_result);
2667 tmp_result = polaris10_enable_ulv(hwmgr);
2668 PP_ASSERT_WITH_CODE((0 == tmp_result),
2669 "Failed to enable ULV!", result = tmp_result);
2671 tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
2672 PP_ASSERT_WITH_CODE((0 == tmp_result),
2673 "Failed to enable deep sleep master switch!", result = tmp_result);
2675 tmp_result = polaris10_start_dpm(hwmgr);
2676 PP_ASSERT_WITH_CODE((0 == tmp_result),
2677 "Failed to start DPM!", result = tmp_result);
2679 tmp_result = polaris10_enable_smc_cac(hwmgr);
2680 PP_ASSERT_WITH_CODE((0 == tmp_result),
2681 "Failed to enable SMC CAC!", result = tmp_result);
2683 tmp_result = polaris10_enable_power_containment(hwmgr);
2684 PP_ASSERT_WITH_CODE((0 == tmp_result),
2685 "Failed to enable power containment!", result = tmp_result);
2687 tmp_result = polaris10_power_control_set_level(hwmgr);
2688 PP_ASSERT_WITH_CODE((0 == tmp_result),
2689 "Failed to power control set level!", result = tmp_result);
2691 tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
2692 PP_ASSERT_WITH_CODE((0 == tmp_result),
2693 "Failed to enable thermal auto throttle!", result = tmp_result);
2695 tmp_result = polaris10_pcie_performance_request(hwmgr);
2696 PP_ASSERT_WITH_CODE((0 == tmp_result),
2697 "pcie performance request failed!", result = tmp_result);
2702 int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2704 int tmp_result, result = 0;
2706 tmp_result = (polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2707 PP_ASSERT_WITH_CODE(tmp_result == 0,
2708 "DPM is not running right now, no need to disable DPM!",
2711 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2712 PHM_PlatformCaps_ThermalController))
2713 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2714 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
2716 tmp_result = polaris10_disable_power_containment(hwmgr);
2717 PP_ASSERT_WITH_CODE((tmp_result == 0),
2718 "Failed to disable power containment!", result = tmp_result);
2720 tmp_result = polaris10_disable_smc_cac(hwmgr);
2721 PP_ASSERT_WITH_CODE((tmp_result == 0),
2722 "Failed to disable SMC CAC!", result = tmp_result);
2724 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2725 CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
2726 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2727 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
2729 tmp_result = polaris10_disable_thermal_auto_throttle(hwmgr);
2730 PP_ASSERT_WITH_CODE((tmp_result == 0),
2731 "Failed to disable thermal auto throttle!", result = tmp_result);
2733 tmp_result = polaris10_stop_dpm(hwmgr);
2734 PP_ASSERT_WITH_CODE((tmp_result == 0),
2735 "Failed to stop DPM!", result = tmp_result);
2737 tmp_result = polaris10_disable_deep_sleep_master_switch(hwmgr);
2738 PP_ASSERT_WITH_CODE((tmp_result == 0),
2739 "Failed to disable deep sleep master switch!", result = tmp_result);
2741 tmp_result = polaris10_disable_ulv(hwmgr);
2742 PP_ASSERT_WITH_CODE((tmp_result == 0),
2743 "Failed to disable ULV!", result = tmp_result);
2745 tmp_result = polaris10_clear_voting_clients(hwmgr);
2746 PP_ASSERT_WITH_CODE((tmp_result == 0),
2747 "Failed to clear voting clients!", result = tmp_result);
2749 tmp_result = polaris10_reset_to_default(hwmgr);
2750 PP_ASSERT_WITH_CODE((tmp_result == 0),
2751 "Failed to reset to default!", result = tmp_result);
2753 tmp_result = polaris10_force_switch_to_arbf0(hwmgr);
2754 PP_ASSERT_WITH_CODE((tmp_result == 0),
2755 "Failed to force to switch arbf0!", result = tmp_result);
2760 int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
2766 int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2768 return phm_hwmgr_backend_fini(hwmgr);
2771 int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
2773 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2775 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2776 PHM_PlatformCaps_SclkDeepSleep);
2778 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2779 PHM_PlatformCaps_DynamicPatchPowerState);
2781 if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2782 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2783 PHM_PlatformCaps_EnableMVDDControl);
2785 if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2786 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2787 PHM_PlatformCaps_ControlVDDCI);
2789 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2790 PHM_PlatformCaps_TablelessHardwareInterface);
2792 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2793 PHM_PlatformCaps_EnableSMU7ThermalManagement);
2795 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2796 PHM_PlatformCaps_DynamicPowerManagement);
2798 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2799 PHM_PlatformCaps_UnTabledHardwareInterface);
2801 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2802 PHM_PlatformCaps_TablelessHardwareInterface);
2804 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2805 PHM_PlatformCaps_SMC);
2807 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2808 PHM_PlatformCaps_NonABMSupportInPPLib);
2810 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2811 PHM_PlatformCaps_DynamicUVDState);
2813 /* power tune caps Assume disabled */
2814 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2815 PHM_PlatformCaps_SQRamping);
2816 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2817 PHM_PlatformCaps_DBRamping);
2818 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2819 PHM_PlatformCaps_TDRamping);
2820 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2821 PHM_PlatformCaps_TCPRamping);
2823 if (hwmgr->powercontainment_enabled)
2824 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2825 PHM_PlatformCaps_PowerContainment);
2827 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2828 PHM_PlatformCaps_PowerContainment);
2830 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2831 PHM_PlatformCaps_CAC);
2833 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2834 PHM_PlatformCaps_RegulatorHot);
2836 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2837 PHM_PlatformCaps_AutomaticDCTransition);
2839 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2840 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2842 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2843 PHM_PlatformCaps_FanSpeedInTableIsRPM);
2845 if (hwmgr->chip_id == CHIP_POLARIS11)
2846 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2847 PHM_PlatformCaps_SPLLShutdownSupport);
2851 static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
2853 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2855 polaris10_initialize_power_tune_defaults(hwmgr);
2857 data->pcie_gen_performance.max = PP_PCIEGen1;
2858 data->pcie_gen_performance.min = PP_PCIEGen3;
2859 data->pcie_gen_power_saving.max = PP_PCIEGen1;
2860 data->pcie_gen_power_saving.min = PP_PCIEGen3;
2861 data->pcie_lane_performance.max = 0;
2862 data->pcie_lane_performance.min = 16;
2863 data->pcie_lane_power_saving.max = 0;
2864 data->pcie_lane_power_saving.min = 16;
2868 * Get Leakage VDDC based on leakage ID.
2870 * @param hwmgr the address of the powerplay hardware manager.
2873 static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
2875 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2880 struct phm_ppt_v1_information *table_info =
2881 (struct phm_ppt_v1_information *)hwmgr->pptable;
2882 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2883 table_info->vdd_dep_on_sclk;
2886 for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
2887 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2888 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2889 table_info->vddc_lookup_table, vv_id, &sclk)) {
2890 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2891 PHM_PlatformCaps_ClockStretcher)) {
2892 for (j = 1; j < sclk_table->count; j++) {
2893 if (sclk_table->entries[j].clk == sclk &&
2894 sclk_table->entries[j].cks_enable == 0) {
2901 if (atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2903 sclk, vv_id, &vddc) != 0) {
2904 printk(KERN_WARNING "failed to retrieving EVV voltage!\n");
2908 /* need to make sure vddc is less than 2v or else, it could burn the ASIC.
2909 * real voltage level in unit of 0.01mv */
2910 PP_ASSERT_WITH_CODE((vddc < 200000 && vddc != 0),
2911 "Invalid VDDC value", result = -EINVAL;);
2913 /* the voltage should not be zero nor equal to leakage ID */
2914 if (vddc != 0 && vddc != vv_id) {
2915 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2916 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2917 data->vddc_leakage.count++;
2926 * Change virtual leakage voltage to actual value.
2928 * @param hwmgr the address of the powerplay hardware manager.
2929 * @param pointer to changing voltage
2930 * @param pointer to leakage table
2932 static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2933 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
2937 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2938 for (index = 0; index < leakage_table->count; index++) {
2939 /* if this voltage matches a leakage voltage ID */
2940 /* patch with actual leakage voltage */
2941 if (leakage_table->leakage_id[index] == *voltage) {
2942 *voltage = leakage_table->actual_voltage[index];
2947 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2948 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2952 * Patch voltage lookup table by EVV leakages.
2954 * @param hwmgr the address of the powerplay hardware manager.
2955 * @param pointer to voltage lookup table
2956 * @param pointer to leakage table
2959 static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
2960 phm_ppt_v1_voltage_lookup_table *lookup_table,
2961 struct polaris10_leakage_voltage *leakage_table)
2965 for (i = 0; i < lookup_table->count; i++)
2966 polaris10_patch_with_vdd_leakage(hwmgr,
2967 &lookup_table->entries[i].us_vdd, leakage_table);
2972 static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2973 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
2976 struct phm_ppt_v1_information *table_info =
2977 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2978 polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
2979 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2980 table_info->max_clock_voltage_on_dc.vddc;
2984 static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
2985 struct pp_hwmgr *hwmgr)
2989 struct phm_ppt_v1_information *table_info =
2990 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2992 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2993 table_info->vdd_dep_on_sclk;
2994 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2995 table_info->vdd_dep_on_mclk;
2996 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2997 table_info->mm_dep_table;
2999 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3000 voltageId = sclk_table->entries[entryId].vddInd;
3001 sclk_table->entries[entryId].vddc =
3002 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
3005 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
3006 voltageId = mclk_table->entries[entryId].vddInd;
3007 mclk_table->entries[entryId].vddc =
3008 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
3011 for (entryId = 0; entryId < mm_table->count; ++entryId) {
3012 voltageId = mm_table->entries[entryId].vddcInd;
3013 mm_table->entries[entryId].vddc =
3014 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
3021 static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
3023 /* Need to determine if we need calculated voltage. */
3027 static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
3029 /* Need to determine if we need calculated voltage from mm table. */
3033 static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
3034 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
3036 uint32_t table_size, i, j;
3037 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
3038 table_size = lookup_table->count;
3040 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
3041 "Lookup table is empty", return -EINVAL);
3043 /* Sorting voltages */
3044 for (i = 0; i < table_size - 1; i++) {
3045 for (j = i + 1; j > 0; j--) {
3046 if (lookup_table->entries[j].us_vdd <
3047 lookup_table->entries[j - 1].us_vdd) {
3048 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
3049 lookup_table->entries[j - 1] = lookup_table->entries[j];
3050 lookup_table->entries[j] = tmp_voltage_lookup_record;
3058 static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
3062 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3063 struct phm_ppt_v1_information *table_info =
3064 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3066 tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
3067 table_info->vddc_lookup_table, &(data->vddc_leakage));
3069 result = tmp_result;
3071 tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
3072 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
3074 result = tmp_result;
3076 tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
3078 result = tmp_result;
3080 tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
3082 result = tmp_result;
3084 tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
3086 result = tmp_result;
3088 tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
3090 result = tmp_result;
3095 static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
3097 struct phm_ppt_v1_information *table_info =
3098 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3100 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
3101 table_info->vdd_dep_on_sclk;
3102 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
3103 table_info->vdd_dep_on_mclk;
3105 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
3106 "VDD dependency on SCLK table is missing. \
3107 This table is mandatory", return -EINVAL);
3108 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
3109 "VDD dependency on SCLK table has to have is missing. \
3110 This table is mandatory", return -EINVAL);
3112 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
3113 "VDD dependency on MCLK table is missing. \
3114 This table is mandatory", return -EINVAL);
3115 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
3116 "VDD dependency on MCLK table has to have is missing. \
3117 This table is mandatory", return -EINVAL);
3119 table_info->max_clock_voltage_on_ac.sclk =
3120 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
3121 table_info->max_clock_voltage_on_ac.mclk =
3122 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
3123 table_info->max_clock_voltage_on_ac.vddc =
3124 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3125 table_info->max_clock_voltage_on_ac.vddci =
3126 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
3128 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
3129 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
3130 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
3131 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
3136 int polaris10_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
3138 struct phm_ppt_v1_information *table_info =
3139 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3140 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3141 table_info->vdd_dep_on_mclk;
3142 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
3143 table_info->vddc_lookup_table;
3146 if (hwmgr->chip_id == CHIP_POLARIS10 && hwmgr->hw_revision == 0xC7) {
3147 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
3150 for (i = 0; i < lookup_table->count; i++) {
3151 if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) {
3152 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;
3161 int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
3163 struct polaris10_hwmgr *data;
3164 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
3167 struct phm_ppt_v1_information *table_info =
3168 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3170 data = kzalloc(sizeof(struct polaris10_hwmgr), GFP_KERNEL);
3174 hwmgr->backend = data;
3176 data->dll_default_on = false;
3177 data->sram_end = SMC_RAM_END;
3178 data->mclk_dpm0_activity_target = 0xa;
3179 data->disable_dpm_mask = 0xFF;
3180 data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
3181 data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
3182 data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3183 data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3184 data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3185 data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3186 data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3187 data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3188 data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3189 data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3191 data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
3192 data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
3193 data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
3194 data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
3195 data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
3196 data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
3197 data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
3198 data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
3200 data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
3202 data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
3204 /* need to set voltage control types before EVV patching */
3205 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3206 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3207 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3209 data->enable_tdc_limit_feature = true;
3210 data->enable_pkg_pwr_tracking_feature = true;
3211 data->force_pcie_gen = PP_PCIEGenInvalid;
3212 data->mclk_stutter_mode_threshold = 40000;
3214 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3215 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
3216 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3218 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3219 PHM_PlatformCaps_EnableMVDDControl)) {
3220 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3221 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
3222 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
3223 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3224 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
3225 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3228 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3229 PHM_PlatformCaps_ControlVDDCI)) {
3230 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3231 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
3232 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
3233 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3234 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
3235 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3238 if (table_info->cac_dtp_table->usClockStretchAmount != 0)
3239 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3240 PHM_PlatformCaps_ClockStretcher);
3242 polaris10_set_features_platform_caps(hwmgr);
3244 polaris10_patch_voltage_workaround(hwmgr);
3245 polaris10_init_dpm_defaults(hwmgr);
3247 /* Get leakage voltage based on leakage ID. */
3248 result = polaris10_get_evv_voltages(hwmgr);
3251 printk("Get EVV Voltage Failed. Abort Driver loading!\n");
3255 polaris10_complete_dependency_tables(hwmgr);
3256 polaris10_set_private_data_based_on_pptable(hwmgr);
3258 /* Initalize Dynamic State Adjustment Rule Settings */
3259 result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
3262 struct cgs_system_info sys_info = {0};
3264 data->is_tlu_enabled = 0;
3266 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
3267 POLARIS10_MAX_HARDWARE_POWERLEVELS;
3268 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3269 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
3272 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
3273 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
3274 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
3276 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3279 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3282 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3285 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3288 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3291 PP_ASSERT_WITH_CODE(0,
3292 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3296 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3299 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
3300 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
3301 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
3302 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3304 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
3305 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3307 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
3309 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
3311 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
3312 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3314 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
3316 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
3317 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
3319 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3320 table_info->cac_dtp_table->usOperatingTempStep = 1;
3321 table_info->cac_dtp_table->usOperatingTempHyst = 1;
3323 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
3324 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3326 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
3327 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
3329 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
3330 table_info->cac_dtp_table->usOperatingTempMinLimit;
3332 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
3333 table_info->cac_dtp_table->usOperatingTempMaxLimit;
3335 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
3336 table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3338 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
3339 table_info->cac_dtp_table->usOperatingTempStep;
3341 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
3342 table_info->cac_dtp_table->usTargetOperatingTemp;
3345 sys_info.size = sizeof(struct cgs_system_info);
3346 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3347 result = cgs_query_system_info(hwmgr->device, &sys_info);
3349 data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3351 data->pcie_gen_cap = (uint32_t)sys_info.value;
3352 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3353 data->pcie_spc_cap = 20;
3354 sys_info.size = sizeof(struct cgs_system_info);
3355 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3356 result = cgs_query_system_info(hwmgr->device, &sys_info);
3358 data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3360 data->pcie_lane_cap = (uint32_t)sys_info.value;
3362 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3363 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3364 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3365 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
3367 /* Ignore return value in here, we are cleaning up a mess. */
3368 polaris10_hwmgr_backend_fini(hwmgr);
3374 static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3376 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3377 uint32_t level, tmp;
3379 if (!data->pcie_dpm_key_disabled) {
3380 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3382 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3387 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3388 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3392 if (!data->sclk_dpm_key_disabled) {
3393 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3395 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3400 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3401 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3406 if (!data->mclk_dpm_key_disabled) {
3407 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3409 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3414 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3415 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3423 static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3425 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3427 phm_apply_dal_min_voltage_request(hwmgr);
3429 if (!data->sclk_dpm_key_disabled) {
3430 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3431 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3432 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3433 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3436 if (!data->mclk_dpm_key_disabled) {
3437 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3438 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3439 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3440 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3446 static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3448 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3450 if (!polaris10_is_dpm_running(hwmgr))
3453 if (!data->pcie_dpm_key_disabled) {
3454 smum_send_msg_to_smc(hwmgr->smumgr,
3455 PPSMC_MSG_PCIeDPM_UnForceLevel);
3458 return polaris10_upload_dpm_level_enable_mask(hwmgr);
3461 static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3463 struct polaris10_hwmgr *data =
3464 (struct polaris10_hwmgr *)(hwmgr->backend);
3467 if (!data->sclk_dpm_key_disabled)
3468 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3469 level = phm_get_lowest_enabled_level(hwmgr,
3470 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3471 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3472 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3477 if (!data->mclk_dpm_key_disabled) {
3478 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3479 level = phm_get_lowest_enabled_level(hwmgr,
3480 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3481 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3482 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3487 if (!data->pcie_dpm_key_disabled) {
3488 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3489 level = phm_get_lowest_enabled_level(hwmgr,
3490 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3491 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3492 PPSMC_MSG_PCIeDPM_ForceLevel,
3500 static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
3501 enum amd_dpm_forced_level level)
3506 case AMD_DPM_FORCED_LEVEL_HIGH:
3507 ret = polaris10_force_dpm_highest(hwmgr);
3511 case AMD_DPM_FORCED_LEVEL_LOW:
3512 ret = polaris10_force_dpm_lowest(hwmgr);
3516 case AMD_DPM_FORCED_LEVEL_AUTO:
3517 ret = polaris10_unforce_dpm_levels(hwmgr);
3525 hwmgr->dpm_level = level;
3530 static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
3532 return sizeof(struct polaris10_power_state);
3536 static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3537 struct pp_power_state *request_ps,
3538 const struct pp_power_state *current_ps)
3541 struct polaris10_power_state *polaris10_ps =
3542 cast_phw_polaris10_power_state(&request_ps->hardware);
3545 struct PP_Clocks minimum_clocks = {0};
3546 bool disable_mclk_switching;
3547 bool disable_mclk_switching_for_frame_lock;
3548 struct cgs_display_info info = {0};
3549 const struct phm_clock_and_voltage_limits *max_limits;
3551 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3552 struct phm_ppt_v1_information *table_info =
3553 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3555 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3557 data->battery_state = (PP_StateUILabel_Battery ==
3558 request_ps->classification.ui_label);
3560 PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
3561 "VI should always have 2 performance levels",
3564 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3565 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3566 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3568 /* Cap clock DPM tables at DC MAX if it is in DC. */
3569 if (PP_PowerSource_DC == hwmgr->power_source) {
3570 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3571 if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3572 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3573 if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3574 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
3578 polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3579 polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3581 cgs_get_active_displays_info(hwmgr->device, &info);
3583 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3585 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3587 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3588 PHM_PlatformCaps_StablePState)) {
3589 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3590 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3592 for (count = table_info->vdd_dep_on_sclk->count - 1;
3593 count >= 0; count--) {
3594 if (stable_pstate_sclk >=
3595 table_info->vdd_dep_on_sclk->entries[count].clk) {
3596 stable_pstate_sclk =
3597 table_info->vdd_dep_on_sclk->entries[count].clk;
3603 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3605 stable_pstate_mclk = max_limits->mclk;
3607 minimum_clocks.engineClock = stable_pstate_sclk;
3608 minimum_clocks.memoryClock = stable_pstate_mclk;
3611 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3612 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3614 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3615 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3617 polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3619 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3620 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3621 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3622 "Overdrive sclk exceeds limit",
3623 hwmgr->gfx_arbiter.sclk_over_drive =
3624 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3626 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3627 polaris10_ps->performance_levels[1].engine_clock =
3628 hwmgr->gfx_arbiter.sclk_over_drive;
3631 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3632 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3633 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3634 "Overdrive mclk exceeds limit",
3635 hwmgr->gfx_arbiter.mclk_over_drive =
3636 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3638 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3639 polaris10_ps->performance_levels[1].memory_clock =
3640 hwmgr->gfx_arbiter.mclk_over_drive;
3643 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3644 hwmgr->platform_descriptor.platformCaps,
3645 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3647 disable_mclk_switching = (1 < info.display_count) ||
3648 disable_mclk_switching_for_frame_lock;
3650 sclk = polaris10_ps->performance_levels[0].engine_clock;
3651 mclk = polaris10_ps->performance_levels[0].memory_clock;
3653 if (disable_mclk_switching)
3654 mclk = polaris10_ps->performance_levels
3655 [polaris10_ps->performance_level_count - 1].memory_clock;
3657 if (sclk < minimum_clocks.engineClock)
3658 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3659 max_limits->sclk : minimum_clocks.engineClock;
3661 if (mclk < minimum_clocks.memoryClock)
3662 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3663 max_limits->mclk : minimum_clocks.memoryClock;
3665 polaris10_ps->performance_levels[0].engine_clock = sclk;
3666 polaris10_ps->performance_levels[0].memory_clock = mclk;
3668 polaris10_ps->performance_levels[1].engine_clock =
3669 (polaris10_ps->performance_levels[1].engine_clock >=
3670 polaris10_ps->performance_levels[0].engine_clock) ?
3671 polaris10_ps->performance_levels[1].engine_clock :
3672 polaris10_ps->performance_levels[0].engine_clock;
3674 if (disable_mclk_switching) {
3675 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3676 mclk = polaris10_ps->performance_levels[1].memory_clock;
3678 polaris10_ps->performance_levels[0].memory_clock = mclk;
3679 polaris10_ps->performance_levels[1].memory_clock = mclk;
3681 if (polaris10_ps->performance_levels[1].memory_clock <
3682 polaris10_ps->performance_levels[0].memory_clock)
3683 polaris10_ps->performance_levels[1].memory_clock =
3684 polaris10_ps->performance_levels[0].memory_clock;
3687 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3688 PHM_PlatformCaps_StablePState)) {
3689 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3690 polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3691 polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3692 polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3693 polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3700 static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3702 struct pp_power_state *ps;
3703 struct polaris10_power_state *polaris10_ps;
3708 ps = hwmgr->request_ps;
3713 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3716 return polaris10_ps->performance_levels[0].memory_clock;
3718 return polaris10_ps->performance_levels
3719 [polaris10_ps->performance_level_count-1].memory_clock;
3722 static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3724 struct pp_power_state *ps;
3725 struct polaris10_power_state *polaris10_ps;
3730 ps = hwmgr->request_ps;
3735 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3738 return polaris10_ps->performance_levels[0].engine_clock;
3740 return polaris10_ps->performance_levels
3741 [polaris10_ps->performance_level_count-1].engine_clock;
3744 static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3745 struct pp_hw_power_state *hw_ps)
3747 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3748 struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
3749 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3752 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3754 /* First retrieve the Boot clocks and VDDC from the firmware info table.
3755 * We assume here that fw_info is unchanged if this call fails.
3757 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3758 hwmgr->device, index,
3759 &size, &frev, &crev);
3761 /* During a test, there is no firmware info table. */
3764 /* Patch the state. */
3765 data->vbios_boot_state.sclk_bootup_value =
3766 le32_to_cpu(fw_info->ulDefaultEngineClock);
3767 data->vbios_boot_state.mclk_bootup_value =
3768 le32_to_cpu(fw_info->ulDefaultMemoryClock);
3769 data->vbios_boot_state.mvdd_bootup_value =
3770 le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3771 data->vbios_boot_state.vddc_bootup_value =
3772 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3773 data->vbios_boot_state.vddci_bootup_value =
3774 le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3775 data->vbios_boot_state.pcie_gen_bootup_value =
3776 phm_get_current_pcie_speed(hwmgr);
3778 data->vbios_boot_state.pcie_lane_bootup_value =
3779 (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3781 /* set boot power state */
3782 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3783 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3784 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3785 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3790 static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3791 void *state, struct pp_power_state *power_state,
3792 void *pp_table, uint32_t classification_flag)
3794 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3795 struct polaris10_power_state *polaris10_power_state =
3796 (struct polaris10_power_state *)(&(power_state->hardware));
3797 struct polaris10_performance_level *performance_level;
3798 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3799 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3800 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3801 PPTable_Generic_SubTable_Header *sclk_dep_table =
3802 (PPTable_Generic_SubTable_Header *)
3803 (((unsigned long)powerplay_table) +
3804 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3806 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3807 (ATOM_Tonga_MCLK_Dependency_Table *)
3808 (((unsigned long)powerplay_table) +
3809 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3811 /* The following fields are not initialized here: id orderedList allStatesList */
3812 power_state->classification.ui_label =
3813 (le16_to_cpu(state_entry->usClassification) &
3814 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3815 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3816 power_state->classification.flags = classification_flag;
3817 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3819 power_state->classification.temporary_state = false;
3820 power_state->classification.to_be_deleted = false;
3822 power_state->validation.disallowOnDC =
3823 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3824 ATOM_Tonga_DISALLOW_ON_DC));
3826 power_state->pcie.lanes = 0;
3828 power_state->display.disableFrameModulation = false;
3829 power_state->display.limitRefreshrate = false;
3830 power_state->display.enableVariBright =
3831 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3832 ATOM_Tonga_ENABLE_VARIBRIGHT));
3834 power_state->validation.supportedPowerLevels = 0;
3835 power_state->uvd_clocks.VCLK = 0;
3836 power_state->uvd_clocks.DCLK = 0;
3837 power_state->temperatures.min = 0;
3838 power_state->temperatures.max = 0;
3840 performance_level = &(polaris10_power_state->performance_levels
3841 [polaris10_power_state->performance_level_count++]);
3843 PP_ASSERT_WITH_CODE(
3844 (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
3845 "Performance levels exceeds SMC limit!",
3848 PP_ASSERT_WITH_CODE(
3849 (polaris10_power_state->performance_level_count <=
3850 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3851 "Performance levels exceeds Driver limit!",
3854 /* Performance levels are arranged from low to high. */
3855 performance_level->memory_clock = mclk_dep_table->entries
3856 [state_entry->ucMemoryClockIndexLow].ulMclk;
3857 if (sclk_dep_table->ucRevId == 0)
3858 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3859 [state_entry->ucEngineClockIndexLow].ulSclk;
3860 else if (sclk_dep_table->ucRevId == 1)
3861 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3862 [state_entry->ucEngineClockIndexLow].ulSclk;
3863 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3864 state_entry->ucPCIEGenLow);
3865 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3866 state_entry->ucPCIELaneHigh);
3868 performance_level = &(polaris10_power_state->performance_levels
3869 [polaris10_power_state->performance_level_count++]);
3870 performance_level->memory_clock = mclk_dep_table->entries
3871 [state_entry->ucMemoryClockIndexHigh].ulMclk;
3873 if (sclk_dep_table->ucRevId == 0)
3874 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3875 [state_entry->ucEngineClockIndexHigh].ulSclk;
3876 else if (sclk_dep_table->ucRevId == 1)
3877 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3878 [state_entry->ucEngineClockIndexHigh].ulSclk;
3880 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3881 state_entry->ucPCIEGenHigh);
3882 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3883 state_entry->ucPCIELaneHigh);
3888 static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3889 unsigned long entry_index, struct pp_power_state *state)
3892 struct polaris10_power_state *ps;
3893 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3894 struct phm_ppt_v1_information *table_info =
3895 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3896 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3897 table_info->vdd_dep_on_mclk;
3899 state->hardware.magic = PHM_VIslands_Magic;
3901 ps = (struct polaris10_power_state *)(&state->hardware);
3903 result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3904 polaris10_get_pp_table_entry_callback_func);
3906 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3907 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3908 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3910 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3911 if (dep_mclk_table->entries[0].clk !=
3912 data->vbios_boot_state.mclk_bootup_value)
3913 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3914 "does not match VBIOS boot MCLK level");
3915 if (dep_mclk_table->entries[0].vddci !=
3916 data->vbios_boot_state.vddci_bootup_value)
3917 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3918 "does not match VBIOS boot VDDCI level");
3921 /* set DC compatible flag if this state supports DC */
3922 if (!state->validation.disallowOnDC)
3923 ps->dc_compatible = true;
3925 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3926 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3928 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3929 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3934 switch (state->classification.ui_label) {
3935 case PP_StateUILabel_Performance:
3936 data->use_pcie_performance_levels = true;
3937 for (i = 0; i < ps->performance_level_count; i++) {
3938 if (data->pcie_gen_performance.max <
3939 ps->performance_levels[i].pcie_gen)
3940 data->pcie_gen_performance.max =
3941 ps->performance_levels[i].pcie_gen;
3943 if (data->pcie_gen_performance.min >
3944 ps->performance_levels[i].pcie_gen)
3945 data->pcie_gen_performance.min =
3946 ps->performance_levels[i].pcie_gen;
3948 if (data->pcie_lane_performance.max <
3949 ps->performance_levels[i].pcie_lane)
3950 data->pcie_lane_performance.max =
3951 ps->performance_levels[i].pcie_lane;
3952 if (data->pcie_lane_performance.min >
3953 ps->performance_levels[i].pcie_lane)
3954 data->pcie_lane_performance.min =
3955 ps->performance_levels[i].pcie_lane;
3958 case PP_StateUILabel_Battery:
3959 data->use_pcie_power_saving_levels = true;
3961 for (i = 0; i < ps->performance_level_count; i++) {
3962 if (data->pcie_gen_power_saving.max <
3963 ps->performance_levels[i].pcie_gen)
3964 data->pcie_gen_power_saving.max =
3965 ps->performance_levels[i].pcie_gen;
3967 if (data->pcie_gen_power_saving.min >
3968 ps->performance_levels[i].pcie_gen)
3969 data->pcie_gen_power_saving.min =
3970 ps->performance_levels[i].pcie_gen;
3972 if (data->pcie_lane_power_saving.max <
3973 ps->performance_levels[i].pcie_lane)
3974 data->pcie_lane_power_saving.max =
3975 ps->performance_levels[i].pcie_lane;
3977 if (data->pcie_lane_power_saving.min >
3978 ps->performance_levels[i].pcie_lane)
3979 data->pcie_lane_power_saving.min =
3980 ps->performance_levels[i].pcie_lane;
3991 polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
3993 uint32_t sclk, mclk, activity_percent;
3995 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3997 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3999 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4001 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4003 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4004 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
4005 mclk / 100, sclk / 100);
4007 offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
4008 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
4009 activity_percent += 0x80;
4010 activity_percent >>= 8;
4012 seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
4014 seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
4016 seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
4019 static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
4021 const struct phm_set_power_state_input *states =
4022 (const struct phm_set_power_state_input *)input;
4023 const struct polaris10_power_state *polaris10_ps =
4024 cast_const_phw_polaris10_power_state(states->pnew_state);
4025 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4026 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4027 uint32_t sclk = polaris10_ps->performance_levels
4028 [polaris10_ps->performance_level_count - 1].engine_clock;
4029 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4030 uint32_t mclk = polaris10_ps->performance_levels
4031 [polaris10_ps->performance_level_count - 1].memory_clock;
4032 struct PP_Clocks min_clocks = {0};
4034 struct cgs_display_info info = {0};
4036 data->need_update_smu7_dpm_table = 0;
4038 for (i = 0; i < sclk_table->count; i++) {
4039 if (sclk == sclk_table->dpm_levels[i].value)
4043 if (i >= sclk_table->count)
4044 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4046 /* TODO: Check SCLK in DAL's minimum clocks
4047 * in case DeepSleep divider update is required.
4049 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
4050 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4051 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4052 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4055 for (i = 0; i < mclk_table->count; i++) {
4056 if (mclk == mclk_table->dpm_levels[i].value)
4060 if (i >= mclk_table->count)
4061 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4063 cgs_get_active_displays_info(hwmgr->device, &info);
4065 if (data->display_timing.num_existing_displays != info.display_count)
4066 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4071 static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
4072 const struct polaris10_power_state *polaris10_ps)
4075 uint32_t sclk, max_sclk = 0;
4076 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4077 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
4079 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
4080 sclk = polaris10_ps->performance_levels[i].engine_clock;
4081 if (max_sclk < sclk)
4085 for (i = 0; i < dpm_table->sclk_table.count; i++) {
4086 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
4087 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
4088 dpm_table->pcie_speed_table.dpm_levels
4089 [dpm_table->pcie_speed_table.count - 1].value :
4090 dpm_table->pcie_speed_table.dpm_levels[i].value);
4096 static int polaris10_request_link_speed_change_before_state_change(
4097 struct pp_hwmgr *hwmgr, const void *input)
4099 const struct phm_set_power_state_input *states =
4100 (const struct phm_set_power_state_input *)input;
4101 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4102 const struct polaris10_power_state *polaris10_nps =
4103 cast_const_phw_polaris10_power_state(states->pnew_state);
4104 const struct polaris10_power_state *polaris10_cps =
4105 cast_const_phw_polaris10_power_state(states->pcurrent_state);
4107 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
4108 uint16_t current_link_speed;
4110 if (data->force_pcie_gen == PP_PCIEGenInvalid)
4111 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
4113 current_link_speed = data->force_pcie_gen;
4115 data->force_pcie_gen = PP_PCIEGenInvalid;
4116 data->pspp_notify_required = false;
4118 if (target_link_speed > current_link_speed) {
4119 switch (target_link_speed) {
4121 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
4123 data->force_pcie_gen = PP_PCIEGen2;
4124 if (current_link_speed == PP_PCIEGen2)
4127 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
4130 data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
4134 if (target_link_speed < current_link_speed)
4135 data->pspp_notify_required = true;
4141 static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4143 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4145 if (0 == data->need_update_smu7_dpm_table)
4148 if ((0 == data->sclk_dpm_key_disabled) &&
4149 (data->need_update_smu7_dpm_table &
4150 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4151 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4152 "Trying to freeze SCLK DPM when DPM is disabled",
4154 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4155 PPSMC_MSG_SCLKDPM_FreezeLevel),
4156 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4160 if ((0 == data->mclk_dpm_key_disabled) &&
4161 (data->need_update_smu7_dpm_table &
4162 DPMTABLE_OD_UPDATE_MCLK)) {
4163 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4164 "Trying to freeze MCLK DPM when DPM is disabled",
4166 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4167 PPSMC_MSG_MCLKDPM_FreezeLevel),
4168 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4175 static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
4176 struct pp_hwmgr *hwmgr, const void *input)
4179 const struct phm_set_power_state_input *states =
4180 (const struct phm_set_power_state_input *)input;
4181 const struct polaris10_power_state *polaris10_ps =
4182 cast_const_phw_polaris10_power_state(states->pnew_state);
4183 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4184 uint32_t sclk = polaris10_ps->performance_levels
4185 [polaris10_ps->performance_level_count - 1].engine_clock;
4186 uint32_t mclk = polaris10_ps->performance_levels
4187 [polaris10_ps->performance_level_count - 1].memory_clock;
4188 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
4190 struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
4191 uint32_t dpm_count, clock_percent;
4194 if (0 == data->need_update_smu7_dpm_table)
4197 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4198 dpm_table->sclk_table.dpm_levels
4199 [dpm_table->sclk_table.count - 1].value = sclk;
4201 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4202 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4203 /* Need to do calculation based on the golden DPM table
4204 * as the Heatmap GPU Clock axis is also based on the default values
4206 PP_ASSERT_WITH_CODE(
4207 (golden_dpm_table->sclk_table.dpm_levels
4208 [golden_dpm_table->sclk_table.count - 1].value != 0),
4211 dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
4213 for (i = dpm_count; i > 1; i--) {
4214 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
4217 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
4219 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4221 dpm_table->sclk_table.dpm_levels[i].value =
4222 golden_dpm_table->sclk_table.dpm_levels[i].value +
4223 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4226 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
4228 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
4230 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4232 dpm_table->sclk_table.dpm_levels[i].value =
4233 golden_dpm_table->sclk_table.dpm_levels[i].value -
4234 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4235 clock_percent) / 100;
4237 dpm_table->sclk_table.dpm_levels[i].value =
4238 golden_dpm_table->sclk_table.dpm_levels[i].value;
4243 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4244 dpm_table->mclk_table.dpm_levels
4245 [dpm_table->mclk_table.count - 1].value = mclk;
4247 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4248 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4250 PP_ASSERT_WITH_CODE(
4251 (golden_dpm_table->mclk_table.dpm_levels
4252 [golden_dpm_table->mclk_table.count-1].value != 0),
4255 dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
4256 for (i = dpm_count; i > 1; i--) {
4257 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
4258 clock_percent = ((mclk -
4259 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
4260 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4262 dpm_table->mclk_table.dpm_levels[i].value =
4263 golden_dpm_table->mclk_table.dpm_levels[i].value +
4264 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4265 clock_percent) / 100;
4267 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
4269 (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
4271 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4273 dpm_table->mclk_table.dpm_levels[i].value =
4274 golden_dpm_table->mclk_table.dpm_levels[i].value -
4275 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4276 clock_percent) / 100;
4278 dpm_table->mclk_table.dpm_levels[i].value =
4279 golden_dpm_table->mclk_table.dpm_levels[i].value;
4284 if (data->need_update_smu7_dpm_table &
4285 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4286 result = polaris10_populate_all_graphic_levels(hwmgr);
4287 PP_ASSERT_WITH_CODE((0 == result),
4288 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4292 if (data->need_update_smu7_dpm_table &
4293 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4294 /*populate MCLK dpm table to SMU7 */
4295 result = polaris10_populate_all_memory_levels(hwmgr);
4296 PP_ASSERT_WITH_CODE((0 == result),
4297 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4304 static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4305 struct polaris10_single_dpm_table *dpm_table,
4306 uint32_t low_limit, uint32_t high_limit)
4310 for (i = 0; i < dpm_table->count; i++) {
4311 if ((dpm_table->dpm_levels[i].value < low_limit)
4312 || (dpm_table->dpm_levels[i].value > high_limit))
4313 dpm_table->dpm_levels[i].enabled = false;
4315 dpm_table->dpm_levels[i].enabled = true;
4321 static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
4322 const struct polaris10_power_state *polaris10_ps)
4325 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4326 uint32_t high_limit_count;
4328 PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
4329 "power state did not have any performance level",
4332 high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
4334 polaris10_trim_single_dpm_states(hwmgr,
4335 &(data->dpm_table.sclk_table),
4336 polaris10_ps->performance_levels[0].engine_clock,
4337 polaris10_ps->performance_levels[high_limit_count].engine_clock);
4339 polaris10_trim_single_dpm_states(hwmgr,
4340 &(data->dpm_table.mclk_table),
4341 polaris10_ps->performance_levels[0].memory_clock,
4342 polaris10_ps->performance_levels[high_limit_count].memory_clock);
4347 static int polaris10_generate_dpm_level_enable_mask(
4348 struct pp_hwmgr *hwmgr, const void *input)
4351 const struct phm_set_power_state_input *states =
4352 (const struct phm_set_power_state_input *)input;
4353 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4354 const struct polaris10_power_state *polaris10_ps =
4355 cast_const_phw_polaris10_power_state(states->pnew_state);
4357 result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
4361 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4362 phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4363 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4364 phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4365 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4366 phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4371 int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4373 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4374 PPSMC_MSG_UVDDPM_Enable :
4375 PPSMC_MSG_UVDDPM_Disable);
4378 int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4380 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4381 PPSMC_MSG_VCEDPM_Enable :
4382 PPSMC_MSG_VCEDPM_Disable);
4385 int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4387 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4388 PPSMC_MSG_SAMUDPM_Enable :
4389 PPSMC_MSG_SAMUDPM_Disable);
4392 int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4394 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4395 uint32_t mm_boot_level_offset, mm_boot_level_value;
4396 struct phm_ppt_v1_information *table_info =
4397 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4400 data->smc_state_table.UvdBootLevel = 0;
4401 if (table_info->mm_dep_table->count > 0)
4402 data->smc_state_table.UvdBootLevel =
4403 (uint8_t) (table_info->mm_dep_table->count - 1);
4404 mm_boot_level_offset = data->dpm_table_start +
4405 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4406 mm_boot_level_offset /= 4;
4407 mm_boot_level_offset *= 4;
4408 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4409 CGS_IND_REG__SMC, mm_boot_level_offset);
4410 mm_boot_level_value &= 0x00FFFFFF;
4411 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4412 cgs_write_ind_register(hwmgr->device,
4413 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4415 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4416 PHM_PlatformCaps_UVDDPM) ||
4417 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4418 PHM_PlatformCaps_StablePState))
4419 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4420 PPSMC_MSG_UVDDPM_SetEnabledMask,
4421 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4424 return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
4427 static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4429 const struct phm_set_power_state_input *states =
4430 (const struct phm_set_power_state_input *)input;
4431 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4432 const struct polaris10_power_state *polaris10_nps =
4433 cast_const_phw_polaris10_power_state(states->pnew_state);
4434 const struct polaris10_power_state *polaris10_cps =
4435 cast_const_phw_polaris10_power_state(states->pcurrent_state);
4437 uint32_t mm_boot_level_offset, mm_boot_level_value;
4438 struct phm_ppt_v1_information *table_info =
4439 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4441 if (polaris10_nps->vce_clks.evclk > 0 &&
4442 (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
4444 data->smc_state_table.VceBootLevel =
4445 (uint8_t) (table_info->mm_dep_table->count - 1);
4447 mm_boot_level_offset = data->dpm_table_start +
4448 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4449 mm_boot_level_offset /= 4;
4450 mm_boot_level_offset *= 4;
4451 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4452 CGS_IND_REG__SMC, mm_boot_level_offset);
4453 mm_boot_level_value &= 0xFF00FFFF;
4454 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4455 cgs_write_ind_register(hwmgr->device,
4456 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4458 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4459 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4460 PPSMC_MSG_VCEDPM_SetEnabledMask,
4461 (uint32_t)1 << data->smc_state_table.VceBootLevel);
4463 polaris10_enable_disable_vce_dpm(hwmgr, true);
4464 } else if (polaris10_nps->vce_clks.evclk == 0 &&
4465 polaris10_cps != NULL &&
4466 polaris10_cps->vce_clks.evclk > 0)
4467 polaris10_enable_disable_vce_dpm(hwmgr, false);
4473 int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4475 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4476 uint32_t mm_boot_level_offset, mm_boot_level_value;
4479 data->smc_state_table.SamuBootLevel = 0;
4480 mm_boot_level_offset = data->dpm_table_start +
4481 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4482 mm_boot_level_offset /= 4;
4483 mm_boot_level_offset *= 4;
4484 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4485 CGS_IND_REG__SMC, mm_boot_level_offset);
4486 mm_boot_level_value &= 0xFFFFFF00;
4487 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4488 cgs_write_ind_register(hwmgr->device,
4489 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4491 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4492 PHM_PlatformCaps_StablePState))
4493 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4494 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4495 (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4498 return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
4501 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4503 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4506 uint32_t low_sclk_interrupt_threshold = 0;
4508 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4509 PHM_PlatformCaps_SclkThrottleLowNotification)
4510 && (hwmgr->gfx_arbiter.sclk_threshold !=
4511 data->low_sclk_interrupt_threshold)) {
4512 data->low_sclk_interrupt_threshold =
4513 hwmgr->gfx_arbiter.sclk_threshold;
4514 low_sclk_interrupt_threshold =
4515 data->low_sclk_interrupt_threshold;
4517 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4519 result = polaris10_copy_bytes_to_smc(
4521 data->dpm_table_start +
4522 offsetof(SMU74_Discrete_DpmTable,
4523 LowSclkInterruptThreshold),
4524 (uint8_t *)&low_sclk_interrupt_threshold,
4532 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4534 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4536 if (data->need_update_smu7_dpm_table &
4537 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4538 return polaris10_program_memory_timing_parameters(hwmgr);
4543 static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4545 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4547 if (0 == data->need_update_smu7_dpm_table)
4550 if ((0 == data->sclk_dpm_key_disabled) &&
4551 (data->need_update_smu7_dpm_table &
4552 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4554 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4555 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4557 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4558 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4559 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4563 if ((0 == data->mclk_dpm_key_disabled) &&
4564 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4566 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4567 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4569 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4570 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4571 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4575 data->need_update_smu7_dpm_table = 0;
4580 static int polaris10_notify_link_speed_change_after_state_change(
4581 struct pp_hwmgr *hwmgr, const void *input)
4583 const struct phm_set_power_state_input *states =
4584 (const struct phm_set_power_state_input *)input;
4585 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4586 const struct polaris10_power_state *polaris10_ps =
4587 cast_const_phw_polaris10_power_state(states->pnew_state);
4588 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
4591 if (data->pspp_notify_required) {
4592 if (target_link_speed == PP_PCIEGen3)
4593 request = PCIE_PERF_REQ_GEN3;
4594 else if (target_link_speed == PP_PCIEGen2)
4595 request = PCIE_PERF_REQ_GEN2;
4597 request = PCIE_PERF_REQ_GEN1;
4599 if (request == PCIE_PERF_REQ_GEN1 &&
4600 phm_get_current_pcie_speed(hwmgr) > 0)
4603 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4604 if (PP_PCIEGen2 == target_link_speed)
4605 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4607 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4614 static int polaris10_notify_smc_display(struct pp_hwmgr *hwmgr)
4616 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4618 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4619 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2);
4620 return (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL;
4623 static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4625 int tmp_result, result = 0;
4626 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4628 tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4629 PP_ASSERT_WITH_CODE((0 == tmp_result),
4630 "Failed to find DPM states clocks in DPM table!",
4631 result = tmp_result);
4633 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4634 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4636 polaris10_request_link_speed_change_before_state_change(hwmgr, input);
4637 PP_ASSERT_WITH_CODE((0 == tmp_result),
4638 "Failed to request link speed change before state change!",
4639 result = tmp_result);
4642 tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
4643 PP_ASSERT_WITH_CODE((0 == tmp_result),
4644 "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4646 tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4647 PP_ASSERT_WITH_CODE((0 == tmp_result),
4648 "Failed to populate and upload SCLK MCLK DPM levels!",
4649 result = tmp_result);
4651 tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
4652 PP_ASSERT_WITH_CODE((0 == tmp_result),
4653 "Failed to generate DPM level enabled mask!",
4654 result = tmp_result);
4656 tmp_result = polaris10_update_vce_dpm(hwmgr, input);
4657 PP_ASSERT_WITH_CODE((0 == tmp_result),
4658 "Failed to update VCE DPM!",
4659 result = tmp_result);
4661 tmp_result = polaris10_update_sclk_threshold(hwmgr);
4662 PP_ASSERT_WITH_CODE((0 == tmp_result),
4663 "Failed to update SCLK threshold!",
4664 result = tmp_result);
4666 tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
4667 PP_ASSERT_WITH_CODE((0 == tmp_result),
4668 "Failed to program memory timing parameters!",
4669 result = tmp_result);
4671 tmp_result = polaris10_notify_smc_display(hwmgr);
4672 PP_ASSERT_WITH_CODE((0 == tmp_result),
4673 "Failed to notify smc display settings!",
4674 result = tmp_result);
4676 tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
4677 PP_ASSERT_WITH_CODE((0 == tmp_result),
4678 "Failed to unfreeze SCLK MCLK DPM!",
4679 result = tmp_result);
4681 tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
4682 PP_ASSERT_WITH_CODE((0 == tmp_result),
4683 "Failed to upload DPM level enabled mask!",
4684 result = tmp_result);
4686 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4687 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4689 polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
4690 PP_ASSERT_WITH_CODE((0 == tmp_result),
4691 "Failed to notify link speed change after state change!",
4692 result = tmp_result);
4694 data->apply_optimized_settings = false;
4698 static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4700 hwmgr->thermal_controller.
4701 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4703 if (phm_is_hw_access_blocked(hwmgr))
4706 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4707 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4711 int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4713 PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4715 return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
4718 int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4720 uint32_t num_active_displays = 0;
4721 struct cgs_display_info info = {0};
4722 info.mode_info = NULL;
4724 cgs_get_active_displays_info(hwmgr->device, &info);
4726 num_active_displays = info.display_count;
4728 if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
4729 polaris10_notify_smc_display_change(hwmgr, false);
4735 * Programs the display gap
4737 * @param hwmgr the address of the powerplay hardware manager.
4740 int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
4742 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4743 uint32_t num_active_displays = 0;
4744 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4745 uint32_t display_gap2;
4746 uint32_t pre_vbi_time_in_us;
4747 uint32_t frame_time_in_us;
4749 uint32_t refresh_rate = 0;
4750 struct cgs_display_info info = {0};
4751 struct cgs_mode_info mode_info;
4753 info.mode_info = &mode_info;
4755 cgs_get_active_displays_info(hwmgr->device, &info);
4756 num_active_displays = info.display_count;
4758 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4759 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4761 ref_clock = mode_info.ref_clock;
4762 refresh_rate = mode_info.refresh_rate;
4764 if (0 == refresh_rate)
4767 frame_time_in_us = 1000000 / refresh_rate;
4769 pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4770 data->frame_time_x2 = frame_time_in_us * 2 / 100;
4772 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4774 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4776 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4778 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4784 int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4786 return polaris10_program_display_gap(hwmgr);
4790 * Set maximum target operating fan output RPM
4792 * @param hwmgr: the address of the powerplay hardware manager.
4793 * @param usMaxFanRpm: max operating fan RPM value.
4794 * @return The response that came from the SMC.
4796 static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4798 hwmgr->thermal_controller.
4799 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4801 if (phm_is_hw_access_blocked(hwmgr))
4804 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4805 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4808 int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
4809 const void *thermal_interrupt_info)
4814 bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4816 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4817 bool is_update_required = false;
4818 struct cgs_display_info info = {0, 0, NULL};
4820 cgs_get_active_displays_info(hwmgr->device, &info);
4822 if (data->display_timing.num_existing_displays != info.display_count)
4823 is_update_required = true;
4824 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4825 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4826 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
4827 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4828 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4829 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4830 is_update_required = true;
4832 return is_update_required;
4835 static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4836 const struct polaris10_performance_level *pl2)
4838 return ((pl1->memory_clock == pl2->memory_clock) &&
4839 (pl1->engine_clock == pl2->engine_clock) &&
4840 (pl1->pcie_gen == pl2->pcie_gen) &&
4841 (pl1->pcie_lane == pl2->pcie_lane));
4844 int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
4846 const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4847 const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
4850 if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4853 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4854 if (psa->performance_level_count != psb->performance_level_count) {
4859 for (i = 0; i < psa->performance_level_count; i++) {
4860 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4861 /* If we have found even one performance level pair that is different the states are different. */
4867 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4868 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4869 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4870 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4875 int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
4877 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4879 uint32_t vbios_version;
4881 /* Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4883 phm_get_mc_microcode_version(hwmgr);
4884 vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4885 /* Full version of MC ucode has already been loaded. */
4886 if (vbios_version == 0) {
4887 data->need_long_memory_training = false;
4891 data->need_long_memory_training = false;
4894 * PPMCME_FirmwareDescriptorEntry *pfd = NULL;
4895 pfd = &tonga_mcmeFirmware;
4896 if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
4897 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
4898 pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4899 pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4905 * Read clock related registers.
4907 * @param hwmgr the address of the powerplay hardware manager.
4910 static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
4912 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4914 data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4915 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4916 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4918 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4919 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4920 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4922 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4923 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4924 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4930 * Find out if memory is GDDR5.
4932 * @param hwmgr the address of the powerplay hardware manager.
4935 static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
4937 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4940 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4942 data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4943 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4944 MC_SEQ_MISC0_GDDR5_SHIFT));
4950 * Enables Dynamic Power Management by SMC
4952 * @param hwmgr the address of the powerplay hardware manager.
4955 static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4957 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4958 GENERAL_PWRMGT, STATIC_PM_EN, 1);
4964 * Initialize PowerGating States for different engines
4966 * @param hwmgr the address of the powerplay hardware manager.
4969 static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
4971 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4973 data->uvd_power_gated = false;
4974 data->vce_power_gated = false;
4975 data->samu_power_gated = false;
4980 static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4982 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4983 data->low_sclk_interrupt_threshold = 0;
4988 int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
4990 int tmp_result, result = 0;
4992 polaris10_upload_mc_firmware(hwmgr);
4994 tmp_result = polaris10_read_clock_registers(hwmgr);
4995 PP_ASSERT_WITH_CODE((0 == tmp_result),
4996 "Failed to read clock registers!", result = tmp_result);
4998 tmp_result = polaris10_get_memory_type(hwmgr);
4999 PP_ASSERT_WITH_CODE((0 == tmp_result),
5000 "Failed to get memory type!", result = tmp_result);
5002 tmp_result = polaris10_enable_acpi_power_management(hwmgr);
5003 PP_ASSERT_WITH_CODE((0 == tmp_result),
5004 "Failed to enable ACPI power management!", result = tmp_result);
5006 tmp_result = polaris10_init_power_gate_state(hwmgr);
5007 PP_ASSERT_WITH_CODE((0 == tmp_result),
5008 "Failed to init power gate state!", result = tmp_result);
5010 tmp_result = phm_get_mc_microcode_version(hwmgr);
5011 PP_ASSERT_WITH_CODE((0 == tmp_result),
5012 "Failed to get MC microcode version!", result = tmp_result);
5014 tmp_result = polaris10_init_sclk_threshold(hwmgr);
5015 PP_ASSERT_WITH_CODE((0 == tmp_result),
5016 "Failed to init sclk threshold!", result = tmp_result);
5021 static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
5022 enum pp_clock_type type, uint32_t mask)
5024 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5026 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
5031 if (!data->sclk_dpm_key_disabled)
5032 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5033 PPSMC_MSG_SCLKDPM_SetEnabledMask,
5034 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
5037 if (!data->mclk_dpm_key_disabled)
5038 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5039 PPSMC_MSG_MCLKDPM_SetEnabledMask,
5040 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
5044 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
5050 if (!data->pcie_dpm_key_disabled)
5051 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5052 PPSMC_MSG_PCIeDPM_ForceLevel,
5063 static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
5065 uint32_t speedCntl = 0;
5067 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
5068 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
5069 ixPCIE_LC_SPEED_CNTL);
5070 return((uint16_t)PHM_GET_FIELD(speedCntl,
5071 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
5074 static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
5075 enum pp_clock_type type, char *buf)
5077 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5078 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5079 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5080 struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
5081 int i, now, size = 0;
5082 uint32_t clock, pcie_speed;
5086 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
5087 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5089 for (i = 0; i < sclk_table->count; i++) {
5090 if (clock > sclk_table->dpm_levels[i].value)
5096 for (i = 0; i < sclk_table->count; i++)
5097 size += sprintf(buf + size, "%d: %uMhz %s\n",
5098 i, sclk_table->dpm_levels[i].value / 100,
5099 (i == now) ? "*" : "");
5102 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
5103 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5105 for (i = 0; i < mclk_table->count; i++) {
5106 if (clock > mclk_table->dpm_levels[i].value)
5112 for (i = 0; i < mclk_table->count; i++)
5113 size += sprintf(buf + size, "%d: %uMhz %s\n",
5114 i, mclk_table->dpm_levels[i].value / 100,
5115 (i == now) ? "*" : "");
5118 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
5119 for (i = 0; i < pcie_table->count; i++) {
5120 if (pcie_speed != pcie_table->dpm_levels[i].value)
5126 for (i = 0; i < pcie_table->count; i++)
5127 size += sprintf(buf + size, "%d: %s %s\n", i,
5128 (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
5129 (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
5130 (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
5131 (i == now) ? "*" : "");
5139 static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
5142 /* stop auto-manage */
5143 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
5144 PHM_PlatformCaps_MicrocodeFanControl))
5145 polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
5146 polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
5148 /* restart auto-manage */
5149 polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
5154 static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
5156 if (hwmgr->fan_ctrl_is_in_default_mode)
5157 return hwmgr->fan_ctrl_default_mode;
5159 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
5160 CG_FDO_CTRL2, FDO_PWM_MODE);
5163 static int polaris10_get_sclk_od(struct pp_hwmgr *hwmgr)
5165 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5166 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5167 struct polaris10_single_dpm_table *golden_sclk_table =
5168 &(data->golden_dpm_table.sclk_table);
5171 value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
5172 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
5174 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5179 static int polaris10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5181 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5182 struct polaris10_single_dpm_table *golden_sclk_table =
5183 &(data->golden_dpm_table.sclk_table);
5184 struct pp_power_state *ps;
5185 struct polaris10_power_state *polaris10_ps;
5190 ps = hwmgr->request_ps;
5195 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
5197 polaris10_ps->performance_levels[polaris10_ps->performance_level_count - 1].engine_clock =
5198 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
5200 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5205 static int polaris10_get_mclk_od(struct pp_hwmgr *hwmgr)
5207 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5208 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5209 struct polaris10_single_dpm_table *golden_mclk_table =
5210 &(data->golden_dpm_table.mclk_table);
5213 value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
5214 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
5216 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5221 static int polaris10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5223 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5224 struct polaris10_single_dpm_table *golden_mclk_table =
5225 &(data->golden_dpm_table.mclk_table);
5226 struct pp_power_state *ps;
5227 struct polaris10_power_state *polaris10_ps;
5232 ps = hwmgr->request_ps;
5237 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
5239 polaris10_ps->performance_levels[polaris10_ps->performance_level_count - 1].memory_clock =
5240 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
5242 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5246 static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
5247 .backend_init = &polaris10_hwmgr_backend_init,
5248 .backend_fini = &polaris10_hwmgr_backend_fini,
5249 .asic_setup = &polaris10_setup_asic_task,
5250 .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
5251 .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
5252 .force_dpm_level = &polaris10_force_dpm_level,
5253 .power_state_set = polaris10_set_power_state_tasks,
5254 .get_power_state_size = polaris10_get_power_state_size,
5255 .get_mclk = polaris10_dpm_get_mclk,
5256 .get_sclk = polaris10_dpm_get_sclk,
5257 .patch_boot_state = polaris10_dpm_patch_boot_state,
5258 .get_pp_table_entry = polaris10_get_pp_table_entry,
5259 .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
5260 .print_current_perforce_level = polaris10_print_current_perforce_level,
5261 .powerdown_uvd = polaris10_phm_powerdown_uvd,
5262 .powergate_uvd = polaris10_phm_powergate_uvd,
5263 .powergate_vce = polaris10_phm_powergate_vce,
5264 .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
5265 .update_clock_gatings = polaris10_phm_update_clock_gatings,
5266 .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
5267 .display_config_changed = polaris10_display_configuration_changed_task,
5268 .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
5269 .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
5270 .get_temperature = polaris10_thermal_get_temperature,
5271 .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
5272 .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
5273 .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
5274 .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
5275 .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
5276 .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
5277 .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
5278 .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
5279 .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
5280 .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
5281 .check_states_equal = polaris10_check_states_equal,
5282 .set_fan_control_mode = polaris10_set_fan_control_mode,
5283 .get_fan_control_mode = polaris10_get_fan_control_mode,
5284 .force_clock_level = polaris10_force_clock_level,
5285 .print_clock_levels = polaris10_print_clock_levels,
5286 .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
5287 .get_sclk_od = polaris10_get_sclk_od,
5288 .set_sclk_od = polaris10_set_sclk_od,
5289 .get_mclk_od = polaris10_get_mclk_od,
5290 .set_mclk_od = polaris10_set_mclk_od,
5293 int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
5295 hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
5296 hwmgr->pptable_func = &tonga_pptable_funcs;
5297 pp_polaris10_thermal_initialize(hwmgr);