2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/module.h>
24 #include <linux/slab.h>
26 #include <asm/div64.h>
27 #include "linux/delay.h"
30 #include "polaris10_hwmgr.h"
31 #include "polaris10_powertune.h"
32 #include "polaris10_dyn_defaults.h"
33 #include "polaris10_smumgr.h"
35 #include "ppatomctrl.h"
37 #include "tonga_pptable.h"
38 #include "pppcielanes.h"
39 #include "amd_pcie_helpers.h"
40 #include "hardwaremanager.h"
41 #include "tonga_processpptables.h"
42 #include "cgs_common.h"
44 #include "smu_ucode_xfer_vi.h"
45 #include "smu74_discrete.h"
46 #include "smu/smu_7_1_3_d.h"
47 #include "smu/smu_7_1_3_sh_mask.h"
48 #include "gmc/gmc_8_1_d.h"
49 #include "gmc/gmc_8_1_sh_mask.h"
50 #include "oss/oss_3_0_d.h"
51 #include "gca/gfx_8_0_d.h"
52 #include "bif/bif_5_0_d.h"
53 #include "bif/bif_5_0_sh_mask.h"
54 #include "gmc/gmc_8_1_d.h"
55 #include "gmc/gmc_8_1_sh_mask.h"
56 #include "bif/bif_5_0_d.h"
57 #include "bif/bif_5_0_sh_mask.h"
58 #include "dce/dce_10_0_d.h"
59 #include "dce/dce_10_0_sh_mask.h"
61 #include "polaris10_thermal.h"
62 #include "polaris10_clockpowergating.h"
64 #define MC_CG_ARB_FREQ_F0 0x0a
65 #define MC_CG_ARB_FREQ_F1 0x0b
66 #define MC_CG_ARB_FREQ_F2 0x0c
67 #define MC_CG_ARB_FREQ_F3 0x0d
69 #define MC_CG_SEQ_DRAMCONF_S0 0x05
70 #define MC_CG_SEQ_DRAMCONF_S1 0x06
71 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
72 #define MC_CG_SEQ_YCLK_RESUME 0x0a
75 #define SMC_RAM_END 0x40000
77 #define SMC_CG_IND_START 0xc0030000
78 #define SMC_CG_IND_END 0xc0040000
80 #define VOLTAGE_SCALE 4
81 #define VOLTAGE_VID_OFFSET_SCALE1 625
82 #define VOLTAGE_VID_OFFSET_SCALE2 100
84 #define VDDC_VDDCI_DELTA 200
86 #define MEM_FREQ_LOW_LATENCY 25000
87 #define MEM_FREQ_HIGH_LATENCY 80000
89 #define MEM_LATENCY_HIGH 45
90 #define MEM_LATENCY_LOW 35
91 #define MEM_LATENCY_ERR 0xFFFF
93 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
94 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
95 #define MC_SEQ_MISC0_GDDR5_VALUE 5
98 #define PCIE_BUS_CLK 10000
99 #define TCLK (PCIE_BUS_CLK / 10)
102 static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
103 { {600, 1050, 3, 0}, {600, 1050, 6, 1} };
105 /* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
106 static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] =
107 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
108 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
110 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
111 static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] =
112 { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
114 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
116 DPM_EVENT_SRC_ANALOG = 0,
117 DPM_EVENT_SRC_EXTERNAL = 1,
118 DPM_EVENT_SRC_DIGITAL = 2,
119 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
120 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
123 static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
125 struct polaris10_power_state *cast_phw_polaris10_power_state(
126 struct pp_hw_power_state *hw_ps)
128 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
129 "Invalid Powerstate Type!",
132 return (struct polaris10_power_state *)hw_ps;
135 const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
136 const struct pp_hw_power_state *hw_ps)
138 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
139 "Invalid Powerstate Type!",
142 return (const struct polaris10_power_state *)hw_ps;
145 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
147 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
148 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
153 * Find the MC microcode version and store it in the HwMgr struct
155 * @param hwmgr the address of the powerplay hardware manager.
158 int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
160 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
162 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
167 uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
169 uint32_t speedCntl = 0;
171 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
172 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
173 ixPCIE_LC_SPEED_CNTL);
174 return((uint16_t)PHM_GET_FIELD(speedCntl,
175 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
178 int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
182 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
183 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
184 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
186 PP_ASSERT_WITH_CODE((7 >= link_width),
187 "Invalid PCIe lane width!", return 0);
189 return decode_pcie_lane_width(link_width);
193 * Enable voltage control
195 * @param pHwMgr the address of the powerplay hardware manager.
196 * @return always PP_Result_OK
198 int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
201 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
202 "Failed to enable voltage DPM during DPM Start Function!",
210 * Checks if we want to support voltage control
212 * @param hwmgr the address of the powerplay hardware manager.
214 static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
216 const struct polaris10_hwmgr *data =
217 (const struct polaris10_hwmgr *)(hwmgr->backend);
219 return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
223 * Enable voltage control
225 * @param hwmgr the address of the powerplay hardware manager.
228 static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
230 /* enable voltage control */
231 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
232 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
238 * Create Voltage Tables.
240 * @param hwmgr the address of the powerplay hardware manager.
243 static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
245 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
246 struct phm_ppt_v1_information *table_info =
247 (struct phm_ppt_v1_information *)hwmgr->pptable;
250 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
251 result = atomctrl_get_voltage_table_v3(hwmgr,
252 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
253 &(data->mvdd_voltage_table));
254 PP_ASSERT_WITH_CODE((0 == result),
255 "Failed to retrieve MVDD table.",
257 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
258 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
259 table_info->vdd_dep_on_mclk);
260 PP_ASSERT_WITH_CODE((0 == result),
261 "Failed to retrieve SVI2 MVDD table from dependancy table.",
265 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
266 result = atomctrl_get_voltage_table_v3(hwmgr,
267 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
268 &(data->vddci_voltage_table));
269 PP_ASSERT_WITH_CODE((0 == result),
270 "Failed to retrieve VDDCI table.",
272 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
273 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
274 table_info->vdd_dep_on_mclk);
275 PP_ASSERT_WITH_CODE((0 == result),
276 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
280 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
281 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
282 table_info->vddc_lookup_table);
283 PP_ASSERT_WITH_CODE((0 == result),
284 "Failed to retrieve SVI2 VDDC table from lookup table.",
289 (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
290 "Too many voltage values for VDDC. Trimming to fit state table.",
291 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
292 &(data->vddc_voltage_table)));
295 (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
296 "Too many voltage values for VDDCI. Trimming to fit state table.",
297 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
298 &(data->vddci_voltage_table)));
301 (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
302 "Too many voltage values for MVDD. Trimming to fit state table.",
303 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
304 &(data->mvdd_voltage_table)));
310 * Programs static screed detection parameters
312 * @param hwmgr the address of the powerplay hardware manager.
315 static int polaris10_program_static_screen_threshold_parameters(
316 struct pp_hwmgr *hwmgr)
318 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
320 /* Set static screen threshold unit */
321 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
322 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
323 data->static_screen_threshold_unit);
324 /* Set static screen threshold */
325 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
326 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
327 data->static_screen_threshold);
333 * Setup display gap for glitch free memory clock switching.
335 * @param hwmgr the address of the powerplay hardware manager.
338 static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
340 uint32_t display_gap =
341 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
342 ixCG_DISPLAY_GAP_CNTL);
344 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
345 DISP_GAP, DISPLAY_GAP_IGNORE);
347 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
348 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
350 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
351 ixCG_DISPLAY_GAP_CNTL, display_gap);
357 * Programs activity state transition voting clients
359 * @param hwmgr the address of the powerplay hardware manager.
362 static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
364 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
366 /* Clear reset for voting clients before enabling DPM */
367 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
368 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
369 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
370 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
372 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
373 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
374 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
375 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
376 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
377 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
378 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
379 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
380 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
381 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
382 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
383 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
384 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
385 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
386 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
387 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
393 * Get the location of various tables inside the FW image.
395 * @param hwmgr the address of the powerplay hardware manager.
398 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
400 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
401 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
406 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
407 SMU7_FIRMWARE_HEADER_LOCATION +
408 offsetof(SMU74_Firmware_Header, DpmTable),
409 &tmp, data->sram_end);
412 data->dpm_table_start = tmp;
414 error |= (0 != result);
416 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
417 SMU7_FIRMWARE_HEADER_LOCATION +
418 offsetof(SMU74_Firmware_Header, SoftRegisters),
419 &tmp, data->sram_end);
422 data->soft_regs_start = tmp;
423 smu_data->soft_regs_start = tmp;
426 error |= (0 != result);
428 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
429 SMU7_FIRMWARE_HEADER_LOCATION +
430 offsetof(SMU74_Firmware_Header, mcRegisterTable),
431 &tmp, data->sram_end);
434 data->mc_reg_table_start = tmp;
436 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
437 SMU7_FIRMWARE_HEADER_LOCATION +
438 offsetof(SMU74_Firmware_Header, FanTable),
439 &tmp, data->sram_end);
442 data->fan_table_start = tmp;
444 error |= (0 != result);
446 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
447 SMU7_FIRMWARE_HEADER_LOCATION +
448 offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
449 &tmp, data->sram_end);
452 data->arb_table_start = tmp;
454 error |= (0 != result);
456 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
457 SMU7_FIRMWARE_HEADER_LOCATION +
458 offsetof(SMU74_Firmware_Header, Version),
459 &tmp, data->sram_end);
462 hwmgr->microcode_version_info.SMC = tmp;
464 error |= (0 != result);
466 return error ? -1 : 0;
469 /* Copy one arb setting to another and then switch the active set.
470 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
472 static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
473 uint32_t arb_src, uint32_t arb_dest)
475 uint32_t mc_arb_dram_timing;
476 uint32_t mc_arb_dram_timing2;
478 uint32_t mc_cg_config;
481 case MC_CG_ARB_FREQ_F0:
482 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
483 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
484 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
486 case MC_CG_ARB_FREQ_F1:
487 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
488 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
489 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
496 case MC_CG_ARB_FREQ_F0:
497 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
498 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
499 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
501 case MC_CG_ARB_FREQ_F1:
502 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
503 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
504 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
510 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
511 mc_cg_config |= 0x0000000F;
512 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
513 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
519 * Initial switch from ARB F0->F1
521 * @param hwmgr the address of the powerplay hardware manager.
523 * This function is to be called from the SetPowerState table.
525 static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
527 return polaris10_copy_and_switch_arb_sets(hwmgr,
528 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
531 static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
533 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
534 struct phm_ppt_v1_information *table_info =
535 (struct phm_ppt_v1_information *)(hwmgr->pptable);
536 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
537 uint32_t i, max_entry;
539 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
540 data->use_pcie_power_saving_levels), "No pcie performance levels!",
543 if (data->use_pcie_performance_levels &&
544 !data->use_pcie_power_saving_levels) {
545 data->pcie_gen_power_saving = data->pcie_gen_performance;
546 data->pcie_lane_power_saving = data->pcie_lane_performance;
547 } else if (!data->use_pcie_performance_levels &&
548 data->use_pcie_power_saving_levels) {
549 data->pcie_gen_performance = data->pcie_gen_power_saving;
550 data->pcie_lane_performance = data->pcie_lane_power_saving;
553 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
554 SMU74_MAX_LEVELS_LINK,
555 MAX_REGULAR_DPM_NUMBER);
557 if (pcie_table != NULL) {
558 /* max_entry is used to make sure we reserve one PCIE level
559 * for boot level (fix for A+A PSPP issue).
560 * If PCIE table from PPTable have ULV entry + 8 entries,
561 * then ignore the last entry.*/
562 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
563 SMU74_MAX_LEVELS_LINK : pcie_table->count;
564 for (i = 1; i < max_entry; i++) {
565 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
566 get_pcie_gen_support(data->pcie_gen_cap,
567 pcie_table->entries[i].gen_speed),
568 get_pcie_lane_support(data->pcie_lane_cap,
569 pcie_table->entries[i].lane_width));
571 data->dpm_table.pcie_speed_table.count = max_entry - 1;
573 /* Setup BIF_SCLK levels */
574 for (i = 0; i < max_entry; i++)
575 data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
577 /* Hardcode Pcie Table */
578 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
579 get_pcie_gen_support(data->pcie_gen_cap,
581 get_pcie_lane_support(data->pcie_lane_cap,
583 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
584 get_pcie_gen_support(data->pcie_gen_cap,
586 get_pcie_lane_support(data->pcie_lane_cap,
588 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
589 get_pcie_gen_support(data->pcie_gen_cap,
591 get_pcie_lane_support(data->pcie_lane_cap,
593 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
594 get_pcie_gen_support(data->pcie_gen_cap,
596 get_pcie_lane_support(data->pcie_lane_cap,
598 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
599 get_pcie_gen_support(data->pcie_gen_cap,
601 get_pcie_lane_support(data->pcie_lane_cap,
603 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
604 get_pcie_gen_support(data->pcie_gen_cap,
606 get_pcie_lane_support(data->pcie_lane_cap,
609 data->dpm_table.pcie_speed_table.count = 6;
611 /* Populate last level for boot PCIE level, but do not increment count. */
612 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
613 data->dpm_table.pcie_speed_table.count,
614 get_pcie_gen_support(data->pcie_gen_cap,
616 get_pcie_lane_support(data->pcie_lane_cap,
623 * This function is to initalize all DPM state tables
624 * for SMU7 based on the dependency table.
625 * Dynamic state patching function will then trim these
626 * state tables to the allowed range based
627 * on the power policy or external client requests,
628 * such as UVD request, etc.
630 int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
632 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
633 struct phm_ppt_v1_information *table_info =
634 (struct phm_ppt_v1_information *)(hwmgr->pptable);
637 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
638 table_info->vdd_dep_on_sclk;
639 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
640 table_info->vdd_dep_on_mclk;
642 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
643 "SCLK dependency table is missing. This table is mandatory",
645 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
646 "SCLK dependency table has to have is missing."
647 "This table is mandatory",
650 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
651 "MCLK dependency table is missing. This table is mandatory",
653 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
654 "MCLK dependency table has to have is missing."
655 "This table is mandatory",
658 /* clear the state table to reset everything to default */
659 phm_reset_single_dpm_table(
660 &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
661 phm_reset_single_dpm_table(
662 &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
665 /* Initialize Sclk DPM table based on allow Sclk values */
666 data->dpm_table.sclk_table.count = 0;
667 for (i = 0; i < dep_sclk_table->count; i++) {
668 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
669 dep_sclk_table->entries[i].clk) {
671 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
672 dep_sclk_table->entries[i].clk;
674 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
675 (i == 0) ? true : false;
676 data->dpm_table.sclk_table.count++;
680 /* Initialize Mclk DPM table based on allow Mclk values */
681 data->dpm_table.mclk_table.count = 0;
682 for (i = 0; i < dep_mclk_table->count; i++) {
683 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
684 [data->dpm_table.mclk_table.count - 1].value !=
685 dep_mclk_table->entries[i].clk) {
686 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
687 dep_mclk_table->entries[i].clk;
688 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
689 (i == 0) ? true : false;
690 data->dpm_table.mclk_table.count++;
694 /* setup PCIE gen speed levels */
695 polaris10_setup_default_pcie_table(hwmgr);
697 /* save a copy of the default DPM table */
698 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
699 sizeof(struct polaris10_dpm_table));
704 uint8_t convert_to_vid(uint16_t vddc)
706 return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
710 * Mvdd table preparation for SMC.
712 * @param *hwmgr The address of the hardware manager.
713 * @param *table The SMC DPM table structure to be populated.
716 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
717 SMU74_Discrete_DpmTable *table)
719 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
720 uint32_t count, level;
722 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
723 count = data->mvdd_voltage_table.count;
724 if (count > SMU_MAX_SMIO_LEVELS)
725 count = SMU_MAX_SMIO_LEVELS;
726 for (level = 0; level < count; level++) {
727 table->SmioTable2.Pattern[level].Voltage =
728 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
729 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
730 table->SmioTable2.Pattern[level].Smio =
732 table->Smio[level] |=
733 data->mvdd_voltage_table.entries[level].smio_low;
735 table->SmioMask2 = data->mvdd_voltage_table.mask_low;
737 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
743 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
744 struct SMU74_Discrete_DpmTable *table)
746 uint32_t count, level;
747 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
749 count = data->vddci_voltage_table.count;
751 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
752 if (count > SMU_MAX_SMIO_LEVELS)
753 count = SMU_MAX_SMIO_LEVELS;
754 for (level = 0; level < count; ++level) {
755 table->SmioTable1.Pattern[level].Voltage =
756 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
757 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
759 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
763 table->SmioMask1 = data->vddci_voltage_table.mask_low;
769 * Preparation of vddc and vddgfx CAC tables for SMC.
771 * @param hwmgr the address of the hardware manager
772 * @param table the SMC DPM table structure to be populated
775 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
776 struct SMU74_Discrete_DpmTable *table)
780 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
781 struct phm_ppt_v1_information *table_info =
782 (struct phm_ppt_v1_information *)(hwmgr->pptable);
783 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
784 table_info->vddc_lookup_table;
785 /* tables is already swapped, so in order to use the value from it,
786 * we need to swap it back.
787 * We are populating vddc CAC data to BapmVddc table
788 * in split and merged mode
790 for (count = 0; count < lookup_table->count; count++) {
791 index = phm_get_voltage_index(lookup_table,
792 data->vddc_voltage_table.entries[count].value);
793 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
794 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
795 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
802 * Preparation of voltage tables for SMC.
804 * @param hwmgr the address of the hardware manager
805 * @param table the SMC DPM table structure to be populated
809 int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
810 struct SMU74_Discrete_DpmTable *table)
812 polaris10_populate_smc_vddci_table(hwmgr, table);
813 polaris10_populate_smc_mvdd_table(hwmgr, table);
814 polaris10_populate_cac_table(hwmgr, table);
819 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
820 struct SMU74_Discrete_Ulv *state)
822 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
823 struct phm_ppt_v1_information *table_info =
824 (struct phm_ppt_v1_information *)(hwmgr->pptable);
826 state->CcPwrDynRm = 0;
827 state->CcPwrDynRm1 = 0;
829 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
830 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
831 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
833 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
835 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
836 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
837 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
842 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
843 struct SMU74_Discrete_DpmTable *table)
845 return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
848 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
849 struct SMU74_Discrete_DpmTable *table)
851 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
852 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
855 /* Index (dpm_table->pcie_speed_table.count)
856 * is reserved for PCIE boot level. */
857 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
858 table->LinkLevel[i].PcieGenSpeed =
859 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
860 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
861 dpm_table->pcie_speed_table.dpm_levels[i].param1);
862 table->LinkLevel[i].EnabledForActivity = 1;
863 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
864 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
865 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
868 data->smc_state_table.LinkLevelCount =
869 (uint8_t)dpm_table->pcie_speed_table.count;
870 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
871 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
876 static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
878 uint32_t reference_clock, tmp;
879 struct cgs_display_info info = {0};
880 struct cgs_mode_info mode_info;
882 info.mode_info = &mode_info;
884 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
889 cgs_get_active_displays_info(hwmgr->device, &info);
890 reference_clock = mode_info.ref_clock;
892 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
895 return reference_clock / 4;
897 return reference_clock;
901 * Calculates the SCLK dividers using the provided engine clock
903 * @param hwmgr the address of the hardware manager
904 * @param clock the engine clock to use to populate the structure
905 * @param sclk the SMC SCLK structure to be populated
907 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
908 uint32_t clock, SMU_SclkSetting *sclk_setting)
910 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
911 const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
912 struct pp_atomctrl_clock_dividers_ai dividers;
915 uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
920 sclk_setting->SclkFrequency = clock;
921 /* get the engine clock dividers for this clock value */
922 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs);
924 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
925 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
926 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
927 sclk_setting->PllRange = dividers.ucSclkPllRange;
928 sclk_setting->Sclk_slew_rate = 0x400;
929 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
930 sclk_setting->Pcc_down_slew_rate = 0xffff;
931 sclk_setting->SSc_En = dividers.ucSscEnable;
932 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
933 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
934 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
938 ref_clock = polaris10_get_xclk(hwmgr);
940 for (i = 0; i < NUM_SCLK_RANGE; i++) {
941 if (clock > data->range_table[i].trans_lower_frequency
942 && clock <= data->range_table[i].trans_upper_frequency) {
943 sclk_setting->PllRange = i;
948 sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
949 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
951 do_div(temp, ref_clock);
952 sclk_setting->Fcw_frac = temp & 0xffff;
954 pcc_target_percent = 10; /* Hardcode 10% for now. */
955 pcc_target_freq = clock - (clock * pcc_target_percent / 100);
956 sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
958 ss_target_percent = 2; /* Hardcode 2% for now. */
959 sclk_setting->SSc_En = 0;
960 if (ss_target_percent) {
961 sclk_setting->SSc_En = 1;
962 ss_target_freq = clock - (clock * ss_target_percent / 100);
963 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
964 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
966 do_div(temp, ref_clock);
967 sclk_setting->Fcw1_frac = temp & 0xffff;
973 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
974 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
975 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
979 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
981 *voltage = *mvdd = 0;
983 /* clock - voltage dependency table is empty table */
984 if (dep_table->count == 0)
987 for (i = 0; i < dep_table->count; i++) {
988 /* find first sclk bigger than request */
989 if (dep_table->entries[i].clk >= clock) {
990 *voltage |= (dep_table->entries[i].vddc *
991 VOLTAGE_SCALE) << VDDC_SHIFT;
992 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
993 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
994 VOLTAGE_SCALE) << VDDCI_SHIFT;
995 else if (dep_table->entries[i].vddci)
996 *voltage |= (dep_table->entries[i].vddci *
997 VOLTAGE_SCALE) << VDDCI_SHIFT;
999 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1000 (dep_table->entries[i].vddc -
1001 (uint16_t)data->vddc_vddci_delta));
1002 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1005 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1006 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1008 else if (dep_table->entries[i].mvdd)
1009 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1012 *voltage |= 1 << PHASES_SHIFT;
1017 /* sclk is bigger than max sclk in the dependence table */
1018 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1020 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1021 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1022 VOLTAGE_SCALE) << VDDCI_SHIFT;
1023 else if (dep_table->entries[i-1].vddci) {
1024 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1025 (dep_table->entries[i].vddc -
1026 (uint16_t)data->vddc_vddci_delta));
1027 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1030 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1031 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1032 else if (dep_table->entries[i].mvdd)
1033 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1038 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] =
1039 { {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
1040 {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1041 {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
1042 {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
1043 {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
1044 {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
1045 {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
1046 {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
1048 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
1050 uint32_t i, ref_clk;
1051 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1052 SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1053 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1055 ref_clk = polaris10_get_xclk(hwmgr);
1057 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1058 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1059 table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1060 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1061 table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1063 table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1064 table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1066 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1067 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1068 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1073 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1075 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1076 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1078 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1079 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1080 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1082 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1083 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1085 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1086 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1087 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1092 * Populates single SMC SCLK structure using the provided engine clock
1094 * @param hwmgr the address of the hardware manager
1095 * @param clock the engine clock to use to populate the structure
1096 * @param sclk the SMC SCLK structure to be populated
1099 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1100 uint32_t clock, uint16_t sclk_al_threshold,
1101 struct SMU74_Discrete_GraphicsLevel *level)
1103 int result, i, temp;
1104 /* PP_Clocks minClocks; */
1106 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1107 struct phm_ppt_v1_information *table_info =
1108 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1109 SMU_SclkSetting curr_sclk_setting = { 0 };
1111 result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
1113 /* populate graphics levels */
1114 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1115 table_info->vdd_dep_on_sclk, clock,
1116 &level->MinVoltage, &mvdd);
1118 PP_ASSERT_WITH_CODE((0 == result),
1119 "can not find VDDC voltage value for "
1120 "VDDC engine clock dependency table",
1122 level->ActivityLevel = sclk_al_threshold;
1124 level->CcPwrDynRm = 0;
1125 level->CcPwrDynRm1 = 0;
1126 level->EnabledForActivity = 0;
1127 level->EnabledForThrottle = 1;
1129 level->DownHyst = 0;
1130 level->VoltageDownHyst = 0;
1131 level->PowerThrottle = 0;
1134 * TODO: get minimum clocks from dal configaration
1135 * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1137 /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1139 /* get level->DeepSleepDivId
1140 if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1141 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1143 PP_ASSERT_WITH_CODE((clock >= POLARIS10_MINIMUM_ENGINE_CLOCK), "Engine clock can't satisfy stutter requirement!", return 0);
1144 for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
1147 if (temp >= POLARIS10_MINIMUM_ENGINE_CLOCK || i == 0)
1151 level->DeepSleepDivId = i;
1153 /* Default to slow, highest DPM level will be
1154 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1156 if (data->update_up_hyst)
1157 level->UpHyst = (uint8_t)data->up_hyst;
1158 if (data->update_down_hyst)
1159 level->DownHyst = (uint8_t)data->down_hyst;
1161 level->SclkSetting = curr_sclk_setting;
1163 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1164 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1165 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1166 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1167 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1168 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1169 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1170 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1171 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1172 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1173 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1174 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1175 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1176 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1181 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1183 * @param hwmgr the address of the hardware manager
1185 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1187 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1188 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1189 struct phm_ppt_v1_information *table_info =
1190 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1191 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1192 uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1194 uint32_t array = data->dpm_table_start +
1195 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1196 uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1197 SMU74_MAX_LEVELS_GRAPHICS;
1198 struct SMU74_Discrete_GraphicsLevel *levels =
1199 data->smc_state_table.GraphicsLevel;
1200 uint32_t i, max_entry;
1201 uint8_t hightest_pcie_level_enabled = 0,
1202 lowest_pcie_level_enabled = 0,
1203 mid_pcie_level_enabled = 0,
1206 polaris10_get_sclk_range_table(hwmgr);
1208 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1210 result = polaris10_populate_single_graphic_level(hwmgr,
1211 dpm_table->sclk_table.dpm_levels[i].value,
1212 (uint16_t)data->activity_target[i],
1213 &(data->smc_state_table.GraphicsLevel[i]));
1217 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1219 levels[i].DeepSleepDivId = 0;
1221 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1222 PHM_PlatformCaps_SPLLShutdownSupport))
1223 data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1225 data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1226 data->smc_state_table.GraphicsDpmLevelCount =
1227 (uint8_t)dpm_table->sclk_table.count;
1228 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1229 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1232 if (pcie_table != NULL) {
1233 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1234 "There must be 1 or more PCIE levels defined in PPTable.",
1236 max_entry = pcie_entry_cnt - 1;
1237 for (i = 0; i < dpm_table->sclk_table.count; i++)
1238 levels[i].pcieDpmLevel =
1239 (uint8_t) ((i < max_entry) ? i : max_entry);
1241 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1242 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1243 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1244 hightest_pcie_level_enabled++;
1246 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1247 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1248 (1 << lowest_pcie_level_enabled)) == 0))
1249 lowest_pcie_level_enabled++;
1251 while ((count < hightest_pcie_level_enabled) &&
1252 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1253 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1256 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1257 hightest_pcie_level_enabled ?
1258 (lowest_pcie_level_enabled + 1 + count) :
1259 hightest_pcie_level_enabled;
1261 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1262 for (i = 2; i < dpm_table->sclk_table.count; i++)
1263 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1265 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1266 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1268 /* set pcieDpmLevel to mid_pcie_level_enabled */
1269 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1271 /* level count will send to smc once at init smc table and never change */
1272 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1273 (uint32_t)array_size, data->sram_end);
1278 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1279 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1281 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1282 struct phm_ppt_v1_information *table_info =
1283 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1285 struct cgs_display_info info = {0, 0, NULL};
1287 cgs_get_active_displays_info(hwmgr->device, &info);
1289 if (table_info->vdd_dep_on_mclk) {
1290 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1291 table_info->vdd_dep_on_mclk, clock,
1292 &mem_level->MinVoltage, &mem_level->MinMvdd);
1293 PP_ASSERT_WITH_CODE((0 == result),
1294 "can not find MinVddc voltage value from memory "
1295 "VDDC voltage dependency table", return result);
1298 mem_level->MclkFrequency = clock;
1299 mem_level->EnabledForThrottle = 1;
1300 mem_level->EnabledForActivity = 0;
1301 mem_level->UpHyst = 0;
1302 mem_level->DownHyst = 100;
1303 mem_level->VoltageDownHyst = 0;
1304 mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1305 mem_level->StutterEnable = false;
1306 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1308 data->display_timing.num_existing_displays = info.display_count;
1310 if ((data->mclk_stutter_mode_threshold) &&
1311 (clock <= data->mclk_stutter_mode_threshold) &&
1312 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1313 STUTTER_ENABLE) & 0x1))
1314 mem_level->StutterEnable = true;
1317 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1318 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1319 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1320 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1326 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1328 * @param hwmgr the address of the hardware manager
1330 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1332 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1333 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1335 /* populate MCLK dpm table to SMU7 */
1336 uint32_t array = data->dpm_table_start +
1337 offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1338 uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1339 SMU74_MAX_LEVELS_MEMORY;
1340 struct SMU74_Discrete_MemoryLevel *levels =
1341 data->smc_state_table.MemoryLevel;
1344 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1345 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1346 "can not populate memory level as memory clock is zero",
1348 result = polaris10_populate_single_memory_level(hwmgr,
1349 dpm_table->mclk_table.dpm_levels[i].value,
1351 if (i == dpm_table->mclk_table.count - 1) {
1352 levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1353 levels[i].EnabledForActivity = 1;
1359 /* in order to prevent MC activity from stutter mode to push DPM up.
1360 * the UVD change complements this by putting the MCLK in
1361 * a higher state by default such that we are not effected by
1362 * up threshold or and MCLK DPM latency.
1364 levels[0].ActivityLevel = 0x1f;
1365 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1367 data->smc_state_table.MemoryDpmLevelCount =
1368 (uint8_t)dpm_table->mclk_table.count;
1369 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1370 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1372 /* level count will send to smc once at init smc table and never change */
1373 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1374 (uint32_t)array_size, data->sram_end);
1380 * Populates the SMC MVDD structure using the provided memory clock.
1382 * @param hwmgr the address of the hardware manager
1383 * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
1384 * @param voltage the SMC VOLTAGE structure to be populated
1386 int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1387 uint32_t mclk, SMIO_Pattern *smio_pat)
1389 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1390 struct phm_ppt_v1_information *table_info =
1391 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1394 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1395 /* find mvdd value which clock is more than request */
1396 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1397 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1398 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1402 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1403 "MVDD Voltage is outside the supported range.",
1411 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1412 SMU74_Discrete_DpmTable *table)
1415 uint32_t sclk_frequency;
1416 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1417 struct phm_ppt_v1_information *table_info =
1418 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1419 SMIO_Pattern vol_level;
1423 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1426 /* Get MinVoltage and Frequency from DPM0,
1427 * already converted to SMC_UL */
1428 sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
1429 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1430 table_info->vdd_dep_on_sclk,
1432 &table->ACPILevel.MinVoltage, &mvdd);
1433 PP_ASSERT_WITH_CODE((0 == result),
1434 "Cannot find ACPI VDDC voltage value "
1435 "in Clock Dependency Table",
1439 result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
1440 PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1442 table->ACPILevel.DeepSleepDivId = 0;
1443 table->ACPILevel.CcPwrDynRm = 0;
1444 table->ACPILevel.CcPwrDynRm1 = 0;
1446 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1447 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1448 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1449 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1451 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1452 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1453 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1454 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1455 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1456 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1457 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1458 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1459 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1460 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1463 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1464 table->MemoryACPILevel.MclkFrequency =
1465 data->dpm_table.mclk_table.dpm_levels[0].value;
1466 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1467 table_info->vdd_dep_on_mclk,
1468 table->MemoryACPILevel.MclkFrequency,
1469 &table->MemoryACPILevel.MinVoltage, &mvdd);
1470 PP_ASSERT_WITH_CODE((0 == result),
1471 "Cannot find ACPI VDDCI voltage value "
1472 "in Clock Dependency Table",
1476 if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1477 (data->mclk_dpm_key_disabled))
1478 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1480 if (!polaris10_populate_mvdd_value(hwmgr,
1481 data->dpm_table.mclk_table.dpm_levels[0].value,
1483 us_mvdd = vol_level.Voltage;
1486 if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1487 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1489 table->MemoryACPILevel.MinMvdd = 0;
1491 table->MemoryACPILevel.StutterEnable = false;
1493 table->MemoryACPILevel.EnabledForThrottle = 0;
1494 table->MemoryACPILevel.EnabledForActivity = 0;
1495 table->MemoryACPILevel.UpHyst = 0;
1496 table->MemoryACPILevel.DownHyst = 100;
1497 table->MemoryACPILevel.VoltageDownHyst = 0;
1498 table->MemoryACPILevel.ActivityLevel =
1499 PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1501 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1502 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1507 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1508 SMU74_Discrete_DpmTable *table)
1510 int result = -EINVAL;
1512 struct pp_atomctrl_clock_dividers_vi dividers;
1513 struct phm_ppt_v1_information *table_info =
1514 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1515 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1516 table_info->mm_dep_table;
1517 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1520 table->VceLevelCount = (uint8_t)(mm_table->count);
1521 table->VceBootLevel = 0;
1523 for (count = 0; count < table->VceLevelCount; count++) {
1524 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1525 table->VceLevel[count].MinVoltage = 0;
1526 table->VceLevel[count].MinVoltage |=
1527 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1529 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1530 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1531 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1532 else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1533 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1535 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1538 table->VceLevel[count].MinVoltage |=
1539 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1540 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1542 /*retrieve divider value for VBIOS */
1543 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1544 table->VceLevel[count].Frequency, ÷rs);
1545 PP_ASSERT_WITH_CODE((0 == result),
1546 "can not find divide id for VCE engine clock",
1549 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1551 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1552 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1557 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1558 SMU74_Discrete_DpmTable *table)
1560 int result = -EINVAL;
1562 struct pp_atomctrl_clock_dividers_vi dividers;
1563 struct phm_ppt_v1_information *table_info =
1564 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1565 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1566 table_info->mm_dep_table;
1567 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1570 table->SamuBootLevel = 0;
1571 table->SamuLevelCount = (uint8_t)(mm_table->count);
1573 for (count = 0; count < table->SamuLevelCount; count++) {
1574 /* not sure whether we need evclk or not */
1575 table->SamuLevel[count].MinVoltage = 0;
1576 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1577 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1578 VOLTAGE_SCALE) << VDDC_SHIFT;
1580 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1581 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1582 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1583 else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1584 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1586 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1588 table->SamuLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1589 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1591 /* retrieve divider value for VBIOS */
1592 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1593 table->SamuLevel[count].Frequency, ÷rs);
1594 PP_ASSERT_WITH_CODE((0 == result),
1595 "can not find divide id for samu clock", return result);
1597 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1599 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1600 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1605 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1606 int32_t eng_clock, int32_t mem_clock,
1607 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1609 uint32_t dram_timing;
1610 uint32_t dram_timing2;
1611 uint32_t burst_time;
1614 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1615 eng_clock, mem_clock);
1616 PP_ASSERT_WITH_CODE(result == 0,
1617 "Error calling VBIOS to set DRAM_TIMING.", return result);
1619 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1620 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1621 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1624 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1625 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1626 arb_regs->McArbBurstTime = (uint8_t)burst_time;
1631 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1633 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1634 struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1638 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1639 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1640 result = polaris10_populate_memory_timing_parameters(hwmgr,
1641 data->dpm_table.sclk_table.dpm_levels[i].value,
1642 data->dpm_table.mclk_table.dpm_levels[j].value,
1643 &arb_regs.entries[i][j]);
1645 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1651 result = polaris10_copy_bytes_to_smc(
1653 data->arb_table_start,
1654 (uint8_t *)&arb_regs,
1655 sizeof(SMU74_Discrete_MCArbDramTimingTable),
1660 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1661 struct SMU74_Discrete_DpmTable *table)
1663 int result = -EINVAL;
1665 struct pp_atomctrl_clock_dividers_vi dividers;
1666 struct phm_ppt_v1_information *table_info =
1667 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1668 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1669 table_info->mm_dep_table;
1670 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1673 table->UvdLevelCount = (uint8_t)(mm_table->count);
1674 table->UvdBootLevel = 0;
1676 for (count = 0; count < table->UvdLevelCount; count++) {
1677 table->UvdLevel[count].MinVoltage = 0;
1678 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1679 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1680 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1681 VOLTAGE_SCALE) << VDDC_SHIFT;
1683 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1684 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1685 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1686 else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1687 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1689 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1691 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1692 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1694 /* retrieve divider value for VBIOS */
1695 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1696 table->UvdLevel[count].VclkFrequency, ÷rs);
1697 PP_ASSERT_WITH_CODE((0 == result),
1698 "can not find divide id for Vclk clock", return result);
1700 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1702 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1703 table->UvdLevel[count].DclkFrequency, ÷rs);
1704 PP_ASSERT_WITH_CODE((0 == result),
1705 "can not find divide id for Dclk clock", return result);
1707 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1709 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1710 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1711 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1717 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1718 struct SMU74_Discrete_DpmTable *table)
1721 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1723 table->GraphicsBootLevel = 0;
1724 table->MemoryBootLevel = 0;
1726 /* find boot level from dpm table */
1727 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1728 data->vbios_boot_state.sclk_bootup_value,
1729 (uint32_t *)&(table->GraphicsBootLevel));
1731 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1732 data->vbios_boot_state.mclk_bootup_value,
1733 (uint32_t *)&(table->MemoryBootLevel));
1735 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1737 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1739 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1742 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1743 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1744 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1750 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1752 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1753 struct phm_ppt_v1_information *table_info =
1754 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1755 uint8_t count, level;
1757 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1759 for (level = 0; level < count; level++) {
1760 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1761 data->vbios_boot_state.sclk_bootup_value) {
1762 data->smc_state_table.GraphicsBootLevel = level;
1767 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1768 for (level = 0; level < count; level++) {
1769 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1770 data->vbios_boot_state.mclk_bootup_value) {
1771 data->smc_state_table.MemoryBootLevel = level;
1779 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1781 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1782 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1783 uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
1784 struct phm_ppt_v1_information *table_info =
1785 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1786 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1787 table_info->vdd_dep_on_sclk;
1789 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1791 /* Read SMU_Eefuse to read and calculate RO and determine
1792 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1794 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1795 ixSMU_EFUSE_0 + (67 * 4));
1796 efuse &= 0xFF000000;
1797 efuse = efuse >> 24;
1799 if (hwmgr->chip_id == CHIP_POLARIS10) {
1807 ro = efuse * (max -min)/255 + min;
1809 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1810 for (i = 0; i < sclk_table->count; i++) {
1811 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1812 sclk_table->entries[i].cks_enable << i;
1813 if (hwmgr->chip_id == CHIP_POLARIS10) {
1814 volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 -(ro - 70) * 1000000) / \
1815 (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1816 volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \
1817 (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
1819 volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 -(ro - 50) * 1000000) / \
1820 (2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));
1821 volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \
1822 (3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));
1825 if (volt_without_cks >= volt_with_cks)
1826 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1827 sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
1829 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1832 data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
1833 /* Populate CKS Lookup Table */
1834 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1835 stretch_amount2 = 0;
1836 else if (stretch_amount == 3 || stretch_amount == 4)
1837 stretch_amount2 = 1;
1839 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1840 PHM_PlatformCaps_ClockStretcher);
1841 PP_ASSERT_WITH_CODE(false,
1842 "Stretch Amount in PPTable not supported\n",
1846 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1847 value &= 0xFFFFFFFE;
1848 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1854 * Populates the SMC VRConfig field in DPM table.
1856 * @param hwmgr the address of the hardware manager
1857 * @param table the SMC DPM table structure to be populated
1860 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1861 struct SMU74_Discrete_DpmTable *table)
1863 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1866 config = VR_MERGED_WITH_VDDC;
1867 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1869 /* Set Vddc Voltage Controller */
1870 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1871 config = VR_SVI2_PLANE_1;
1872 table->VRConfig |= config;
1874 PP_ASSERT_WITH_CODE(false,
1875 "VDDC should be on SVI2 control in merged mode!",
1878 /* Set Vddci Voltage Controller */
1879 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1880 config = VR_SVI2_PLANE_2; /* only in merged mode */
1881 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1882 } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1883 config = VR_SMIO_PATTERN_1;
1884 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1886 config = VR_STATIC_VOLTAGE;
1887 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1889 /* Set Mvdd Voltage Controller */
1890 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1891 config = VR_SVI2_PLANE_2;
1892 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1893 } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1894 config = VR_SMIO_PATTERN_2;
1895 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1897 config = VR_STATIC_VOLTAGE;
1898 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1905 int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1907 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1908 SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1910 struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1911 AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1912 AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1914 struct pp_smumgr *smumgr = hwmgr->smumgr;
1915 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
1917 struct phm_ppt_v1_information *table_info =
1918 (struct phm_ppt_v1_information *)hwmgr->pptable;
1919 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1920 table_info->vdd_dep_on_sclk;
1923 if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
1926 result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1929 table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1930 table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1931 table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1932 table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1933 table->BTCGB_VDROOP_TABLE[1].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1934 table->BTCGB_VDROOP_TABLE[1].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1935 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1936 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1937 table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1938 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1939 table->AVFSGB_VDROOP_TABLE[0].m2_shift = 12;
1940 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1941 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1942 table->AVFSGB_VDROOP_TABLE[1].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1943 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1944 table->AVFSGB_VDROOP_TABLE[1].m2_shift = 12;
1945 table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1946 AVFS_meanNsigma.Aconstant[0] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1947 AVFS_meanNsigma.Aconstant[1] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1948 AVFS_meanNsigma.Aconstant[2] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1949 AVFS_meanNsigma.DC_tol_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1950 AVFS_meanNsigma.Platform_mean = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1951 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1952 AVFS_meanNsigma.Platform_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1954 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1955 AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1956 AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
1959 result = polaris10_read_smc_sram_dword(smumgr,
1960 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1961 &tmp, data->sram_end);
1963 polaris10_copy_bytes_to_smc(smumgr,
1965 (uint8_t *)&AVFS_meanNsigma,
1966 sizeof(AVFS_meanNsigma_t),
1969 result = polaris10_read_smc_sram_dword(smumgr,
1970 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
1971 &tmp, data->sram_end);
1972 polaris10_copy_bytes_to_smc(smumgr,
1974 (uint8_t *)&AVFS_SclkOffset,
1975 sizeof(AVFS_Sclk_Offset_t),
1978 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
1979 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
1980 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
1981 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
1982 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
1989 * Initializes the SMC table and uploads it
1991 * @param hwmgr the address of the powerplay hardware manager.
1994 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1997 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1998 struct phm_ppt_v1_information *table_info =
1999 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2000 struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
2001 const struct polaris10_ulv_parm *ulv = &(data->ulv);
2003 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
2004 pp_atomctrl_clock_dividers_vi dividers;
2006 result = polaris10_setup_default_dpm_tables(hwmgr);
2007 PP_ASSERT_WITH_CODE(0 == result,
2008 "Failed to setup default DPM tables!", return result);
2010 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
2011 polaris10_populate_smc_voltage_tables(hwmgr, table);
2013 table->SystemFlags = 0;
2014 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2015 PHM_PlatformCaps_AutomaticDCTransition))
2016 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2018 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2019 PHM_PlatformCaps_StepVddc))
2020 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2022 if (data->is_memory_gddr5)
2023 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2025 if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2026 result = polaris10_populate_ulv_state(hwmgr, table);
2027 PP_ASSERT_WITH_CODE(0 == result,
2028 "Failed to initialize ULV state!", return result);
2029 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2030 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
2033 result = polaris10_populate_smc_link_level(hwmgr, table);
2034 PP_ASSERT_WITH_CODE(0 == result,
2035 "Failed to initialize Link Level!", return result);
2037 result = polaris10_populate_all_graphic_levels(hwmgr);
2038 PP_ASSERT_WITH_CODE(0 == result,
2039 "Failed to initialize Graphics Level!", return result);
2041 result = polaris10_populate_all_memory_levels(hwmgr);
2042 PP_ASSERT_WITH_CODE(0 == result,
2043 "Failed to initialize Memory Level!", return result);
2045 result = polaris10_populate_smc_acpi_level(hwmgr, table);
2046 PP_ASSERT_WITH_CODE(0 == result,
2047 "Failed to initialize ACPI Level!", return result);
2049 result = polaris10_populate_smc_vce_level(hwmgr, table);
2050 PP_ASSERT_WITH_CODE(0 == result,
2051 "Failed to initialize VCE Level!", return result);
2053 result = polaris10_populate_smc_samu_level(hwmgr, table);
2054 PP_ASSERT_WITH_CODE(0 == result,
2055 "Failed to initialize SAMU Level!", return result);
2057 /* Since only the initial state is completely set up at this point
2058 * (the other states are just copies of the boot state) we only
2059 * need to populate the ARB settings for the initial state.
2061 result = polaris10_program_memory_timing_parameters(hwmgr);
2062 PP_ASSERT_WITH_CODE(0 == result,
2063 "Failed to Write ARB settings for the initial state.", return result);
2065 result = polaris10_populate_smc_uvd_level(hwmgr, table);
2066 PP_ASSERT_WITH_CODE(0 == result,
2067 "Failed to initialize UVD Level!", return result);
2069 result = polaris10_populate_smc_boot_level(hwmgr, table);
2070 PP_ASSERT_WITH_CODE(0 == result,
2071 "Failed to initialize Boot Level!", return result);
2073 result = polaris10_populate_smc_initailial_state(hwmgr);
2074 PP_ASSERT_WITH_CODE(0 == result,
2075 "Failed to initialize Boot State!", return result);
2077 result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
2078 PP_ASSERT_WITH_CODE(0 == result,
2079 "Failed to populate BAPM Parameters!", return result);
2081 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2082 PHM_PlatformCaps_ClockStretcher)) {
2083 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
2084 PP_ASSERT_WITH_CODE(0 == result,
2085 "Failed to populate Clock Stretcher Data Table!",
2089 result = polaris10_populate_avfs_parameters(hwmgr);
2090 PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
2092 table->CurrSclkPllRange = 0xff;
2093 table->GraphicsVoltageChangeEnable = 1;
2094 table->GraphicsThermThrottleEnable = 1;
2095 table->GraphicsInterval = 1;
2096 table->VoltageInterval = 1;
2097 table->ThermalInterval = 1;
2098 table->TemperatureLimitHigh =
2099 table_info->cac_dtp_table->usTargetOperatingTemp *
2100 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2101 table->TemperatureLimitLow =
2102 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2103 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2104 table->MemoryVoltageChangeEnable = 1;
2105 table->MemoryInterval = 1;
2106 table->VoltageResponseTime = 0;
2107 table->PhaseResponseTime = 0;
2108 table->MemoryThermThrottleEnable = 1;
2109 table->PCIeBootLinkLevel = 0;
2110 table->PCIeGenInterval = 1;
2111 table->VRConfig = 0;
2113 result = polaris10_populate_vr_config(hwmgr, table);
2114 PP_ASSERT_WITH_CODE(0 == result,
2115 "Failed to populate VRConfig setting!", return result);
2117 table->ThermGpio = 17;
2118 table->SclkStepSize = 0x4000;
2120 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2121 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2123 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
2124 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2125 PHM_PlatformCaps_RegulatorHot);
2128 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2130 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2131 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2132 PHM_PlatformCaps_AutomaticDCTransition);
2134 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
2135 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2136 PHM_PlatformCaps_AutomaticDCTransition);
2139 /* Thermal Output GPIO */
2140 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2142 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2143 PHM_PlatformCaps_ThermalOutGPIO);
2145 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2147 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2148 * since VBIOS will program this register to set 'inactive state',
2149 * driver can then determine 'active state' from this and
2150 * program SMU with correct polarity
2152 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2153 & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2154 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2156 /* if required, combine VRHot/PCC with thermal out GPIO */
2157 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2158 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2159 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2161 table->ThermOutGpio = 17;
2162 table->ThermOutPolarity = 1;
2163 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2166 /* Populate BIF_SCLK levels into SMC DPM table */
2167 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2168 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], ÷rs);
2169 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2172 table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2174 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2177 for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2178 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2180 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2181 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2182 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2183 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2184 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2185 CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2186 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2187 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2188 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2189 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2191 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2192 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
2193 data->dpm_table_start +
2194 offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2195 (uint8_t *)&(table->SystemFlags),
2196 sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2198 PP_ASSERT_WITH_CODE(0 == result,
2199 "Failed to upload dpm data to SMC memory!", return result);
2205 * Initialize the ARB DRAM timing table's index field.
2207 * @param hwmgr the address of the powerplay hardware manager.
2210 static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
2212 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2216 /* This is a read-modify-write on the first byte of the ARB table.
2217 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2218 * is the field 'current'.
2219 * This solution is ugly, but we never write the whole table only
2220 * individual fields in it.
2221 * In reality this field should not be in that structure
2222 * but in a soft register.
2224 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
2225 data->arb_table_start, &tmp, data->sram_end);
2231 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2233 return polaris10_write_smc_sram_dword(hwmgr->smumgr,
2234 data->arb_table_start, tmp, data->sram_end);
2237 static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
2239 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2240 PHM_PlatformCaps_RegulatorHot))
2241 return smum_send_msg_to_smc(hwmgr->smumgr,
2242 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2247 static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
2249 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2250 SCLK_PWRMGT_OFF, 0);
2254 static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
2256 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2257 struct polaris10_ulv_parm *ulv = &(data->ulv);
2259 if (ulv->ulv_supported)
2260 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2265 static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2267 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2268 PHM_PlatformCaps_SclkDeepSleep)) {
2269 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2270 PP_ASSERT_WITH_CODE(false,
2271 "Attempt to enable Master Deep Sleep switch failed!",
2274 if (smum_send_msg_to_smc(hwmgr->smumgr,
2275 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2276 PP_ASSERT_WITH_CODE(false,
2277 "Attempt to disable Master Deep Sleep switch failed!",
2285 static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2287 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2288 uint32_t soft_register_value = 0;
2289 uint32_t handshake_disables_offset = data->soft_regs_start
2290 + offsetof(SMU74_SoftRegisters, HandshakeDisables);
2292 /* enable SCLK dpm */
2293 if (!data->sclk_dpm_key_disabled)
2294 PP_ASSERT_WITH_CODE(
2295 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2296 "Failed to enable SCLK DPM during DPM Start Function!",
2299 /* enable MCLK dpm */
2300 if (0 == data->mclk_dpm_key_disabled) {
2301 /* Disable UVD - SMU handshake for MCLK. */
2302 soft_register_value = cgs_read_ind_register(hwmgr->device,
2303 CGS_IND_REG__SMC, handshake_disables_offset);
2304 soft_register_value |= SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2305 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2306 handshake_disables_offset, soft_register_value);
2308 PP_ASSERT_WITH_CODE(
2309 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2310 PPSMC_MSG_MCLKDPM_Enable)),
2311 "Failed to enable MCLK DPM during DPM Start Function!",
2314 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2316 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2317 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2318 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2320 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2321 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2322 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2328 static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
2330 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2332 /*enable general power management */
2334 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2335 GLOBAL_PWRMGT_EN, 1);
2337 /* enable sclk deep sleep */
2339 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2342 /* prepare for PCIE DPM */
2344 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2345 data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2346 VoltageChangeTimeout), 0x1000);
2347 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2348 SWRST_COMMAND_1, RESETLC, 0x0);
2350 PP_ASSERT_WITH_CODE(
2351 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2352 PPSMC_MSG_Voltage_Cntl_Enable)),
2353 "Failed to enable voltage DPM during DPM Start Function!",
2357 if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
2358 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2362 /* enable PCIE dpm */
2363 if (0 == data->pcie_dpm_key_disabled) {
2364 PP_ASSERT_WITH_CODE(
2365 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2366 PPSMC_MSG_PCIeDPM_Enable)),
2367 "Failed to enable pcie DPM during DPM Start Function!",
2371 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2372 PHM_PlatformCaps_Falcon_QuickTransition)) {
2373 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2374 PPSMC_MSG_EnableACDCGPIOInterrupt)),
2375 "Failed to enable AC DC GPIO Interrupt!",
2382 static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
2385 enum DPM_EVENT_SRC src;
2389 printk(KERN_ERR "Unknown throttling event sources.");
2395 case (1 << PHM_AutoThrottleSource_Thermal):
2397 src = DPM_EVENT_SRC_DIGITAL;
2399 case (1 << PHM_AutoThrottleSource_External):
2401 src = DPM_EVENT_SRC_EXTERNAL;
2403 case (1 << PHM_AutoThrottleSource_External) |
2404 (1 << PHM_AutoThrottleSource_Thermal):
2406 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2409 /* Order matters - don't enable thermal protection for the wrong source. */
2411 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2412 DPM_EVENT_SRC, src);
2413 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2414 THERMAL_PROTECTION_DIS,
2415 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2416 PHM_PlatformCaps_ThermalController));
2418 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2419 THERMAL_PROTECTION_DIS, 1);
2422 static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2423 PHM_AutoThrottleSource source)
2425 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2427 if (!(data->active_auto_throttle_sources & (1 << source))) {
2428 data->active_auto_throttle_sources |= 1 << source;
2429 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2434 static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2436 return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2439 int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
2441 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2442 data->pcie_performance_request = true;
2447 int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2449 int tmp_result, result = 0;
2450 tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2451 PP_ASSERT_WITH_CODE(result == 0,
2452 "DPM is already running right now, no need to enable DPM!",
2455 if (polaris10_voltage_control(hwmgr)) {
2456 tmp_result = polaris10_enable_voltage_control(hwmgr);
2457 PP_ASSERT_WITH_CODE(tmp_result == 0,
2458 "Failed to enable voltage control!",
2459 result = tmp_result);
2461 tmp_result = polaris10_construct_voltage_tables(hwmgr);
2462 PP_ASSERT_WITH_CODE((0 == tmp_result),
2463 "Failed to contruct voltage tables!",
2464 result = tmp_result);
2467 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2468 PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2469 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2470 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2472 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2473 PHM_PlatformCaps_ThermalController))
2474 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2475 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2477 tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
2478 PP_ASSERT_WITH_CODE((0 == tmp_result),
2479 "Failed to program static screen threshold parameters!",
2480 result = tmp_result);
2482 tmp_result = polaris10_enable_display_gap(hwmgr);
2483 PP_ASSERT_WITH_CODE((0 == tmp_result),
2484 "Failed to enable display gap!", result = tmp_result);
2486 tmp_result = polaris10_program_voting_clients(hwmgr);
2487 PP_ASSERT_WITH_CODE((0 == tmp_result),
2488 "Failed to program voting clients!", result = tmp_result);
2490 tmp_result = polaris10_process_firmware_header(hwmgr);
2491 PP_ASSERT_WITH_CODE((0 == tmp_result),
2492 "Failed to process firmware header!", result = tmp_result);
2494 tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
2495 PP_ASSERT_WITH_CODE((0 == tmp_result),
2496 "Failed to initialize switch from ArbF0 to F1!",
2497 result = tmp_result);
2499 tmp_result = polaris10_init_smc_table(hwmgr);
2500 PP_ASSERT_WITH_CODE((0 == tmp_result),
2501 "Failed to initialize SMC table!", result = tmp_result);
2503 tmp_result = polaris10_init_arb_table_index(hwmgr);
2504 PP_ASSERT_WITH_CODE((0 == tmp_result),
2505 "Failed to initialize ARB table index!", result = tmp_result);
2507 tmp_result = polaris10_populate_pm_fuses(hwmgr);
2508 PP_ASSERT_WITH_CODE((0 == tmp_result),
2509 "Failed to populate PM fuses!", result = tmp_result);
2511 tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
2512 PP_ASSERT_WITH_CODE((0 == tmp_result),
2513 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2515 smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay);
2517 tmp_result = polaris10_enable_sclk_control(hwmgr);
2518 PP_ASSERT_WITH_CODE((0 == tmp_result),
2519 "Failed to enable SCLK control!", result = tmp_result);
2521 tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
2522 PP_ASSERT_WITH_CODE((0 == tmp_result),
2523 "Failed to enable voltage control!", result = tmp_result);
2525 tmp_result = polaris10_enable_ulv(hwmgr);
2526 PP_ASSERT_WITH_CODE((0 == tmp_result),
2527 "Failed to enable ULV!", result = tmp_result);
2529 tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
2530 PP_ASSERT_WITH_CODE((0 == tmp_result),
2531 "Failed to enable deep sleep master switch!", result = tmp_result);
2533 tmp_result = polaris10_start_dpm(hwmgr);
2534 PP_ASSERT_WITH_CODE((0 == tmp_result),
2535 "Failed to start DPM!", result = tmp_result);
2537 tmp_result = polaris10_enable_smc_cac(hwmgr);
2538 PP_ASSERT_WITH_CODE((0 == tmp_result),
2539 "Failed to enable SMC CAC!", result = tmp_result);
2541 tmp_result = polaris10_enable_power_containment(hwmgr);
2542 PP_ASSERT_WITH_CODE((0 == tmp_result),
2543 "Failed to enable power containment!", result = tmp_result);
2545 tmp_result = polaris10_power_control_set_level(hwmgr);
2546 PP_ASSERT_WITH_CODE((0 == tmp_result),
2547 "Failed to power control set level!", result = tmp_result);
2549 tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
2550 PP_ASSERT_WITH_CODE((0 == tmp_result),
2551 "Failed to enable thermal auto throttle!", result = tmp_result);
2553 tmp_result = polaris10_pcie_performance_request(hwmgr);
2554 PP_ASSERT_WITH_CODE((0 == tmp_result),
2555 "pcie performance request failed!", result = tmp_result);
2560 int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2566 int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
2572 int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2574 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2576 if (data->soft_pp_table) {
2577 kfree(data->soft_pp_table);
2578 data->soft_pp_table = NULL;
2581 return phm_hwmgr_backend_fini(hwmgr);
2584 int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
2586 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2588 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2589 PHM_PlatformCaps_SclkDeepSleep);
2591 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2592 PHM_PlatformCaps_DynamicPatchPowerState);
2594 if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2595 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2596 PHM_PlatformCaps_EnableMVDDControl);
2598 if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2599 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2600 PHM_PlatformCaps_ControlVDDCI);
2602 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2603 PHM_PlatformCaps_TablelessHardwareInterface);
2605 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2606 PHM_PlatformCaps_EnableSMU7ThermalManagement);
2608 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2609 PHM_PlatformCaps_DynamicPowerManagement);
2611 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2612 PHM_PlatformCaps_UnTabledHardwareInterface);
2614 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2615 PHM_PlatformCaps_TablelessHardwareInterface);
2617 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2618 PHM_PlatformCaps_SMC);
2620 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2621 PHM_PlatformCaps_NonABMSupportInPPLib);
2623 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2624 PHM_PlatformCaps_DynamicUVDState);
2626 /* power tune caps Assume disabled */
2627 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2628 PHM_PlatformCaps_SQRamping);
2629 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2630 PHM_PlatformCaps_DBRamping);
2631 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2632 PHM_PlatformCaps_TDRamping);
2633 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2634 PHM_PlatformCaps_TCPRamping);
2636 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2637 PHM_PlatformCaps_PowerContainment);
2638 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2639 PHM_PlatformCaps_CAC);
2641 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2642 PHM_PlatformCaps_RegulatorHot);
2644 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2645 PHM_PlatformCaps_AutomaticDCTransition);
2647 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2648 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2650 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2651 PHM_PlatformCaps_FanSpeedInTableIsRPM);
2653 if (hwmgr->chip_id == CHIP_POLARIS11)
2654 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2655 PHM_PlatformCaps_SPLLShutdownSupport);
2659 static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
2661 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2663 polaris10_initialize_power_tune_defaults(hwmgr);
2665 data->pcie_gen_performance.max = PP_PCIEGen1;
2666 data->pcie_gen_performance.min = PP_PCIEGen3;
2667 data->pcie_gen_power_saving.max = PP_PCIEGen1;
2668 data->pcie_gen_power_saving.min = PP_PCIEGen3;
2669 data->pcie_lane_performance.max = 0;
2670 data->pcie_lane_performance.min = 16;
2671 data->pcie_lane_power_saving.max = 0;
2672 data->pcie_lane_power_saving.min = 16;
2676 * Get Leakage VDDC based on leakage ID.
2678 * @param hwmgr the address of the powerplay hardware manager.
2681 static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
2683 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2688 struct phm_ppt_v1_information *table_info =
2689 (struct phm_ppt_v1_information *)hwmgr->pptable;
2690 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2691 table_info->vdd_dep_on_sclk;
2694 for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
2695 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2696 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2697 table_info->vddc_lookup_table, vv_id, &sclk)) {
2698 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2699 PHM_PlatformCaps_ClockStretcher)) {
2700 for (j = 1; j < sclk_table->count; j++) {
2701 if (sclk_table->entries[j].clk == sclk &&
2702 sclk_table->entries[j].cks_enable == 0) {
2710 PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2711 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
2712 "Error retrieving EVV voltage value!",
2716 /* need to make sure vddc is less than 2v or else, it could burn the ASIC.
2717 * real voltage level in unit of 0.01mv */
2718 PP_ASSERT_WITH_CODE((vddc < 200000 && vddc != 0),
2719 "Invalid VDDC value", result = -EINVAL;);
2721 /* the voltage should not be zero nor equal to leakage ID */
2722 if (vddc != 0 && vddc != vv_id) {
2723 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2724 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2725 data->vddc_leakage.count++;
2734 * Change virtual leakage voltage to actual value.
2736 * @param hwmgr the address of the powerplay hardware manager.
2737 * @param pointer to changing voltage
2738 * @param pointer to leakage table
2740 static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2741 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
2745 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2746 for (index = 0; index < leakage_table->count; index++) {
2747 /* if this voltage matches a leakage voltage ID */
2748 /* patch with actual leakage voltage */
2749 if (leakage_table->leakage_id[index] == *voltage) {
2750 *voltage = leakage_table->actual_voltage[index];
2755 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2756 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2760 * Patch voltage lookup table by EVV leakages.
2762 * @param hwmgr the address of the powerplay hardware manager.
2763 * @param pointer to voltage lookup table
2764 * @param pointer to leakage table
2767 static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
2768 phm_ppt_v1_voltage_lookup_table *lookup_table,
2769 struct polaris10_leakage_voltage *leakage_table)
2773 for (i = 0; i < lookup_table->count; i++)
2774 polaris10_patch_with_vdd_leakage(hwmgr,
2775 &lookup_table->entries[i].us_vdd, leakage_table);
2780 static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2781 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
2784 struct phm_ppt_v1_information *table_info =
2785 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2786 polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
2787 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2788 table_info->max_clock_voltage_on_dc.vddc;
2792 static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
2793 struct pp_hwmgr *hwmgr)
2797 struct phm_ppt_v1_information *table_info =
2798 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2800 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2801 table_info->vdd_dep_on_sclk;
2802 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2803 table_info->vdd_dep_on_mclk;
2804 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2805 table_info->mm_dep_table;
2807 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
2808 voltageId = sclk_table->entries[entryId].vddInd;
2809 sclk_table->entries[entryId].vddc =
2810 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2813 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
2814 voltageId = mclk_table->entries[entryId].vddInd;
2815 mclk_table->entries[entryId].vddc =
2816 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2819 for (entryId = 0; entryId < mm_table->count; ++entryId) {
2820 voltageId = mm_table->entries[entryId].vddcInd;
2821 mm_table->entries[entryId].vddc =
2822 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2829 static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
2831 /* Need to determine if we need calculated voltage. */
2835 static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
2837 /* Need to determine if we need calculated voltage from mm table. */
2841 static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
2842 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
2844 uint32_t table_size, i, j;
2845 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
2846 table_size = lookup_table->count;
2848 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2849 "Lookup table is empty", return -EINVAL);
2851 /* Sorting voltages */
2852 for (i = 0; i < table_size - 1; i++) {
2853 for (j = i + 1; j > 0; j--) {
2854 if (lookup_table->entries[j].us_vdd <
2855 lookup_table->entries[j - 1].us_vdd) {
2856 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
2857 lookup_table->entries[j - 1] = lookup_table->entries[j];
2858 lookup_table->entries[j] = tmp_voltage_lookup_record;
2866 static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
2870 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2871 struct phm_ppt_v1_information *table_info =
2872 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2874 tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
2875 table_info->vddc_lookup_table, &(data->vddc_leakage));
2877 result = tmp_result;
2879 tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
2880 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2882 result = tmp_result;
2884 tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
2886 result = tmp_result;
2888 tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
2890 result = tmp_result;
2892 tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
2894 result = tmp_result;
2896 tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
2898 result = tmp_result;
2903 static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
2905 struct phm_ppt_v1_information *table_info =
2906 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2908 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2909 table_info->vdd_dep_on_sclk;
2910 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2911 table_info->vdd_dep_on_mclk;
2913 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2914 "VDD dependency on SCLK table is missing. \
2915 This table is mandatory", return -EINVAL);
2916 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2917 "VDD dependency on SCLK table has to have is missing. \
2918 This table is mandatory", return -EINVAL);
2920 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2921 "VDD dependency on MCLK table is missing. \
2922 This table is mandatory", return -EINVAL);
2923 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2924 "VDD dependency on MCLK table has to have is missing. \
2925 This table is mandatory", return -EINVAL);
2927 table_info->max_clock_voltage_on_ac.sclk =
2928 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2929 table_info->max_clock_voltage_on_ac.mclk =
2930 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2931 table_info->max_clock_voltage_on_ac.vddc =
2932 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2933 table_info->max_clock_voltage_on_ac.vddci =
2934 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2936 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2937 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2938 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2939 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
2944 int polaris10_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
2946 struct phm_ppt_v1_information *table_info =
2947 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2948 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
2949 table_info->vdd_dep_on_mclk;
2950 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
2951 table_info->vddc_lookup_table;
2954 if (hwmgr->chip_id == CHIP_POLARIS10 && hwmgr->hw_revision == 0xC7) {
2955 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
2958 for (i = 0; i < lookup_table->count; i++) {
2959 if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) {
2960 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;
2969 int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2971 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2972 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2975 struct phm_ppt_v1_information *table_info =
2976 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2978 data->dll_default_on = false;
2979 data->sram_end = SMC_RAM_END;
2980 data->mclk_dpm0_activity_target = 0xa;
2981 data->disable_dpm_mask = 0xFF;
2982 data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2983 data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2984 data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2985 data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2986 data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2987 data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2988 data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2989 data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2990 data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2991 data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2993 data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
2994 data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
2995 data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
2996 data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
2997 data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
2998 data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
2999 data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
3000 data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
3002 data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
3004 data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
3006 /* need to set voltage control types before EVV patching */
3007 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3008 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3009 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3011 data->enable_tdc_limit_feature = true;
3012 data->enable_pkg_pwr_tracking_feature = true;
3013 data->force_pcie_gen = PP_PCIEGenInvalid;
3014 data->mclk_stutter_mode_threshold = 40000;
3016 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3017 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
3018 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3020 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3021 PHM_PlatformCaps_EnableMVDDControl)) {
3022 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3023 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
3024 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
3025 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3026 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
3027 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3030 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3031 PHM_PlatformCaps_ControlVDDCI)) {
3032 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3033 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
3034 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
3035 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3036 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
3037 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3040 if (table_info->cac_dtp_table->usClockStretchAmount != 0)
3041 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3042 PHM_PlatformCaps_ClockStretcher);
3044 polaris10_set_features_platform_caps(hwmgr);
3046 polaris10_patch_voltage_workaround(hwmgr);
3047 polaris10_init_dpm_defaults(hwmgr);
3049 /* Get leakage voltage based on leakage ID. */
3050 result = polaris10_get_evv_voltages(hwmgr);
3053 printk("Get EVV Voltage Failed. Abort Driver loading!\n");
3057 polaris10_complete_dependency_tables(hwmgr);
3058 polaris10_set_private_data_based_on_pptable(hwmgr);
3060 /* Initalize Dynamic State Adjustment Rule Settings */
3061 result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
3064 struct cgs_system_info sys_info = {0};
3066 data->is_tlu_enabled = 0;
3068 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
3069 POLARIS10_MAX_HARDWARE_POWERLEVELS;
3070 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3071 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
3074 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
3075 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
3076 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
3078 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3081 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3084 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3087 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3090 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3093 PP_ASSERT_WITH_CODE(0,
3094 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3098 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3101 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
3102 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
3103 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
3104 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3106 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
3107 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3109 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
3111 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
3113 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
3114 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3116 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
3118 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
3119 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
3121 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3122 table_info->cac_dtp_table->usOperatingTempStep = 1;
3123 table_info->cac_dtp_table->usOperatingTempHyst = 1;
3125 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
3126 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3128 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
3129 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
3131 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
3132 table_info->cac_dtp_table->usOperatingTempMinLimit;
3134 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
3135 table_info->cac_dtp_table->usOperatingTempMaxLimit;
3137 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
3138 table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3140 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
3141 table_info->cac_dtp_table->usOperatingTempStep;
3143 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
3144 table_info->cac_dtp_table->usTargetOperatingTemp;
3147 sys_info.size = sizeof(struct cgs_system_info);
3148 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3149 result = cgs_query_system_info(hwmgr->device, &sys_info);
3151 data->pcie_gen_cap = 0x30007;
3153 data->pcie_gen_cap = (uint32_t)sys_info.value;
3154 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3155 data->pcie_spc_cap = 20;
3156 sys_info.size = sizeof(struct cgs_system_info);
3157 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3158 result = cgs_query_system_info(hwmgr->device, &sys_info);
3160 data->pcie_lane_cap = 0x2f0000;
3162 data->pcie_lane_cap = (uint32_t)sys_info.value;
3164 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3165 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3166 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3167 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
3169 /* Ignore return value in here, we are cleaning up a mess. */
3170 polaris10_hwmgr_backend_fini(hwmgr);
3176 static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3178 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3179 uint32_t level, tmp;
3181 if (!data->pcie_dpm_key_disabled) {
3182 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3184 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3189 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3190 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3194 if (!data->sclk_dpm_key_disabled) {
3195 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3197 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3202 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3203 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3208 if (!data->mclk_dpm_key_disabled) {
3209 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3211 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3216 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3217 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3225 static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3227 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3229 phm_apply_dal_min_voltage_request(hwmgr);
3231 if (!data->sclk_dpm_key_disabled) {
3232 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3233 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3234 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3235 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3238 if (!data->mclk_dpm_key_disabled) {
3239 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3240 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3241 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3242 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3248 static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3250 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3252 if (!polaris10_is_dpm_running(hwmgr))
3255 if (!data->pcie_dpm_key_disabled) {
3256 smum_send_msg_to_smc(hwmgr->smumgr,
3257 PPSMC_MSG_PCIeDPM_UnForceLevel);
3260 return polaris10_upload_dpm_level_enable_mask(hwmgr);
3263 static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3265 struct polaris10_hwmgr *data =
3266 (struct polaris10_hwmgr *)(hwmgr->backend);
3269 if (!data->sclk_dpm_key_disabled)
3270 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3271 level = phm_get_lowest_enabled_level(hwmgr,
3272 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3273 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3274 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3279 if (!data->mclk_dpm_key_disabled) {
3280 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3281 level = phm_get_lowest_enabled_level(hwmgr,
3282 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3283 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3284 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3289 if (!data->pcie_dpm_key_disabled) {
3290 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3291 level = phm_get_lowest_enabled_level(hwmgr,
3292 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3293 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3294 PPSMC_MSG_PCIeDPM_ForceLevel,
3302 static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
3303 enum amd_dpm_forced_level level)
3308 case AMD_DPM_FORCED_LEVEL_HIGH:
3309 ret = polaris10_force_dpm_highest(hwmgr);
3313 case AMD_DPM_FORCED_LEVEL_LOW:
3314 ret = polaris10_force_dpm_lowest(hwmgr);
3318 case AMD_DPM_FORCED_LEVEL_AUTO:
3319 ret = polaris10_unforce_dpm_levels(hwmgr);
3327 hwmgr->dpm_level = level;
3332 static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
3334 return sizeof(struct polaris10_power_state);
3338 static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3339 struct pp_power_state *request_ps,
3340 const struct pp_power_state *current_ps)
3343 struct polaris10_power_state *polaris10_ps =
3344 cast_phw_polaris10_power_state(&request_ps->hardware);
3347 struct PP_Clocks minimum_clocks = {0};
3348 bool disable_mclk_switching;
3349 bool disable_mclk_switching_for_frame_lock;
3350 struct cgs_display_info info = {0};
3351 const struct phm_clock_and_voltage_limits *max_limits;
3353 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3354 struct phm_ppt_v1_information *table_info =
3355 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3357 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3359 data->battery_state = (PP_StateUILabel_Battery ==
3360 request_ps->classification.ui_label);
3362 PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
3363 "VI should always have 2 performance levels",
3366 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3367 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3368 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3370 /* Cap clock DPM tables at DC MAX if it is in DC. */
3371 if (PP_PowerSource_DC == hwmgr->power_source) {
3372 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3373 if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3374 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3375 if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3376 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
3380 polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3381 polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3383 cgs_get_active_displays_info(hwmgr->device, &info);
3385 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3387 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3389 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3390 PHM_PlatformCaps_StablePState)) {
3391 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3392 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3394 for (count = table_info->vdd_dep_on_sclk->count - 1;
3395 count >= 0; count--) {
3396 if (stable_pstate_sclk >=
3397 table_info->vdd_dep_on_sclk->entries[count].clk) {
3398 stable_pstate_sclk =
3399 table_info->vdd_dep_on_sclk->entries[count].clk;
3405 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3407 stable_pstate_mclk = max_limits->mclk;
3409 minimum_clocks.engineClock = stable_pstate_sclk;
3410 minimum_clocks.memoryClock = stable_pstate_mclk;
3413 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3414 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3416 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3417 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3419 polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3421 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3422 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3423 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3424 "Overdrive sclk exceeds limit",
3425 hwmgr->gfx_arbiter.sclk_over_drive =
3426 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3428 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3429 polaris10_ps->performance_levels[1].engine_clock =
3430 hwmgr->gfx_arbiter.sclk_over_drive;
3433 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3434 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3435 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3436 "Overdrive mclk exceeds limit",
3437 hwmgr->gfx_arbiter.mclk_over_drive =
3438 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3440 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3441 polaris10_ps->performance_levels[1].memory_clock =
3442 hwmgr->gfx_arbiter.mclk_over_drive;
3445 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3446 hwmgr->platform_descriptor.platformCaps,
3447 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3449 disable_mclk_switching = (1 < info.display_count) ||
3450 disable_mclk_switching_for_frame_lock;
3452 sclk = polaris10_ps->performance_levels[0].engine_clock;
3453 mclk = polaris10_ps->performance_levels[0].memory_clock;
3455 if (disable_mclk_switching)
3456 mclk = polaris10_ps->performance_levels
3457 [polaris10_ps->performance_level_count - 1].memory_clock;
3459 if (sclk < minimum_clocks.engineClock)
3460 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3461 max_limits->sclk : minimum_clocks.engineClock;
3463 if (mclk < minimum_clocks.memoryClock)
3464 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3465 max_limits->mclk : minimum_clocks.memoryClock;
3467 polaris10_ps->performance_levels[0].engine_clock = sclk;
3468 polaris10_ps->performance_levels[0].memory_clock = mclk;
3470 polaris10_ps->performance_levels[1].engine_clock =
3471 (polaris10_ps->performance_levels[1].engine_clock >=
3472 polaris10_ps->performance_levels[0].engine_clock) ?
3473 polaris10_ps->performance_levels[1].engine_clock :
3474 polaris10_ps->performance_levels[0].engine_clock;
3476 if (disable_mclk_switching) {
3477 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3478 mclk = polaris10_ps->performance_levels[1].memory_clock;
3480 polaris10_ps->performance_levels[0].memory_clock = mclk;
3481 polaris10_ps->performance_levels[1].memory_clock = mclk;
3483 if (polaris10_ps->performance_levels[1].memory_clock <
3484 polaris10_ps->performance_levels[0].memory_clock)
3485 polaris10_ps->performance_levels[1].memory_clock =
3486 polaris10_ps->performance_levels[0].memory_clock;
3489 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3490 PHM_PlatformCaps_StablePState)) {
3491 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3492 polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3493 polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3494 polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3495 polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3502 static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3504 struct pp_power_state *ps;
3505 struct polaris10_power_state *polaris10_ps;
3510 ps = hwmgr->request_ps;
3515 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3518 return polaris10_ps->performance_levels[0].memory_clock;
3520 return polaris10_ps->performance_levels
3521 [polaris10_ps->performance_level_count-1].memory_clock;
3524 static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3526 struct pp_power_state *ps;
3527 struct polaris10_power_state *polaris10_ps;
3532 ps = hwmgr->request_ps;
3537 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3540 return polaris10_ps->performance_levels[0].engine_clock;
3542 return polaris10_ps->performance_levels
3543 [polaris10_ps->performance_level_count-1].engine_clock;
3546 static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3547 struct pp_hw_power_state *hw_ps)
3549 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3550 struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
3551 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3554 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3556 /* First retrieve the Boot clocks and VDDC from the firmware info table.
3557 * We assume here that fw_info is unchanged if this call fails.
3559 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3560 hwmgr->device, index,
3561 &size, &frev, &crev);
3563 /* During a test, there is no firmware info table. */
3566 /* Patch the state. */
3567 data->vbios_boot_state.sclk_bootup_value =
3568 le32_to_cpu(fw_info->ulDefaultEngineClock);
3569 data->vbios_boot_state.mclk_bootup_value =
3570 le32_to_cpu(fw_info->ulDefaultMemoryClock);
3571 data->vbios_boot_state.mvdd_bootup_value =
3572 le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3573 data->vbios_boot_state.vddc_bootup_value =
3574 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3575 data->vbios_boot_state.vddci_bootup_value =
3576 le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3577 data->vbios_boot_state.pcie_gen_bootup_value =
3578 phm_get_current_pcie_speed(hwmgr);
3580 data->vbios_boot_state.pcie_lane_bootup_value =
3581 (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3583 /* set boot power state */
3584 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3585 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3586 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3587 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3592 static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3593 void *state, struct pp_power_state *power_state,
3594 void *pp_table, uint32_t classification_flag)
3596 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3597 struct polaris10_power_state *polaris10_power_state =
3598 (struct polaris10_power_state *)(&(power_state->hardware));
3599 struct polaris10_performance_level *performance_level;
3600 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3601 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3602 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3603 PPTable_Generic_SubTable_Header *sclk_dep_table =
3604 (PPTable_Generic_SubTable_Header *)
3605 (((unsigned long)powerplay_table) +
3606 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3608 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3609 (ATOM_Tonga_MCLK_Dependency_Table *)
3610 (((unsigned long)powerplay_table) +
3611 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3613 /* The following fields are not initialized here: id orderedList allStatesList */
3614 power_state->classification.ui_label =
3615 (le16_to_cpu(state_entry->usClassification) &
3616 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3617 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3618 power_state->classification.flags = classification_flag;
3619 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3621 power_state->classification.temporary_state = false;
3622 power_state->classification.to_be_deleted = false;
3624 power_state->validation.disallowOnDC =
3625 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3626 ATOM_Tonga_DISALLOW_ON_DC));
3628 power_state->pcie.lanes = 0;
3630 power_state->display.disableFrameModulation = false;
3631 power_state->display.limitRefreshrate = false;
3632 power_state->display.enableVariBright =
3633 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3634 ATOM_Tonga_ENABLE_VARIBRIGHT));
3636 power_state->validation.supportedPowerLevels = 0;
3637 power_state->uvd_clocks.VCLK = 0;
3638 power_state->uvd_clocks.DCLK = 0;
3639 power_state->temperatures.min = 0;
3640 power_state->temperatures.max = 0;
3642 performance_level = &(polaris10_power_state->performance_levels
3643 [polaris10_power_state->performance_level_count++]);
3645 PP_ASSERT_WITH_CODE(
3646 (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
3647 "Performance levels exceeds SMC limit!",
3650 PP_ASSERT_WITH_CODE(
3651 (polaris10_power_state->performance_level_count <=
3652 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3653 "Performance levels exceeds Driver limit!",
3656 /* Performance levels are arranged from low to high. */
3657 performance_level->memory_clock = mclk_dep_table->entries
3658 [state_entry->ucMemoryClockIndexLow].ulMclk;
3659 if (sclk_dep_table->ucRevId == 0)
3660 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3661 [state_entry->ucEngineClockIndexLow].ulSclk;
3662 else if (sclk_dep_table->ucRevId == 1)
3663 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3664 [state_entry->ucEngineClockIndexLow].ulSclk;
3665 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3666 state_entry->ucPCIEGenLow);
3667 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3668 state_entry->ucPCIELaneHigh);
3670 performance_level = &(polaris10_power_state->performance_levels
3671 [polaris10_power_state->performance_level_count++]);
3672 performance_level->memory_clock = mclk_dep_table->entries
3673 [state_entry->ucMemoryClockIndexHigh].ulMclk;
3675 if (sclk_dep_table->ucRevId == 0)
3676 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3677 [state_entry->ucEngineClockIndexHigh].ulSclk;
3678 else if (sclk_dep_table->ucRevId == 1)
3679 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3680 [state_entry->ucEngineClockIndexHigh].ulSclk;
3682 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3683 state_entry->ucPCIEGenHigh);
3684 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3685 state_entry->ucPCIELaneHigh);
3690 static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3691 unsigned long entry_index, struct pp_power_state *state)
3694 struct polaris10_power_state *ps;
3695 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3696 struct phm_ppt_v1_information *table_info =
3697 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3698 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3699 table_info->vdd_dep_on_mclk;
3701 state->hardware.magic = PHM_VIslands_Magic;
3703 ps = (struct polaris10_power_state *)(&state->hardware);
3705 result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3706 polaris10_get_pp_table_entry_callback_func);
3708 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3709 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3710 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3712 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3713 if (dep_mclk_table->entries[0].clk !=
3714 data->vbios_boot_state.mclk_bootup_value)
3715 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3716 "does not match VBIOS boot MCLK level");
3717 if (dep_mclk_table->entries[0].vddci !=
3718 data->vbios_boot_state.vddci_bootup_value)
3719 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3720 "does not match VBIOS boot VDDCI level");
3723 /* set DC compatible flag if this state supports DC */
3724 if (!state->validation.disallowOnDC)
3725 ps->dc_compatible = true;
3727 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3728 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3730 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3731 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3736 switch (state->classification.ui_label) {
3737 case PP_StateUILabel_Performance:
3738 data->use_pcie_performance_levels = true;
3739 for (i = 0; i < ps->performance_level_count; i++) {
3740 if (data->pcie_gen_performance.max <
3741 ps->performance_levels[i].pcie_gen)
3742 data->pcie_gen_performance.max =
3743 ps->performance_levels[i].pcie_gen;
3745 if (data->pcie_gen_performance.min >
3746 ps->performance_levels[i].pcie_gen)
3747 data->pcie_gen_performance.min =
3748 ps->performance_levels[i].pcie_gen;
3750 if (data->pcie_lane_performance.max <
3751 ps->performance_levels[i].pcie_lane)
3752 data->pcie_lane_performance.max =
3753 ps->performance_levels[i].pcie_lane;
3754 if (data->pcie_lane_performance.min >
3755 ps->performance_levels[i].pcie_lane)
3756 data->pcie_lane_performance.min =
3757 ps->performance_levels[i].pcie_lane;
3760 case PP_StateUILabel_Battery:
3761 data->use_pcie_power_saving_levels = true;
3763 for (i = 0; i < ps->performance_level_count; i++) {
3764 if (data->pcie_gen_power_saving.max <
3765 ps->performance_levels[i].pcie_gen)
3766 data->pcie_gen_power_saving.max =
3767 ps->performance_levels[i].pcie_gen;
3769 if (data->pcie_gen_power_saving.min >
3770 ps->performance_levels[i].pcie_gen)
3771 data->pcie_gen_power_saving.min =
3772 ps->performance_levels[i].pcie_gen;
3774 if (data->pcie_lane_power_saving.max <
3775 ps->performance_levels[i].pcie_lane)
3776 data->pcie_lane_power_saving.max =
3777 ps->performance_levels[i].pcie_lane;
3779 if (data->pcie_lane_power_saving.min >
3780 ps->performance_levels[i].pcie_lane)
3781 data->pcie_lane_power_saving.min =
3782 ps->performance_levels[i].pcie_lane;
3793 polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
3795 uint32_t sclk, mclk, activity_percent;
3797 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3799 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3801 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3803 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
3805 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3806 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
3807 mclk / 100, sclk / 100);
3809 offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
3810 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3811 activity_percent += 0x80;
3812 activity_percent >>= 8;
3814 seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
3816 seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
3818 seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
3821 static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3823 const struct phm_set_power_state_input *states =
3824 (const struct phm_set_power_state_input *)input;
3825 const struct polaris10_power_state *polaris10_ps =
3826 cast_const_phw_polaris10_power_state(states->pnew_state);
3827 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3828 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3829 uint32_t sclk = polaris10_ps->performance_levels
3830 [polaris10_ps->performance_level_count - 1].engine_clock;
3831 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3832 uint32_t mclk = polaris10_ps->performance_levels
3833 [polaris10_ps->performance_level_count - 1].memory_clock;
3834 struct PP_Clocks min_clocks = {0};
3836 struct cgs_display_info info = {0};
3838 data->need_update_smu7_dpm_table = 0;
3840 for (i = 0; i < sclk_table->count; i++) {
3841 if (sclk == sclk_table->dpm_levels[i].value)
3845 if (i >= sclk_table->count)
3846 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3848 /* TODO: Check SCLK in DAL's minimum clocks
3849 * in case DeepSleep divider update is required.
3851 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3852 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
3853 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
3854 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3857 for (i = 0; i < mclk_table->count; i++) {
3858 if (mclk == mclk_table->dpm_levels[i].value)
3862 if (i >= mclk_table->count)
3863 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3865 cgs_get_active_displays_info(hwmgr->device, &info);
3867 if (data->display_timing.num_existing_displays != info.display_count)
3868 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3873 static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
3874 const struct polaris10_power_state *polaris10_ps)
3877 uint32_t sclk, max_sclk = 0;
3878 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3879 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3881 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3882 sclk = polaris10_ps->performance_levels[i].engine_clock;
3883 if (max_sclk < sclk)
3887 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3888 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
3889 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
3890 dpm_table->pcie_speed_table.dpm_levels
3891 [dpm_table->pcie_speed_table.count - 1].value :
3892 dpm_table->pcie_speed_table.dpm_levels[i].value);
3898 static int polaris10_request_link_speed_change_before_state_change(
3899 struct pp_hwmgr *hwmgr, const void *input)
3901 const struct phm_set_power_state_input *states =
3902 (const struct phm_set_power_state_input *)input;
3903 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3904 const struct polaris10_power_state *polaris10_nps =
3905 cast_const_phw_polaris10_power_state(states->pnew_state);
3906 const struct polaris10_power_state *polaris10_cps =
3907 cast_const_phw_polaris10_power_state(states->pcurrent_state);
3909 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
3910 uint16_t current_link_speed;
3912 if (data->force_pcie_gen == PP_PCIEGenInvalid)
3913 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
3915 current_link_speed = data->force_pcie_gen;
3917 data->force_pcie_gen = PP_PCIEGenInvalid;
3918 data->pspp_notify_required = false;
3920 if (target_link_speed > current_link_speed) {
3921 switch (target_link_speed) {
3923 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
3925 data->force_pcie_gen = PP_PCIEGen2;
3926 if (current_link_speed == PP_PCIEGen2)
3929 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
3932 data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
3936 if (target_link_speed < current_link_speed)
3937 data->pspp_notify_required = true;
3943 static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3945 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3947 if (0 == data->need_update_smu7_dpm_table)
3950 if ((0 == data->sclk_dpm_key_disabled) &&
3951 (data->need_update_smu7_dpm_table &
3952 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3953 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3954 "Trying to freeze SCLK DPM when DPM is disabled",
3956 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3957 PPSMC_MSG_SCLKDPM_FreezeLevel),
3958 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3962 if ((0 == data->mclk_dpm_key_disabled) &&
3963 (data->need_update_smu7_dpm_table &
3964 DPMTABLE_OD_UPDATE_MCLK)) {
3965 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3966 "Trying to freeze MCLK DPM when DPM is disabled",
3968 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3969 PPSMC_MSG_MCLKDPM_FreezeLevel),
3970 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3977 static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
3978 struct pp_hwmgr *hwmgr, const void *input)
3981 const struct phm_set_power_state_input *states =
3982 (const struct phm_set_power_state_input *)input;
3983 const struct polaris10_power_state *polaris10_ps =
3984 cast_const_phw_polaris10_power_state(states->pnew_state);
3985 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3986 uint32_t sclk = polaris10_ps->performance_levels
3987 [polaris10_ps->performance_level_count - 1].engine_clock;
3988 uint32_t mclk = polaris10_ps->performance_levels
3989 [polaris10_ps->performance_level_count - 1].memory_clock;
3990 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3992 struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
3993 uint32_t dpm_count, clock_percent;
3996 if (0 == data->need_update_smu7_dpm_table)
3999 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4000 dpm_table->sclk_table.dpm_levels
4001 [dpm_table->sclk_table.count - 1].value = sclk;
4003 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4004 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4005 /* Need to do calculation based on the golden DPM table
4006 * as the Heatmap GPU Clock axis is also based on the default values
4008 PP_ASSERT_WITH_CODE(
4009 (golden_dpm_table->sclk_table.dpm_levels
4010 [golden_dpm_table->sclk_table.count - 1].value != 0),
4013 dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
4015 for (i = dpm_count; i > 1; i--) {
4016 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
4019 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
4021 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4023 dpm_table->sclk_table.dpm_levels[i].value =
4024 golden_dpm_table->sclk_table.dpm_levels[i].value +
4025 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4028 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
4030 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
4032 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4034 dpm_table->sclk_table.dpm_levels[i].value =
4035 golden_dpm_table->sclk_table.dpm_levels[i].value -
4036 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4037 clock_percent) / 100;
4039 dpm_table->sclk_table.dpm_levels[i].value =
4040 golden_dpm_table->sclk_table.dpm_levels[i].value;
4045 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4046 dpm_table->mclk_table.dpm_levels
4047 [dpm_table->mclk_table.count - 1].value = mclk;
4049 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4050 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4052 PP_ASSERT_WITH_CODE(
4053 (golden_dpm_table->mclk_table.dpm_levels
4054 [golden_dpm_table->mclk_table.count-1].value != 0),
4057 dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
4058 for (i = dpm_count; i > 1; i--) {
4059 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
4060 clock_percent = ((mclk -
4061 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
4062 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4064 dpm_table->mclk_table.dpm_levels[i].value =
4065 golden_dpm_table->mclk_table.dpm_levels[i].value +
4066 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4067 clock_percent) / 100;
4069 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
4071 (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
4073 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4075 dpm_table->mclk_table.dpm_levels[i].value =
4076 golden_dpm_table->mclk_table.dpm_levels[i].value -
4077 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4078 clock_percent) / 100;
4080 dpm_table->mclk_table.dpm_levels[i].value =
4081 golden_dpm_table->mclk_table.dpm_levels[i].value;
4086 if (data->need_update_smu7_dpm_table &
4087 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4088 result = polaris10_populate_all_graphic_levels(hwmgr);
4089 PP_ASSERT_WITH_CODE((0 == result),
4090 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4094 if (data->need_update_smu7_dpm_table &
4095 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4096 /*populate MCLK dpm table to SMU7 */
4097 result = polaris10_populate_all_memory_levels(hwmgr);
4098 PP_ASSERT_WITH_CODE((0 == result),
4099 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4106 static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4107 struct polaris10_single_dpm_table *dpm_table,
4108 uint32_t low_limit, uint32_t high_limit)
4112 for (i = 0; i < dpm_table->count; i++) {
4113 if ((dpm_table->dpm_levels[i].value < low_limit)
4114 || (dpm_table->dpm_levels[i].value > high_limit))
4115 dpm_table->dpm_levels[i].enabled = false;
4117 dpm_table->dpm_levels[i].enabled = true;
4123 static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
4124 const struct polaris10_power_state *polaris10_ps)
4127 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4128 uint32_t high_limit_count;
4130 PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
4131 "power state did not have any performance level",
4134 high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
4136 polaris10_trim_single_dpm_states(hwmgr,
4137 &(data->dpm_table.sclk_table),
4138 polaris10_ps->performance_levels[0].engine_clock,
4139 polaris10_ps->performance_levels[high_limit_count].engine_clock);
4141 polaris10_trim_single_dpm_states(hwmgr,
4142 &(data->dpm_table.mclk_table),
4143 polaris10_ps->performance_levels[0].memory_clock,
4144 polaris10_ps->performance_levels[high_limit_count].memory_clock);
4149 static int polaris10_generate_dpm_level_enable_mask(
4150 struct pp_hwmgr *hwmgr, const void *input)
4153 const struct phm_set_power_state_input *states =
4154 (const struct phm_set_power_state_input *)input;
4155 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4156 const struct polaris10_power_state *polaris10_ps =
4157 cast_const_phw_polaris10_power_state(states->pnew_state);
4159 result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
4163 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4164 phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4165 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4166 phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4167 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4168 phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4173 int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4175 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4176 PPSMC_MSG_UVDDPM_Enable :
4177 PPSMC_MSG_UVDDPM_Disable);
4180 int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4182 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4183 PPSMC_MSG_VCEDPM_Enable :
4184 PPSMC_MSG_VCEDPM_Disable);
4187 int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4189 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4190 PPSMC_MSG_SAMUDPM_Enable :
4191 PPSMC_MSG_SAMUDPM_Disable);
4194 int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4196 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4197 uint32_t mm_boot_level_offset, mm_boot_level_value;
4198 struct phm_ppt_v1_information *table_info =
4199 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4202 data->smc_state_table.UvdBootLevel = 0;
4203 if (table_info->mm_dep_table->count > 0)
4204 data->smc_state_table.UvdBootLevel =
4205 (uint8_t) (table_info->mm_dep_table->count - 1);
4206 mm_boot_level_offset = data->dpm_table_start +
4207 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4208 mm_boot_level_offset /= 4;
4209 mm_boot_level_offset *= 4;
4210 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4211 CGS_IND_REG__SMC, mm_boot_level_offset);
4212 mm_boot_level_value &= 0x00FFFFFF;
4213 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4214 cgs_write_ind_register(hwmgr->device,
4215 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4217 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4218 PHM_PlatformCaps_UVDDPM) ||
4219 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4220 PHM_PlatformCaps_StablePState))
4221 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4222 PPSMC_MSG_UVDDPM_SetEnabledMask,
4223 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4226 return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
4229 static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4231 const struct phm_set_power_state_input *states =
4232 (const struct phm_set_power_state_input *)input;
4233 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4234 const struct polaris10_power_state *polaris10_nps =
4235 cast_const_phw_polaris10_power_state(states->pnew_state);
4236 const struct polaris10_power_state *polaris10_cps =
4237 cast_const_phw_polaris10_power_state(states->pcurrent_state);
4239 uint32_t mm_boot_level_offset, mm_boot_level_value;
4240 struct phm_ppt_v1_information *table_info =
4241 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4243 if (polaris10_nps->vce_clks.evclk > 0 &&
4244 (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
4246 data->smc_state_table.VceBootLevel =
4247 (uint8_t) (table_info->mm_dep_table->count - 1);
4249 mm_boot_level_offset = data->dpm_table_start +
4250 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4251 mm_boot_level_offset /= 4;
4252 mm_boot_level_offset *= 4;
4253 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4254 CGS_IND_REG__SMC, mm_boot_level_offset);
4255 mm_boot_level_value &= 0xFF00FFFF;
4256 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4257 cgs_write_ind_register(hwmgr->device,
4258 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4260 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4261 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4262 PPSMC_MSG_VCEDPM_SetEnabledMask,
4263 (uint32_t)1 << data->smc_state_table.VceBootLevel);
4265 polaris10_enable_disable_vce_dpm(hwmgr, true);
4266 } else if (polaris10_nps->vce_clks.evclk == 0 &&
4267 polaris10_cps != NULL &&
4268 polaris10_cps->vce_clks.evclk > 0)
4269 polaris10_enable_disable_vce_dpm(hwmgr, false);
4275 int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4277 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4278 uint32_t mm_boot_level_offset, mm_boot_level_value;
4281 data->smc_state_table.SamuBootLevel = 0;
4282 mm_boot_level_offset = data->dpm_table_start +
4283 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4284 mm_boot_level_offset /= 4;
4285 mm_boot_level_offset *= 4;
4286 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4287 CGS_IND_REG__SMC, mm_boot_level_offset);
4288 mm_boot_level_value &= 0xFFFFFF00;
4289 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4290 cgs_write_ind_register(hwmgr->device,
4291 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4293 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4294 PHM_PlatformCaps_StablePState))
4295 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4296 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4297 (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4300 return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
4303 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4305 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4308 uint32_t low_sclk_interrupt_threshold = 0;
4310 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4311 PHM_PlatformCaps_SclkThrottleLowNotification)
4312 && (hwmgr->gfx_arbiter.sclk_threshold !=
4313 data->low_sclk_interrupt_threshold)) {
4314 data->low_sclk_interrupt_threshold =
4315 hwmgr->gfx_arbiter.sclk_threshold;
4316 low_sclk_interrupt_threshold =
4317 data->low_sclk_interrupt_threshold;
4319 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4321 result = polaris10_copy_bytes_to_smc(
4323 data->dpm_table_start +
4324 offsetof(SMU74_Discrete_DpmTable,
4325 LowSclkInterruptThreshold),
4326 (uint8_t *)&low_sclk_interrupt_threshold,
4334 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4336 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4338 if (data->need_update_smu7_dpm_table &
4339 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4340 return polaris10_program_memory_timing_parameters(hwmgr);
4345 static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4347 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4349 if (0 == data->need_update_smu7_dpm_table)
4352 if ((0 == data->sclk_dpm_key_disabled) &&
4353 (data->need_update_smu7_dpm_table &
4354 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4356 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4357 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4359 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4360 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4361 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4365 if ((0 == data->mclk_dpm_key_disabled) &&
4366 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4368 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4369 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4371 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4372 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4373 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4377 data->need_update_smu7_dpm_table = 0;
4382 static int polaris10_notify_link_speed_change_after_state_change(
4383 struct pp_hwmgr *hwmgr, const void *input)
4385 const struct phm_set_power_state_input *states =
4386 (const struct phm_set_power_state_input *)input;
4387 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4388 const struct polaris10_power_state *polaris10_ps =
4389 cast_const_phw_polaris10_power_state(states->pnew_state);
4390 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
4393 if (data->pspp_notify_required) {
4394 if (target_link_speed == PP_PCIEGen3)
4395 request = PCIE_PERF_REQ_GEN3;
4396 else if (target_link_speed == PP_PCIEGen2)
4397 request = PCIE_PERF_REQ_GEN2;
4399 request = PCIE_PERF_REQ_GEN1;
4401 if (request == PCIE_PERF_REQ_GEN1 &&
4402 phm_get_current_pcie_speed(hwmgr) > 0)
4405 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4406 if (PP_PCIEGen2 == target_link_speed)
4407 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4409 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4416 static int polaris10_notify_smc_display(struct pp_hwmgr *hwmgr)
4418 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4420 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4421 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2);
4422 return (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL;
4425 static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4427 int tmp_result, result = 0;
4428 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4430 tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4431 PP_ASSERT_WITH_CODE((0 == tmp_result),
4432 "Failed to find DPM states clocks in DPM table!",
4433 result = tmp_result);
4435 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4436 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4438 polaris10_request_link_speed_change_before_state_change(hwmgr, input);
4439 PP_ASSERT_WITH_CODE((0 == tmp_result),
4440 "Failed to request link speed change before state change!",
4441 result = tmp_result);
4444 tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
4445 PP_ASSERT_WITH_CODE((0 == tmp_result),
4446 "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4448 tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4449 PP_ASSERT_WITH_CODE((0 == tmp_result),
4450 "Failed to populate and upload SCLK MCLK DPM levels!",
4451 result = tmp_result);
4453 tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
4454 PP_ASSERT_WITH_CODE((0 == tmp_result),
4455 "Failed to generate DPM level enabled mask!",
4456 result = tmp_result);
4458 tmp_result = polaris10_update_vce_dpm(hwmgr, input);
4459 PP_ASSERT_WITH_CODE((0 == tmp_result),
4460 "Failed to update VCE DPM!",
4461 result = tmp_result);
4463 tmp_result = polaris10_update_sclk_threshold(hwmgr);
4464 PP_ASSERT_WITH_CODE((0 == tmp_result),
4465 "Failed to update SCLK threshold!",
4466 result = tmp_result);
4468 tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
4469 PP_ASSERT_WITH_CODE((0 == tmp_result),
4470 "Failed to program memory timing parameters!",
4471 result = tmp_result);
4473 tmp_result = polaris10_notify_smc_display(hwmgr);
4474 PP_ASSERT_WITH_CODE((0 == tmp_result),
4475 "Failed to notify smc display settings!",
4476 result = tmp_result);
4478 tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
4479 PP_ASSERT_WITH_CODE((0 == tmp_result),
4480 "Failed to unfreeze SCLK MCLK DPM!",
4481 result = tmp_result);
4483 tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
4484 PP_ASSERT_WITH_CODE((0 == tmp_result),
4485 "Failed to upload DPM level enabled mask!",
4486 result = tmp_result);
4488 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4489 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4491 polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
4492 PP_ASSERT_WITH_CODE((0 == tmp_result),
4493 "Failed to notify link speed change after state change!",
4494 result = tmp_result);
4496 data->apply_optimized_settings = false;
4500 static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4502 hwmgr->thermal_controller.
4503 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4505 if (phm_is_hw_access_blocked(hwmgr))
4508 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4509 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4513 int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4515 PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4517 return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
4520 int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4522 uint32_t num_active_displays = 0;
4523 struct cgs_display_info info = {0};
4524 info.mode_info = NULL;
4526 cgs_get_active_displays_info(hwmgr->device, &info);
4528 num_active_displays = info.display_count;
4530 if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
4531 polaris10_notify_smc_display_change(hwmgr, false);
4537 * Programs the display gap
4539 * @param hwmgr the address of the powerplay hardware manager.
4542 int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
4544 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4545 uint32_t num_active_displays = 0;
4546 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4547 uint32_t display_gap2;
4548 uint32_t pre_vbi_time_in_us;
4549 uint32_t frame_time_in_us;
4551 uint32_t refresh_rate = 0;
4552 struct cgs_display_info info = {0};
4553 struct cgs_mode_info mode_info;
4555 info.mode_info = &mode_info;
4557 cgs_get_active_displays_info(hwmgr->device, &info);
4558 num_active_displays = info.display_count;
4560 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4561 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4563 ref_clock = mode_info.ref_clock;
4564 refresh_rate = mode_info.refresh_rate;
4566 if (0 == refresh_rate)
4569 frame_time_in_us = 1000000 / refresh_rate;
4571 pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4572 data->frame_time_x2 = frame_time_in_us * 2 / 100;
4574 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4576 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4578 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4580 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4586 int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4588 return polaris10_program_display_gap(hwmgr);
4592 * Set maximum target operating fan output RPM
4594 * @param hwmgr: the address of the powerplay hardware manager.
4595 * @param usMaxFanRpm: max operating fan RPM value.
4596 * @return The response that came from the SMC.
4598 static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4600 hwmgr->thermal_controller.
4601 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4603 if (phm_is_hw_access_blocked(hwmgr))
4606 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4607 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4610 int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
4611 const void *thermal_interrupt_info)
4616 bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4618 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4619 bool is_update_required = false;
4620 struct cgs_display_info info = {0, 0, NULL};
4622 cgs_get_active_displays_info(hwmgr->device, &info);
4624 if (data->display_timing.num_existing_displays != info.display_count)
4625 is_update_required = true;
4626 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4627 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4628 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
4629 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4630 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4631 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4632 is_update_required = true;
4634 return is_update_required;
4637 static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4638 const struct polaris10_performance_level *pl2)
4640 return ((pl1->memory_clock == pl2->memory_clock) &&
4641 (pl1->engine_clock == pl2->engine_clock) &&
4642 (pl1->pcie_gen == pl2->pcie_gen) &&
4643 (pl1->pcie_lane == pl2->pcie_lane));
4646 int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
4648 const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4649 const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
4652 if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4655 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4656 if (psa->performance_level_count != psb->performance_level_count) {
4661 for (i = 0; i < psa->performance_level_count; i++) {
4662 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4663 /* If we have found even one performance level pair that is different the states are different. */
4669 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4670 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4671 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4672 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4677 int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
4679 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4681 uint32_t vbios_version;
4683 /* Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4685 phm_get_mc_microcode_version(hwmgr);
4686 vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4687 /* Full version of MC ucode has already been loaded. */
4688 if (vbios_version == 0) {
4689 data->need_long_memory_training = false;
4693 data->need_long_memory_training = false;
4696 * PPMCME_FirmwareDescriptorEntry *pfd = NULL;
4697 pfd = &tonga_mcmeFirmware;
4698 if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
4699 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
4700 pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4701 pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4707 * Read clock related registers.
4709 * @param hwmgr the address of the powerplay hardware manager.
4712 static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
4714 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4716 data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4717 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4718 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4720 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4721 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4722 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4724 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4725 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4726 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4732 * Find out if memory is GDDR5.
4734 * @param hwmgr the address of the powerplay hardware manager.
4737 static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
4739 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4742 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4744 data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4745 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4746 MC_SEQ_MISC0_GDDR5_SHIFT));
4752 * Enables Dynamic Power Management by SMC
4754 * @param hwmgr the address of the powerplay hardware manager.
4757 static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4759 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4760 GENERAL_PWRMGT, STATIC_PM_EN, 1);
4766 * Initialize PowerGating States for different engines
4768 * @param hwmgr the address of the powerplay hardware manager.
4771 static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
4773 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4775 data->uvd_power_gated = false;
4776 data->vce_power_gated = false;
4777 data->samu_power_gated = false;
4782 static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4784 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4785 data->low_sclk_interrupt_threshold = 0;
4790 int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
4792 int tmp_result, result = 0;
4794 polaris10_upload_mc_firmware(hwmgr);
4796 tmp_result = polaris10_read_clock_registers(hwmgr);
4797 PP_ASSERT_WITH_CODE((0 == tmp_result),
4798 "Failed to read clock registers!", result = tmp_result);
4800 tmp_result = polaris10_get_memory_type(hwmgr);
4801 PP_ASSERT_WITH_CODE((0 == tmp_result),
4802 "Failed to get memory type!", result = tmp_result);
4804 tmp_result = polaris10_enable_acpi_power_management(hwmgr);
4805 PP_ASSERT_WITH_CODE((0 == tmp_result),
4806 "Failed to enable ACPI power management!", result = tmp_result);
4808 tmp_result = polaris10_init_power_gate_state(hwmgr);
4809 PP_ASSERT_WITH_CODE((0 == tmp_result),
4810 "Failed to init power gate state!", result = tmp_result);
4812 tmp_result = phm_get_mc_microcode_version(hwmgr);
4813 PP_ASSERT_WITH_CODE((0 == tmp_result),
4814 "Failed to get MC microcode version!", result = tmp_result);
4816 tmp_result = polaris10_init_sclk_threshold(hwmgr);
4817 PP_ASSERT_WITH_CODE((0 == tmp_result),
4818 "Failed to init sclk threshold!", result = tmp_result);
4823 static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
4825 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4827 if (!data->soft_pp_table) {
4828 data->soft_pp_table = kmemdup(hwmgr->soft_pp_table,
4829 hwmgr->soft_pp_table_size,
4831 if (!data->soft_pp_table)
4835 *table = (char *)&data->soft_pp_table;
4837 return hwmgr->soft_pp_table_size;
4840 static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
4842 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4844 if (!data->soft_pp_table) {
4845 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
4846 if (!data->soft_pp_table)
4850 memcpy(data->soft_pp_table, buf, size);
4852 hwmgr->soft_pp_table = data->soft_pp_table;
4854 /* TODO: re-init powerplay to implement modified pptable */
4859 static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
4860 enum pp_clock_type type, uint32_t mask)
4862 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4864 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
4869 if (!data->sclk_dpm_key_disabled)
4870 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4871 PPSMC_MSG_SCLKDPM_SetEnabledMask,
4872 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
4875 if (!data->mclk_dpm_key_disabled)
4876 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4877 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4878 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
4882 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4888 if (!data->pcie_dpm_key_disabled)
4889 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4890 PPSMC_MSG_PCIeDPM_ForceLevel,
4901 static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
4903 uint32_t speedCntl = 0;
4905 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
4906 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
4907 ixPCIE_LC_SPEED_CNTL);
4908 return((uint16_t)PHM_GET_FIELD(speedCntl,
4909 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4912 static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
4913 enum pp_clock_type type, char *buf)
4915 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4916 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4917 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4918 struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4919 int i, now, size = 0;
4920 uint32_t clock, pcie_speed;
4924 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4925 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4927 for (i = 0; i < sclk_table->count; i++) {
4928 if (clock > sclk_table->dpm_levels[i].value)
4934 for (i = 0; i < sclk_table->count; i++)
4935 size += sprintf(buf + size, "%d: %uMhz %s\n",
4936 i, sclk_table->dpm_levels[i].value / 100,
4937 (i == now) ? "*" : "");
4940 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4941 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4943 for (i = 0; i < mclk_table->count; i++) {
4944 if (clock > mclk_table->dpm_levels[i].value)
4950 for (i = 0; i < mclk_table->count; i++)
4951 size += sprintf(buf + size, "%d: %uMhz %s\n",
4952 i, mclk_table->dpm_levels[i].value / 100,
4953 (i == now) ? "*" : "");
4956 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
4957 for (i = 0; i < pcie_table->count; i++) {
4958 if (pcie_speed != pcie_table->dpm_levels[i].value)
4964 for (i = 0; i < pcie_table->count; i++)
4965 size += sprintf(buf + size, "%d: %s %s\n", i,
4966 (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
4967 (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
4968 (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
4969 (i == now) ? "*" : "");
4977 static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4980 /* stop auto-manage */
4981 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4982 PHM_PlatformCaps_MicrocodeFanControl))
4983 polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
4984 polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
4986 /* restart auto-manage */
4987 polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
4992 static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4994 if (hwmgr->fan_ctrl_is_in_default_mode)
4995 return hwmgr->fan_ctrl_default_mode;
4997 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4998 CG_FDO_CTRL2, FDO_PWM_MODE);
5001 static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
5002 .backend_init = &polaris10_hwmgr_backend_init,
5003 .backend_fini = &polaris10_hwmgr_backend_fini,
5004 .asic_setup = &polaris10_setup_asic_task,
5005 .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
5006 .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
5007 .force_dpm_level = &polaris10_force_dpm_level,
5008 .power_state_set = polaris10_set_power_state_tasks,
5009 .get_power_state_size = polaris10_get_power_state_size,
5010 .get_mclk = polaris10_dpm_get_mclk,
5011 .get_sclk = polaris10_dpm_get_sclk,
5012 .patch_boot_state = polaris10_dpm_patch_boot_state,
5013 .get_pp_table_entry = polaris10_get_pp_table_entry,
5014 .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
5015 .print_current_perforce_level = polaris10_print_current_perforce_level,
5016 .powerdown_uvd = polaris10_phm_powerdown_uvd,
5017 .powergate_uvd = polaris10_phm_powergate_uvd,
5018 .powergate_vce = polaris10_phm_powergate_vce,
5019 .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
5020 .update_clock_gatings = polaris10_phm_update_clock_gatings,
5021 .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
5022 .display_config_changed = polaris10_display_configuration_changed_task,
5023 .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
5024 .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
5025 .get_temperature = polaris10_thermal_get_temperature,
5026 .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
5027 .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
5028 .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
5029 .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
5030 .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
5031 .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
5032 .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
5033 .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
5034 .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
5035 .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
5036 .check_states_equal = polaris10_check_states_equal,
5037 .set_fan_control_mode = polaris10_set_fan_control_mode,
5038 .get_fan_control_mode = polaris10_get_fan_control_mode,
5039 .get_pp_table = polaris10_get_pp_table,
5040 .set_pp_table = polaris10_set_pp_table,
5041 .force_clock_level = polaris10_force_clock_level,
5042 .print_clock_levels = polaris10_print_clock_levels,
5043 .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
5046 int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
5048 struct polaris10_hwmgr *data;
5050 data = kzalloc (sizeof(struct polaris10_hwmgr), GFP_KERNEL);
5054 hwmgr->backend = data;
5055 hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
5056 hwmgr->pptable_func = &tonga_pptable_funcs;
5057 pp_polaris10_thermal_initialize(hwmgr);