2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/errno.h>
25 #include "hardwaremanager.h"
26 #include "power_state.h"
31 #define PHM_FUNC_CHECK(hw) \
33 if ((hw) == NULL || (hw)->hwmgr_func == NULL) \
37 void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
39 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);
40 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);
41 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);
42 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);
43 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);
44 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);
45 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);
46 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);
47 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);
48 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);
50 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);
51 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);
52 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);
54 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
56 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);
57 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);
59 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);
61 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
62 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
64 if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
65 acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
66 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
69 bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
71 return hwmgr->block_hw_access;
74 int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
76 hwmgr->block_hw_access = block;
80 int phm_setup_asic(struct pp_hwmgr *hwmgr)
82 PHM_FUNC_CHECK(hwmgr);
84 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
85 PHM_PlatformCaps_TablelessHardwareInterface)) {
86 if (NULL != hwmgr->hwmgr_func->asic_setup)
87 return hwmgr->hwmgr_func->asic_setup(hwmgr);
89 return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
96 int phm_power_down_asic(struct pp_hwmgr *hwmgr)
98 PHM_FUNC_CHECK(hwmgr);
100 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
101 PHM_PlatformCaps_TablelessHardwareInterface)) {
102 if (NULL != hwmgr->hwmgr_func->power_off_asic)
103 return hwmgr->hwmgr_func->power_off_asic(hwmgr);
105 return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic),
112 int phm_set_power_state(struct pp_hwmgr *hwmgr,
113 const struct pp_hw_power_state *pcurrent_state,
114 const struct pp_hw_power_state *pnew_power_state)
116 struct phm_set_power_state_input states;
118 PHM_FUNC_CHECK(hwmgr);
120 states.pcurrent_state = pcurrent_state;
121 states.pnew_state = pnew_power_state;
123 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
124 PHM_PlatformCaps_TablelessHardwareInterface)) {
125 if (NULL != hwmgr->hwmgr_func->power_state_set)
126 return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
128 return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
134 int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
138 PHM_FUNC_CHECK(hwmgr);
140 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
141 PHM_PlatformCaps_TablelessHardwareInterface)) {
142 if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
143 ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
145 ret = phm_dispatch_table(hwmgr,
146 &(hwmgr->enable_dynamic_state_management),
150 enabled = ret == 0 ? true : false;
152 cgs_notify_dpm_enabled(hwmgr->device, enabled);
157 int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
159 PHM_FUNC_CHECK(hwmgr);
161 if (hwmgr->hwmgr_func->force_dpm_level != NULL)
162 return hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
167 int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
168 struct pp_power_state *adjusted_ps,
169 const struct pp_power_state *current_ps)
171 PHM_FUNC_CHECK(hwmgr);
173 if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
174 return hwmgr->hwmgr_func->apply_state_adjust_rules(
181 int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
183 PHM_FUNC_CHECK(hwmgr);
185 if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
186 return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
190 int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
192 PHM_FUNC_CHECK(hwmgr);
194 if (hwmgr->hwmgr_func->powergate_uvd != NULL)
195 return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
199 int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
201 PHM_FUNC_CHECK(hwmgr);
203 if (hwmgr->hwmgr_func->powergate_vce != NULL)
204 return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
208 int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
210 PHM_FUNC_CHECK(hwmgr);
212 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
213 PHM_PlatformCaps_TablelessHardwareInterface)) {
214 if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
215 return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
217 return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
222 int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
224 PHM_FUNC_CHECK(hwmgr);
226 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
227 PHM_PlatformCaps_TablelessHardwareInterface)) {
228 if (NULL != hwmgr->hwmgr_func->display_config_changed)
229 hwmgr->hwmgr_func->display_config_changed(hwmgr);
231 return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
235 int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
237 PHM_FUNC_CHECK(hwmgr);
239 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
240 PHM_PlatformCaps_TablelessHardwareInterface))
241 if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
242 hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
247 int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
249 PHM_FUNC_CHECK(hwmgr);
251 if (hwmgr->hwmgr_func->stop_thermal_controller == NULL)
254 return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
257 int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
259 PHM_FUNC_CHECK(hwmgr);
261 if (hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
264 return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
268 * Initializes the thermal controller subsystem.
270 * @param pHwMgr the address of the powerplay hardware manager.
271 * @param pTemperatureRange the address of the structure holding the temperature range.
272 * @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
274 int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range)
276 return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
280 bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
282 PHM_FUNC_CHECK(hwmgr);
284 if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
287 return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
291 int phm_check_states_equal(struct pp_hwmgr *hwmgr,
292 const struct pp_hw_power_state *pstate1,
293 const struct pp_hw_power_state *pstate2,
296 PHM_FUNC_CHECK(hwmgr);
298 if (hwmgr->hwmgr_func->check_states_equal == NULL)
301 return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
304 int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
305 const struct amd_pp_display_configuration *display_config)
307 PHM_FUNC_CHECK(hwmgr);
309 if (hwmgr->hwmgr_func->store_cc6_data == NULL)
312 hwmgr->display_config = *display_config;
313 /* to do pass other display configuration in furture */
315 if (hwmgr->hwmgr_func->store_cc6_data)
316 hwmgr->hwmgr_func->store_cc6_data(hwmgr,
317 display_config->cpu_pstate_separation_time,
318 display_config->cpu_cc6_disable,
319 display_config->cpu_pstate_disable,
320 display_config->nb_pstate_switch_disable);
325 int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
326 struct amd_pp_simple_clock_info *info)
328 PHM_FUNC_CHECK(hwmgr);
330 if (info == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
332 return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
335 int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
337 PHM_FUNC_CHECK(hwmgr);
339 if (hwmgr->hwmgr_func->set_cpu_power_state != NULL)
340 return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);
346 int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
347 PHM_PerformanceLevelDesignation designation, uint32_t index,
348 PHM_PerformanceLevel *level)
350 PHM_FUNC_CHECK(hwmgr);
351 if (hwmgr->hwmgr_func->get_performance_level == NULL)
354 return hwmgr->hwmgr_func->get_performance_level(hwmgr, state, designation, index, level);
363 * @param pHwMgr the address of the powerplay hardware manager.
364 * @param pPowerState the address of the Power State structure.
365 * @param pClockInfo the address of PP_ClockInfo structure where the result will be returned.
366 * @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the back-end.
368 int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *pclock_info,
369 PHM_PerformanceLevelDesignation designation)
372 PHM_PerformanceLevel performance_level;
374 PHM_FUNC_CHECK(hwmgr);
376 PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL);
377 PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL);
379 result = phm_get_performance_level(hwmgr, state, PHM_PerformanceLevelDesignation_Activity, 0, &performance_level);
381 PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result);
384 pclock_info->min_mem_clk = performance_level.memory_clock;
385 pclock_info->min_eng_clk = performance_level.coreClock;
386 pclock_info->min_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
389 result = phm_get_performance_level(hwmgr, state, designation,
390 (hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1), &performance_level);
392 PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result);
394 pclock_info->max_mem_clk = performance_level.memory_clock;
395 pclock_info->max_eng_clk = performance_level.coreClock;
396 pclock_info->max_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
401 int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
403 PHM_FUNC_CHECK(hwmgr);
405 if (hwmgr->hwmgr_func->get_current_shallow_sleep_clocks == NULL)
408 return hwmgr->hwmgr_func->get_current_shallow_sleep_clocks(hwmgr, state, clock_info);
412 int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
414 PHM_FUNC_CHECK(hwmgr);
416 if (hwmgr->hwmgr_func->get_clock_by_type == NULL)
419 return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks);
423 int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
425 PHM_FUNC_CHECK(hwmgr);
427 if (hwmgr->hwmgr_func->get_max_high_clocks == NULL)
430 return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks);