drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/fb.h>
  26 #include "linux/delay.h"
  27
  28 #include "hwmgr.h"
  29 #include "fiji_smumgr.h"
  30 #include "atombios.h"
  31 #include "hardwaremanager.h"
  32 #include "ppatomctrl.h"
  33 #include "atombios.h"
  34 #include "cgs_common.h"
  35 #include "fiji_dyn_defaults.h"
  36 #include "fiji_powertune.h"
  37 #include "smu73.h"
  38 #include "smu/smu_7_1_3_d.h"
  39 #include "smu/smu_7_1_3_sh_mask.h"
  40 #include "gmc/gmc_8_1_d.h"
  41 #include "gmc/gmc_8_1_sh_mask.h"
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44 #include "dce/dce_10_0_d.h"
  45 #include "dce/dce_10_0_sh_mask.h"
  46 #include "pppcielanes.h"
  47 #include "fiji_hwmgr.h"
  48 #include "tonga_processpptables.h"
  49 #include "tonga_pptable.h"
  50 #include "pp_debug.h"
  51 #include "pp_acpi.h"
  52 #include "amd_pcie_helpers.h"
  53
  54 #define VOLTAGE_SCALE   4
  55 #define SMC_RAM_END             0x40000
  56 #define VDDC_VDDCI_DELTA        300
  57
  58 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  59 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  60 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  61
  62 #define MC_CG_ARB_FREQ_F0           0x0a /* boot-up default */
  63 #define MC_CG_ARB_FREQ_F1           0x0b
  64 #define MC_CG_ARB_FREQ_F2           0x0c
  65 #define MC_CG_ARB_FREQ_F3           0x0d
  66
  67 /* From smc_reg.h */
  68 #define SMC_CG_IND_START            0xc0030000
  69 #define SMC_CG_IND_END              0xc0040000  /* First byte after SMC_CG_IND */
  70
  71 #define VOLTAGE_SCALE               4
  72 #define VOLTAGE_VID_OFFSET_SCALE1   625
  73 #define VOLTAGE_VID_OFFSET_SCALE2   100
  74
  75 #define VDDC_VDDCI_DELTA            300
  76
  77 #define ixSWRST_COMMAND_1           0x1400103
  78 #define MC_SEQ_CNTL__CAC_EN_MASK    0x40000000
  79
  80 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
  81 enum DPM_EVENT_SRC {
  82     DPM_EVENT_SRC_ANALOG = 0,               /* Internal analog trip point */
  83     DPM_EVENT_SRC_EXTERNAL = 1,             /* External (GPIO 17) signal */
  84     DPM_EVENT_SRC_DIGITAL = 2,              /* Internal digital trip point (DIG_THERM_DPM) */
  85     DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,   /* Internal analog or external */
  86     DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4   /* Internal digital or external */
  87 };
  88
  89 enum DISPLAY_GAP {
  90         DISPLAY_GAP_VBLANK_OR_WM = 0,   /* Wait for vblank or MCHG watermark. */
  91         DISPLAY_GAP_VBLANK       = 1,   /* Wait for vblank. */
  92         DISPLAY_GAP_WATERMARK    = 2,   /* Wait for MCHG watermark. */
  93         DISPLAY_GAP_IGNORE       = 3    /* Do not wait. */
  94 };
  95
  96 /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
  97  * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
  98  */
  99 uint16_t fiji_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0},
 100                                                 {600, 1050, 6, 1} };
 101
 102 /* [FF, SS] type, [] 4 voltage ranges, and
 103  * [Floor Freq, Boundary Freq, VID min , VID max]
 104  */
 105 uint32_t fiji_clock_stretcher_ddt_table[2][4][4] =
 106 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
 107   { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
 108
 109 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
 110  * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
 111  */
 112 uint8_t fiji_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5},
 113                                                   {0, 2, 4, 5, 6, 5} };
 114
 115 const unsigned long PhwFiji_Magic = (unsigned long)(PHM_VIslands_Magic);
 116
 117 struct fiji_power_state *cast_phw_fiji_power_state(
 118                                   struct pp_hw_power_state *hw_ps)
 119 {
 120         PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
 121                                 "Invalid Powerstate Type!",
 122                                  return NULL;);
 123
 124         return (struct fiji_power_state *)hw_ps;
 125 }
 126
 127 const struct fiji_power_state *cast_const_phw_fiji_power_state(
 128                                  const struct pp_hw_power_state *hw_ps)
 129 {
 130         PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
 131                                 "Invalid Powerstate Type!",
 132                                  return NULL;);
 133
 134         return (const struct fiji_power_state *)hw_ps;
 135 }
 136
 137 static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr)
 138 {
 139         return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
 140                         CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
 141                         ? true : false;
 142 }
 143
 144 static void fiji_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 145 {
 146         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 147         struct fiji_ulv_parm *ulv = &data->ulv;
 148
 149         ulv->cg_ulv_parameter = PPFIJI_CGULVPARAMETER_DFLT;
 150         data->voting_rights_clients0 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT0;
 151         data->voting_rights_clients1 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT1;
 152         data->voting_rights_clients2 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT2;
 153         data->voting_rights_clients3 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT3;
 154         data->voting_rights_clients4 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT4;
 155         data->voting_rights_clients5 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT5;
 156         data->voting_rights_clients6 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT6;
 157         data->voting_rights_clients7 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT7;
 158
 159         data->static_screen_threshold_unit =
 160                         PPFIJI_STATICSCREENTHRESHOLDUNIT_DFLT;
 161         data->static_screen_threshold =
 162                         PPFIJI_STATICSCREENTHRESHOLD_DFLT;
 163
 164         /* Unset ABM cap as it moved to DAL.
 165          * Add PHM_PlatformCaps_NonABMSupportInPPLib
 166          * for re-direct ABM related request to DAL
 167          */
 168         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 169                         PHM_PlatformCaps_ABM);
 170         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 171                         PHM_PlatformCaps_NonABMSupportInPPLib);
 172
 173         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 174                         PHM_PlatformCaps_DynamicACTiming);
 175
 176         fiji_initialize_power_tune_defaults(hwmgr);
 177
 178         data->mclk_stutter_mode_threshold = 60000;
 179         data->pcie_gen_performance.max = PP_PCIEGen1;
 180         data->pcie_gen_performance.min = PP_PCIEGen3;
 181         data->pcie_gen_power_saving.max = PP_PCIEGen1;
 182         data->pcie_gen_power_saving.min = PP_PCIEGen3;
 183         data->pcie_lane_performance.max = 0;
 184         data->pcie_lane_performance.min = 16;
 185         data->pcie_lane_power_saving.max = 0;
 186         data->pcie_lane_power_saving.min = 16;
 187
 188         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 189                         PHM_PlatformCaps_DynamicUVDState);
 190 }
 191
 192 static int fiji_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
 193         phm_ppt_v1_voltage_lookup_table *lookup_table,
 194         uint16_t virtual_voltage_id, int32_t *sclk)
 195 {
 196         uint8_t entryId;
 197         uint8_t voltageId;
 198         struct phm_ppt_v1_information *table_info =
 199                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 200
 201         PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);
 202
 203         /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
 204         for (entryId = 0; entryId < table_info->vdd_dep_on_sclk->count; entryId++) {
 205                 voltageId = table_info->vdd_dep_on_sclk->entries[entryId].vddInd;
 206                 if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
 207                         break;
 208         }
 209
 210         PP_ASSERT_WITH_CODE(entryId < table_info->vdd_dep_on_sclk->count,
 211                         "Can't find requested voltage id in vdd_dep_on_sclk table!",
 212                         return -EINVAL;
 213                         );
 214
 215         *sclk = table_info->vdd_dep_on_sclk->entries[entryId].clk;
 216
 217         return 0;
 218 }
 219
 220 /**
 221 * Get Leakage VDDC based on leakage ID.
 222 *
 223 * @param    hwmgr  the address of the powerplay hardware manager.
 224 * @return   always 0
 225 */
 226 static int fiji_get_evv_voltages(struct pp_hwmgr *hwmgr)
 227 {
 228         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 229         uint16_t    vv_id;
 230         uint16_t    vddc = 0;
 231         uint16_t    evv_default = 1150;
 232         uint16_t    i, j;
 233         uint32_t  sclk = 0;
 234         struct phm_ppt_v1_information *table_info =
 235                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 236         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
 237                         table_info->vdd_dep_on_sclk;
 238         int result;
 239
 240         for (i = 0; i < FIJI_MAX_LEAKAGE_COUNT; i++) {
 241                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 242                 if (!fiji_get_sclk_for_voltage_evv(hwmgr,
 243                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
 244                         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 245                                         PHM_PlatformCaps_ClockStretcher)) {
 246                                 for (j = 1; j < sclk_table->count; j++) {
 247                                         if (sclk_table->entries[j].clk == sclk &&
 248                                                         sclk_table->entries[j].cks_enable == 0) {
 249                                                 sclk += 5000;
 250                                                 break;
 251                                         }
 252                                 }
 253                         }
 254
 255                         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 256                                         PHM_PlatformCaps_EnableDriverEVV))
 257                                 result = atomctrl_calculate_voltage_evv_on_sclk(hwmgr,
 258                                                 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc, i, true);
 259                         else
 260                                 result = -EINVAL;
 261
 262                         if (result)
 263                                 result = atomctrl_get_voltage_evv_on_sclk(hwmgr,
 264                                                 VOLTAGE_TYPE_VDDC, sclk,vv_id, &vddc);
 265
 266                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
 267                         PP_ASSERT_WITH_CODE((vddc < 2000),
 268                                         "Invalid VDDC value, greater than 2v!", result = -EINVAL;);
 269
 270                         if (result)
 271                                 /* 1.15V is the default safe value for Fiji */
 272                                 vddc = evv_default;
 273
 274                         /* the voltage should not be zero nor equal to leakage ID */
 275                         if (vddc != 0 && vddc != vv_id) {
 276                                 data->vddc_leakage.actual_voltage
 277                                 [data->vddc_leakage.count] = vddc;
 278                                 data->vddc_leakage.leakage_id
 279                                 [data->vddc_leakage.count] = vv_id;
 280                                 data->vddc_leakage.count++;
 281                         }
 282                 }
 283         }
 284         return 0;
 285 }
 286
 287 /**
 288  * Change virtual leakage voltage to actual value.
 289  *
 290  * @param     hwmgr  the address of the powerplay hardware manager.
 291  * @param     pointer to changing voltage
 292  * @param     pointer to leakage table
 293  */
 294 static void fiji_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
 295                 uint16_t *voltage, struct fiji_leakage_voltage *leakage_table)
 296 {
 297         uint32_t index;
 298
 299         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
 300         for (index = 0; index < leakage_table->count; index++) {
 301                 /* if this voltage matches a leakage voltage ID */
 302                 /* patch with actual leakage voltage */
 303                 if (leakage_table->leakage_id[index] == *voltage) {
 304                         *voltage = leakage_table->actual_voltage[index];
 305                         break;
 306                 }
 307         }
 308
 309         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
 310                 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
 311 }
 312
 313 /**
 314 * Patch voltage lookup table by EVV leakages.
 315 *
 316 * @param     hwmgr  the address of the powerplay hardware manager.
 317 * @param     pointer to voltage lookup table
 318 * @param     pointer to leakage table
 319 * @return     always 0
 320 */
 321 static int fiji_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
 322                 phm_ppt_v1_voltage_lookup_table *lookup_table,
 323                 struct fiji_leakage_voltage *leakage_table)
 324 {
 325         uint32_t i;
 326
 327         for (i = 0; i < lookup_table->count; i++)
 328                 fiji_patch_with_vdd_leakage(hwmgr,
 329                                 &lookup_table->entries[i].us_vdd, leakage_table);
 330
 331         return 0;
 332 }
 333
 334 static int fiji_patch_clock_voltage_limits_with_vddc_leakage(
 335                 struct pp_hwmgr *hwmgr, struct fiji_leakage_voltage *leakage_table,
 336                 uint16_t *vddc)
 337 {
 338         struct phm_ppt_v1_information *table_info =
 339                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 340         fiji_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
 341         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
 342                         table_info->max_clock_voltage_on_dc.vddc;
 343         return 0;
 344 }
 345
 346 static int fiji_patch_voltage_dependency_tables_with_lookup_table(
 347                 struct pp_hwmgr *hwmgr)
 348 {
 349         uint8_t entryId;
 350         uint8_t voltageId;
 351         struct phm_ppt_v1_information *table_info =
 352                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 353
 354         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
 355                         table_info->vdd_dep_on_sclk;
 356         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
 357                         table_info->vdd_dep_on_mclk;
 358         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
 359                         table_info->mm_dep_table;
 360
 361         for (entryId = 0; entryId < sclk_table->count; ++entryId) {
 362                 voltageId = sclk_table->entries[entryId].vddInd;
 363                 sclk_table->entries[entryId].vddc =
 364                                 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
 365         }
 366
 367         for (entryId = 0; entryId < mclk_table->count; ++entryId) {
 368                 voltageId = mclk_table->entries[entryId].vddInd;
 369                 mclk_table->entries[entryId].vddc =
 370                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
 371         }
 372
 373         for (entryId = 0; entryId < mm_table->count; ++entryId) {
 374                 voltageId = mm_table->entries[entryId].vddcInd;
 375                 mm_table->entries[entryId].vddc =
 376                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
 377         }
 378
 379         return 0;
 380
 381 }
 382
 383 static int fiji_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
 384 {
 385         /* Need to determine if we need calculated voltage. */
 386         return 0;
 387 }
 388
 389 static int fiji_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
 390 {
 391         /* Need to determine if we need calculated voltage from mm table. */
 392         return 0;
 393 }
 394
 395 static int fiji_sort_lookup_table(struct pp_hwmgr *hwmgr,
 396                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
 397 {
 398         uint32_t table_size, i, j;
 399         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
 400         table_size = lookup_table->count;
 401
 402         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
 403                 "Lookup table is empty", return -EINVAL);
 404
 405         /* Sorting voltages */
 406         for (i = 0; i < table_size - 1; i++) {
 407                 for (j = i + 1; j > 0; j--) {
 408                         if (lookup_table->entries[j].us_vdd <
 409                                         lookup_table->entries[j - 1].us_vdd) {
 410                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
 411                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
 412                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
 413                         }
 414                 }
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int fiji_complete_dependency_tables(struct pp_hwmgr *hwmgr)
 421 {
 422         int result = 0;
 423         int tmp_result;
 424         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 425         struct phm_ppt_v1_information *table_info =
 426                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 427
 428         tmp_result = fiji_patch_lookup_table_with_leakage(hwmgr,
 429                         table_info->vddc_lookup_table, &(data->vddc_leakage));
 430         if (tmp_result)
 431                 result = tmp_result;
 432
 433         tmp_result = fiji_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
 434                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
 435         if (tmp_result)
 436                 result = tmp_result;
 437
 438         tmp_result = fiji_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
 439         if (tmp_result)
 440                 result = tmp_result;
 441
 442         tmp_result = fiji_calc_voltage_dependency_tables(hwmgr);
 443         if (tmp_result)
 444                 result = tmp_result;
 445
 446         tmp_result = fiji_calc_mm_voltage_dependency_table(hwmgr);
 447         if (tmp_result)
 448                 result = tmp_result;
 449
 450         tmp_result = fiji_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
 451         if(tmp_result)
 452                 result = tmp_result;
 453
 454         return result;
 455 }
 456
 457 static int fiji_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 458 {
 459         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 460         struct phm_ppt_v1_information *table_info =
 461                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 462
 463         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
 464                         table_info->vdd_dep_on_sclk;
 465         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
 466                         table_info->vdd_dep_on_mclk;
 467
 468         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
 469                 "VDD dependency on SCLK table is missing.       \
 470                 This table is mandatory", return -EINVAL);
 471         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
 472                 "VDD dependency on SCLK table has to have is missing.   \
 473                 This table is mandatory", return -EINVAL);
 474
 475         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
 476                 "VDD dependency on MCLK table is missing.       \
 477                 This table is mandatory", return -EINVAL);
 478         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
 479                 "VDD dependency on MCLK table has to have is missing.    \
 480                 This table is mandatory", return -EINVAL);
 481
 482         data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc;
 483         data->max_vddc_in_pptable =     (uint16_t)allowed_sclk_vdd_table->
 484                         entries[allowed_sclk_vdd_table->count - 1].vddc;
 485
 486         table_info->max_clock_voltage_on_ac.sclk =
 487                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
 488         table_info->max_clock_voltage_on_ac.mclk =
 489                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
 490         table_info->max_clock_voltage_on_ac.vddc =
 491                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
 492         table_info->max_clock_voltage_on_ac.vddci =
 493                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
 494
 495         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
 496                 table_info->max_clock_voltage_on_ac.sclk;
 497         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
 498                 table_info->max_clock_voltage_on_ac.mclk;
 499         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
 500                 table_info->max_clock_voltage_on_ac.vddc;
 501         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
 502                 table_info->max_clock_voltage_on_ac.vddci;
 503
 504         return 0;
 505 }
 506
 507 static uint16_t fiji_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 508 {
 509         uint32_t speedCntl = 0;
 510
 511         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 512         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
 513                         ixPCIE_LC_SPEED_CNTL);
 514         return((uint16_t)PHM_GET_FIELD(speedCntl,
 515                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 516 }
 517
 518 static int fiji_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 519 {
 520         uint32_t link_width;
 521
 522         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 523         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 524                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
 525
 526         PP_ASSERT_WITH_CODE((7 >= link_width),
 527                         "Invalid PCIe lane width!", return 0);
 528
 529         return decode_pcie_lane_width(link_width);
 530 }
 531
 532 /** Patch the Boot State to match VBIOS boot clocks and voltage.
 533 *
 534 * @param hwmgr Pointer to the hardware manager.
 535 * @param pPowerState The address of the PowerState instance being created.
 536 *
 537 */
 538 static int fiji_patch_boot_state(struct pp_hwmgr *hwmgr,
 539                 struct pp_hw_power_state *hw_ps)
 540 {
 541         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 542         struct fiji_power_state *ps = (struct fiji_power_state *)hw_ps;
 543         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
 544         uint16_t size;
 545         uint8_t frev, crev;
 546         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 547
 548         /* First retrieve the Boot clocks and VDDC from the firmware info table.
 549          * We assume here that fw_info is unchanged if this call fails.
 550          */
 551         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
 552                         hwmgr->device, index,
 553                         &size, &frev, &crev);
 554         if (!fw_info)
 555                 /* During a test, there is no firmware info table. */
 556                 return 0;
 557
 558         /* Patch the state. */
 559         data->vbios_boot_state.sclk_bootup_value =
 560                         le32_to_cpu(fw_info->ulDefaultEngineClock);
 561         data->vbios_boot_state.mclk_bootup_value =
 562                         le32_to_cpu(fw_info->ulDefaultMemoryClock);
 563         data->vbios_boot_state.mvdd_bootup_value =
 564                         le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
 565         data->vbios_boot_state.vddc_bootup_value =
 566                         le16_to_cpu(fw_info->usBootUpVDDCVoltage);
 567         data->vbios_boot_state.vddci_bootup_value =
 568                         le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
 569         data->vbios_boot_state.pcie_gen_bootup_value =
 570                         fiji_get_current_pcie_speed(hwmgr);
 571         data->vbios_boot_state.pcie_lane_bootup_value =
 572                         (uint16_t)fiji_get_current_pcie_lane_number(hwmgr);
 573
 574         /* set boot power state */
 575         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
 576         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
 577         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
 578         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
 579
 580         return 0;
 581 }
 582
 583 static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 584 {
 585         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 586         uint32_t i;
 587         struct phm_ppt_v1_information *table_info =
 588                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 589         bool stay_in_boot;
 590         int result;
 591
 592         data->dll_default_on = false;
 593         data->sram_end = SMC_RAM_END;
 594
 595         for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
 596                 data->activity_target[i] = FIJI_AT_DFLT;
 597
 598         data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
 599
 600         data->mclk_activity_target = PPFIJI_MCLK_TARGETACTIVITY_DFLT;
 601         data->mclk_dpm0_activity_target = 0xa;
 602
 603         data->sclk_dpm_key_disabled = 0;
 604         data->mclk_dpm_key_disabled = 0;
 605         data->pcie_dpm_key_disabled = 0;
 606
 607         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 608                         PHM_PlatformCaps_UnTabledHardwareInterface);
 609         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 610                         PHM_PlatformCaps_TablelessHardwareInterface);
 611
 612         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 613                         PHM_PlatformCaps_SclkDeepSleep);
 614
 615         data->gpio_debug = 0;
 616
 617         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 618                         PHM_PlatformCaps_DynamicPatchPowerState);
 619
 620         /* need to set voltage control types before EVV patching */
 621         data->voltage_control = FIJI_VOLTAGE_CONTROL_NONE;
 622         data->vddci_control = FIJI_VOLTAGE_CONTROL_NONE;
 623         data->mvdd_control = FIJI_VOLTAGE_CONTROL_NONE;
 624
 625         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
 626                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
 627                 data->voltage_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
 628
 629         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 630                         PHM_PlatformCaps_EnableMVDDControl))
 631                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
 632                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
 633                         data->mvdd_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;
 634
 635         if (data->mvdd_control == FIJI_VOLTAGE_CONTROL_NONE)
 636                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 637                         PHM_PlatformCaps_EnableMVDDControl);
 638
 639         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 640                         PHM_PlatformCaps_ControlVDDCI)) {
 641                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
 642                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
 643                         data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;
 644                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
 645                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
 646                         data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
 647         }
 648
 649         if (data->vddci_control == FIJI_VOLTAGE_CONTROL_NONE)
 650                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 651                                 PHM_PlatformCaps_ControlVDDCI);
 652
 653         if (table_info && table_info->cac_dtp_table->usClockStretchAmount)
 654                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 655                                 PHM_PlatformCaps_ClockStretcher);
 656
 657         fiji_init_dpm_defaults(hwmgr);
 658
 659         /* Get leakage voltage based on leakage ID. */
 660         fiji_get_evv_voltages(hwmgr);
 661
 662         /* Patch our voltage dependency table with actual leakage voltage
 663          * We need to perform leakage translation before it's used by other functions
 664          */
 665         fiji_complete_dependency_tables(hwmgr);
 666
 667         /* Parse pptable data read from VBIOS */
 668         fiji_set_private_data_based_on_pptable(hwmgr);
 669
 670         /* ULV Support */
 671         data->ulv.ulv_supported = true; /* ULV feature is enabled by default */
 672
 673         /* Initalize Dynamic State Adjustment Rule Settings */
 674         result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
 675
 676         if (!result) {
 677                 data->uvd_enabled = false;
 678                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 679                                 PHM_PlatformCaps_EnableSMU7ThermalManagement);
 680                 data->vddc_phase_shed_control = false;
 681         }
 682
 683         stay_in_boot = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 684                         PHM_PlatformCaps_StayInBootState);
 685
 686         if (0 == result) {
 687                 data->is_tlu_enabled = 0;
 688                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 689                                 FIJI_MAX_HARDWARE_POWERLEVELS;
 690                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
 691                 hwmgr->platform_descriptor.minimumClocksReductionPercentage  = 50;
 692
 693                 data->pcie_gen_cap = 0x30007;
 694                 data->pcie_lane_cap = 0x2f0000;
 695         } else {
 696                 /* Ignore return value in here, we are cleaning up a mess. */
 697                 tonga_hwmgr_backend_fini(hwmgr);
 698         }
 699
 700         return 0;
 701 }
 702
 703 /**
 704  * Read clock related registers.
 705  *
 706  * @param    hwmgr  the address of the powerplay hardware manager.
 707  * @return   always 0
 708  */
 709 static int fiji_read_clock_registers(struct pp_hwmgr *hwmgr)
 710 {
 711         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 712
 713         data->clock_registers.vCG_SPLL_FUNC_CNTL =
 714                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 715                                 ixCG_SPLL_FUNC_CNTL);
 716         data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
 717                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 718                                 ixCG_SPLL_FUNC_CNTL_2);
 719         data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
 720                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 721                                 ixCG_SPLL_FUNC_CNTL_3);
 722         data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
 723                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 724                                 ixCG_SPLL_FUNC_CNTL_4);
 725         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
 726                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 727                                 ixCG_SPLL_SPREAD_SPECTRUM);
 728         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
 729                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 730                                 ixCG_SPLL_SPREAD_SPECTRUM_2);
 731
 732         return 0;
 733 }
 734
 735 /**
 736  * Find out if memory is GDDR5.
 737  *
 738  * @param    hwmgr  the address of the powerplay hardware manager.
 739  * @return   always 0
 740  */
 741 static int fiji_get_memory_type(struct pp_hwmgr *hwmgr)
 742 {
 743         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 744         uint32_t temp;
 745
 746         temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
 747
 748         data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
 749                         ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
 750                          MC_SEQ_MISC0_GDDR5_SHIFT));
 751
 752         return 0;
 753 }
 754
 755 /**
 756  * Enables Dynamic Power Management by SMC
 757  *
 758  * @param    hwmgr  the address of the powerplay hardware manager.
 759  * @return   always 0
 760  */
 761 static int fiji_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
 762 {
 763         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 764                         GENERAL_PWRMGT, STATIC_PM_EN, 1);
 765
 766         return 0;
 767 }
 768
 769 /**
 770  * Initialize PowerGating States for different engines
 771  *
 772  * @param    hwmgr  the address of the powerplay hardware manager.
 773  * @return   always 0
 774  */
 775 static int fiji_init_power_gate_state(struct pp_hwmgr *hwmgr)
 776 {
 777         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 778
 779         data->uvd_power_gated = false;
 780         data->vce_power_gated = false;
 781         data->samu_power_gated = false;
 782         data->acp_power_gated = false;
 783         data->pg_acp_init = true;
 784
 785         return 0;
 786 }
 787
 788 static int fiji_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 789 {
 790         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 791         data->low_sclk_interrupt_threshold = 0;
 792
 793         return 0;
 794 }
 795
 796 static int fiji_setup_asic_task(struct pp_hwmgr *hwmgr)
 797 {
 798         int tmp_result, result = 0;
 799
 800         tmp_result = fiji_read_clock_registers(hwmgr);
 801         PP_ASSERT_WITH_CODE((0 == tmp_result),
 802                         "Failed to read clock registers!", result = tmp_result);
 803
 804         tmp_result = fiji_get_memory_type(hwmgr);
 805         PP_ASSERT_WITH_CODE((0 == tmp_result),
 806                         "Failed to get memory type!", result = tmp_result);
 807
 808         tmp_result = fiji_enable_acpi_power_management(hwmgr);
 809         PP_ASSERT_WITH_CODE((0 == tmp_result),
 810                         "Failed to enable ACPI power management!", result = tmp_result);
 811
 812         tmp_result = fiji_init_power_gate_state(hwmgr);
 813         PP_ASSERT_WITH_CODE((0 == tmp_result),
 814                         "Failed to init power gate state!", result = tmp_result);
 815
 816         tmp_result = tonga_get_mc_microcode_version(hwmgr);
 817         PP_ASSERT_WITH_CODE((0 == tmp_result),
 818                         "Failed to get MC microcode version!", result = tmp_result);
 819
 820         tmp_result = fiji_init_sclk_threshold(hwmgr);
 821         PP_ASSERT_WITH_CODE((0 == tmp_result),
 822                         "Failed to init sclk threshold!", result = tmp_result);
 823
 824         return result;
 825 }
 826
 827 /**
 828 * Checks if we want to support voltage control
 829 *
 830 * @param    hwmgr  the address of the powerplay hardware manager.
 831 */
 832 static bool fiji_voltage_control(const struct pp_hwmgr *hwmgr)
 833 {
 834         const struct fiji_hwmgr *data =
 835                         (const struct fiji_hwmgr *)(hwmgr->backend);
 836
 837         return (FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control);
 838 }
 839
 840 /**
 841 * Enable voltage control
 842 *
 843 * @param    hwmgr  the address of the powerplay hardware manager.
 844 * @return   always 0
 845 */
 846 static int fiji_enable_voltage_control(struct pp_hwmgr *hwmgr)
 847 {
 848         /* enable voltage control */
 849         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 850                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 851
 852         return 0;
 853 }
 854
 855 /**
 856 * Remove repeated voltage values and create table with unique values.
 857 *
 858 * @param    hwmgr  the address of the powerplay hardware manager.
 859 * @param    vol_table  the pointer to changing voltage table
 860 * @return    0 in success
 861 */
 862
 863 static int fiji_trim_voltage_table(struct pp_hwmgr *hwmgr,
 864                 struct pp_atomctrl_voltage_table *vol_table)
 865 {
 866         uint32_t i, j;
 867         uint16_t vvalue;
 868         bool found = false;
 869         struct pp_atomctrl_voltage_table *table;
 870
 871         PP_ASSERT_WITH_CODE((NULL != vol_table),
 872                         "Voltage Table empty.", return -EINVAL);
 873         table = kzalloc(sizeof(struct pp_atomctrl_voltage_table),
 874                         GFP_KERNEL);
 875
 876         if (NULL == table)
 877                 return -EINVAL;
 878
 879         table->mask_low = vol_table->mask_low;
 880         table->phase_delay = vol_table->phase_delay;
 881
 882         for (i = 0; i < vol_table->count; i++) {
 883                 vvalue = vol_table->entries[i].value;
 884                 found = false;
 885
 886                 for (j = 0; j < table->count; j++) {
 887                         if (vvalue == table->entries[j].value) {
 888                                 found = true;
 889                                 break;
 890                         }
 891                 }
 892
 893                 if (!found) {
 894                         table->entries[table->count].value = vvalue;
 895                         table->entries[table->count].smio_low =
 896                                         vol_table->entries[i].smio_low;
 897                         table->count++;
 898                 }
 899         }
 900
 901         memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
 902         kfree(table);
 903
 904     return 0;
 905 }
 906 static int fiji_get_svi2_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
 907                 phm_ppt_v1_clock_voltage_dependency_table *dep_table)
 908 {
 909         uint32_t i;
 910         int result;
 911         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 912         struct pp_atomctrl_voltage_table *vol_table = &(data->mvdd_voltage_table);
 913
 914         PP_ASSERT_WITH_CODE((0 != dep_table->count),
 915                         "Voltage Dependency Table empty.", return -EINVAL);
 916
 917         vol_table->mask_low = 0;
 918         vol_table->phase_delay = 0;
 919         vol_table->count = dep_table->count;
 920
 921         for (i = 0; i < dep_table->count; i++) {
 922                 vol_table->entries[i].value = dep_table->entries[i].mvdd;
 923                 vol_table->entries[i].smio_low = 0;
 924         }
 925
 926         result = fiji_trim_voltage_table(hwmgr, vol_table);
 927         PP_ASSERT_WITH_CODE((0 == result),
 928                         "Failed to trim MVDD table.", return result);
 929
 930         return 0;
 931 }
 932
 933 static int fiji_get_svi2_vddci_voltage_table(struct pp_hwmgr *hwmgr,
 934                 phm_ppt_v1_clock_voltage_dependency_table *dep_table)
 935 {
 936         uint32_t i;
 937         int result;
 938         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 939         struct pp_atomctrl_voltage_table *vol_table = &(data->vddci_voltage_table);
 940
 941         PP_ASSERT_WITH_CODE((0 != dep_table->count),
 942                         "Voltage Dependency Table empty.", return -EINVAL);
 943
 944         vol_table->mask_low = 0;
 945         vol_table->phase_delay = 0;
 946         vol_table->count = dep_table->count;
 947
 948         for (i = 0; i < dep_table->count; i++) {
 949                 vol_table->entries[i].value = dep_table->entries[i].vddci;
 950                 vol_table->entries[i].smio_low = 0;
 951         }
 952
 953         result = fiji_trim_voltage_table(hwmgr, vol_table);
 954         PP_ASSERT_WITH_CODE((0 == result),
 955                         "Failed to trim VDDCI table.", return result);
 956
 957         return 0;
 958 }
 959
 960 static int fiji_get_svi2_vdd_voltage_table(struct pp_hwmgr *hwmgr,
 961                 phm_ppt_v1_voltage_lookup_table *lookup_table)
 962 {
 963         int i = 0;
 964         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 965         struct pp_atomctrl_voltage_table *vol_table = &(data->vddc_voltage_table);
 966
 967         PP_ASSERT_WITH_CODE((0 != lookup_table->count),
 968                         "Voltage Lookup Table empty.", return -EINVAL);
 969
 970         vol_table->mask_low = 0;
 971         vol_table->phase_delay = 0;
 972
 973         vol_table->count = lookup_table->count;
 974
 975         for (i = 0; i < vol_table->count; i++) {
 976                 vol_table->entries[i].value = lookup_table->entries[i].us_vdd;
 977                 vol_table->entries[i].smio_low = 0;
 978         }
 979
 980         return 0;
 981 }
 982
 983 /* ---- Voltage Tables ----
 984  * If the voltage table would be bigger than
 985  * what will fit into the state table on
 986  * the SMC keep only the higher entries.
 987  */
 988 static void fiji_trim_voltage_table_to_fit_state_table(struct pp_hwmgr *hwmgr,
 989                 uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table)
 990 {
 991         unsigned int i, diff;
 992
 993         if (vol_table->count <= max_vol_steps)
 994                 return;
 995
 996         diff = vol_table->count - max_vol_steps;
 997
 998         for (i = 0; i < max_vol_steps; i++)
 999                 vol_table->entries[i] = vol_table->entries[i + diff];
1000
1001         vol_table->count = max_vol_steps;
1002
1003         return;
1004 }
1005
1006 /**
1007 * Create Voltage Tables.
1008 *
1009 * @param    hwmgr  the address of the powerplay hardware manager.
1010 * @return   always 0
1011 */
1012 static int fiji_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1013 {
1014         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1015         struct phm_ppt_v1_information *table_info =
1016                         (struct phm_ppt_v1_information *)hwmgr->pptable;
1017         int result;
1018
1019         if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1020                 result = atomctrl_get_voltage_table_v3(hwmgr,
1021                                 VOLTAGE_TYPE_MVDDC,     VOLTAGE_OBJ_GPIO_LUT,
1022                                 &(data->mvdd_voltage_table));
1023                 PP_ASSERT_WITH_CODE((0 == result),
1024                                 "Failed to retrieve MVDD table.",
1025                                 return result);
1026         } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1027                 result = fiji_get_svi2_mvdd_voltage_table(hwmgr,
1028                                 table_info->vdd_dep_on_mclk);
1029                 PP_ASSERT_WITH_CODE((0 == result),
1030                                 "Failed to retrieve SVI2 MVDD table from dependancy table.",
1031                                 return result;);
1032         }
1033
1034         if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1035                 result = atomctrl_get_voltage_table_v3(hwmgr,
1036                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
1037                                 &(data->vddci_voltage_table));
1038                 PP_ASSERT_WITH_CODE((0 == result),
1039                                 "Failed to retrieve VDDCI table.",
1040                                 return result);
1041         } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1042                 result = fiji_get_svi2_vddci_voltage_table(hwmgr,
1043                                 table_info->vdd_dep_on_mclk);
1044                 PP_ASSERT_WITH_CODE((0 == result),
1045                                 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
1046                                 return result);
1047         }
1048
1049         if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1050                 result = fiji_get_svi2_vdd_voltage_table(hwmgr,
1051                                 table_info->vddc_lookup_table);
1052                 PP_ASSERT_WITH_CODE((0 == result),
1053                                 "Failed to retrieve SVI2 VDDC table from lookup table.",
1054                                 return result);
1055         }
1056
1057         PP_ASSERT_WITH_CODE(
1058                         (data->vddc_voltage_table.count <= (SMU73_MAX_LEVELS_VDDC)),
1059                         "Too many voltage values for VDDC. Trimming to fit state table.",
1060                         fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1061                                         SMU73_MAX_LEVELS_VDDC, &(data->vddc_voltage_table)));
1062
1063         PP_ASSERT_WITH_CODE(
1064                         (data->vddci_voltage_table.count <= (SMU73_MAX_LEVELS_VDDCI)),
1065                         "Too many voltage values for VDDCI. Trimming to fit state table.",
1066                         fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1067                                         SMU73_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table)));
1068
1069         PP_ASSERT_WITH_CODE(
1070                         (data->mvdd_voltage_table.count <= (SMU73_MAX_LEVELS_MVDD)),
1071                         "Too many voltage values for MVDD. Trimming to fit state table.",
1072                         fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1073                                         SMU73_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table)));
1074
1075     return 0;
1076 }
1077
1078 static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
1079 {
1080         /* Program additional LP registers
1081          * that are no longer programmed by VBIOS
1082          */
1083         cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
1084                         cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
1085         cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
1086                         cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
1087         cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
1088                         cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
1089         cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
1090                         cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
1091         cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
1092                         cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
1093         cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
1094                         cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
1095         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
1096                         cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
1097
1098         return 0;
1099 }
1100
1101 /**
1102 * Programs static screed detection parameters
1103 *
1104 * @param    hwmgr  the address of the powerplay hardware manager.
1105 * @return   always 0
1106 */
1107 static int fiji_program_static_screen_threshold_parameters(
1108                 struct pp_hwmgr *hwmgr)
1109 {
1110         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1111
1112         /* Set static screen threshold unit */
1113         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1114                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
1115                         data->static_screen_threshold_unit);
1116         /* Set static screen threshold */
1117         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1118                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
1119                         data->static_screen_threshold);
1120
1121     return 0;
1122 }
1123
1124 /**
1125 * Setup display gap for glitch free memory clock switching.
1126 *
1127 * @param    hwmgr  the address of the powerplay hardware manager.
1128 * @return   always  0
1129 */
1130 static int fiji_enable_display_gap(struct pp_hwmgr *hwmgr)
1131 {
1132         uint32_t displayGap =
1133                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1134                                         ixCG_DISPLAY_GAP_CNTL);
1135
1136         displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
1137                         DISP_GAP, DISPLAY_GAP_IGNORE);
1138
1139         displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
1140                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
1141
1142         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1143                         ixCG_DISPLAY_GAP_CNTL, displayGap);
1144
1145         return 0;
1146 }
1147
1148 /**
1149 * Programs activity state transition voting clients
1150 *
1151 * @param    hwmgr  the address of the powerplay hardware manager.
1152 * @return   always  0
1153 */
1154 static int fiji_program_voting_clients(struct pp_hwmgr *hwmgr)
1155 {
1156         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1157
1158         /* Clear reset for voting clients before enabling DPM */
1159         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1160                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
1161         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1162                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
1163
1164         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1165                         ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
1166         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1167                         ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
1168         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1169                         ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
1170         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1171                         ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
1172         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1173                         ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
1174         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1175                         ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
1176         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1177                         ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
1178         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1179                         ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
1180
1181         return 0;
1182 }
1183
1184 /**
1185 * Get the location of various tables inside the FW image.
1186 *
1187 * @param    hwmgr  the address of the powerplay hardware manager.
1188 * @return   always  0
1189 */
1190 static int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
1191 {
1192         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1193         struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
1194         uint32_t tmp;
1195         int result;
1196         bool error = false;
1197
1198         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1199                         SMU7_FIRMWARE_HEADER_LOCATION +
1200                         offsetof(SMU73_Firmware_Header, DpmTable),
1201                         &tmp, data->sram_end);
1202
1203         if (0 == result)
1204                 data->dpm_table_start = tmp;
1205
1206         error |= (0 != result);
1207
1208         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1209                         SMU7_FIRMWARE_HEADER_LOCATION +
1210                         offsetof(SMU73_Firmware_Header, SoftRegisters),
1211                         &tmp, data->sram_end);
1212
1213         if (!result) {
1214                 data->soft_regs_start = tmp;
1215                 smu_data->soft_regs_start = tmp;
1216         }
1217
1218         error |= (0 != result);
1219
1220         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1221                         SMU7_FIRMWARE_HEADER_LOCATION +
1222                         offsetof(SMU73_Firmware_Header, mcRegisterTable),
1223                         &tmp, data->sram_end);
1224
1225         if (!result)
1226                 data->mc_reg_table_start = tmp;
1227
1228         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1229                         SMU7_FIRMWARE_HEADER_LOCATION +
1230                         offsetof(SMU73_Firmware_Header, FanTable),
1231                         &tmp, data->sram_end);
1232
1233         if (!result)
1234                 data->fan_table_start = tmp;
1235
1236         error |= (0 != result);
1237
1238         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1239                         SMU7_FIRMWARE_HEADER_LOCATION +
1240                         offsetof(SMU73_Firmware_Header, mcArbDramTimingTable),
1241                         &tmp, data->sram_end);
1242
1243         if (!result)
1244                 data->arb_table_start = tmp;
1245
1246         error |= (0 != result);
1247
1248         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1249                         SMU7_FIRMWARE_HEADER_LOCATION +
1250                         offsetof(SMU73_Firmware_Header, Version),
1251                         &tmp, data->sram_end);
1252
1253         if (!result)
1254                 hwmgr->microcode_version_info.SMC = tmp;
1255
1256         error |= (0 != result);
1257
1258     return error ? -1 : 0;
1259 }
1260
1261 /* Copy one arb setting to another and then switch the active set.
1262  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
1263  */
1264 static int fiji_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
1265                 uint32_t arb_src, uint32_t arb_dest)
1266 {
1267         uint32_t mc_arb_dram_timing;
1268         uint32_t mc_arb_dram_timing2;
1269         uint32_t burst_time;
1270         uint32_t mc_cg_config;
1271
1272         switch (arb_src) {
1273         case MC_CG_ARB_FREQ_F0:
1274                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1275                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1276                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1277                 break;
1278         case MC_CG_ARB_FREQ_F1:
1279                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
1280                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
1281                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
1282                 break;
1283         default:
1284                 return -EINVAL;
1285         }
1286
1287         switch (arb_dest) {
1288         case MC_CG_ARB_FREQ_F0:
1289                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
1290                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
1291                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
1292                 break;
1293         case MC_CG_ARB_FREQ_F1:
1294                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
1295                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
1296                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
1297                 break;
1298         default:
1299                 return -EINVAL;
1300         }
1301
1302     mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
1303     mc_cg_config |= 0x0000000F;
1304     cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
1305     PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
1306
1307     return 0;
1308 }
1309
1310 /**
1311 * Initial switch from ARB F0->F1
1312 *
1313 * @param    hwmgr  the address of the powerplay hardware manager.
1314 * @return   always 0
1315 * This function is to be called from the SetPowerState table.
1316 */
1317 static int fiji_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
1318 {
1319         return fiji_copy_and_switch_arb_sets(hwmgr,
1320                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
1321 }
1322
1323 static int fiji_reset_single_dpm_table(struct pp_hwmgr *hwmgr,
1324                 struct fiji_single_dpm_table *dpm_table, uint32_t count)
1325 {
1326         int i;
1327         PP_ASSERT_WITH_CODE(count <= MAX_REGULAR_DPM_NUMBER,
1328                         "Fatal error, can not set up single DPM table entries "
1329                         "to exceed max number!",);
1330
1331         dpm_table->count = count;
1332         for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
1333                 dpm_table->dpm_levels[i].enabled = false;
1334
1335         return 0;
1336 }
1337
1338 static void fiji_setup_pcie_table_entry(
1339         struct fiji_single_dpm_table *dpm_table,
1340         uint32_t index, uint32_t pcie_gen,
1341         uint32_t pcie_lanes)
1342 {
1343         dpm_table->dpm_levels[index].value = pcie_gen;
1344         dpm_table->dpm_levels[index].param1 = pcie_lanes;
1345         dpm_table->dpm_levels[index].enabled = 1;
1346 }
1347
1348 static int fiji_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
1349 {
1350         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1351         struct phm_ppt_v1_information *table_info =
1352                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1353         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1354         uint32_t i, max_entry;
1355
1356         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
1357                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
1358                         return -EINVAL);
1359
1360         if (data->use_pcie_performance_levels &&
1361                         !data->use_pcie_power_saving_levels) {
1362                 data->pcie_gen_power_saving = data->pcie_gen_performance;
1363                 data->pcie_lane_power_saving = data->pcie_lane_performance;
1364         } else if (!data->use_pcie_performance_levels &&
1365                         data->use_pcie_power_saving_levels) {
1366                 data->pcie_gen_performance = data->pcie_gen_power_saving;
1367                 data->pcie_lane_performance = data->pcie_lane_power_saving;
1368         }
1369
1370         fiji_reset_single_dpm_table(hwmgr,
1371                         &data->dpm_table.pcie_speed_table, SMU73_MAX_LEVELS_LINK);
1372
1373         if (pcie_table != NULL) {
1374                 /* max_entry is used to make sure we reserve one PCIE level
1375                  * for boot level (fix for A+A PSPP issue).
1376                  * If PCIE table from PPTable have ULV entry + 8 entries,
1377                  * then ignore the last entry.*/
1378                 max_entry = (SMU73_MAX_LEVELS_LINK < pcie_table->count) ?
1379                                 SMU73_MAX_LEVELS_LINK : pcie_table->count;
1380                 for (i = 1; i < max_entry; i++) {
1381                         fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
1382                                         get_pcie_gen_support(data->pcie_gen_cap,
1383                                                         pcie_table->entries[i].gen_speed),
1384                                         get_pcie_lane_support(data->pcie_lane_cap,
1385                                                         pcie_table->entries[i].lane_width));
1386                 }
1387                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
1388         } else {
1389                 /* Hardcode Pcie Table */
1390                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
1391                                 get_pcie_gen_support(data->pcie_gen_cap,
1392                                                 PP_Min_PCIEGen),
1393                                 get_pcie_lane_support(data->pcie_lane_cap,
1394                                                 PP_Max_PCIELane));
1395                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
1396                                 get_pcie_gen_support(data->pcie_gen_cap,
1397                                                 PP_Min_PCIEGen),
1398                                 get_pcie_lane_support(data->pcie_lane_cap,
1399                                                 PP_Max_PCIELane));
1400                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
1401                                 get_pcie_gen_support(data->pcie_gen_cap,
1402                                                 PP_Max_PCIEGen),
1403                                 get_pcie_lane_support(data->pcie_lane_cap,
1404                                                 PP_Max_PCIELane));
1405                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
1406                                 get_pcie_gen_support(data->pcie_gen_cap,
1407                                                 PP_Max_PCIEGen),
1408                                 get_pcie_lane_support(data->pcie_lane_cap,
1409                                                 PP_Max_PCIELane));
1410                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
1411                                 get_pcie_gen_support(data->pcie_gen_cap,
1412                                                 PP_Max_PCIEGen),
1413                                 get_pcie_lane_support(data->pcie_lane_cap,
1414                                                 PP_Max_PCIELane));
1415                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
1416                                 get_pcie_gen_support(data->pcie_gen_cap,
1417                                                 PP_Max_PCIEGen),
1418                                 get_pcie_lane_support(data->pcie_lane_cap,
1419                                                 PP_Max_PCIELane));
1420
1421                 data->dpm_table.pcie_speed_table.count = 6;
1422         }
1423         /* Populate last level for boot PCIE level, but do not increment count. */
1424         fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
1425                         data->dpm_table.pcie_speed_table.count,
1426                         get_pcie_gen_support(data->pcie_gen_cap,
1427                                         PP_Min_PCIEGen),
1428                         get_pcie_lane_support(data->pcie_lane_cap,
1429                                         PP_Max_PCIELane));
1430
1431         return 0;
1432 }
1433
1434 /*
1435  * This function is to initalize all DPM state tables
1436  * for SMU7 based on the dependency table.
1437  * Dynamic state patching function will then trim these
1438  * state tables to the allowed range based
1439  * on the power policy or external client requests,
1440  * such as UVD request, etc.
1441  */
1442 static int fiji_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1443 {
1444         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1445         struct phm_ppt_v1_information *table_info =
1446                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1447         uint32_t i;
1448
1449         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
1450                         table_info->vdd_dep_on_sclk;
1451         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
1452                         table_info->vdd_dep_on_mclk;
1453
1454         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
1455                         "SCLK dependency table is missing. This table is mandatory",
1456                         return -EINVAL);
1457         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
1458                         "SCLK dependency table has to have is missing. "
1459                         "This table is mandatory",
1460                         return -EINVAL);
1461
1462         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
1463                         "MCLK dependency table is missing. This table is mandatory",
1464                         return -EINVAL);
1465         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
1466                         "MCLK dependency table has to have is missing. "
1467                         "This table is mandatory",
1468                         return -EINVAL);
1469
1470         /* clear the state table to reset everything to default */
1471         fiji_reset_single_dpm_table(hwmgr,
1472                         &data->dpm_table.sclk_table, SMU73_MAX_LEVELS_GRAPHICS);
1473         fiji_reset_single_dpm_table(hwmgr,
1474                         &data->dpm_table.mclk_table, SMU73_MAX_LEVELS_MEMORY);
1475
1476         /* Initialize Sclk DPM table based on allow Sclk values */
1477         data->dpm_table.sclk_table.count = 0;
1478         for (i = 0; i < dep_sclk_table->count; i++) {
1479                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels
1480                                 [data->dpm_table.sclk_table.count - 1].value !=
1481                                                 dep_sclk_table->entries[i].clk) {
1482                         data->dpm_table.sclk_table.dpm_levels
1483                         [data->dpm_table.sclk_table.count].value =
1484                                         dep_sclk_table->entries[i].clk;
1485                         data->dpm_table.sclk_table.dpm_levels
1486                         [data->dpm_table.sclk_table.count].enabled =
1487                                         (i == 0) ? true : false;
1488                         data->dpm_table.sclk_table.count++;
1489                 }
1490         }
1491
1492         /* Initialize Mclk DPM table based on allow Mclk values */
1493         data->dpm_table.mclk_table.count = 0;
1494         for (i=0; i<dep_mclk_table->count; i++) {
1495                 if ( i==0 || data->dpm_table.mclk_table.dpm_levels
1496                                 [data->dpm_table.mclk_table.count - 1].value !=
1497                                                 dep_mclk_table->entries[i].clk) {
1498                         data->dpm_table.mclk_table.dpm_levels
1499                         [data->dpm_table.mclk_table.count].value =
1500                                         dep_mclk_table->entries[i].clk;
1501                         data->dpm_table.mclk_table.dpm_levels
1502                         [data->dpm_table.mclk_table.count].enabled =
1503                                         (i == 0) ? true : false;
1504                         data->dpm_table.mclk_table.count++;
1505                 }
1506         }
1507
1508         /* setup PCIE gen speed levels */
1509         fiji_setup_default_pcie_table(hwmgr);
1510
1511         /* save a copy of the default DPM table */
1512         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1513                         sizeof(struct fiji_dpm_table));
1514
1515         return 0;
1516 }
1517
1518 /**
1519  * @brief PhwFiji_GetVoltageOrder
1520  *  Returns index of requested voltage record in lookup(table)
1521  * @param lookup_table - lookup list to search in
1522  * @param voltage - voltage to look for
1523  * @return 0 on success
1524  */
1525 uint8_t fiji_get_voltage_index(
1526                 struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage)
1527 {
1528         uint8_t count = (uint8_t) (lookup_table->count);
1529         uint8_t i;
1530
1531         PP_ASSERT_WITH_CODE((NULL != lookup_table),
1532                         "Lookup Table empty.", return 0);
1533         PP_ASSERT_WITH_CODE((0 != count),
1534                         "Lookup Table empty.", return 0);
1535
1536         for (i = 0; i < lookup_table->count; i++) {
1537                 /* find first voltage equal or bigger than requested */
1538                 if (lookup_table->entries[i].us_vdd >= voltage)
1539                         return i;
1540         }
1541         /* voltage is bigger than max voltage in the table */
1542         return i - 1;
1543 }
1544
1545 /**
1546 * Preparation of vddc and vddgfx CAC tables for SMC.
1547 *
1548 * @param    hwmgr  the address of the hardware manager
1549 * @param    table  the SMC DPM table structure to be populated
1550 * @return   always 0
1551 */
1552 static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr,
1553                 struct SMU73_Discrete_DpmTable *table)
1554 {
1555         uint32_t count;
1556         uint8_t index;
1557         int result = 0;
1558         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1559         struct phm_ppt_v1_information *table_info =
1560                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1561         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
1562                         table_info->vddc_lookup_table;
1563         /* tables is already swapped, so in order to use the value from it,
1564          * we need to swap it back.
1565          * We are populating vddc CAC data to BapmVddc table
1566          * in split and merged mode
1567          */
1568         for( count = 0; count<lookup_table->count; count++) {
1569                 index = fiji_get_voltage_index(lookup_table,
1570                                 data->vddc_voltage_table.entries[count].value);
1571                 table->BapmVddcVidLoSidd[count] = (uint8_t) ((6200 -
1572                                 (lookup_table->entries[index].us_cac_low *
1573                                                 VOLTAGE_SCALE)) / 25);
1574                 table->BapmVddcVidHiSidd[count] = (uint8_t) ((6200 -
1575                                 (lookup_table->entries[index].us_cac_high *
1576                                                 VOLTAGE_SCALE)) / 25);
1577         }
1578
1579         return result;
1580 }
1581
1582 /**
1583 * Preparation of voltage tables for SMC.
1584 *
1585 * @param    hwmgr   the address of the hardware manager
1586 * @param    table   the SMC DPM table structure to be populated
1587 * @return   always  0
1588 */
1589
1590 int fiji_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
1591                 struct SMU73_Discrete_DpmTable *table)
1592 {
1593         int result;
1594
1595         result = fiji_populate_cac_table(hwmgr, table);
1596         PP_ASSERT_WITH_CODE(0 == result,
1597                         "can not populate CAC voltage tables to SMC",
1598                         return -EINVAL);
1599
1600         return 0;
1601 }
1602
1603 static int fiji_populate_ulv_level(struct pp_hwmgr *hwmgr,
1604                 struct SMU73_Discrete_Ulv *state)
1605 {
1606         int result = 0;
1607         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1608         struct phm_ppt_v1_information *table_info =
1609                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1610
1611         state->CcPwrDynRm = 0;
1612         state->CcPwrDynRm1 = 0;
1613
1614         state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
1615         state->VddcOffsetVid = (uint8_t)( table_info->us_ulv_voltage_offset *
1616                         VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1 );
1617
1618         state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
1619
1620         if (!result) {
1621                 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
1622                 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
1623                 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
1624         }
1625         return result;
1626 }
1627
1628 static int fiji_populate_ulv_state(struct pp_hwmgr *hwmgr,
1629                 struct SMU73_Discrete_DpmTable *table)
1630 {
1631         return fiji_populate_ulv_level(hwmgr, &table->Ulv);
1632 }
1633
1634 static int32_t fiji_get_dpm_level_enable_mask_value(
1635                 struct fiji_single_dpm_table* dpm_table)
1636 {
1637         int32_t i;
1638         int32_t mask = 0;
1639
1640         for (i = dpm_table->count; i > 0; i--) {
1641                 mask = mask << 1;
1642                 if (dpm_table->dpm_levels[i - 1].enabled)
1643                         mask |= 0x1;
1644                 else
1645                         mask &= 0xFFFFFFFE;
1646         }
1647         return mask;
1648 }
1649
1650 static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr,
1651                 struct SMU73_Discrete_DpmTable *table)
1652 {
1653         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1654         struct fiji_dpm_table *dpm_table = &data->dpm_table;
1655         int i;
1656
1657         /* Index (dpm_table->pcie_speed_table.count)
1658          * is reserved for PCIE boot level. */
1659         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1660                 table->LinkLevel[i].PcieGenSpeed  =
1661                                 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1662                 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
1663                                 dpm_table->pcie_speed_table.dpm_levels[i].param1);
1664                 table->LinkLevel[i].EnabledForActivity = 1;
1665                 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
1666                 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
1667                 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
1668         }
1669
1670         data->smc_state_table.LinkLevelCount =
1671                         (uint8_t)dpm_table->pcie_speed_table.count;
1672         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1673                         fiji_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1674
1675         return 0;
1676 }
1677
1678 /**
1679 * Calculates the SCLK dividers using the provided engine clock
1680 *
1681 * @param    hwmgr  the address of the hardware manager
1682 * @param    clock  the engine clock to use to populate the structure
1683 * @param    sclk   the SMC SCLK structure to be populated
1684 */
1685 static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr,
1686                 uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk)
1687 {
1688         const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1689         struct pp_atomctrl_clock_dividers_vi dividers;
1690         uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1691         uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1692         uint32_t spll_func_cntl_4          = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
1693         uint32_t cg_spll_spread_spectrum   = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
1694         uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
1695         uint32_t ref_clock;
1696         uint32_t ref_divider;
1697         uint32_t fbdiv;
1698         int result;
1699
1700         /* get the engine clock dividers for this clock value */
1701         result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock,  &dividers);
1702
1703         PP_ASSERT_WITH_CODE(result == 0,
1704                         "Error retrieving Engine Clock dividers from VBIOS.",
1705                         return result);
1706
1707         /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
1708         ref_clock = atomctrl_get_reference_clock(hwmgr);
1709         ref_divider = 1 + dividers.uc_pll_ref_div;
1710
1711         /* low 14 bits is fraction and high 12 bits is divider */
1712         fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
1713
1714         /* SPLL_FUNC_CNTL setup */
1715         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1716                         SPLL_REF_DIV, dividers.uc_pll_ref_div);
1717         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1718                         SPLL_PDIV_A,  dividers.uc_pll_post_div);
1719
1720         /* SPLL_FUNC_CNTL_3 setup*/
1721         spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
1722                         SPLL_FB_DIV, fbdiv);
1723
1724         /* set to use fractional accumulation*/
1725         spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
1726                         SPLL_DITHEN, 1);
1727
1728         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1729                                 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
1730                 struct pp_atomctrl_internal_ss_info ssInfo;
1731
1732                 uint32_t vco_freq = clock * dividers.uc_pll_post_div;
1733                 if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
1734                                 vco_freq, &ssInfo)) {
1735                         /*
1736                          * ss_info.speed_spectrum_percentage -- in unit of 0.01%
1737                          * ss_info.speed_spectrum_rate -- in unit of khz
1738                          *
1739                          * clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2
1740                          */
1741                         uint32_t clk_s = ref_clock * 5 /
1742                                         (ref_divider * ssInfo.speed_spectrum_rate);
1743                         /* clkv = 2 * D * fbdiv / NS */
1744                         uint32_t clk_v = 4 * ssInfo.speed_spectrum_percentage *
1745                                         fbdiv / (clk_s * 10000);
1746
1747                         cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
1748                                         CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
1749                         cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
1750                                         CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
1751                         cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2,
1752                                         CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
1753                 }
1754         }
1755
1756         sclk->SclkFrequency        = clock;
1757         sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
1758         sclk->CgSpllFuncCntl4      = spll_func_cntl_4;
1759         sclk->SpllSpreadSpectrum   = cg_spll_spread_spectrum;
1760         sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
1761         sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
1762
1763         return 0;
1764 }
1765
1766 static uint16_t fiji_find_closest_vddci(struct pp_hwmgr *hwmgr, uint16_t vddci)
1767 {
1768         uint32_t  i;
1769         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1770         struct pp_atomctrl_voltage_table *vddci_table =
1771                         &(data->vddci_voltage_table);
1772
1773         for (i = 0; i < vddci_table->count; i++) {
1774                 if (vddci_table->entries[i].value >= vddci)
1775                         return vddci_table->entries[i].value;
1776         }
1777
1778         PP_ASSERT_WITH_CODE(false,
1779                         "VDDCI is larger than max VDDCI in VDDCI Voltage Table!",
1780                         return vddci_table->entries[i].value);
1781 }
1782
1783 static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
1784                 struct phm_ppt_v1_clock_voltage_dependency_table* dep_table,
1785                 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1786 {
1787         uint32_t i;
1788         uint16_t vddci;
1789         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1790
1791         *voltage = *mvdd = 0;
1792
1793         /* clock - voltage dependency table is empty table */
1794         if (dep_table->count == 0)
1795                 return -EINVAL;
1796
1797         for (i = 0; i < dep_table->count; i++) {
1798                 /* find first sclk bigger than request */
1799                 if (dep_table->entries[i].clk >= clock) {
1800                         *voltage |= (dep_table->entries[i].vddc *
1801                                         VOLTAGE_SCALE) << VDDC_SHIFT;
1802                         if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
1803                                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1804                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1805                         else if (dep_table->entries[i].vddci)
1806                                 *voltage |= (dep_table->entries[i].vddci *
1807                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1808                         else {
1809                                 vddci = fiji_find_closest_vddci(hwmgr,
1810                                                 (dep_table->entries[i].vddc -
1811                                                                 (uint16_t)data->vddc_vddci_delta));
1812                                 *voltage |= (vddci * VOLTAGE_SCALE) <<  VDDCI_SHIFT;
1813                         }
1814
1815                         if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1816                                 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1817                                         VOLTAGE_SCALE;
1818                         else if (dep_table->entries[i].mvdd)
1819                                 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1820                                         VOLTAGE_SCALE;
1821
1822                         *voltage |= 1 << PHASES_SHIFT;
1823                         return 0;
1824                 }
1825         }
1826
1827         /* sclk is bigger than max sclk in the dependence table */
1828         *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1829
1830         if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
1831                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1832                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1833         else if (dep_table->entries[i-1].vddci) {
1834                 vddci = fiji_find_closest_vddci(hwmgr,
1835                                 (dep_table->entries[i].vddc -
1836                                                 (uint16_t)data->vddc_vddci_delta));
1837                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1838         }
1839
1840         if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1841                 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1842         else if (dep_table->entries[i].mvdd)
1843                 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1844
1845         return 0;
1846 }
1847 /**
1848 * Populates single SMC SCLK structure using the provided engine clock
1849 *
1850 * @param    hwmgr      the address of the hardware manager
1851 * @param    clock the engine clock to use to populate the structure
1852 * @param    sclk        the SMC SCLK structure to be populated
1853 */
1854
1855 static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1856                 uint32_t clock, uint16_t sclk_al_threshold,
1857                 struct SMU73_Discrete_GraphicsLevel *level)
1858 {
1859         int result;
1860         /* PP_Clocks minClocks; */
1861         uint32_t threshold, mvdd;
1862         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1863         struct phm_ppt_v1_information *table_info =
1864                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1865
1866         result = fiji_calculate_sclk_params(hwmgr, clock, level);
1867
1868         /* populate graphics levels */
1869         result = fiji_get_dependency_volt_by_clk(hwmgr,
1870                         table_info->vdd_dep_on_sclk, clock,
1871                         &level->MinVoltage, &mvdd);
1872         PP_ASSERT_WITH_CODE((0 == result),
1873                         "can not find VDDC voltage value for "
1874                         "VDDC engine clock dependency table",
1875                         return result);
1876
1877         level->SclkFrequency = clock;
1878         level->ActivityLevel = sclk_al_threshold;
1879         level->CcPwrDynRm = 0;
1880         level->CcPwrDynRm1 = 0;
1881         level->EnabledForActivity = 0;
1882         level->EnabledForThrottle = 1;
1883         level->UpHyst = 10;
1884         level->DownHyst = 0;
1885         level->VoltageDownHyst = 0;
1886         level->PowerThrottle = 0;
1887
1888         threshold = clock * data->fast_watermark_threshold / 100;
1889
1890     /*
1891      * TODO: get minimum clocks from dal configaration
1892      * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1893      */
1894     /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1895
1896     /* get level->DeepSleepDivId
1897     if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1898     {
1899         level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1900     } */
1901
1902         /* Default to slow, highest DPM level will be
1903          * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1904          */
1905         level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1906
1907         CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1908         CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
1909         CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1910         CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
1911         CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
1912         CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
1913         CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
1914         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1915         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1916
1917         return 0;
1918 }
1919 /**
1920 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1921 *
1922 * @param    hwmgr      the address of the hardware manager
1923 */
1924 static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1925 {
1926         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1927         struct fiji_dpm_table *dpm_table = &data->dpm_table;
1928         struct phm_ppt_v1_information *table_info =
1929                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1930         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1931         uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1932         int result = 0;
1933         uint32_t array = data->dpm_table_start +
1934                         offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
1935         uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
1936                         SMU73_MAX_LEVELS_GRAPHICS;
1937         struct SMU73_Discrete_GraphicsLevel *levels =
1938                         data->smc_state_table.GraphicsLevel;
1939         uint32_t i, max_entry;
1940         uint8_t hightest_pcie_level_enabled = 0,
1941                         lowest_pcie_level_enabled = 0,
1942                         mid_pcie_level_enabled = 0,
1943                         count = 0;
1944
1945         for (i = 0; i < dpm_table->sclk_table.count; i++) {
1946                 result = fiji_populate_single_graphic_level(hwmgr,
1947                                 dpm_table->sclk_table.dpm_levels[i].value,
1948                                 (uint16_t)data->activity_target[i],
1949                                 &levels[i]);
1950                 if (result)
1951                         return result;
1952
1953                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1954                 if (i > 1)
1955                         levels[i].DeepSleepDivId = 0;
1956         }
1957
1958         /* Only enable level 0 for now.*/
1959         levels[0].EnabledForActivity = 1;
1960
1961         /* set highest level watermark to high */
1962         levels[dpm_table->sclk_table.count - 1].DisplayWatermark =
1963                         PPSMC_DISPLAY_WATERMARK_HIGH;
1964
1965         data->smc_state_table.GraphicsDpmLevelCount =
1966                         (uint8_t)dpm_table->sclk_table.count;
1967         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1968                         fiji_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1969
1970         if (pcie_table != NULL) {
1971                 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1972                                 "There must be 1 or more PCIE levels defined in PPTable.",
1973                                 return -EINVAL);
1974                 max_entry = pcie_entry_cnt - 1;
1975                 for (i = 0; i < dpm_table->sclk_table.count; i++)
1976                         levels[i].pcieDpmLevel =
1977                                         (uint8_t) ((i < max_entry)? i : max_entry);
1978         } else {
1979                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1980                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1981                                                 (1 << (hightest_pcie_level_enabled + 1))) != 0 ))
1982                         hightest_pcie_level_enabled++;
1983
1984                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1985                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1986                                                 (1 << lowest_pcie_level_enabled)) == 0 ))
1987                         lowest_pcie_level_enabled++;
1988
1989                 while ((count < hightest_pcie_level_enabled) &&
1990                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1991                                                 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0 ))
1992                         count++;
1993
1994                 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1+ count) <
1995                                 hightest_pcie_level_enabled?
1996                                                 (lowest_pcie_level_enabled + 1 + count) :
1997                                                 hightest_pcie_level_enabled;
1998
1999                 /* set pcieDpmLevel to hightest_pcie_level_enabled */
2000                 for(i = 2; i < dpm_table->sclk_table.count; i++)
2001                         levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
2002
2003                 /* set pcieDpmLevel to lowest_pcie_level_enabled */
2004                 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
2005
2006                 /* set pcieDpmLevel to mid_pcie_level_enabled */
2007                 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
2008         }
2009         /* level count will send to smc once at init smc table and never change */
2010         result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
2011                         (uint32_t)array_size, data->sram_end);
2012
2013         return result;
2014 }
2015
2016 /**
2017  * MCLK Frequency Ratio
2018  * SEQ_CG_RESP  Bit[31:24] - 0x0
2019  * Bit[27:24] \96 DDR3 Frequency ratio
2020  * 0x0 <= 100MHz,       450 < 0x8 <= 500MHz
2021  * 100 < 0x1 <= 150MHz,       500 < 0x9 <= 550MHz
2022  * 150 < 0x2 <= 200MHz,       550 < 0xA <= 600MHz
2023  * 200 < 0x3 <= 250MHz,       600 < 0xB <= 650MHz
2024  * 250 < 0x4 <= 300MHz,       650 < 0xC <= 700MHz
2025  * 300 < 0x5 <= 350MHz,       700 < 0xD <= 750MHz
2026  * 350 < 0x6 <= 400MHz,       750 < 0xE <= 800MHz
2027  * 400 < 0x7 <= 450MHz,       800 < 0xF
2028  */
2029 static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock)
2030 {
2031         if (mem_clock <= 10000) return 0x0;
2032         if (mem_clock <= 15000) return 0x1;
2033         if (mem_clock <= 20000) return 0x2;
2034         if (mem_clock <= 25000) return 0x3;
2035         if (mem_clock <= 30000) return 0x4;
2036         if (mem_clock <= 35000) return 0x5;
2037         if (mem_clock <= 40000) return 0x6;
2038         if (mem_clock <= 45000) return 0x7;
2039         if (mem_clock <= 50000) return 0x8;
2040         if (mem_clock <= 55000) return 0x9;
2041         if (mem_clock <= 60000) return 0xa;
2042         if (mem_clock <= 65000) return 0xb;
2043         if (mem_clock <= 70000) return 0xc;
2044         if (mem_clock <= 75000) return 0xd;
2045         if (mem_clock <= 80000) return 0xe;
2046         /* mem_clock > 800MHz */
2047         return 0xf;
2048 }
2049
2050 /**
2051 * Populates the SMC MCLK structure using the provided memory clock
2052 *
2053 * @param    hwmgr   the address of the hardware manager
2054 * @param    clock   the memory clock to use to populate the structure
2055 * @param    sclk    the SMC SCLK structure to be populated
2056 */
2057 static int fiji_calculate_mclk_params(struct pp_hwmgr *hwmgr,
2058     uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk)
2059 {
2060         struct pp_atomctrl_memory_clock_param mem_param;
2061         int result;
2062
2063         result = atomctrl_get_memory_pll_dividers_vi(hwmgr, clock, &mem_param);
2064         PP_ASSERT_WITH_CODE((0 == result),
2065                         "Failed to get Memory PLL Dividers.",);
2066
2067         /* Save the result data to outpupt memory level structure */
2068         mclk->MclkFrequency   = clock;
2069         mclk->MclkDivider     = (uint8_t)mem_param.mpll_post_divider;
2070         mclk->FreqRange       = fiji_get_mclk_frequency_ratio(clock);
2071
2072         return result;
2073 }
2074
2075 static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
2076                 uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level)
2077 {
2078         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2079         struct phm_ppt_v1_information *table_info =
2080                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2081         int result = 0;
2082
2083         if (table_info->vdd_dep_on_mclk) {
2084                 result = fiji_get_dependency_volt_by_clk(hwmgr,
2085                                 table_info->vdd_dep_on_mclk, clock,
2086                                 &mem_level->MinVoltage, &mem_level->MinMvdd);
2087                 PP_ASSERT_WITH_CODE((0 == result),
2088                                 "can not find MinVddc voltage value from memory "
2089                                 "VDDC voltage dependency table", return result);
2090         }
2091
2092         mem_level->EnabledForThrottle = 1;
2093         mem_level->EnabledForActivity = 0;
2094         mem_level->UpHyst = 0;
2095         mem_level->DownHyst = 100;
2096         mem_level->VoltageDownHyst = 0;
2097         mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
2098         mem_level->StutterEnable = false;
2099
2100         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2101
2102         /* enable stutter mode if all the follow condition applied
2103          * PECI_GetNumberOfActiveDisplays(hwmgr->pPECI,
2104          * &(data->DisplayTiming.numExistingDisplays));
2105          */
2106         data->display_timing.num_existing_displays = 1;
2107
2108         if ((data->mclk_stutter_mode_threshold) &&
2109                 (clock <= data->mclk_stutter_mode_threshold) &&
2110                 (!data->is_uvd_enabled) &&
2111                 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
2112                                 STUTTER_ENABLE) & 0x1))
2113                 mem_level->StutterEnable = true;
2114
2115         result = fiji_calculate_mclk_params(hwmgr, clock, mem_level);
2116         if (!result) {
2117                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
2118                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
2119                 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
2120                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
2121         }
2122         return result;
2123 }
2124
2125 /**
2126 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
2127 *
2128 * @param    hwmgr      the address of the hardware manager
2129 */
2130 static int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
2131 {
2132         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2133         struct fiji_dpm_table *dpm_table = &data->dpm_table;
2134         int result;
2135         /* populate MCLK dpm table to SMU7 */
2136         uint32_t array = data->dpm_table_start +
2137                         offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
2138         uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) *
2139                         SMU73_MAX_LEVELS_MEMORY;
2140         struct SMU73_Discrete_MemoryLevel *levels =
2141                         data->smc_state_table.MemoryLevel;
2142         uint32_t i;
2143
2144         for (i = 0; i < dpm_table->mclk_table.count; i++) {
2145                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
2146                                 "can not populate memory level as memory clock is zero",
2147                                 return -EINVAL);
2148                 result = fiji_populate_single_memory_level(hwmgr,
2149                                 dpm_table->mclk_table.dpm_levels[i].value,
2150                                 &levels[i]);
2151                 if (result)
2152                         return result;
2153         }
2154
2155         /* Only enable level 0 for now. */
2156         levels[0].EnabledForActivity = 1;
2157
2158         /* in order to prevent MC activity from stutter mode to push DPM up.
2159          * the UVD change complements this by putting the MCLK in
2160          * a higher state by default such that we are not effected by
2161          * up threshold or and MCLK DPM latency.
2162          */
2163         levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
2164         CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
2165
2166         data->smc_state_table.MemoryDpmLevelCount =
2167                         (uint8_t)dpm_table->mclk_table.count;
2168         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
2169                         fiji_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2170         /* set highest level watermark to high */
2171         levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
2172                         PPSMC_DISPLAY_WATERMARK_HIGH;
2173
2174         /* level count will send to smc once at init smc table and never change */
2175         result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
2176                         (uint32_t)array_size, data->sram_end);
2177
2178         return result;
2179 }
2180
2181 /**
2182 * Populates the SMC MVDD structure using the provided memory clock.
2183 *
2184 * @param    hwmgr      the address of the hardware manager
2185 * @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
2186 * @param    voltage     the SMC VOLTAGE structure to be populated
2187 */
2188 int fiji_populate_mvdd_value(struct pp_hwmgr *hwmgr,
2189                 uint32_t mclk, SMIO_Pattern *smio_pat)
2190 {
2191         const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2192         struct phm_ppt_v1_information *table_info =
2193                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2194         uint32_t i = 0;
2195
2196         if (FIJI_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
2197                 /* find mvdd value which clock is more than request */
2198                 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
2199                         if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
2200                                 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
2201                                 break;
2202                         }
2203                 }
2204                 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
2205                                 "MVDD Voltage is outside the supported range.",
2206                                 return -EINVAL);
2207         } else
2208                 return -EINVAL;
2209
2210         return 0;
2211 }
2212
2213 static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
2214                 SMU73_Discrete_DpmTable *table)
2215 {
2216         int result = 0;
2217         const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2218         struct phm_ppt_v1_information *table_info =
2219                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2220         struct pp_atomctrl_clock_dividers_vi dividers;
2221         SMIO_Pattern vol_level;
2222         uint32_t mvdd;
2223         uint16_t us_mvdd;
2224         uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2225         uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
2226
2227         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2228
2229         if (!data->sclk_dpm_key_disabled) {
2230                 /* Get MinVoltage and Frequency from DPM0,
2231                  * already converted to SMC_UL */
2232                 table->ACPILevel.SclkFrequency =
2233                                 data->dpm_table.sclk_table.dpm_levels[0].value;
2234                 result = fiji_get_dependency_volt_by_clk(hwmgr,
2235                                 table_info->vdd_dep_on_sclk,
2236                                 table->ACPILevel.SclkFrequency,
2237                                 &table->ACPILevel.MinVoltage, &mvdd);
2238                 PP_ASSERT_WITH_CODE((0 == result),
2239                                 "Cannot find ACPI VDDC voltage value "
2240                                 "in Clock Dependency Table",);
2241         } else {
2242                 table->ACPILevel.SclkFrequency =
2243                                 data->vbios_boot_state.sclk_bootup_value;
2244                 table->ACPILevel.MinVoltage =
2245                                 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
2246         }
2247
2248         /* get the engine clock dividers for this clock value */
2249         result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
2250                         table->ACPILevel.SclkFrequency,  &dividers);
2251         PP_ASSERT_WITH_CODE(result == 0,
2252                         "Error retrieving Engine Clock dividers from VBIOS.",
2253                         return result);
2254
2255         table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
2256         table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2257         table->ACPILevel.DeepSleepDivId = 0;
2258
2259         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
2260                         SPLL_PWRON, 0);
2261         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
2262                         SPLL_RESET, 1);
2263         spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
2264                         SCLK_MUX_SEL, 4);
2265
2266         table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2267         table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2268         table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2269         table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2270         table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2271         table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2272         table->ACPILevel.CcPwrDynRm = 0;
2273         table->ACPILevel.CcPwrDynRm1 = 0;
2274
2275         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
2276         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
2277         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
2278         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
2279         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
2280         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
2281         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
2282         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
2283         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
2284         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
2285         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
2286
2287         if (!data->mclk_dpm_key_disabled) {
2288                 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
2289                 table->MemoryACPILevel.MclkFrequency =
2290                                 data->dpm_table.mclk_table.dpm_levels[0].value;
2291                 result = fiji_get_dependency_volt_by_clk(hwmgr,
2292                                 table_info->vdd_dep_on_mclk,
2293                                 table->MemoryACPILevel.MclkFrequency,
2294                                 &table->MemoryACPILevel.MinVoltage, &mvdd);
2295                 PP_ASSERT_WITH_CODE((0 == result),
2296                                 "Cannot find ACPI VDDCI voltage value "
2297                                 "in Clock Dependency Table",);
2298         } else {
2299                 table->MemoryACPILevel.MclkFrequency =
2300                                 data->vbios_boot_state.mclk_bootup_value;
2301                 table->MemoryACPILevel.MinVoltage =
2302                                 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
2303         }
2304
2305         us_mvdd = 0;
2306         if ((FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
2307                         (data->mclk_dpm_key_disabled))
2308                 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
2309         else {
2310                 if (!fiji_populate_mvdd_value(hwmgr,
2311                                 data->dpm_table.mclk_table.dpm_levels[0].value,
2312                                 &vol_level))
2313                         us_mvdd = vol_level.Voltage;
2314         }
2315
2316         table->MemoryACPILevel.MinMvdd =
2317                         PP_HOST_TO_SMC_UL(us_mvdd * VOLTAGE_SCALE);
2318
2319         table->MemoryACPILevel.EnabledForThrottle = 0;
2320         table->MemoryACPILevel.EnabledForActivity = 0;
2321         table->MemoryACPILevel.UpHyst = 0;
2322         table->MemoryACPILevel.DownHyst = 100;
2323         table->MemoryACPILevel.VoltageDownHyst = 0;
2324         table->MemoryACPILevel.ActivityLevel =
2325                         PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
2326
2327         table->MemoryACPILevel.StutterEnable = false;
2328         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
2329         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
2330
2331         return result;
2332 }
2333
2334 static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
2335                 SMU73_Discrete_DpmTable *table)
2336 {
2337         int result = -EINVAL;
2338         uint8_t count;
2339         struct pp_atomctrl_clock_dividers_vi dividers;
2340         struct phm_ppt_v1_information *table_info =
2341                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2342         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2343                         table_info->mm_dep_table;
2344         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2345
2346         table->VceLevelCount = (uint8_t)(mm_table->count);
2347         table->VceBootLevel = 0;
2348
2349         for(count = 0; count < table->VceLevelCount; count++) {
2350                 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
2351                 table->VceLevel[count].MinVoltage |=
2352                                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
2353                 table->VceLevel[count].MinVoltage |=
2354                                 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
2355                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
2356                 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2357
2358                 /*retrieve divider value for VBIOS */
2359                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2360                                 table->VceLevel[count].Frequency, &dividers);
2361                 PP_ASSERT_WITH_CODE((0 == result),
2362                                 "can not find divide id for VCE engine clock",
2363                                 return result);
2364
2365                 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2366
2367                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
2368                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
2369         }
2370         return result;
2371 }
2372
2373 static int fiji_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
2374                 SMU73_Discrete_DpmTable *table)
2375 {
2376         int result = -EINVAL;
2377         uint8_t count;
2378         struct pp_atomctrl_clock_dividers_vi dividers;
2379         struct phm_ppt_v1_information *table_info =
2380                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2381         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2382                         table_info->mm_dep_table;
2383         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2384
2385         table->AcpLevelCount = (uint8_t)(mm_table->count);
2386         table->AcpBootLevel = 0;
2387
2388         for (count = 0; count < table->AcpLevelCount; count++) {
2389                 table->AcpLevel[count].Frequency = mm_table->entries[count].aclk;
2390                 table->AcpLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2391                                 VOLTAGE_SCALE) << VDDC_SHIFT;
2392                 table->AcpLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2393                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2394                 table->AcpLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2395
2396                 /* retrieve divider value for VBIOS */
2397                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2398                                 table->AcpLevel[count].Frequency, &dividers);
2399                 PP_ASSERT_WITH_CODE((0 == result),
2400                                 "can not find divide id for engine clock", return result);
2401
2402                 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2403
2404                 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
2405                 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].MinVoltage);
2406         }
2407         return result;
2408 }
2409
2410 static int fiji_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
2411                 SMU73_Discrete_DpmTable *table)
2412 {
2413         int result = -EINVAL;
2414         uint8_t count;
2415         struct pp_atomctrl_clock_dividers_vi dividers;
2416         struct phm_ppt_v1_information *table_info =
2417                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2418         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2419                         table_info->mm_dep_table;
2420         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2421
2422         table->SamuBootLevel = 0;
2423         table->SamuLevelCount = (uint8_t)(mm_table->count);
2424
2425         for (count = 0; count < table->SamuLevelCount; count++) {
2426                 /* not sure whether we need evclk or not */
2427                 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
2428                 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2429                                 VOLTAGE_SCALE) << VDDC_SHIFT;
2430                 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2431                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2432                 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2433
2434                 /* retrieve divider value for VBIOS */
2435                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2436                                 table->SamuLevel[count].Frequency, &dividers);
2437                 PP_ASSERT_WITH_CODE((0 == result),
2438                                 "can not find divide id for samu clock", return result);
2439
2440                 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2441
2442                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
2443                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
2444         }
2445         return result;
2446 }
2447
2448 static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
2449                 int32_t eng_clock, int32_t mem_clock,
2450                 struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs)
2451 {
2452         uint32_t dram_timing;
2453         uint32_t dram_timing2;
2454         uint32_t burstTime;
2455         ULONG state, trrds, trrdl;
2456         int result;
2457
2458         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
2459                         eng_clock, mem_clock);
2460         PP_ASSERT_WITH_CODE(result == 0,
2461                         "Error calling VBIOS to set DRAM_TIMING.", return result);
2462
2463         dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
2464         dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
2465         burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
2466
2467         state = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, STATE0);
2468         trrds = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDS0);
2469         trrdl = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDL0);
2470
2471         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
2472         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
2473         arb_regs->McArbBurstTime   = (uint8_t)burstTime;
2474         arb_regs->TRRDS            = (uint8_t)trrds;
2475         arb_regs->TRRDL            = (uint8_t)trrdl;
2476
2477         return 0;
2478 }
2479
2480 static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
2481 {
2482         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2483         struct SMU73_Discrete_MCArbDramTimingTable arb_regs;
2484         uint32_t i, j;
2485         int result = 0;
2486
2487         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
2488                 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
2489                         result = fiji_populate_memory_timing_parameters(hwmgr,
2490                                         data->dpm_table.sclk_table.dpm_levels[i].value,
2491                                         data->dpm_table.mclk_table.dpm_levels[j].value,
2492                                         &arb_regs.entries[i][j]);
2493                         if (result)
2494                                 break;
2495                 }
2496         }
2497
2498         if (!result)
2499                 result = fiji_copy_bytes_to_smc(
2500                                 hwmgr->smumgr,
2501                                 data->arb_table_start,
2502                                 (uint8_t *)&arb_regs,
2503                                 sizeof(SMU73_Discrete_MCArbDramTimingTable),
2504                                 data->sram_end);
2505         return result;
2506 }
2507
2508 static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
2509                 struct SMU73_Discrete_DpmTable *table)
2510 {
2511         int result = -EINVAL;
2512         uint8_t count;
2513         struct pp_atomctrl_clock_dividers_vi dividers;
2514         struct phm_ppt_v1_information *table_info =
2515                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2516         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2517                         table_info->mm_dep_table;
2518         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2519
2520         table->UvdLevelCount = (uint8_t)(mm_table->count);
2521         table->UvdBootLevel = 0;
2522
2523         for (count = 0; count < table->UvdLevelCount; count++) {
2524                 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
2525                 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
2526                 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2527                                 VOLTAGE_SCALE) << VDDC_SHIFT;
2528                 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2529                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2530                 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2531
2532                 /* retrieve divider value for VBIOS */
2533                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2534                                 table->UvdLevel[count].VclkFrequency, &dividers);
2535                 PP_ASSERT_WITH_CODE((0 == result),
2536                                 "can not find divide id for Vclk clock", return result);
2537
2538                 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
2539
2540                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2541                                 table->UvdLevel[count].DclkFrequency, &dividers);
2542                 PP_ASSERT_WITH_CODE((0 == result),
2543                                 "can not find divide id for Dclk clock", return result);
2544
2545                 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
2546
2547                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
2548                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
2549                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
2550
2551         }
2552         return result;
2553 }
2554
2555 static int fiji_find_boot_level(struct fiji_single_dpm_table *table,
2556                 uint32_t value, uint32_t *boot_level)
2557 {
2558         int result = -EINVAL;
2559         uint32_t i;
2560
2561         for (i = 0; i < table->count; i++) {
2562                 if (value == table->dpm_levels[i].value) {
2563                         *boot_level = i;
2564                         result = 0;
2565                 }
2566         }
2567         return result;
2568 }
2569
2570 static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
2571                 struct SMU73_Discrete_DpmTable *table)
2572 {
2573         int result = 0;
2574         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2575
2576         table->GraphicsBootLevel = 0;
2577         table->MemoryBootLevel = 0;
2578
2579         /* find boot level from dpm table */
2580         result = fiji_find_boot_level(&(data->dpm_table.sclk_table),
2581                         data->vbios_boot_state.sclk_bootup_value,
2582                         (uint32_t *)&(table->GraphicsBootLevel));
2583
2584         result = fiji_find_boot_level(&(data->dpm_table.mclk_table),
2585                         data->vbios_boot_state.mclk_bootup_value,
2586                         (uint32_t *)&(table->MemoryBootLevel));
2587
2588         table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
2589                         VOLTAGE_SCALE;
2590         table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
2591                         VOLTAGE_SCALE;
2592         table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
2593                         VOLTAGE_SCALE;
2594
2595         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
2596         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
2597         CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
2598
2599         return 0;
2600 }
2601
2602 static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
2603 {
2604         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2605         struct phm_ppt_v1_information *table_info =
2606                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2607         uint8_t count, level;
2608
2609         count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
2610         for (level = 0; level < count; level++) {
2611                 if(table_info->vdd_dep_on_sclk->entries[level].clk >=
2612                                 data->vbios_boot_state.sclk_bootup_value) {
2613                         data->smc_state_table.GraphicsBootLevel = level;
2614                         break;
2615                 }
2616         }
2617
2618         count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
2619         for (level = 0; level < count; level++) {
2620                 if(table_info->vdd_dep_on_mclk->entries[level].clk >=
2621                                 data->vbios_boot_state.mclk_bootup_value) {
2622                         data->smc_state_table.MemoryBootLevel = level;
2623                         break;
2624                 }
2625         }
2626
2627         return 0;
2628 }
2629
2630 static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
2631 {
2632         uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
2633                         volt_with_cks, value;
2634         uint16_t clock_freq_u16;
2635         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2636         uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
2637                         volt_offset = 0;
2638         struct phm_ppt_v1_information *table_info =
2639                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2640         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2641                         table_info->vdd_dep_on_sclk;
2642
2643         stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
2644
2645         /* Read SMU_Eefuse to read and calculate RO and determine
2646          * if the part is SS or FF. if RO >= 1660MHz, part is FF.
2647          */
2648         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2649                         ixSMU_EFUSE_0 + (146 * 4));
2650         efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2651                         ixSMU_EFUSE_0 + (148 * 4));
2652         efuse &= 0xFF000000;
2653         efuse = efuse >> 24;
2654         efuse2 &= 0xF;
2655
2656         if (efuse2 == 1)
2657                 ro = (2300 - 1350) * efuse / 255 + 1350;
2658         else
2659                 ro = (2500 - 1000) * efuse / 255 + 1000;
2660
2661         if (ro >= 1660)
2662                 type = 0;
2663         else
2664                 type = 1;
2665
2666         /* Populate Stretch amount */
2667         data->smc_state_table.ClockStretcherAmount = stretch_amount;
2668
2669         /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
2670         for (i = 0; i < sclk_table->count; i++) {
2671                 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
2672                                 sclk_table->entries[i].cks_enable << i;
2673                 volt_without_cks = (uint32_t)((14041 *
2674                         (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
2675                         (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
2676                 volt_with_cks = (uint32_t)((13946 *
2677                         (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
2678                         (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
2679                 if (volt_without_cks >= volt_with_cks)
2680                         volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
2681                                         sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
2682                 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
2683         }
2684
2685         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2686                         STRETCH_ENABLE, 0x0);
2687         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2688                         masterReset, 0x1);
2689         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2690                         staticEnable, 0x1);
2691         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2692                         masterReset, 0x0);
2693
2694         /* Populate CKS Lookup Table */
2695         if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
2696                 stretch_amount2 = 0;
2697         else if (stretch_amount == 3 || stretch_amount == 4)
2698                 stretch_amount2 = 1;
2699         else {
2700                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2701                                 PHM_PlatformCaps_ClockStretcher);
2702                 PP_ASSERT_WITH_CODE(false,
2703                                 "Stretch Amount in PPTable not supported\n",
2704                                 return -EINVAL);
2705         }
2706
2707         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2708                         ixPWR_CKS_CNTL);
2709         value &= 0xFFC2FF87;
2710         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
2711                         fiji_clock_stretcher_lookup_table[stretch_amount2][0];
2712         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
2713                         fiji_clock_stretcher_lookup_table[stretch_amount2][1];
2714         clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
2715                         GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].
2716                         SclkFrequency) / 100);
2717         if (fiji_clock_stretcher_lookup_table[stretch_amount2][0] <
2718                         clock_freq_u16 &&
2719         fiji_clock_stretcher_lookup_table[stretch_amount2][1] >
2720                         clock_freq_u16) {
2721                 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
2722                 value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
2723                 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
2724                 value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
2725                 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
2726                 value |= (fiji_clock_stretch_amount_conversion
2727                                 [fiji_clock_stretcher_lookup_table[stretch_amount2][3]]
2728                                  [stretch_amount]) << 3;
2729         }
2730         CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
2731                         CKS_LOOKUPTableEntry[0].minFreq);
2732         CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
2733                         CKS_LOOKUPTableEntry[0].maxFreq);
2734         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
2735                         fiji_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
2736         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
2737                         (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
2738
2739         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2740                         ixPWR_CKS_CNTL, value);
2741
2742         /* Populate DDT Lookup Table */
2743         for (i = 0; i < 4; i++) {
2744                 /* Assign the minimum and maximum VID stored
2745                  * in the last row of Clock Stretcher Voltage Table.
2746                  */
2747                 data->smc_state_table.ClockStretcherDataTable.
2748                 ClockStretcherDataTableEntry[i].minVID =
2749                                 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][2];
2750                 data->smc_state_table.ClockStretcherDataTable.
2751                 ClockStretcherDataTableEntry[i].maxVID =
2752                                 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][3];
2753                 /* Loop through each SCLK and check the frequency
2754                  * to see if it lies within the frequency for clock stretcher.
2755                  */
2756                 for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
2757                         cks_setting = 0;
2758                         clock_freq = PP_SMC_TO_HOST_UL(
2759                                         data->smc_state_table.GraphicsLevel[j].SclkFrequency);
2760                         /* Check the allowed frequency against the sclk level[j].
2761                          *  Sclk's endianness has already been converted,
2762                          *  and it's in 10Khz unit,
2763                          *  as opposed to Data table, which is in Mhz unit.
2764                          */
2765                         if (clock_freq >=
2766                                         (fiji_clock_stretcher_ddt_table[type][i][0]) * 100) {
2767                                 cks_setting |= 0x2;
2768                                 if (clock_freq <
2769                                                 (fiji_clock_stretcher_ddt_table[type][i][1]) * 100)
2770                                         cks_setting |= 0x1;
2771                         }
2772                         data->smc_state_table.ClockStretcherDataTable.
2773                         ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
2774                 }
2775                 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.
2776                                 ClockStretcherDataTable.
2777                                 ClockStretcherDataTableEntry[i].setting);
2778         }
2779
2780         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
2781         value &= 0xFFFFFFFE;
2782         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
2783
2784         return 0;
2785 }
2786
2787 /**
2788 * Populates the SMC VRConfig field in DPM table.
2789 *
2790 * @param    hwmgr   the address of the hardware manager
2791 * @param    table   the SMC DPM table structure to be populated
2792 * @return   always 0
2793 */
2794 static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
2795                 struct SMU73_Discrete_DpmTable *table)
2796 {
2797         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2798         uint16_t config;
2799
2800         config = VR_MERGED_WITH_VDDC;
2801         table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
2802
2803         /* Set Vddc Voltage Controller */
2804         if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
2805                 config = VR_SVI2_PLANE_1;
2806                 table->VRConfig |= config;
2807         } else {
2808                 PP_ASSERT_WITH_CODE(false,
2809                                 "VDDC should be on SVI2 control in merged mode!",);
2810         }
2811         /* Set Vddci Voltage Controller */
2812         if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
2813                 config = VR_SVI2_PLANE_2;  /* only in merged mode */
2814                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2815         } else if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
2816                 config = VR_SMIO_PATTERN_1;
2817                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2818         } else {
2819                 config = VR_STATIC_VOLTAGE;
2820                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2821         }
2822         /* Set Mvdd Voltage Controller */
2823         if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
2824                 config = VR_SVI2_PLANE_2;
2825                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2826         } else if(FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
2827                 config = VR_SMIO_PATTERN_2;
2828                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2829         } else {
2830                 config = VR_STATIC_VOLTAGE;
2831                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2832         }
2833
2834         return 0;
2835 }
2836
2837 /**
2838 * Initializes the SMC table and uploads it
2839 *
2840 * @param    hwmgr  the address of the powerplay hardware manager.
2841 * @param    pInput  the pointer to input data (PowerState)
2842 * @return   always 0
2843 */
2844 static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
2845 {
2846         int result;
2847         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2848         struct phm_ppt_v1_information *table_info =
2849                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2850         struct SMU73_Discrete_DpmTable *table = &(data->smc_state_table);
2851         const struct fiji_ulv_parm *ulv = &(data->ulv);
2852         uint8_t i;
2853         struct pp_atomctrl_gpio_pin_assignment gpio_pin;
2854
2855         result = fiji_setup_default_dpm_tables(hwmgr);
2856         PP_ASSERT_WITH_CODE(0 == result,
2857                         "Failed to setup default DPM tables!", return result);
2858
2859         if(FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control)
2860                 fiji_populate_smc_voltage_tables(hwmgr, table);
2861
2862         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2863                         PHM_PlatformCaps_AutomaticDCTransition))
2864                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2865
2866         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2867                         PHM_PlatformCaps_StepVddc))
2868                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2869
2870         if (data->is_memory_gddr5)
2871                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2872
2873         if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2874                 result = fiji_populate_ulv_state(hwmgr, table);
2875                 PP_ASSERT_WITH_CODE(0 == result,
2876                                 "Failed to initialize ULV state!", return result);
2877                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2878                                 ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
2879         }
2880
2881         result = fiji_populate_smc_link_level(hwmgr, table);
2882         PP_ASSERT_WITH_CODE(0 == result,
2883                         "Failed to initialize Link Level!", return result);
2884
2885         result = fiji_populate_all_graphic_levels(hwmgr);
2886         PP_ASSERT_WITH_CODE(0 == result,
2887                         "Failed to initialize Graphics Level!", return result);
2888
2889         result = fiji_populate_all_memory_levels(hwmgr);
2890         PP_ASSERT_WITH_CODE(0 == result,
2891                         "Failed to initialize Memory Level!", return result);
2892
2893         result = fiji_populate_smc_acpi_level(hwmgr, table);
2894         PP_ASSERT_WITH_CODE(0 == result,
2895                         "Failed to initialize ACPI Level!", return result);
2896
2897         result = fiji_populate_smc_vce_level(hwmgr, table);
2898         PP_ASSERT_WITH_CODE(0 == result,
2899                         "Failed to initialize VCE Level!", return result);
2900
2901         result = fiji_populate_smc_acp_level(hwmgr, table);
2902         PP_ASSERT_WITH_CODE(0 == result,
2903                         "Failed to initialize ACP Level!", return result);
2904
2905         result = fiji_populate_smc_samu_level(hwmgr, table);
2906         PP_ASSERT_WITH_CODE(0 == result,
2907                         "Failed to initialize SAMU Level!", return result);
2908
2909         /* Since only the initial state is completely set up at this point
2910          * (the other states are just copies of the boot state) we only
2911          * need to populate the  ARB settings for the initial state.
2912          */
2913         result = fiji_program_memory_timing_parameters(hwmgr);
2914         PP_ASSERT_WITH_CODE(0 == result,
2915                         "Failed to Write ARB settings for the initial state.", return result);
2916
2917         result = fiji_populate_smc_uvd_level(hwmgr, table);
2918         PP_ASSERT_WITH_CODE(0 == result,
2919                         "Failed to initialize UVD Level!", return result);
2920
2921         result = fiji_populate_smc_boot_level(hwmgr, table);
2922         PP_ASSERT_WITH_CODE(0 == result,
2923                         "Failed to initialize Boot Level!", return result);
2924
2925         result = fiji_populate_smc_initailial_state(hwmgr);
2926         PP_ASSERT_WITH_CODE(0 == result,
2927                         "Failed to initialize Boot State!", return result);
2928
2929         result = fiji_populate_bapm_parameters_in_dpm_table(hwmgr);
2930         PP_ASSERT_WITH_CODE(0 == result,
2931                         "Failed to populate BAPM Parameters!", return result);
2932
2933         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2934                         PHM_PlatformCaps_ClockStretcher)) {
2935                 result = fiji_populate_clock_stretcher_data_table(hwmgr);
2936                 PP_ASSERT_WITH_CODE(0 == result,
2937                                 "Failed to populate Clock Stretcher Data Table!",
2938                                 return result);
2939         }
2940
2941         table->GraphicsVoltageChangeEnable  = 1;
2942         table->GraphicsThermThrottleEnable  = 1;
2943         table->GraphicsInterval = 1;
2944         table->VoltageInterval  = 1;
2945         table->ThermalInterval  = 1;
2946         table->TemperatureLimitHigh =
2947                         table_info->cac_dtp_table->usTargetOperatingTemp *
2948                         FIJI_Q88_FORMAT_CONVERSION_UNIT;
2949         table->TemperatureLimitLow  =
2950                         (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2951                         FIJI_Q88_FORMAT_CONVERSION_UNIT;
2952         table->MemoryVoltageChangeEnable = 1;
2953         table->MemoryInterval = 1;
2954         table->VoltageResponseTime = 0;
2955         table->PhaseResponseTime = 0;
2956         table->MemoryThermThrottleEnable = 1;
2957         table->PCIeBootLinkLevel = 0;      /* 0:Gen1 1:Gen2 2:Gen3*/
2958         table->PCIeGenInterval = 1;
2959
2960         result = fiji_populate_vr_config(hwmgr, table);
2961         PP_ASSERT_WITH_CODE(0 == result,
2962                         "Failed to populate VRConfig setting!", return result);
2963
2964         table->ThermGpio = 17;
2965         table->SclkStepSize = 0x4000;
2966
2967         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2968                 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2969                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2970                                 PHM_PlatformCaps_RegulatorHot);
2971         } else {
2972                 table->VRHotGpio = FIJI_UNUSED_GPIO_PIN;
2973                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2974                                 PHM_PlatformCaps_RegulatorHot);
2975         }
2976
2977         if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2978                         &gpio_pin)) {
2979                 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2980                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2981                                 PHM_PlatformCaps_AutomaticDCTransition);
2982         } else {
2983                 table->AcDcGpio = FIJI_UNUSED_GPIO_PIN;
2984                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2985                                 PHM_PlatformCaps_AutomaticDCTransition);
2986         }
2987
2988         /* Thermal Output GPIO */
2989         if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2990                         &gpio_pin)) {
2991                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2992                                 PHM_PlatformCaps_ThermalOutGPIO);
2993
2994                 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2995
2996                 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2997                  * since VBIOS will program this register to set 'inactive state',
2998                  * driver can then determine 'active state' from this and
2999                  * program SMU with correct polarity
3000                  */
3001                 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
3002                                 (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
3003                 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
3004
3005                 /* if required, combine VRHot/PCC with thermal out GPIO */
3006                 if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3007                                 PHM_PlatformCaps_RegulatorHot) &&
3008                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3009                                         PHM_PlatformCaps_CombinePCCWithThermalSignal))
3010                         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
3011         } else {
3012                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3013                                 PHM_PlatformCaps_ThermalOutGPIO);
3014                 table->ThermOutGpio = 17;
3015                 table->ThermOutPolarity = 1;
3016                 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
3017         }
3018
3019         for (i = 0; i < SMU73_MAX_ENTRIES_SMIO; i++)
3020                 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
3021
3022         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
3023         CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
3024         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
3025         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
3026         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
3027         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
3028         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
3029         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
3030         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
3031
3032         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
3033         result = fiji_copy_bytes_to_smc(hwmgr->smumgr,
3034                         data->dpm_table_start +
3035                         offsetof(SMU73_Discrete_DpmTable, SystemFlags),
3036                         (uint8_t *)&(table->SystemFlags),
3037                         sizeof(SMU73_Discrete_DpmTable) - 3 * sizeof(SMU73_PIDController),
3038                         data->sram_end);
3039         PP_ASSERT_WITH_CODE(0 == result,
3040                         "Failed to upload dpm data to SMC memory!", return result);
3041
3042         return 0;
3043 }
3044
3045 /**
3046 * Initialize the ARB DRAM timing table's index field.
3047 *
3048 * @param    hwmgr  the address of the powerplay hardware manager.
3049 * @return   always 0
3050 */
3051 static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr)
3052 {
3053         const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3054         uint32_t tmp;
3055         int result;
3056
3057         /* This is a read-modify-write on the first byte of the ARB table.
3058          * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
3059          * is the field 'current'.
3060          * This solution is ugly, but we never write the whole table only
3061          * individual fields in it.
3062          * In reality this field should not be in that structure
3063          * but in a soft register.
3064          */
3065         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
3066                         data->arb_table_start, &tmp, data->sram_end);
3067
3068         if (result)
3069                 return result;
3070
3071         tmp &= 0x00FFFFFF;
3072         tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
3073
3074         return fiji_write_smc_sram_dword(hwmgr->smumgr,
3075                         data->arb_table_start,  tmp, data->sram_end);
3076 }
3077
3078 static int fiji_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
3079 {
3080         if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3081                         PHM_PlatformCaps_RegulatorHot))
3082                 return smum_send_msg_to_smc(hwmgr->smumgr,
3083                                 PPSMC_MSG_EnableVRHotGPIOInterrupt);
3084
3085         return 0;
3086 }
3087
3088 static int fiji_enable_sclk_control(struct pp_hwmgr *hwmgr)
3089 {
3090         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
3091                         SCLK_PWRMGT_OFF, 0);
3092         return 0;
3093 }
3094
3095 static int fiji_enable_ulv(struct pp_hwmgr *hwmgr)
3096 {
3097         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3098         struct fiji_ulv_parm *ulv = &(data->ulv);
3099
3100         if (ulv->ulv_supported)
3101                 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
3102
3103         return 0;
3104 }
3105
3106 static int fiji_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
3107 {
3108         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3109                         PHM_PlatformCaps_SclkDeepSleep)) {
3110                 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
3111                         PP_ASSERT_WITH_CODE(false,
3112                                         "Attempt to enable Master Deep Sleep switch failed!",
3113                                         return -1);
3114         } else {
3115                 if (smum_send_msg_to_smc(hwmgr->smumgr,
3116                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
3117                         PP_ASSERT_WITH_CODE(false,
3118                                         "Attempt to disable Master Deep Sleep switch failed!",
3119                                         return -1);
3120                 }
3121         }
3122
3123         return 0;
3124 }
3125
3126 static int fiji_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3127 {
3128         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3129         uint32_t   val, val0, val2;
3130         uint32_t   i, cpl_cntl, cpl_threshold, mc_threshold;
3131
3132         /* enable SCLK dpm */
3133         if(!data->sclk_dpm_key_disabled)
3134                 PP_ASSERT_WITH_CODE(
3135             (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
3136             "Failed to enable SCLK DPM during DPM Start Function!",
3137             return -1);
3138
3139         /* enable MCLK dpm */
3140         if(0 == data->mclk_dpm_key_disabled) {
3141                 cpl_threshold = 0;
3142                 mc_threshold = 0;
3143
3144                 /* Read per MCD tile (0 - 7) */
3145                 for (i = 0; i < 8; i++) {
3146                         PHM_WRITE_FIELD(hwmgr->device, MC_CONFIG_MCD, MC_RD_ENABLE, i);
3147                         val = cgs_read_register(hwmgr->device, mmMC_SEQ_RESERVE_0_S) & 0xf0000000;
3148                         if (0xf0000000 != val) {
3149                                 /* count number of MCQ that has channel(s) enabled */
3150                                 cpl_threshold++;
3151                                 /* only harvest 3 or full 4 supported */
3152                                 mc_threshold = val ? 3 : 4;
3153                         }
3154                 }
3155                 PP_ASSERT_WITH_CODE(0 != cpl_threshold,
3156                                 "Number of MCQ is zero!", return -EINVAL;);
3157
3158                 mc_threshold = ((mc_threshold & LCAC_MC0_CNTL__MC0_THRESHOLD_MASK) <<
3159                                 LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT) |
3160                                                 LCAC_MC0_CNTL__MC0_ENABLE_MASK;
3161                 cpl_cntl = ((cpl_threshold & LCAC_CPL_CNTL__CPL_THRESHOLD_MASK) <<
3162                                 LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT) |
3163                                                 LCAC_CPL_CNTL__CPL_ENABLE_MASK;
3164                 cpl_cntl = (cpl_cntl | (8 << LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT));
3165                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3166                                 ixLCAC_MC0_CNTL, mc_threshold);
3167                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3168                                 ixLCAC_MC1_CNTL, mc_threshold);
3169                 if (8 == cpl_threshold) {
3170                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3171                                         ixLCAC_MC2_CNTL, mc_threshold);
3172                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3173                                         ixLCAC_MC3_CNTL, mc_threshold);
3174                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3175                                         ixLCAC_MC4_CNTL, mc_threshold);
3176                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3177                                         ixLCAC_MC5_CNTL, mc_threshold);
3178                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3179                                         ixLCAC_MC6_CNTL, mc_threshold);
3180                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3181                                         ixLCAC_MC7_CNTL, mc_threshold);
3182                 }
3183                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3184                                 ixLCAC_CPL_CNTL, cpl_cntl);
3185
3186                 udelay(5);
3187
3188                 mc_threshold = mc_threshold |
3189                                 (1 << LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT);
3190                 cpl_cntl = cpl_cntl | (1 << LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT);
3191                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3192                                 ixLCAC_MC0_CNTL, mc_threshold);
3193                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3194                                 ixLCAC_MC1_CNTL, mc_threshold);
3195                 if (8 == cpl_threshold) {
3196                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3197                                         ixLCAC_MC2_CNTL, mc_threshold);
3198                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3199                                         ixLCAC_MC3_CNTL, mc_threshold);
3200                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3201                                         ixLCAC_MC4_CNTL, mc_threshold);
3202                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3203                                         ixLCAC_MC5_CNTL, mc_threshold);
3204                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3205                                         ixLCAC_MC6_CNTL, mc_threshold);
3206                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3207                                         ixLCAC_MC7_CNTL, mc_threshold);
3208                 }
3209                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3210                                 ixLCAC_CPL_CNTL, cpl_cntl);
3211
3212                 /* Program CAC_EN per MCD (0-7) Tile */
3213                 val0 = val = cgs_read_register(hwmgr->device, mmMC_CONFIG_MCD);
3214                 val &= ~(MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK |
3215                                 MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK |
3216                                 MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK |
3217                                 MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK |
3218                                 MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK |
3219                                 MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK |
3220                                 MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK |
3221                                 MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK |
3222                                 MC_CONFIG_MCD__MC_RD_ENABLE_MASK);
3223
3224                 for (i = 0; i < 8; i++) {
3225                         /* Enable MCD i Tile read & write */
3226                         val2  = (val | (i << MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT) |
3227                                         (1 << i));
3228                         cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val2);
3229                         /* Enbale CAC_ON MCD i Tile */
3230                         val2 = cgs_read_register(hwmgr->device, mmMC_SEQ_CNTL);
3231                         val2 |= MC_SEQ_CNTL__CAC_EN_MASK;
3232                         cgs_write_register(hwmgr->device, mmMC_SEQ_CNTL, val2);
3233                 }
3234                 /* Set MC_CONFIG_MCD back to its default setting val0 */
3235                 cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val0);
3236
3237                 PP_ASSERT_WITH_CODE(
3238                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3239                                                 PPSMC_MSG_MCLKDPM_Enable)),
3240                                 "Failed to enable MCLK DPM during DPM Start Function!",
3241                                 return -1);
3242         }
3243         return 0;
3244 }
3245
3246 static int fiji_start_dpm(struct pp_hwmgr *hwmgr)
3247 {
3248         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3249
3250         /*enable general power management */
3251         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3252                         GLOBAL_PWRMGT_EN, 1);
3253         /* enable sclk deep sleep */
3254         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
3255                         DYNAMIC_PM_EN, 1);
3256         /* prepare for PCIE DPM */
3257         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3258                         data->soft_regs_start + offsetof(SMU73_SoftRegisters,
3259                                         VoltageChangeTimeout), 0x1000);
3260         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
3261                         SWRST_COMMAND_1, RESETLC, 0x0);
3262
3263         PP_ASSERT_WITH_CODE(
3264                         (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3265                                         PPSMC_MSG_Voltage_Cntl_Enable)),
3266                         "Failed to enable voltage DPM during DPM Start Function!",
3267                         return -1);
3268
3269         if (fiji_enable_sclk_mclk_dpm(hwmgr)) {
3270                 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
3271                 return -1;
3272         }
3273
3274         /* enable PCIE dpm */
3275         if(!data->pcie_dpm_key_disabled) {
3276                 PP_ASSERT_WITH_CODE(
3277                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3278                                                 PPSMC_MSG_PCIeDPM_Enable)),
3279                                 "Failed to enable pcie DPM during DPM Start Function!",
3280                                 return -1);
3281         }
3282
3283     return 0;
3284 }
3285
3286 static void fiji_set_dpm_event_sources(struct pp_hwmgr *hwmgr,
3287                 uint32_t sources)
3288 {
3289         bool protection;
3290         enum DPM_EVENT_SRC src;
3291
3292         switch (sources) {
3293         default:
3294                 printk(KERN_ERR "Unknown throttling event sources.");
3295                 /* fall through */
3296         case 0:
3297                 protection = false;
3298                 /* src is unused */
3299                 break;
3300         case (1 << PHM_AutoThrottleSource_Thermal):
3301                 protection = true;
3302                 src = DPM_EVENT_SRC_DIGITAL;
3303                 break;
3304         case (1 << PHM_AutoThrottleSource_External):
3305                 protection = true;
3306                 src = DPM_EVENT_SRC_EXTERNAL;
3307                 break;
3308         case (1 << PHM_AutoThrottleSource_External) |
3309                         (1 << PHM_AutoThrottleSource_Thermal):
3310                 protection = true;
3311                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
3312                 break;
3313         }
3314         /* Order matters - don't enable thermal protection for the wrong source. */
3315         if (protection) {
3316                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
3317                                 DPM_EVENT_SRC, src);
3318                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3319                                 THERMAL_PROTECTION_DIS,
3320                                 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3321                                                 PHM_PlatformCaps_ThermalController));
3322         } else
3323                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3324                                 THERMAL_PROTECTION_DIS, 1);
3325 }
3326
3327 static int fiji_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
3328                 PHM_AutoThrottleSource source)
3329 {
3330         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3331
3332         if (!(data->active_auto_throttle_sources & (1 << source))) {
3333                 data->active_auto_throttle_sources |= 1 << source;
3334                 fiji_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
3335         }
3336         return 0;
3337 }
3338
3339 static int fiji_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
3340 {
3341     return fiji_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
3342 }
3343
3344 static int fiji_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
3345 {
3346         int tmp_result, result = 0;
3347
3348         tmp_result = (!fiji_is_dpm_running(hwmgr))? 0 : -1;
3349         PP_ASSERT_WITH_CODE(result == 0,
3350                         "DPM is already running right now, no need to enable DPM!",
3351                         return 0);
3352
3353         if (fiji_voltage_control(hwmgr)) {
3354                 tmp_result = fiji_enable_voltage_control(hwmgr);
3355                 PP_ASSERT_WITH_CODE(tmp_result == 0,
3356                                 "Failed to enable voltage control!",
3357                                 result = tmp_result);
3358         }
3359
3360         if (fiji_voltage_control(hwmgr)) {
3361                 tmp_result = fiji_construct_voltage_tables(hwmgr);
3362                 PP_ASSERT_WITH_CODE((0 == tmp_result),
3363                                 "Failed to contruct voltage tables!",
3364                                 result = tmp_result);
3365         }
3366
3367         tmp_result = fiji_initialize_mc_reg_table(hwmgr);
3368         PP_ASSERT_WITH_CODE((0 == tmp_result),
3369                         "Failed to initialize MC reg table!", result = tmp_result);
3370
3371         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3372                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
3373                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3374                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
3375
3376         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3377                         PHM_PlatformCaps_ThermalController))
3378                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3379                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
3380
3381         tmp_result = fiji_program_static_screen_threshold_parameters(hwmgr);
3382         PP_ASSERT_WITH_CODE((0 == tmp_result),
3383                         "Failed to program static screen threshold parameters!",
3384                         result = tmp_result);
3385
3386         tmp_result = fiji_enable_display_gap(hwmgr);
3387         PP_ASSERT_WITH_CODE((0 == tmp_result),
3388                         "Failed to enable display gap!", result = tmp_result);
3389
3390         tmp_result = fiji_program_voting_clients(hwmgr);
3391         PP_ASSERT_WITH_CODE((0 == tmp_result),
3392                         "Failed to program voting clients!", result = tmp_result);
3393
3394         tmp_result = fiji_process_firmware_header(hwmgr);
3395         PP_ASSERT_WITH_CODE((0 == tmp_result),
3396                         "Failed to process firmware header!", result = tmp_result);
3397
3398         tmp_result = fiji_initial_switch_from_arbf0_to_f1(hwmgr);
3399         PP_ASSERT_WITH_CODE((0 == tmp_result),
3400                         "Failed to initialize switch from ArbF0 to F1!",
3401                         result = tmp_result);
3402
3403         tmp_result = fiji_init_smc_table(hwmgr);
3404         PP_ASSERT_WITH_CODE((0 == tmp_result),
3405                         "Failed to initialize SMC table!", result = tmp_result);
3406
3407         tmp_result = fiji_init_arb_table_index(hwmgr);
3408         PP_ASSERT_WITH_CODE((0 == tmp_result),
3409                         "Failed to initialize ARB table index!", result = tmp_result);
3410
3411         tmp_result = fiji_populate_pm_fuses(hwmgr);
3412         PP_ASSERT_WITH_CODE((0 == tmp_result),
3413                         "Failed to populate PM fuses!", result = tmp_result);
3414
3415         tmp_result = fiji_enable_vrhot_gpio_interrupt(hwmgr);
3416         PP_ASSERT_WITH_CODE((0 == tmp_result),
3417                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
3418
3419         tmp_result = fiji_enable_sclk_control(hwmgr);
3420         PP_ASSERT_WITH_CODE((0 == tmp_result),
3421                         "Failed to enable SCLK control!", result = tmp_result);
3422
3423         tmp_result = fiji_enable_ulv(hwmgr);
3424         PP_ASSERT_WITH_CODE((0 == tmp_result),
3425                         "Failed to enable ULV!", result = tmp_result);
3426
3427         tmp_result = fiji_enable_deep_sleep_master_switch(hwmgr);
3428         PP_ASSERT_WITH_CODE((0 == tmp_result),
3429                         "Failed to enable deep sleep master switch!", result = tmp_result);
3430
3431         tmp_result = fiji_start_dpm(hwmgr);
3432         PP_ASSERT_WITH_CODE((0 == tmp_result),
3433                         "Failed to start DPM!", result = tmp_result);
3434
3435         tmp_result = fiji_enable_smc_cac(hwmgr);
3436         PP_ASSERT_WITH_CODE((0 == tmp_result),
3437                         "Failed to enable SMC CAC!", result = tmp_result);
3438
3439         tmp_result = fiji_enable_power_containment(hwmgr);
3440         PP_ASSERT_WITH_CODE((0 == tmp_result),
3441                         "Failed to enable power containment!", result = tmp_result);
3442
3443         tmp_result = fiji_power_control_set_level(hwmgr);
3444         PP_ASSERT_WITH_CODE((0 == tmp_result),
3445                         "Failed to power control set level!", result = tmp_result);
3446
3447         tmp_result = fiji_enable_thermal_auto_throttle(hwmgr);
3448         PP_ASSERT_WITH_CODE((0 == tmp_result),
3449                         "Failed to enable thermal auto throttle!", result = tmp_result);
3450
3451         return result;
3452 }
3453
3454 static int fiji_force_dpm_highest(struct pp_hwmgr *hwmgr)
3455 {
3456         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3457         uint32_t level, tmp;
3458
3459         if (!data->sclk_dpm_key_disabled) {
3460                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3461                         level = 0;
3462                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3463                         while (tmp >>= 1)
3464                                 level++;
3465                         if (level)
3466                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3467                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3468                                                 (1 << level));
3469                 }
3470         }
3471
3472         if (!data->mclk_dpm_key_disabled) {
3473                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3474                         level = 0;
3475                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3476                         while (tmp >>= 1)
3477                                 level++;
3478                         if (level)
3479                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3480                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3481                                                 (1 << level));
3482                 }
3483         }
3484
3485         if (!data->pcie_dpm_key_disabled) {
3486                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3487                         level = 0;
3488                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3489                         while (tmp >>= 1)
3490                                 level++;
3491                         if (level)
3492                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3493                                                 PPSMC_MSG_PCIeDPM_ForceLevel,
3494                                                 (1 << level));
3495                 }
3496         }
3497         return 0;
3498 }
3499
3500 static void fiji_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
3501 {
3502         struct phm_ppt_v1_information *table_info =
3503                         (struct phm_ppt_v1_information *)hwmgr->pptable;
3504         struct phm_clock_voltage_dependency_table *table =
3505                                 table_info->vddc_dep_on_dal_pwrl;
3506         struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
3507         enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
3508         uint32_t req_vddc = 0, req_volt, i;
3509
3510         if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW &&
3511                         dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE))
3512                 return;
3513
3514         for (i= 0; i < table->count; i++) {
3515                 if (dal_power_level == table->entries[i].clk) {
3516                         req_vddc = table->entries[i].v;
3517                         break;
3518                 }
3519         }
3520
3521         vddc_table = table_info->vdd_dep_on_sclk;
3522         for (i= 0; i < vddc_table->count; i++) {
3523                 if (req_vddc <= vddc_table->entries[i].vddc) {
3524                         req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE)
3525                                         << VDDC_SHIFT;
3526                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3527                                         PPSMC_MSG_VddC_Request, req_volt);
3528                         return;
3529                 }
3530         }
3531         printk(KERN_ERR "DAL requested level can not"
3532                         " found a available voltage in VDDC DPM Table \n");
3533 }
3534
3535 static int fiji_upload_dpmlevel_enable_mask(struct pp_hwmgr *hwmgr)
3536 {
3537         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3538
3539         fiji_apply_dal_min_voltage_request(hwmgr);
3540
3541         if (!data->sclk_dpm_key_disabled) {
3542                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3543                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3544                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
3545                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3546         }
3547         return 0;
3548 }
3549
3550 static int fiji_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3551 {
3552         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3553
3554         if (!fiji_is_dpm_running(hwmgr))
3555                 return -EINVAL;
3556
3557         if (!data->pcie_dpm_key_disabled) {
3558                 smum_send_msg_to_smc(hwmgr->smumgr,
3559                                 PPSMC_MSG_PCIeDPM_UnForceLevel);
3560         }
3561
3562         return fiji_upload_dpmlevel_enable_mask(hwmgr);
3563 }
3564
3565 static uint32_t fiji_get_lowest_enabled_level(
3566                 struct pp_hwmgr *hwmgr, uint32_t mask)
3567 {
3568         uint32_t level = 0;
3569
3570         while(0 == (mask & (1 << level)))
3571                 level++;
3572
3573         return level;
3574 }
3575
3576 static int fiji_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3577 {
3578         struct fiji_hwmgr *data =
3579                         (struct fiji_hwmgr *)(hwmgr->backend);
3580         uint32_t level;
3581
3582         if (!data->sclk_dpm_key_disabled)
3583                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3584                         level = fiji_get_lowest_enabled_level(hwmgr,
3585                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3586                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3587                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
3588                                                             (1 << level));
3589
3590         }
3591
3592         if (!data->mclk_dpm_key_disabled) {
3593                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3594                         level = fiji_get_lowest_enabled_level(hwmgr,
3595                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3596                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3597                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
3598                                                             (1 << level));
3599                 }
3600         }
3601
3602         if (!data->pcie_dpm_key_disabled) {
3603                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3604                         level = fiji_get_lowest_enabled_level(hwmgr,
3605                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3606                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3607                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
3608                                                             (1 << level));
3609                 }
3610         }
3611
3612         return 0;
3613
3614 }
3615 static int fiji_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
3616                                 enum amd_dpm_forced_level level)
3617 {
3618         int ret = 0;
3619
3620         switch (level) {
3621         case AMD_DPM_FORCED_LEVEL_HIGH:
3622                 ret = fiji_force_dpm_highest(hwmgr);
3623                 if (ret)
3624                         return ret;
3625                 break;
3626         case AMD_DPM_FORCED_LEVEL_LOW:
3627                 ret = fiji_force_dpm_lowest(hwmgr);
3628                 if (ret)
3629                         return ret;
3630                 break;
3631         case AMD_DPM_FORCED_LEVEL_AUTO:
3632                 ret = fiji_unforce_dpm_levels(hwmgr);
3633                 if (ret)
3634                         return ret;
3635                 break;
3636         default:
3637                 break;
3638         }
3639
3640         hwmgr->dpm_level = level;
3641
3642         return ret;
3643 }
3644
3645 static int fiji_get_power_state_size(struct pp_hwmgr *hwmgr)
3646 {
3647         return sizeof(struct fiji_power_state);
3648 }
3649
3650 static int fiji_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3651                 void *state, struct pp_power_state *power_state,
3652                 void *pp_table, uint32_t classification_flag)
3653 {
3654         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3655         struct fiji_power_state  *fiji_power_state =
3656                         (struct fiji_power_state *)(&(power_state->hardware));
3657         struct fiji_performance_level *performance_level;
3658         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3659         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3660                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3661         ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
3662                         (ATOM_Tonga_SCLK_Dependency_Table *)
3663                         (((unsigned long)powerplay_table) +
3664                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3665         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3666                         (ATOM_Tonga_MCLK_Dependency_Table *)
3667                         (((unsigned long)powerplay_table) +
3668                                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3669
3670         /* The following fields are not initialized here: id orderedList allStatesList */
3671         power_state->classification.ui_label =
3672                         (le16_to_cpu(state_entry->usClassification) &
3673                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3674                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3675         power_state->classification.flags = classification_flag;
3676         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3677
3678         power_state->classification.temporary_state = false;
3679         power_state->classification.to_be_deleted = false;
3680
3681         power_state->validation.disallowOnDC =
3682                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3683                                         ATOM_Tonga_DISALLOW_ON_DC));
3684
3685         power_state->pcie.lanes = 0;
3686
3687         power_state->display.disableFrameModulation = false;
3688         power_state->display.limitRefreshrate = false;
3689         power_state->display.enableVariBright =
3690                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3691                                         ATOM_Tonga_ENABLE_VARIBRIGHT));
3692
3693         power_state->validation.supportedPowerLevels = 0;
3694         power_state->uvd_clocks.VCLK = 0;
3695         power_state->uvd_clocks.DCLK = 0;
3696         power_state->temperatures.min = 0;
3697         power_state->temperatures.max = 0;
3698
3699         performance_level = &(fiji_power_state->performance_levels
3700                         [fiji_power_state->performance_level_count++]);
3701
3702         PP_ASSERT_WITH_CODE(
3703                         (fiji_power_state->performance_level_count < SMU73_MAX_LEVELS_GRAPHICS),
3704                         "Performance levels exceeds SMC limit!",
3705                         return -1);
3706
3707         PP_ASSERT_WITH_CODE(
3708                         (fiji_power_state->performance_level_count <=
3709                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3710                         "Performance levels exceeds Driver limit!",
3711                         return -1);
3712
3713         /* Performance levels are arranged from low to high. */
3714         performance_level->memory_clock = mclk_dep_table->entries
3715                         [state_entry->ucMemoryClockIndexLow].ulMclk;
3716         performance_level->engine_clock = sclk_dep_table->entries
3717                         [state_entry->ucEngineClockIndexLow].ulSclk;
3718         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3719                         state_entry->ucPCIEGenLow);
3720         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3721                         state_entry->ucPCIELaneHigh);
3722
3723         performance_level = &(fiji_power_state->performance_levels
3724                         [fiji_power_state->performance_level_count++]);
3725         performance_level->memory_clock = mclk_dep_table->entries
3726                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
3727         performance_level->engine_clock = sclk_dep_table->entries
3728                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3729         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3730                         state_entry->ucPCIEGenHigh);
3731         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3732                         state_entry->ucPCIELaneHigh);
3733
3734         return 0;
3735 }
3736
3737 static int fiji_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3738                 unsigned long entry_index, struct pp_power_state *state)
3739 {
3740         int result;
3741         struct fiji_power_state *ps;
3742         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3743         struct phm_ppt_v1_information *table_info =
3744                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3745         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3746                         table_info->vdd_dep_on_mclk;
3747
3748         state->hardware.magic = PHM_VIslands_Magic;
3749
3750         ps = (struct fiji_power_state *)(&state->hardware);
3751
3752         result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3753                         fiji_get_pp_table_entry_callback_func);
3754
3755         /* This is the earliest time we have all the dependency table and the VBIOS boot state
3756          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3757          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3758          */
3759         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3760                 if (dep_mclk_table->entries[0].clk !=
3761                                 data->vbios_boot_state.mclk_bootup_value)
3762                         printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3763                                         "does not match VBIOS boot MCLK level");
3764                 if (dep_mclk_table->entries[0].vddci !=
3765                                 data->vbios_boot_state.vddci_bootup_value)
3766                         printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3767                                         "does not match VBIOS boot VDDCI level");
3768         }
3769
3770         /* set DC compatible flag if this state supports DC */
3771         if (!state->validation.disallowOnDC)
3772                 ps->dc_compatible = true;
3773
3774         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3775                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3776
3777         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3778         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3779
3780         if (!result) {
3781                 uint32_t i;
3782
3783                 switch (state->classification.ui_label) {
3784                 case PP_StateUILabel_Performance:
3785                         data->use_pcie_performance_levels = true;
3786
3787                         for (i = 0; i < ps->performance_level_count; i++) {
3788                                 if (data->pcie_gen_performance.max <
3789                                                 ps->performance_levels[i].pcie_gen)
3790                                         data->pcie_gen_performance.max =
3791                                                         ps->performance_levels[i].pcie_gen;
3792
3793                                 if (data->pcie_gen_performance.min >
3794                                                 ps->performance_levels[i].pcie_gen)
3795                                         data->pcie_gen_performance.min =
3796                                                         ps->performance_levels[i].pcie_gen;
3797
3798                                 if (data->pcie_lane_performance.max <
3799                                                 ps->performance_levels[i].pcie_lane)
3800                                         data->pcie_lane_performance.max =
3801                                                         ps->performance_levels[i].pcie_lane;
3802
3803                                 if (data->pcie_lane_performance.min >
3804                                                 ps->performance_levels[i].pcie_lane)
3805                                         data->pcie_lane_performance.min =
3806                                                         ps->performance_levels[i].pcie_lane;
3807                         }
3808                         break;
3809                 case PP_StateUILabel_Battery:
3810                         data->use_pcie_power_saving_levels = true;
3811
3812                         for (i = 0; i < ps->performance_level_count; i++) {
3813                                 if (data->pcie_gen_power_saving.max <
3814                                                 ps->performance_levels[i].pcie_gen)
3815                                         data->pcie_gen_power_saving.max =
3816                                                         ps->performance_levels[i].pcie_gen;
3817
3818                                 if (data->pcie_gen_power_saving.min >
3819                                                 ps->performance_levels[i].pcie_gen)
3820                                         data->pcie_gen_power_saving.min =
3821                                                         ps->performance_levels[i].pcie_gen;
3822
3823                                 if (data->pcie_lane_power_saving.max <
3824                                                 ps->performance_levels[i].pcie_lane)
3825                                         data->pcie_lane_power_saving.max =
3826                                                         ps->performance_levels[i].pcie_lane;
3827
3828                                 if (data->pcie_lane_power_saving.min >
3829                                                 ps->performance_levels[i].pcie_lane)
3830                                         data->pcie_lane_power_saving.min =
3831                                                         ps->performance_levels[i].pcie_lane;
3832                         }
3833                         break;
3834                 default:
3835                         break;
3836                 }
3837         }
3838         return 0;
3839 }
3840
3841 static int fiji_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3842                                 struct pp_power_state  *request_ps,
3843                         const struct pp_power_state *current_ps)
3844 {
3845         struct fiji_power_state *fiji_ps =
3846                                 cast_phw_fiji_power_state(&request_ps->hardware);
3847         uint32_t sclk;
3848         uint32_t mclk;
3849         struct PP_Clocks minimum_clocks = {0};
3850         bool disable_mclk_switching;
3851         bool disable_mclk_switching_for_frame_lock;
3852         struct cgs_display_info info = {0};
3853         const struct phm_clock_and_voltage_limits *max_limits;
3854         uint32_t i;
3855         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3856         struct phm_ppt_v1_information *table_info =
3857                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3858         int32_t count;
3859         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3860
3861         data->battery_state = (PP_StateUILabel_Battery ==
3862                         request_ps->classification.ui_label);
3863
3864         PP_ASSERT_WITH_CODE(fiji_ps->performance_level_count == 2,
3865                                  "VI should always have 2 performance levels",);
3866
3867         max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3868                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3869                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3870
3871         /* Cap clock DPM tables at DC MAX if it is in DC. */
3872         if (PP_PowerSource_DC == hwmgr->power_source) {
3873                 for (i = 0; i < fiji_ps->performance_level_count; i++) {
3874                         if (fiji_ps->performance_levels[i].memory_clock > max_limits->mclk)
3875                                 fiji_ps->performance_levels[i].memory_clock = max_limits->mclk;
3876                         if (fiji_ps->performance_levels[i].engine_clock > max_limits->sclk)
3877                                 fiji_ps->performance_levels[i].engine_clock = max_limits->sclk;
3878                 }
3879         }
3880
3881         fiji_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3882         fiji_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3883
3884         fiji_ps->acp_clk = hwmgr->acp_arbiter.acpclk;
3885
3886         cgs_get_active_displays_info(hwmgr->device, &info);
3887
3888         /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3889
3890         /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3891
3892         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3893                         PHM_PlatformCaps_StablePState)) {
3894                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3895                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3896
3897                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3898                                 count >= 0; count--) {
3899                         if (stable_pstate_sclk >=
3900                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3901                                 stable_pstate_sclk =
3902                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3903                                 break;
3904                         }
3905                 }
3906
3907                 if (count < 0)
3908                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3909
3910                 stable_pstate_mclk = max_limits->mclk;
3911
3912                 minimum_clocks.engineClock = stable_pstate_sclk;
3913                 minimum_clocks.memoryClock = stable_pstate_mclk;
3914         }
3915
3916         if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3917                 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3918
3919         if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3920                 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3921
3922         fiji_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3923
3924         if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3925                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3926                                 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3927                                 "Overdrive sclk exceeds limit",
3928                                 hwmgr->gfx_arbiter.sclk_over_drive =
3929                                                 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3930
3931                 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3932                         fiji_ps->performance_levels[1].engine_clock =
3933                                         hwmgr->gfx_arbiter.sclk_over_drive;
3934         }
3935
3936         if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3937                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3938                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3939                                 "Overdrive mclk exceeds limit",
3940                                 hwmgr->gfx_arbiter.mclk_over_drive =
3941                                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3942
3943                 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3944                         fiji_ps->performance_levels[1].memory_clock =
3945                                         hwmgr->gfx_arbiter.mclk_over_drive;
3946         }
3947
3948         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3949                                     hwmgr->platform_descriptor.platformCaps,
3950                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3951
3952         disable_mclk_switching = (1 < info.display_count) ||
3953                                     disable_mclk_switching_for_frame_lock;
3954
3955         sclk = fiji_ps->performance_levels[0].engine_clock;
3956         mclk = fiji_ps->performance_levels[0].memory_clock;
3957
3958         if (disable_mclk_switching)
3959                 mclk = fiji_ps->performance_levels
3960                 [fiji_ps->performance_level_count - 1].memory_clock;
3961
3962         if (sclk < minimum_clocks.engineClock)
3963                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3964                                 max_limits->sclk : minimum_clocks.engineClock;
3965
3966         if (mclk < minimum_clocks.memoryClock)
3967                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3968                                 max_limits->mclk : minimum_clocks.memoryClock;
3969
3970         fiji_ps->performance_levels[0].engine_clock = sclk;
3971         fiji_ps->performance_levels[0].memory_clock = mclk;
3972
3973         fiji_ps->performance_levels[1].engine_clock =
3974                 (fiji_ps->performance_levels[1].engine_clock >=
3975                                 fiji_ps->performance_levels[0].engine_clock) ?
3976                                                 fiji_ps->performance_levels[1].engine_clock :
3977                                                 fiji_ps->performance_levels[0].engine_clock;
3978
3979         if (disable_mclk_switching) {
3980                 if (mclk < fiji_ps->performance_levels[1].memory_clock)
3981                         mclk = fiji_ps->performance_levels[1].memory_clock;
3982
3983                 fiji_ps->performance_levels[0].memory_clock = mclk;
3984                 fiji_ps->performance_levels[1].memory_clock = mclk;
3985         } else {
3986                 if (fiji_ps->performance_levels[1].memory_clock <
3987                                 fiji_ps->performance_levels[0].memory_clock)
3988                         fiji_ps->performance_levels[1].memory_clock =
3989                                         fiji_ps->performance_levels[0].memory_clock;
3990         }
3991
3992         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3993                         PHM_PlatformCaps_StablePState)) {
3994                 for (i = 0; i < fiji_ps->performance_level_count; i++) {
3995                         fiji_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3996                         fiji_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3997                         fiji_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3998                         fiji_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3999                 }
4000         }
4001
4002         return 0;
4003 }
4004
4005 static int fiji_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
4006 {
4007         const struct phm_set_power_state_input *states =
4008                         (const struct phm_set_power_state_input *)input;
4009         const struct fiji_power_state *fiji_ps =
4010                         cast_const_phw_fiji_power_state(states->pnew_state);
4011         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4012         struct fiji_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4013         uint32_t sclk = fiji_ps->performance_levels
4014                         [fiji_ps->performance_level_count - 1].engine_clock;
4015         struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4016         uint32_t mclk = fiji_ps->performance_levels
4017                         [fiji_ps->performance_level_count - 1].memory_clock;
4018         struct PP_Clocks min_clocks = {0};
4019         uint32_t i;
4020         struct cgs_display_info info = {0};
4021
4022         data->need_update_smu7_dpm_table = 0;
4023
4024         for (i = 0; i < sclk_table->count; i++) {
4025                 if (sclk == sclk_table->dpm_levels[i].value)
4026                         break;
4027         }
4028
4029         if (i >= sclk_table->count)
4030                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4031         else {
4032         /* TODO: Check SCLK in DAL's minimum clocks
4033          * in case DeepSleep divider update is required.
4034          */
4035                 if(data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR)
4036                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4037         }
4038
4039         for (i = 0; i < mclk_table->count; i++) {
4040                 if (mclk == mclk_table->dpm_levels[i].value)
4041                         break;
4042         }
4043
4044         if (i >= mclk_table->count)
4045                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4046
4047         cgs_get_active_displays_info(hwmgr->device, &info);
4048
4049         if (data->display_timing.num_existing_displays != info.display_count)
4050                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4051
4052         return 0;
4053 }
4054
4055 static uint16_t fiji_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
4056                 const struct fiji_power_state *fiji_ps)
4057 {
4058         uint32_t i;
4059         uint32_t sclk, max_sclk = 0;
4060         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4061         struct fiji_dpm_table *dpm_table = &data->dpm_table;
4062
4063         for (i = 0; i < fiji_ps->performance_level_count; i++) {
4064                 sclk = fiji_ps->performance_levels[i].engine_clock;
4065                 if (max_sclk < sclk)
4066                         max_sclk = sclk;
4067         }
4068
4069         for (i = 0; i < dpm_table->sclk_table.count; i++) {
4070                 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
4071                         return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
4072                                         dpm_table->pcie_speed_table.dpm_levels
4073                                         [dpm_table->pcie_speed_table.count - 1].value :
4074                                         dpm_table->pcie_speed_table.dpm_levels[i].value);
4075         }
4076
4077         return 0;
4078 }
4079
4080 static int fiji_request_link_speed_change_before_state_change(
4081                 struct pp_hwmgr *hwmgr, const void *input)
4082 {
4083         const struct phm_set_power_state_input *states =
4084                         (const struct phm_set_power_state_input *)input;
4085         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4086         const struct fiji_power_state *fiji_nps =
4087                         cast_const_phw_fiji_power_state(states->pnew_state);
4088         const struct fiji_power_state *fiji_cps =
4089                         cast_const_phw_fiji_power_state(states->pcurrent_state);
4090
4091         uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_nps);
4092         uint16_t current_link_speed;
4093
4094         if (data->force_pcie_gen == PP_PCIEGenInvalid)
4095                 current_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_cps);
4096         else
4097                 current_link_speed = data->force_pcie_gen;
4098
4099         data->force_pcie_gen = PP_PCIEGenInvalid;
4100         data->pspp_notify_required = false;
4101         if (target_link_speed > current_link_speed) {
4102                 switch(target_link_speed) {
4103                 case PP_PCIEGen3:
4104                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
4105                                 break;
4106                         data->force_pcie_gen = PP_PCIEGen2;
4107                         if (current_link_speed == PP_PCIEGen2)
4108                                 break;
4109                 case PP_PCIEGen2:
4110                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
4111                                 break;
4112                 default:
4113                         data->force_pcie_gen = fiji_get_current_pcie_speed(hwmgr);
4114                         break;
4115                 }
4116         } else {
4117                 if (target_link_speed < current_link_speed)
4118                         data->pspp_notify_required = true;
4119         }
4120
4121         return 0;
4122 }
4123
4124 static int fiji_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4125 {
4126         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4127
4128         if (0 == data->need_update_smu7_dpm_table)
4129                 return 0;
4130
4131         if ((0 == data->sclk_dpm_key_disabled) &&
4132                 (data->need_update_smu7_dpm_table &
4133                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4134                 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4135                                 "Trying to freeze SCLK DPM when DPM is disabled",);
4136                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4137                                 PPSMC_MSG_SCLKDPM_FreezeLevel),
4138                                 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4139                                 return -1);
4140         }
4141
4142         if ((0 == data->mclk_dpm_key_disabled) &&
4143                 (data->need_update_smu7_dpm_table &
4144                  DPMTABLE_OD_UPDATE_MCLK)) {
4145                 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4146                                 "Trying to freeze MCLK DPM when DPM is disabled",);
4147                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4148                                 PPSMC_MSG_MCLKDPM_FreezeLevel),
4149                                 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4150                                 return -1);
4151         }
4152
4153         return 0;
4154 }
4155
4156 static int fiji_populate_and_upload_sclk_mclk_dpm_levels(
4157                 struct pp_hwmgr *hwmgr, const void *input)
4158 {
4159         int result = 0;
4160         const struct phm_set_power_state_input *states =
4161                         (const struct phm_set_power_state_input *)input;
4162         const struct fiji_power_state *fiji_ps =
4163                         cast_const_phw_fiji_power_state(states->pnew_state);
4164         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4165         uint32_t sclk = fiji_ps->performance_levels
4166                         [fiji_ps->performance_level_count - 1].engine_clock;
4167         uint32_t mclk = fiji_ps->performance_levels
4168                         [fiji_ps->performance_level_count - 1].memory_clock;
4169         struct fiji_dpm_table *dpm_table = &data->dpm_table;
4170
4171         struct fiji_dpm_table *golden_dpm_table = &data->golden_dpm_table;
4172         uint32_t dpm_count, clock_percent;
4173         uint32_t i;
4174
4175         if (0 == data->need_update_smu7_dpm_table)
4176                 return 0;
4177
4178         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4179                 dpm_table->sclk_table.dpm_levels
4180                 [dpm_table->sclk_table.count - 1].value = sclk;
4181
4182                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4183                                 PHM_PlatformCaps_OD6PlusinACSupport) ||
4184                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4185                                         PHM_PlatformCaps_OD6PlusinDCSupport)) {
4186                 /* Need to do calculation based on the golden DPM table
4187                  * as the Heatmap GPU Clock axis is also based on the default values
4188                  */
4189                         PP_ASSERT_WITH_CODE(
4190                                 (golden_dpm_table->sclk_table.dpm_levels
4191                                                 [golden_dpm_table->sclk_table.count - 1].value != 0),
4192                                 "Divide by 0!",
4193                                 return -1);
4194                         dpm_count = dpm_table->sclk_table.count < 2 ?
4195                                         0 : dpm_table->sclk_table.count - 2;
4196                         for (i = dpm_count; i > 1; i--) {
4197                                 if (sclk > golden_dpm_table->sclk_table.dpm_levels
4198                                                 [golden_dpm_table->sclk_table.count-1].value) {
4199                                         clock_percent =
4200                                                 ((sclk - golden_dpm_table->sclk_table.dpm_levels
4201                                                         [golden_dpm_table->sclk_table.count-1].value) * 100) /
4202                                                 golden_dpm_table->sclk_table.dpm_levels
4203                                                         [golden_dpm_table->sclk_table.count-1].value;
4204
4205                                         dpm_table->sclk_table.dpm_levels[i].value =
4206                                                         golden_dpm_table->sclk_table.dpm_levels[i].value +
4207                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
4208                                                                 clock_percent)/100;
4209
4210                                 } else if (golden_dpm_table->sclk_table.dpm_levels
4211                                                 [dpm_table->sclk_table.count-1].value > sclk) {
4212                                         clock_percent =
4213                                                 ((golden_dpm_table->sclk_table.dpm_levels
4214                                                 [golden_dpm_table->sclk_table.count - 1].value - sclk) *
4215                                                                 100) /
4216                                                 golden_dpm_table->sclk_table.dpm_levels
4217                                                         [golden_dpm_table->sclk_table.count-1].value;
4218
4219                                         dpm_table->sclk_table.dpm_levels[i].value =
4220                                                         golden_dpm_table->sclk_table.dpm_levels[i].value -
4221                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
4222                                                                         clock_percent) / 100;
4223                                 } else
4224                                         dpm_table->sclk_table.dpm_levels[i].value =
4225                                                         golden_dpm_table->sclk_table.dpm_levels[i].value;
4226                         }
4227                 }
4228         }
4229
4230         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4231                 dpm_table->mclk_table.dpm_levels
4232                         [dpm_table->mclk_table.count - 1].value = mclk;
4233
4234                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4235                                 PHM_PlatformCaps_OD6PlusinACSupport) ||
4236                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4237                                 PHM_PlatformCaps_OD6PlusinDCSupport)) {
4238
4239                         PP_ASSERT_WITH_CODE(
4240                                         (golden_dpm_table->mclk_table.dpm_levels
4241                                                 [golden_dpm_table->mclk_table.count-1].value != 0),
4242                                         "Divide by 0!",
4243                                         return -1);
4244                         dpm_count = dpm_table->mclk_table.count < 2 ?
4245                                         0 : dpm_table->mclk_table.count - 2;
4246                         for (i = dpm_count; i > 1; i--) {
4247                                 if (mclk > golden_dpm_table->mclk_table.dpm_levels
4248                                                 [golden_dpm_table->mclk_table.count-1].value) {
4249                                         clock_percent = ((mclk -
4250                                                         golden_dpm_table->mclk_table.dpm_levels
4251                                                         [golden_dpm_table->mclk_table.count-1].value) * 100) /
4252                                                         golden_dpm_table->mclk_table.dpm_levels
4253                                                         [golden_dpm_table->mclk_table.count-1].value;
4254
4255                                         dpm_table->mclk_table.dpm_levels[i].value =
4256                                                         golden_dpm_table->mclk_table.dpm_levels[i].value +
4257                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4258                                                                         clock_percent) / 100;
4259
4260                                 } else if (golden_dpm_table->mclk_table.dpm_levels
4261                                                 [dpm_table->mclk_table.count-1].value > mclk) {
4262                                         clock_percent = ((golden_dpm_table->mclk_table.dpm_levels
4263                                                         [golden_dpm_table->mclk_table.count-1].value - mclk) * 100) /
4264                                                                         golden_dpm_table->mclk_table.dpm_levels
4265                                                                         [golden_dpm_table->mclk_table.count-1].value;
4266
4267                                         dpm_table->mclk_table.dpm_levels[i].value =
4268                                                         golden_dpm_table->mclk_table.dpm_levels[i].value -
4269                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4270                                                                         clock_percent) / 100;
4271                                 } else
4272                                         dpm_table->mclk_table.dpm_levels[i].value =
4273                                                         golden_dpm_table->mclk_table.dpm_levels[i].value;
4274                         }
4275                 }
4276         }
4277
4278         if (data->need_update_smu7_dpm_table &
4279                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4280                 result = fiji_populate_all_memory_levels(hwmgr);
4281                 PP_ASSERT_WITH_CODE((0 == result),
4282                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4283                                 return result);
4284         }
4285
4286         if (data->need_update_smu7_dpm_table &
4287                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4288                 /*populate MCLK dpm table to SMU7 */
4289                 result = fiji_populate_all_memory_levels(hwmgr);
4290                 PP_ASSERT_WITH_CODE((0 == result),
4291                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4292                                 return result);
4293         }
4294
4295         return result;
4296 }
4297
4298 static int fiji_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4299                           struct fiji_single_dpm_table * dpm_table,
4300                              uint32_t low_limit, uint32_t high_limit)
4301 {
4302         uint32_t i;
4303
4304         for (i = 0; i < dpm_table->count; i++) {
4305                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
4306                     (dpm_table->dpm_levels[i].value > high_limit))
4307                         dpm_table->dpm_levels[i].enabled = false;
4308                 else
4309                         dpm_table->dpm_levels[i].enabled = true;
4310         }
4311         return 0;
4312 }
4313
4314 static int fiji_trim_dpm_states(struct pp_hwmgr *hwmgr,
4315                 const struct fiji_power_state *fiji_ps)
4316 {
4317         int result = 0;
4318         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4319         uint32_t high_limit_count;
4320
4321         PP_ASSERT_WITH_CODE((fiji_ps->performance_level_count >= 1),
4322                         "power state did not have any performance level",
4323                         return -1);
4324
4325         high_limit_count = (1 == fiji_ps->performance_level_count) ? 0 : 1;
4326
4327         fiji_trim_single_dpm_states(hwmgr,
4328                         &(data->dpm_table.sclk_table),
4329                         fiji_ps->performance_levels[0].engine_clock,
4330                         fiji_ps->performance_levels[high_limit_count].engine_clock);
4331
4332         fiji_trim_single_dpm_states(hwmgr,
4333                         &(data->dpm_table.mclk_table),
4334                         fiji_ps->performance_levels[0].memory_clock,
4335                         fiji_ps->performance_levels[high_limit_count].memory_clock);
4336
4337         return result;
4338 }
4339
4340 static int fiji_generate_dpm_level_enable_mask(
4341                 struct pp_hwmgr *hwmgr, const void *input)
4342 {
4343         int result;
4344         const struct phm_set_power_state_input *states =
4345                         (const struct phm_set_power_state_input *)input;
4346         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4347         const struct fiji_power_state *fiji_ps =
4348                         cast_const_phw_fiji_power_state(states->pnew_state);
4349
4350         result = fiji_trim_dpm_states(hwmgr, fiji_ps);
4351         if (result)
4352                 return result;
4353
4354         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4355                         fiji_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4356         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4357                         fiji_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4358         data->last_mclk_dpm_enable_mask =
4359                         data->dpm_level_enable_mask.mclk_dpm_enable_mask;
4360
4361         if (data->uvd_enabled) {
4362                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4363                         data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4364         }
4365
4366         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4367                         fiji_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4368
4369         return 0;
4370 }
4371
4372 static int fiji_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4373 {
4374         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4375                         PPSMC_MSG_VCEDPM_Enable :
4376                         PPSMC_MSG_VCEDPM_Disable);
4377 }
4378
4379 static int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4380 {
4381         const struct phm_set_power_state_input *states =
4382                         (const struct phm_set_power_state_input *)input;
4383         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4384         const struct fiji_power_state *fiji_nps =
4385                         cast_const_phw_fiji_power_state(states->pnew_state);
4386         const struct fiji_power_state *fiji_cps =
4387                         cast_const_phw_fiji_power_state(states->pcurrent_state);
4388
4389         uint32_t mm_boot_level_offset, mm_boot_level_value;
4390         struct phm_ppt_v1_information *table_info =
4391                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4392
4393         if (fiji_nps->vce_clks.evclk >0 &&
4394         (fiji_cps == NULL || fiji_cps->vce_clks.evclk == 0)) {
4395                 data->smc_state_table.VceBootLevel =
4396                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4397
4398                 mm_boot_level_offset = data->dpm_table_start +
4399                                 offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
4400                 mm_boot_level_offset /= 4;
4401                 mm_boot_level_offset *= 4;
4402                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4403                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4404                 mm_boot_level_value &= 0xFF00FFFF;
4405                 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4406                 cgs_write_ind_register(hwmgr->device,
4407                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4408
4409                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4410                                 PHM_PlatformCaps_StablePState)) {
4411                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4412                                         PPSMC_MSG_VCEDPM_SetEnabledMask,
4413                                         (uint32_t)1 << data->smc_state_table.VceBootLevel);
4414
4415                         fiji_enable_disable_vce_dpm(hwmgr, true);
4416                 } else if (fiji_nps->vce_clks.evclk == 0 &&
4417                                 fiji_cps != NULL &&
4418                                 fiji_cps->vce_clks.evclk > 0)
4419                         fiji_enable_disable_vce_dpm(hwmgr, false);
4420         }
4421
4422         return 0;
4423 }
4424
4425 static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4426 {
4427         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4428
4429         int result = 0;
4430         uint32_t low_sclk_interrupt_threshold = 0;
4431
4432         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4433                         PHM_PlatformCaps_SclkThrottleLowNotification)
4434                 && (hwmgr->gfx_arbiter.sclk_threshold !=
4435                                 data->low_sclk_interrupt_threshold)) {
4436                 data->low_sclk_interrupt_threshold =
4437                                 hwmgr->gfx_arbiter.sclk_threshold;
4438                 low_sclk_interrupt_threshold =
4439                                 data->low_sclk_interrupt_threshold;
4440
4441                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4442
4443                 result = fiji_copy_bytes_to_smc(
4444                                 hwmgr->smumgr,
4445                                 data->dpm_table_start +
4446                                 offsetof(SMU73_Discrete_DpmTable,
4447                                         LowSclkInterruptThreshold),
4448                                 (uint8_t *)&low_sclk_interrupt_threshold,
4449                                 sizeof(uint32_t),
4450                                 data->sram_end);
4451         }
4452
4453         return result;
4454 }
4455
4456 static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4457 {
4458         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4459
4460         if (data->need_update_smu7_dpm_table &
4461                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4462                 return fiji_program_memory_timing_parameters(hwmgr);
4463
4464         return 0;
4465 }
4466
4467 static int fiji_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4468 {
4469         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4470
4471         if (0 == data->need_update_smu7_dpm_table)
4472                 return 0;
4473
4474         if ((0 == data->sclk_dpm_key_disabled) &&
4475                 (data->need_update_smu7_dpm_table &
4476                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4477
4478                 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4479                                 "Trying to Unfreeze SCLK DPM when DPM is disabled",);
4480                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4481                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4482                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4483                         return -1);
4484         }
4485
4486         if ((0 == data->mclk_dpm_key_disabled) &&
4487                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4488
4489                 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4490                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",);
4491                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4492                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4493                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4494                     return -1);
4495         }
4496
4497         data->need_update_smu7_dpm_table = 0;
4498
4499         return 0;
4500 }
4501
4502 /* Look up the voltaged based on DAL's requested level.
4503  * and then send the requested VDDC voltage to SMC
4504  */
4505 static void fiji_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr)
4506 {
4507         return;
4508 }
4509
4510 int fiji_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
4511 {
4512         int result;
4513         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4514
4515         /* Apply minimum voltage based on DAL's request level */
4516         fiji_apply_dal_minimum_voltage_request(hwmgr);
4517
4518         if (0 == data->sclk_dpm_key_disabled) {
4519                 /* Checking if DPM is running.  If we discover hang because of this,
4520                  *  we should skip this message.
4521                  */
4522                 if (!fiji_is_dpm_running(hwmgr))
4523                         printk(KERN_ERR "[ powerplay ] "
4524                                         "Trying to set Enable Mask when DPM is disabled \n");
4525
4526                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4527                         result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4528                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
4529                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
4530                         PP_ASSERT_WITH_CODE((0 == result),
4531                                 "Set Sclk Dpm enable Mask failed", return -1);
4532                 }
4533         }
4534
4535         if (0 == data->mclk_dpm_key_disabled) {
4536                 /* Checking if DPM is running.  If we discover hang because of this,
4537                  *  we should skip this message.
4538                  */
4539                 if (!fiji_is_dpm_running(hwmgr))
4540                         printk(KERN_ERR "[ powerplay ]"
4541                                         " Trying to set Enable Mask when DPM is disabled \n");
4542
4543                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4544                         result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4545                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
4546                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask);
4547                         PP_ASSERT_WITH_CODE((0 == result),
4548                                 "Set Mclk Dpm enable Mask failed", return -1);
4549                 }
4550         }
4551
4552         return 0;
4553 }
4554
4555 static int fiji_notify_link_speed_change_after_state_change(
4556                 struct pp_hwmgr *hwmgr, const void *input)
4557 {
4558         const struct phm_set_power_state_input *states =
4559                         (const struct phm_set_power_state_input *)input;
4560         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4561         const struct fiji_power_state *fiji_ps =
4562                         cast_const_phw_fiji_power_state(states->pnew_state);
4563         uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_ps);
4564         uint8_t  request;
4565
4566         if (data->pspp_notify_required) {
4567                 if (target_link_speed == PP_PCIEGen3)
4568                         request = PCIE_PERF_REQ_GEN3;
4569                 else if (target_link_speed == PP_PCIEGen2)
4570                         request = PCIE_PERF_REQ_GEN2;
4571                 else
4572                         request = PCIE_PERF_REQ_GEN1;
4573
4574                 if(request == PCIE_PERF_REQ_GEN1 &&
4575                                 fiji_get_current_pcie_speed(hwmgr) > 0)
4576                         return 0;
4577
4578                 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4579                         if (PP_PCIEGen2 == target_link_speed)
4580                                 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4581                         else
4582                                 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4583                 }
4584         }
4585
4586         return 0;
4587 }
4588
4589 static int fiji_set_power_state_tasks(struct pp_hwmgr *hwmgr,
4590                 const void *input)
4591 {
4592         int tmp_result, result = 0;
4593
4594         tmp_result = fiji_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4595         PP_ASSERT_WITH_CODE((0 == tmp_result),
4596                         "Failed to find DPM states clocks in DPM table!",
4597                         result = tmp_result);
4598
4599         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4600                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4601                 tmp_result =
4602                         fiji_request_link_speed_change_before_state_change(hwmgr, input);
4603                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4604                                 "Failed to request link speed change before state change!",
4605                                 result = tmp_result);
4606         }
4607
4608         tmp_result = fiji_freeze_sclk_mclk_dpm(hwmgr);
4609         PP_ASSERT_WITH_CODE((0 == tmp_result),
4610                         "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4611
4612         tmp_result = fiji_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4613         PP_ASSERT_WITH_CODE((0 == tmp_result),
4614                         "Failed to populate and upload SCLK MCLK DPM levels!",
4615                         result = tmp_result);
4616
4617         tmp_result = fiji_generate_dpm_level_enable_mask(hwmgr, input);
4618         PP_ASSERT_WITH_CODE((0 == tmp_result),
4619                         "Failed to generate DPM level enabled mask!",
4620                         result = tmp_result);
4621
4622         tmp_result = fiji_update_vce_dpm(hwmgr, input);
4623         PP_ASSERT_WITH_CODE((0 == tmp_result),
4624                         "Failed to update VCE DPM!",
4625                         result = tmp_result);
4626
4627         tmp_result = fiji_update_sclk_threshold(hwmgr);
4628         PP_ASSERT_WITH_CODE((0 == tmp_result),
4629                         "Failed to update SCLK threshold!",
4630                         result = tmp_result);
4631
4632         tmp_result = fiji_program_mem_timing_parameters(hwmgr);
4633         PP_ASSERT_WITH_CODE((0 == tmp_result),
4634                         "Failed to program memory timing parameters!",
4635                         result = tmp_result);
4636
4637         tmp_result = fiji_unfreeze_sclk_mclk_dpm(hwmgr);
4638         PP_ASSERT_WITH_CODE((0 == tmp_result),
4639                         "Failed to unfreeze SCLK MCLK DPM!",
4640                         result = tmp_result);
4641
4642         tmp_result = fiji_upload_dpm_level_enable_mask(hwmgr);
4643         PP_ASSERT_WITH_CODE((0 == tmp_result),
4644                         "Failed to upload DPM level enabled mask!",
4645                         result = tmp_result);
4646
4647         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4648                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4649                 tmp_result =
4650                         fiji_notify_link_speed_change_after_state_change(hwmgr, input);
4651                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4652                                 "Failed to notify link speed change after state change!",
4653                                 result = tmp_result);
4654         }
4655
4656         return result;
4657 }
4658
4659 static int fiji_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
4660 {
4661         struct pp_power_state  *ps;
4662         struct fiji_power_state  *fiji_ps;
4663
4664         if (hwmgr == NULL)
4665                 return -EINVAL;
4666
4667         ps = hwmgr->request_ps;
4668
4669         if (ps == NULL)
4670                 return -EINVAL;
4671
4672         fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
4673
4674         if (low)
4675                 return fiji_ps->performance_levels[0].engine_clock;
4676         else
4677                 return fiji_ps->performance_levels
4678                                 [fiji_ps->performance_level_count-1].engine_clock;
4679 }
4680
4681 static int fiji_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
4682 {
4683         struct pp_power_state  *ps;
4684         struct fiji_power_state  *fiji_ps;
4685
4686         if (hwmgr == NULL)
4687                 return -EINVAL;
4688
4689         ps = hwmgr->request_ps;
4690
4691         if (ps == NULL)
4692                 return -EINVAL;
4693
4694         fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
4695
4696         if (low)
4697                 return fiji_ps->performance_levels[0].memory_clock;
4698         else
4699                 return fiji_ps->performance_levels
4700                                 [fiji_ps->performance_level_count-1].memory_clock;
4701 }
4702
4703 static void fiji_print_current_perforce_level(
4704                 struct pp_hwmgr *hwmgr, struct seq_file *m)
4705 {
4706         uint32_t sclk, mclk;
4707
4708         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4709
4710         sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4711
4712         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4713
4714         mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4715         seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
4716                         mclk / 100, sclk / 100);
4717 }
4718
4719 static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
4720         .backend_init = &fiji_hwmgr_backend_init,
4721         .backend_fini = &tonga_hwmgr_backend_fini,
4722         .asic_setup = &fiji_setup_asic_task,
4723         .dynamic_state_management_enable = &fiji_enable_dpm_tasks,
4724         .force_dpm_level = &fiji_dpm_force_dpm_level,
4725         .get_num_of_pp_table_entries = &tonga_get_number_of_powerplay_table_entries,
4726         .get_power_state_size = &fiji_get_power_state_size,
4727         .get_pp_table_entry = &fiji_get_pp_table_entry,
4728         .patch_boot_state = &fiji_patch_boot_state,
4729         .apply_state_adjust_rules = &fiji_apply_state_adjust_rules,
4730         .power_state_set = &fiji_set_power_state_tasks,
4731         .get_sclk = &fiji_dpm_get_sclk,
4732         .get_mclk = &fiji_dpm_get_mclk,
4733         .print_current_perforce_level = &fiji_print_current_perforce_level,
4734 };
4735
4736 int fiji_hwmgr_init(struct pp_hwmgr *hwmgr)
4737 {
4738         struct fiji_hwmgr  *data;
4739         int ret = 0;
4740
4741         data = kzalloc(sizeof(struct fiji_hwmgr), GFP_KERNEL);
4742         if (data == NULL)
4743                 return -ENOMEM;
4744
4745         hwmgr->backend = data;
4746         hwmgr->hwmgr_func = &fiji_hwmgr_funcs;
4747         hwmgr->pptable_func = &tonga_pptable_funcs;
4748         return ret;
4749 }