drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include "linux/delay.h"
  26
  27 #include "hwmgr.h"
  28 #include "fiji_smumgr.h"
  29 #include "atombios.h"
  30 #include "hardwaremanager.h"
  31 #include "ppatomctrl.h"
  32 #include "atombios.h"
  33 #include "cgs_common.h"
  34 #include "fiji_dyn_defaults.h"
  35 #include "fiji_powertune.h"
  36 #include "smu73.h"
  37 #include "smu/smu_7_1_3_d.h"
  38 #include "smu/smu_7_1_3_sh_mask.h"
  39 #include "gmc/gmc_8_1_d.h"
  40 #include "gmc/gmc_8_1_sh_mask.h"
  41 #include "bif/bif_5_0_d.h"
  42 #include "bif/bif_5_0_sh_mask.h"
  43 #include "dce/dce_10_0_d.h"
  44 #include "dce/dce_10_0_sh_mask.h"
  45 #include "pppcielanes.h"
  46 #include "fiji_hwmgr.h"
  47 #include "process_pptables_v1_0.h"
  48 #include "pptable_v1_0.h"
  49 #include "pp_debug.h"
  50 #include "pp_acpi.h"
  51 #include "amd_pcie_helpers.h"
  52 #include "cgs_linux.h"
  53 #include "ppinterrupt.h"
  54
  55 #include "fiji_clockpowergating.h"
  56 #include "fiji_thermal.h"
  57
  58 #define VOLTAGE_SCALE   4
  59 #define SMC_RAM_END             0x40000
  60 #define VDDC_VDDCI_DELTA        300
  61
  62 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  63 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  64 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  65
  66 #define MC_CG_ARB_FREQ_F0           0x0a /* boot-up default */
  67 #define MC_CG_ARB_FREQ_F1           0x0b
  68 #define MC_CG_ARB_FREQ_F2           0x0c
  69 #define MC_CG_ARB_FREQ_F3           0x0d
  70
  71 /* From smc_reg.h */
  72 #define SMC_CG_IND_START            0xc0030000
  73 #define SMC_CG_IND_END              0xc0040000  /* First byte after SMC_CG_IND */
  74
  75 #define VOLTAGE_SCALE               4
  76 #define VOLTAGE_VID_OFFSET_SCALE1   625
  77 #define VOLTAGE_VID_OFFSET_SCALE2   100
  78
  79 #define VDDC_VDDCI_DELTA            300
  80
  81 #define ixSWRST_COMMAND_1           0x1400103
  82 #define MC_SEQ_CNTL__CAC_EN_MASK    0x40000000
  83
  84 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
  85 enum DPM_EVENT_SRC {
  86     DPM_EVENT_SRC_ANALOG = 0,               /* Internal analog trip point */
  87     DPM_EVENT_SRC_EXTERNAL = 1,             /* External (GPIO 17) signal */
  88     DPM_EVENT_SRC_DIGITAL = 2,              /* Internal digital trip point (DIG_THERM_DPM) */
  89     DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,   /* Internal analog or external */
  90     DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4   /* Internal digital or external */
  91 };
  92
  93
  94 /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
  95  * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
  96  */
  97 static const uint16_t fiji_clock_stretcher_lookup_table[2][4] =
  98 { {600, 1050, 3, 0}, {600, 1050, 6, 1} };
  99
 100 /* [FF, SS] type, [] 4 voltage ranges, and
 101  * [Floor Freq, Boundary Freq, VID min , VID max]
 102  */
 103 static const uint32_t fiji_clock_stretcher_ddt_table[2][4][4] =
 104 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
 105   { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
 106
 107 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
 108  * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
 109  */
 110 static const uint8_t fiji_clock_stretch_amount_conversion[2][6] =
 111 { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
 112
 113 static const unsigned long PhwFiji_Magic = (unsigned long)(PHM_VIslands_Magic);
 114
 115 static struct fiji_power_state *cast_phw_fiji_power_state(
 116                                   struct pp_hw_power_state *hw_ps)
 117 {
 118         PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
 119                                 "Invalid Powerstate Type!",
 120                                  return NULL;);
 121
 122         return (struct fiji_power_state *)hw_ps;
 123 }
 124
 125 static const struct
 126 fiji_power_state *cast_const_phw_fiji_power_state(
 127                                  const struct pp_hw_power_state *hw_ps)
 128 {
 129         PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
 130                                 "Invalid Powerstate Type!",
 131                                  return NULL;);
 132
 133         return (const struct fiji_power_state *)hw_ps;
 134 }
 135
 136 static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr)
 137 {
 138         return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
 139                         CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
 140                         ? true : false;
 141 }
 142
 143 static void fiji_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 144 {
 145         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 146         struct fiji_ulv_parm *ulv = &data->ulv;
 147
 148         ulv->cg_ulv_parameter = PPFIJI_CGULVPARAMETER_DFLT;
 149         data->voting_rights_clients0 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT0;
 150         data->voting_rights_clients1 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT1;
 151         data->voting_rights_clients2 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT2;
 152         data->voting_rights_clients3 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT3;
 153         data->voting_rights_clients4 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT4;
 154         data->voting_rights_clients5 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT5;
 155         data->voting_rights_clients6 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT6;
 156         data->voting_rights_clients7 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT7;
 157
 158         data->static_screen_threshold_unit =
 159                         PPFIJI_STATICSCREENTHRESHOLDUNIT_DFLT;
 160         data->static_screen_threshold =
 161                         PPFIJI_STATICSCREENTHRESHOLD_DFLT;
 162
 163         /* Unset ABM cap as it moved to DAL.
 164          * Add PHM_PlatformCaps_NonABMSupportInPPLib
 165          * for re-direct ABM related request to DAL
 166          */
 167         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 168                         PHM_PlatformCaps_ABM);
 169         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 170                         PHM_PlatformCaps_NonABMSupportInPPLib);
 171
 172         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 173                         PHM_PlatformCaps_DynamicACTiming);
 174
 175         fiji_initialize_power_tune_defaults(hwmgr);
 176
 177         data->mclk_stutter_mode_threshold = 60000;
 178         data->pcie_gen_performance.max = PP_PCIEGen1;
 179         data->pcie_gen_performance.min = PP_PCIEGen3;
 180         data->pcie_gen_power_saving.max = PP_PCIEGen1;
 181         data->pcie_gen_power_saving.min = PP_PCIEGen3;
 182         data->pcie_lane_performance.max = 0;
 183         data->pcie_lane_performance.min = 16;
 184         data->pcie_lane_power_saving.max = 0;
 185         data->pcie_lane_power_saving.min = 16;
 186
 187         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 188                         PHM_PlatformCaps_DynamicUVDState);
 189 }
 190
 191 static int fiji_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
 192         phm_ppt_v1_voltage_lookup_table *lookup_table,
 193         uint16_t virtual_voltage_id, int32_t *sclk)
 194 {
 195         uint8_t entryId;
 196         uint8_t voltageId;
 197         struct phm_ppt_v1_information *table_info =
 198                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 199
 200         PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);
 201
 202         /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
 203         for (entryId = 0; entryId < table_info->vdd_dep_on_sclk->count; entryId++) {
 204                 voltageId = table_info->vdd_dep_on_sclk->entries[entryId].vddInd;
 205                 if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
 206                         break;
 207         }
 208
 209         PP_ASSERT_WITH_CODE(entryId < table_info->vdd_dep_on_sclk->count,
 210                         "Can't find requested voltage id in vdd_dep_on_sclk table!",
 211                         return -EINVAL;
 212                         );
 213
 214         *sclk = table_info->vdd_dep_on_sclk->entries[entryId].clk;
 215
 216         return 0;
 217 }
 218
 219 /**
 220 * Get Leakage VDDC based on leakage ID.
 221 *
 222 * @param    hwmgr  the address of the powerplay hardware manager.
 223 * @return   always 0
 224 */
 225 static int fiji_get_evv_voltages(struct pp_hwmgr *hwmgr)
 226 {
 227         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 228         uint16_t    vv_id;
 229         uint16_t    vddc = 0;
 230         uint16_t    evv_default = 1150;
 231         uint16_t    i, j;
 232         uint32_t  sclk = 0;
 233         struct phm_ppt_v1_information *table_info =
 234                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 235         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
 236                         table_info->vdd_dep_on_sclk;
 237         int result;
 238
 239         for (i = 0; i < FIJI_MAX_LEAKAGE_COUNT; i++) {
 240                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 241                 if (!fiji_get_sclk_for_voltage_evv(hwmgr,
 242                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
 243                         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 244                                         PHM_PlatformCaps_ClockStretcher)) {
 245                                 for (j = 1; j < sclk_table->count; j++) {
 246                                         if (sclk_table->entries[j].clk == sclk &&
 247                                                         sclk_table->entries[j].cks_enable == 0) {
 248                                                 sclk += 5000;
 249                                                 break;
 250                                         }
 251                                 }
 252                         }
 253
 254                         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 255                                         PHM_PlatformCaps_EnableDriverEVV))
 256                                 result = atomctrl_calculate_voltage_evv_on_sclk(hwmgr,
 257                                                 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc, i, true);
 258                         else
 259                                 result = -EINVAL;
 260
 261                         if (result)
 262                                 result = atomctrl_get_voltage_evv_on_sclk(hwmgr,
 263                                                 VOLTAGE_TYPE_VDDC, sclk,vv_id, &vddc);
 264
 265                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
 266                         PP_ASSERT_WITH_CODE((vddc < 2000),
 267                                         "Invalid VDDC value, greater than 2v!", result = -EINVAL;);
 268
 269                         if (result)
 270                                 /* 1.15V is the default safe value for Fiji */
 271                                 vddc = evv_default;
 272
 273                         /* the voltage should not be zero nor equal to leakage ID */
 274                         if (vddc != 0 && vddc != vv_id) {
 275                                 data->vddc_leakage.actual_voltage
 276                                 [data->vddc_leakage.count] = vddc;
 277                                 data->vddc_leakage.leakage_id
 278                                 [data->vddc_leakage.count] = vv_id;
 279                                 data->vddc_leakage.count++;
 280                         }
 281                 }
 282         }
 283         return 0;
 284 }
 285
 286 /**
 287  * Change virtual leakage voltage to actual value.
 288  *
 289  * @param     hwmgr  the address of the powerplay hardware manager.
 290  * @param     pointer to changing voltage
 291  * @param     pointer to leakage table
 292  */
 293 static void fiji_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
 294                 uint16_t *voltage, struct fiji_leakage_voltage *leakage_table)
 295 {
 296         uint32_t index;
 297
 298         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
 299         for (index = 0; index < leakage_table->count; index++) {
 300                 /* if this voltage matches a leakage voltage ID */
 301                 /* patch with actual leakage voltage */
 302                 if (leakage_table->leakage_id[index] == *voltage) {
 303                         *voltage = leakage_table->actual_voltage[index];
 304                         break;
 305                 }
 306         }
 307
 308         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
 309                 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
 310 }
 311
 312 /**
 313 * Patch voltage lookup table by EVV leakages.
 314 *
 315 * @param     hwmgr  the address of the powerplay hardware manager.
 316 * @param     pointer to voltage lookup table
 317 * @param     pointer to leakage table
 318 * @return     always 0
 319 */
 320 static int fiji_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
 321                 phm_ppt_v1_voltage_lookup_table *lookup_table,
 322                 struct fiji_leakage_voltage *leakage_table)
 323 {
 324         uint32_t i;
 325
 326         for (i = 0; i < lookup_table->count; i++)
 327                 fiji_patch_with_vdd_leakage(hwmgr,
 328                                 &lookup_table->entries[i].us_vdd, leakage_table);
 329
 330         return 0;
 331 }
 332
 333 static int fiji_patch_clock_voltage_limits_with_vddc_leakage(
 334                 struct pp_hwmgr *hwmgr, struct fiji_leakage_voltage *leakage_table,
 335                 uint16_t *vddc)
 336 {
 337         struct phm_ppt_v1_information *table_info =
 338                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 339         fiji_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
 340         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
 341                         table_info->max_clock_voltage_on_dc.vddc;
 342         return 0;
 343 }
 344
 345 static int fiji_patch_voltage_dependency_tables_with_lookup_table(
 346                 struct pp_hwmgr *hwmgr)
 347 {
 348         uint8_t entryId;
 349         uint8_t voltageId;
 350         struct phm_ppt_v1_information *table_info =
 351                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 352
 353         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
 354                         table_info->vdd_dep_on_sclk;
 355         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
 356                         table_info->vdd_dep_on_mclk;
 357         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
 358                         table_info->mm_dep_table;
 359
 360         for (entryId = 0; entryId < sclk_table->count; ++entryId) {
 361                 voltageId = sclk_table->entries[entryId].vddInd;
 362                 sclk_table->entries[entryId].vddc =
 363                                 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
 364         }
 365
 366         for (entryId = 0; entryId < mclk_table->count; ++entryId) {
 367                 voltageId = mclk_table->entries[entryId].vddInd;
 368                 mclk_table->entries[entryId].vddc =
 369                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
 370         }
 371
 372         for (entryId = 0; entryId < mm_table->count; ++entryId) {
 373                 voltageId = mm_table->entries[entryId].vddcInd;
 374                 mm_table->entries[entryId].vddc =
 375                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
 376         }
 377
 378         return 0;
 379
 380 }
 381
 382 static int fiji_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
 383 {
 384         /* Need to determine if we need calculated voltage. */
 385         return 0;
 386 }
 387
 388 static int fiji_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
 389 {
 390         /* Need to determine if we need calculated voltage from mm table. */
 391         return 0;
 392 }
 393
 394 static int fiji_sort_lookup_table(struct pp_hwmgr *hwmgr,
 395                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
 396 {
 397         uint32_t table_size, i, j;
 398         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
 399         table_size = lookup_table->count;
 400
 401         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
 402                 "Lookup table is empty", return -EINVAL);
 403
 404         /* Sorting voltages */
 405         for (i = 0; i < table_size - 1; i++) {
 406                 for (j = i + 1; j > 0; j--) {
 407                         if (lookup_table->entries[j].us_vdd <
 408                                         lookup_table->entries[j - 1].us_vdd) {
 409                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
 410                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
 411                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
 412                         }
 413                 }
 414         }
 415
 416         return 0;
 417 }
 418
 419 static int fiji_complete_dependency_tables(struct pp_hwmgr *hwmgr)
 420 {
 421         int result = 0;
 422         int tmp_result;
 423         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 424         struct phm_ppt_v1_information *table_info =
 425                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 426
 427         tmp_result = fiji_patch_lookup_table_with_leakage(hwmgr,
 428                         table_info->vddc_lookup_table, &(data->vddc_leakage));
 429         if (tmp_result)
 430                 result = tmp_result;
 431
 432         tmp_result = fiji_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
 433                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
 434         if (tmp_result)
 435                 result = tmp_result;
 436
 437         tmp_result = fiji_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
 438         if (tmp_result)
 439                 result = tmp_result;
 440
 441         tmp_result = fiji_calc_voltage_dependency_tables(hwmgr);
 442         if (tmp_result)
 443                 result = tmp_result;
 444
 445         tmp_result = fiji_calc_mm_voltage_dependency_table(hwmgr);
 446         if (tmp_result)
 447                 result = tmp_result;
 448
 449         tmp_result = fiji_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
 450         if(tmp_result)
 451                 result = tmp_result;
 452
 453         return result;
 454 }
 455
 456 static int fiji_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 457 {
 458         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 459         struct phm_ppt_v1_information *table_info =
 460                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 461
 462         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
 463                         table_info->vdd_dep_on_sclk;
 464         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
 465                         table_info->vdd_dep_on_mclk;
 466
 467         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
 468                 "VDD dependency on SCLK table is missing.       \
 469                 This table is mandatory", return -EINVAL);
 470         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
 471                 "VDD dependency on SCLK table has to have is missing.   \
 472                 This table is mandatory", return -EINVAL);
 473
 474         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
 475                 "VDD dependency on MCLK table is missing.       \
 476                 This table is mandatory", return -EINVAL);
 477         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
 478                 "VDD dependency on MCLK table has to have is missing.    \
 479                 This table is mandatory", return -EINVAL);
 480
 481         data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc;
 482         data->max_vddc_in_pptable =     (uint16_t)allowed_sclk_vdd_table->
 483                         entries[allowed_sclk_vdd_table->count - 1].vddc;
 484
 485         table_info->max_clock_voltage_on_ac.sclk =
 486                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
 487         table_info->max_clock_voltage_on_ac.mclk =
 488                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
 489         table_info->max_clock_voltage_on_ac.vddc =
 490                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
 491         table_info->max_clock_voltage_on_ac.vddci =
 492                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
 493
 494         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
 495                 table_info->max_clock_voltage_on_ac.sclk;
 496         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
 497                 table_info->max_clock_voltage_on_ac.mclk;
 498         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
 499                 table_info->max_clock_voltage_on_ac.vddc;
 500         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
 501                 table_info->max_clock_voltage_on_ac.vddci;
 502
 503         return 0;
 504 }
 505
 506 static uint16_t fiji_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 507 {
 508         uint32_t speedCntl = 0;
 509
 510         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 511         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
 512                         ixPCIE_LC_SPEED_CNTL);
 513         return((uint16_t)PHM_GET_FIELD(speedCntl,
 514                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 515 }
 516
 517 static int fiji_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 518 {
 519         uint32_t link_width;
 520
 521         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 522         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 523                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
 524
 525         PP_ASSERT_WITH_CODE((7 >= link_width),
 526                         "Invalid PCIe lane width!", return 0);
 527
 528         return decode_pcie_lane_width(link_width);
 529 }
 530
 531 /** Patch the Boot State to match VBIOS boot clocks and voltage.
 532 *
 533 * @param hwmgr Pointer to the hardware manager.
 534 * @param pPowerState The address of the PowerState instance being created.
 535 *
 536 */
 537 static int fiji_patch_boot_state(struct pp_hwmgr *hwmgr,
 538                 struct pp_hw_power_state *hw_ps)
 539 {
 540         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 541         struct fiji_power_state *ps = (struct fiji_power_state *)hw_ps;
 542         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
 543         uint16_t size;
 544         uint8_t frev, crev;
 545         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 546
 547         /* First retrieve the Boot clocks and VDDC from the firmware info table.
 548          * We assume here that fw_info is unchanged if this call fails.
 549          */
 550         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
 551                         hwmgr->device, index,
 552                         &size, &frev, &crev);
 553         if (!fw_info)
 554                 /* During a test, there is no firmware info table. */
 555                 return 0;
 556
 557         /* Patch the state. */
 558         data->vbios_boot_state.sclk_bootup_value =
 559                         le32_to_cpu(fw_info->ulDefaultEngineClock);
 560         data->vbios_boot_state.mclk_bootup_value =
 561                         le32_to_cpu(fw_info->ulDefaultMemoryClock);
 562         data->vbios_boot_state.mvdd_bootup_value =
 563                         le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
 564         data->vbios_boot_state.vddc_bootup_value =
 565                         le16_to_cpu(fw_info->usBootUpVDDCVoltage);
 566         data->vbios_boot_state.vddci_bootup_value =
 567                         le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
 568         data->vbios_boot_state.pcie_gen_bootup_value =
 569                         fiji_get_current_pcie_speed(hwmgr);
 570         data->vbios_boot_state.pcie_lane_bootup_value =
 571                         (uint16_t)fiji_get_current_pcie_lane_number(hwmgr);
 572
 573         /* set boot power state */
 574         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
 575         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
 576         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
 577         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
 578
 579         return 0;
 580 }
 581
 582 static int fiji_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 583 {
 584         return phm_hwmgr_backend_fini(hwmgr);
 585 }
 586
 587 static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 588 {
 589         struct fiji_hwmgr *data;
 590         uint32_t i;
 591         struct phm_ppt_v1_information *table_info =
 592                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 593         bool stay_in_boot;
 594         int result;
 595
 596         data = kzalloc(sizeof(struct fiji_hwmgr), GFP_KERNEL);
 597         if (data == NULL)
 598                 return -ENOMEM;
 599
 600         hwmgr->backend = data;
 601
 602         data->dll_default_on = false;
 603         data->sram_end = SMC_RAM_END;
 604
 605         for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
 606                 data->activity_target[i] = FIJI_AT_DFLT;
 607
 608         data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
 609
 610         data->mclk_activity_target = PPFIJI_MCLK_TARGETACTIVITY_DFLT;
 611         data->mclk_dpm0_activity_target = 0xa;
 612
 613         data->sclk_dpm_key_disabled = 0;
 614         data->mclk_dpm_key_disabled = 0;
 615         data->pcie_dpm_key_disabled = 0;
 616
 617         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 618                         PHM_PlatformCaps_UnTabledHardwareInterface);
 619         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 620                         PHM_PlatformCaps_TablelessHardwareInterface);
 621
 622         data->gpio_debug = 0;
 623
 624         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 625                         PHM_PlatformCaps_DynamicPatchPowerState);
 626
 627         /* need to set voltage control types before EVV patching */
 628         data->voltage_control = FIJI_VOLTAGE_CONTROL_NONE;
 629         data->vddci_control = FIJI_VOLTAGE_CONTROL_NONE;
 630         data->mvdd_control = FIJI_VOLTAGE_CONTROL_NONE;
 631
 632         data->force_pcie_gen = PP_PCIEGenInvalid;
 633
 634         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
 635                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
 636                 data->voltage_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
 637
 638         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 639                         PHM_PlatformCaps_EnableMVDDControl))
 640                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
 641                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
 642                         data->mvdd_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;
 643
 644         if (data->mvdd_control == FIJI_VOLTAGE_CONTROL_NONE)
 645                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 646                         PHM_PlatformCaps_EnableMVDDControl);
 647
 648         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 649                         PHM_PlatformCaps_ControlVDDCI)) {
 650                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
 651                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
 652                         data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;
 653                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
 654                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
 655                         data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
 656         }
 657
 658         if (data->vddci_control == FIJI_VOLTAGE_CONTROL_NONE)
 659                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 660                                 PHM_PlatformCaps_ControlVDDCI);
 661
 662         if (table_info && table_info->cac_dtp_table->usClockStretchAmount)
 663                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 664                                 PHM_PlatformCaps_ClockStretcher);
 665
 666         fiji_init_dpm_defaults(hwmgr);
 667
 668         /* Get leakage voltage based on leakage ID. */
 669         fiji_get_evv_voltages(hwmgr);
 670
 671         /* Patch our voltage dependency table with actual leakage voltage
 672          * We need to perform leakage translation before it's used by other functions
 673          */
 674         fiji_complete_dependency_tables(hwmgr);
 675
 676         /* Parse pptable data read from VBIOS */
 677         fiji_set_private_data_based_on_pptable(hwmgr);
 678
 679         /* ULV Support */
 680         data->ulv.ulv_supported = true; /* ULV feature is enabled by default */
 681
 682         /* Initalize Dynamic State Adjustment Rule Settings */
 683         result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
 684
 685         if (!result) {
 686                 data->uvd_enabled = false;
 687                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 688                                 PHM_PlatformCaps_EnableSMU7ThermalManagement);
 689                 data->vddc_phase_shed_control = false;
 690         }
 691
 692         stay_in_boot = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 693                         PHM_PlatformCaps_StayInBootState);
 694
 695         if (0 == result) {
 696                 struct cgs_system_info sys_info = {0};
 697
 698                 data->is_tlu_enabled = false;
 699                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 700                                 FIJI_MAX_HARDWARE_POWERLEVELS;
 701                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
 702                 hwmgr->platform_descriptor.minimumClocksReductionPercentage  = 50;
 703
 704                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 705                                 PHM_PlatformCaps_FanSpeedInTableIsRPM);
 706
 707                 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp &&
 708                                 hwmgr->thermal_controller.
 709                                 advanceFanControlParameters.ucFanControlMode) {
 710                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
 711                                         hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
 712                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
 713                                         hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
 714                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
 715                                         table_info->cac_dtp_table->usOperatingTempMinLimit;
 716                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
 717                                         table_info->cac_dtp_table->usOperatingTempMaxLimit;
 718                         hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
 719                                         table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
 720                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
 721                                         table_info->cac_dtp_table->usOperatingTempStep;
 722                         hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
 723                                         table_info->cac_dtp_table->usTargetOperatingTemp;
 724
 725                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 726                                         PHM_PlatformCaps_ODFuzzyFanControlSupport);
 727                 }
 728
 729                 sys_info.size = sizeof(struct cgs_system_info);
 730                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
 731                 result = cgs_query_system_info(hwmgr->device, &sys_info);
 732                 if (result)
 733                         data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;
 734                 else
 735                         data->pcie_gen_cap = (uint32_t)sys_info.value;
 736                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 737                         data->pcie_spc_cap = 20;
 738                 sys_info.size = sizeof(struct cgs_system_info);
 739                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
 740                 result = cgs_query_system_info(hwmgr->device, &sys_info);
 741                 if (result)
 742                         data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK;
 743                 else
 744                         data->pcie_lane_cap = (uint32_t)sys_info.value;
 745         } else {
 746                 /* Ignore return value in here, we are cleaning up a mess. */
 747                 fiji_hwmgr_backend_fini(hwmgr);
 748         }
 749
 750         return 0;
 751 }
 752
 753 /**
 754  * Read clock related registers.
 755  *
 756  * @param    hwmgr  the address of the powerplay hardware manager.
 757  * @return   always 0
 758  */
 759 static int fiji_read_clock_registers(struct pp_hwmgr *hwmgr)
 760 {
 761         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 762
 763         data->clock_registers.vCG_SPLL_FUNC_CNTL =
 764                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 765                                 ixCG_SPLL_FUNC_CNTL);
 766         data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
 767                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 768                                 ixCG_SPLL_FUNC_CNTL_2);
 769         data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
 770                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 771                                 ixCG_SPLL_FUNC_CNTL_3);
 772         data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
 773                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 774                                 ixCG_SPLL_FUNC_CNTL_4);
 775         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
 776                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 777                                 ixCG_SPLL_SPREAD_SPECTRUM);
 778         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
 779                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 780                                 ixCG_SPLL_SPREAD_SPECTRUM_2);
 781
 782         return 0;
 783 }
 784
 785 /**
 786  * Find out if memory is GDDR5.
 787  *
 788  * @param    hwmgr  the address of the powerplay hardware manager.
 789  * @return   always 0
 790  */
 791 static int fiji_get_memory_type(struct pp_hwmgr *hwmgr)
 792 {
 793         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 794         uint32_t temp;
 795
 796         temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
 797
 798         data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
 799                         ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
 800                          MC_SEQ_MISC0_GDDR5_SHIFT));
 801
 802         return 0;
 803 }
 804
 805 /**
 806  * Enables Dynamic Power Management by SMC
 807  *
 808  * @param    hwmgr  the address of the powerplay hardware manager.
 809  * @return   always 0
 810  */
 811 static int fiji_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
 812 {
 813         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 814                         GENERAL_PWRMGT, STATIC_PM_EN, 1);
 815
 816         return 0;
 817 }
 818
 819 /**
 820  * Initialize PowerGating States for different engines
 821  *
 822  * @param    hwmgr  the address of the powerplay hardware manager.
 823  * @return   always 0
 824  */
 825 static int fiji_init_power_gate_state(struct pp_hwmgr *hwmgr)
 826 {
 827         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 828
 829         data->uvd_power_gated = false;
 830         data->vce_power_gated = false;
 831         data->samu_power_gated = false;
 832         data->acp_power_gated = false;
 833         data->pg_acp_init = true;
 834
 835         return 0;
 836 }
 837
 838 static int fiji_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 839 {
 840         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 841         data->low_sclk_interrupt_threshold = 0;
 842
 843         return 0;
 844 }
 845
 846 static int fiji_setup_asic_task(struct pp_hwmgr *hwmgr)
 847 {
 848         int tmp_result, result = 0;
 849
 850         tmp_result = fiji_read_clock_registers(hwmgr);
 851         PP_ASSERT_WITH_CODE((0 == tmp_result),
 852                         "Failed to read clock registers!", result = tmp_result);
 853
 854         tmp_result = fiji_get_memory_type(hwmgr);
 855         PP_ASSERT_WITH_CODE((0 == tmp_result),
 856                         "Failed to get memory type!", result = tmp_result);
 857
 858         tmp_result = fiji_enable_acpi_power_management(hwmgr);
 859         PP_ASSERT_WITH_CODE((0 == tmp_result),
 860                         "Failed to enable ACPI power management!", result = tmp_result);
 861
 862         tmp_result = fiji_init_power_gate_state(hwmgr);
 863         PP_ASSERT_WITH_CODE((0 == tmp_result),
 864                         "Failed to init power gate state!", result = tmp_result);
 865
 866         tmp_result = tonga_get_mc_microcode_version(hwmgr);
 867         PP_ASSERT_WITH_CODE((0 == tmp_result),
 868                         "Failed to get MC microcode version!", result = tmp_result);
 869
 870         tmp_result = fiji_init_sclk_threshold(hwmgr);
 871         PP_ASSERT_WITH_CODE((0 == tmp_result),
 872                         "Failed to init sclk threshold!", result = tmp_result);
 873
 874         return result;
 875 }
 876
 877 /**
 878 * Checks if we want to support voltage control
 879 *
 880 * @param    hwmgr  the address of the powerplay hardware manager.
 881 */
 882 static bool fiji_voltage_control(const struct pp_hwmgr *hwmgr)
 883 {
 884         const struct fiji_hwmgr *data =
 885                         (const struct fiji_hwmgr *)(hwmgr->backend);
 886
 887         return (FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control);
 888 }
 889
 890 /**
 891 * Enable voltage control
 892 *
 893 * @param    hwmgr  the address of the powerplay hardware manager.
 894 * @return   always 0
 895 */
 896 static int fiji_enable_voltage_control(struct pp_hwmgr *hwmgr)
 897 {
 898         /* enable voltage control */
 899         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 900                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 901
 902         return 0;
 903 }
 904
 905 /**
 906 * Remove repeated voltage values and create table with unique values.
 907 *
 908 * @param    hwmgr  the address of the powerplay hardware manager.
 909 * @param    vol_table  the pointer to changing voltage table
 910 * @return    0 in success
 911 */
 912
 913 static int fiji_trim_voltage_table(struct pp_hwmgr *hwmgr,
 914                 struct pp_atomctrl_voltage_table *vol_table)
 915 {
 916         uint32_t i, j;
 917         uint16_t vvalue;
 918         bool found = false;
 919         struct pp_atomctrl_voltage_table *table;
 920
 921         PP_ASSERT_WITH_CODE((NULL != vol_table),
 922                         "Voltage Table empty.", return -EINVAL);
 923         table = kzalloc(sizeof(struct pp_atomctrl_voltage_table),
 924                         GFP_KERNEL);
 925
 926         if (NULL == table)
 927                 return -ENOMEM;
 928
 929         table->mask_low = vol_table->mask_low;
 930         table->phase_delay = vol_table->phase_delay;
 931
 932         for (i = 0; i < vol_table->count; i++) {
 933                 vvalue = vol_table->entries[i].value;
 934                 found = false;
 935
 936                 for (j = 0; j < table->count; j++) {
 937                         if (vvalue == table->entries[j].value) {
 938                                 found = true;
 939                                 break;
 940                         }
 941                 }
 942
 943                 if (!found) {
 944                         table->entries[table->count].value = vvalue;
 945                         table->entries[table->count].smio_low =
 946                                         vol_table->entries[i].smio_low;
 947                         table->count++;
 948                 }
 949         }
 950
 951         memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
 952         kfree(table);
 953
 954         return 0;
 955 }
 956
 957 static int fiji_get_svi2_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
 958                 phm_ppt_v1_clock_voltage_dependency_table *dep_table)
 959 {
 960         uint32_t i;
 961         int result;
 962         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 963         struct pp_atomctrl_voltage_table *vol_table = &(data->mvdd_voltage_table);
 964
 965         PP_ASSERT_WITH_CODE((0 != dep_table->count),
 966                         "Voltage Dependency Table empty.", return -EINVAL);
 967
 968         vol_table->mask_low = 0;
 969         vol_table->phase_delay = 0;
 970         vol_table->count = dep_table->count;
 971
 972         for (i = 0; i < dep_table->count; i++) {
 973                 vol_table->entries[i].value = dep_table->entries[i].mvdd;
 974                 vol_table->entries[i].smio_low = 0;
 975         }
 976
 977         result = fiji_trim_voltage_table(hwmgr, vol_table);
 978         PP_ASSERT_WITH_CODE((0 == result),
 979                         "Failed to trim MVDD table.", return result);
 980
 981         return 0;
 982 }
 983
 984 static int fiji_get_svi2_vddci_voltage_table(struct pp_hwmgr *hwmgr,
 985                 phm_ppt_v1_clock_voltage_dependency_table *dep_table)
 986 {
 987         uint32_t i;
 988         int result;
 989         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 990         struct pp_atomctrl_voltage_table *vol_table = &(data->vddci_voltage_table);
 991
 992         PP_ASSERT_WITH_CODE((0 != dep_table->count),
 993                         "Voltage Dependency Table empty.", return -EINVAL);
 994
 995         vol_table->mask_low = 0;
 996         vol_table->phase_delay = 0;
 997         vol_table->count = dep_table->count;
 998
 999         for (i = 0; i < dep_table->count; i++) {
1000                 vol_table->entries[i].value = dep_table->entries[i].vddci;
1001                 vol_table->entries[i].smio_low = 0;
1002         }
1003
1004         result = fiji_trim_voltage_table(hwmgr, vol_table);
1005         PP_ASSERT_WITH_CODE((0 == result),
1006                         "Failed to trim VDDCI table.", return result);
1007
1008         return 0;
1009 }
1010
1011 static int fiji_get_svi2_vdd_voltage_table(struct pp_hwmgr *hwmgr,
1012                 phm_ppt_v1_voltage_lookup_table *lookup_table)
1013 {
1014         int i = 0;
1015         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1016         struct pp_atomctrl_voltage_table *vol_table = &(data->vddc_voltage_table);
1017
1018         PP_ASSERT_WITH_CODE((0 != lookup_table->count),
1019                         "Voltage Lookup Table empty.", return -EINVAL);
1020
1021         vol_table->mask_low = 0;
1022         vol_table->phase_delay = 0;
1023
1024         vol_table->count = lookup_table->count;
1025
1026         for (i = 0; i < vol_table->count; i++) {
1027                 vol_table->entries[i].value = lookup_table->entries[i].us_vdd;
1028                 vol_table->entries[i].smio_low = 0;
1029         }
1030
1031         return 0;
1032 }
1033
1034 /* ---- Voltage Tables ----
1035  * If the voltage table would be bigger than
1036  * what will fit into the state table on
1037  * the SMC keep only the higher entries.
1038  */
1039 static void fiji_trim_voltage_table_to_fit_state_table(struct pp_hwmgr *hwmgr,
1040                 uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table)
1041 {
1042         unsigned int i, diff;
1043
1044         if (vol_table->count <= max_vol_steps)
1045                 return;
1046
1047         diff = vol_table->count - max_vol_steps;
1048
1049         for (i = 0; i < max_vol_steps; i++)
1050                 vol_table->entries[i] = vol_table->entries[i + diff];
1051
1052         vol_table->count = max_vol_steps;
1053
1054         return;
1055 }
1056
1057 /**
1058 * Create Voltage Tables.
1059 *
1060 * @param    hwmgr  the address of the powerplay hardware manager.
1061 * @return   always 0
1062 */
1063 static int fiji_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1064 {
1065         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1066         struct phm_ppt_v1_information *table_info =
1067                         (struct phm_ppt_v1_information *)hwmgr->pptable;
1068         int result;
1069
1070         if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1071                 result = atomctrl_get_voltage_table_v3(hwmgr,
1072                                 VOLTAGE_TYPE_MVDDC,     VOLTAGE_OBJ_GPIO_LUT,
1073                                 &(data->mvdd_voltage_table));
1074                 PP_ASSERT_WITH_CODE((0 == result),
1075                                 "Failed to retrieve MVDD table.",
1076                                 return result);
1077         } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1078                 result = fiji_get_svi2_mvdd_voltage_table(hwmgr,
1079                                 table_info->vdd_dep_on_mclk);
1080                 PP_ASSERT_WITH_CODE((0 == result),
1081                                 "Failed to retrieve SVI2 MVDD table from dependancy table.",
1082                                 return result;);
1083         }
1084
1085         if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1086                 result = atomctrl_get_voltage_table_v3(hwmgr,
1087                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
1088                                 &(data->vddci_voltage_table));
1089                 PP_ASSERT_WITH_CODE((0 == result),
1090                                 "Failed to retrieve VDDCI table.",
1091                                 return result);
1092         } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1093                 result = fiji_get_svi2_vddci_voltage_table(hwmgr,
1094                                 table_info->vdd_dep_on_mclk);
1095                 PP_ASSERT_WITH_CODE((0 == result),
1096                                 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
1097                                 return result);
1098         }
1099
1100         if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1101                 result = fiji_get_svi2_vdd_voltage_table(hwmgr,
1102                                 table_info->vddc_lookup_table);
1103                 PP_ASSERT_WITH_CODE((0 == result),
1104                                 "Failed to retrieve SVI2 VDDC table from lookup table.",
1105                                 return result);
1106         }
1107
1108         PP_ASSERT_WITH_CODE(
1109                         (data->vddc_voltage_table.count <= (SMU73_MAX_LEVELS_VDDC)),
1110                         "Too many voltage values for VDDC. Trimming to fit state table.",
1111                         fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1112                                         SMU73_MAX_LEVELS_VDDC, &(data->vddc_voltage_table)));
1113
1114         PP_ASSERT_WITH_CODE(
1115                         (data->vddci_voltage_table.count <= (SMU73_MAX_LEVELS_VDDCI)),
1116                         "Too many voltage values for VDDCI. Trimming to fit state table.",
1117                         fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1118                                         SMU73_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table)));
1119
1120         PP_ASSERT_WITH_CODE(
1121                         (data->mvdd_voltage_table.count <= (SMU73_MAX_LEVELS_MVDD)),
1122                         "Too many voltage values for MVDD. Trimming to fit state table.",
1123                         fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1124                                         SMU73_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table)));
1125
1126         return 0;
1127 }
1128
1129 static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
1130 {
1131         /* Program additional LP registers
1132          * that are no longer programmed by VBIOS
1133          */
1134         cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
1135                         cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
1136         cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
1137                         cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
1138         cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
1139                         cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
1140         cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
1141                         cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
1142         cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
1143                         cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
1144         cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
1145                         cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
1146         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
1147                         cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
1148
1149         return 0;
1150 }
1151
1152 /**
1153 * Programs static screed detection parameters
1154 *
1155 * @param    hwmgr  the address of the powerplay hardware manager.
1156 * @return   always 0
1157 */
1158 static int fiji_program_static_screen_threshold_parameters(
1159                 struct pp_hwmgr *hwmgr)
1160 {
1161         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1162
1163         /* Set static screen threshold unit */
1164         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1165                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
1166                         data->static_screen_threshold_unit);
1167         /* Set static screen threshold */
1168         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1169                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
1170                         data->static_screen_threshold);
1171
1172         return 0;
1173 }
1174
1175 /**
1176 * Setup display gap for glitch free memory clock switching.
1177 *
1178 * @param    hwmgr  the address of the powerplay hardware manager.
1179 * @return   always  0
1180 */
1181 static int fiji_enable_display_gap(struct pp_hwmgr *hwmgr)
1182 {
1183         uint32_t displayGap =
1184                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1185                                         ixCG_DISPLAY_GAP_CNTL);
1186
1187         displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
1188                         DISP_GAP, DISPLAY_GAP_IGNORE);
1189
1190         displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
1191                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
1192
1193         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1194                         ixCG_DISPLAY_GAP_CNTL, displayGap);
1195
1196         return 0;
1197 }
1198
1199 /**
1200 * Programs activity state transition voting clients
1201 *
1202 * @param    hwmgr  the address of the powerplay hardware manager.
1203 * @return   always  0
1204 */
1205 static int fiji_program_voting_clients(struct pp_hwmgr *hwmgr)
1206 {
1207         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1208
1209         /* Clear reset for voting clients before enabling DPM */
1210         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1211                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
1212         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1213                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
1214
1215         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1216                         ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
1217         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1218                         ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
1219         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1220                         ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
1221         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1222                         ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
1223         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1224                         ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
1225         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1226                         ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
1227         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1228                         ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
1229         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1230                         ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
1231
1232         return 0;
1233 }
1234
1235 static int fiji_clear_voting_clients(struct pp_hwmgr *hwmgr)
1236 {
1237         /* Reset voting clients before disabling DPM */
1238         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1239                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
1240         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1241                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
1242
1243         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1244                         ixCG_FREQ_TRAN_VOTING_0, 0);
1245         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1246                         ixCG_FREQ_TRAN_VOTING_1, 0);
1247         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1248                         ixCG_FREQ_TRAN_VOTING_2, 0);
1249         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1250                         ixCG_FREQ_TRAN_VOTING_3, 0);
1251         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1252                         ixCG_FREQ_TRAN_VOTING_4, 0);
1253         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1254                         ixCG_FREQ_TRAN_VOTING_5, 0);
1255         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1256                         ixCG_FREQ_TRAN_VOTING_6, 0);
1257         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1258                         ixCG_FREQ_TRAN_VOTING_7, 0);
1259
1260         return 0;
1261 }
1262
1263 /**
1264 * Get the location of various tables inside the FW image.
1265 *
1266 * @param    hwmgr  the address of the powerplay hardware manager.
1267 * @return   always  0
1268 */
1269 static int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
1270 {
1271         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1272         struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
1273         uint32_t tmp;
1274         int result;
1275         bool error = false;
1276
1277         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1278                         SMU7_FIRMWARE_HEADER_LOCATION +
1279                         offsetof(SMU73_Firmware_Header, DpmTable),
1280                         &tmp, data->sram_end);
1281
1282         if (0 == result)
1283                 data->dpm_table_start = tmp;
1284
1285         error |= (0 != result);
1286
1287         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1288                         SMU7_FIRMWARE_HEADER_LOCATION +
1289                         offsetof(SMU73_Firmware_Header, SoftRegisters),
1290                         &tmp, data->sram_end);
1291
1292         if (!result) {
1293                 data->soft_regs_start = tmp;
1294                 smu_data->soft_regs_start = tmp;
1295         }
1296
1297         error |= (0 != result);
1298
1299         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1300                         SMU7_FIRMWARE_HEADER_LOCATION +
1301                         offsetof(SMU73_Firmware_Header, mcRegisterTable),
1302                         &tmp, data->sram_end);
1303
1304         if (!result)
1305                 data->mc_reg_table_start = tmp;
1306
1307         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1308                         SMU7_FIRMWARE_HEADER_LOCATION +
1309                         offsetof(SMU73_Firmware_Header, FanTable),
1310                         &tmp, data->sram_end);
1311
1312         if (!result)
1313                 data->fan_table_start = tmp;
1314
1315         error |= (0 != result);
1316
1317         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1318                         SMU7_FIRMWARE_HEADER_LOCATION +
1319                         offsetof(SMU73_Firmware_Header, mcArbDramTimingTable),
1320                         &tmp, data->sram_end);
1321
1322         if (!result)
1323                 data->arb_table_start = tmp;
1324
1325         error |= (0 != result);
1326
1327         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1328                         SMU7_FIRMWARE_HEADER_LOCATION +
1329                         offsetof(SMU73_Firmware_Header, Version),
1330                         &tmp, data->sram_end);
1331
1332         if (!result)
1333                 hwmgr->microcode_version_info.SMC = tmp;
1334
1335         error |= (0 != result);
1336
1337         return error ? -1 : 0;
1338 }
1339
1340 /* Copy one arb setting to another and then switch the active set.
1341  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
1342  */
1343 static int fiji_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
1344                 uint32_t arb_src, uint32_t arb_dest)
1345 {
1346         uint32_t mc_arb_dram_timing;
1347         uint32_t mc_arb_dram_timing2;
1348         uint32_t burst_time;
1349         uint32_t mc_cg_config;
1350
1351         switch (arb_src) {
1352         case MC_CG_ARB_FREQ_F0:
1353                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1354                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1355                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1356                 break;
1357         case MC_CG_ARB_FREQ_F1:
1358                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
1359                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
1360                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
1361                 break;
1362         default:
1363                 return -EINVAL;
1364         }
1365
1366         switch (arb_dest) {
1367         case MC_CG_ARB_FREQ_F0:
1368                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
1369                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
1370                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
1371                 break;
1372         case MC_CG_ARB_FREQ_F1:
1373                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
1374                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
1375                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
1376                 break;
1377         default:
1378                 return -EINVAL;
1379         }
1380
1381         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
1382         mc_cg_config |= 0x0000000F;
1383         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
1384         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
1385
1386         return 0;
1387 }
1388
1389 /**
1390 * Call SMC to reset S0/S1 to S1 and Reset SMIO to initial value
1391 *
1392 * @param    hwmgr  the address of the powerplay hardware manager.
1393 * @return   if success then 0;
1394 */
1395 static int fiji_reset_to_default(struct pp_hwmgr *hwmgr)
1396 {
1397         return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults);
1398 }
1399
1400 /**
1401 * Initial switch from ARB F0->F1
1402 *
1403 * @param    hwmgr  the address of the powerplay hardware manager.
1404 * @return   always 0
1405 * This function is to be called from the SetPowerState table.
1406 */
1407 static int fiji_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
1408 {
1409         return fiji_copy_and_switch_arb_sets(hwmgr,
1410                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
1411 }
1412
1413 static int fiji_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
1414 {
1415         uint32_t tmp;
1416
1417         tmp = (cgs_read_ind_register(hwmgr->device,
1418                         CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
1419                         0x0000ff00) >> 8;
1420
1421         if (tmp == MC_CG_ARB_FREQ_F0)
1422                 return 0;
1423
1424         return fiji_copy_and_switch_arb_sets(hwmgr,
1425                         tmp, MC_CG_ARB_FREQ_F0);
1426 }
1427
1428 static int fiji_reset_single_dpm_table(struct pp_hwmgr *hwmgr,
1429                 struct fiji_single_dpm_table *dpm_table, uint32_t count)
1430 {
1431         int i;
1432         PP_ASSERT_WITH_CODE(count <= MAX_REGULAR_DPM_NUMBER,
1433                         "Fatal error, can not set up single DPM table entries "
1434                         "to exceed max number!",);
1435
1436         dpm_table->count = count;
1437         for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
1438                 dpm_table->dpm_levels[i].enabled = false;
1439
1440         return 0;
1441 }
1442
1443 static void fiji_setup_pcie_table_entry(
1444         struct fiji_single_dpm_table *dpm_table,
1445         uint32_t index, uint32_t pcie_gen,
1446         uint32_t pcie_lanes)
1447 {
1448         dpm_table->dpm_levels[index].value = pcie_gen;
1449         dpm_table->dpm_levels[index].param1 = pcie_lanes;
1450         dpm_table->dpm_levels[index].enabled = true;
1451 }
1452
1453 static int fiji_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
1454 {
1455         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1456         struct phm_ppt_v1_information *table_info =
1457                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1458         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1459         uint32_t i, max_entry;
1460
1461         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
1462                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
1463                         return -EINVAL);
1464
1465         if (data->use_pcie_performance_levels &&
1466                         !data->use_pcie_power_saving_levels) {
1467                 data->pcie_gen_power_saving = data->pcie_gen_performance;
1468                 data->pcie_lane_power_saving = data->pcie_lane_performance;
1469         } else if (!data->use_pcie_performance_levels &&
1470                         data->use_pcie_power_saving_levels) {
1471                 data->pcie_gen_performance = data->pcie_gen_power_saving;
1472                 data->pcie_lane_performance = data->pcie_lane_power_saving;
1473         }
1474
1475         fiji_reset_single_dpm_table(hwmgr,
1476                         &data->dpm_table.pcie_speed_table, SMU73_MAX_LEVELS_LINK);
1477
1478         if (pcie_table != NULL) {
1479                 /* max_entry is used to make sure we reserve one PCIE level
1480                  * for boot level (fix for A+A PSPP issue).
1481                  * If PCIE table from PPTable have ULV entry + 8 entries,
1482                  * then ignore the last entry.*/
1483                 max_entry = (SMU73_MAX_LEVELS_LINK < pcie_table->count) ?
1484                                 SMU73_MAX_LEVELS_LINK : pcie_table->count;
1485                 for (i = 1; i < max_entry; i++) {
1486                         fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
1487                                         get_pcie_gen_support(data->pcie_gen_cap,
1488                                                         pcie_table->entries[i].gen_speed),
1489                                         get_pcie_lane_support(data->pcie_lane_cap,
1490                                                         pcie_table->entries[i].lane_width));
1491                 }
1492                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
1493         } else {
1494                 /* Hardcode Pcie Table */
1495                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
1496                                 get_pcie_gen_support(data->pcie_gen_cap,
1497                                                 PP_Min_PCIEGen),
1498                                 get_pcie_lane_support(data->pcie_lane_cap,
1499                                                 PP_Max_PCIELane));
1500                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
1501                                 get_pcie_gen_support(data->pcie_gen_cap,
1502                                                 PP_Min_PCIEGen),
1503                                 get_pcie_lane_support(data->pcie_lane_cap,
1504                                                 PP_Max_PCIELane));
1505                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
1506                                 get_pcie_gen_support(data->pcie_gen_cap,
1507                                                 PP_Max_PCIEGen),
1508                                 get_pcie_lane_support(data->pcie_lane_cap,
1509                                                 PP_Max_PCIELane));
1510                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
1511                                 get_pcie_gen_support(data->pcie_gen_cap,
1512                                                 PP_Max_PCIEGen),
1513                                 get_pcie_lane_support(data->pcie_lane_cap,
1514                                                 PP_Max_PCIELane));
1515                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
1516                                 get_pcie_gen_support(data->pcie_gen_cap,
1517                                                 PP_Max_PCIEGen),
1518                                 get_pcie_lane_support(data->pcie_lane_cap,
1519                                                 PP_Max_PCIELane));
1520                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
1521                                 get_pcie_gen_support(data->pcie_gen_cap,
1522                                                 PP_Max_PCIEGen),
1523                                 get_pcie_lane_support(data->pcie_lane_cap,
1524                                                 PP_Max_PCIELane));
1525
1526                 data->dpm_table.pcie_speed_table.count = 6;
1527         }
1528         /* Populate last level for boot PCIE level, but do not increment count. */
1529         fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
1530                         data->dpm_table.pcie_speed_table.count,
1531                         get_pcie_gen_support(data->pcie_gen_cap,
1532                                         PP_Min_PCIEGen),
1533                         get_pcie_lane_support(data->pcie_lane_cap,
1534                                         PP_Max_PCIELane));
1535
1536         return 0;
1537 }
1538
1539 /*
1540  * This function is to initalize all DPM state tables
1541  * for SMU7 based on the dependency table.
1542  * Dynamic state patching function will then trim these
1543  * state tables to the allowed range based
1544  * on the power policy or external client requests,
1545  * such as UVD request, etc.
1546  */
1547 static int fiji_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1548 {
1549         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1550         struct phm_ppt_v1_information *table_info =
1551                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1552         uint32_t i;
1553
1554         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
1555                         table_info->vdd_dep_on_sclk;
1556         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
1557                         table_info->vdd_dep_on_mclk;
1558
1559         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
1560                         "SCLK dependency table is missing. This table is mandatory",
1561                         return -EINVAL);
1562         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
1563                         "SCLK dependency table has to have is missing. "
1564                         "This table is mandatory",
1565                         return -EINVAL);
1566
1567         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
1568                         "MCLK dependency table is missing. This table is mandatory",
1569                         return -EINVAL);
1570         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
1571                         "MCLK dependency table has to have is missing. "
1572                         "This table is mandatory",
1573                         return -EINVAL);
1574
1575         /* clear the state table to reset everything to default */
1576         fiji_reset_single_dpm_table(hwmgr,
1577                         &data->dpm_table.sclk_table, SMU73_MAX_LEVELS_GRAPHICS);
1578         fiji_reset_single_dpm_table(hwmgr,
1579                         &data->dpm_table.mclk_table, SMU73_MAX_LEVELS_MEMORY);
1580
1581         /* Initialize Sclk DPM table based on allow Sclk values */
1582         data->dpm_table.sclk_table.count = 0;
1583         for (i = 0; i < dep_sclk_table->count; i++) {
1584                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels
1585                                 [data->dpm_table.sclk_table.count - 1].value !=
1586                                                 dep_sclk_table->entries[i].clk) {
1587                         data->dpm_table.sclk_table.dpm_levels
1588                         [data->dpm_table.sclk_table.count].value =
1589                                         dep_sclk_table->entries[i].clk;
1590                         data->dpm_table.sclk_table.dpm_levels
1591                         [data->dpm_table.sclk_table.count].enabled =
1592                                         (i == 0) ? true : false;
1593                         data->dpm_table.sclk_table.count++;
1594                 }
1595         }
1596
1597         /* Initialize Mclk DPM table based on allow Mclk values */
1598         data->dpm_table.mclk_table.count = 0;
1599         for (i=0; i<dep_mclk_table->count; i++) {
1600                 if ( i==0 || data->dpm_table.mclk_table.dpm_levels
1601                                 [data->dpm_table.mclk_table.count - 1].value !=
1602                                                 dep_mclk_table->entries[i].clk) {
1603                         data->dpm_table.mclk_table.dpm_levels
1604                         [data->dpm_table.mclk_table.count].value =
1605                                         dep_mclk_table->entries[i].clk;
1606                         data->dpm_table.mclk_table.dpm_levels
1607                         [data->dpm_table.mclk_table.count].enabled =
1608                                         (i == 0) ? true : false;
1609                         data->dpm_table.mclk_table.count++;
1610                 }
1611         }
1612
1613         /* setup PCIE gen speed levels */
1614         fiji_setup_default_pcie_table(hwmgr);
1615
1616         /* save a copy of the default DPM table */
1617         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1618                         sizeof(struct fiji_dpm_table));
1619
1620         return 0;
1621 }
1622
1623 /**
1624  * @brief PhwFiji_GetVoltageOrder
1625  *  Returns index of requested voltage record in lookup(table)
1626  * @param lookup_table - lookup list to search in
1627  * @param voltage - voltage to look for
1628  * @return 0 on success
1629  */
1630 static uint8_t fiji_get_voltage_index(
1631                 struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage)
1632 {
1633         uint8_t count = (uint8_t) (lookup_table->count);
1634         uint8_t i;
1635
1636         PP_ASSERT_WITH_CODE((NULL != lookup_table),
1637                         "Lookup Table empty.", return 0);
1638         PP_ASSERT_WITH_CODE((0 != count),
1639                         "Lookup Table empty.", return 0);
1640
1641         for (i = 0; i < lookup_table->count; i++) {
1642                 /* find first voltage equal or bigger than requested */
1643                 if (lookup_table->entries[i].us_vdd >= voltage)
1644                         return i;
1645         }
1646         /* voltage is bigger than max voltage in the table */
1647         return i - 1;
1648 }
1649
1650 /**
1651 * Preparation of vddc and vddgfx CAC tables for SMC.
1652 *
1653 * @param    hwmgr  the address of the hardware manager
1654 * @param    table  the SMC DPM table structure to be populated
1655 * @return   always 0
1656 */
1657 static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr,
1658                 struct SMU73_Discrete_DpmTable *table)
1659 {
1660         uint32_t count;
1661         uint8_t index;
1662         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1663         struct phm_ppt_v1_information *table_info =
1664                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1665         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
1666                         table_info->vddc_lookup_table;
1667         /* tables is already swapped, so in order to use the value from it,
1668          * we need to swap it back.
1669          * We are populating vddc CAC data to BapmVddc table
1670          * in split and merged mode
1671          */
1672         for( count = 0; count<lookup_table->count; count++) {
1673                 index = fiji_get_voltage_index(lookup_table,
1674                                 data->vddc_voltage_table.entries[count].value);
1675                 table->BapmVddcVidLoSidd[count] = (uint8_t) ((6200 -
1676                                 (lookup_table->entries[index].us_cac_low *
1677                                                 VOLTAGE_SCALE)) / 25);
1678                 table->BapmVddcVidHiSidd[count] = (uint8_t) ((6200 -
1679                                 (lookup_table->entries[index].us_cac_high *
1680                                                 VOLTAGE_SCALE)) / 25);
1681         }
1682
1683         return 0;
1684 }
1685
1686 /**
1687 * Preparation of voltage tables for SMC.
1688 *
1689 * @param    hwmgr   the address of the hardware manager
1690 * @param    table   the SMC DPM table structure to be populated
1691 * @return   always  0
1692 */
1693
1694 static int fiji_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
1695                 struct SMU73_Discrete_DpmTable *table)
1696 {
1697         int result;
1698
1699         result = fiji_populate_cac_table(hwmgr, table);
1700         PP_ASSERT_WITH_CODE(0 == result,
1701                         "can not populate CAC voltage tables to SMC",
1702                         return -EINVAL);
1703
1704         return 0;
1705 }
1706
1707 static int fiji_populate_ulv_level(struct pp_hwmgr *hwmgr,
1708                 struct SMU73_Discrete_Ulv *state)
1709 {
1710         int result = 0;
1711         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1712         struct phm_ppt_v1_information *table_info =
1713                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1714
1715         state->CcPwrDynRm = 0;
1716         state->CcPwrDynRm1 = 0;
1717
1718         state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
1719         state->VddcOffsetVid = (uint8_t)( table_info->us_ulv_voltage_offset *
1720                         VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1 );
1721
1722         state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
1723
1724         if (!result) {
1725                 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
1726                 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
1727                 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
1728         }
1729         return result;
1730 }
1731
1732 static int fiji_populate_ulv_state(struct pp_hwmgr *hwmgr,
1733                 struct SMU73_Discrete_DpmTable *table)
1734 {
1735         return fiji_populate_ulv_level(hwmgr, &table->Ulv);
1736 }
1737
1738 static int32_t fiji_get_dpm_level_enable_mask_value(
1739                 struct fiji_single_dpm_table* dpm_table)
1740 {
1741         int32_t i;
1742         int32_t mask = 0;
1743
1744         for (i = dpm_table->count; i > 0; i--) {
1745                 mask = mask << 1;
1746                 if (dpm_table->dpm_levels[i - 1].enabled)
1747                         mask |= 0x1;
1748                 else
1749                         mask &= 0xFFFFFFFE;
1750         }
1751         return mask;
1752 }
1753
1754 static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr,
1755                 struct SMU73_Discrete_DpmTable *table)
1756 {
1757         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1758         struct fiji_dpm_table *dpm_table = &data->dpm_table;
1759         int i;
1760
1761         /* Index (dpm_table->pcie_speed_table.count)
1762          * is reserved for PCIE boot level. */
1763         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1764                 table->LinkLevel[i].PcieGenSpeed  =
1765                                 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1766                 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
1767                                 dpm_table->pcie_speed_table.dpm_levels[i].param1);
1768                 table->LinkLevel[i].EnabledForActivity = 1;
1769                 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
1770                 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
1771                 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
1772         }
1773
1774         data->smc_state_table.LinkLevelCount =
1775                         (uint8_t)dpm_table->pcie_speed_table.count;
1776         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1777                         fiji_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1778
1779         return 0;
1780 }
1781
1782 /**
1783 * Calculates the SCLK dividers using the provided engine clock
1784 *
1785 * @param    hwmgr  the address of the hardware manager
1786 * @param    clock  the engine clock to use to populate the structure
1787 * @param    sclk   the SMC SCLK structure to be populated
1788 */
1789 static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr,
1790                 uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk)
1791 {
1792         const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1793         struct pp_atomctrl_clock_dividers_vi dividers;
1794         uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1795         uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1796         uint32_t spll_func_cntl_4          = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
1797         uint32_t cg_spll_spread_spectrum   = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
1798         uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
1799         uint32_t ref_clock;
1800         uint32_t ref_divider;
1801         uint32_t fbdiv;
1802         int result;
1803
1804         /* get the engine clock dividers for this clock value */
1805         result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock,  &dividers);
1806
1807         PP_ASSERT_WITH_CODE(result == 0,
1808                         "Error retrieving Engine Clock dividers from VBIOS.",
1809                         return result);
1810
1811         /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
1812         ref_clock = atomctrl_get_reference_clock(hwmgr);
1813         ref_divider = 1 + dividers.uc_pll_ref_div;
1814
1815         /* low 14 bits is fraction and high 12 bits is divider */
1816         fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
1817
1818         /* SPLL_FUNC_CNTL setup */
1819         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1820                         SPLL_REF_DIV, dividers.uc_pll_ref_div);
1821         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1822                         SPLL_PDIV_A,  dividers.uc_pll_post_div);
1823
1824         /* SPLL_FUNC_CNTL_3 setup*/
1825         spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
1826                         SPLL_FB_DIV, fbdiv);
1827
1828         /* set to use fractional accumulation*/
1829         spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
1830                         SPLL_DITHEN, 1);
1831
1832         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1833                                 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
1834                 struct pp_atomctrl_internal_ss_info ssInfo;
1835
1836                 uint32_t vco_freq = clock * dividers.uc_pll_post_div;
1837                 if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
1838                                 vco_freq, &ssInfo)) {
1839                         /*
1840                          * ss_info.speed_spectrum_percentage -- in unit of 0.01%
1841                          * ss_info.speed_spectrum_rate -- in unit of khz
1842                          *
1843                          * clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2
1844                          */
1845                         uint32_t clk_s = ref_clock * 5 /
1846                                         (ref_divider * ssInfo.speed_spectrum_rate);
1847                         /* clkv = 2 * D * fbdiv / NS */
1848                         uint32_t clk_v = 4 * ssInfo.speed_spectrum_percentage *
1849                                         fbdiv / (clk_s * 10000);
1850
1851                         cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
1852                                         CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
1853                         cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
1854                                         CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
1855                         cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2,
1856                                         CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
1857                 }
1858         }
1859
1860         sclk->SclkFrequency        = clock;
1861         sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
1862         sclk->CgSpllFuncCntl4      = spll_func_cntl_4;
1863         sclk->SpllSpreadSpectrum   = cg_spll_spread_spectrum;
1864         sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
1865         sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
1866
1867         return 0;
1868 }
1869
1870 static uint16_t fiji_find_closest_vddci(struct pp_hwmgr *hwmgr, uint16_t vddci)
1871 {
1872         uint32_t  i;
1873         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1874         struct pp_atomctrl_voltage_table *vddci_table =
1875                         &(data->vddci_voltage_table);
1876
1877         for (i = 0; i < vddci_table->count; i++) {
1878                 if (vddci_table->entries[i].value >= vddci)
1879                         return vddci_table->entries[i].value;
1880         }
1881
1882         PP_ASSERT_WITH_CODE(false,
1883                         "VDDCI is larger than max VDDCI in VDDCI Voltage Table!",
1884                         return vddci_table->entries[i-1].value);
1885 }
1886
1887 static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
1888                 struct phm_ppt_v1_clock_voltage_dependency_table* dep_table,
1889                 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1890 {
1891         uint32_t i;
1892         uint16_t vddci;
1893         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1894
1895         *voltage = *mvdd = 0;
1896
1897         /* clock - voltage dependency table is empty table */
1898         if (dep_table->count == 0)
1899                 return -EINVAL;
1900
1901         for (i = 0; i < dep_table->count; i++) {
1902                 /* find first sclk bigger than request */
1903                 if (dep_table->entries[i].clk >= clock) {
1904                         *voltage |= (dep_table->entries[i].vddc *
1905                                         VOLTAGE_SCALE) << VDDC_SHIFT;
1906                         if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
1907                                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1908                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1909                         else if (dep_table->entries[i].vddci)
1910                                 *voltage |= (dep_table->entries[i].vddci *
1911                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1912                         else {
1913                                 vddci = fiji_find_closest_vddci(hwmgr,
1914                                                 (dep_table->entries[i].vddc -
1915                                                                 (uint16_t)data->vddc_vddci_delta));
1916                                 *voltage |= (vddci * VOLTAGE_SCALE) <<  VDDCI_SHIFT;
1917                         }
1918
1919                         if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1920                                 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1921                                         VOLTAGE_SCALE;
1922                         else if (dep_table->entries[i].mvdd)
1923                                 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1924                                         VOLTAGE_SCALE;
1925
1926                         *voltage |= 1 << PHASES_SHIFT;
1927                         return 0;
1928                 }
1929         }
1930
1931         /* sclk is bigger than max sclk in the dependence table */
1932         *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1933
1934         if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
1935                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1936                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1937         else if (dep_table->entries[i-1].vddci) {
1938                 vddci = fiji_find_closest_vddci(hwmgr,
1939                                 (dep_table->entries[i].vddc -
1940                                                 (uint16_t)data->vddc_vddci_delta));
1941                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1942         }
1943
1944         if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1945                 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1946         else if (dep_table->entries[i].mvdd)
1947                 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1948
1949         return 0;
1950 }
1951
1952 static uint8_t fiji_get_sleep_divider_id_from_clock(uint32_t clock,
1953                 uint32_t clock_insr)
1954 {
1955         uint8_t i;
1956         uint32_t temp;
1957         uint32_t min = max(clock_insr, (uint32_t)FIJI_MINIMUM_ENGINE_CLOCK);
1958
1959         PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);
1960         for (i = FIJI_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
1961                 temp = clock >> i;
1962
1963                 if (temp >= min || i == 0)
1964                         break;
1965         }
1966         return i;
1967 }
1968 /**
1969 * Populates single SMC SCLK structure using the provided engine clock
1970 *
1971 * @param    hwmgr      the address of the hardware manager
1972 * @param    clock the engine clock to use to populate the structure
1973 * @param    sclk        the SMC SCLK structure to be populated
1974 */
1975
1976 static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1977                 uint32_t clock, uint16_t sclk_al_threshold,
1978                 struct SMU73_Discrete_GraphicsLevel *level)
1979 {
1980         int result;
1981         /* PP_Clocks minClocks; */
1982         uint32_t threshold, mvdd;
1983         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1984         struct phm_ppt_v1_information *table_info =
1985                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1986
1987         result = fiji_calculate_sclk_params(hwmgr, clock, level);
1988
1989         /* populate graphics levels */
1990         result = fiji_get_dependency_volt_by_clk(hwmgr,
1991                         table_info->vdd_dep_on_sclk, clock,
1992                         &level->MinVoltage, &mvdd);
1993         PP_ASSERT_WITH_CODE((0 == result),
1994                         "can not find VDDC voltage value for "
1995                         "VDDC engine clock dependency table",
1996                         return result);
1997
1998         level->SclkFrequency = clock;
1999         level->ActivityLevel = sclk_al_threshold;
2000         level->CcPwrDynRm = 0;
2001         level->CcPwrDynRm1 = 0;
2002         level->EnabledForActivity = 0;
2003         level->EnabledForThrottle = 1;
2004         level->UpHyst = 10;
2005         level->DownHyst = 0;
2006         level->VoltageDownHyst = 0;
2007         level->PowerThrottle = 0;
2008
2009         threshold = clock * data->fast_watermark_threshold / 100;
2010
2011
2012         data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr;
2013
2014         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
2015                 level->DeepSleepDivId = fiji_get_sleep_divider_id_from_clock(clock,
2016                                                                 hwmgr->display_config.min_core_set_clock_in_sr);
2017
2018
2019         /* Default to slow, highest DPM level will be
2020          * set to PPSMC_DISPLAY_WATERMARK_LOW later.
2021          */
2022         level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2023
2024         CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
2025         CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
2026         CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
2027         CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
2028         CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
2029         CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
2030         CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
2031         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
2032         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
2033
2034         return 0;
2035 }
2036 /**
2037 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
2038 *
2039 * @param    hwmgr      the address of the hardware manager
2040 */
2041 static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
2042 {
2043         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2044         struct fiji_dpm_table *dpm_table = &data->dpm_table;
2045         struct phm_ppt_v1_information *table_info =
2046                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2047         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
2048         uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
2049         int result = 0;
2050         uint32_t array = data->dpm_table_start +
2051                         offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
2052         uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
2053                         SMU73_MAX_LEVELS_GRAPHICS;
2054         struct SMU73_Discrete_GraphicsLevel *levels =
2055                         data->smc_state_table.GraphicsLevel;
2056         uint32_t i, max_entry;
2057         uint8_t hightest_pcie_level_enabled = 0,
2058                         lowest_pcie_level_enabled = 0,
2059                         mid_pcie_level_enabled = 0,
2060                         count = 0;
2061
2062         for (i = 0; i < dpm_table->sclk_table.count; i++) {
2063                 result = fiji_populate_single_graphic_level(hwmgr,
2064                                 dpm_table->sclk_table.dpm_levels[i].value,
2065                                 (uint16_t)data->activity_target[i],
2066                                 &levels[i]);
2067                 if (result)
2068                         return result;
2069
2070                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
2071                 if (i > 1)
2072                         levels[i].DeepSleepDivId = 0;
2073         }
2074
2075         /* Only enable level 0 for now.*/
2076         levels[0].EnabledForActivity = 1;
2077
2078         /* set highest level watermark to high */
2079         levels[dpm_table->sclk_table.count - 1].DisplayWatermark =
2080                         PPSMC_DISPLAY_WATERMARK_HIGH;
2081
2082         data->smc_state_table.GraphicsDpmLevelCount =
2083                         (uint8_t)dpm_table->sclk_table.count;
2084         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
2085                         fiji_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2086
2087         if (pcie_table != NULL) {
2088                 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
2089                                 "There must be 1 or more PCIE levels defined in PPTable.",
2090                                 return -EINVAL);
2091                 max_entry = pcie_entry_cnt - 1;
2092                 for (i = 0; i < dpm_table->sclk_table.count; i++)
2093                         levels[i].pcieDpmLevel =
2094                                         (uint8_t) ((i < max_entry)? i : max_entry);
2095         } else {
2096                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2097                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2098                                                 (1 << (hightest_pcie_level_enabled + 1))) != 0 ))
2099                         hightest_pcie_level_enabled++;
2100
2101                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2102                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2103                                                 (1 << lowest_pcie_level_enabled)) == 0 ))
2104                         lowest_pcie_level_enabled++;
2105
2106                 while ((count < hightest_pcie_level_enabled) &&
2107                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2108                                                 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0 ))
2109                         count++;
2110
2111                 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1+ count) <
2112                                 hightest_pcie_level_enabled?
2113                                                 (lowest_pcie_level_enabled + 1 + count) :
2114                                                 hightest_pcie_level_enabled;
2115
2116                 /* set pcieDpmLevel to hightest_pcie_level_enabled */
2117                 for(i = 2; i < dpm_table->sclk_table.count; i++)
2118                         levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
2119
2120                 /* set pcieDpmLevel to lowest_pcie_level_enabled */
2121                 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
2122
2123                 /* set pcieDpmLevel to mid_pcie_level_enabled */
2124                 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
2125         }
2126         /* level count will send to smc once at init smc table and never change */
2127         result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
2128                         (uint32_t)array_size, data->sram_end);
2129
2130         return result;
2131 }
2132
2133 /**
2134  * MCLK Frequency Ratio
2135  * SEQ_CG_RESP  Bit[31:24] - 0x0
2136  * Bit[27:24] \96 DDR3 Frequency ratio
2137  * 0x0 <= 100MHz,       450 < 0x8 <= 500MHz
2138  * 100 < 0x1 <= 150MHz,       500 < 0x9 <= 550MHz
2139  * 150 < 0x2 <= 200MHz,       550 < 0xA <= 600MHz
2140  * 200 < 0x3 <= 250MHz,       600 < 0xB <= 650MHz
2141  * 250 < 0x4 <= 300MHz,       650 < 0xC <= 700MHz
2142  * 300 < 0x5 <= 350MHz,       700 < 0xD <= 750MHz
2143  * 350 < 0x6 <= 400MHz,       750 < 0xE <= 800MHz
2144  * 400 < 0x7 <= 450MHz,       800 < 0xF
2145  */
2146 static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock)
2147 {
2148         if (mem_clock <= 10000) return 0x0;
2149         if (mem_clock <= 15000) return 0x1;
2150         if (mem_clock <= 20000) return 0x2;
2151         if (mem_clock <= 25000) return 0x3;
2152         if (mem_clock <= 30000) return 0x4;
2153         if (mem_clock <= 35000) return 0x5;
2154         if (mem_clock <= 40000) return 0x6;
2155         if (mem_clock <= 45000) return 0x7;
2156         if (mem_clock <= 50000) return 0x8;
2157         if (mem_clock <= 55000) return 0x9;
2158         if (mem_clock <= 60000) return 0xa;
2159         if (mem_clock <= 65000) return 0xb;
2160         if (mem_clock <= 70000) return 0xc;
2161         if (mem_clock <= 75000) return 0xd;
2162         if (mem_clock <= 80000) return 0xe;
2163         /* mem_clock > 800MHz */
2164         return 0xf;
2165 }
2166
2167 /**
2168 * Populates the SMC MCLK structure using the provided memory clock
2169 *
2170 * @param    hwmgr   the address of the hardware manager
2171 * @param    clock   the memory clock to use to populate the structure
2172 * @param    sclk    the SMC SCLK structure to be populated
2173 */
2174 static int fiji_calculate_mclk_params(struct pp_hwmgr *hwmgr,
2175     uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk)
2176 {
2177         struct pp_atomctrl_memory_clock_param mem_param;
2178         int result;
2179
2180         result = atomctrl_get_memory_pll_dividers_vi(hwmgr, clock, &mem_param);
2181         PP_ASSERT_WITH_CODE((0 == result),
2182                         "Failed to get Memory PLL Dividers.",);
2183
2184         /* Save the result data to outpupt memory level structure */
2185         mclk->MclkFrequency   = clock;
2186         mclk->MclkDivider     = (uint8_t)mem_param.mpll_post_divider;
2187         mclk->FreqRange       = fiji_get_mclk_frequency_ratio(clock);
2188
2189         return result;
2190 }
2191
2192 static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
2193                 uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level)
2194 {
2195         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2196         struct phm_ppt_v1_information *table_info =
2197                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2198         int result = 0;
2199
2200         if (table_info->vdd_dep_on_mclk) {
2201                 result = fiji_get_dependency_volt_by_clk(hwmgr,
2202                                 table_info->vdd_dep_on_mclk, clock,
2203                                 &mem_level->MinVoltage, &mem_level->MinMvdd);
2204                 PP_ASSERT_WITH_CODE((0 == result),
2205                                 "can not find MinVddc voltage value from memory "
2206                                 "VDDC voltage dependency table", return result);
2207         }
2208
2209         mem_level->EnabledForThrottle = 1;
2210         mem_level->EnabledForActivity = 0;
2211         mem_level->UpHyst = 0;
2212         mem_level->DownHyst = 100;
2213         mem_level->VoltageDownHyst = 0;
2214         mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
2215         mem_level->StutterEnable = false;
2216
2217         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2218
2219         /* enable stutter mode if all the follow condition applied
2220          * PECI_GetNumberOfActiveDisplays(hwmgr->pPECI,
2221          * &(data->DisplayTiming.numExistingDisplays));
2222          */
2223         data->display_timing.num_existing_displays = 1;
2224
2225         if ((data->mclk_stutter_mode_threshold) &&
2226                 (clock <= data->mclk_stutter_mode_threshold) &&
2227                 (!data->is_uvd_enabled) &&
2228                 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
2229                                 STUTTER_ENABLE) & 0x1))
2230                 mem_level->StutterEnable = true;
2231
2232         result = fiji_calculate_mclk_params(hwmgr, clock, mem_level);
2233         if (!result) {
2234                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
2235                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
2236                 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
2237                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
2238         }
2239         return result;
2240 }
2241
2242 /**
2243 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
2244 *
2245 * @param    hwmgr      the address of the hardware manager
2246 */
2247 static int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
2248 {
2249         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2250         struct fiji_dpm_table *dpm_table = &data->dpm_table;
2251         int result;
2252         /* populate MCLK dpm table to SMU7 */
2253         uint32_t array = data->dpm_table_start +
2254                         offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
2255         uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) *
2256                         SMU73_MAX_LEVELS_MEMORY;
2257         struct SMU73_Discrete_MemoryLevel *levels =
2258                         data->smc_state_table.MemoryLevel;
2259         uint32_t i;
2260
2261         for (i = 0; i < dpm_table->mclk_table.count; i++) {
2262                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
2263                                 "can not populate memory level as memory clock is zero",
2264                                 return -EINVAL);
2265                 result = fiji_populate_single_memory_level(hwmgr,
2266                                 dpm_table->mclk_table.dpm_levels[i].value,
2267                                 &levels[i]);
2268                 if (result)
2269                         return result;
2270         }
2271
2272         /* Only enable level 0 for now. */
2273         levels[0].EnabledForActivity = 1;
2274
2275         /* in order to prevent MC activity from stutter mode to push DPM up.
2276          * the UVD change complements this by putting the MCLK in
2277          * a higher state by default such that we are not effected by
2278          * up threshold or and MCLK DPM latency.
2279          */
2280         levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
2281         CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
2282
2283         data->smc_state_table.MemoryDpmLevelCount =
2284                         (uint8_t)dpm_table->mclk_table.count;
2285         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
2286                         fiji_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2287         /* set highest level watermark to high */
2288         levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
2289                         PPSMC_DISPLAY_WATERMARK_HIGH;
2290
2291         /* level count will send to smc once at init smc table and never change */
2292         result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
2293                         (uint32_t)array_size, data->sram_end);
2294
2295         return result;
2296 }
2297
2298 /**
2299 * Populates the SMC MVDD structure using the provided memory clock.
2300 *
2301 * @param    hwmgr      the address of the hardware manager
2302 * @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
2303 * @param    voltage     the SMC VOLTAGE structure to be populated
2304 */
2305 static int fiji_populate_mvdd_value(struct pp_hwmgr *hwmgr,
2306                 uint32_t mclk, SMIO_Pattern *smio_pat)
2307 {
2308         const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2309         struct phm_ppt_v1_information *table_info =
2310                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2311         uint32_t i = 0;
2312
2313         if (FIJI_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
2314                 /* find mvdd value which clock is more than request */
2315                 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
2316                         if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
2317                                 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
2318                                 break;
2319                         }
2320                 }
2321                 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
2322                                 "MVDD Voltage is outside the supported range.",
2323                                 return -EINVAL);
2324         } else
2325                 return -EINVAL;
2326
2327         return 0;
2328 }
2329
2330 static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
2331                 SMU73_Discrete_DpmTable *table)
2332 {
2333         int result = 0;
2334         const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2335         struct phm_ppt_v1_information *table_info =
2336                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2337         struct pp_atomctrl_clock_dividers_vi dividers;
2338         SMIO_Pattern vol_level;
2339         uint32_t mvdd;
2340         uint16_t us_mvdd;
2341         uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2342         uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
2343
2344         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2345
2346         if (!data->sclk_dpm_key_disabled) {
2347                 /* Get MinVoltage and Frequency from DPM0,
2348                  * already converted to SMC_UL */
2349                 table->ACPILevel.SclkFrequency =
2350                                 data->dpm_table.sclk_table.dpm_levels[0].value;
2351                 result = fiji_get_dependency_volt_by_clk(hwmgr,
2352                                 table_info->vdd_dep_on_sclk,
2353                                 table->ACPILevel.SclkFrequency,
2354                                 &table->ACPILevel.MinVoltage, &mvdd);
2355                 PP_ASSERT_WITH_CODE((0 == result),
2356                                 "Cannot find ACPI VDDC voltage value "
2357                                 "in Clock Dependency Table",);
2358         } else {
2359                 table->ACPILevel.SclkFrequency =
2360                                 data->vbios_boot_state.sclk_bootup_value;
2361                 table->ACPILevel.MinVoltage =
2362                                 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
2363         }
2364
2365         /* get the engine clock dividers for this clock value */
2366         result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
2367                         table->ACPILevel.SclkFrequency,  &dividers);
2368         PP_ASSERT_WITH_CODE(result == 0,
2369                         "Error retrieving Engine Clock dividers from VBIOS.",
2370                         return result);
2371
2372         table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
2373         table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2374         table->ACPILevel.DeepSleepDivId = 0;
2375
2376         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
2377                         SPLL_PWRON, 0);
2378         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
2379                         SPLL_RESET, 1);
2380         spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
2381                         SCLK_MUX_SEL, 4);
2382
2383         table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2384         table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2385         table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2386         table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2387         table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2388         table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2389         table->ACPILevel.CcPwrDynRm = 0;
2390         table->ACPILevel.CcPwrDynRm1 = 0;
2391
2392         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
2393         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
2394         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
2395         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
2396         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
2397         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
2398         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
2399         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
2400         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
2401         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
2402         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
2403
2404         if (!data->mclk_dpm_key_disabled) {
2405                 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
2406                 table->MemoryACPILevel.MclkFrequency =
2407                                 data->dpm_table.mclk_table.dpm_levels[0].value;
2408                 result = fiji_get_dependency_volt_by_clk(hwmgr,
2409                                 table_info->vdd_dep_on_mclk,
2410                                 table->MemoryACPILevel.MclkFrequency,
2411                                 &table->MemoryACPILevel.MinVoltage, &mvdd);
2412                 PP_ASSERT_WITH_CODE((0 == result),
2413                                 "Cannot find ACPI VDDCI voltage value "
2414                                 "in Clock Dependency Table",);
2415         } else {
2416                 table->MemoryACPILevel.MclkFrequency =
2417                                 data->vbios_boot_state.mclk_bootup_value;
2418                 table->MemoryACPILevel.MinVoltage =
2419                                 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
2420         }
2421
2422         us_mvdd = 0;
2423         if ((FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
2424                         (data->mclk_dpm_key_disabled))
2425                 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
2426         else {
2427                 if (!fiji_populate_mvdd_value(hwmgr,
2428                                 data->dpm_table.mclk_table.dpm_levels[0].value,
2429                                 &vol_level))
2430                         us_mvdd = vol_level.Voltage;
2431         }
2432
2433         table->MemoryACPILevel.MinMvdd =
2434                         PP_HOST_TO_SMC_UL(us_mvdd * VOLTAGE_SCALE);
2435
2436         table->MemoryACPILevel.EnabledForThrottle = 0;
2437         table->MemoryACPILevel.EnabledForActivity = 0;
2438         table->MemoryACPILevel.UpHyst = 0;
2439         table->MemoryACPILevel.DownHyst = 100;
2440         table->MemoryACPILevel.VoltageDownHyst = 0;
2441         table->MemoryACPILevel.ActivityLevel =
2442                         PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
2443
2444         table->MemoryACPILevel.StutterEnable = false;
2445         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
2446         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
2447
2448         return result;
2449 }
2450
2451 static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
2452                 SMU73_Discrete_DpmTable *table)
2453 {
2454         int result = -EINVAL;
2455         uint8_t count;
2456         struct pp_atomctrl_clock_dividers_vi dividers;
2457         struct phm_ppt_v1_information *table_info =
2458                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2459         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2460                         table_info->mm_dep_table;
2461         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2462
2463         table->VceLevelCount = (uint8_t)(mm_table->count);
2464         table->VceBootLevel = 0;
2465
2466         for(count = 0; count < table->VceLevelCount; count++) {
2467                 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
2468                 table->VceLevel[count].MinVoltage = 0;
2469                 table->VceLevel[count].MinVoltage |=
2470                                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
2471                 table->VceLevel[count].MinVoltage |=
2472                                 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
2473                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
2474                 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2475
2476                 /*retrieve divider value for VBIOS */
2477                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2478                                 table->VceLevel[count].Frequency, &dividers);
2479                 PP_ASSERT_WITH_CODE((0 == result),
2480                                 "can not find divide id for VCE engine clock",
2481                                 return result);
2482
2483                 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2484
2485                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
2486                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
2487         }
2488         return result;
2489 }
2490
2491 static int fiji_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
2492                 SMU73_Discrete_DpmTable *table)
2493 {
2494         int result = -EINVAL;
2495         uint8_t count;
2496         struct pp_atomctrl_clock_dividers_vi dividers;
2497         struct phm_ppt_v1_information *table_info =
2498                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2499         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2500                         table_info->mm_dep_table;
2501         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2502
2503         table->AcpLevelCount = (uint8_t)(mm_table->count);
2504         table->AcpBootLevel = 0;
2505
2506         for (count = 0; count < table->AcpLevelCount; count++) {
2507                 table->AcpLevel[count].Frequency = mm_table->entries[count].aclk;
2508                 table->AcpLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2509                                 VOLTAGE_SCALE) << VDDC_SHIFT;
2510                 table->AcpLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2511                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2512                 table->AcpLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2513
2514                 /* retrieve divider value for VBIOS */
2515                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2516                                 table->AcpLevel[count].Frequency, &dividers);
2517                 PP_ASSERT_WITH_CODE((0 == result),
2518                                 "can not find divide id for engine clock", return result);
2519
2520                 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2521
2522                 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
2523                 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].MinVoltage);
2524         }
2525         return result;
2526 }
2527
2528 static int fiji_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
2529                 SMU73_Discrete_DpmTable *table)
2530 {
2531         int result = -EINVAL;
2532         uint8_t count;
2533         struct pp_atomctrl_clock_dividers_vi dividers;
2534         struct phm_ppt_v1_information *table_info =
2535                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2536         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2537                         table_info->mm_dep_table;
2538         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2539
2540         table->SamuBootLevel = 0;
2541         table->SamuLevelCount = (uint8_t)(mm_table->count);
2542
2543         for (count = 0; count < table->SamuLevelCount; count++) {
2544                 /* not sure whether we need evclk or not */
2545                 table->SamuLevel[count].MinVoltage = 0;
2546                 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
2547                 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2548                                 VOLTAGE_SCALE) << VDDC_SHIFT;
2549                 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2550                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2551                 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2552
2553                 /* retrieve divider value for VBIOS */
2554                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2555                                 table->SamuLevel[count].Frequency, &dividers);
2556                 PP_ASSERT_WITH_CODE((0 == result),
2557                                 "can not find divide id for samu clock", return result);
2558
2559                 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2560
2561                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
2562                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
2563         }
2564         return result;
2565 }
2566
2567 static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
2568                 int32_t eng_clock, int32_t mem_clock,
2569                 struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs)
2570 {
2571         uint32_t dram_timing;
2572         uint32_t dram_timing2;
2573         uint32_t burstTime;
2574         ULONG state, trrds, trrdl;
2575         int result;
2576
2577         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
2578                         eng_clock, mem_clock);
2579         PP_ASSERT_WITH_CODE(result == 0,
2580                         "Error calling VBIOS to set DRAM_TIMING.", return result);
2581
2582         dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
2583         dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
2584         burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
2585
2586         state = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, STATE0);
2587         trrds = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDS0);
2588         trrdl = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDL0);
2589
2590         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
2591         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
2592         arb_regs->McArbBurstTime   = (uint8_t)burstTime;
2593         arb_regs->TRRDS            = (uint8_t)trrds;
2594         arb_regs->TRRDL            = (uint8_t)trrdl;
2595
2596         return 0;
2597 }
2598
2599 static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
2600 {
2601         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2602         struct SMU73_Discrete_MCArbDramTimingTable arb_regs;
2603         uint32_t i, j;
2604         int result = 0;
2605
2606         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
2607                 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
2608                         result = fiji_populate_memory_timing_parameters(hwmgr,
2609                                         data->dpm_table.sclk_table.dpm_levels[i].value,
2610                                         data->dpm_table.mclk_table.dpm_levels[j].value,
2611                                         &arb_regs.entries[i][j]);
2612                         if (result)
2613                                 break;
2614                 }
2615         }
2616
2617         if (!result)
2618                 result = fiji_copy_bytes_to_smc(
2619                                 hwmgr->smumgr,
2620                                 data->arb_table_start,
2621                                 (uint8_t *)&arb_regs,
2622                                 sizeof(SMU73_Discrete_MCArbDramTimingTable),
2623                                 data->sram_end);
2624         return result;
2625 }
2626
2627 static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
2628                 struct SMU73_Discrete_DpmTable *table)
2629 {
2630         int result = -EINVAL;
2631         uint8_t count;
2632         struct pp_atomctrl_clock_dividers_vi dividers;
2633         struct phm_ppt_v1_information *table_info =
2634                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2635         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2636                         table_info->mm_dep_table;
2637         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2638
2639         table->UvdLevelCount = (uint8_t)(mm_table->count);
2640         table->UvdBootLevel = 0;
2641
2642         for (count = 0; count < table->UvdLevelCount; count++) {
2643                 table->UvdLevel[count].MinVoltage = 0;
2644                 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
2645                 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
2646                 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2647                                 VOLTAGE_SCALE) << VDDC_SHIFT;
2648                 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2649                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2650                 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2651
2652                 /* retrieve divider value for VBIOS */
2653                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2654                                 table->UvdLevel[count].VclkFrequency, &dividers);
2655                 PP_ASSERT_WITH_CODE((0 == result),
2656                                 "can not find divide id for Vclk clock", return result);
2657
2658                 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
2659
2660                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2661                                 table->UvdLevel[count].DclkFrequency, &dividers);
2662                 PP_ASSERT_WITH_CODE((0 == result),
2663                                 "can not find divide id for Dclk clock", return result);
2664
2665                 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
2666
2667                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
2668                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
2669                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
2670
2671         }
2672         return result;
2673 }
2674
2675 static int fiji_find_boot_level(struct fiji_single_dpm_table *table,
2676                 uint32_t value, uint32_t *boot_level)
2677 {
2678         int result = -EINVAL;
2679         uint32_t i;
2680
2681         for (i = 0; i < table->count; i++) {
2682                 if (value == table->dpm_levels[i].value) {
2683                         *boot_level = i;
2684                         result = 0;
2685                 }
2686         }
2687         return result;
2688 }
2689
2690 static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
2691                 struct SMU73_Discrete_DpmTable *table)
2692 {
2693         int result = 0;
2694         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2695
2696         table->GraphicsBootLevel = 0;
2697         table->MemoryBootLevel = 0;
2698
2699         /* find boot level from dpm table */
2700         result = fiji_find_boot_level(&(data->dpm_table.sclk_table),
2701                         data->vbios_boot_state.sclk_bootup_value,
2702                         (uint32_t *)&(table->GraphicsBootLevel));
2703
2704         result = fiji_find_boot_level(&(data->dpm_table.mclk_table),
2705                         data->vbios_boot_state.mclk_bootup_value,
2706                         (uint32_t *)&(table->MemoryBootLevel));
2707
2708         table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
2709                         VOLTAGE_SCALE;
2710         table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
2711                         VOLTAGE_SCALE;
2712         table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
2713                         VOLTAGE_SCALE;
2714
2715         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
2716         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
2717         CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
2718
2719         return 0;
2720 }
2721
2722 static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
2723 {
2724         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2725         struct phm_ppt_v1_information *table_info =
2726                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2727         uint8_t count, level;
2728
2729         count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
2730         for (level = 0; level < count; level++) {
2731                 if(table_info->vdd_dep_on_sclk->entries[level].clk >=
2732                                 data->vbios_boot_state.sclk_bootup_value) {
2733                         data->smc_state_table.GraphicsBootLevel = level;
2734                         break;
2735                 }
2736         }
2737
2738         count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
2739         for (level = 0; level < count; level++) {
2740                 if(table_info->vdd_dep_on_mclk->entries[level].clk >=
2741                                 data->vbios_boot_state.mclk_bootup_value) {
2742                         data->smc_state_table.MemoryBootLevel = level;
2743                         break;
2744                 }
2745         }
2746
2747         return 0;
2748 }
2749
2750 static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
2751 {
2752         uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
2753                         volt_with_cks, value;
2754         uint16_t clock_freq_u16;
2755         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2756         uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
2757                         volt_offset = 0;
2758         struct phm_ppt_v1_information *table_info =
2759                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2760         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2761                         table_info->vdd_dep_on_sclk;
2762
2763         stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
2764
2765         /* Read SMU_Eefuse to read and calculate RO and determine
2766          * if the part is SS or FF. if RO >= 1660MHz, part is FF.
2767          */
2768         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2769                         ixSMU_EFUSE_0 + (146 * 4));
2770         efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2771                         ixSMU_EFUSE_0 + (148 * 4));
2772         efuse &= 0xFF000000;
2773         efuse = efuse >> 24;
2774         efuse2 &= 0xF;
2775
2776         if (efuse2 == 1)
2777                 ro = (2300 - 1350) * efuse / 255 + 1350;
2778         else
2779                 ro = (2500 - 1000) * efuse / 255 + 1000;
2780
2781         if (ro >= 1660)
2782                 type = 0;
2783         else
2784                 type = 1;
2785
2786         /* Populate Stretch amount */
2787         data->smc_state_table.ClockStretcherAmount = stretch_amount;
2788
2789         /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
2790         for (i = 0; i < sclk_table->count; i++) {
2791                 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
2792                                 sclk_table->entries[i].cks_enable << i;
2793                 volt_without_cks = (uint32_t)((14041 *
2794                         (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
2795                         (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
2796                 volt_with_cks = (uint32_t)((13946 *
2797                         (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
2798                         (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
2799                 if (volt_without_cks >= volt_with_cks)
2800                         volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
2801                                         sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
2802                 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
2803         }
2804
2805         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2806                         STRETCH_ENABLE, 0x0);
2807         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2808                         masterReset, 0x1);
2809         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2810                         staticEnable, 0x1);
2811         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2812                         masterReset, 0x0);
2813
2814         /* Populate CKS Lookup Table */
2815         if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
2816                 stretch_amount2 = 0;
2817         else if (stretch_amount == 3 || stretch_amount == 4)
2818                 stretch_amount2 = 1;
2819         else {
2820                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2821                                 PHM_PlatformCaps_ClockStretcher);
2822                 PP_ASSERT_WITH_CODE(false,
2823                                 "Stretch Amount in PPTable not supported\n",
2824                                 return -EINVAL);
2825         }
2826
2827         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2828                         ixPWR_CKS_CNTL);
2829         value &= 0xFFC2FF87;
2830         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
2831                         fiji_clock_stretcher_lookup_table[stretch_amount2][0];
2832         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
2833                         fiji_clock_stretcher_lookup_table[stretch_amount2][1];
2834         clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
2835                         GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].
2836                         SclkFrequency) / 100);
2837         if (fiji_clock_stretcher_lookup_table[stretch_amount2][0] <
2838                         clock_freq_u16 &&
2839             fiji_clock_stretcher_lookup_table[stretch_amount2][1] >
2840                         clock_freq_u16) {
2841                 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
2842                 value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
2843                 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
2844                 value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
2845                 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
2846                 value |= (fiji_clock_stretch_amount_conversion
2847                                 [fiji_clock_stretcher_lookup_table[stretch_amount2][3]]
2848                                  [stretch_amount]) << 3;
2849         }
2850         CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
2851                         CKS_LOOKUPTableEntry[0].minFreq);
2852         CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
2853                         CKS_LOOKUPTableEntry[0].maxFreq);
2854         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
2855                         fiji_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
2856         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
2857                         (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
2858
2859         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2860                         ixPWR_CKS_CNTL, value);
2861
2862         /* Populate DDT Lookup Table */
2863         for (i = 0; i < 4; i++) {
2864                 /* Assign the minimum and maximum VID stored
2865                  * in the last row of Clock Stretcher Voltage Table.
2866                  */
2867                 data->smc_state_table.ClockStretcherDataTable.
2868                 ClockStretcherDataTableEntry[i].minVID =
2869                                 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][2];
2870                 data->smc_state_table.ClockStretcherDataTable.
2871                 ClockStretcherDataTableEntry[i].maxVID =
2872                                 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][3];
2873                 /* Loop through each SCLK and check the frequency
2874                  * to see if it lies within the frequency for clock stretcher.
2875                  */
2876                 for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
2877                         cks_setting = 0;
2878                         clock_freq = PP_SMC_TO_HOST_UL(
2879                                         data->smc_state_table.GraphicsLevel[j].SclkFrequency);
2880                         /* Check the allowed frequency against the sclk level[j].
2881                          *  Sclk's endianness has already been converted,
2882                          *  and it's in 10Khz unit,
2883                          *  as opposed to Data table, which is in Mhz unit.
2884                          */
2885                         if (clock_freq >=
2886                                         (fiji_clock_stretcher_ddt_table[type][i][0]) * 100) {
2887                                 cks_setting |= 0x2;
2888                                 if (clock_freq <
2889                                                 (fiji_clock_stretcher_ddt_table[type][i][1]) * 100)
2890                                         cks_setting |= 0x1;
2891                         }
2892                         data->smc_state_table.ClockStretcherDataTable.
2893                         ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
2894                 }
2895                 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.
2896                                 ClockStretcherDataTable.
2897                                 ClockStretcherDataTableEntry[i].setting);
2898         }
2899
2900         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
2901         value &= 0xFFFFFFFE;
2902         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
2903
2904         return 0;
2905 }
2906
2907 /**
2908 * Populates the SMC VRConfig field in DPM table.
2909 *
2910 * @param    hwmgr   the address of the hardware manager
2911 * @param    table   the SMC DPM table structure to be populated
2912 * @return   always 0
2913 */
2914 static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
2915                 struct SMU73_Discrete_DpmTable *table)
2916 {
2917         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2918         uint16_t config;
2919
2920         config = VR_MERGED_WITH_VDDC;
2921         table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
2922
2923         /* Set Vddc Voltage Controller */
2924         if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
2925                 config = VR_SVI2_PLANE_1;
2926                 table->VRConfig |= config;
2927         } else {
2928                 PP_ASSERT_WITH_CODE(false,
2929                                 "VDDC should be on SVI2 control in merged mode!",);
2930         }
2931         /* Set Vddci Voltage Controller */
2932         if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
2933                 config = VR_SVI2_PLANE_2;  /* only in merged mode */
2934                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2935         } else if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
2936                 config = VR_SMIO_PATTERN_1;
2937                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2938         } else {
2939                 config = VR_STATIC_VOLTAGE;
2940                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2941         }
2942         /* Set Mvdd Voltage Controller */
2943         if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
2944                 config = VR_SVI2_PLANE_2;
2945                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2946         } else if(FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
2947                 config = VR_SMIO_PATTERN_2;
2948                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2949         } else {
2950                 config = VR_STATIC_VOLTAGE;
2951                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2952         }
2953
2954         return 0;
2955 }
2956
2957 /**
2958 * Initializes the SMC table and uploads it
2959 *
2960 * @param    hwmgr  the address of the powerplay hardware manager.
2961 * @param    pInput  the pointer to input data (PowerState)
2962 * @return   always 0
2963 */
2964 static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
2965 {
2966         int result;
2967         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2968         struct phm_ppt_v1_information *table_info =
2969                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2970         struct SMU73_Discrete_DpmTable *table = &(data->smc_state_table);
2971         const struct fiji_ulv_parm *ulv = &(data->ulv);
2972         uint8_t i;
2973         struct pp_atomctrl_gpio_pin_assignment gpio_pin;
2974
2975         result = fiji_setup_default_dpm_tables(hwmgr);
2976         PP_ASSERT_WITH_CODE(0 == result,
2977                         "Failed to setup default DPM tables!", return result);
2978
2979         if(FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control)
2980                 fiji_populate_smc_voltage_tables(hwmgr, table);
2981
2982         table->SystemFlags = 0;
2983
2984         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2985                         PHM_PlatformCaps_AutomaticDCTransition))
2986                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2987
2988         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2989                         PHM_PlatformCaps_StepVddc))
2990                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2991
2992         if (data->is_memory_gddr5)
2993                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2994
2995         if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2996                 result = fiji_populate_ulv_state(hwmgr, table);
2997                 PP_ASSERT_WITH_CODE(0 == result,
2998                                 "Failed to initialize ULV state!", return result);
2999                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3000                                 ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3001         }
3002
3003         result = fiji_populate_smc_link_level(hwmgr, table);
3004         PP_ASSERT_WITH_CODE(0 == result,
3005                         "Failed to initialize Link Level!", return result);
3006
3007         result = fiji_populate_all_graphic_levels(hwmgr);
3008         PP_ASSERT_WITH_CODE(0 == result,
3009                         "Failed to initialize Graphics Level!", return result);
3010
3011         result = fiji_populate_all_memory_levels(hwmgr);
3012         PP_ASSERT_WITH_CODE(0 == result,
3013                         "Failed to initialize Memory Level!", return result);
3014
3015         result = fiji_populate_smc_acpi_level(hwmgr, table);
3016         PP_ASSERT_WITH_CODE(0 == result,
3017                         "Failed to initialize ACPI Level!", return result);
3018
3019         result = fiji_populate_smc_vce_level(hwmgr, table);
3020         PP_ASSERT_WITH_CODE(0 == result,
3021                         "Failed to initialize VCE Level!", return result);
3022
3023         result = fiji_populate_smc_acp_level(hwmgr, table);
3024         PP_ASSERT_WITH_CODE(0 == result,
3025                         "Failed to initialize ACP Level!", return result);
3026
3027         result = fiji_populate_smc_samu_level(hwmgr, table);
3028         PP_ASSERT_WITH_CODE(0 == result,
3029                         "Failed to initialize SAMU Level!", return result);
3030
3031         /* Since only the initial state is completely set up at this point
3032          * (the other states are just copies of the boot state) we only
3033          * need to populate the  ARB settings for the initial state.
3034          */
3035         result = fiji_program_memory_timing_parameters(hwmgr);
3036         PP_ASSERT_WITH_CODE(0 == result,
3037                         "Failed to Write ARB settings for the initial state.", return result);
3038
3039         result = fiji_populate_smc_uvd_level(hwmgr, table);
3040         PP_ASSERT_WITH_CODE(0 == result,
3041                         "Failed to initialize UVD Level!", return result);
3042
3043         result = fiji_populate_smc_boot_level(hwmgr, table);
3044         PP_ASSERT_WITH_CODE(0 == result,
3045                         "Failed to initialize Boot Level!", return result);
3046
3047         result = fiji_populate_smc_initailial_state(hwmgr);
3048         PP_ASSERT_WITH_CODE(0 == result,
3049                         "Failed to initialize Boot State!", return result);
3050
3051         result = fiji_populate_bapm_parameters_in_dpm_table(hwmgr);
3052         PP_ASSERT_WITH_CODE(0 == result,
3053                         "Failed to populate BAPM Parameters!", return result);
3054
3055         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3056                         PHM_PlatformCaps_ClockStretcher)) {
3057                 result = fiji_populate_clock_stretcher_data_table(hwmgr);
3058                 PP_ASSERT_WITH_CODE(0 == result,
3059                                 "Failed to populate Clock Stretcher Data Table!",
3060                                 return result);
3061         }
3062
3063         table->GraphicsVoltageChangeEnable  = 1;
3064         table->GraphicsThermThrottleEnable  = 1;
3065         table->GraphicsInterval = 1;
3066         table->VoltageInterval  = 1;
3067         table->ThermalInterval  = 1;
3068         table->TemperatureLimitHigh =
3069                         table_info->cac_dtp_table->usTargetOperatingTemp *
3070                         FIJI_Q88_FORMAT_CONVERSION_UNIT;
3071         table->TemperatureLimitLow  =
3072                         (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
3073                         FIJI_Q88_FORMAT_CONVERSION_UNIT;
3074         table->MemoryVoltageChangeEnable = 1;
3075         table->MemoryInterval = 1;
3076         table->VoltageResponseTime = 0;
3077         table->PhaseResponseTime = 0;
3078         table->MemoryThermThrottleEnable = 1;
3079         table->PCIeBootLinkLevel = 0;      /* 0:Gen1 1:Gen2 2:Gen3*/
3080         table->PCIeGenInterval = 1;
3081         table->VRConfig = 0;
3082
3083         result = fiji_populate_vr_config(hwmgr, table);
3084         PP_ASSERT_WITH_CODE(0 == result,
3085                         "Failed to populate VRConfig setting!", return result);
3086
3087         table->ThermGpio = 17;
3088         table->SclkStepSize = 0x4000;
3089
3090         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
3091                 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
3092                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3093                                 PHM_PlatformCaps_RegulatorHot);
3094         } else {
3095                 table->VRHotGpio = FIJI_UNUSED_GPIO_PIN;
3096                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3097                                 PHM_PlatformCaps_RegulatorHot);
3098         }
3099
3100         if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
3101                         &gpio_pin)) {
3102                 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
3103                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3104                                 PHM_PlatformCaps_AutomaticDCTransition);
3105         } else {
3106                 table->AcDcGpio = FIJI_UNUSED_GPIO_PIN;
3107                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3108                                 PHM_PlatformCaps_AutomaticDCTransition);
3109         }
3110
3111         /* Thermal Output GPIO */
3112         if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
3113                         &gpio_pin)) {
3114                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3115                                 PHM_PlatformCaps_ThermalOutGPIO);
3116
3117                 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
3118
3119                 /* For porlarity read GPIOPAD_A with assigned Gpio pin
3120                  * since VBIOS will program this register to set 'inactive state',
3121                  * driver can then determine 'active state' from this and
3122                  * program SMU with correct polarity
3123                  */
3124                 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
3125                                 (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
3126                 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
3127
3128                 /* if required, combine VRHot/PCC with thermal out GPIO */
3129                 if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3130                                 PHM_PlatformCaps_RegulatorHot) &&
3131                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3132                                         PHM_PlatformCaps_CombinePCCWithThermalSignal))
3133                         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
3134         } else {
3135                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3136                                 PHM_PlatformCaps_ThermalOutGPIO);
3137                 table->ThermOutGpio = 17;
3138                 table->ThermOutPolarity = 1;
3139                 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
3140         }
3141
3142         for (i = 0; i < SMU73_MAX_ENTRIES_SMIO; i++)
3143                 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
3144
3145         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
3146         CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
3147         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
3148         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
3149         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
3150         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
3151         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
3152         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
3153         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
3154
3155         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
3156         result = fiji_copy_bytes_to_smc(hwmgr->smumgr,
3157                         data->dpm_table_start +
3158                         offsetof(SMU73_Discrete_DpmTable, SystemFlags),
3159                         (uint8_t *)&(table->SystemFlags),
3160                         sizeof(SMU73_Discrete_DpmTable) - 3 * sizeof(SMU73_PIDController),
3161                         data->sram_end);
3162         PP_ASSERT_WITH_CODE(0 == result,
3163                         "Failed to upload dpm data to SMC memory!", return result);
3164
3165         return 0;
3166 }
3167
3168 /**
3169 * Initialize the ARB DRAM timing table's index field.
3170 *
3171 * @param    hwmgr  the address of the powerplay hardware manager.
3172 * @return   always 0
3173 */
3174 static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr)
3175 {
3176         const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3177         uint32_t tmp;
3178         int result;
3179
3180         /* This is a read-modify-write on the first byte of the ARB table.
3181          * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
3182          * is the field 'current'.
3183          * This solution is ugly, but we never write the whole table only
3184          * individual fields in it.
3185          * In reality this field should not be in that structure
3186          * but in a soft register.
3187          */
3188         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
3189                         data->arb_table_start, &tmp, data->sram_end);
3190
3191         if (result)
3192                 return result;
3193
3194         tmp &= 0x00FFFFFF;
3195         tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
3196
3197         return fiji_write_smc_sram_dword(hwmgr->smumgr,
3198                         data->arb_table_start,  tmp, data->sram_end);
3199 }
3200
3201 static int fiji_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
3202 {
3203         if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3204                         PHM_PlatformCaps_RegulatorHot))
3205                 return smum_send_msg_to_smc(hwmgr->smumgr,
3206                                 PPSMC_MSG_EnableVRHotGPIOInterrupt);
3207
3208         return 0;
3209 }
3210
3211 static int fiji_enable_sclk_control(struct pp_hwmgr *hwmgr)
3212 {
3213         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
3214                         SCLK_PWRMGT_OFF, 0);
3215         return 0;
3216 }
3217
3218 static int fiji_enable_ulv(struct pp_hwmgr *hwmgr)
3219 {
3220         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3221         struct fiji_ulv_parm *ulv = &(data->ulv);
3222
3223         if (ulv->ulv_supported)
3224                 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
3225
3226         return 0;
3227 }
3228
3229 static int fiji_disable_ulv(struct pp_hwmgr *hwmgr)
3230 {
3231         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3232         struct fiji_ulv_parm *ulv = &(data->ulv);
3233
3234         if (ulv->ulv_supported)
3235                 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableULV);
3236
3237         return 0;
3238 }
3239
3240 static int fiji_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
3241 {
3242         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3243                         PHM_PlatformCaps_SclkDeepSleep)) {
3244                 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
3245                         PP_ASSERT_WITH_CODE(false,
3246                                         "Attempt to enable Master Deep Sleep switch failed!",
3247                                         return -1);
3248         } else {
3249                 if (smum_send_msg_to_smc(hwmgr->smumgr,
3250                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
3251                         PP_ASSERT_WITH_CODE(false,
3252                                         "Attempt to disable Master Deep Sleep switch failed!",
3253                                         return -1);
3254                 }
3255         }
3256
3257         return 0;
3258 }
3259
3260 static int fiji_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
3261 {
3262         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3263                         PHM_PlatformCaps_SclkDeepSleep)) {
3264                 if (smum_send_msg_to_smc(hwmgr->smumgr,
3265                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
3266                         PP_ASSERT_WITH_CODE(false,
3267                                         "Attempt to disable Master Deep Sleep switch failed!",
3268                                         return -1);
3269                 }
3270         }
3271
3272         return 0;
3273 }
3274
3275 static int fiji_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3276 {
3277         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3278         uint32_t   val, val0, val2;
3279         uint32_t   i, cpl_cntl, cpl_threshold, mc_threshold;
3280
3281         /* enable SCLK dpm */
3282         if(!data->sclk_dpm_key_disabled)
3283                 PP_ASSERT_WITH_CODE(
3284                 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
3285                 "Failed to enable SCLK DPM during DPM Start Function!",
3286                 return -1);
3287
3288         /* enable MCLK dpm */
3289         if(0 == data->mclk_dpm_key_disabled) {
3290                 cpl_threshold = 0;
3291                 mc_threshold = 0;
3292
3293                 /* Read per MCD tile (0 - 7) */
3294                 for (i = 0; i < 8; i++) {
3295                         PHM_WRITE_FIELD(hwmgr->device, MC_CONFIG_MCD, MC_RD_ENABLE, i);
3296                         val = cgs_read_register(hwmgr->device, mmMC_SEQ_RESERVE_0_S) & 0xf0000000;
3297                         if (0xf0000000 != val) {
3298                                 /* count number of MCQ that has channel(s) enabled */
3299                                 cpl_threshold++;
3300                                 /* only harvest 3 or full 4 supported */
3301                                 mc_threshold = val ? 3 : 4;
3302                         }
3303                 }
3304                 PP_ASSERT_WITH_CODE(0 != cpl_threshold,
3305                                 "Number of MCQ is zero!", return -EINVAL;);
3306
3307                 mc_threshold = ((mc_threshold & LCAC_MC0_CNTL__MC0_THRESHOLD_MASK) <<
3308                                 LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT) |
3309                                                 LCAC_MC0_CNTL__MC0_ENABLE_MASK;
3310                 cpl_cntl = ((cpl_threshold & LCAC_CPL_CNTL__CPL_THRESHOLD_MASK) <<
3311                                 LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT) |
3312                                                 LCAC_CPL_CNTL__CPL_ENABLE_MASK;
3313                 cpl_cntl = (cpl_cntl | (8 << LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT));
3314                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3315                                 ixLCAC_MC0_CNTL, mc_threshold);
3316                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3317                                 ixLCAC_MC1_CNTL, mc_threshold);
3318                 if (8 == cpl_threshold) {
3319                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3320                                         ixLCAC_MC2_CNTL, mc_threshold);
3321                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3322                                         ixLCAC_MC3_CNTL, mc_threshold);
3323                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3324                                         ixLCAC_MC4_CNTL, mc_threshold);
3325                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3326                                         ixLCAC_MC5_CNTL, mc_threshold);
3327                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3328                                         ixLCAC_MC6_CNTL, mc_threshold);
3329                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3330                                         ixLCAC_MC7_CNTL, mc_threshold);
3331                 }
3332                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3333                                 ixLCAC_CPL_CNTL, cpl_cntl);
3334
3335                 udelay(5);
3336
3337                 mc_threshold = mc_threshold |
3338                                 (1 << LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT);
3339                 cpl_cntl = cpl_cntl | (1 << LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT);
3340                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3341                                 ixLCAC_MC0_CNTL, mc_threshold);
3342                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3343                                 ixLCAC_MC1_CNTL, mc_threshold);
3344                 if (8 == cpl_threshold) {
3345                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3346                                         ixLCAC_MC2_CNTL, mc_threshold);
3347                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3348                                         ixLCAC_MC3_CNTL, mc_threshold);
3349                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3350                                         ixLCAC_MC4_CNTL, mc_threshold);
3351                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3352                                         ixLCAC_MC5_CNTL, mc_threshold);
3353                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3354                                         ixLCAC_MC6_CNTL, mc_threshold);
3355                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3356                                         ixLCAC_MC7_CNTL, mc_threshold);
3357                 }
3358                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3359                                 ixLCAC_CPL_CNTL, cpl_cntl);
3360
3361                 /* Program CAC_EN per MCD (0-7) Tile */
3362                 val0 = val = cgs_read_register(hwmgr->device, mmMC_CONFIG_MCD);
3363                 val &= ~(MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK |
3364                                 MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK |
3365                                 MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK |
3366                                 MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK |
3367                                 MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK |
3368                                 MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK |
3369                                 MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK |
3370                                 MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK |
3371                                 MC_CONFIG_MCD__MC_RD_ENABLE_MASK);
3372
3373                 for (i = 0; i < 8; i++) {
3374                         /* Enable MCD i Tile read & write */
3375                         val2  = (val | (i << MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT) |
3376                                         (1 << i));
3377                         cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val2);
3378                         /* Enbale CAC_ON MCD i Tile */
3379                         val2 = cgs_read_register(hwmgr->device, mmMC_SEQ_CNTL);
3380                         val2 |= MC_SEQ_CNTL__CAC_EN_MASK;
3381                         cgs_write_register(hwmgr->device, mmMC_SEQ_CNTL, val2);
3382                 }
3383                 /* Set MC_CONFIG_MCD back to its default setting val0 */
3384                 cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val0);
3385
3386                 PP_ASSERT_WITH_CODE(
3387                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3388                                                 PPSMC_MSG_MCLKDPM_Enable)),
3389                                 "Failed to enable MCLK DPM during DPM Start Function!",
3390                                 return -1);
3391         }
3392         return 0;
3393 }
3394
3395 static int fiji_start_dpm(struct pp_hwmgr *hwmgr)
3396 {
3397         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3398
3399         /*enable general power management */
3400         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3401                         GLOBAL_PWRMGT_EN, 1);
3402         /* enable sclk deep sleep */
3403         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
3404                         DYNAMIC_PM_EN, 1);
3405         /* prepare for PCIE DPM */
3406         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3407                         data->soft_regs_start + offsetof(SMU73_SoftRegisters,
3408                                         VoltageChangeTimeout), 0x1000);
3409         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
3410                         SWRST_COMMAND_1, RESETLC, 0x0);
3411
3412         PP_ASSERT_WITH_CODE(
3413                         (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3414                                         PPSMC_MSG_Voltage_Cntl_Enable)),
3415                         "Failed to enable voltage DPM during DPM Start Function!",
3416                         return -1);
3417
3418         if (fiji_enable_sclk_mclk_dpm(hwmgr)) {
3419                 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
3420                 return -1;
3421         }
3422
3423         /* enable PCIE dpm */
3424         if(!data->pcie_dpm_key_disabled) {
3425                 PP_ASSERT_WITH_CODE(
3426                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3427                                                 PPSMC_MSG_PCIeDPM_Enable)),
3428                                 "Failed to enable pcie DPM during DPM Start Function!",
3429                                 return -1);
3430         }
3431
3432         return 0;
3433 }
3434
3435 static int fiji_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3436 {
3437         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3438
3439         /* disable SCLK dpm */
3440         if (!data->sclk_dpm_key_disabled)
3441                 PP_ASSERT_WITH_CODE(
3442                                 (smum_send_msg_to_smc(hwmgr->smumgr,
3443                                                 PPSMC_MSG_DPM_Disable) == 0),
3444                                 "Failed to disable SCLK DPM!",
3445                                 return -1);
3446
3447         /* disable MCLK dpm */
3448         if (!data->mclk_dpm_key_disabled) {
3449                 PP_ASSERT_WITH_CODE(
3450                                 (smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3451                                 PPSMC_MSG_MCLKDPM_SetEnabledMask, 1) == 0),
3452                                 "Failed to force MCLK DPM0!",
3453                                 return -1);
3454
3455                 PP_ASSERT_WITH_CODE(
3456                                 (smum_send_msg_to_smc(hwmgr->smumgr,
3457                                                 PPSMC_MSG_MCLKDPM_Disable) == 0),
3458                                 "Failed to disable MCLK DPM!",
3459                                 return -1);
3460         }
3461
3462         return 0;
3463 }
3464
3465 static int fiji_stop_dpm(struct pp_hwmgr *hwmgr)
3466 {
3467         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3468
3469         /* disable general power management */
3470         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3471                         GLOBAL_PWRMGT_EN, 0);
3472         /* disable sclk deep sleep */
3473         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
3474                         DYNAMIC_PM_EN, 0);
3475
3476         /* disable PCIE dpm */
3477         if (!data->pcie_dpm_key_disabled) {
3478                 PP_ASSERT_WITH_CODE(
3479                                 (smum_send_msg_to_smc(hwmgr->smumgr,
3480                                                 PPSMC_MSG_PCIeDPM_Disable) == 0),
3481                                 "Failed to disable pcie DPM during DPM Stop Function!",
3482                                 return -1);
3483         }
3484
3485         if (fiji_disable_sclk_mclk_dpm(hwmgr)) {
3486                 printk(KERN_ERR "Failed to disable Sclk DPM and Mclk DPM!");
3487                 return -1;
3488         }
3489
3490         PP_ASSERT_WITH_CODE(
3491                         (smum_send_msg_to_smc(hwmgr->smumgr,
3492                                         PPSMC_MSG_Voltage_Cntl_Disable) == 0),
3493                         "Failed to disable voltage DPM during DPM Stop Function!",
3494                         return -1);
3495
3496         return 0;
3497 }
3498
3499 static void fiji_set_dpm_event_sources(struct pp_hwmgr *hwmgr,
3500                 uint32_t sources)
3501 {
3502         bool protection;
3503         enum DPM_EVENT_SRC src;
3504
3505         switch (sources) {
3506         default:
3507                 printk(KERN_ERR "Unknown throttling event sources.");
3508                 /* fall through */
3509         case 0:
3510                 protection = false;
3511                 /* src is unused */
3512                 break;
3513         case (1 << PHM_AutoThrottleSource_Thermal):
3514                 protection = true;
3515                 src = DPM_EVENT_SRC_DIGITAL;
3516                 break;
3517         case (1 << PHM_AutoThrottleSource_External):
3518                 protection = true;
3519                 src = DPM_EVENT_SRC_EXTERNAL;
3520                 break;
3521         case (1 << PHM_AutoThrottleSource_External) |
3522                         (1 << PHM_AutoThrottleSource_Thermal):
3523                 protection = true;
3524                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
3525                 break;
3526         }
3527         /* Order matters - don't enable thermal protection for the wrong source. */
3528         if (protection) {
3529                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
3530                                 DPM_EVENT_SRC, src);
3531                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3532                                 THERMAL_PROTECTION_DIS,
3533                                 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3534                                                 PHM_PlatformCaps_ThermalController));
3535         } else
3536                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3537                                 THERMAL_PROTECTION_DIS, 1);
3538 }
3539
3540 static int fiji_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
3541                 PHM_AutoThrottleSource source)
3542 {
3543         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3544
3545         if (!(data->active_auto_throttle_sources & (1 << source))) {
3546                 data->active_auto_throttle_sources |= 1 << source;
3547                 fiji_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
3548         }
3549         return 0;
3550 }
3551
3552 static int fiji_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
3553 {
3554         return fiji_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
3555 }
3556
3557 static int fiji_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
3558                 PHM_AutoThrottleSource source)
3559 {
3560         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3561
3562         if (data->active_auto_throttle_sources & (1 << source)) {
3563                 data->active_auto_throttle_sources &= ~(1 << source);
3564                 fiji_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
3565         }
3566         return 0;
3567 }
3568
3569 static int fiji_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
3570 {
3571         return fiji_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
3572 }
3573
3574 static int fiji_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
3575 {
3576         int tmp_result, result = 0;
3577
3578         tmp_result = (!fiji_is_dpm_running(hwmgr))? 0 : -1;
3579         PP_ASSERT_WITH_CODE(result == 0,
3580                         "DPM is already running right now, no need to enable DPM!",
3581                         return 0);
3582
3583         if (fiji_voltage_control(hwmgr)) {
3584                 tmp_result = fiji_enable_voltage_control(hwmgr);
3585                 PP_ASSERT_WITH_CODE(tmp_result == 0,
3586                                 "Failed to enable voltage control!",
3587                                 result = tmp_result);
3588         }
3589
3590         if (fiji_voltage_control(hwmgr)) {
3591                 tmp_result = fiji_construct_voltage_tables(hwmgr);
3592                 PP_ASSERT_WITH_CODE((0 == tmp_result),
3593                                 "Failed to contruct voltage tables!",
3594                                 result = tmp_result);
3595         }
3596
3597         tmp_result = fiji_initialize_mc_reg_table(hwmgr);
3598         PP_ASSERT_WITH_CODE((0 == tmp_result),
3599                         "Failed to initialize MC reg table!", result = tmp_result);
3600
3601         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3602                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
3603                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3604                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
3605
3606         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3607                         PHM_PlatformCaps_ThermalController))
3608                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3609                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
3610
3611         tmp_result = fiji_program_static_screen_threshold_parameters(hwmgr);
3612         PP_ASSERT_WITH_CODE((0 == tmp_result),
3613                         "Failed to program static screen threshold parameters!",
3614                         result = tmp_result);
3615
3616         tmp_result = fiji_enable_display_gap(hwmgr);
3617         PP_ASSERT_WITH_CODE((0 == tmp_result),
3618                         "Failed to enable display gap!", result = tmp_result);
3619
3620         tmp_result = fiji_program_voting_clients(hwmgr);
3621         PP_ASSERT_WITH_CODE((0 == tmp_result),
3622                         "Failed to program voting clients!", result = tmp_result);
3623
3624         tmp_result = fiji_process_firmware_header(hwmgr);
3625         PP_ASSERT_WITH_CODE((0 == tmp_result),
3626                         "Failed to process firmware header!", result = tmp_result);
3627
3628         tmp_result = fiji_initial_switch_from_arbf0_to_f1(hwmgr);
3629         PP_ASSERT_WITH_CODE((0 == tmp_result),
3630                         "Failed to initialize switch from ArbF0 to F1!",
3631                         result = tmp_result);
3632
3633         tmp_result = fiji_init_smc_table(hwmgr);
3634         PP_ASSERT_WITH_CODE((0 == tmp_result),
3635                         "Failed to initialize SMC table!", result = tmp_result);
3636
3637         tmp_result = fiji_init_arb_table_index(hwmgr);
3638         PP_ASSERT_WITH_CODE((0 == tmp_result),
3639                         "Failed to initialize ARB table index!", result = tmp_result);
3640
3641         tmp_result = fiji_populate_pm_fuses(hwmgr);
3642         PP_ASSERT_WITH_CODE((0 == tmp_result),
3643                         "Failed to populate PM fuses!", result = tmp_result);
3644
3645         tmp_result = fiji_enable_vrhot_gpio_interrupt(hwmgr);
3646         PP_ASSERT_WITH_CODE((0 == tmp_result),
3647                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
3648
3649         tmp_result = tonga_notify_smc_display_change(hwmgr, false);
3650         PP_ASSERT_WITH_CODE((0 == tmp_result),
3651                         "Failed to notify no display!", result = tmp_result);
3652
3653         tmp_result = fiji_enable_sclk_control(hwmgr);
3654         PP_ASSERT_WITH_CODE((0 == tmp_result),
3655                         "Failed to enable SCLK control!", result = tmp_result);
3656
3657         tmp_result = fiji_enable_ulv(hwmgr);
3658         PP_ASSERT_WITH_CODE((0 == tmp_result),
3659                         "Failed to enable ULV!", result = tmp_result);
3660
3661         tmp_result = fiji_enable_deep_sleep_master_switch(hwmgr);
3662         PP_ASSERT_WITH_CODE((0 == tmp_result),
3663                         "Failed to enable deep sleep master switch!", result = tmp_result);
3664
3665         tmp_result = fiji_start_dpm(hwmgr);
3666         PP_ASSERT_WITH_CODE((0 == tmp_result),
3667                         "Failed to start DPM!", result = tmp_result);
3668
3669         tmp_result = fiji_enable_smc_cac(hwmgr);
3670         PP_ASSERT_WITH_CODE((0 == tmp_result),
3671                         "Failed to enable SMC CAC!", result = tmp_result);
3672
3673         tmp_result = fiji_enable_power_containment(hwmgr);
3674         PP_ASSERT_WITH_CODE((0 == tmp_result),
3675                         "Failed to enable power containment!", result = tmp_result);
3676
3677         tmp_result = fiji_power_control_set_level(hwmgr);
3678         PP_ASSERT_WITH_CODE((0 == tmp_result),
3679                         "Failed to power control set level!", result = tmp_result);
3680
3681         tmp_result = fiji_enable_thermal_auto_throttle(hwmgr);
3682         PP_ASSERT_WITH_CODE((0 == tmp_result),
3683                         "Failed to enable thermal auto throttle!", result = tmp_result);
3684
3685         return result;
3686 }
3687
3688 static int fiji_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
3689 {
3690         int tmp_result, result = 0;
3691
3692         tmp_result = (fiji_is_dpm_running(hwmgr)) ? 0 : -1;
3693         PP_ASSERT_WITH_CODE(tmp_result == 0,
3694                         "DPM is not running right now, no need to disable DPM!",
3695                         return 0);
3696
3697         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3698                         PHM_PlatformCaps_ThermalController))
3699                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3700                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
3701
3702         tmp_result = fiji_disable_power_containment(hwmgr);
3703         PP_ASSERT_WITH_CODE((tmp_result == 0),
3704                         "Failed to disable power containment!", result = tmp_result);
3705
3706         tmp_result = fiji_disable_smc_cac(hwmgr);
3707         PP_ASSERT_WITH_CODE((tmp_result == 0),
3708                         "Failed to disable SMC CAC!", result = tmp_result);
3709
3710         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3711                         CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
3712         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3713                         GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
3714
3715         tmp_result = fiji_disable_thermal_auto_throttle(hwmgr);
3716         PP_ASSERT_WITH_CODE((tmp_result == 0),
3717                         "Failed to disable thermal auto throttle!", result = tmp_result);
3718
3719         tmp_result = fiji_stop_dpm(hwmgr);
3720         PP_ASSERT_WITH_CODE((tmp_result == 0),
3721                         "Failed to stop DPM!", result = tmp_result);
3722
3723         tmp_result = fiji_disable_deep_sleep_master_switch(hwmgr);
3724         PP_ASSERT_WITH_CODE((tmp_result == 0),
3725                         "Failed to disable deep sleep master switch!", result = tmp_result);
3726
3727         tmp_result = fiji_disable_ulv(hwmgr);
3728         PP_ASSERT_WITH_CODE((tmp_result == 0),
3729                         "Failed to disable ULV!", result = tmp_result);
3730
3731         tmp_result = fiji_clear_voting_clients(hwmgr);
3732         PP_ASSERT_WITH_CODE((tmp_result == 0),
3733                         "Failed to clear voting clients!", result = tmp_result);
3734
3735         tmp_result = fiji_reset_to_default(hwmgr);
3736         PP_ASSERT_WITH_CODE((tmp_result == 0),
3737                         "Failed to reset to default!", result = tmp_result);
3738
3739         tmp_result = fiji_force_switch_to_arbf0(hwmgr);
3740         PP_ASSERT_WITH_CODE((tmp_result == 0),
3741                         "Failed to force to switch arbf0!", result = tmp_result);
3742
3743         return result;
3744 }
3745
3746 static int fiji_force_dpm_highest(struct pp_hwmgr *hwmgr)
3747 {
3748         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3749         uint32_t level, tmp;
3750
3751         if (!data->sclk_dpm_key_disabled) {
3752                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3753                         level = 0;
3754                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3755                         while (tmp >>= 1)
3756                                 level++;
3757                         if (level)
3758                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3759                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3760                                                 (1 << level));
3761                 }
3762         }
3763
3764         if (!data->mclk_dpm_key_disabled) {
3765                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3766                         level = 0;
3767                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3768                         while (tmp >>= 1)
3769                                 level++;
3770                         if (level)
3771                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3772                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3773                                                 (1 << level));
3774                 }
3775         }
3776
3777         if (!data->pcie_dpm_key_disabled) {
3778                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3779                         level = 0;
3780                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3781                         while (tmp >>= 1)
3782                                 level++;
3783                         if (level)
3784                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3785                                                 PPSMC_MSG_PCIeDPM_ForceLevel,
3786                                                 (1 << level));
3787                 }
3788         }
3789         return 0;
3790 }
3791
3792 static int fiji_upload_dpmlevel_enable_mask(struct pp_hwmgr *hwmgr)
3793 {
3794         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3795
3796         phm_apply_dal_min_voltage_request(hwmgr);
3797
3798         if (!data->sclk_dpm_key_disabled) {
3799                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3800                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3801                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
3802                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3803         }
3804         return 0;
3805 }
3806
3807 static int fiji_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3808 {
3809         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3810
3811         if (!fiji_is_dpm_running(hwmgr))
3812                 return -EINVAL;
3813
3814         if (!data->pcie_dpm_key_disabled) {
3815                 smum_send_msg_to_smc(hwmgr->smumgr,
3816                                 PPSMC_MSG_PCIeDPM_UnForceLevel);
3817         }
3818
3819         return fiji_upload_dpmlevel_enable_mask(hwmgr);
3820 }
3821
3822 static uint32_t fiji_get_lowest_enabled_level(
3823                 struct pp_hwmgr *hwmgr, uint32_t mask)
3824 {
3825         uint32_t level = 0;
3826
3827         while(0 == (mask & (1 << level)))
3828                 level++;
3829
3830         return level;
3831 }
3832
3833 static int fiji_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3834 {
3835         struct fiji_hwmgr *data =
3836                         (struct fiji_hwmgr *)(hwmgr->backend);
3837         uint32_t level;
3838
3839         if (!data->sclk_dpm_key_disabled)
3840                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3841                         level = fiji_get_lowest_enabled_level(hwmgr,
3842                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3843                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3844                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
3845                                                             (1 << level));
3846
3847         }
3848
3849         if (!data->mclk_dpm_key_disabled) {
3850                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3851                         level = fiji_get_lowest_enabled_level(hwmgr,
3852                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3853                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3854                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
3855                                                             (1 << level));
3856                 }
3857         }
3858
3859         if (!data->pcie_dpm_key_disabled) {
3860                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3861                         level = fiji_get_lowest_enabled_level(hwmgr,
3862                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3863                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3864                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
3865                                                             (1 << level));
3866                 }
3867         }
3868
3869         return 0;
3870
3871 }
3872 static int fiji_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
3873                                 enum amd_dpm_forced_level level)
3874 {
3875         int ret = 0;
3876
3877         switch (level) {
3878         case AMD_DPM_FORCED_LEVEL_HIGH:
3879                 ret = fiji_force_dpm_highest(hwmgr);
3880                 if (ret)
3881                         return ret;
3882                 break;
3883         case AMD_DPM_FORCED_LEVEL_LOW:
3884                 ret = fiji_force_dpm_lowest(hwmgr);
3885                 if (ret)
3886                         return ret;
3887                 break;
3888         case AMD_DPM_FORCED_LEVEL_AUTO:
3889                 ret = fiji_unforce_dpm_levels(hwmgr);
3890                 if (ret)
3891                         return ret;
3892                 break;
3893         default:
3894                 break;
3895         }
3896
3897         hwmgr->dpm_level = level;
3898
3899         return ret;
3900 }
3901
3902 static int fiji_get_power_state_size(struct pp_hwmgr *hwmgr)
3903 {
3904         return sizeof(struct fiji_power_state);
3905 }
3906
3907 static int fiji_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3908                 void *state, struct pp_power_state *power_state,
3909                 void *pp_table, uint32_t classification_flag)
3910 {
3911         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3912         struct fiji_power_state  *fiji_power_state =
3913                         (struct fiji_power_state *)(&(power_state->hardware));
3914         struct fiji_performance_level *performance_level;
3915         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3916         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3917                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3918         ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
3919                         (ATOM_Tonga_SCLK_Dependency_Table *)
3920                         (((unsigned long)powerplay_table) +
3921                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3922         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3923                         (ATOM_Tonga_MCLK_Dependency_Table *)
3924                         (((unsigned long)powerplay_table) +
3925                                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3926
3927         /* The following fields are not initialized here: id orderedList allStatesList */
3928         power_state->classification.ui_label =
3929                         (le16_to_cpu(state_entry->usClassification) &
3930                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3931                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3932         power_state->classification.flags = classification_flag;
3933         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3934
3935         power_state->classification.temporary_state = false;
3936         power_state->classification.to_be_deleted = false;
3937
3938         power_state->validation.disallowOnDC =
3939                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3940                                         ATOM_Tonga_DISALLOW_ON_DC));
3941
3942         power_state->pcie.lanes = 0;
3943
3944         power_state->display.disableFrameModulation = false;
3945         power_state->display.limitRefreshrate = false;
3946         power_state->display.enableVariBright =
3947                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3948                                         ATOM_Tonga_ENABLE_VARIBRIGHT));
3949
3950         power_state->validation.supportedPowerLevels = 0;
3951         power_state->uvd_clocks.VCLK = 0;
3952         power_state->uvd_clocks.DCLK = 0;
3953         power_state->temperatures.min = 0;
3954         power_state->temperatures.max = 0;
3955
3956         performance_level = &(fiji_power_state->performance_levels
3957                         [fiji_power_state->performance_level_count++]);
3958
3959         PP_ASSERT_WITH_CODE(
3960                         (fiji_power_state->performance_level_count < SMU73_MAX_LEVELS_GRAPHICS),
3961                         "Performance levels exceeds SMC limit!",
3962                         return -1);
3963
3964         PP_ASSERT_WITH_CODE(
3965                         (fiji_power_state->performance_level_count <=
3966                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3967                         "Performance levels exceeds Driver limit!",
3968                         return -1);
3969
3970         /* Performance levels are arranged from low to high. */
3971         performance_level->memory_clock = mclk_dep_table->entries
3972                         [state_entry->ucMemoryClockIndexLow].ulMclk;
3973         performance_level->engine_clock = sclk_dep_table->entries
3974                         [state_entry->ucEngineClockIndexLow].ulSclk;
3975         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3976                         state_entry->ucPCIEGenLow);
3977         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3978                         state_entry->ucPCIELaneHigh);
3979
3980         performance_level = &(fiji_power_state->performance_levels
3981                         [fiji_power_state->performance_level_count++]);
3982         performance_level->memory_clock = mclk_dep_table->entries
3983                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
3984         performance_level->engine_clock = sclk_dep_table->entries
3985                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3986         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3987                         state_entry->ucPCIEGenHigh);
3988         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3989                         state_entry->ucPCIELaneHigh);
3990
3991         return 0;
3992 }
3993
3994 static int fiji_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3995                 unsigned long entry_index, struct pp_power_state *state)
3996 {
3997         int result;
3998         struct fiji_power_state *ps;
3999         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4000         struct phm_ppt_v1_information *table_info =
4001                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4002         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
4003                         table_info->vdd_dep_on_mclk;
4004
4005         state->hardware.magic = PHM_VIslands_Magic;
4006
4007         ps = (struct fiji_power_state *)(&state->hardware);
4008
4009         result = get_powerplay_table_entry_v1_0(hwmgr, entry_index, state,
4010                         fiji_get_pp_table_entry_callback_func);
4011
4012         /* This is the earliest time we have all the dependency table and the VBIOS boot state
4013          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
4014          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
4015          */
4016         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
4017                 if (dep_mclk_table->entries[0].clk !=
4018                                 data->vbios_boot_state.mclk_bootup_value)
4019                         printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
4020                                         "does not match VBIOS boot MCLK level");
4021                 if (dep_mclk_table->entries[0].vddci !=
4022                                 data->vbios_boot_state.vddci_bootup_value)
4023                         printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
4024                                         "does not match VBIOS boot VDDCI level");
4025         }
4026
4027         /* set DC compatible flag if this state supports DC */
4028         if (!state->validation.disallowOnDC)
4029                 ps->dc_compatible = true;
4030
4031         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
4032                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
4033
4034         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
4035         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
4036
4037         if (!result) {
4038                 uint32_t i;
4039
4040                 switch (state->classification.ui_label) {
4041                 case PP_StateUILabel_Performance:
4042                         data->use_pcie_performance_levels = true;
4043
4044                         for (i = 0; i < ps->performance_level_count; i++) {
4045                                 if (data->pcie_gen_performance.max <
4046                                                 ps->performance_levels[i].pcie_gen)
4047                                         data->pcie_gen_performance.max =
4048                                                         ps->performance_levels[i].pcie_gen;
4049
4050                                 if (data->pcie_gen_performance.min >
4051                                                 ps->performance_levels[i].pcie_gen)
4052                                         data->pcie_gen_performance.min =
4053                                                         ps->performance_levels[i].pcie_gen;
4054
4055                                 if (data->pcie_lane_performance.max <
4056                                                 ps->performance_levels[i].pcie_lane)
4057                                         data->pcie_lane_performance.max =
4058                                                         ps->performance_levels[i].pcie_lane;
4059
4060                                 if (data->pcie_lane_performance.min >
4061                                                 ps->performance_levels[i].pcie_lane)
4062                                         data->pcie_lane_performance.min =
4063                                                         ps->performance_levels[i].pcie_lane;
4064                         }
4065                         break;
4066                 case PP_StateUILabel_Battery:
4067                         data->use_pcie_power_saving_levels = true;
4068
4069                         for (i = 0; i < ps->performance_level_count; i++) {
4070                                 if (data->pcie_gen_power_saving.max <
4071                                                 ps->performance_levels[i].pcie_gen)
4072                                         data->pcie_gen_power_saving.max =
4073                                                         ps->performance_levels[i].pcie_gen;
4074
4075                                 if (data->pcie_gen_power_saving.min >
4076                                                 ps->performance_levels[i].pcie_gen)
4077                                         data->pcie_gen_power_saving.min =
4078                                                         ps->performance_levels[i].pcie_gen;
4079
4080                                 if (data->pcie_lane_power_saving.max <
4081                                                 ps->performance_levels[i].pcie_lane)
4082                                         data->pcie_lane_power_saving.max =
4083                                                         ps->performance_levels[i].pcie_lane;
4084
4085                                 if (data->pcie_lane_power_saving.min >
4086                                                 ps->performance_levels[i].pcie_lane)
4087                                         data->pcie_lane_power_saving.min =
4088                                                         ps->performance_levels[i].pcie_lane;
4089                         }
4090                         break;
4091                 default:
4092                         break;
4093                 }
4094         }
4095         return 0;
4096 }
4097
4098 static int fiji_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
4099                                 struct pp_power_state  *request_ps,
4100                         const struct pp_power_state *current_ps)
4101 {
4102         struct fiji_power_state *fiji_ps =
4103                                 cast_phw_fiji_power_state(&request_ps->hardware);
4104         uint32_t sclk;
4105         uint32_t mclk;
4106         struct PP_Clocks minimum_clocks = {0};
4107         bool disable_mclk_switching;
4108         bool disable_mclk_switching_for_frame_lock;
4109         struct cgs_display_info info = {0};
4110         const struct phm_clock_and_voltage_limits *max_limits;
4111         uint32_t i;
4112         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4113         struct phm_ppt_v1_information *table_info =
4114                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4115         int32_t count;
4116         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
4117
4118         data->battery_state = (PP_StateUILabel_Battery ==
4119                         request_ps->classification.ui_label);
4120
4121         PP_ASSERT_WITH_CODE(fiji_ps->performance_level_count == 2,
4122                                  "VI should always have 2 performance levels",);
4123
4124         max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
4125                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
4126                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
4127
4128         /* Cap clock DPM tables at DC MAX if it is in DC. */
4129         if (PP_PowerSource_DC == hwmgr->power_source) {
4130                 for (i = 0; i < fiji_ps->performance_level_count; i++) {
4131                         if (fiji_ps->performance_levels[i].memory_clock > max_limits->mclk)
4132                                 fiji_ps->performance_levels[i].memory_clock = max_limits->mclk;
4133                         if (fiji_ps->performance_levels[i].engine_clock > max_limits->sclk)
4134                                 fiji_ps->performance_levels[i].engine_clock = max_limits->sclk;
4135                 }
4136         }
4137
4138         fiji_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
4139         fiji_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
4140
4141         fiji_ps->acp_clk = hwmgr->acp_arbiter.acpclk;
4142
4143         cgs_get_active_displays_info(hwmgr->device, &info);
4144
4145         /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
4146
4147         /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
4148
4149         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4150                         PHM_PlatformCaps_StablePState)) {
4151                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
4152                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
4153
4154                 for (count = table_info->vdd_dep_on_sclk->count - 1;
4155                                 count >= 0; count--) {
4156                         if (stable_pstate_sclk >=
4157                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
4158                                 stable_pstate_sclk =
4159                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
4160                                 break;
4161                         }
4162                 }
4163
4164                 if (count < 0)
4165                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
4166
4167                 stable_pstate_mclk = max_limits->mclk;
4168
4169                 minimum_clocks.engineClock = stable_pstate_sclk;
4170                 minimum_clocks.memoryClock = stable_pstate_mclk;
4171         }
4172
4173         if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
4174                 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
4175
4176         if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
4177                 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
4178
4179         fiji_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
4180
4181         if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
4182                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
4183                                 hwmgr->platform_descriptor.overdriveLimit.engineClock),
4184                                 "Overdrive sclk exceeds limit",
4185                                 hwmgr->gfx_arbiter.sclk_over_drive =
4186                                                 hwmgr->platform_descriptor.overdriveLimit.engineClock);
4187
4188                 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
4189                         fiji_ps->performance_levels[1].engine_clock =
4190                                         hwmgr->gfx_arbiter.sclk_over_drive;
4191         }
4192
4193         if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
4194                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
4195                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
4196                                 "Overdrive mclk exceeds limit",
4197                                 hwmgr->gfx_arbiter.mclk_over_drive =
4198                                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
4199
4200                 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
4201                         fiji_ps->performance_levels[1].memory_clock =
4202                                         hwmgr->gfx_arbiter.mclk_over_drive;
4203         }
4204
4205         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
4206                                     hwmgr->platform_descriptor.platformCaps,
4207                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
4208
4209         disable_mclk_switching = (1 < info.display_count) ||
4210                                     disable_mclk_switching_for_frame_lock;
4211
4212         sclk = fiji_ps->performance_levels[0].engine_clock;
4213         mclk = fiji_ps->performance_levels[0].memory_clock;
4214
4215         if (disable_mclk_switching)
4216                 mclk = fiji_ps->performance_levels
4217                 [fiji_ps->performance_level_count - 1].memory_clock;
4218
4219         if (sclk < minimum_clocks.engineClock)
4220                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
4221                                 max_limits->sclk : minimum_clocks.engineClock;
4222
4223         if (mclk < minimum_clocks.memoryClock)
4224                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
4225                                 max_limits->mclk : minimum_clocks.memoryClock;
4226
4227         fiji_ps->performance_levels[0].engine_clock = sclk;
4228         fiji_ps->performance_levels[0].memory_clock = mclk;
4229
4230         fiji_ps->performance_levels[1].engine_clock =
4231                 (fiji_ps->performance_levels[1].engine_clock >=
4232                                 fiji_ps->performance_levels[0].engine_clock) ?
4233                                                 fiji_ps->performance_levels[1].engine_clock :
4234                                                 fiji_ps->performance_levels[0].engine_clock;
4235
4236         if (disable_mclk_switching) {
4237                 if (mclk < fiji_ps->performance_levels[1].memory_clock)
4238                         mclk = fiji_ps->performance_levels[1].memory_clock;
4239
4240                 fiji_ps->performance_levels[0].memory_clock = mclk;
4241                 fiji_ps->performance_levels[1].memory_clock = mclk;
4242         } else {
4243                 if (fiji_ps->performance_levels[1].memory_clock <
4244                                 fiji_ps->performance_levels[0].memory_clock)
4245                         fiji_ps->performance_levels[1].memory_clock =
4246                                         fiji_ps->performance_levels[0].memory_clock;
4247         }
4248
4249         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4250                         PHM_PlatformCaps_StablePState)) {
4251                 for (i = 0; i < fiji_ps->performance_level_count; i++) {
4252                         fiji_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
4253                         fiji_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
4254                         fiji_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
4255                         fiji_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
4256                 }
4257         }
4258
4259         return 0;
4260 }
4261
4262 static int fiji_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
4263 {
4264         const struct phm_set_power_state_input *states =
4265                         (const struct phm_set_power_state_input *)input;
4266         const struct fiji_power_state *fiji_ps =
4267                         cast_const_phw_fiji_power_state(states->pnew_state);
4268         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4269         struct fiji_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4270         uint32_t sclk = fiji_ps->performance_levels
4271                         [fiji_ps->performance_level_count - 1].engine_clock;
4272         struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4273         uint32_t mclk = fiji_ps->performance_levels
4274                         [fiji_ps->performance_level_count - 1].memory_clock;
4275         uint32_t i;
4276         struct cgs_display_info info = {0};
4277
4278         data->need_update_smu7_dpm_table = 0;
4279
4280         for (i = 0; i < sclk_table->count; i++) {
4281                 if (sclk == sclk_table->dpm_levels[i].value)
4282                         break;
4283         }
4284
4285         if (i >= sclk_table->count)
4286                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4287         else {
4288                 if(data->display_timing.min_clock_in_sr !=
4289                         hwmgr->display_config.min_core_set_clock_in_sr)
4290                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4291         }
4292
4293         for (i = 0; i < mclk_table->count; i++) {
4294                 if (mclk == mclk_table->dpm_levels[i].value)
4295                         break;
4296         }
4297
4298         if (i >= mclk_table->count)
4299                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4300
4301         cgs_get_active_displays_info(hwmgr->device, &info);
4302
4303         if (data->display_timing.num_existing_displays != info.display_count)
4304                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4305
4306         return 0;
4307 }
4308
4309 static uint16_t fiji_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
4310                 const struct fiji_power_state *fiji_ps)
4311 {
4312         uint32_t i;
4313         uint32_t sclk, max_sclk = 0;
4314         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4315         struct fiji_dpm_table *dpm_table = &data->dpm_table;
4316
4317         for (i = 0; i < fiji_ps->performance_level_count; i++) {
4318                 sclk = fiji_ps->performance_levels[i].engine_clock;
4319                 if (max_sclk < sclk)
4320                         max_sclk = sclk;
4321         }
4322
4323         for (i = 0; i < dpm_table->sclk_table.count; i++) {
4324                 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
4325                         return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
4326                                         dpm_table->pcie_speed_table.dpm_levels
4327                                         [dpm_table->pcie_speed_table.count - 1].value :
4328                                         dpm_table->pcie_speed_table.dpm_levels[i].value);
4329         }
4330
4331         return 0;
4332 }
4333
4334 static int fiji_request_link_speed_change_before_state_change(
4335                 struct pp_hwmgr *hwmgr, const void *input)
4336 {
4337         const struct phm_set_power_state_input *states =
4338                         (const struct phm_set_power_state_input *)input;
4339         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4340         const struct fiji_power_state *fiji_nps =
4341                         cast_const_phw_fiji_power_state(states->pnew_state);
4342         const struct fiji_power_state *fiji_cps =
4343                         cast_const_phw_fiji_power_state(states->pcurrent_state);
4344
4345         uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_nps);
4346         uint16_t current_link_speed;
4347
4348         if (data->force_pcie_gen == PP_PCIEGenInvalid)
4349                 current_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_cps);
4350         else
4351                 current_link_speed = data->force_pcie_gen;
4352
4353         data->force_pcie_gen = PP_PCIEGenInvalid;
4354         data->pspp_notify_required = false;
4355         if (target_link_speed > current_link_speed) {
4356                 switch(target_link_speed) {
4357                 case PP_PCIEGen3:
4358                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
4359                                 break;
4360                         data->force_pcie_gen = PP_PCIEGen2;
4361                         if (current_link_speed == PP_PCIEGen2)
4362                                 break;
4363                 case PP_PCIEGen2:
4364                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
4365                                 break;
4366                 default:
4367                         data->force_pcie_gen = fiji_get_current_pcie_speed(hwmgr);
4368                         break;
4369                 }
4370         } else {
4371                 if (target_link_speed < current_link_speed)
4372                         data->pspp_notify_required = true;
4373         }
4374
4375         return 0;
4376 }
4377
4378 static int fiji_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4379 {
4380         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4381
4382         if (0 == data->need_update_smu7_dpm_table)
4383                 return 0;
4384
4385         if ((0 == data->sclk_dpm_key_disabled) &&
4386                 (data->need_update_smu7_dpm_table &
4387                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4388                 PP_ASSERT_WITH_CODE(fiji_is_dpm_running(hwmgr),
4389                                     "Trying to freeze SCLK DPM when DPM is disabled",
4390                                     );
4391                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4392                                 PPSMC_MSG_SCLKDPM_FreezeLevel),
4393                                 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4394                                 return -1);
4395         }
4396
4397         if ((0 == data->mclk_dpm_key_disabled) &&
4398                 (data->need_update_smu7_dpm_table &
4399                  DPMTABLE_OD_UPDATE_MCLK)) {
4400                 PP_ASSERT_WITH_CODE(fiji_is_dpm_running(hwmgr),
4401                                     "Trying to freeze MCLK DPM when DPM is disabled",
4402                                     );
4403                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4404                                 PPSMC_MSG_MCLKDPM_FreezeLevel),
4405                                 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4406                                 return -1);
4407         }
4408
4409         return 0;
4410 }
4411
4412 static int fiji_populate_and_upload_sclk_mclk_dpm_levels(
4413                 struct pp_hwmgr *hwmgr, const void *input)
4414 {
4415         int result = 0;
4416         const struct phm_set_power_state_input *states =
4417                         (const struct phm_set_power_state_input *)input;
4418         const struct fiji_power_state *fiji_ps =
4419                         cast_const_phw_fiji_power_state(states->pnew_state);
4420         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4421         uint32_t sclk = fiji_ps->performance_levels
4422                         [fiji_ps->performance_level_count - 1].engine_clock;
4423         uint32_t mclk = fiji_ps->performance_levels
4424                         [fiji_ps->performance_level_count - 1].memory_clock;
4425         struct fiji_dpm_table *dpm_table = &data->dpm_table;
4426
4427         struct fiji_dpm_table *golden_dpm_table = &data->golden_dpm_table;
4428         uint32_t dpm_count, clock_percent;
4429         uint32_t i;
4430
4431         if (0 == data->need_update_smu7_dpm_table)
4432                 return 0;
4433
4434         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4435                 dpm_table->sclk_table.dpm_levels
4436                 [dpm_table->sclk_table.count - 1].value = sclk;
4437
4438                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4439                                 PHM_PlatformCaps_OD6PlusinACSupport) ||
4440                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4441                                         PHM_PlatformCaps_OD6PlusinDCSupport)) {
4442                 /* Need to do calculation based on the golden DPM table
4443                  * as the Heatmap GPU Clock axis is also based on the default values
4444                  */
4445                         PP_ASSERT_WITH_CODE(
4446                                 (golden_dpm_table->sclk_table.dpm_levels
4447                                                 [golden_dpm_table->sclk_table.count - 1].value != 0),
4448                                 "Divide by 0!",
4449                                 return -1);
4450                         dpm_count = dpm_table->sclk_table.count < 2 ?
4451                                         0 : dpm_table->sclk_table.count - 2;
4452                         for (i = dpm_count; i > 1; i--) {
4453                                 if (sclk > golden_dpm_table->sclk_table.dpm_levels
4454                                                 [golden_dpm_table->sclk_table.count-1].value) {
4455                                         clock_percent =
4456                                                 ((sclk - golden_dpm_table->sclk_table.dpm_levels
4457                                                         [golden_dpm_table->sclk_table.count-1].value) * 100) /
4458                                                 golden_dpm_table->sclk_table.dpm_levels
4459                                                         [golden_dpm_table->sclk_table.count-1].value;
4460
4461                                         dpm_table->sclk_table.dpm_levels[i].value =
4462                                                         golden_dpm_table->sclk_table.dpm_levels[i].value +
4463                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
4464                                                                 clock_percent)/100;
4465
4466                                 } else if (golden_dpm_table->sclk_table.dpm_levels
4467                                                 [dpm_table->sclk_table.count-1].value > sclk) {
4468                                         clock_percent =
4469                                                 ((golden_dpm_table->sclk_table.dpm_levels
4470                                                 [golden_dpm_table->sclk_table.count - 1].value - sclk) *
4471                                                                 100) /
4472                                                 golden_dpm_table->sclk_table.dpm_levels
4473                                                         [golden_dpm_table->sclk_table.count-1].value;
4474
4475                                         dpm_table->sclk_table.dpm_levels[i].value =
4476                                                         golden_dpm_table->sclk_table.dpm_levels[i].value -
4477                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
4478                                                                         clock_percent) / 100;
4479                                 } else
4480                                         dpm_table->sclk_table.dpm_levels[i].value =
4481                                                         golden_dpm_table->sclk_table.dpm_levels[i].value;
4482                         }
4483                 }
4484         }
4485
4486         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4487                 dpm_table->mclk_table.dpm_levels
4488                         [dpm_table->mclk_table.count - 1].value = mclk;
4489                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4490                                 PHM_PlatformCaps_OD6PlusinACSupport) ||
4491                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4492                                 PHM_PlatformCaps_OD6PlusinDCSupport)) {
4493
4494                         PP_ASSERT_WITH_CODE(
4495                                         (golden_dpm_table->mclk_table.dpm_levels
4496                                                 [golden_dpm_table->mclk_table.count-1].value != 0),
4497                                         "Divide by 0!",
4498                                         return -1);
4499                         dpm_count = dpm_table->mclk_table.count < 2 ?
4500                                         0 : dpm_table->mclk_table.count - 2;
4501                         for (i = dpm_count; i > 1; i--) {
4502                                 if (mclk > golden_dpm_table->mclk_table.dpm_levels
4503                                                 [golden_dpm_table->mclk_table.count-1].value) {
4504                                         clock_percent = ((mclk -
4505                                                         golden_dpm_table->mclk_table.dpm_levels
4506                                                         [golden_dpm_table->mclk_table.count-1].value) * 100) /
4507                                                         golden_dpm_table->mclk_table.dpm_levels
4508                                                         [golden_dpm_table->mclk_table.count-1].value;
4509
4510                                         dpm_table->mclk_table.dpm_levels[i].value =
4511                                                         golden_dpm_table->mclk_table.dpm_levels[i].value +
4512                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4513                                                                         clock_percent) / 100;
4514
4515                                 } else if (golden_dpm_table->mclk_table.dpm_levels
4516                                                 [dpm_table->mclk_table.count-1].value > mclk) {
4517                                         clock_percent = ((golden_dpm_table->mclk_table.dpm_levels
4518                                                         [golden_dpm_table->mclk_table.count-1].value - mclk) * 100) /
4519                                                                         golden_dpm_table->mclk_table.dpm_levels
4520                                                                         [golden_dpm_table->mclk_table.count-1].value;
4521
4522                                         dpm_table->mclk_table.dpm_levels[i].value =
4523                                                         golden_dpm_table->mclk_table.dpm_levels[i].value -
4524                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4525                                                                         clock_percent) / 100;
4526                                 } else
4527                                         dpm_table->mclk_table.dpm_levels[i].value =
4528                                                         golden_dpm_table->mclk_table.dpm_levels[i].value;
4529                         }
4530                 }
4531         }
4532
4533         if (data->need_update_smu7_dpm_table &
4534                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4535                 result = fiji_populate_all_graphic_levels(hwmgr);
4536                 PP_ASSERT_WITH_CODE((0 == result),
4537                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4538                                 return result);
4539         }
4540
4541         if (data->need_update_smu7_dpm_table &
4542                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4543                 /*populate MCLK dpm table to SMU7 */
4544                 result = fiji_populate_all_memory_levels(hwmgr);
4545                 PP_ASSERT_WITH_CODE((0 == result),
4546                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4547                                 return result);
4548         }
4549
4550         return result;
4551 }
4552
4553 static int fiji_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4554                           struct fiji_single_dpm_table * dpm_table,
4555                              uint32_t low_limit, uint32_t high_limit)
4556 {
4557         uint32_t i;
4558
4559         for (i = 0; i < dpm_table->count; i++) {
4560                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
4561                     (dpm_table->dpm_levels[i].value > high_limit))
4562                         dpm_table->dpm_levels[i].enabled = false;
4563                 else
4564                         dpm_table->dpm_levels[i].enabled = true;
4565         }
4566         return 0;
4567 }
4568
4569 static int fiji_trim_dpm_states(struct pp_hwmgr *hwmgr,
4570                 const struct fiji_power_state *fiji_ps)
4571 {
4572         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4573         uint32_t high_limit_count;
4574
4575         PP_ASSERT_WITH_CODE((fiji_ps->performance_level_count >= 1),
4576                         "power state did not have any performance level",
4577                         return -1);
4578
4579         high_limit_count = (1 == fiji_ps->performance_level_count) ? 0 : 1;
4580
4581         fiji_trim_single_dpm_states(hwmgr,
4582                         &(data->dpm_table.sclk_table),
4583                         fiji_ps->performance_levels[0].engine_clock,
4584                         fiji_ps->performance_levels[high_limit_count].engine_clock);
4585
4586         fiji_trim_single_dpm_states(hwmgr,
4587                         &(data->dpm_table.mclk_table),
4588                         fiji_ps->performance_levels[0].memory_clock,
4589                         fiji_ps->performance_levels[high_limit_count].memory_clock);
4590
4591         return 0;
4592 }
4593
4594 static int fiji_generate_dpm_level_enable_mask(
4595                 struct pp_hwmgr *hwmgr, const void *input)
4596 {
4597         int result;
4598         const struct phm_set_power_state_input *states =
4599                         (const struct phm_set_power_state_input *)input;
4600         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4601         const struct fiji_power_state *fiji_ps =
4602                         cast_const_phw_fiji_power_state(states->pnew_state);
4603
4604         result = fiji_trim_dpm_states(hwmgr, fiji_ps);
4605         if (result)
4606                 return result;
4607
4608         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4609                         fiji_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4610         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4611                         fiji_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4612         data->last_mclk_dpm_enable_mask =
4613                         data->dpm_level_enable_mask.mclk_dpm_enable_mask;
4614
4615         if (data->uvd_enabled) {
4616                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4617                         data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4618         }
4619
4620         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4621                         fiji_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4622
4623         return 0;
4624 }
4625
4626 static int fiji_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4627 {
4628         return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4629                                   (PPSMC_Msg)PPSMC_MSG_UVDDPM_Enable :
4630                                   (PPSMC_Msg)PPSMC_MSG_UVDDPM_Disable);
4631 }
4632
4633 int fiji_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4634 {
4635         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4636                         PPSMC_MSG_VCEDPM_Enable :
4637                         PPSMC_MSG_VCEDPM_Disable);
4638 }
4639
4640 static int fiji_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4641 {
4642         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4643                         PPSMC_MSG_SAMUDPM_Enable :
4644                         PPSMC_MSG_SAMUDPM_Disable);
4645 }
4646
4647 static int fiji_enable_disable_acp_dpm(struct pp_hwmgr *hwmgr, bool enable)
4648 {
4649         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4650                         PPSMC_MSG_ACPDPM_Enable :
4651                         PPSMC_MSG_ACPDPM_Disable);
4652 }
4653
4654 int fiji_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4655 {
4656         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4657         uint32_t mm_boot_level_offset, mm_boot_level_value;
4658         struct phm_ppt_v1_information *table_info =
4659                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4660
4661         if (!bgate) {
4662                 data->smc_state_table.UvdBootLevel = 0;
4663                 if (table_info->mm_dep_table->count > 0)
4664                         data->smc_state_table.UvdBootLevel =
4665                                         (uint8_t) (table_info->mm_dep_table->count - 1);
4666                 mm_boot_level_offset = data->dpm_table_start +
4667                                 offsetof(SMU73_Discrete_DpmTable, UvdBootLevel);
4668                 mm_boot_level_offset /= 4;
4669                 mm_boot_level_offset *= 4;
4670                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4671                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4672                 mm_boot_level_value &= 0x00FFFFFF;
4673                 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4674                 cgs_write_ind_register(hwmgr->device,
4675                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4676
4677                 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4678                                 PHM_PlatformCaps_UVDDPM) ||
4679                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4680                                 PHM_PlatformCaps_StablePState))
4681                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4682                                         PPSMC_MSG_UVDDPM_SetEnabledMask,
4683                                         (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4684         }
4685
4686         return fiji_enable_disable_uvd_dpm(hwmgr, !bgate);
4687 }
4688
4689 int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4690 {
4691         const struct phm_set_power_state_input *states =
4692                         (const struct phm_set_power_state_input *)input;
4693         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4694         const struct fiji_power_state *fiji_nps =
4695                         cast_const_phw_fiji_power_state(states->pnew_state);
4696         const struct fiji_power_state *fiji_cps =
4697                         cast_const_phw_fiji_power_state(states->pcurrent_state);
4698
4699         uint32_t mm_boot_level_offset, mm_boot_level_value;
4700         struct phm_ppt_v1_information *table_info =
4701                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4702
4703         if (fiji_nps->vce_clks.evclk >0 &&
4704         (fiji_cps == NULL || fiji_cps->vce_clks.evclk == 0)) {
4705                 data->smc_state_table.VceBootLevel =
4706                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4707
4708                 mm_boot_level_offset = data->dpm_table_start +
4709                                 offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
4710                 mm_boot_level_offset /= 4;
4711                 mm_boot_level_offset *= 4;
4712                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4713                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4714                 mm_boot_level_value &= 0xFF00FFFF;
4715                 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4716                 cgs_write_ind_register(hwmgr->device,
4717                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4718
4719                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4720                                 PHM_PlatformCaps_StablePState)) {
4721                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4722                                         PPSMC_MSG_VCEDPM_SetEnabledMask,
4723                                         (uint32_t)1 << data->smc_state_table.VceBootLevel);
4724
4725                         fiji_enable_disable_vce_dpm(hwmgr, true);
4726                 } else if (fiji_nps->vce_clks.evclk == 0 &&
4727                                 fiji_cps != NULL &&
4728                                 fiji_cps->vce_clks.evclk > 0)
4729                         fiji_enable_disable_vce_dpm(hwmgr, false);
4730         }
4731
4732         return 0;
4733 }
4734
4735 int fiji_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4736 {
4737         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4738         uint32_t mm_boot_level_offset, mm_boot_level_value;
4739         struct phm_ppt_v1_information *table_info =
4740                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4741
4742         if (!bgate) {
4743                 data->smc_state_table.SamuBootLevel =
4744                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4745                 mm_boot_level_offset = data->dpm_table_start +
4746                                 offsetof(SMU73_Discrete_DpmTable, SamuBootLevel);
4747                 mm_boot_level_offset /= 4;
4748                 mm_boot_level_offset *= 4;
4749                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4750                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4751                 mm_boot_level_value &= 0xFFFFFF00;
4752                 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4753                 cgs_write_ind_register(hwmgr->device,
4754                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4755
4756                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4757                                 PHM_PlatformCaps_StablePState))
4758                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4759                                         PPSMC_MSG_SAMUDPM_SetEnabledMask,
4760                                         (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4761         }
4762
4763         return fiji_enable_disable_samu_dpm(hwmgr, !bgate);
4764 }
4765
4766 int fiji_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4767 {
4768         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4769         uint32_t mm_boot_level_offset, mm_boot_level_value;
4770         struct phm_ppt_v1_information *table_info =
4771                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4772
4773         if (!bgate) {
4774                 data->smc_state_table.AcpBootLevel =
4775                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4776                 mm_boot_level_offset = data->dpm_table_start +
4777                                 offsetof(SMU73_Discrete_DpmTable, AcpBootLevel);
4778                 mm_boot_level_offset /= 4;
4779                 mm_boot_level_offset *= 4;
4780                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4781                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4782                 mm_boot_level_value &= 0xFFFF00FF;
4783                 mm_boot_level_value |= data->smc_state_table.AcpBootLevel << 8;
4784                 cgs_write_ind_register(hwmgr->device,
4785                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4786
4787                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4788                                 PHM_PlatformCaps_StablePState))
4789                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4790                                                 PPSMC_MSG_ACPDPM_SetEnabledMask,
4791                                                 (uint32_t)(1 << data->smc_state_table.AcpBootLevel));
4792         }
4793
4794         return fiji_enable_disable_acp_dpm(hwmgr, !bgate);
4795 }
4796
4797 static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4798 {
4799         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4800
4801         int result = 0;
4802         uint32_t low_sclk_interrupt_threshold = 0;
4803
4804         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4805                         PHM_PlatformCaps_SclkThrottleLowNotification)
4806                 && (hwmgr->gfx_arbiter.sclk_threshold !=
4807                                 data->low_sclk_interrupt_threshold)) {
4808                 data->low_sclk_interrupt_threshold =
4809                                 hwmgr->gfx_arbiter.sclk_threshold;
4810                 low_sclk_interrupt_threshold =
4811                                 data->low_sclk_interrupt_threshold;
4812
4813                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4814
4815                 result = fiji_copy_bytes_to_smc(
4816                                 hwmgr->smumgr,
4817                                 data->dpm_table_start +
4818                                 offsetof(SMU73_Discrete_DpmTable,
4819                                         LowSclkInterruptThreshold),
4820                                 (uint8_t *)&low_sclk_interrupt_threshold,
4821                                 sizeof(uint32_t),
4822                                 data->sram_end);
4823         }
4824
4825         return result;
4826 }
4827
4828 static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4829 {
4830         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4831
4832         if (data->need_update_smu7_dpm_table &
4833                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4834                 return fiji_program_memory_timing_parameters(hwmgr);
4835
4836         return 0;
4837 }
4838
4839 static int fiji_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4840 {
4841         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4842
4843         if (0 == data->need_update_smu7_dpm_table)
4844                 return 0;
4845
4846         if ((0 == data->sclk_dpm_key_disabled) &&
4847                 (data->need_update_smu7_dpm_table &
4848                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4849
4850                 PP_ASSERT_WITH_CODE(fiji_is_dpm_running(hwmgr),
4851                                     "Trying to Unfreeze SCLK DPM when DPM is disabled",
4852                                     );
4853                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4854                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4855                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4856                         return -1);
4857         }
4858
4859         if ((0 == data->mclk_dpm_key_disabled) &&
4860                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4861
4862                 PP_ASSERT_WITH_CODE(fiji_is_dpm_running(hwmgr),
4863                                     "Trying to Unfreeze MCLK DPM when DPM is disabled",
4864                                     );
4865                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4866                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4867                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4868                     return -1);
4869         }
4870
4871         data->need_update_smu7_dpm_table = 0;
4872
4873         return 0;
4874 }
4875
4876 /* Look up the voltaged based on DAL's requested level.
4877  * and then send the requested VDDC voltage to SMC
4878  */
4879 static void fiji_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr)
4880 {
4881         return;
4882 }
4883
4884 static int fiji_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
4885 {
4886         int result;
4887         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4888
4889         /* Apply minimum voltage based on DAL's request level */
4890         fiji_apply_dal_minimum_voltage_request(hwmgr);
4891
4892         if (0 == data->sclk_dpm_key_disabled) {
4893                 /* Checking if DPM is running.  If we discover hang because of this,
4894                  *  we should skip this message.
4895                  */
4896                 if (!fiji_is_dpm_running(hwmgr))
4897                         printk(KERN_ERR "[ powerplay ] "
4898                                         "Trying to set Enable Mask when DPM is disabled \n");
4899
4900                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4901                         result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4902                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
4903                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
4904                         PP_ASSERT_WITH_CODE((0 == result),
4905                                 "Set Sclk Dpm enable Mask failed", return -1);
4906                 }
4907         }
4908
4909         if (0 == data->mclk_dpm_key_disabled) {
4910                 /* Checking if DPM is running.  If we discover hang because of this,
4911                  *  we should skip this message.
4912                  */
4913                 if (!fiji_is_dpm_running(hwmgr))
4914                         printk(KERN_ERR "[ powerplay ]"
4915                                         " Trying to set Enable Mask when DPM is disabled \n");
4916
4917                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4918                         result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4919                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
4920                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask);
4921                         PP_ASSERT_WITH_CODE((0 == result),
4922                                 "Set Mclk Dpm enable Mask failed", return -1);
4923                 }
4924         }
4925
4926         return 0;
4927 }
4928
4929 static int fiji_notify_link_speed_change_after_state_change(
4930                 struct pp_hwmgr *hwmgr, const void *input)
4931 {
4932         const struct phm_set_power_state_input *states =
4933                         (const struct phm_set_power_state_input *)input;
4934         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4935         const struct fiji_power_state *fiji_ps =
4936                         cast_const_phw_fiji_power_state(states->pnew_state);
4937         uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_ps);
4938         uint8_t  request;
4939
4940         if (data->pspp_notify_required) {
4941                 if (target_link_speed == PP_PCIEGen3)
4942                         request = PCIE_PERF_REQ_GEN3;
4943                 else if (target_link_speed == PP_PCIEGen2)
4944                         request = PCIE_PERF_REQ_GEN2;
4945                 else
4946                         request = PCIE_PERF_REQ_GEN1;
4947
4948                 if(request == PCIE_PERF_REQ_GEN1 &&
4949                                 fiji_get_current_pcie_speed(hwmgr) > 0)
4950                         return 0;
4951
4952                 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4953                         if (PP_PCIEGen2 == target_link_speed)
4954                                 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4955                         else
4956                                 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4957                 }
4958         }
4959
4960         return 0;
4961 }
4962
4963 static int fiji_set_power_state_tasks(struct pp_hwmgr *hwmgr,
4964                 const void *input)
4965 {
4966         int tmp_result, result = 0;
4967
4968         tmp_result = fiji_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4969         PP_ASSERT_WITH_CODE((0 == tmp_result),
4970                         "Failed to find DPM states clocks in DPM table!",
4971                         result = tmp_result);
4972
4973         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4974                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4975                 tmp_result =
4976                         fiji_request_link_speed_change_before_state_change(hwmgr, input);
4977                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4978                                 "Failed to request link speed change before state change!",
4979                                 result = tmp_result);
4980         }
4981
4982         tmp_result = fiji_freeze_sclk_mclk_dpm(hwmgr);
4983         PP_ASSERT_WITH_CODE((0 == tmp_result),
4984                         "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4985
4986         tmp_result = fiji_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4987         PP_ASSERT_WITH_CODE((0 == tmp_result),
4988                         "Failed to populate and upload SCLK MCLK DPM levels!",
4989                         result = tmp_result);
4990
4991         tmp_result = fiji_generate_dpm_level_enable_mask(hwmgr, input);
4992         PP_ASSERT_WITH_CODE((0 == tmp_result),
4993                         "Failed to generate DPM level enabled mask!",
4994                         result = tmp_result);
4995
4996         tmp_result = fiji_update_vce_dpm(hwmgr, input);
4997         PP_ASSERT_WITH_CODE((0 == tmp_result),
4998                         "Failed to update VCE DPM!",
4999                         result = tmp_result);
5000
5001         tmp_result = fiji_update_sclk_threshold(hwmgr);
5002         PP_ASSERT_WITH_CODE((0 == tmp_result),
5003                         "Failed to update SCLK threshold!",
5004                         result = tmp_result);
5005
5006         tmp_result = fiji_program_mem_timing_parameters(hwmgr);
5007         PP_ASSERT_WITH_CODE((0 == tmp_result),
5008                         "Failed to program memory timing parameters!",
5009                         result = tmp_result);
5010
5011         tmp_result = fiji_unfreeze_sclk_mclk_dpm(hwmgr);
5012         PP_ASSERT_WITH_CODE((0 == tmp_result),
5013                         "Failed to unfreeze SCLK MCLK DPM!",
5014                         result = tmp_result);
5015
5016         tmp_result = fiji_upload_dpm_level_enable_mask(hwmgr);
5017         PP_ASSERT_WITH_CODE((0 == tmp_result),
5018                         "Failed to upload DPM level enabled mask!",
5019                         result = tmp_result);
5020
5021         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
5022                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
5023                 tmp_result =
5024                         fiji_notify_link_speed_change_after_state_change(hwmgr, input);
5025                 PP_ASSERT_WITH_CODE((0 == tmp_result),
5026                                 "Failed to notify link speed change after state change!",
5027                                 result = tmp_result);
5028         }
5029
5030         return result;
5031 }
5032
5033 static int fiji_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
5034 {
5035         struct pp_power_state  *ps;
5036         struct fiji_power_state  *fiji_ps;
5037
5038         if (hwmgr == NULL)
5039                 return -EINVAL;
5040
5041         ps = hwmgr->request_ps;
5042
5043         if (ps == NULL)
5044                 return -EINVAL;
5045
5046         fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
5047
5048         if (low)
5049                 return fiji_ps->performance_levels[0].engine_clock;
5050         else
5051                 return fiji_ps->performance_levels
5052                                 [fiji_ps->performance_level_count-1].engine_clock;
5053 }
5054
5055 static int fiji_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
5056 {
5057         struct pp_power_state  *ps;
5058         struct fiji_power_state  *fiji_ps;
5059
5060         if (hwmgr == NULL)
5061                 return -EINVAL;
5062
5063         ps = hwmgr->request_ps;
5064
5065         if (ps == NULL)
5066                 return -EINVAL;
5067
5068         fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
5069
5070         if (low)
5071                 return fiji_ps->performance_levels[0].memory_clock;
5072         else
5073                 return fiji_ps->performance_levels
5074                                 [fiji_ps->performance_level_count-1].memory_clock;
5075 }
5076
5077 static void fiji_print_current_perforce_level(
5078                 struct pp_hwmgr *hwmgr, struct seq_file *m)
5079 {
5080         uint32_t sclk, mclk, activity_percent = 0;
5081         uint32_t offset;
5082         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5083
5084         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
5085
5086         sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5087
5088         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
5089
5090         mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5091         seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
5092                         mclk / 100, sclk / 100);
5093
5094         offset = data->soft_regs_start + offsetof(SMU73_SoftRegisters, AverageGraphicsActivity);
5095         activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
5096         activity_percent += 0x80;
5097         activity_percent >>= 8;
5098
5099         seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
5100
5101         seq_printf(m, "uvd    %sabled\n", data->uvd_power_gated ? "dis" : "en");
5102
5103         seq_printf(m, "vce    %sabled\n", data->vce_power_gated ? "dis" : "en");
5104 }
5105
5106 static int fiji_program_display_gap(struct pp_hwmgr *hwmgr)
5107 {
5108         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5109         uint32_t num_active_displays = 0;
5110         uint32_t display_gap = cgs_read_ind_register(hwmgr->device,
5111                         CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
5112         uint32_t display_gap2;
5113         uint32_t pre_vbi_time_in_us;
5114         uint32_t frame_time_in_us;
5115         uint32_t ref_clock;
5116         uint32_t refresh_rate = 0;
5117         struct cgs_display_info info = {0};
5118         struct cgs_mode_info mode_info;
5119
5120         info.mode_info = &mode_info;
5121
5122         cgs_get_active_displays_info(hwmgr->device, &info);
5123         num_active_displays = info.display_count;
5124
5125         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
5126                         DISP_GAP, (num_active_displays > 0)?
5127                         DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
5128         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
5129                         ixCG_DISPLAY_GAP_CNTL, display_gap);
5130
5131         ref_clock = mode_info.ref_clock;
5132         refresh_rate = mode_info.refresh_rate;
5133
5134         if (refresh_rate == 0)
5135                 refresh_rate = 60;
5136
5137         frame_time_in_us = 1000000 / refresh_rate;
5138
5139         pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
5140         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
5141
5142         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
5143                         ixCG_DISPLAY_GAP_CNTL2, display_gap2);
5144
5145         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
5146                         data->soft_regs_start +
5147                         offsetof(SMU73_SoftRegisters, PreVBlankGap), 0x64);
5148
5149         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
5150                         data->soft_regs_start +
5151                         offsetof(SMU73_SoftRegisters, VBlankTimeout),
5152                         (frame_time_in_us - pre_vbi_time_in_us));
5153
5154         if (num_active_displays == 1)
5155                 tonga_notify_smc_display_change(hwmgr, true);
5156
5157         return 0;
5158 }
5159
5160 static int fiji_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
5161 {
5162         return fiji_program_display_gap(hwmgr);
5163 }
5164
5165 static int fiji_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr,
5166                 uint16_t us_max_fan_pwm)
5167 {
5168         hwmgr->thermal_controller.
5169         advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
5170
5171         if (phm_is_hw_access_blocked(hwmgr))
5172                 return 0;
5173
5174         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5175                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
5176 }
5177
5178 static int fiji_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr,
5179                 uint16_t us_max_fan_rpm)
5180 {
5181         hwmgr->thermal_controller.
5182         advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
5183
5184         if (phm_is_hw_access_blocked(hwmgr))
5185                 return 0;
5186
5187         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5188                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
5189 }
5190
5191 static int fiji_dpm_set_interrupt_state(void *private_data,
5192                                          unsigned src_id, unsigned type,
5193                                          int enabled)
5194 {
5195         uint32_t cg_thermal_int;
5196         struct pp_hwmgr *hwmgr = ((struct pp_eventmgr *)private_data)->hwmgr;
5197
5198         if (hwmgr == NULL)
5199                 return -EINVAL;
5200
5201         switch (type) {
5202         case AMD_THERMAL_IRQ_LOW_TO_HIGH:
5203                 if (enabled) {
5204                         cg_thermal_int = cgs_read_ind_register(hwmgr->device,
5205                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5206                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5207                         cgs_write_ind_register(hwmgr->device,
5208                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5209                 } else {
5210                         cg_thermal_int = cgs_read_ind_register(hwmgr->device,
5211                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5212                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5213                         cgs_write_ind_register(hwmgr->device,
5214                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5215                 }
5216                 break;
5217
5218         case AMD_THERMAL_IRQ_HIGH_TO_LOW:
5219                 if (enabled) {
5220                         cg_thermal_int = cgs_read_ind_register(hwmgr->device,
5221                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5222                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5223                         cgs_write_ind_register(hwmgr->device,
5224                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5225                 } else {
5226                         cg_thermal_int = cgs_read_ind_register(hwmgr->device,
5227                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5228                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5229                         cgs_write_ind_register(hwmgr->device,
5230                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5231                 }
5232                 break;
5233         default:
5234                 break;
5235         }
5236         return 0;
5237 }
5238
5239 static int fiji_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
5240                                         const void *thermal_interrupt_info)
5241 {
5242         int result;
5243         const struct pp_interrupt_registration_info *info =
5244                         (const struct pp_interrupt_registration_info *)
5245                         thermal_interrupt_info;
5246
5247         if (info == NULL)
5248                 return -EINVAL;
5249
5250         result = cgs_add_irq_source(hwmgr->device, 230, AMD_THERMAL_IRQ_LAST,
5251                                 fiji_dpm_set_interrupt_state,
5252                                 info->call_back, info->context);
5253
5254         if (result)
5255                 return -EINVAL;
5256
5257         result = cgs_add_irq_source(hwmgr->device, 231, AMD_THERMAL_IRQ_LAST,
5258                                 fiji_dpm_set_interrupt_state,
5259                                 info->call_back, info->context);
5260
5261         if (result)
5262                 return -EINVAL;
5263
5264         return 0;
5265 }
5266
5267 static int fiji_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
5268 {
5269         if (mode) {
5270                 /* stop auto-manage */
5271                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
5272                                 PHM_PlatformCaps_MicrocodeFanControl))
5273                         fiji_fan_ctrl_stop_smc_fan_control(hwmgr);
5274                 fiji_fan_ctrl_set_static_mode(hwmgr, mode);
5275         } else
5276                 /* restart auto-manage */
5277                 fiji_fan_ctrl_reset_fan_speed_to_default(hwmgr);
5278
5279         return 0;
5280 }
5281
5282 static int fiji_get_fan_control_mode(struct pp_hwmgr *hwmgr)
5283 {
5284         if (hwmgr->fan_ctrl_is_in_default_mode)
5285                 return hwmgr->fan_ctrl_default_mode;
5286         else
5287                 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
5288                                 CG_FDO_CTRL2, FDO_PWM_MODE);
5289 }
5290
5291 static int fiji_force_clock_level(struct pp_hwmgr *hwmgr,
5292                 enum pp_clock_type type, uint32_t mask)
5293 {
5294         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5295
5296         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
5297                 return -EINVAL;
5298
5299         switch (type) {
5300         case PP_SCLK:
5301                 if (!data->sclk_dpm_key_disabled)
5302                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5303                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
5304                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
5305                 break;
5306
5307         case PP_MCLK:
5308                 if (!data->mclk_dpm_key_disabled)
5309                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5310                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
5311                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
5312                 break;
5313
5314         case PP_PCIE:
5315         {
5316                 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
5317                 uint32_t level = 0;
5318
5319                 while (tmp >>= 1)
5320                         level++;
5321
5322                 if (!data->pcie_dpm_key_disabled)
5323                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5324                                         PPSMC_MSG_PCIeDPM_ForceLevel,
5325                                         level);
5326                 break;
5327         }
5328         default:
5329                 break;
5330         }
5331
5332         return 0;
5333 }
5334
5335 static int fiji_print_clock_levels(struct pp_hwmgr *hwmgr,
5336                 enum pp_clock_type type, char *buf)
5337 {
5338         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5339         struct fiji_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5340         struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5341         struct fiji_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
5342         int i, now, size = 0;
5343         uint32_t clock, pcie_speed;
5344
5345         switch (type) {
5346         case PP_SCLK:
5347                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
5348                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5349
5350                 for (i = 0; i < sclk_table->count; i++) {
5351                         if (clock > sclk_table->dpm_levels[i].value)
5352                                 continue;
5353                         break;
5354                 }
5355                 now = i;
5356
5357                 for (i = 0; i < sclk_table->count; i++)
5358                         size += sprintf(buf + size, "%d: %uMhz %s\n",
5359                                         i, sclk_table->dpm_levels[i].value / 100,
5360                                         (i == now) ? "*" : "");
5361                 break;
5362         case PP_MCLK:
5363                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
5364                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5365
5366                 for (i = 0; i < mclk_table->count; i++) {
5367                         if (clock > mclk_table->dpm_levels[i].value)
5368                                 continue;
5369                         break;
5370                 }
5371                 now = i;
5372
5373                 for (i = 0; i < mclk_table->count; i++)
5374                         size += sprintf(buf + size, "%d: %uMhz %s\n",
5375                                         i, mclk_table->dpm_levels[i].value / 100,
5376                                         (i == now) ? "*" : "");
5377                 break;
5378         case PP_PCIE:
5379                 pcie_speed = fiji_get_current_pcie_speed(hwmgr);
5380                 for (i = 0; i < pcie_table->count; i++) {
5381                         if (pcie_speed != pcie_table->dpm_levels[i].value)
5382                                 continue;
5383                         break;
5384                 }
5385                 now = i;
5386
5387                 for (i = 0; i < pcie_table->count; i++)
5388                         size += sprintf(buf + size, "%d: %s %s\n", i,
5389                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x1" :
5390                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
5391                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
5392                                         (i == now) ? "*" : "");
5393                 break;
5394         default:
5395                 break;
5396         }
5397         return size;
5398 }
5399
5400 static inline bool fiji_are_power_levels_equal(const struct fiji_performance_level *pl1,
5401                                                            const struct fiji_performance_level *pl2)
5402 {
5403         return ((pl1->memory_clock == pl2->memory_clock) &&
5404                   (pl1->engine_clock == pl2->engine_clock) &&
5405                   (pl1->pcie_gen == pl2->pcie_gen) &&
5406                   (pl1->pcie_lane == pl2->pcie_lane));
5407 }
5408
5409 static int
5410 fiji_check_states_equal(struct pp_hwmgr *hwmgr,
5411                 const struct pp_hw_power_state *pstate1,
5412                 const struct pp_hw_power_state *pstate2, bool *equal)
5413 {
5414         const struct fiji_power_state *psa = cast_const_phw_fiji_power_state(pstate1);
5415         const struct fiji_power_state *psb = cast_const_phw_fiji_power_state(pstate2);
5416         int i;
5417
5418         if (equal == NULL || psa == NULL || psb == NULL)
5419                 return -EINVAL;
5420
5421         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
5422         if (psa->performance_level_count != psb->performance_level_count) {
5423                 *equal = false;
5424                 return 0;
5425         }
5426
5427         for (i = 0; i < psa->performance_level_count; i++) {
5428                 if (!fiji_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
5429                         /* If we have found even one performance level pair that is different the states are different. */
5430                         *equal = false;
5431                         return 0;
5432                 }
5433         }
5434
5435         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
5436         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
5437         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
5438         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
5439         *equal &= (psa->acp_clk == psb->acp_clk);
5440
5441         return 0;
5442 }
5443
5444 static bool
5445 fiji_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
5446 {
5447         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5448         bool is_update_required = false;
5449         struct cgs_display_info info = {0,0,NULL};
5450
5451         cgs_get_active_displays_info(hwmgr->device, &info);
5452
5453         if (data->display_timing.num_existing_displays != info.display_count)
5454                 is_update_required = true;
5455
5456         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
5457                 if(hwmgr->display_config.min_core_set_clock_in_sr != data->display_timing.min_clock_in_sr)
5458                         is_update_required = true;
5459         }
5460
5461         return is_update_required;
5462 }
5463
5464 static int fiji_get_sclk_od(struct pp_hwmgr *hwmgr)
5465 {
5466         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5467         struct fiji_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5468         struct fiji_single_dpm_table *golden_sclk_table =
5469                         &(data->golden_dpm_table.sclk_table);
5470         int value;
5471
5472         value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
5473                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
5474                         100 /
5475                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5476
5477         return value;
5478 }
5479
5480 static int fiji_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5481 {
5482         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5483         struct fiji_single_dpm_table *golden_sclk_table =
5484                         &(data->golden_dpm_table.sclk_table);
5485         struct pp_power_state  *ps;
5486         struct fiji_power_state  *fiji_ps;
5487
5488         if (value > 20)
5489                 value = 20;
5490
5491         ps = hwmgr->request_ps;
5492
5493         if (ps == NULL)
5494                 return -EINVAL;
5495
5496         fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
5497
5498         fiji_ps->performance_levels[fiji_ps->performance_level_count - 1].engine_clock =
5499                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
5500                         value / 100 +
5501                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5502
5503         return 0;
5504 }
5505
5506 static int fiji_get_mclk_od(struct pp_hwmgr *hwmgr)
5507 {
5508         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5509         struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5510         struct fiji_single_dpm_table *golden_mclk_table =
5511                         &(data->golden_dpm_table.mclk_table);
5512         int value;
5513
5514         value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
5515                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
5516                         100 /
5517                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5518
5519         return value;
5520 }
5521
5522 static int fiji_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5523 {
5524         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5525         struct fiji_single_dpm_table *golden_mclk_table =
5526                         &(data->golden_dpm_table.mclk_table);
5527         struct pp_power_state  *ps;
5528         struct fiji_power_state  *fiji_ps;
5529
5530         if (value > 20)
5531                 value = 20;
5532
5533         ps = hwmgr->request_ps;
5534
5535         if (ps == NULL)
5536                 return -EINVAL;
5537
5538         fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
5539
5540         fiji_ps->performance_levels[fiji_ps->performance_level_count - 1].memory_clock =
5541                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
5542                         value / 100 +
5543                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5544
5545         return 0;
5546 }
5547
5548 static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
5549         .backend_init = &fiji_hwmgr_backend_init,
5550         .backend_fini = &fiji_hwmgr_backend_fini,
5551         .asic_setup = &fiji_setup_asic_task,
5552         .dynamic_state_management_enable = &fiji_enable_dpm_tasks,
5553         .dynamic_state_management_disable = &fiji_disable_dpm_tasks,
5554         .force_dpm_level = &fiji_dpm_force_dpm_level,
5555         .get_num_of_pp_table_entries = &get_number_of_powerplay_table_entries_v1_0,
5556         .get_power_state_size = &fiji_get_power_state_size,
5557         .get_pp_table_entry = &fiji_get_pp_table_entry,
5558         .patch_boot_state = &fiji_patch_boot_state,
5559         .apply_state_adjust_rules = &fiji_apply_state_adjust_rules,
5560         .power_state_set = &fiji_set_power_state_tasks,
5561         .get_sclk = &fiji_dpm_get_sclk,
5562         .get_mclk = &fiji_dpm_get_mclk,
5563         .print_current_perforce_level = &fiji_print_current_perforce_level,
5564         .powergate_uvd = &fiji_phm_powergate_uvd,
5565         .powergate_vce = &fiji_phm_powergate_vce,
5566         .disable_clock_power_gating = &fiji_phm_disable_clock_power_gating,
5567         .notify_smc_display_config_after_ps_adjustment =
5568                         &tonga_notify_smc_display_config_after_ps_adjustment,
5569         .display_config_changed = &fiji_display_configuration_changed_task,
5570         .set_max_fan_pwm_output = fiji_set_max_fan_pwm_output,
5571         .set_max_fan_rpm_output = fiji_set_max_fan_rpm_output,
5572         .get_temperature = fiji_thermal_get_temperature,
5573         .stop_thermal_controller = fiji_thermal_stop_thermal_controller,
5574         .get_fan_speed_info = fiji_fan_ctrl_get_fan_speed_info,
5575         .get_fan_speed_percent = fiji_fan_ctrl_get_fan_speed_percent,
5576         .set_fan_speed_percent = fiji_fan_ctrl_set_fan_speed_percent,
5577         .reset_fan_speed_to_default = fiji_fan_ctrl_reset_fan_speed_to_default,
5578         .get_fan_speed_rpm = fiji_fan_ctrl_get_fan_speed_rpm,
5579         .set_fan_speed_rpm = fiji_fan_ctrl_set_fan_speed_rpm,
5580         .uninitialize_thermal_controller = fiji_thermal_ctrl_uninitialize_thermal_controller,
5581         .register_internal_thermal_interrupt = fiji_register_internal_thermal_interrupt,
5582         .set_fan_control_mode = fiji_set_fan_control_mode,
5583         .get_fan_control_mode = fiji_get_fan_control_mode,
5584         .check_states_equal = fiji_check_states_equal,
5585         .check_smc_update_required_for_display_configuration = fiji_check_smc_update_required_for_display_configuration,
5586         .force_clock_level = fiji_force_clock_level,
5587         .print_clock_levels = fiji_print_clock_levels,
5588         .get_sclk_od = fiji_get_sclk_od,
5589         .set_sclk_od = fiji_set_sclk_od,
5590         .get_mclk_od = fiji_get_mclk_od,
5591         .set_mclk_od = fiji_set_mclk_od,
5592 };
5593
5594 int fiji_hwmgr_init(struct pp_hwmgr *hwmgr)
5595 {
5596         hwmgr->hwmgr_func = &fiji_hwmgr_funcs;
5597         hwmgr->pptable_func = &pptable_v1_0_funcs;
5598         pp_fiji_thermal_initialize(hwmgr);
5599         return 0;
5600 }