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25 #include "cz_clockpowergating.h"
28 /* PhyID -> Status Mapping in DDI_PHY_GEN_STATUS
29 0 GFX0L (3:0), (27:24),
30 1 GFX0H (7:4), (31:28),
31 2 GFX1L (3:0), (19:16),
32 3 GFX1H (7:4), (23:20),
33 4 DDIL (3:0), (11: 8),
34 5 DDIH (7:4), (15:12),
35 6 DDI2L (3:0), ( 3: 0),
36 7 DDI2H (7:4), ( 7: 4),
38 #define DDI_PHY_GEN_STATUS_VAL(phyID) (1 << ((3 - ((phyID & 0x07)/2))*8 + (phyID & 0x01)*4))
39 #define IS_PHY_ID_USED_BY_PLL(PhyID) (((0xF3 & (1 << PhyID)) & 0xFF) ? true : false)
42 int cz_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock block, enum PHM_ClockGateSetting gating)
47 case PHM_AsicBlock_UVD_MVC:
48 case PHM_AsicBlock_UVD:
49 case PHM_AsicBlock_UVD_HD:
50 case PHM_AsicBlock_UVD_SD:
51 if (gating == PHM_ClockGateSetting_StaticOff)
52 ret = cz_dpm_powerdown_uvd(hwmgr);
54 ret = cz_dpm_powerup_uvd(hwmgr);
56 case PHM_AsicBlock_GFX:
65 bool cz_phm_is_safe_for_asic_block(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, enum PHM_AsicBlock block)
71 int cz_phm_enable_disable_gfx_power_gating(struct pp_hwmgr *hwmgr, bool enable)
76 int cz_phm_smu_power_up_down_pcie(struct pp_hwmgr *hwmgr, uint32_t target, bool up, uint32_t args)
82 int cz_phm_initialize_display_phy_access(struct pp_hwmgr *hwmgr, bool initialize, bool accesshw)
88 int cz_phm_get_display_phy_access_info(struct pp_hwmgr *hwmgr)
94 int cz_phm_gate_unused_display_phys(struct pp_hwmgr *hwmgr)
100 int cz_phm_ungate_all_display_phys(struct pp_hwmgr *hwmgr)
106 int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
108 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
109 uint32_t dpm_features = 0;
112 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
113 PHM_PlatformCaps_UVDDPM)) {
114 cz_hwmgr->dpm_flags |= DPMFlags_UVD_Enabled;
115 dpm_features |= UVD_DPM_MASK;
116 smum_send_msg_to_smc_with_parameter(hwmgr,
117 PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
119 dpm_features |= UVD_DPM_MASK;
120 cz_hwmgr->dpm_flags &= ~DPMFlags_UVD_Enabled;
121 smum_send_msg_to_smc_with_parameter(hwmgr,
122 PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
127 int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
129 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
130 uint32_t dpm_features = 0;
132 if (enable && phm_cap_enabled(
133 hwmgr->platform_descriptor.platformCaps,
134 PHM_PlatformCaps_VCEDPM)) {
135 cz_hwmgr->dpm_flags |= DPMFlags_VCE_Enabled;
136 dpm_features |= VCE_DPM_MASK;
137 smum_send_msg_to_smc_with_parameter(hwmgr,
138 PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
140 dpm_features |= VCE_DPM_MASK;
141 cz_hwmgr->dpm_flags &= ~DPMFlags_VCE_Enabled;
142 smum_send_msg_to_smc_with_parameter(hwmgr,
143 PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
150 void cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
152 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
154 cz_hwmgr->uvd_power_gated = bgate;
157 cgs_set_powergating_state(hwmgr->device,
158 AMD_IP_BLOCK_TYPE_UVD,
160 cgs_set_clockgating_state(hwmgr->device,
161 AMD_IP_BLOCK_TYPE_UVD,
163 cz_dpm_update_uvd_dpm(hwmgr, true);
164 cz_dpm_powerdown_uvd(hwmgr);
166 cz_dpm_powerup_uvd(hwmgr);
167 cgs_set_clockgating_state(hwmgr->device,
168 AMD_IP_BLOCK_TYPE_UVD,
169 AMD_PG_STATE_UNGATE);
170 cgs_set_powergating_state(hwmgr->device,
171 AMD_IP_BLOCK_TYPE_UVD,
172 AMD_CG_STATE_UNGATE);
173 cz_dpm_update_uvd_dpm(hwmgr, false);
178 void cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
180 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
183 cgs_set_powergating_state(
185 AMD_IP_BLOCK_TYPE_VCE,
187 cgs_set_clockgating_state(
189 AMD_IP_BLOCK_TYPE_VCE,
191 cz_enable_disable_vce_dpm(hwmgr, false);
192 cz_dpm_powerdown_vce(hwmgr);
193 cz_hwmgr->vce_power_gated = true;
195 cz_dpm_powerup_vce(hwmgr);
196 cz_hwmgr->vce_power_gated = false;
197 cgs_set_clockgating_state(
199 AMD_IP_BLOCK_TYPE_VCE,
200 AMD_PG_STATE_UNGATE);
201 cgs_set_powergating_state(
203 AMD_IP_BLOCK_TYPE_VCE,
204 AMD_CG_STATE_UNGATE);
205 cz_dpm_update_vce_dpm(hwmgr);
206 cz_enable_disable_vce_dpm(hwmgr, true);