drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_smu.h"
  27 #include "smu_internal.h"
  28 #include "atomfirmware.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "smu_v11_0.h"
  31 #include "smu11_driver_if_arcturus.h"
  32 #include "soc15_common.h"
  33 #include "atom.h"
  34 #include "power_state.h"
  35 #include "arcturus_ppt.h"
  36 #include "smu_v11_0_pptable.h"
  37 #include "arcturus_ppsmc.h"
  38 #include "nbio/nbio_7_4_offset.h"
  39 #include "nbio/nbio_7_4_sh_mask.h"
  40 #include "amdgpu_xgmi.h"
  41 #include <linux/i2c.h>
  42 #include <linux/pci.h>
  43 #include "amdgpu_ras.h"
  44
  45 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  46
  47 #define CTF_OFFSET_EDGE                 5
  48 #define CTF_OFFSET_HOTSPOT              5
  49 #define CTF_OFFSET_HBM                  5
  50
  51 #define MSG_MAP(msg, index, valid_in_vf) \
  52         [SMU_MSG_##msg] = {1, (index), (valid_in_vf)}
  53 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
  54         [smu_feature] = {1, (arcturus_feature)}
  55
  56 #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  57 #define SMU_FEATURES_LOW_SHIFT       0
  58 #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  59 #define SMU_FEATURES_HIGH_SHIFT      32
  60
  61 #define SMC_DPM_FEATURE ( \
  62         FEATURE_DPM_PREFETCHER_MASK | \
  63         FEATURE_DPM_GFXCLK_MASK | \
  64         FEATURE_DPM_UCLK_MASK | \
  65         FEATURE_DPM_SOCCLK_MASK | \
  66         FEATURE_DPM_MP0CLK_MASK | \
  67         FEATURE_DPM_FCLK_MASK | \
  68         FEATURE_DPM_XGMI_MASK)
  69
  70 /* possible frequency drift (1Mhz) */
  71 #define EPSILON                         1
  72
  73 static struct smu_11_0_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
  74         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage,                     0),
  75         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion,                   1),
  76         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion,              1),
  77         MSG_MAP(SetAllowedFeaturesMaskLow,           PPSMC_MSG_SetAllowedFeaturesMaskLow,       0),
  78         MSG_MAP(SetAllowedFeaturesMaskHigh,          PPSMC_MSG_SetAllowedFeaturesMaskHigh,      0),
  79         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures,            0),
  80         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures,           0),
  81         MSG_MAP(EnableSmuFeaturesLow,                PPSMC_MSG_EnableSmuFeaturesLow,            1),
  82         MSG_MAP(EnableSmuFeaturesHigh,               PPSMC_MSG_EnableSmuFeaturesHigh,           1),
  83         MSG_MAP(DisableSmuFeaturesLow,               PPSMC_MSG_DisableSmuFeaturesLow,           0),
  84         MSG_MAP(DisableSmuFeaturesHigh,              PPSMC_MSG_DisableSmuFeaturesHigh,          0),
  85         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow,        0),
  86         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh,       0),
  87         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh,           1),
  88         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow,            1),
  89         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh,            0),
  90         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow,             0),
  91         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram,           1),
  92         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu,           0),
  93         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable,               0),
  94         MSG_MAP(UseBackupPPTable,                    PPSMC_MSG_UseBackupPPTable,                0),
  95         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh,    0),
  96         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow,     0),
  97         MSG_MAP(EnterBaco,                           PPSMC_MSG_EnterBaco,                       0),
  98         MSG_MAP(ExitBaco,                            PPSMC_MSG_ExitBaco,                        0),
  99         MSG_MAP(ArmD3,                               PPSMC_MSG_ArmD3,                           0),
 100         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq,                0),
 101         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq,                0),
 102         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq,                0),
 103         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq,                0),
 104         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq,                   0),
 105         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq,                   0),
 106         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex,               1),
 107         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask,                 1),
 108         MSG_MAP(SetDfSwitchType,                     PPSMC_MSG_SetDfSwitchType,                 0),
 109         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm,                 0),
 110         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive,        0),
 111         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,                     0),
 112         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,                     1),
 113         MSG_MAP(PowerUpVcn0,                         PPSMC_MSG_PowerUpVcn0,                     0),
 114         MSG_MAP(PowerDownVcn0,                       PPSMC_MSG_PowerDownVcn0,                   0),
 115         MSG_MAP(PowerUpVcn1,                         PPSMC_MSG_PowerUpVcn1,                     0),
 116         MSG_MAP(PowerDownVcn1,                       PPSMC_MSG_PowerDownVcn1,                   0),
 117         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload,             0),
 118         MSG_MAP(PrepareMp1ForReset,                  PPSMC_MSG_PrepareMp1ForReset,              0),
 119         MSG_MAP(PrepareMp1ForShutdown,               PPSMC_MSG_PrepareMp1ForShutdown,           0),
 120         MSG_MAP(SoftReset,                           PPSMC_MSG_SoftReset,                       0),
 121         MSG_MAP(RunAfllBtc,                          PPSMC_MSG_RunAfllBtc,                      0),
 122         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc,                        0),
 123         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh,          0),
 124         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow,           0),
 125         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize,              0),
 126         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData,                    0),
 127         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest,                        0),
 128         MSG_MAP(SetXgmiMode,                         PPSMC_MSG_SetXgmiMode,                     0),
 129         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable,          0),
 130         MSG_MAP(DFCstateControl,                     PPSMC_MSG_DFCstateControl,                 0),
 131         MSG_MAP(GmiPwrDnControl,                     PPSMC_MSG_GmiPwrDnControl,                 0),
 132         MSG_MAP(ReadSerialNumTop32,                  PPSMC_MSG_ReadSerialNumTop32,              1),
 133         MSG_MAP(ReadSerialNumBottom32,               PPSMC_MSG_ReadSerialNumBottom32,           1),
 134 };
 135
 136 static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
 137         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 138         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 139         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 140         CLK_MAP(FCLK, PPCLK_FCLK),
 141         CLK_MAP(UCLK, PPCLK_UCLK),
 142         CLK_MAP(MCLK, PPCLK_UCLK),
 143         CLK_MAP(DCLK, PPCLK_DCLK),
 144         CLK_MAP(VCLK, PPCLK_VCLK),
 145 };
 146
 147 static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
 148         FEA_MAP(DPM_PREFETCHER),
 149         FEA_MAP(DPM_GFXCLK),
 150         FEA_MAP(DPM_UCLK),
 151         FEA_MAP(DPM_SOCCLK),
 152         FEA_MAP(DPM_FCLK),
 153         FEA_MAP(DPM_MP0CLK),
 154         ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
 155         FEA_MAP(DS_GFXCLK),
 156         FEA_MAP(DS_SOCCLK),
 157         FEA_MAP(DS_LCLK),
 158         FEA_MAP(DS_FCLK),
 159         FEA_MAP(DS_UCLK),
 160         FEA_MAP(GFX_ULV),
 161         ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
 162         FEA_MAP(RSMU_SMN_CG),
 163         FEA_MAP(WAFL_CG),
 164         FEA_MAP(PPT),
 165         FEA_MAP(TDC),
 166         FEA_MAP(APCC_PLUS),
 167         FEA_MAP(VR0HOT),
 168         FEA_MAP(VR1HOT),
 169         FEA_MAP(FW_CTF),
 170         FEA_MAP(FAN_CONTROL),
 171         FEA_MAP(THERMAL),
 172         FEA_MAP(OUT_OF_BAND_MONITOR),
 173         FEA_MAP(TEMP_DEPENDENT_VMIN),
 174 };
 175
 176 static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
 177         TAB_MAP(PPTABLE),
 178         TAB_MAP(AVFS),
 179         TAB_MAP(AVFS_PSM_DEBUG),
 180         TAB_MAP(AVFS_FUSE_OVERRIDE),
 181         TAB_MAP(PMSTATUSLOG),
 182         TAB_MAP(SMU_METRICS),
 183         TAB_MAP(DRIVER_SMU_CONFIG),
 184         TAB_MAP(OVERDRIVE),
 185         TAB_MAP(I2C_COMMANDS),
 186         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 187 };
 188
 189 static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 190         PWR_MAP(AC),
 191         PWR_MAP(DC),
 192 };
 193
 194 static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 195         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 196         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 197         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 198         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 199         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 200 };
 201
 202 static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 203 {
 204         struct smu_11_0_msg_mapping mapping;
 205
 206         if (index >= SMU_MSG_MAX_COUNT)
 207                 return -EINVAL;
 208
 209         mapping = arcturus_message_map[index];
 210         if (!(mapping.valid_mapping))
 211                 return -EINVAL;
 212
 213         if (amdgpu_sriov_vf(smc->adev) && !mapping.valid_in_vf)
 214                 return -EACCES;
 215
 216         return mapping.map_to;
 217 }
 218
 219 static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 220 {
 221         struct smu_11_0_cmn2aisc_mapping mapping;
 222
 223         if (index >= SMU_CLK_COUNT)
 224                 return -EINVAL;
 225
 226         mapping = arcturus_clk_map[index];
 227         if (!(mapping.valid_mapping)) {
 228                 pr_warn("Unsupported SMU clk: %d\n", index);
 229                 return -EINVAL;
 230         }
 231
 232         return mapping.map_to;
 233 }
 234
 235 static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 236 {
 237         struct smu_11_0_cmn2aisc_mapping mapping;
 238
 239         if (index >= SMU_FEATURE_COUNT)
 240                 return -EINVAL;
 241
 242         mapping = arcturus_feature_mask_map[index];
 243         if (!(mapping.valid_mapping)) {
 244                 return -EINVAL;
 245         }
 246
 247         return mapping.map_to;
 248 }
 249
 250 static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)
 251 {
 252         struct smu_11_0_cmn2aisc_mapping mapping;
 253
 254         if (index >= SMU_TABLE_COUNT)
 255                 return -EINVAL;
 256
 257         mapping = arcturus_table_map[index];
 258         if (!(mapping.valid_mapping)) {
 259                 pr_warn("Unsupported SMU table: %d\n", index);
 260                 return -EINVAL;
 261         }
 262
 263         return mapping.map_to;
 264 }
 265
 266 static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 267 {
 268         struct smu_11_0_cmn2aisc_mapping mapping;
 269
 270         if (index >= SMU_POWER_SOURCE_COUNT)
 271                 return -EINVAL;
 272
 273         mapping = arcturus_pwr_src_map[index];
 274         if (!(mapping.valid_mapping)) {
 275                 pr_warn("Unsupported SMU power source: %d\n", index);
 276                 return -EINVAL;
 277         }
 278
 279         return mapping.map_to;
 280 }
 281
 282
 283 static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 284 {
 285         struct smu_11_0_cmn2aisc_mapping mapping;
 286
 287         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 288                 return -EINVAL;
 289
 290         mapping = arcturus_workload_map[profile];
 291         if (!(mapping.valid_mapping))
 292                 return -EINVAL;
 293
 294         return mapping.map_to;
 295 }
 296
 297 static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
 298 {
 299         struct smu_table_context *smu_table = &smu->smu_table;
 300
 301         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 302                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 303
 304         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 305                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 306
 307         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 308                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 309
 310         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 311                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 312
 313         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 314                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 315                        AMDGPU_GEM_DOMAIN_VRAM);
 316
 317         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 318         if (!smu_table->metrics_table)
 319                 return -ENOMEM;
 320         smu_table->metrics_time = 0;
 321
 322         return 0;
 323 }
 324
 325 static int arcturus_allocate_dpm_context(struct smu_context *smu)
 326 {
 327         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 328
 329         if (smu_dpm->dpm_context)
 330                 return -EINVAL;
 331
 332         smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
 333                                        GFP_KERNEL);
 334         if (!smu_dpm->dpm_context)
 335                 return -ENOMEM;
 336
 337         if (smu_dpm->golden_dpm_context)
 338                 return -EINVAL;
 339
 340         smu_dpm->golden_dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
 341                                               GFP_KERNEL);
 342         if (!smu_dpm->golden_dpm_context)
 343                 return -ENOMEM;
 344
 345         smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
 346
 347         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 348                                        GFP_KERNEL);
 349         if (!smu_dpm->dpm_current_power_state)
 350                 return -ENOMEM;
 351
 352         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 353                                        GFP_KERNEL);
 354         if (!smu_dpm->dpm_request_power_state)
 355                 return -ENOMEM;
 356
 357         return 0;
 358 }
 359
 360 static int
 361 arcturus_get_allowed_feature_mask(struct smu_context *smu,
 362                                   uint32_t *feature_mask, uint32_t num)
 363 {
 364         if (num > 2)
 365                 return -EINVAL;
 366
 367         /* pptable will handle the features to enable */
 368         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 369
 370         return 0;
 371 }
 372
 373 static int
 374 arcturus_set_single_dpm_table(struct smu_context *smu,
 375                             struct arcturus_single_dpm_table *single_dpm_table,
 376                             PPCLK_e clk_id)
 377 {
 378         int ret = 0;
 379         uint32_t i, num_of_levels = 0, clk;
 380
 381         ret = smu_send_smc_msg_with_param(smu,
 382                         SMU_MSG_GetDpmFreqByIndex,
 383                         (clk_id << 16 | 0xFF),
 384                         &num_of_levels);
 385         if (ret) {
 386                 pr_err("[%s] failed to get dpm levels!\n", __func__);
 387                 return ret;
 388         }
 389
 390         single_dpm_table->count = num_of_levels;
 391         for (i = 0; i < num_of_levels; i++) {
 392                 ret = smu_send_smc_msg_with_param(smu,
 393                                 SMU_MSG_GetDpmFreqByIndex,
 394                                 (clk_id << 16 | i),
 395                                 &clk);
 396                 if (ret) {
 397                         pr_err("[%s] failed to get dpm freq by index!\n", __func__);
 398                         return ret;
 399                 }
 400                 single_dpm_table->dpm_levels[i].value = clk;
 401                 single_dpm_table->dpm_levels[i].enabled = true;
 402         }
 403         return 0;
 404 }
 405
 406 static void arcturus_init_single_dpm_state(struct arcturus_dpm_state *dpm_state)
 407 {
 408         dpm_state->soft_min_level = 0x0;
 409         dpm_state->soft_max_level = 0xffff;
 410         dpm_state->hard_min_level = 0x0;
 411         dpm_state->hard_max_level = 0xffff;
 412 }
 413
 414 static int arcturus_set_default_dpm_table(struct smu_context *smu)
 415 {
 416         int ret;
 417
 418         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 419         struct arcturus_dpm_table *dpm_table = NULL;
 420         struct arcturus_single_dpm_table *single_dpm_table;
 421
 422         dpm_table = smu_dpm->dpm_context;
 423
 424         /* socclk */
 425         single_dpm_table = &(dpm_table->soc_table);
 426         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 427                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 428                                                   PPCLK_SOCCLK);
 429                 if (ret) {
 430                         pr_err("[%s] failed to get socclk dpm levels!\n", __func__);
 431                         return ret;
 432                 }
 433         } else {
 434                 single_dpm_table->count = 1;
 435                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 436         }
 437         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 438
 439         /* gfxclk */
 440         single_dpm_table = &(dpm_table->gfx_table);
 441         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 442                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 443                                                   PPCLK_GFXCLK);
 444                 if (ret) {
 445                         pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
 446                         return ret;
 447                 }
 448         } else {
 449                 single_dpm_table->count = 1;
 450                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 451         }
 452         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 453
 454         /* memclk */
 455         single_dpm_table = &(dpm_table->mem_table);
 456         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 457                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 458                                                   PPCLK_UCLK);
 459                 if (ret) {
 460                         pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
 461                         return ret;
 462                 }
 463         } else {
 464                 single_dpm_table->count = 1;
 465                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 466         }
 467         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 468
 469         /* fclk */
 470         single_dpm_table = &(dpm_table->fclk_table);
 471         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 472                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 473                                                   PPCLK_FCLK);
 474                 if (ret) {
 475                         pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
 476                         return ret;
 477                 }
 478         } else {
 479                 single_dpm_table->count = 1;
 480                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 481         }
 482         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 483
 484         memcpy(smu_dpm->golden_dpm_context, dpm_table,
 485                sizeof(struct arcturus_dpm_table));
 486
 487         return 0;
 488 }
 489
 490 static int arcturus_check_powerplay_table(struct smu_context *smu)
 491 {
 492         struct smu_table_context *table_context = &smu->smu_table;
 493         struct smu_11_0_powerplay_table *powerplay_table =
 494                 table_context->power_play_table;
 495         struct smu_baco_context *smu_baco = &smu->smu_baco;
 496
 497         mutex_lock(&smu_baco->mutex);
 498         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 499             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 500                 smu_baco->platform_support = true;
 501         mutex_unlock(&smu_baco->mutex);
 502
 503         table_context->thermal_controller_type =
 504                 powerplay_table->thermal_controller_type;
 505
 506         return 0;
 507 }
 508
 509 static int arcturus_store_powerplay_table(struct smu_context *smu)
 510 {
 511         struct smu_table_context *table_context = &smu->smu_table;
 512         struct smu_11_0_powerplay_table *powerplay_table =
 513                 table_context->power_play_table;
 514
 515         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 516                sizeof(PPTable_t));
 517
 518         return 0;
 519 }
 520
 521 static int arcturus_append_powerplay_table(struct smu_context *smu)
 522 {
 523         struct smu_table_context *table_context = &smu->smu_table;
 524         PPTable_t *smc_pptable = table_context->driver_pptable;
 525         struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
 526         int index, ret;
 527
 528         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 529                                            smc_dpm_info);
 530
 531         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 532                                       (uint8_t **)&smc_dpm_table);
 533         if (ret)
 534                 return ret;
 535
 536         pr_info("smc_dpm_info table revision(format.content): %d.%d\n",
 537                         smc_dpm_table->table_header.format_revision,
 538                         smc_dpm_table->table_header.content_revision);
 539
 540         if ((smc_dpm_table->table_header.format_revision == 4) &&
 541             (smc_dpm_table->table_header.content_revision == 6))
 542                 memcpy(&smc_pptable->MaxVoltageStepGfx,
 543                        &smc_dpm_table->maxvoltagestepgfx,
 544                        sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
 545
 546         return 0;
 547 }
 548
 549 static int arcturus_setup_pptable(struct smu_context *smu)
 550 {
 551         int ret = 0;
 552
 553         ret = smu_v11_0_setup_pptable(smu);
 554         if (ret)
 555                 return ret;
 556
 557         ret = arcturus_store_powerplay_table(smu);
 558         if (ret)
 559                 return ret;
 560
 561         ret = arcturus_append_powerplay_table(smu);
 562         if (ret)
 563                 return ret;
 564
 565         ret = arcturus_check_powerplay_table(smu);
 566         if (ret)
 567                 return ret;
 568
 569         return ret;
 570 }
 571
 572 static int arcturus_run_btc(struct smu_context *smu)
 573 {
 574         int ret = 0;
 575
 576         ret = smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
 577         if (ret) {
 578                 pr_err("RunAfllBtc failed!\n");
 579                 return ret;
 580         }
 581
 582         return smu_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 583 }
 584
 585 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 586 {
 587         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 588         struct arcturus_dpm_table *dpm_table = NULL;
 589         struct arcturus_single_dpm_table *gfx_table = NULL;
 590         struct arcturus_single_dpm_table *mem_table = NULL;
 591
 592         dpm_table = smu_dpm->dpm_context;
 593         gfx_table = &(dpm_table->gfx_table);
 594         mem_table = &(dpm_table->mem_table);
 595
 596         smu->pstate_sclk = gfx_table->dpm_levels[0].value;
 597         smu->pstate_mclk = mem_table->dpm_levels[0].value;
 598
 599         if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
 600             mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL) {
 601                 smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
 602                 smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
 603         }
 604
 605         smu->pstate_sclk = smu->pstate_sclk * 100;
 606         smu->pstate_mclk = smu->pstate_mclk * 100;
 607
 608         return 0;
 609 }
 610
 611 static int arcturus_get_clk_table(struct smu_context *smu,
 612                         struct pp_clock_levels_with_latency *clocks,
 613                         struct arcturus_single_dpm_table *dpm_table)
 614 {
 615         int i, count;
 616
 617         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 618         clocks->num_levels = count;
 619
 620         for (i = 0; i < count; i++) {
 621                 clocks->data[i].clocks_in_khz =
 622                         dpm_table->dpm_levels[i].value * 1000;
 623                 clocks->data[i].latency_in_us = 0;
 624         }
 625
 626         return 0;
 627 }
 628
 629 static int arcturus_freqs_in_same_level(int32_t frequency1,
 630                                         int32_t frequency2)
 631 {
 632         return (abs(frequency1 - frequency2) <= EPSILON);
 633 }
 634
 635 static int arcturus_print_clk_levels(struct smu_context *smu,
 636                         enum smu_clk_type type, char *buf)
 637 {
 638         int i, now, size = 0;
 639         int ret = 0;
 640         struct pp_clock_levels_with_latency clocks;
 641         struct arcturus_single_dpm_table *single_dpm_table;
 642         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 643         struct arcturus_dpm_table *dpm_table = NULL;
 644
 645         if (amdgpu_ras_intr_triggered())
 646                 return snprintf(buf, PAGE_SIZE, "unavailable\n");
 647
 648         dpm_table = smu_dpm->dpm_context;
 649
 650         switch (type) {
 651         case SMU_SCLK:
 652                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
 653                 if (ret) {
 654                         pr_err("Attempt to get current gfx clk Failed!");
 655                         return ret;
 656                 }
 657
 658                 single_dpm_table = &(dpm_table->gfx_table);
 659                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 660                 if (ret) {
 661                         pr_err("Attempt to get gfx clk levels Failed!");
 662                         return ret;
 663                 }
 664
 665                 /*
 666                  * For DPM disabled case, there will be only one clock level.
 667                  * And it's safe to assume that is always the current clock.
 668                  */
 669                 for (i = 0; i < clocks.num_levels; i++)
 670                         size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 671                                         clocks.data[i].clocks_in_khz / 1000,
 672                                         (clocks.num_levels == 1) ? "*" :
 673                                         (arcturus_freqs_in_same_level(
 674                                         clocks.data[i].clocks_in_khz / 1000,
 675                                         now / 100) ? "*" : ""));
 676                 break;
 677
 678         case SMU_MCLK:
 679                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
 680                 if (ret) {
 681                         pr_err("Attempt to get current mclk Failed!");
 682                         return ret;
 683                 }
 684
 685                 single_dpm_table = &(dpm_table->mem_table);
 686                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 687                 if (ret) {
 688                         pr_err("Attempt to get memory clk levels Failed!");
 689                         return ret;
 690                 }
 691
 692                 for (i = 0; i < clocks.num_levels; i++)
 693                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 694                                 i, clocks.data[i].clocks_in_khz / 1000,
 695                                 (clocks.num_levels == 1) ? "*" :
 696                                 (arcturus_freqs_in_same_level(
 697                                 clocks.data[i].clocks_in_khz / 1000,
 698                                 now / 100) ? "*" : ""));
 699                 break;
 700
 701         case SMU_SOCCLK:
 702                 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
 703                 if (ret) {
 704                         pr_err("Attempt to get current socclk Failed!");
 705                         return ret;
 706                 }
 707
 708                 single_dpm_table = &(dpm_table->soc_table);
 709                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 710                 if (ret) {
 711                         pr_err("Attempt to get socclk levels Failed!");
 712                         return ret;
 713                 }
 714
 715                 for (i = 0; i < clocks.num_levels; i++)
 716                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 717                                 i, clocks.data[i].clocks_in_khz / 1000,
 718                                 (clocks.num_levels == 1) ? "*" :
 719                                 (arcturus_freqs_in_same_level(
 720                                 clocks.data[i].clocks_in_khz / 1000,
 721                                 now / 100) ? "*" : ""));
 722                 break;
 723
 724         case SMU_FCLK:
 725                 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
 726                 if (ret) {
 727                         pr_err("Attempt to get current fclk Failed!");
 728                         return ret;
 729                 }
 730
 731                 single_dpm_table = &(dpm_table->fclk_table);
 732                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 733                 if (ret) {
 734                         pr_err("Attempt to get fclk levels Failed!");
 735                         return ret;
 736                 }
 737
 738                 for (i = 0; i < single_dpm_table->count; i++)
 739                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 740                                 i, single_dpm_table->dpm_levels[i].value,
 741                                 (clocks.num_levels == 1) ? "*" :
 742                                 (arcturus_freqs_in_same_level(
 743                                 clocks.data[i].clocks_in_khz / 1000,
 744                                 now / 100) ? "*" : ""));
 745                 break;
 746
 747         default:
 748                 break;
 749         }
 750
 751         return size;
 752 }
 753
 754 static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
 755                                      uint32_t feature_mask)
 756 {
 757         struct arcturus_single_dpm_table *single_dpm_table;
 758         struct arcturus_dpm_table *dpm_table =
 759                         smu->smu_dpm.dpm_context;
 760         uint32_t freq;
 761         int ret = 0;
 762
 763         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 764             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 765                 single_dpm_table = &(dpm_table->gfx_table);
 766                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 767                         single_dpm_table->dpm_state.soft_min_level;
 768                 ret = smu_send_smc_msg_with_param(smu,
 769                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 770                         (PPCLK_GFXCLK << 16) | (freq & 0xffff),
 771                         NULL);
 772                 if (ret) {
 773                         pr_err("Failed to set soft %s gfxclk !\n",
 774                                                 max ? "max" : "min");
 775                         return ret;
 776                 }
 777         }
 778
 779         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 780             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 781                 single_dpm_table = &(dpm_table->mem_table);
 782                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 783                         single_dpm_table->dpm_state.soft_min_level;
 784                 ret = smu_send_smc_msg_with_param(smu,
 785                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 786                         (PPCLK_UCLK << 16) | (freq & 0xffff),
 787                         NULL);
 788                 if (ret) {
 789                         pr_err("Failed to set soft %s memclk !\n",
 790                                                 max ? "max" : "min");
 791                         return ret;
 792                 }
 793         }
 794
 795         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 796             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
 797                 single_dpm_table = &(dpm_table->soc_table);
 798                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 799                         single_dpm_table->dpm_state.soft_min_level;
 800                 ret = smu_send_smc_msg_with_param(smu,
 801                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 802                         (PPCLK_SOCCLK << 16) | (freq & 0xffff),
 803                         NULL);
 804                 if (ret) {
 805                         pr_err("Failed to set soft %s socclk !\n",
 806                                                 max ? "max" : "min");
 807                         return ret;
 808                 }
 809         }
 810
 811         return ret;
 812 }
 813
 814 static int arcturus_force_clk_levels(struct smu_context *smu,
 815                         enum smu_clk_type type, uint32_t mask)
 816 {
 817         struct arcturus_dpm_table *dpm_table;
 818         struct arcturus_single_dpm_table *single_dpm_table;
 819         uint32_t soft_min_level, soft_max_level;
 820         uint32_t smu_version;
 821         int ret = 0;
 822
 823         ret = smu_get_smc_version(smu, NULL, &smu_version);
 824         if (ret) {
 825                 pr_err("Failed to get smu version!\n");
 826                 return ret;
 827         }
 828
 829         if (smu_version >= 0x361200) {
 830                 pr_err("Forcing clock level is not supported with "
 831                        "54.18 and onwards SMU firmwares\n");
 832                 return -EOPNOTSUPP;
 833         }
 834
 835         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 836         soft_max_level = mask ? (fls(mask) - 1) : 0;
 837
 838         dpm_table = smu->smu_dpm.dpm_context;
 839
 840         switch (type) {
 841         case SMU_SCLK:
 842                 single_dpm_table = &(dpm_table->gfx_table);
 843
 844                 if (soft_max_level >= single_dpm_table->count) {
 845                         pr_err("Clock level specified %d is over max allowed %d\n",
 846                                         soft_max_level, single_dpm_table->count - 1);
 847                         ret = -EINVAL;
 848                         break;
 849                 }
 850
 851                 single_dpm_table->dpm_state.soft_min_level =
 852                         single_dpm_table->dpm_levels[soft_min_level].value;
 853                 single_dpm_table->dpm_state.soft_max_level =
 854                         single_dpm_table->dpm_levels[soft_max_level].value;
 855
 856                 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
 857                 if (ret) {
 858                         pr_err("Failed to upload boot level to lowest!\n");
 859                         break;
 860                 }
 861
 862                 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
 863                 if (ret)
 864                         pr_err("Failed to upload dpm max level to highest!\n");
 865
 866                 break;
 867
 868         case SMU_MCLK:
 869         case SMU_SOCCLK:
 870         case SMU_FCLK:
 871                 /*
 872                  * Should not arrive here since Arcturus does not
 873                  * support mclk/socclk/fclk softmin/softmax settings
 874                  */
 875                 ret = -EINVAL;
 876                 break;
 877
 878         default:
 879                 break;
 880         }
 881
 882         return ret;
 883 }
 884
 885 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
 886                                                 struct smu_temperature_range *range)
 887 {
 888         PPTable_t *pptable = smu->smu_table.driver_pptable;
 889
 890         if (!range)
 891                 return -EINVAL;
 892
 893         range->max = pptable->TedgeLimit *
 894                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 895         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
 896                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 897         range->hotspot_crit_max = pptable->ThotspotLimit *
 898                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 899         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
 900                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 901         range->mem_crit_max = pptable->TmemLimit *
 902                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 903         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)*
 904                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 905
 906         return 0;
 907 }
 908
 909 static int arcturus_get_metrics_table(struct smu_context *smu,
 910                                       SmuMetrics_t *metrics_table)
 911 {
 912         struct smu_table_context *smu_table= &smu->smu_table;
 913         int ret = 0;
 914
 915         mutex_lock(&smu->metrics_lock);
 916         if (!smu_table->metrics_time ||
 917              time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
 918                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 919                                 (void *)smu_table->metrics_table, false);
 920                 if (ret) {
 921                         pr_info("Failed to export SMU metrics table!\n");
 922                         mutex_unlock(&smu->metrics_lock);
 923                         return ret;
 924                 }
 925                 smu_table->metrics_time = jiffies;
 926         }
 927
 928         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 929         mutex_unlock(&smu->metrics_lock);
 930
 931         return ret;
 932 }
 933
 934 static int arcturus_get_current_activity_percent(struct smu_context *smu,
 935                                                  enum amd_pp_sensors sensor,
 936                                                  uint32_t *value)
 937 {
 938         SmuMetrics_t metrics;
 939         int ret = 0;
 940
 941         if (!value)
 942                 return -EINVAL;
 943
 944         ret = arcturus_get_metrics_table(smu, &metrics);
 945         if (ret)
 946                 return ret;
 947
 948         switch (sensor) {
 949         case AMDGPU_PP_SENSOR_GPU_LOAD:
 950                 *value = metrics.AverageGfxActivity;
 951                 break;
 952         case AMDGPU_PP_SENSOR_MEM_LOAD:
 953                 *value = metrics.AverageUclkActivity;
 954                 break;
 955         default:
 956                 pr_err("Invalid sensor for retrieving clock activity\n");
 957                 return -EINVAL;
 958         }
 959
 960         return 0;
 961 }
 962
 963 static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
 964 {
 965         SmuMetrics_t metrics;
 966         int ret = 0;
 967
 968         if (!value)
 969                 return -EINVAL;
 970
 971         ret = arcturus_get_metrics_table(smu, &metrics);
 972         if (ret)
 973                 return ret;
 974
 975         *value = metrics.AverageSocketPower << 8;
 976
 977         return 0;
 978 }
 979
 980 static int arcturus_thermal_get_temperature(struct smu_context *smu,
 981                                             enum amd_pp_sensors sensor,
 982                                             uint32_t *value)
 983 {
 984         SmuMetrics_t metrics;
 985         int ret = 0;
 986
 987         if (!value)
 988                 return -EINVAL;
 989
 990         ret = arcturus_get_metrics_table(smu, &metrics);
 991         if (ret)
 992                 return ret;
 993
 994         switch (sensor) {
 995         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 996                 *value = metrics.TemperatureHotspot *
 997                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 998                 break;
 999         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1000                 *value = metrics.TemperatureEdge *
1001                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1002                 break;
1003         case AMDGPU_PP_SENSOR_MEM_TEMP:
1004                 *value = metrics.TemperatureHBM *
1005                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1006                 break;
1007         default:
1008                 pr_err("Invalid sensor for retrieving temp\n");
1009                 return -EINVAL;
1010         }
1011
1012         return 0;
1013 }
1014
1015 static int arcturus_read_sensor(struct smu_context *smu,
1016                                 enum amd_pp_sensors sensor,
1017                                 void *data, uint32_t *size)
1018 {
1019         struct smu_table_context *table_context = &smu->smu_table;
1020         PPTable_t *pptable = table_context->driver_pptable;
1021         int ret = 0;
1022
1023         if (amdgpu_ras_intr_triggered())
1024                 return 0;
1025
1026         if (!data || !size)
1027                 return -EINVAL;
1028
1029         mutex_lock(&smu->sensor_lock);
1030         switch (sensor) {
1031         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1032                 *(uint32_t *)data = pptable->FanMaximumRpm;
1033                 *size = 4;
1034                 break;
1035         case AMDGPU_PP_SENSOR_MEM_LOAD:
1036         case AMDGPU_PP_SENSOR_GPU_LOAD:
1037                 ret = arcturus_get_current_activity_percent(smu,
1038                                                             sensor,
1039                                                 (uint32_t *)data);
1040                 *size = 4;
1041                 break;
1042         case AMDGPU_PP_SENSOR_GPU_POWER:
1043                 ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
1044                 *size = 4;
1045                 break;
1046         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1047         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1048         case AMDGPU_PP_SENSOR_MEM_TEMP:
1049                 ret = arcturus_thermal_get_temperature(smu, sensor,
1050                                                 (uint32_t *)data);
1051                 *size = 4;
1052                 break;
1053         default:
1054                 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1055         }
1056         mutex_unlock(&smu->sensor_lock);
1057
1058         return ret;
1059 }
1060
1061 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1062                                       uint32_t *speed)
1063 {
1064         SmuMetrics_t metrics;
1065         int ret = 0;
1066
1067         if (!speed)
1068                 return -EINVAL;
1069
1070         ret = arcturus_get_metrics_table(smu, &metrics);
1071         if (ret)
1072                 return ret;
1073
1074         *speed = metrics.CurrFanSpeed;
1075
1076         return ret;
1077 }
1078
1079 static int arcturus_get_fan_speed_percent(struct smu_context *smu,
1080                                           uint32_t *speed)
1081 {
1082         PPTable_t *pptable = smu->smu_table.driver_pptable;
1083         uint32_t percent, current_rpm;
1084         int ret = 0;
1085
1086         if (!speed)
1087                 return -EINVAL;
1088
1089         ret = arcturus_get_fan_speed_rpm(smu, &current_rpm);
1090         if (ret)
1091                 return ret;
1092
1093         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1094         *speed = percent > 100 ? 100 : percent;
1095
1096         return ret;
1097 }
1098
1099 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
1100                                        enum smu_clk_type clk_type,
1101                                        uint32_t *value)
1102 {
1103         static SmuMetrics_t metrics;
1104         int ret = 0, clk_id = 0;
1105
1106         if (!value)
1107                 return -EINVAL;
1108
1109         clk_id = smu_clk_get_index(smu, clk_type);
1110         if (clk_id < 0)
1111                 return -EINVAL;
1112
1113         ret = arcturus_get_metrics_table(smu, &metrics);
1114         if (ret)
1115                 return ret;
1116
1117         switch (clk_id) {
1118         case PPCLK_GFXCLK:
1119                 /*
1120                  * CurrClock[clk_id] can provide accurate
1121                  *   output only when the dpm feature is enabled.
1122                  * We can use Average_* for dpm disabled case.
1123                  *   But this is available for gfxclk/uclk/socclk.
1124                  */
1125                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
1126                         *value = metrics.CurrClock[PPCLK_GFXCLK];
1127                 else
1128                         *value = metrics.AverageGfxclkFrequency;
1129                 break;
1130         case PPCLK_UCLK:
1131                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
1132                         *value = metrics.CurrClock[PPCLK_UCLK];
1133                 else
1134                         *value = metrics.AverageUclkFrequency;
1135                 break;
1136         case PPCLK_SOCCLK:
1137                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
1138                         *value = metrics.CurrClock[PPCLK_SOCCLK];
1139                 else
1140                         *value = metrics.AverageSocclkFrequency;
1141                 break;
1142         default:
1143                 *value = metrics.CurrClock[clk_id];
1144                 break;
1145         }
1146
1147         return ret;
1148 }
1149
1150 static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table *table)
1151 {
1152         uint32_t i;
1153
1154         for (i = 0; i < table->count; i++) {
1155                 if (table->dpm_levels[i].enabled)
1156                         break;
1157         }
1158         if (i >= table->count) {
1159                 i = 0;
1160                 table->dpm_levels[i].enabled = true;
1161         }
1162
1163         return i;
1164 }
1165
1166 static uint32_t arcturus_find_highest_dpm_level(struct arcturus_single_dpm_table *table)
1167 {
1168         int i = 0;
1169
1170         if (table->count <= 0) {
1171                 pr_err("[%s] DPM Table has no entry!", __func__);
1172                 return 0;
1173         }
1174         if (table->count > MAX_DPM_NUMBER) {
1175                 pr_err("[%s] DPM Table has too many entries!", __func__);
1176                 return MAX_DPM_NUMBER - 1;
1177         }
1178
1179         for (i = table->count - 1; i >= 0; i--) {
1180                 if (table->dpm_levels[i].enabled)
1181                         break;
1182         }
1183         if (i < 0) {
1184                 i = 0;
1185                 table->dpm_levels[i].enabled = true;
1186         }
1187
1188         return i;
1189 }
1190
1191
1192
1193 static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
1194 {
1195         struct arcturus_dpm_table *dpm_table =
1196                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1197         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
1198         uint32_t soft_level;
1199         int ret = 0;
1200
1201         /* gfxclk */
1202         if (highest)
1203                 soft_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1204         else
1205                 soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1206
1207         dpm_table->gfx_table.dpm_state.soft_min_level =
1208                 dpm_table->gfx_table.dpm_state.soft_max_level =
1209                 dpm_table->gfx_table.dpm_levels[soft_level].value;
1210
1211         ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1212         if (ret) {
1213                 pr_err("Failed to upload boot level to %s!\n",
1214                                 highest ? "highest" : "lowest");
1215                 return ret;
1216         }
1217
1218         ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1219         if (ret) {
1220                 pr_err("Failed to upload dpm max level to %s!\n!",
1221                                 highest ? "highest" : "lowest");
1222                 return ret;
1223         }
1224
1225         if (hive)
1226                 /*
1227                  * Force XGMI Pstate to highest or lowest
1228                  * TODO: revise this when xgmi dpm is functional
1229                  */
1230                 ret = smu_v11_0_set_xgmi_pstate(smu, highest ? 1 : 0);
1231
1232         return ret;
1233 }
1234
1235 static int arcturus_unforce_dpm_levels(struct smu_context *smu)
1236 {
1237         struct arcturus_dpm_table *dpm_table =
1238                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1239         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
1240         uint32_t soft_min_level, soft_max_level;
1241         int ret = 0;
1242
1243         /* gfxclk */
1244         soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1245         soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1246         dpm_table->gfx_table.dpm_state.soft_min_level =
1247                 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
1248         dpm_table->gfx_table.dpm_state.soft_max_level =
1249                 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
1250
1251         ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1252         if (ret) {
1253                 pr_err("Failed to upload DPM Bootup Levels!");
1254                 return ret;
1255         }
1256
1257         ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1258         if (ret) {
1259                 pr_err("Failed to upload DPM Max Levels!");
1260                 return ret;
1261         }
1262
1263         if (hive)
1264                 /*
1265                  * Reset XGMI Pstate back to default
1266                  * TODO: revise this when xgmi dpm is functional
1267                  */
1268                 ret = smu_v11_0_set_xgmi_pstate(smu, 0);
1269
1270         return ret;
1271 }
1272
1273 static int
1274 arcturus_get_profiling_clk_mask(struct smu_context *smu,
1275                                 enum amd_dpm_forced_level level,
1276                                 uint32_t *sclk_mask,
1277                                 uint32_t *mclk_mask,
1278                                 uint32_t *soc_mask)
1279 {
1280         struct arcturus_dpm_table *dpm_table =
1281                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1282         struct arcturus_single_dpm_table *gfx_dpm_table;
1283         struct arcturus_single_dpm_table *mem_dpm_table;
1284         struct arcturus_single_dpm_table *soc_dpm_table;
1285
1286         if (!smu->smu_dpm.dpm_context)
1287                 return -EINVAL;
1288
1289         gfx_dpm_table = &dpm_table->gfx_table;
1290         mem_dpm_table = &dpm_table->mem_table;
1291         soc_dpm_table = &dpm_table->soc_table;
1292
1293         *sclk_mask = 0;
1294         *mclk_mask = 0;
1295         *soc_mask  = 0;
1296
1297         if (gfx_dpm_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
1298             mem_dpm_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
1299             soc_dpm_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
1300                 *sclk_mask = ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL;
1301                 *mclk_mask = ARCTURUS_UMD_PSTATE_MCLK_LEVEL;
1302                 *soc_mask  = ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL;
1303         }
1304
1305         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1306                 *sclk_mask = 0;
1307         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1308                 *mclk_mask = 0;
1309         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1310                 *sclk_mask = gfx_dpm_table->count - 1;
1311                 *mclk_mask = mem_dpm_table->count - 1;
1312                 *soc_mask  = soc_dpm_table->count - 1;
1313         }
1314
1315         return 0;
1316 }
1317
1318 static int arcturus_get_power_limit(struct smu_context *smu,
1319                                      uint32_t *limit,
1320                                      bool cap)
1321 {
1322         PPTable_t *pptable = smu->smu_table.driver_pptable;
1323         uint32_t asic_default_power_limit = 0;
1324         int ret = 0;
1325         int power_src;
1326
1327         if (!smu->power_limit) {
1328                 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1329                         power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1330                         if (power_src < 0)
1331                                 return -EINVAL;
1332
1333                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1334                                 power_src << 16, &asic_default_power_limit);
1335                         if (ret) {
1336                                 pr_err("[%s] get PPT limit failed!", __func__);
1337                                 return ret;
1338                         }
1339                 } else {
1340                         /* the last hope to figure out the ppt limit */
1341                         if (!pptable) {
1342                                 pr_err("Cannot get PPT limit due to pptable missing!");
1343                                 return -EINVAL;
1344                         }
1345                         asic_default_power_limit =
1346                                 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1347                 }
1348
1349                 smu->power_limit = asic_default_power_limit;
1350         }
1351
1352         if (cap)
1353                 *limit = smu_v11_0_get_max_power_limit(smu);
1354         else
1355                 *limit = smu->power_limit;
1356
1357         return 0;
1358 }
1359
1360 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1361                                            char *buf)
1362 {
1363         DpmActivityMonitorCoeffInt_t activity_monitor;
1364         static const char *profile_name[] = {
1365                                         "BOOTUP_DEFAULT",
1366                                         "3D_FULL_SCREEN",
1367                                         "POWER_SAVING",
1368                                         "VIDEO",
1369                                         "VR",
1370                                         "COMPUTE",
1371                                         "CUSTOM"};
1372         static const char *title[] = {
1373                         "PROFILE_INDEX(NAME)",
1374                         "CLOCK_TYPE(NAME)",
1375                         "FPS",
1376                         "UseRlcBusy",
1377                         "MinActiveFreqType",
1378                         "MinActiveFreq",
1379                         "BoosterFreqType",
1380                         "BoosterFreq",
1381                         "PD_Data_limit_c",
1382                         "PD_Data_error_coeff",
1383                         "PD_Data_error_rate_coeff"};
1384         uint32_t i, size = 0;
1385         int16_t workload_type = 0;
1386         int result = 0;
1387         uint32_t smu_version;
1388
1389         if (!buf)
1390                 return -EINVAL;
1391
1392         result = smu_get_smc_version(smu, NULL, &smu_version);
1393         if (result)
1394                 return result;
1395
1396         if (smu_version >= 0x360d00)
1397                 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1398                         title[0], title[1], title[2], title[3], title[4], title[5],
1399                         title[6], title[7], title[8], title[9], title[10]);
1400         else
1401                 size += sprintf(buf + size, "%16s\n",
1402                         title[0]);
1403
1404         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1405                 /*
1406                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1407                  * Not all profile modes are supported on arcturus.
1408                  */
1409                 workload_type = smu_workload_get_type(smu, i);
1410                 if (workload_type < 0)
1411                         continue;
1412
1413                 if (smu_version >= 0x360d00) {
1414                         result = smu_update_table(smu,
1415                                                   SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1416                                                   workload_type,
1417                                                   (void *)(&activity_monitor),
1418                                                   false);
1419                         if (result) {
1420                                 pr_err("[%s] Failed to get activity monitor!", __func__);
1421                                 return result;
1422                         }
1423                 }
1424
1425                 size += sprintf(buf + size, "%2d %14s%s\n",
1426                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1427
1428                 if (smu_version >= 0x360d00) {
1429                         size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1430                                 " ",
1431                                 0,
1432                                 "GFXCLK",
1433                                 activity_monitor.Gfx_FPS,
1434                                 activity_monitor.Gfx_UseRlcBusy,
1435                                 activity_monitor.Gfx_MinActiveFreqType,
1436                                 activity_monitor.Gfx_MinActiveFreq,
1437                                 activity_monitor.Gfx_BoosterFreqType,
1438                                 activity_monitor.Gfx_BoosterFreq,
1439                                 activity_monitor.Gfx_PD_Data_limit_c,
1440                                 activity_monitor.Gfx_PD_Data_error_coeff,
1441                                 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1442
1443                         size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1444                                 " ",
1445                                 1,
1446                                 "UCLK",
1447                                 activity_monitor.Mem_FPS,
1448                                 activity_monitor.Mem_UseRlcBusy,
1449                                 activity_monitor.Mem_MinActiveFreqType,
1450                                 activity_monitor.Mem_MinActiveFreq,
1451                                 activity_monitor.Mem_BoosterFreqType,
1452                                 activity_monitor.Mem_BoosterFreq,
1453                                 activity_monitor.Mem_PD_Data_limit_c,
1454                                 activity_monitor.Mem_PD_Data_error_coeff,
1455                                 activity_monitor.Mem_PD_Data_error_rate_coeff);
1456                 }
1457         }
1458
1459         return size;
1460 }
1461
1462 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1463                                            long *input,
1464                                            uint32_t size)
1465 {
1466         DpmActivityMonitorCoeffInt_t activity_monitor;
1467         int workload_type = 0;
1468         uint32_t profile_mode = input[size];
1469         int ret = 0;
1470         uint32_t smu_version;
1471
1472         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1473                 pr_err("Invalid power profile mode %d\n", profile_mode);
1474                 return -EINVAL;
1475         }
1476
1477         ret = smu_get_smc_version(smu, NULL, &smu_version);
1478         if (ret)
1479                 return ret;
1480
1481         if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1482              (smu_version >=0x360d00)) {
1483                 ret = smu_update_table(smu,
1484                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1485                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1486                                        (void *)(&activity_monitor),
1487                                        false);
1488                 if (ret) {
1489                         pr_err("[%s] Failed to get activity monitor!", __func__);
1490                         return ret;
1491                 }
1492
1493                 switch (input[0]) {
1494                 case 0: /* Gfxclk */
1495                         activity_monitor.Gfx_FPS = input[1];
1496                         activity_monitor.Gfx_UseRlcBusy = input[2];
1497                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1498                         activity_monitor.Gfx_MinActiveFreq = input[4];
1499                         activity_monitor.Gfx_BoosterFreqType = input[5];
1500                         activity_monitor.Gfx_BoosterFreq = input[6];
1501                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1502                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1503                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1504                         break;
1505                 case 1: /* Uclk */
1506                         activity_monitor.Mem_FPS = input[1];
1507                         activity_monitor.Mem_UseRlcBusy = input[2];
1508                         activity_monitor.Mem_MinActiveFreqType = input[3];
1509                         activity_monitor.Mem_MinActiveFreq = input[4];
1510                         activity_monitor.Mem_BoosterFreqType = input[5];
1511                         activity_monitor.Mem_BoosterFreq = input[6];
1512                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1513                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1514                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1515                         break;
1516                 }
1517
1518                 ret = smu_update_table(smu,
1519                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1520                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1521                                        (void *)(&activity_monitor),
1522                                        true);
1523                 if (ret) {
1524                         pr_err("[%s] Failed to set activity monitor!", __func__);
1525                         return ret;
1526                 }
1527         }
1528
1529         /*
1530          * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1531          * Not all profile modes are supported on arcturus.
1532          */
1533         workload_type = smu_workload_get_type(smu, profile_mode);
1534         if (workload_type < 0) {
1535                 pr_err("Unsupported power profile mode %d on arcturus\n", profile_mode);
1536                 return -EINVAL;
1537         }
1538
1539         ret = smu_send_smc_msg_with_param(smu,
1540                                           SMU_MSG_SetWorkloadMask,
1541                                           1 << workload_type,
1542                                           NULL);
1543         if (ret) {
1544                 pr_err("Fail to set workload type %d\n", workload_type);
1545                 return ret;
1546         }
1547
1548         smu->power_profile_mode = profile_mode;
1549
1550         return 0;
1551 }
1552
1553 static int arcturus_set_performance_level(struct smu_context *smu,
1554                                           enum amd_dpm_forced_level level)
1555 {
1556         uint32_t smu_version;
1557         int ret;
1558
1559         ret = smu_get_smc_version(smu, NULL, &smu_version);
1560         if (ret) {
1561                 pr_err("Failed to get smu version!\n");
1562                 return ret;
1563         }
1564
1565         switch (level) {
1566         case AMD_DPM_FORCED_LEVEL_HIGH:
1567         case AMD_DPM_FORCED_LEVEL_LOW:
1568         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1569         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1570         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1571         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1572                 if (smu_version >= 0x361200) {
1573                         pr_err("Forcing clock level is not supported with "
1574                                "54.18 and onwards SMU firmwares\n");
1575                         return -EOPNOTSUPP;
1576                 }
1577                 break;
1578         default:
1579                 break;
1580         }
1581
1582         return smu_v11_0_set_performance_level(smu, level);
1583 }
1584
1585 static void arcturus_dump_pptable(struct smu_context *smu)
1586 {
1587         struct smu_table_context *table_context = &smu->smu_table;
1588         PPTable_t *pptable = table_context->driver_pptable;
1589         int i;
1590
1591         pr_info("Dumped PPTable:\n");
1592
1593         pr_info("Version = 0x%08x\n", pptable->Version);
1594
1595         pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1596         pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1597
1598         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1599                 pr_info("SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1600                 pr_info("SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1601         }
1602
1603         pr_info("TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1604         pr_info("TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1605         pr_info("TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1606         pr_info("TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1607
1608         pr_info("TedgeLimit = %d\n", pptable->TedgeLimit);
1609         pr_info("ThotspotLimit = %d\n", pptable->ThotspotLimit);
1610         pr_info("TmemLimit = %d\n", pptable->TmemLimit);
1611         pr_info("Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1612         pr_info("Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1613         pr_info("Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1614         pr_info("FitLimit = %d\n", pptable->FitLimit);
1615
1616         pr_info("PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1617         pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1618
1619         pr_info("ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1620
1621         pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1622         pr_info("UlvPadding = 0x%08x\n", pptable->UlvPadding);
1623
1624         pr_info("UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1625         pr_info("Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1626         pr_info("Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1627         pr_info("Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1628
1629         pr_info("MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1630         pr_info("MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1631         pr_info("MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1632         pr_info("MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1633
1634         pr_info("LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1635         pr_info("LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1636
1637         pr_info("[PPCLK_GFXCLK]\n"
1638                         "  .VoltageMode          = 0x%02x\n"
1639                         "  .SnapToDiscrete       = 0x%02x\n"
1640                         "  .NumDiscreteLevels    = 0x%02x\n"
1641                         "  .padding              = 0x%02x\n"
1642                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1643                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1644                         "  .SsFmin               = 0x%04x\n"
1645                         "  .Padding_16           = 0x%04x\n",
1646                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1647                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1648                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1649                         pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1650                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1651                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1652                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1653                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1654                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1655                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1656                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1657
1658         pr_info("[PPCLK_VCLK]\n"
1659                         "  .VoltageMode          = 0x%02x\n"
1660                         "  .SnapToDiscrete       = 0x%02x\n"
1661                         "  .NumDiscreteLevels    = 0x%02x\n"
1662                         "  .padding              = 0x%02x\n"
1663                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1664                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1665                         "  .SsFmin               = 0x%04x\n"
1666                         "  .Padding_16           = 0x%04x\n",
1667                         pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1668                         pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1669                         pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1670                         pptable->DpmDescriptor[PPCLK_VCLK].padding,
1671                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1672                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1673                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1674                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1675                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1676                         pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1677                         pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1678
1679         pr_info("[PPCLK_DCLK]\n"
1680                         "  .VoltageMode          = 0x%02x\n"
1681                         "  .SnapToDiscrete       = 0x%02x\n"
1682                         "  .NumDiscreteLevels    = 0x%02x\n"
1683                         "  .padding              = 0x%02x\n"
1684                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1685                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1686                         "  .SsFmin               = 0x%04x\n"
1687                         "  .Padding_16           = 0x%04x\n",
1688                         pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1689                         pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1690                         pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1691                         pptable->DpmDescriptor[PPCLK_DCLK].padding,
1692                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1693                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1694                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1695                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1696                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1697                         pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1698                         pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1699
1700         pr_info("[PPCLK_SOCCLK]\n"
1701                         "  .VoltageMode          = 0x%02x\n"
1702                         "  .SnapToDiscrete       = 0x%02x\n"
1703                         "  .NumDiscreteLevels    = 0x%02x\n"
1704                         "  .padding              = 0x%02x\n"
1705                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1706                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1707                         "  .SsFmin               = 0x%04x\n"
1708                         "  .Padding_16           = 0x%04x\n",
1709                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1710                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1711                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1712                         pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1713                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1714                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1715                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1716                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1717                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1718                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1719                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1720
1721         pr_info("[PPCLK_UCLK]\n"
1722                         "  .VoltageMode          = 0x%02x\n"
1723                         "  .SnapToDiscrete       = 0x%02x\n"
1724                         "  .NumDiscreteLevels    = 0x%02x\n"
1725                         "  .padding              = 0x%02x\n"
1726                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1727                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1728                         "  .SsFmin               = 0x%04x\n"
1729                         "  .Padding_16           = 0x%04x\n",
1730                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1731                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1732                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1733                         pptable->DpmDescriptor[PPCLK_UCLK].padding,
1734                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1735                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1736                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1737                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1738                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1739                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1740                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1741
1742         pr_info("[PPCLK_FCLK]\n"
1743                         "  .VoltageMode          = 0x%02x\n"
1744                         "  .SnapToDiscrete       = 0x%02x\n"
1745                         "  .NumDiscreteLevels    = 0x%02x\n"
1746                         "  .padding              = 0x%02x\n"
1747                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1748                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1749                         "  .SsFmin               = 0x%04x\n"
1750                         "  .Padding_16           = 0x%04x\n",
1751                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1752                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1753                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1754                         pptable->DpmDescriptor[PPCLK_FCLK].padding,
1755                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1756                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1757                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1758                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1759                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1760                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1761                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1762
1763
1764         pr_info("FreqTableGfx\n");
1765         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1766                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1767
1768         pr_info("FreqTableVclk\n");
1769         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1770                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1771
1772         pr_info("FreqTableDclk\n");
1773         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1774                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1775
1776         pr_info("FreqTableSocclk\n");
1777         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1778                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1779
1780         pr_info("FreqTableUclk\n");
1781         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1782                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1783
1784         pr_info("FreqTableFclk\n");
1785         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1786                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1787
1788         pr_info("Mp0clkFreq\n");
1789         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1790                 pr_info("  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1791
1792         pr_info("Mp0DpmVoltage\n");
1793         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1794                 pr_info("  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1795
1796         pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1797         pr_info("GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1798         pr_info("Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1799         pr_info("Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1800         pr_info("Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1801         pr_info("Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1802         pr_info("GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1803         pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1804         pr_info("Padding456 = 0x%x\n", pptable->Padding456);
1805
1806         pr_info("EnableTdpm = %d\n", pptable->EnableTdpm);
1807         pr_info("TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1808         pr_info("TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1809         pr_info("GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1810
1811         pr_info("FanStopTemp = %d\n", pptable->FanStopTemp);
1812         pr_info("FanStartTemp = %d\n", pptable->FanStartTemp);
1813
1814         pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);
1815         pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);
1816         pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1817         pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1818         pr_info("FanGainVrMem = %d\n", pptable->FanGainVrMem);
1819         pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);
1820
1821         pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);
1822         pr_info("FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1823         pr_info("FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1824         pr_info("FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1825         pr_info("FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1826         pr_info("FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1827         pr_info("FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1828         pr_info("FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1829         pr_info("FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1830
1831         pr_info("FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1832         pr_info("FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1833         pr_info("FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1834         pr_info("FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1835
1836         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1837         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1838         pr_info("Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1839         pr_info("Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1840
1841         pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1842                         pptable->dBtcGbGfxPll.a,
1843                         pptable->dBtcGbGfxPll.b,
1844                         pptable->dBtcGbGfxPll.c);
1845         pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1846                         pptable->dBtcGbGfxAfll.a,
1847                         pptable->dBtcGbGfxAfll.b,
1848                         pptable->dBtcGbGfxAfll.c);
1849         pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1850                         pptable->dBtcGbSoc.a,
1851                         pptable->dBtcGbSoc.b,
1852                         pptable->dBtcGbSoc.c);
1853
1854         pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1855                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1856                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1857         pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1858                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1859                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1860
1861         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1862                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1863                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1864                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1865         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1866                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1867                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1868                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1869
1870         pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1871         pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1872
1873         pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1874         pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1875         pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1876         pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1877
1878         pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1879         pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1880         pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1881         pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1882
1883         pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1884         pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1885
1886         pr_info("XgmiDpmPstates\n");
1887         for (i = 0; i < NUM_XGMI_LEVELS; i++)
1888                 pr_info("  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1889         pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1890         pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1891
1892         pr_info("VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1893         pr_info("VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1894         pr_info("VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1895         pr_info("VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1896         pr_info("VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1897         pr_info("VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1898         pr_info("VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1899         pr_info("VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1900
1901         pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1902         pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1903                         pptable->ReservedEquation0.a,
1904                         pptable->ReservedEquation0.b,
1905                         pptable->ReservedEquation0.c);
1906         pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1907                         pptable->ReservedEquation1.a,
1908                         pptable->ReservedEquation1.b,
1909                         pptable->ReservedEquation1.c);
1910         pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1911                         pptable->ReservedEquation2.a,
1912                         pptable->ReservedEquation2.b,
1913                         pptable->ReservedEquation2.c);
1914         pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1915                         pptable->ReservedEquation3.a,
1916                         pptable->ReservedEquation3.b,
1917                         pptable->ReservedEquation3.c);
1918
1919         pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1920         pr_info("PaddingUlv = %d\n", pptable->PaddingUlv);
1921
1922         pr_info("TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1923         pr_info("TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1924         pr_info("TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1925
1926         pr_info("PccThresholdLow = %d\n", pptable->PccThresholdLow);
1927         pr_info("PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1928
1929         pr_info("Board Parameters:\n");
1930         pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1931         pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1932
1933         pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1934         pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1935         pr_info("VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1936         pr_info("BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1937
1938         pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1939         pr_info("ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1940
1941         pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1942         pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
1943         pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1944
1945         pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1946         pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
1947         pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1948
1949         pr_info("MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1950         pr_info("MemOffset = 0x%x\n", pptable->MemOffset);
1951         pr_info("Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1952
1953         pr_info("BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1954         pr_info("BoardOffset = 0x%x\n", pptable->BoardOffset);
1955         pr_info("Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1956
1957         pr_info("VR0HotGpio = %d\n", pptable->VR0HotGpio);
1958         pr_info("VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1959         pr_info("VR1HotGpio = %d\n", pptable->VR1HotGpio);
1960         pr_info("VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1961
1962         pr_info("PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1963         pr_info("PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1964         pr_info("PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1965
1966         pr_info("UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1967         pr_info("UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1968         pr_info("UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1969
1970         pr_info("FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1971         pr_info("FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1972         pr_info("FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1973
1974         pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1975         pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1976         pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1977
1978         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1979                 pr_info("I2cControllers[%d]:\n", i);
1980                 pr_info("                   .Enabled = %d\n",
1981                                 pptable->I2cControllers[i].Enabled);
1982                 pr_info("                   .SlaveAddress = 0x%x\n",
1983                                 pptable->I2cControllers[i].SlaveAddress);
1984                 pr_info("                   .ControllerPort = %d\n",
1985                                 pptable->I2cControllers[i].ControllerPort);
1986                 pr_info("                   .ControllerName = %d\n",
1987                                 pptable->I2cControllers[i].ControllerName);
1988                 pr_info("                   .ThermalThrottler = %d\n",
1989                                 pptable->I2cControllers[i].ThermalThrotter);
1990                 pr_info("                   .I2cProtocol = %d\n",
1991                                 pptable->I2cControllers[i].I2cProtocol);
1992                 pr_info("                   .Speed = %d\n",
1993                                 pptable->I2cControllers[i].Speed);
1994         }
1995
1996         pr_info("MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1997         pr_info("DramBitWidth = %d\n", pptable->DramBitWidth);
1998
1999         pr_info("TotalBoardPower = %d\n", pptable->TotalBoardPower);
2000
2001         pr_info("XgmiLinkSpeed\n");
2002         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2003                 pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
2004         pr_info("XgmiLinkWidth\n");
2005         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2006                 pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
2007         pr_info("XgmiFclkFreq\n");
2008         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2009                 pr_info("  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
2010         pr_info("XgmiSocVoltage\n");
2011         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2012                 pr_info("  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
2013
2014 }
2015
2016 static bool arcturus_is_dpm_running(struct smu_context *smu)
2017 {
2018         int ret = 0;
2019         uint32_t feature_mask[2];
2020         unsigned long feature_enabled;
2021         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
2022         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
2023                            ((uint64_t)feature_mask[1] << 32));
2024         return !!(feature_enabled & SMC_DPM_FEATURE);
2025 }
2026
2027 static int arcturus_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
2028 {
2029         struct smu_power_context *smu_power = &smu->smu_power;
2030         struct smu_power_gate *power_gate = &smu_power->power_gate;
2031         int ret = 0;
2032
2033         if (enable) {
2034                 if (!smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
2035                         ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
2036                         if (ret) {
2037                                 pr_err("[EnableVCNDPM] failed!\n");
2038                                 return ret;
2039                         }
2040                 }
2041                 power_gate->vcn_gated = false;
2042         } else {
2043                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
2044                         ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
2045                         if (ret) {
2046                                 pr_err("[DisableVCNDPM] failed!\n");
2047                                 return ret;
2048                         }
2049                 }
2050                 power_gate->vcn_gated = true;
2051         }
2052
2053         return ret;
2054 }
2055
2056
2057 static void arcturus_fill_eeprom_i2c_req(SwI2cRequest_t  *req, bool write,
2058                                   uint8_t address, uint32_t numbytes,
2059                                   uint8_t *data)
2060 {
2061         int i;
2062
2063         BUG_ON(numbytes > MAX_SW_I2C_COMMANDS);
2064
2065         req->I2CcontrollerPort = 0;
2066         req->I2CSpeed = 2;
2067         req->SlaveAddress = address;
2068         req->NumCmds = numbytes;
2069
2070         for (i = 0; i < numbytes; i++) {
2071                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
2072
2073                 /* First 2 bytes are always write for lower 2b EEPROM address */
2074                 if (i < 2)
2075                         cmd->Cmd = 1;
2076                 else
2077                         cmd->Cmd = write;
2078
2079
2080                 /* Add RESTART for read  after address filled */
2081                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
2082
2083                 /* Add STOP in the end */
2084                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
2085
2086                 /* Fill with data regardless if read or write to simplify code */
2087                 cmd->RegisterAddr = data[i];
2088         }
2089 }
2090
2091 static int arcturus_i2c_eeprom_read_data(struct i2c_adapter *control,
2092                                                uint8_t address,
2093                                                uint8_t *data,
2094                                                uint32_t numbytes)
2095 {
2096         uint32_t  i, ret = 0;
2097         SwI2cRequest_t req;
2098         struct amdgpu_device *adev = to_amdgpu_device(control);
2099         struct smu_table_context *smu_table = &adev->smu.smu_table;
2100         struct smu_table *table = &smu_table->driver_table;
2101
2102         memset(&req, 0, sizeof(req));
2103         arcturus_fill_eeprom_i2c_req(&req, false, address, numbytes, data);
2104
2105         mutex_lock(&adev->smu.mutex);
2106         /* Now read data starting with that address */
2107         ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
2108                                         true);
2109         mutex_unlock(&adev->smu.mutex);
2110
2111         if (!ret) {
2112                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
2113
2114                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
2115                 for (i = 0; i < numbytes; i++)
2116                         data[i] = res->SwI2cCmds[i].Data;
2117
2118                 pr_debug("arcturus_i2c_eeprom_read_data, address = %x, bytes = %d, data :",
2119                                   (uint16_t)address, numbytes);
2120
2121                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2122                                8, 1, data, numbytes, false);
2123         } else
2124                 pr_err("arcturus_i2c_eeprom_read_data - error occurred :%x", ret);
2125
2126         return ret;
2127 }
2128
2129 static int arcturus_i2c_eeprom_write_data(struct i2c_adapter *control,
2130                                                 uint8_t address,
2131                                                 uint8_t *data,
2132                                                 uint32_t numbytes)
2133 {
2134         uint32_t ret;
2135         SwI2cRequest_t req;
2136         struct amdgpu_device *adev = to_amdgpu_device(control);
2137
2138         memset(&req, 0, sizeof(req));
2139         arcturus_fill_eeprom_i2c_req(&req, true, address, numbytes, data);
2140
2141         mutex_lock(&adev->smu.mutex);
2142         ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
2143         mutex_unlock(&adev->smu.mutex);
2144
2145         if (!ret) {
2146                 pr_debug("arcturus_i2c_write(), address = %x, bytes = %d , data: ",
2147                                          (uint16_t)address, numbytes);
2148
2149                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2150                                8, 1, data, numbytes, false);
2151                 /*
2152                  * According to EEPROM spec there is a MAX of 10 ms required for
2153                  * EEPROM to flush internal RX buffer after STOP was issued at the
2154                  * end of write transaction. During this time the EEPROM will not be
2155                  * responsive to any more commands - so wait a bit more.
2156                  */
2157                 msleep(10);
2158
2159         } else
2160                 pr_err("arcturus_i2c_write- error occurred :%x", ret);
2161
2162         return ret;
2163 }
2164
2165 static int arcturus_i2c_eeprom_i2c_xfer(struct i2c_adapter *i2c_adap,
2166                               struct i2c_msg *msgs, int num)
2167 {
2168         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2169         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2170
2171         for (i = 0; i < num; i++) {
2172                 /*
2173                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2174                  * once and hence the data needs to be spliced into chunks and sent each
2175                  * chunk separately
2176                  */
2177                 data_size = msgs[i].len - 2;
2178                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2179                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2180                 data_ptr = msgs[i].buf + 2;
2181
2182                 for (j = 0; j < data_size / data_chunk_size; j++) {
2183                         /* Insert the EEPROM dest addess, bits 0-15 */
2184                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2185                         data_chunk[1] = (next_eeprom_addr & 0xff);
2186
2187                         if (msgs[i].flags & I2C_M_RD) {
2188                                 ret = arcturus_i2c_eeprom_read_data(i2c_adap,
2189                                                                 (uint8_t)msgs[i].addr,
2190                                                                 data_chunk, MAX_SW_I2C_COMMANDS);
2191
2192                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2193                         } else {
2194
2195                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2196
2197                                 ret = arcturus_i2c_eeprom_write_data(i2c_adap,
2198                                                                  (uint8_t)msgs[i].addr,
2199                                                                  data_chunk, MAX_SW_I2C_COMMANDS);
2200                         }
2201
2202                         if (ret) {
2203                                 num = -EIO;
2204                                 goto fail;
2205                         }
2206
2207                         next_eeprom_addr += data_chunk_size;
2208                         data_ptr += data_chunk_size;
2209                 }
2210
2211                 if (data_size % data_chunk_size) {
2212                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2213                         data_chunk[1] = (next_eeprom_addr & 0xff);
2214
2215                         if (msgs[i].flags & I2C_M_RD) {
2216                                 ret = arcturus_i2c_eeprom_read_data(i2c_adap,
2217                                                                 (uint8_t)msgs[i].addr,
2218                                                                 data_chunk, (data_size % data_chunk_size) + 2);
2219
2220                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2221                         } else {
2222                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2223
2224                                 ret = arcturus_i2c_eeprom_write_data(i2c_adap,
2225                                                                  (uint8_t)msgs[i].addr,
2226                                                                  data_chunk, (data_size % data_chunk_size) + 2);
2227                         }
2228
2229                         if (ret) {
2230                                 num = -EIO;
2231                                 goto fail;
2232                         }
2233                 }
2234         }
2235
2236 fail:
2237         return num;
2238 }
2239
2240 static u32 arcturus_i2c_eeprom_i2c_func(struct i2c_adapter *adap)
2241 {
2242         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2243 }
2244
2245
2246 static const struct i2c_algorithm arcturus_i2c_eeprom_i2c_algo = {
2247         .master_xfer = arcturus_i2c_eeprom_i2c_xfer,
2248         .functionality = arcturus_i2c_eeprom_i2c_func,
2249 };
2250
2251 static bool arcturus_i2c_adapter_is_added(struct i2c_adapter *control)
2252 {
2253         struct amdgpu_device *adev = to_amdgpu_device(control);
2254
2255         return control->dev.parent == &adev->pdev->dev;
2256 }
2257
2258 static int arcturus_i2c_eeprom_control_init(struct i2c_adapter *control)
2259 {
2260         struct amdgpu_device *adev = to_amdgpu_device(control);
2261         int res;
2262
2263         /* smu_i2c_eeprom_init may be called twice in sriov */
2264         if (arcturus_i2c_adapter_is_added(control))
2265                 return 0;
2266
2267         control->owner = THIS_MODULE;
2268         control->class = I2C_CLASS_SPD;
2269         control->dev.parent = &adev->pdev->dev;
2270         control->algo = &arcturus_i2c_eeprom_i2c_algo;
2271         snprintf(control->name, sizeof(control->name), "AMDGPU EEPROM");
2272
2273         res = i2c_add_adapter(control);
2274         if (res)
2275                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2276
2277         return res;
2278 }
2279
2280 static void arcturus_i2c_eeprom_control_fini(struct i2c_adapter *control)
2281 {
2282         if (!arcturus_i2c_adapter_is_added(control))
2283                 return;
2284
2285         i2c_del_adapter(control);
2286 }
2287
2288 static void arcturus_get_unique_id(struct smu_context *smu)
2289 {
2290         struct amdgpu_device *adev = smu->adev;
2291         uint32_t top32, bottom32, smu_version, size;
2292         char sn[16];
2293         uint64_t id;
2294
2295         if (smu_get_smc_version(smu, NULL, &smu_version)) {
2296                 pr_warn("Failed to get smu version, cannot get unique_id or serial_number\n");
2297                 return;
2298         }
2299
2300         /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
2301         if (smu_version < 0x361700) {
2302                 pr_warn("ReadSerial is only supported by PMFW 54.23.0 and onwards\n");
2303                 return;
2304         }
2305
2306         /* Get the SN to turn into a Unique ID */
2307         smu_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2308         smu_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
2309
2310         id = ((uint64_t)bottom32 << 32) | top32;
2311         adev->unique_id = id;
2312         /* For Arcturus-and-later, unique_id == serial_number, so convert it to a
2313          * 16-digit HEX string for convenience and backwards-compatibility
2314          */
2315         size = sprintf(sn, "%llx", id);
2316         memcpy(adev->serial, &sn, size);
2317 }
2318
2319 static bool arcturus_is_baco_supported(struct smu_context *smu)
2320 {
2321         struct amdgpu_device *adev = smu->adev;
2322         uint32_t val;
2323
2324         if (!smu_v11_0_baco_is_support(smu) || amdgpu_sriov_vf(adev))
2325                 return false;
2326
2327         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
2328         return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
2329 }
2330
2331 static uint32_t arcturus_get_pptable_power_limit(struct smu_context *smu)
2332 {
2333         PPTable_t *pptable = smu->smu_table.driver_pptable;
2334
2335         return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
2336 }
2337
2338 static int arcturus_set_df_cstate(struct smu_context *smu,
2339                                   enum pp_df_cstate state)
2340 {
2341         uint32_t smu_version;
2342         int ret;
2343
2344         ret = smu_get_smc_version(smu, NULL, &smu_version);
2345         if (ret) {
2346                 pr_err("Failed to get smu version!\n");
2347                 return ret;
2348         }
2349
2350         /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
2351         if (smu_version < 0x360F00) {
2352                 pr_err("DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
2353                 return -EINVAL;
2354         }
2355
2356         return smu_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
2357 }
2358
2359 static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en)
2360 {
2361         uint32_t smu_version;
2362         int ret;
2363
2364         ret = smu_get_smc_version(smu, NULL, &smu_version);
2365         if (ret) {
2366                 pr_err("Failed to get smu version!\n");
2367                 return ret;
2368         }
2369
2370         /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */
2371         if (smu_version < 0x00361700) {
2372                 pr_err("XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");
2373                 return -EINVAL;
2374         }
2375
2376         if (en)
2377                 return smu_send_smc_msg_with_param(smu,
2378                                                    SMU_MSG_GmiPwrDnControl,
2379                                                    1,
2380                                                    NULL);
2381
2382         return smu_send_smc_msg_with_param(smu,
2383                                            SMU_MSG_GmiPwrDnControl,
2384                                            0,
2385                                            NULL);
2386 }
2387
2388 static const struct throttling_logging_label {
2389         uint32_t feature_mask;
2390         const char *label;
2391 } logging_label[] = {
2392         {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
2393         {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
2394         {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
2395         {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
2396         {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
2397         {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"},
2398         {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"},
2399 };
2400 static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
2401 {
2402         int throttler_idx, throtting_events = 0, buf_idx = 0;
2403         struct amdgpu_device *adev = smu->adev;
2404         SmuMetrics_t metrics;
2405         char log_buf[256];
2406
2407         arcturus_get_metrics_table(smu, &metrics);
2408
2409         memset(log_buf, 0, sizeof(log_buf));
2410         for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
2411              throttler_idx++) {
2412                 if (metrics.ThrottlerStatus & logging_label[throttler_idx].feature_mask) {
2413                         throtting_events++;
2414                         buf_idx += snprintf(log_buf + buf_idx,
2415                                             sizeof(log_buf) - buf_idx,
2416                                             "%s%s",
2417                                             throtting_events > 1 ? " and " : "",
2418                                             logging_label[throttler_idx].label);
2419                         if (buf_idx >= sizeof(log_buf)) {
2420                                 pr_err("buffer overflow!\n");
2421                                 log_buf[sizeof(log_buf) - 1] = '\0';
2422                                 break;
2423                         }
2424                 }
2425         }
2426
2427         dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
2428                         log_buf);
2429 }
2430
2431 static const struct pptable_funcs arcturus_ppt_funcs = {
2432         /* translate smu index into arcturus specific index */
2433         .get_smu_msg_index = arcturus_get_smu_msg_index,
2434         .get_smu_clk_index = arcturus_get_smu_clk_index,
2435         .get_smu_feature_index = arcturus_get_smu_feature_index,
2436         .get_smu_table_index = arcturus_get_smu_table_index,
2437         .get_smu_power_index= arcturus_get_pwr_src_index,
2438         .get_workload_type = arcturus_get_workload_type,
2439         /* internal structurs allocations */
2440         .tables_init = arcturus_tables_init,
2441         .alloc_dpm_context = arcturus_allocate_dpm_context,
2442         /* init dpm */
2443         .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2444         /* btc */
2445         .run_btc = arcturus_run_btc,
2446         /* dpm/clk tables */
2447         .set_default_dpm_table = arcturus_set_default_dpm_table,
2448         .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2449         .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2450         .get_current_clk_freq_by_table = arcturus_get_current_clk_freq_by_table,
2451         .print_clk_levels = arcturus_print_clk_levels,
2452         .force_clk_levels = arcturus_force_clk_levels,
2453         .read_sensor = arcturus_read_sensor,
2454         .get_fan_speed_percent = arcturus_get_fan_speed_percent,
2455         .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
2456         .force_dpm_limit_value = arcturus_force_dpm_limit_value,
2457         .unforce_dpm_levels = arcturus_unforce_dpm_levels,
2458         .get_profiling_clk_mask = arcturus_get_profiling_clk_mask,
2459         .get_power_profile_mode = arcturus_get_power_profile_mode,
2460         .set_power_profile_mode = arcturus_set_power_profile_mode,
2461         .set_performance_level = arcturus_set_performance_level,
2462         /* debug (internal used) */
2463         .dump_pptable = arcturus_dump_pptable,
2464         .get_power_limit = arcturus_get_power_limit,
2465         .is_dpm_running = arcturus_is_dpm_running,
2466         .dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
2467         .i2c_eeprom_init = arcturus_i2c_eeprom_control_init,
2468         .i2c_eeprom_fini = arcturus_i2c_eeprom_control_fini,
2469         .get_unique_id = arcturus_get_unique_id,
2470         .init_microcode = smu_v11_0_init_microcode,
2471         .load_microcode = smu_v11_0_load_microcode,
2472         .init_smc_tables = smu_v11_0_init_smc_tables,
2473         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2474         .init_power = smu_v11_0_init_power,
2475         .fini_power = smu_v11_0_fini_power,
2476         .check_fw_status = smu_v11_0_check_fw_status,
2477         /* pptable related */
2478         .setup_pptable = arcturus_setup_pptable,
2479         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2480         .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2481         .check_fw_version = smu_v11_0_check_fw_version,
2482         .write_pptable = smu_v11_0_write_pptable,
2483         .set_min_dcef_deep_sleep = NULL,
2484         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2485         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2486         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2487         .system_features_control = smu_v11_0_system_features_control,
2488         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2489         .init_display_count = NULL,
2490         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2491         .get_enabled_mask = smu_v11_0_get_enabled_mask,
2492         .notify_display_change = NULL,
2493         .set_power_limit = smu_v11_0_set_power_limit,
2494         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2495         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2496         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2497         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2498         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2499         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2500         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2501         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2502         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2503         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2504         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2505         .gfx_off_control = smu_v11_0_gfx_off_control,
2506         .register_irq_handler = smu_v11_0_register_irq_handler,
2507         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2508         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2509         .baco_is_support= arcturus_is_baco_supported,
2510         .baco_get_state = smu_v11_0_baco_get_state,
2511         .baco_set_state = smu_v11_0_baco_set_state,
2512         .baco_enter = smu_v11_0_baco_enter,
2513         .baco_exit = smu_v11_0_baco_exit,
2514         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2515         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2516         .override_pcie_parameters = NULL,
2517         .get_pptable_power_limit = arcturus_get_pptable_power_limit,
2518         .set_df_cstate = arcturus_set_df_cstate,
2519         .allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
2520         .log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
2521 };
2522
2523 void arcturus_set_ppt_funcs(struct smu_context *smu)
2524 {
2525         smu->ppt_funcs = &arcturus_ppt_funcs;
2526 }