drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "atomfirmware.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "smu_v11_0.h"
  31 #include "smu11_driver_if_arcturus.h"
  32 #include "soc15_common.h"
  33 #include "atom.h"
  34 #include "power_state.h"
  35 #include "arcturus_ppt.h"
  36 #include "smu_v11_0_pptable.h"
  37 #include "arcturus_ppsmc.h"
  38 #include "nbio/nbio_7_4_sh_mask.h"
  39
  40 #define CTF_OFFSET_EDGE                 5
  41 #define CTF_OFFSET_HOTSPOT              5
  42 #define CTF_OFFSET_HBM                  5
  43
  44 #define MSG_MAP(msg, index) \
  45         [SMU_MSG_##msg] = {1, (index)}
  46 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
  47         [smu_feature] = {1, (arcturus_feature)}
  48
  49 #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  50 #define SMU_FEATURES_LOW_SHIFT       0
  51 #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  52 #define SMU_FEATURES_HIGH_SHIFT      32
  53
  54 #define SMC_DPM_FEATURE ( \
  55         FEATURE_DPM_PREFETCHER_MASK | \
  56         FEATURE_DPM_GFXCLK_MASK | \
  57         FEATURE_DPM_UCLK_MASK | \
  58         FEATURE_DPM_SOCCLK_MASK | \
  59         FEATURE_DPM_MP0CLK_MASK | \
  60         FEATURE_DPM_FCLK_MASK | \
  61         FEATURE_DPM_XGMI_MASK)
  62
  63 /* possible frequency drift (1Mhz) */
  64 #define EPSILON                         1
  65
  66 static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
  67         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage),
  68         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion),
  69         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion),
  70         MSG_MAP(SetAllowedFeaturesMaskLow,           PPSMC_MSG_SetAllowedFeaturesMaskLow),
  71         MSG_MAP(SetAllowedFeaturesMaskHigh,          PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  72         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures),
  73         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures),
  74         MSG_MAP(EnableSmuFeaturesLow,                PPSMC_MSG_EnableSmuFeaturesLow),
  75         MSG_MAP(EnableSmuFeaturesHigh,               PPSMC_MSG_EnableSmuFeaturesHigh),
  76         MSG_MAP(DisableSmuFeaturesLow,               PPSMC_MSG_DisableSmuFeaturesLow),
  77         MSG_MAP(DisableSmuFeaturesHigh,              PPSMC_MSG_DisableSmuFeaturesHigh),
  78         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow),
  79         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  80         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh),
  81         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow),
  82         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh),
  83         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow),
  84         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram),
  85         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu),
  86         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable),
  87         MSG_MAP(UseBackupPPTable,                    PPSMC_MSG_UseBackupPPTable),
  88         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh),
  89         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow),
  90         MSG_MAP(EnterBaco,                           PPSMC_MSG_EnterBaco),
  91         MSG_MAP(ExitBaco,                            PPSMC_MSG_ExitBaco),
  92         MSG_MAP(ArmD3,                               PPSMC_MSG_ArmD3),
  93         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq),
  94         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq),
  95         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq),
  96         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq),
  97         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq),
  98         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq),
  99         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex),
 100         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask),
 101         MSG_MAP(SetDfSwitchType,                     PPSMC_MSG_SetDfSwitchType),
 102         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm),
 103         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive),
 104         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit),
 105         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit),
 106         MSG_MAP(PowerUpVcn0,                         PPSMC_MSG_PowerUpVcn0),
 107         MSG_MAP(PowerDownVcn0,                       PPSMC_MSG_PowerDownVcn0),
 108         MSG_MAP(PowerUpVcn1,                         PPSMC_MSG_PowerUpVcn1),
 109         MSG_MAP(PowerDownVcn1,                       PPSMC_MSG_PowerDownVcn1),
 110         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload),
 111         MSG_MAP(PrepareMp1ForReset,                  PPSMC_MSG_PrepareMp1ForReset),
 112         MSG_MAP(PrepareMp1ForShutdown,               PPSMC_MSG_PrepareMp1ForShutdown),
 113         MSG_MAP(SoftReset,                           PPSMC_MSG_SoftReset),
 114         MSG_MAP(RunAfllBtc,                          PPSMC_MSG_RunAfllBtc),
 115         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc),
 116         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh),
 117         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow),
 118         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize),
 119         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData),
 120         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest),
 121         MSG_MAP(SetXgmiMode,                         PPSMC_MSG_SetXgmiMode),
 122         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable),
 123 };
 124
 125 static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
 126         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 127         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 128         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 129         CLK_MAP(FCLK, PPCLK_FCLK),
 130         CLK_MAP(UCLK, PPCLK_UCLK),
 131         CLK_MAP(MCLK, PPCLK_UCLK),
 132         CLK_MAP(DCLK, PPCLK_DCLK),
 133         CLK_MAP(VCLK, PPCLK_VCLK),
 134 };
 135
 136 static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
 137         FEA_MAP(DPM_PREFETCHER),
 138         FEA_MAP(DPM_GFXCLK),
 139         FEA_MAP(DPM_UCLK),
 140         FEA_MAP(DPM_SOCCLK),
 141         FEA_MAP(DPM_FCLK),
 142         FEA_MAP(DPM_MP0CLK),
 143         ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
 144         FEA_MAP(DS_GFXCLK),
 145         FEA_MAP(DS_SOCCLK),
 146         FEA_MAP(DS_LCLK),
 147         FEA_MAP(DS_FCLK),
 148         FEA_MAP(DS_UCLK),
 149         FEA_MAP(GFX_ULV),
 150         ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
 151         FEA_MAP(RSMU_SMN_CG),
 152         FEA_MAP(WAFL_CG),
 153         FEA_MAP(PPT),
 154         FEA_MAP(TDC),
 155         FEA_MAP(APCC_PLUS),
 156         FEA_MAP(VR0HOT),
 157         FEA_MAP(VR1HOT),
 158         FEA_MAP(FW_CTF),
 159         FEA_MAP(FAN_CONTROL),
 160         FEA_MAP(THERMAL),
 161         FEA_MAP(OUT_OF_BAND_MONITOR),
 162         FEA_MAP(TEMP_DEPENDENT_VMIN),
 163 };
 164
 165 static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
 166         TAB_MAP(PPTABLE),
 167         TAB_MAP(AVFS),
 168         TAB_MAP(AVFS_PSM_DEBUG),
 169         TAB_MAP(AVFS_FUSE_OVERRIDE),
 170         TAB_MAP(PMSTATUSLOG),
 171         TAB_MAP(SMU_METRICS),
 172         TAB_MAP(DRIVER_SMU_CONFIG),
 173         TAB_MAP(OVERDRIVE),
 174 };
 175
 176 static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 177         PWR_MAP(AC),
 178         PWR_MAP(DC),
 179 };
 180
 181 static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 182         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 183         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 184         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 185         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 186         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 187 };
 188
 189 static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 190 {
 191         struct smu_11_0_cmn2aisc_mapping mapping;
 192
 193         if (index >= SMU_MSG_MAX_COUNT)
 194                 return -EINVAL;
 195
 196         mapping = arcturus_message_map[index];
 197         if (!(mapping.valid_mapping))
 198                 return -EINVAL;
 199
 200         return mapping.map_to;
 201 }
 202
 203 static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 204 {
 205         struct smu_11_0_cmn2aisc_mapping mapping;
 206
 207         if (index >= SMU_CLK_COUNT)
 208                 return -EINVAL;
 209
 210         mapping = arcturus_clk_map[index];
 211         if (!(mapping.valid_mapping)) {
 212                 pr_warn("Unsupported SMU clk: %d\n", index);
 213                 return -EINVAL;
 214         }
 215
 216         return mapping.map_to;
 217 }
 218
 219 static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 220 {
 221         struct smu_11_0_cmn2aisc_mapping mapping;
 222
 223         if (index >= SMU_FEATURE_COUNT)
 224                 return -EINVAL;
 225
 226         mapping = arcturus_feature_mask_map[index];
 227         if (!(mapping.valid_mapping)) {
 228                 return -EINVAL;
 229         }
 230
 231         return mapping.map_to;
 232 }
 233
 234 static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)
 235 {
 236         struct smu_11_0_cmn2aisc_mapping mapping;
 237
 238         if (index >= SMU_TABLE_COUNT)
 239                 return -EINVAL;
 240
 241         mapping = arcturus_table_map[index];
 242         if (!(mapping.valid_mapping)) {
 243                 pr_warn("Unsupported SMU table: %d\n", index);
 244                 return -EINVAL;
 245         }
 246
 247         return mapping.map_to;
 248 }
 249
 250 static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 251 {
 252         struct smu_11_0_cmn2aisc_mapping mapping;
 253
 254         if (index >= SMU_POWER_SOURCE_COUNT)
 255                 return -EINVAL;
 256
 257         mapping = arcturus_pwr_src_map[index];
 258         if (!(mapping.valid_mapping)) {
 259                 pr_warn("Unsupported SMU power source: %d\n", index);
 260                 return -EINVAL;
 261         }
 262
 263         return mapping.map_to;
 264 }
 265
 266
 267 static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 268 {
 269         struct smu_11_0_cmn2aisc_mapping mapping;
 270
 271         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 272                 return -EINVAL;
 273
 274         mapping = arcturus_workload_map[profile];
 275         if (!(mapping.valid_mapping)) {
 276                 pr_warn("Unsupported SMU power source: %d\n", profile);
 277                 return -EINVAL;
 278         }
 279
 280         return mapping.map_to;
 281 }
 282
 283 static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
 284 {
 285         struct smu_table_context *smu_table = &smu->smu_table;
 286
 287         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 288                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 289
 290         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 291                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 292
 293         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 294                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 295
 296         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 297         if (!smu_table->metrics_table)
 298                 return -ENOMEM;
 299         smu_table->metrics_time = 0;
 300
 301         return 0;
 302 }
 303
 304 static int arcturus_allocate_dpm_context(struct smu_context *smu)
 305 {
 306         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 307
 308         if (smu_dpm->dpm_context)
 309                 return -EINVAL;
 310
 311         smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
 312                                        GFP_KERNEL);
 313         if (!smu_dpm->dpm_context)
 314                 return -ENOMEM;
 315
 316         if (smu_dpm->golden_dpm_context)
 317                 return -EINVAL;
 318
 319         smu_dpm->golden_dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
 320                                               GFP_KERNEL);
 321         if (!smu_dpm->golden_dpm_context)
 322                 return -ENOMEM;
 323
 324         smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
 325
 326         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 327                                        GFP_KERNEL);
 328         if (!smu_dpm->dpm_current_power_state)
 329                 return -ENOMEM;
 330
 331         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 332                                        GFP_KERNEL);
 333         if (!smu_dpm->dpm_request_power_state)
 334                 return -ENOMEM;
 335
 336         return 0;
 337 }
 338
 339 static int
 340 arcturus_get_allowed_feature_mask(struct smu_context *smu,
 341                                   uint32_t *feature_mask, uint32_t num)
 342 {
 343         if (num > 2)
 344                 return -EINVAL;
 345
 346         /* pptable will handle the features to enable */
 347         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 348
 349         return 0;
 350 }
 351
 352 static int
 353 arcturus_set_single_dpm_table(struct smu_context *smu,
 354                             struct arcturus_single_dpm_table *single_dpm_table,
 355                             PPCLK_e clk_id)
 356 {
 357         int ret = 0;
 358         uint32_t i, num_of_levels = 0, clk;
 359
 360         ret = smu_send_smc_msg_with_param(smu,
 361                         SMU_MSG_GetDpmFreqByIndex,
 362                         (clk_id << 16 | 0xFF));
 363         if (ret) {
 364                 pr_err("[%s] failed to get dpm levels!\n", __func__);
 365                 return ret;
 366         }
 367
 368         smu_read_smc_arg(smu, &num_of_levels);
 369         if (!num_of_levels) {
 370                 pr_err("[%s] number of clk levels is invalid!\n", __func__);
 371                 return -EINVAL;
 372         }
 373
 374         single_dpm_table->count = num_of_levels;
 375         for (i = 0; i < num_of_levels; i++) {
 376                 ret = smu_send_smc_msg_with_param(smu,
 377                                 SMU_MSG_GetDpmFreqByIndex,
 378                                 (clk_id << 16 | i));
 379                 if (ret) {
 380                         pr_err("[%s] failed to get dpm freq by index!\n", __func__);
 381                         return ret;
 382                 }
 383                 smu_read_smc_arg(smu, &clk);
 384                 if (!clk) {
 385                         pr_err("[%s] clk value is invalid!\n", __func__);
 386                         return -EINVAL;
 387                 }
 388                 single_dpm_table->dpm_levels[i].value = clk;
 389                 single_dpm_table->dpm_levels[i].enabled = true;
 390         }
 391         return 0;
 392 }
 393
 394 static void arcturus_init_single_dpm_state(struct arcturus_dpm_state *dpm_state)
 395 {
 396         dpm_state->soft_min_level = 0x0;
 397         dpm_state->soft_max_level = 0xffff;
 398         dpm_state->hard_min_level = 0x0;
 399         dpm_state->hard_max_level = 0xffff;
 400 }
 401
 402 static int arcturus_set_default_dpm_table(struct smu_context *smu)
 403 {
 404         int ret;
 405
 406         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 407         struct arcturus_dpm_table *dpm_table = NULL;
 408         struct arcturus_single_dpm_table *single_dpm_table;
 409
 410         dpm_table = smu_dpm->dpm_context;
 411
 412         /* socclk */
 413         single_dpm_table = &(dpm_table->soc_table);
 414         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 415                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 416                                                   PPCLK_SOCCLK);
 417                 if (ret) {
 418                         pr_err("[%s] failed to get socclk dpm levels!\n", __func__);
 419                         return ret;
 420                 }
 421         } else {
 422                 single_dpm_table->count = 1;
 423                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 424         }
 425         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 426
 427         /* gfxclk */
 428         single_dpm_table = &(dpm_table->gfx_table);
 429         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 430                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 431                                                   PPCLK_GFXCLK);
 432                 if (ret) {
 433                         pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
 434                         return ret;
 435                 }
 436         } else {
 437                 single_dpm_table->count = 1;
 438                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 439         }
 440         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 441
 442         /* memclk */
 443         single_dpm_table = &(dpm_table->mem_table);
 444         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 445                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 446                                                   PPCLK_UCLK);
 447                 if (ret) {
 448                         pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
 449                         return ret;
 450                 }
 451         } else {
 452                 single_dpm_table->count = 1;
 453                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 454         }
 455         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 456
 457         /* fclk */
 458         single_dpm_table = &(dpm_table->fclk_table);
 459         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 460                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 461                                                   PPCLK_FCLK);
 462                 if (ret) {
 463                         pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
 464                         return ret;
 465                 }
 466         } else {
 467                 single_dpm_table->count = 1;
 468                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 469         }
 470         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 471
 472         memcpy(smu_dpm->golden_dpm_context, dpm_table,
 473                sizeof(struct arcturus_dpm_table));
 474
 475         return 0;
 476 }
 477
 478 static int arcturus_check_powerplay_table(struct smu_context *smu)
 479 {
 480         return 0;
 481 }
 482
 483 static int arcturus_store_powerplay_table(struct smu_context *smu)
 484 {
 485         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 486         struct smu_table_context *table_context = &smu->smu_table;
 487         int ret = 0;
 488
 489         if (!table_context->power_play_table)
 490                 return -EINVAL;
 491
 492         powerplay_table = table_context->power_play_table;
 493
 494         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 495                sizeof(PPTable_t));
 496
 497         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 498
 499         return ret;
 500 }
 501
 502 static int arcturus_append_powerplay_table(struct smu_context *smu)
 503 {
 504         struct smu_table_context *table_context = &smu->smu_table;
 505         PPTable_t *smc_pptable = table_context->driver_pptable;
 506         struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
 507         int index, ret;
 508
 509         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 510                                            smc_dpm_info);
 511
 512         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 513                                       (uint8_t **)&smc_dpm_table);
 514         if (ret)
 515                 return ret;
 516
 517         pr_info("smc_dpm_info table revision(format.content): %d.%d\n",
 518                         smc_dpm_table->table_header.format_revision,
 519                         smc_dpm_table->table_header.content_revision);
 520
 521         if ((smc_dpm_table->table_header.format_revision == 4) &&
 522             (smc_dpm_table->table_header.content_revision == 6))
 523                 memcpy(&smc_pptable->MaxVoltageStepGfx,
 524                        &smc_dpm_table->maxvoltagestepgfx,
 525                        sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
 526
 527         return 0;
 528 }
 529
 530 static int arcturus_run_btc(struct smu_context *smu)
 531 {
 532         int ret = 0;
 533
 534         ret = smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
 535         if (ret) {
 536                 pr_err("RunAfllBtc failed!\n");
 537                 return ret;
 538         }
 539
 540         return smu_send_smc_msg(smu, SMU_MSG_RunDcBtc);
 541 }
 542
 543 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 544 {
 545         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 546         struct arcturus_dpm_table *dpm_table = NULL;
 547         struct arcturus_single_dpm_table *gfx_table = NULL;
 548         struct arcturus_single_dpm_table *mem_table = NULL;
 549
 550         dpm_table = smu_dpm->dpm_context;
 551         gfx_table = &(dpm_table->gfx_table);
 552         mem_table = &(dpm_table->mem_table);
 553
 554         smu->pstate_sclk = gfx_table->dpm_levels[0].value;
 555         smu->pstate_mclk = mem_table->dpm_levels[0].value;
 556
 557         if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
 558             mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL) {
 559                 smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
 560                 smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
 561         }
 562
 563         smu->pstate_sclk = smu->pstate_sclk * 100;
 564         smu->pstate_mclk = smu->pstate_mclk * 100;
 565
 566         return 0;
 567 }
 568
 569 static int arcturus_get_clk_table(struct smu_context *smu,
 570                         struct pp_clock_levels_with_latency *clocks,
 571                         struct arcturus_single_dpm_table *dpm_table)
 572 {
 573         int i, count;
 574
 575         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 576         clocks->num_levels = count;
 577
 578         for (i = 0; i < count; i++) {
 579                 clocks->data[i].clocks_in_khz =
 580                         dpm_table->dpm_levels[i].value * 1000;
 581                 clocks->data[i].latency_in_us = 0;
 582         }
 583
 584         return 0;
 585 }
 586
 587 static int arcturus_freqs_in_same_level(int32_t frequency1,
 588                                         int32_t frequency2)
 589 {
 590         return (abs(frequency1 - frequency2) <= EPSILON);
 591 }
 592
 593 static int arcturus_print_clk_levels(struct smu_context *smu,
 594                         enum smu_clk_type type, char *buf)
 595 {
 596         int i, now, size = 0;
 597         int ret = 0;
 598         struct pp_clock_levels_with_latency clocks;
 599         struct arcturus_single_dpm_table *single_dpm_table;
 600         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 601         struct arcturus_dpm_table *dpm_table = NULL;
 602
 603         dpm_table = smu_dpm->dpm_context;
 604
 605         switch (type) {
 606         case SMU_SCLK:
 607                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
 608                 if (ret) {
 609                         pr_err("Attempt to get current gfx clk Failed!");
 610                         return ret;
 611                 }
 612
 613                 single_dpm_table = &(dpm_table->gfx_table);
 614                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 615                 if (ret) {
 616                         pr_err("Attempt to get gfx clk levels Failed!");
 617                         return ret;
 618                 }
 619
 620                 for (i = 0; i < clocks.num_levels; i++)
 621                         size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 622                                         clocks.data[i].clocks_in_khz / 1000,
 623                                         arcturus_freqs_in_same_level(
 624                                         clocks.data[i].clocks_in_khz / 1000,
 625                                         now / 100) ? "*" : "");
 626                 break;
 627
 628         case SMU_MCLK:
 629                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
 630                 if (ret) {
 631                         pr_err("Attempt to get current mclk Failed!");
 632                         return ret;
 633                 }
 634
 635                 single_dpm_table = &(dpm_table->mem_table);
 636                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 637                 if (ret) {
 638                         pr_err("Attempt to get memory clk levels Failed!");
 639                         return ret;
 640                 }
 641
 642                 for (i = 0; i < clocks.num_levels; i++)
 643                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 644                                 i, clocks.data[i].clocks_in_khz / 1000,
 645                                 arcturus_freqs_in_same_level(
 646                                 clocks.data[i].clocks_in_khz / 1000,
 647                                 now / 100) ? "*" : "");
 648                 break;
 649
 650         case SMU_SOCCLK:
 651                 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
 652                 if (ret) {
 653                         pr_err("Attempt to get current socclk Failed!");
 654                         return ret;
 655                 }
 656
 657                 single_dpm_table = &(dpm_table->soc_table);
 658                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 659                 if (ret) {
 660                         pr_err("Attempt to get socclk levels Failed!");
 661                         return ret;
 662                 }
 663
 664                 for (i = 0; i < clocks.num_levels; i++)
 665                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 666                                 i, clocks.data[i].clocks_in_khz / 1000,
 667                                 arcturus_freqs_in_same_level(
 668                                 clocks.data[i].clocks_in_khz / 1000,
 669                                 now / 100) ? "*" : "");
 670                 break;
 671
 672         case SMU_FCLK:
 673                 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
 674                 if (ret) {
 675                         pr_err("Attempt to get current fclk Failed!");
 676                         return ret;
 677                 }
 678
 679                 single_dpm_table = &(dpm_table->fclk_table);
 680                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 681                 if (ret) {
 682                         pr_err("Attempt to get fclk levels Failed!");
 683                         return ret;
 684                 }
 685
 686                 for (i = 0; i < single_dpm_table->count; i++)
 687                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 688                                 i, single_dpm_table->dpm_levels[i].value,
 689                                 arcturus_freqs_in_same_level(
 690                                 clocks.data[i].clocks_in_khz / 1000,
 691                                 now / 100) ? "*" : "");
 692                 break;
 693
 694         default:
 695                 break;
 696         }
 697
 698         return size;
 699 }
 700
 701 static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
 702                                      uint32_t feature_mask)
 703 {
 704         struct arcturus_single_dpm_table *single_dpm_table;
 705         struct arcturus_dpm_table *dpm_table =
 706                         smu->smu_dpm.dpm_context;
 707         uint32_t freq;
 708         int ret = 0;
 709
 710         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 711             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 712                 single_dpm_table = &(dpm_table->gfx_table);
 713                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 714                         single_dpm_table->dpm_state.soft_min_level;
 715                 ret = smu_send_smc_msg_with_param(smu,
 716                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 717                         (PPCLK_GFXCLK << 16) | (freq & 0xffff));
 718                 if (ret) {
 719                         pr_err("Failed to set soft %s gfxclk !\n",
 720                                                 max ? "max" : "min");
 721                         return ret;
 722                 }
 723         }
 724
 725         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 726             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 727                 single_dpm_table = &(dpm_table->mem_table);
 728                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 729                         single_dpm_table->dpm_state.soft_min_level;
 730                 ret = smu_send_smc_msg_with_param(smu,
 731                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 732                         (PPCLK_UCLK << 16) | (freq & 0xffff));
 733                 if (ret) {
 734                         pr_err("Failed to set soft %s memclk !\n",
 735                                                 max ? "max" : "min");
 736                         return ret;
 737                 }
 738         }
 739
 740         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 741             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
 742                 single_dpm_table = &(dpm_table->soc_table);
 743                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 744                         single_dpm_table->dpm_state.soft_min_level;
 745                 ret = smu_send_smc_msg_with_param(smu,
 746                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 747                         (PPCLK_SOCCLK << 16) | (freq & 0xffff));
 748                 if (ret) {
 749                         pr_err("Failed to set soft %s socclk !\n",
 750                                                 max ? "max" : "min");
 751                         return ret;
 752                 }
 753         }
 754
 755         return ret;
 756 }
 757
 758 static int arcturus_force_clk_levels(struct smu_context *smu,
 759                         enum smu_clk_type type, uint32_t mask)
 760 {
 761         struct arcturus_dpm_table *dpm_table;
 762         struct arcturus_single_dpm_table *single_dpm_table;
 763         uint32_t soft_min_level, soft_max_level;
 764         int ret = 0;
 765
 766         mutex_lock(&(smu->mutex));
 767
 768         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 769         soft_max_level = mask ? (fls(mask) - 1) : 0;
 770
 771         dpm_table = smu->smu_dpm.dpm_context;
 772
 773         switch (type) {
 774         case SMU_SCLK:
 775                 single_dpm_table = &(dpm_table->gfx_table);
 776
 777                 if (soft_max_level >= single_dpm_table->count) {
 778                         pr_err("Clock level specified %d is over max allowed %d\n",
 779                                         soft_max_level, single_dpm_table->count - 1);
 780                         ret = -EINVAL;
 781                         break;
 782                 }
 783
 784                 single_dpm_table->dpm_state.soft_min_level =
 785                         single_dpm_table->dpm_levels[soft_min_level].value;
 786                 single_dpm_table->dpm_state.soft_max_level =
 787                         single_dpm_table->dpm_levels[soft_max_level].value;
 788
 789                 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
 790                 if (ret) {
 791                         pr_err("Failed to upload boot level to lowest!\n");
 792                         break;
 793                 }
 794
 795                 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
 796                 if (ret)
 797                         pr_err("Failed to upload dpm max level to highest!\n");
 798
 799                 break;
 800
 801         case SMU_MCLK:
 802                 single_dpm_table = &(dpm_table->mem_table);
 803
 804                 if (soft_max_level >= single_dpm_table->count) {
 805                         pr_err("Clock level specified %d is over max allowed %d\n",
 806                                         soft_max_level, single_dpm_table->count - 1);
 807                         ret = -EINVAL;
 808                         break;
 809                 }
 810
 811                 single_dpm_table->dpm_state.soft_min_level =
 812                         single_dpm_table->dpm_levels[soft_min_level].value;
 813                 single_dpm_table->dpm_state.soft_max_level =
 814                         single_dpm_table->dpm_levels[soft_max_level].value;
 815
 816                 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
 817                 if (ret) {
 818                         pr_err("Failed to upload boot level to lowest!\n");
 819                         break;
 820                 }
 821
 822                 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
 823                 if (ret)
 824                         pr_err("Failed to upload dpm max level to highest!\n");
 825
 826                 break;
 827
 828         case SMU_SOCCLK:
 829                 single_dpm_table = &(dpm_table->soc_table);
 830
 831                 if (soft_max_level >= single_dpm_table->count) {
 832                         pr_err("Clock level specified %d is over max allowed %d\n",
 833                                         soft_max_level, single_dpm_table->count - 1);
 834                         ret = -EINVAL;
 835                         break;
 836                 }
 837
 838                 single_dpm_table->dpm_state.soft_min_level =
 839                         single_dpm_table->dpm_levels[soft_min_level].value;
 840                 single_dpm_table->dpm_state.soft_max_level =
 841                         single_dpm_table->dpm_levels[soft_max_level].value;
 842
 843                 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
 844                 if (ret) {
 845                         pr_err("Failed to upload boot level to lowest!\n");
 846                         break;
 847                 }
 848
 849                 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
 850                 if (ret)
 851                         pr_err("Failed to upload dpm max level to highest!\n");
 852
 853                 break;
 854
 855         case SMU_FCLK:
 856                 single_dpm_table = &(dpm_table->fclk_table);
 857
 858                 if (soft_max_level >= single_dpm_table->count) {
 859                         pr_err("Clock level specified %d is over max allowed %d\n",
 860                                         soft_max_level, single_dpm_table->count - 1);
 861                         ret = -EINVAL;
 862                         break;
 863                 }
 864
 865                 single_dpm_table->dpm_state.soft_min_level =
 866                         single_dpm_table->dpm_levels[soft_min_level].value;
 867                 single_dpm_table->dpm_state.soft_max_level =
 868                         single_dpm_table->dpm_levels[soft_max_level].value;
 869
 870                 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
 871                 if (ret) {
 872                         pr_err("Failed to upload boot level to lowest!\n");
 873                         break;
 874                 }
 875
 876                 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
 877                 if (ret)
 878                         pr_err("Failed to upload dpm max level to highest!\n");
 879
 880                 break;
 881
 882         default:
 883                 break;
 884         }
 885
 886         mutex_unlock(&(smu->mutex));
 887         return ret;
 888 }
 889
 890 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
 891                                                 struct smu_temperature_range *range)
 892 {
 893         PPTable_t *pptable = smu->smu_table.driver_pptable;
 894
 895         if (!range)
 896                 return -EINVAL;
 897
 898         range->max = pptable->TedgeLimit *
 899                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 900         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
 901                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 902         range->hotspot_crit_max = pptable->ThotspotLimit *
 903                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 904         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
 905                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 906         range->mem_crit_max = pptable->TmemLimit *
 907                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 908         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)*
 909                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 910
 911         return 0;
 912 }
 913
 914 static int arcturus_get_metrics_table(struct smu_context *smu,
 915                                       SmuMetrics_t *metrics_table)
 916 {
 917         struct smu_table_context *smu_table= &smu->smu_table;
 918         int ret = 0;
 919
 920         if (!smu_table->metrics_time ||
 921              time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
 922                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 923                                 (void *)smu_table->metrics_table, false);
 924                 if (ret) {
 925                         pr_info("Failed to export SMU metrics table!\n");
 926                         return ret;
 927                 }
 928                 smu_table->metrics_time = jiffies;
 929         }
 930
 931         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 932
 933         return ret;
 934 }
 935
 936 static int arcturus_get_current_activity_percent(struct smu_context *smu,
 937                                                  enum amd_pp_sensors sensor,
 938                                                  uint32_t *value)
 939 {
 940         SmuMetrics_t metrics;
 941         int ret = 0;
 942
 943         if (!value)
 944                 return -EINVAL;
 945
 946         ret = arcturus_get_metrics_table(smu, &metrics);
 947         if (ret)
 948                 return ret;
 949
 950         switch (sensor) {
 951         case AMDGPU_PP_SENSOR_GPU_LOAD:
 952                 *value = metrics.AverageGfxActivity;
 953                 break;
 954         case AMDGPU_PP_SENSOR_MEM_LOAD:
 955                 *value = metrics.AverageUclkActivity;
 956                 break;
 957         default:
 958                 pr_err("Invalid sensor for retrieving clock activity\n");
 959                 return -EINVAL;
 960         }
 961
 962         return 0;
 963 }
 964
 965 static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
 966 {
 967         SmuMetrics_t metrics;
 968         int ret = 0;
 969
 970         if (!value)
 971                 return -EINVAL;
 972
 973         ret = arcturus_get_metrics_table(smu, &metrics);
 974         if (ret)
 975                 return ret;
 976
 977         *value = metrics.AverageSocketPower << 8;
 978
 979         return 0;
 980 }
 981
 982 static int arcturus_thermal_get_temperature(struct smu_context *smu,
 983                                             enum amd_pp_sensors sensor,
 984                                             uint32_t *value)
 985 {
 986         SmuMetrics_t metrics;
 987         int ret = 0;
 988
 989         if (!value)
 990                 return -EINVAL;
 991
 992         ret = arcturus_get_metrics_table(smu, &metrics);
 993         if (ret)
 994                 return ret;
 995
 996         switch (sensor) {
 997         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 998                 *value = metrics.TemperatureHotspot *
 999                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1000                 break;
1001         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1002                 *value = metrics.TemperatureEdge *
1003                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1004                 break;
1005         case AMDGPU_PP_SENSOR_MEM_TEMP:
1006                 *value = metrics.TemperatureHBM *
1007                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1008                 break;
1009         default:
1010                 pr_err("Invalid sensor for retrieving temp\n");
1011                 return -EINVAL;
1012         }
1013
1014         return 0;
1015 }
1016
1017 static int arcturus_read_sensor(struct smu_context *smu,
1018                                 enum amd_pp_sensors sensor,
1019                                 void *data, uint32_t *size)
1020 {
1021         struct smu_table_context *table_context = &smu->smu_table;
1022         PPTable_t *pptable = table_context->driver_pptable;
1023         int ret = 0;
1024
1025         if (!data || !size)
1026                 return -EINVAL;
1027
1028         mutex_lock(&smu->sensor_lock);
1029         switch (sensor) {
1030         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1031                 *(uint32_t *)data = pptable->FanMaximumRpm;
1032                 *size = 4;
1033                 break;
1034         case AMDGPU_PP_SENSOR_MEM_LOAD:
1035         case AMDGPU_PP_SENSOR_GPU_LOAD:
1036                 ret = arcturus_get_current_activity_percent(smu,
1037                                                             sensor,
1038                                                 (uint32_t *)data);
1039                 *size = 4;
1040                 break;
1041         case AMDGPU_PP_SENSOR_GPU_POWER:
1042                 ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
1043                 *size = 4;
1044                 break;
1045         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1046         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1047         case AMDGPU_PP_SENSOR_MEM_TEMP:
1048                 ret = arcturus_thermal_get_temperature(smu, sensor,
1049                                                 (uint32_t *)data);
1050                 *size = 4;
1051                 break;
1052         default:
1053                 ret = smu_smc_read_sensor(smu, sensor, data, size);
1054         }
1055         mutex_unlock(&smu->sensor_lock);
1056
1057         return ret;
1058 }
1059
1060 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1061                                       uint32_t *speed)
1062 {
1063         SmuMetrics_t metrics;
1064         int ret = 0;
1065
1066         if (!speed)
1067                 return -EINVAL;
1068
1069         ret = arcturus_get_metrics_table(smu, &metrics);
1070         if (ret)
1071                 return ret;
1072
1073         *speed = metrics.CurrFanSpeed;
1074
1075         return ret;
1076 }
1077
1078 static int arcturus_get_fan_speed_percent(struct smu_context *smu,
1079                                           uint32_t *speed)
1080 {
1081         PPTable_t *pptable = smu->smu_table.driver_pptable;
1082         uint32_t percent, current_rpm;
1083         int ret = 0;
1084
1085         if (!speed)
1086                 return -EINVAL;
1087
1088         ret = arcturus_get_fan_speed_rpm(smu, &current_rpm);
1089         if (ret)
1090                 return ret;
1091
1092         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1093         *speed = percent > 100 ? 100 : percent;
1094
1095         return ret;
1096 }
1097
1098 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
1099                                        enum smu_clk_type clk_type,
1100                                        uint32_t *value)
1101 {
1102         static SmuMetrics_t metrics;
1103         int ret = 0, clk_id = 0;
1104
1105         if (!value)
1106                 return -EINVAL;
1107
1108         clk_id = smu_clk_get_index(smu, clk_type);
1109         if (clk_id < 0)
1110                 return -EINVAL;
1111
1112         ret = arcturus_get_metrics_table(smu, &metrics);
1113         if (ret)
1114                 return ret;
1115
1116         switch (clk_id) {
1117         case PPCLK_GFXCLK:
1118                 /*
1119                  * CurrClock[clk_id] can provide accurate
1120                  *   output only when the dpm feature is enabled.
1121                  * We can use Average_* for dpm disabled case.
1122                  *   But this is available for gfxclk/uclk/socclk.
1123                  */
1124                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
1125                         *value = metrics.CurrClock[PPCLK_GFXCLK];
1126                 else
1127                         *value = metrics.AverageGfxclkFrequency;
1128                 break;
1129         case PPCLK_UCLK:
1130                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
1131                         *value = metrics.CurrClock[PPCLK_UCLK];
1132                 else
1133                         *value = metrics.AverageUclkFrequency;
1134                 break;
1135         case PPCLK_SOCCLK:
1136                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
1137                         *value = metrics.CurrClock[PPCLK_SOCCLK];
1138                 else
1139                         *value = metrics.AverageSocclkFrequency;
1140                 break;
1141         default:
1142                 *value = metrics.CurrClock[clk_id];
1143                 break;
1144         }
1145
1146         return ret;
1147 }
1148
1149 static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table *table)
1150 {
1151         uint32_t i;
1152
1153         for (i = 0; i < table->count; i++) {
1154                 if (table->dpm_levels[i].enabled)
1155                         break;
1156         }
1157         if (i >= table->count) {
1158                 i = 0;
1159                 table->dpm_levels[i].enabled = true;
1160         }
1161
1162         return i;
1163 }
1164
1165 static uint32_t arcturus_find_highest_dpm_level(struct arcturus_single_dpm_table *table)
1166 {
1167         int i = 0;
1168
1169         if (table->count <= 0) {
1170                 pr_err("[%s] DPM Table has no entry!", __func__);
1171                 return 0;
1172         }
1173         if (table->count > MAX_DPM_NUMBER) {
1174                 pr_err("[%s] DPM Table has too many entries!", __func__);
1175                 return MAX_DPM_NUMBER - 1;
1176         }
1177
1178         for (i = table->count - 1; i >= 0; i--) {
1179                 if (table->dpm_levels[i].enabled)
1180                         break;
1181         }
1182         if (i < 0) {
1183                 i = 0;
1184                 table->dpm_levels[i].enabled = true;
1185         }
1186
1187         return i;
1188 }
1189
1190
1191
1192 static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
1193 {
1194         struct arcturus_dpm_table *dpm_table =
1195                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1196         uint32_t soft_level;
1197         int ret = 0;
1198
1199         /* gfxclk */
1200         if (highest)
1201                 soft_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1202         else
1203                 soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1204
1205         dpm_table->gfx_table.dpm_state.soft_min_level =
1206                 dpm_table->gfx_table.dpm_state.soft_max_level =
1207                 dpm_table->gfx_table.dpm_levels[soft_level].value;
1208
1209         /* uclk */
1210         if (highest)
1211                 soft_level = arcturus_find_highest_dpm_level(&(dpm_table->mem_table));
1212         else
1213                 soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->mem_table));
1214
1215         dpm_table->mem_table.dpm_state.soft_min_level =
1216                 dpm_table->mem_table.dpm_state.soft_max_level =
1217                 dpm_table->mem_table.dpm_levels[soft_level].value;
1218
1219         /* socclk */
1220         if (highest)
1221                 soft_level = arcturus_find_highest_dpm_level(&(dpm_table->soc_table));
1222         else
1223                 soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->soc_table));
1224
1225         dpm_table->soc_table.dpm_state.soft_min_level =
1226                 dpm_table->soc_table.dpm_state.soft_max_level =
1227                 dpm_table->soc_table.dpm_levels[soft_level].value;
1228
1229         ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
1230         if (ret) {
1231                 pr_err("Failed to upload boot level to %s!\n",
1232                                 highest ? "highest" : "lowest");
1233                 return ret;
1234         }
1235
1236         ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
1237         if (ret) {
1238                 pr_err("Failed to upload dpm max level to %s!\n!",
1239                                 highest ? "highest" : "lowest");
1240                 return ret;
1241         }
1242
1243         return ret;
1244 }
1245
1246 static int arcturus_unforce_dpm_levels(struct smu_context *smu)
1247 {
1248         struct arcturus_dpm_table *dpm_table =
1249                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1250         uint32_t soft_min_level, soft_max_level;
1251         int ret = 0;
1252
1253         /* gfxclk */
1254         soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1255         soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1256         dpm_table->gfx_table.dpm_state.soft_min_level =
1257                 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
1258         dpm_table->gfx_table.dpm_state.soft_max_level =
1259                 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
1260
1261         /* uclk */
1262         soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->mem_table));
1263         soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->mem_table));
1264         dpm_table->mem_table.dpm_state.soft_min_level =
1265                 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
1266         dpm_table->mem_table.dpm_state.soft_max_level =
1267                 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
1268
1269         /* socclk */
1270         soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->soc_table));
1271         soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->soc_table));
1272         dpm_table->soc_table.dpm_state.soft_min_level =
1273                 dpm_table->soc_table.dpm_levels[soft_min_level].value;
1274         dpm_table->soc_table.dpm_state.soft_max_level =
1275                 dpm_table->soc_table.dpm_levels[soft_max_level].value;
1276
1277         ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
1278         if (ret) {
1279                 pr_err("Failed to upload DPM Bootup Levels!");
1280                 return ret;
1281         }
1282
1283         ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
1284         if (ret) {
1285                 pr_err("Failed to upload DPM Max Levels!");
1286                 return ret;
1287         }
1288
1289         return ret;
1290 }
1291
1292 static int
1293 arcturus_get_profiling_clk_mask(struct smu_context *smu,
1294                                 enum amd_dpm_forced_level level,
1295                                 uint32_t *sclk_mask,
1296                                 uint32_t *mclk_mask,
1297                                 uint32_t *soc_mask)
1298 {
1299         struct arcturus_dpm_table *dpm_table =
1300                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1301         struct arcturus_single_dpm_table *gfx_dpm_table;
1302         struct arcturus_single_dpm_table *mem_dpm_table;
1303         struct arcturus_single_dpm_table *soc_dpm_table;
1304
1305         if (!smu->smu_dpm.dpm_context)
1306                 return -EINVAL;
1307
1308         gfx_dpm_table = &dpm_table->gfx_table;
1309         mem_dpm_table = &dpm_table->mem_table;
1310         soc_dpm_table = &dpm_table->soc_table;
1311
1312         *sclk_mask = 0;
1313         *mclk_mask = 0;
1314         *soc_mask  = 0;
1315
1316         if (gfx_dpm_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
1317             mem_dpm_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
1318             soc_dpm_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
1319                 *sclk_mask = ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL;
1320                 *mclk_mask = ARCTURUS_UMD_PSTATE_MCLK_LEVEL;
1321                 *soc_mask  = ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL;
1322         }
1323
1324         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1325                 *sclk_mask = 0;
1326         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1327                 *mclk_mask = 0;
1328         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1329                 *sclk_mask = gfx_dpm_table->count - 1;
1330                 *mclk_mask = mem_dpm_table->count - 1;
1331                 *soc_mask  = soc_dpm_table->count - 1;
1332         }
1333
1334         return 0;
1335 }
1336
1337 static int arcturus_get_power_limit(struct smu_context *smu,
1338                                      uint32_t *limit,
1339                                      bool asic_default)
1340 {
1341         PPTable_t *pptable = smu->smu_table.driver_pptable;
1342         uint32_t asic_default_power_limit = 0;
1343         int ret = 0;
1344         int power_src;
1345
1346         if (!smu->default_power_limit ||
1347             !smu->power_limit) {
1348                 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1349                         power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1350                         if (power_src < 0)
1351                                 return -EINVAL;
1352
1353                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1354                                 power_src << 16);
1355                         if (ret) {
1356                                 pr_err("[%s] get PPT limit failed!", __func__);
1357                                 return ret;
1358                         }
1359                         smu_read_smc_arg(smu, &asic_default_power_limit);
1360                 } else {
1361                         /* the last hope to figure out the ppt limit */
1362                         if (!pptable) {
1363                                 pr_err("Cannot get PPT limit due to pptable missing!");
1364                                 return -EINVAL;
1365                         }
1366                         asic_default_power_limit =
1367                                 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1368                 }
1369
1370                 if (smu->od_enabled) {
1371                         asic_default_power_limit *= (100 + smu->smu_table.TDPODLimit);
1372                         asic_default_power_limit /= 100;
1373                 }
1374
1375                 smu->default_power_limit = asic_default_power_limit;
1376                 smu->power_limit = asic_default_power_limit;
1377         }
1378
1379         if (asic_default)
1380                 *limit = smu->default_power_limit;
1381         else
1382                 *limit = smu->power_limit;
1383
1384         return 0;
1385 }
1386
1387 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1388                                            char *buf)
1389 {
1390         static const char *profile_name[] = {
1391                                         "BOOTUP_DEFAULT",
1392                                         "3D_FULL_SCREEN",
1393                                         "POWER_SAVING",
1394                                         "VIDEO",
1395                                         "VR",
1396                                         "COMPUTE",
1397                                         "CUSTOM"};
1398         uint32_t i, size = 0;
1399         int16_t workload_type = 0;
1400
1401         if (!smu->pm_enabled || !buf)
1402                 return -EINVAL;
1403
1404         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1405                 /*
1406                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1407                  * Not all profile modes are supported on arcturus.
1408                  */
1409                 workload_type = smu_workload_get_type(smu, i);
1410                 if (workload_type < 0)
1411                         continue;
1412
1413                 size += sprintf(buf + size, "%2d %14s%s\n",
1414                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1415         }
1416
1417         return size;
1418 }
1419
1420 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1421                                            long *input,
1422                                            uint32_t size)
1423 {
1424         int workload_type = 0;
1425         uint32_t profile_mode = input[size];
1426         int ret = 0;
1427
1428         if (!smu->pm_enabled)
1429                 return -EINVAL;
1430
1431         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1432                 pr_err("Invalid power profile mode %d\n", profile_mode);
1433                 return -EINVAL;
1434         }
1435
1436         /*
1437          * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1438          * Not all profile modes are supported on arcturus.
1439          */
1440         workload_type = smu_workload_get_type(smu, profile_mode);
1441         if (workload_type < 0) {
1442                 pr_err("Unsupported power profile mode %d on arcturus\n", profile_mode);
1443                 return -EINVAL;
1444         }
1445
1446         ret = smu_send_smc_msg_with_param(smu,
1447                                           SMU_MSG_SetWorkloadMask,
1448                                           1 << workload_type);
1449         if (ret) {
1450                 pr_err("Fail to set workload type %d\n", workload_type);
1451                 return ret;
1452         }
1453
1454         smu->power_profile_mode = profile_mode;
1455
1456         return 0;
1457 }
1458
1459 static void arcturus_dump_pptable(struct smu_context *smu)
1460 {
1461         struct smu_table_context *table_context = &smu->smu_table;
1462         PPTable_t *pptable = table_context->driver_pptable;
1463         int i;
1464
1465         pr_info("Dumped PPTable:\n");
1466
1467         pr_info("Version = 0x%08x\n", pptable->Version);
1468
1469         pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1470         pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1471
1472         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1473                 pr_info("SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1474                 pr_info("SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1475         }
1476
1477         pr_info("TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1478         pr_info("TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1479         pr_info("TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1480         pr_info("TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1481
1482         pr_info("TedgeLimit = %d\n", pptable->TedgeLimit);
1483         pr_info("ThotspotLimit = %d\n", pptable->ThotspotLimit);
1484         pr_info("TmemLimit = %d\n", pptable->TmemLimit);
1485         pr_info("Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1486         pr_info("Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1487         pr_info("Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1488         pr_info("FitLimit = %d\n", pptable->FitLimit);
1489
1490         pr_info("PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1491         pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1492
1493         pr_info("ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1494
1495         pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1496         pr_info("UlvPadding = 0x%08x\n", pptable->UlvPadding);
1497
1498         pr_info("UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1499         pr_info("Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1500         pr_info("Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1501         pr_info("Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1502
1503         pr_info("MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1504         pr_info("MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1505         pr_info("MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1506         pr_info("MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1507
1508         pr_info("LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1509         pr_info("LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1510
1511         pr_info("[PPCLK_GFXCLK]\n"
1512                         "  .VoltageMode          = 0x%02x\n"
1513                         "  .SnapToDiscrete       = 0x%02x\n"
1514                         "  .NumDiscreteLevels    = 0x%02x\n"
1515                         "  .padding              = 0x%02x\n"
1516                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1517                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1518                         "  .SsFmin               = 0x%04x\n"
1519                         "  .Padding_16           = 0x%04x\n",
1520                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1521                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1522                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1523                         pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1524                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1525                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1526                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1527                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1528                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1529                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1530                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1531
1532         pr_info("[PPCLK_VCLK]\n"
1533                         "  .VoltageMode          = 0x%02x\n"
1534                         "  .SnapToDiscrete       = 0x%02x\n"
1535                         "  .NumDiscreteLevels    = 0x%02x\n"
1536                         "  .padding              = 0x%02x\n"
1537                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1538                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1539                         "  .SsFmin               = 0x%04x\n"
1540                         "  .Padding_16           = 0x%04x\n",
1541                         pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1542                         pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1543                         pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1544                         pptable->DpmDescriptor[PPCLK_VCLK].padding,
1545                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1546                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1547                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1548                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1549                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1550                         pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1551                         pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1552
1553         pr_info("[PPCLK_DCLK]\n"
1554                         "  .VoltageMode          = 0x%02x\n"
1555                         "  .SnapToDiscrete       = 0x%02x\n"
1556                         "  .NumDiscreteLevels    = 0x%02x\n"
1557                         "  .padding              = 0x%02x\n"
1558                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1559                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1560                         "  .SsFmin               = 0x%04x\n"
1561                         "  .Padding_16           = 0x%04x\n",
1562                         pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1563                         pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1564                         pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1565                         pptable->DpmDescriptor[PPCLK_DCLK].padding,
1566                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1567                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1568                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1569                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1570                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1571                         pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1572                         pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1573
1574         pr_info("[PPCLK_SOCCLK]\n"
1575                         "  .VoltageMode          = 0x%02x\n"
1576                         "  .SnapToDiscrete       = 0x%02x\n"
1577                         "  .NumDiscreteLevels    = 0x%02x\n"
1578                         "  .padding              = 0x%02x\n"
1579                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1580                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1581                         "  .SsFmin               = 0x%04x\n"
1582                         "  .Padding_16           = 0x%04x\n",
1583                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1584                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1585                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1586                         pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1587                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1588                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1589                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1590                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1591                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1592                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1593                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1594
1595         pr_info("[PPCLK_UCLK]\n"
1596                         "  .VoltageMode          = 0x%02x\n"
1597                         "  .SnapToDiscrete       = 0x%02x\n"
1598                         "  .NumDiscreteLevels    = 0x%02x\n"
1599                         "  .padding              = 0x%02x\n"
1600                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1601                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1602                         "  .SsFmin               = 0x%04x\n"
1603                         "  .Padding_16           = 0x%04x\n",
1604                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1605                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1606                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1607                         pptable->DpmDescriptor[PPCLK_UCLK].padding,
1608                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1609                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1610                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1611                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1612                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1613                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1614                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1615
1616         pr_info("[PPCLK_FCLK]\n"
1617                         "  .VoltageMode          = 0x%02x\n"
1618                         "  .SnapToDiscrete       = 0x%02x\n"
1619                         "  .NumDiscreteLevels    = 0x%02x\n"
1620                         "  .padding              = 0x%02x\n"
1621                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1622                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1623                         "  .SsFmin               = 0x%04x\n"
1624                         "  .Padding_16           = 0x%04x\n",
1625                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1626                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1627                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1628                         pptable->DpmDescriptor[PPCLK_FCLK].padding,
1629                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1630                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1631                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1632                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1633                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1634                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1635                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1636
1637
1638         pr_info("FreqTableGfx\n");
1639         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1640                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1641
1642         pr_info("FreqTableVclk\n");
1643         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1644                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1645
1646         pr_info("FreqTableDclk\n");
1647         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1648                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1649
1650         pr_info("FreqTableSocclk\n");
1651         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1652                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1653
1654         pr_info("FreqTableUclk\n");
1655         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1656                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1657
1658         pr_info("FreqTableFclk\n");
1659         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1660                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1661
1662         pr_info("Mp0clkFreq\n");
1663         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1664                 pr_info("  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1665
1666         pr_info("Mp0DpmVoltage\n");
1667         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1668                 pr_info("  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1669
1670         pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1671         pr_info("GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1672         pr_info("Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1673         pr_info("Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1674         pr_info("Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1675         pr_info("Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1676         pr_info("GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1677         pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1678         pr_info("Padding456 = 0x%x\n", pptable->Padding456);
1679
1680         pr_info("EnableTdpm = %d\n", pptable->EnableTdpm);
1681         pr_info("TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1682         pr_info("TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1683         pr_info("GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1684
1685         pr_info("FanStopTemp = %d\n", pptable->FanStopTemp);
1686         pr_info("FanStartTemp = %d\n", pptable->FanStartTemp);
1687
1688         pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);
1689         pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);
1690         pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1691         pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1692         pr_info("FanGainVrMem = %d\n", pptable->FanGainVrMem);
1693         pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);
1694
1695         pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);
1696         pr_info("FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1697         pr_info("FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1698         pr_info("FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1699         pr_info("FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1700         pr_info("FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1701         pr_info("FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1702         pr_info("FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1703         pr_info("FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1704
1705         pr_info("FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1706         pr_info("FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1707         pr_info("FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1708         pr_info("FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1709
1710         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1711         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1712         pr_info("Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1713         pr_info("Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1714
1715         pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1716                         pptable->dBtcGbGfxPll.a,
1717                         pptable->dBtcGbGfxPll.b,
1718                         pptable->dBtcGbGfxPll.c);
1719         pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1720                         pptable->dBtcGbGfxAfll.a,
1721                         pptable->dBtcGbGfxAfll.b,
1722                         pptable->dBtcGbGfxAfll.c);
1723         pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1724                         pptable->dBtcGbSoc.a,
1725                         pptable->dBtcGbSoc.b,
1726                         pptable->dBtcGbSoc.c);
1727
1728         pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1729                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1730                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1731         pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1732                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1733                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1734
1735         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1736                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1737                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1738                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1739         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1740                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1741                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1742                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1743
1744         pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1745         pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1746
1747         pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1748         pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1749         pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1750         pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1751
1752         pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1753         pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1754         pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1755         pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1756
1757         pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1758         pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1759
1760         pr_info("XgmiDpmPstates\n");
1761         for (i = 0; i < NUM_XGMI_LEVELS; i++)
1762                 pr_info("  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1763         pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1764         pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1765
1766         pr_info("VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1767         pr_info("VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1768         pr_info("VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1769         pr_info("VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1770         pr_info("VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1771         pr_info("VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1772         pr_info("VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1773         pr_info("VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1774
1775         pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1776         pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1777                         pptable->ReservedEquation0.a,
1778                         pptable->ReservedEquation0.b,
1779                         pptable->ReservedEquation0.c);
1780         pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1781                         pptable->ReservedEquation1.a,
1782                         pptable->ReservedEquation1.b,
1783                         pptable->ReservedEquation1.c);
1784         pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1785                         pptable->ReservedEquation2.a,
1786                         pptable->ReservedEquation2.b,
1787                         pptable->ReservedEquation2.c);
1788         pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1789                         pptable->ReservedEquation3.a,
1790                         pptable->ReservedEquation3.b,
1791                         pptable->ReservedEquation3.c);
1792
1793         pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1794         pr_info("PaddingUlv = %d\n", pptable->PaddingUlv);
1795
1796         pr_info("TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1797         pr_info("TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1798         pr_info("TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1799
1800         pr_info("PccThresholdLow = %d\n", pptable->PccThresholdLow);
1801         pr_info("PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1802
1803         pr_info("Board Parameters:\n");
1804         pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1805         pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1806
1807         pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1808         pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1809         pr_info("VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1810         pr_info("BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1811
1812         pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1813         pr_info("ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1814
1815         pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1816         pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
1817         pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1818
1819         pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1820         pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
1821         pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1822
1823         pr_info("MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1824         pr_info("MemOffset = 0x%x\n", pptable->MemOffset);
1825         pr_info("Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1826
1827         pr_info("BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1828         pr_info("BoardOffset = 0x%x\n", pptable->BoardOffset);
1829         pr_info("Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1830
1831         pr_info("VR0HotGpio = %d\n", pptable->VR0HotGpio);
1832         pr_info("VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1833         pr_info("VR1HotGpio = %d\n", pptable->VR1HotGpio);
1834         pr_info("VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1835
1836         pr_info("PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1837         pr_info("PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1838         pr_info("PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1839
1840         pr_info("UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1841         pr_info("UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1842         pr_info("UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1843
1844         pr_info("FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1845         pr_info("FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1846         pr_info("FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1847
1848         pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1849         pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1850         pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1851
1852         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1853                 pr_info("I2cControllers[%d]:\n", i);
1854                 pr_info("                   .Enabled = %d\n",
1855                                 pptable->I2cControllers[i].Enabled);
1856                 pr_info("                   .SlaveAddress = 0x%x\n",
1857                                 pptable->I2cControllers[i].SlaveAddress);
1858                 pr_info("                   .ControllerPort = %d\n",
1859                                 pptable->I2cControllers[i].ControllerPort);
1860                 pr_info("                   .ControllerName = %d\n",
1861                                 pptable->I2cControllers[i].ControllerName);
1862                 pr_info("                   .ThermalThrottler = %d\n",
1863                                 pptable->I2cControllers[i].ThermalThrotter);
1864                 pr_info("                   .I2cProtocol = %d\n",
1865                                 pptable->I2cControllers[i].I2cProtocol);
1866                 pr_info("                   .Speed = %d\n",
1867                                 pptable->I2cControllers[i].Speed);
1868         }
1869
1870         pr_info("MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1871         pr_info("DramBitWidth = %d\n", pptable->DramBitWidth);
1872
1873         pr_info("TotalBoardPower = %d\n", pptable->TotalBoardPower);
1874
1875         pr_info("XgmiLinkSpeed\n");
1876         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1877                 pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1878         pr_info("XgmiLinkWidth\n");
1879         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1880                 pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1881         pr_info("XgmiFclkFreq\n");
1882         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1883                 pr_info("  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1884         pr_info("XgmiSocVoltage\n");
1885         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1886                 pr_info("  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1887
1888 }
1889
1890 static bool arcturus_is_dpm_running(struct smu_context *smu)
1891 {
1892         int ret = 0;
1893         uint32_t feature_mask[2];
1894         unsigned long feature_enabled;
1895         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1896         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1897                            ((uint64_t)feature_mask[1] << 32));
1898         return !!(feature_enabled & SMC_DPM_FEATURE);
1899 }
1900
1901 static int arcturus_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
1902 {
1903         struct smu_power_context *smu_power = &smu->smu_power;
1904         struct smu_power_gate *power_gate = &smu_power->power_gate;
1905         int ret = 0;
1906
1907         if (enable) {
1908                 if (!smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1909                         ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
1910                         if (ret) {
1911                                 pr_err("[EnableVCNDPM] failed!\n");
1912                                 return ret;
1913                         }
1914                 }
1915                 power_gate->vcn_gated = false;
1916         } else {
1917                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1918                         ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
1919                         if (ret) {
1920                                 pr_err("[DisableVCNDPM] failed!\n");
1921                                 return ret;
1922                         }
1923                 }
1924                 power_gate->vcn_gated = true;
1925         }
1926
1927         return ret;
1928 }
1929
1930 static const struct pptable_funcs arcturus_ppt_funcs = {
1931         /* translate smu index into arcturus specific index */
1932         .get_smu_msg_index = arcturus_get_smu_msg_index,
1933         .get_smu_clk_index = arcturus_get_smu_clk_index,
1934         .get_smu_feature_index = arcturus_get_smu_feature_index,
1935         .get_smu_table_index = arcturus_get_smu_table_index,
1936         .get_smu_power_index= arcturus_get_pwr_src_index,
1937         .get_workload_type = arcturus_get_workload_type,
1938         /* internal structurs allocations */
1939         .tables_init = arcturus_tables_init,
1940         .alloc_dpm_context = arcturus_allocate_dpm_context,
1941         /* pptable related */
1942         .check_powerplay_table = arcturus_check_powerplay_table,
1943         .store_powerplay_table = arcturus_store_powerplay_table,
1944         .append_powerplay_table = arcturus_append_powerplay_table,
1945         /* init dpm */
1946         .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
1947         /* btc */
1948         .run_btc = arcturus_run_btc,
1949         /* dpm/clk tables */
1950         .set_default_dpm_table = arcturus_set_default_dpm_table,
1951         .populate_umd_state_clk = arcturus_populate_umd_state_clk,
1952         .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
1953         .get_current_clk_freq_by_table = arcturus_get_current_clk_freq_by_table,
1954         .print_clk_levels = arcturus_print_clk_levels,
1955         .force_clk_levels = arcturus_force_clk_levels,
1956         .read_sensor = arcturus_read_sensor,
1957         .get_fan_speed_percent = arcturus_get_fan_speed_percent,
1958         .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
1959         .force_dpm_limit_value = arcturus_force_dpm_limit_value,
1960         .unforce_dpm_levels = arcturus_unforce_dpm_levels,
1961         .get_profiling_clk_mask = arcturus_get_profiling_clk_mask,
1962         .get_power_profile_mode = arcturus_get_power_profile_mode,
1963         .set_power_profile_mode = arcturus_set_power_profile_mode,
1964         /* debug (internal used) */
1965         .dump_pptable = arcturus_dump_pptable,
1966         .get_power_limit = arcturus_get_power_limit,
1967         .is_dpm_running = arcturus_is_dpm_running,
1968         .dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
1969 };
1970
1971 void arcturus_set_ppt_funcs(struct smu_context *smu)
1972 {
1973         smu->ppt_funcs = &arcturus_ppt_funcs;
1974 }