drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_smu.h"
  27 #include "smu_internal.h"
  28 #include "atomfirmware.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "amdgpu_atombios.h"
  31 #include "smu_v11_0.h"
  32 #include "smu11_driver_if_arcturus.h"
  33 #include "soc15_common.h"
  34 #include "atom.h"
  35 #include "power_state.h"
  36 #include "arcturus_ppt.h"
  37 #include "smu_v11_0_pptable.h"
  38 #include "arcturus_ppsmc.h"
  39 #include "nbio/nbio_7_4_offset.h"
  40 #include "nbio/nbio_7_4_sh_mask.h"
  41 #include "thm/thm_11_0_2_offset.h"
  42 #include "thm/thm_11_0_2_sh_mask.h"
  43 #include "amdgpu_xgmi.h"
  44 #include <linux/i2c.h>
  45 #include <linux/pci.h>
  46 #include "amdgpu_ras.h"
  47 #include "smu_cmn.h"
  48
  49 /*
  50  * DO NOT use these for err/warn/info/debug messages.
  51  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  52  * They are more MGPU friendly.
  53  */
  54 #undef pr_err
  55 #undef pr_warn
  56 #undef pr_info
  57 #undef pr_debug
  58
  59 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  60
  61 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
  62         [smu_feature] = {1, (arcturus_feature)}
  63
  64 #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  65 #define SMU_FEATURES_LOW_SHIFT       0
  66 #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  67 #define SMU_FEATURES_HIGH_SHIFT      32
  68
  69 #define SMC_DPM_FEATURE ( \
  70         FEATURE_DPM_PREFETCHER_MASK | \
  71         FEATURE_DPM_GFXCLK_MASK | \
  72         FEATURE_DPM_UCLK_MASK | \
  73         FEATURE_DPM_SOCCLK_MASK | \
  74         FEATURE_DPM_MP0CLK_MASK | \
  75         FEATURE_DPM_FCLK_MASK | \
  76         FEATURE_DPM_XGMI_MASK)
  77
  78 /* possible frequency drift (1Mhz) */
  79 #define EPSILON                         1
  80
  81 static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
  82         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage,                     0),
  83         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion,                   1),
  84         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion,              1),
  85         MSG_MAP(SetAllowedFeaturesMaskLow,           PPSMC_MSG_SetAllowedFeaturesMaskLow,       0),
  86         MSG_MAP(SetAllowedFeaturesMaskHigh,          PPSMC_MSG_SetAllowedFeaturesMaskHigh,      0),
  87         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures,            0),
  88         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures,           0),
  89         MSG_MAP(EnableSmuFeaturesLow,                PPSMC_MSG_EnableSmuFeaturesLow,            1),
  90         MSG_MAP(EnableSmuFeaturesHigh,               PPSMC_MSG_EnableSmuFeaturesHigh,           1),
  91         MSG_MAP(DisableSmuFeaturesLow,               PPSMC_MSG_DisableSmuFeaturesLow,           0),
  92         MSG_MAP(DisableSmuFeaturesHigh,              PPSMC_MSG_DisableSmuFeaturesHigh,          0),
  93         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow,        0),
  94         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh,       0),
  95         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh,           1),
  96         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow,            1),
  97         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh,            0),
  98         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow,             0),
  99         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram,           1),
 100         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu,           0),
 101         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable,               0),
 102         MSG_MAP(UseBackupPPTable,                    PPSMC_MSG_UseBackupPPTable,                0),
 103         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh,    0),
 104         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow,     0),
 105         MSG_MAP(EnterBaco,                           PPSMC_MSG_EnterBaco,                       0),
 106         MSG_MAP(ExitBaco,                            PPSMC_MSG_ExitBaco,                        0),
 107         MSG_MAP(ArmD3,                               PPSMC_MSG_ArmD3,                           0),
 108         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq,                0),
 109         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq,                0),
 110         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq,                0),
 111         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq,                0),
 112         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq,                   0),
 113         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq,                   0),
 114         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex,               1),
 115         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask,                 1),
 116         MSG_MAP(SetDfSwitchType,                     PPSMC_MSG_SetDfSwitchType,                 0),
 117         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm,                 0),
 118         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive,        0),
 119         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,                     0),
 120         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,                     1),
 121         MSG_MAP(PowerUpVcn0,                         PPSMC_MSG_PowerUpVcn0,                     0),
 122         MSG_MAP(PowerDownVcn0,                       PPSMC_MSG_PowerDownVcn0,                   0),
 123         MSG_MAP(PowerUpVcn1,                         PPSMC_MSG_PowerUpVcn1,                     0),
 124         MSG_MAP(PowerDownVcn1,                       PPSMC_MSG_PowerDownVcn1,                   0),
 125         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload,             0),
 126         MSG_MAP(PrepareMp1ForReset,                  PPSMC_MSG_PrepareMp1ForReset,              0),
 127         MSG_MAP(PrepareMp1ForShutdown,               PPSMC_MSG_PrepareMp1ForShutdown,           0),
 128         MSG_MAP(SoftReset,                           PPSMC_MSG_SoftReset,                       0),
 129         MSG_MAP(RunAfllBtc,                          PPSMC_MSG_RunAfllBtc,                      0),
 130         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc,                        0),
 131         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh,          0),
 132         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow,           0),
 133         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize,              0),
 134         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData,                    0),
 135         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest,                        0),
 136         MSG_MAP(SetXgmiMode,                         PPSMC_MSG_SetXgmiMode,                     0),
 137         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable,          0),
 138         MSG_MAP(DFCstateControl,                     PPSMC_MSG_DFCstateControl,                 0),
 139         MSG_MAP(GmiPwrDnControl,                     PPSMC_MSG_GmiPwrDnControl,                 0),
 140         MSG_MAP(ReadSerialNumTop32,                  PPSMC_MSG_ReadSerialNumTop32,              1),
 141         MSG_MAP(ReadSerialNumBottom32,               PPSMC_MSG_ReadSerialNumBottom32,           1),
 142 };
 143
 144 static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
 145         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 146         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 147         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 148         CLK_MAP(FCLK, PPCLK_FCLK),
 149         CLK_MAP(UCLK, PPCLK_UCLK),
 150         CLK_MAP(MCLK, PPCLK_UCLK),
 151         CLK_MAP(DCLK, PPCLK_DCLK),
 152         CLK_MAP(VCLK, PPCLK_VCLK),
 153 };
 154
 155 static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
 156         FEA_MAP(DPM_PREFETCHER),
 157         FEA_MAP(DPM_GFXCLK),
 158         FEA_MAP(DPM_UCLK),
 159         FEA_MAP(DPM_SOCCLK),
 160         FEA_MAP(DPM_FCLK),
 161         FEA_MAP(DPM_MP0CLK),
 162         ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
 163         FEA_MAP(DS_GFXCLK),
 164         FEA_MAP(DS_SOCCLK),
 165         FEA_MAP(DS_LCLK),
 166         FEA_MAP(DS_FCLK),
 167         FEA_MAP(DS_UCLK),
 168         FEA_MAP(GFX_ULV),
 169         ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
 170         FEA_MAP(RSMU_SMN_CG),
 171         FEA_MAP(WAFL_CG),
 172         FEA_MAP(PPT),
 173         FEA_MAP(TDC),
 174         FEA_MAP(APCC_PLUS),
 175         FEA_MAP(VR0HOT),
 176         FEA_MAP(VR1HOT),
 177         FEA_MAP(FW_CTF),
 178         FEA_MAP(FAN_CONTROL),
 179         FEA_MAP(THERMAL),
 180         FEA_MAP(OUT_OF_BAND_MONITOR),
 181         FEA_MAP(TEMP_DEPENDENT_VMIN),
 182 };
 183
 184 static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
 185         TAB_MAP(PPTABLE),
 186         TAB_MAP(AVFS),
 187         TAB_MAP(AVFS_PSM_DEBUG),
 188         TAB_MAP(AVFS_FUSE_OVERRIDE),
 189         TAB_MAP(PMSTATUSLOG),
 190         TAB_MAP(SMU_METRICS),
 191         TAB_MAP(DRIVER_SMU_CONFIG),
 192         TAB_MAP(OVERDRIVE),
 193         TAB_MAP(I2C_COMMANDS),
 194         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 195 };
 196
 197 static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 198         PWR_MAP(AC),
 199         PWR_MAP(DC),
 200 };
 201
 202 static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 203         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 204         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 205         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 206         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 207         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 208 };
 209
 210 static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
 211 {
 212         struct smu_table_context *smu_table = &smu->smu_table;
 213
 214         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 215                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 216
 217         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 218                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 219
 220         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 221                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 222
 223         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 224                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 225
 226         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 227                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 228                        AMDGPU_GEM_DOMAIN_VRAM);
 229
 230         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 231         if (!smu_table->metrics_table)
 232                 return -ENOMEM;
 233         smu_table->metrics_time = 0;
 234
 235         return 0;
 236 }
 237
 238 static int arcturus_allocate_dpm_context(struct smu_context *smu)
 239 {
 240         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 241
 242         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 243                                        GFP_KERNEL);
 244         if (!smu_dpm->dpm_context)
 245                 return -ENOMEM;
 246         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 247
 248         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 249                                        GFP_KERNEL);
 250         if (!smu_dpm->dpm_current_power_state)
 251                 return -ENOMEM;
 252
 253         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 254                                        GFP_KERNEL);
 255         if (!smu_dpm->dpm_request_power_state)
 256                 return -ENOMEM;
 257
 258         return 0;
 259 }
 260
 261 static int
 262 arcturus_get_allowed_feature_mask(struct smu_context *smu,
 263                                   uint32_t *feature_mask, uint32_t num)
 264 {
 265         if (num > 2)
 266                 return -EINVAL;
 267
 268         /* pptable will handle the features to enable */
 269         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 270
 271         return 0;
 272 }
 273
 274 static int arcturus_set_default_dpm_table(struct smu_context *smu)
 275 {
 276         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 277         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 278         struct smu_11_0_dpm_table *dpm_table = NULL;
 279         int ret = 0;
 280
 281         /* socclk dpm table setup */
 282         dpm_table = &dpm_context->dpm_tables.soc_table;
 283         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 284                 ret = smu_v11_0_set_single_dpm_table(smu,
 285                                                      SMU_SOCCLK,
 286                                                      dpm_table);
 287                 if (ret)
 288                         return ret;
 289                 dpm_table->is_fine_grained =
 290                         !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 291         } else {
 292                 dpm_table->count = 1;
 293                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 294                 dpm_table->dpm_levels[0].enabled = true;
 295                 dpm_table->min = dpm_table->dpm_levels[0].value;
 296                 dpm_table->max = dpm_table->dpm_levels[0].value;
 297         }
 298
 299         /* gfxclk dpm table setup */
 300         dpm_table = &dpm_context->dpm_tables.gfx_table;
 301         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 302                 ret = smu_v11_0_set_single_dpm_table(smu,
 303                                                      SMU_GFXCLK,
 304                                                      dpm_table);
 305                 if (ret)
 306                         return ret;
 307                 dpm_table->is_fine_grained =
 308                         !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
 309         } else {
 310                 dpm_table->count = 1;
 311                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 312                 dpm_table->dpm_levels[0].enabled = true;
 313                 dpm_table->min = dpm_table->dpm_levels[0].value;
 314                 dpm_table->max = dpm_table->dpm_levels[0].value;
 315         }
 316
 317         /* memclk dpm table setup */
 318         dpm_table = &dpm_context->dpm_tables.uclk_table;
 319         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 320                 ret = smu_v11_0_set_single_dpm_table(smu,
 321                                                      SMU_UCLK,
 322                                                      dpm_table);
 323                 if (ret)
 324                         return ret;
 325                 dpm_table->is_fine_grained =
 326                         !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
 327         } else {
 328                 dpm_table->count = 1;
 329                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 330                 dpm_table->dpm_levels[0].enabled = true;
 331                 dpm_table->min = dpm_table->dpm_levels[0].value;
 332                 dpm_table->max = dpm_table->dpm_levels[0].value;
 333         }
 334
 335         /* fclk dpm table setup */
 336         dpm_table = &dpm_context->dpm_tables.fclk_table;
 337         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 338                 ret = smu_v11_0_set_single_dpm_table(smu,
 339                                                      SMU_FCLK,
 340                                                      dpm_table);
 341                 if (ret)
 342                         return ret;
 343                 dpm_table->is_fine_grained =
 344                         !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
 345         } else {
 346                 dpm_table->count = 1;
 347                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 348                 dpm_table->dpm_levels[0].enabled = true;
 349                 dpm_table->min = dpm_table->dpm_levels[0].value;
 350                 dpm_table->max = dpm_table->dpm_levels[0].value;
 351         }
 352
 353         return 0;
 354 }
 355
 356 static int arcturus_check_powerplay_table(struct smu_context *smu)
 357 {
 358         struct smu_table_context *table_context = &smu->smu_table;
 359         struct smu_11_0_powerplay_table *powerplay_table =
 360                 table_context->power_play_table;
 361         struct smu_baco_context *smu_baco = &smu->smu_baco;
 362
 363         mutex_lock(&smu_baco->mutex);
 364         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 365             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 366                 smu_baco->platform_support = true;
 367         mutex_unlock(&smu_baco->mutex);
 368
 369         table_context->thermal_controller_type =
 370                 powerplay_table->thermal_controller_type;
 371
 372         return 0;
 373 }
 374
 375 static int arcturus_store_powerplay_table(struct smu_context *smu)
 376 {
 377         struct smu_table_context *table_context = &smu->smu_table;
 378         struct smu_11_0_powerplay_table *powerplay_table =
 379                 table_context->power_play_table;
 380
 381         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 382                sizeof(PPTable_t));
 383
 384         return 0;
 385 }
 386
 387 static int arcturus_append_powerplay_table(struct smu_context *smu)
 388 {
 389         struct smu_table_context *table_context = &smu->smu_table;
 390         PPTable_t *smc_pptable = table_context->driver_pptable;
 391         struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
 392         int index, ret;
 393
 394         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 395                                            smc_dpm_info);
 396
 397         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 398                                       (uint8_t **)&smc_dpm_table);
 399         if (ret)
 400                 return ret;
 401
 402         dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 403                         smc_dpm_table->table_header.format_revision,
 404                         smc_dpm_table->table_header.content_revision);
 405
 406         if ((smc_dpm_table->table_header.format_revision == 4) &&
 407             (smc_dpm_table->table_header.content_revision == 6))
 408                 memcpy(&smc_pptable->MaxVoltageStepGfx,
 409                        &smc_dpm_table->maxvoltagestepgfx,
 410                        sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
 411
 412         return 0;
 413 }
 414
 415 static int arcturus_setup_pptable(struct smu_context *smu)
 416 {
 417         int ret = 0;
 418
 419         ret = smu_v11_0_setup_pptable(smu);
 420         if (ret)
 421                 return ret;
 422
 423         ret = arcturus_store_powerplay_table(smu);
 424         if (ret)
 425                 return ret;
 426
 427         ret = arcturus_append_powerplay_table(smu);
 428         if (ret)
 429                 return ret;
 430
 431         ret = arcturus_check_powerplay_table(smu);
 432         if (ret)
 433                 return ret;
 434
 435         return ret;
 436 }
 437
 438 static int arcturus_run_btc(struct smu_context *smu)
 439 {
 440         int ret = 0;
 441
 442         ret = smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
 443         if (ret) {
 444                 dev_err(smu->adev->dev, "RunAfllBtc failed!\n");
 445                 return ret;
 446         }
 447
 448         return smu_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 449 }
 450
 451 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 452 {
 453         struct smu_11_0_dpm_context *dpm_context =
 454                                 smu->smu_dpm.dpm_context;
 455         struct smu_11_0_dpm_table *gfx_table =
 456                                 &dpm_context->dpm_tables.gfx_table;
 457         struct smu_11_0_dpm_table *mem_table =
 458                                 &dpm_context->dpm_tables.uclk_table;
 459         struct smu_11_0_dpm_table *soc_table =
 460                                 &dpm_context->dpm_tables.soc_table;
 461         struct smu_umd_pstate_table *pstate_table =
 462                                 &smu->pstate_table;
 463
 464         pstate_table->gfxclk_pstate.min = gfx_table->min;
 465         pstate_table->gfxclk_pstate.peak = gfx_table->max;
 466
 467         pstate_table->uclk_pstate.min = mem_table->min;
 468         pstate_table->uclk_pstate.peak = mem_table->max;
 469
 470         pstate_table->socclk_pstate.min = soc_table->min;
 471         pstate_table->socclk_pstate.peak = soc_table->max;
 472
 473         if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
 474             mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
 475             soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
 476                 pstate_table->gfxclk_pstate.standard =
 477                         gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
 478                 pstate_table->uclk_pstate.standard =
 479                         mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
 480                 pstate_table->socclk_pstate.standard =
 481                         soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
 482         } else {
 483                 pstate_table->gfxclk_pstate.standard =
 484                         pstate_table->gfxclk_pstate.min;
 485                 pstate_table->uclk_pstate.standard =
 486                         pstate_table->uclk_pstate.min;
 487                 pstate_table->socclk_pstate.standard =
 488                         pstate_table->socclk_pstate.min;
 489         }
 490
 491         return 0;
 492 }
 493
 494 static int arcturus_get_clk_table(struct smu_context *smu,
 495                         struct pp_clock_levels_with_latency *clocks,
 496                         struct smu_11_0_dpm_table *dpm_table)
 497 {
 498         int i, count;
 499
 500         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 501         clocks->num_levels = count;
 502
 503         for (i = 0; i < count; i++) {
 504                 clocks->data[i].clocks_in_khz =
 505                         dpm_table->dpm_levels[i].value * 1000;
 506                 clocks->data[i].latency_in_us = 0;
 507         }
 508
 509         return 0;
 510 }
 511
 512 static int arcturus_freqs_in_same_level(int32_t frequency1,
 513                                         int32_t frequency2)
 514 {
 515         return (abs(frequency1 - frequency2) <= EPSILON);
 516 }
 517
 518 static int arcturus_get_smu_metrics_data(struct smu_context *smu,
 519                                          MetricsMember_t member,
 520                                          uint32_t *value)
 521 {
 522         struct smu_table_context *smu_table= &smu->smu_table;
 523         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 524         int ret = 0;
 525
 526         mutex_lock(&smu->metrics_lock);
 527
 528         if (!smu_table->metrics_time ||
 529              time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) {
 530                 ret = smu_update_table(smu,
 531                                        SMU_TABLE_SMU_METRICS,
 532                                        0,
 533                                        smu_table->metrics_table,
 534                                        false);
 535                 if (ret) {
 536                         dev_info(smu->adev->dev, "Failed to export SMU metrics table!\n");
 537                         mutex_unlock(&smu->metrics_lock);
 538                         return ret;
 539                 }
 540                 smu_table->metrics_time = jiffies;
 541         }
 542
 543         switch (member) {
 544         case METRICS_CURR_GFXCLK:
 545                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 546                 break;
 547         case METRICS_CURR_SOCCLK:
 548                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 549                 break;
 550         case METRICS_CURR_UCLK:
 551                 *value = metrics->CurrClock[PPCLK_UCLK];
 552                 break;
 553         case METRICS_CURR_VCLK:
 554                 *value = metrics->CurrClock[PPCLK_VCLK];
 555                 break;
 556         case METRICS_CURR_DCLK:
 557                 *value = metrics->CurrClock[PPCLK_DCLK];
 558                 break;
 559         case METRICS_CURR_FCLK:
 560                 *value = metrics->CurrClock[PPCLK_FCLK];
 561                 break;
 562         case METRICS_AVERAGE_GFXCLK:
 563                 *value = metrics->AverageGfxclkFrequency;
 564                 break;
 565         case METRICS_AVERAGE_SOCCLK:
 566                 *value = metrics->AverageSocclkFrequency;
 567                 break;
 568         case METRICS_AVERAGE_UCLK:
 569                 *value = metrics->AverageUclkFrequency;
 570                 break;
 571         case METRICS_AVERAGE_VCLK:
 572                 *value = metrics->AverageVclkFrequency;
 573                 break;
 574         case METRICS_AVERAGE_DCLK:
 575                 *value = metrics->AverageDclkFrequency;
 576                 break;
 577         case METRICS_AVERAGE_GFXACTIVITY:
 578                 *value = metrics->AverageGfxActivity;
 579                 break;
 580         case METRICS_AVERAGE_MEMACTIVITY:
 581                 *value = metrics->AverageUclkActivity;
 582                 break;
 583         case METRICS_AVERAGE_VCNACTIVITY:
 584                 *value = metrics->VcnActivityPercentage;
 585                 break;
 586         case METRICS_AVERAGE_SOCKETPOWER:
 587                 *value = metrics->AverageSocketPower << 8;
 588                 break;
 589         case METRICS_TEMPERATURE_EDGE:
 590                 *value = metrics->TemperatureEdge *
 591                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 592                 break;
 593         case METRICS_TEMPERATURE_HOTSPOT:
 594                 *value = metrics->TemperatureHotspot *
 595                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 596                 break;
 597         case METRICS_TEMPERATURE_MEM:
 598                 *value = metrics->TemperatureHBM *
 599                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 600                 break;
 601         case METRICS_TEMPERATURE_VRGFX:
 602                 *value = metrics->TemperatureVrGfx *
 603                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 604                 break;
 605         case METRICS_TEMPERATURE_VRSOC:
 606                 *value = metrics->TemperatureVrSoc *
 607                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 608                 break;
 609         case METRICS_TEMPERATURE_VRMEM:
 610                 *value = metrics->TemperatureVrMem *
 611                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 612                 break;
 613         case METRICS_THROTTLER_STATUS:
 614                 *value = metrics->ThrottlerStatus;
 615                 break;
 616         case METRICS_CURR_FANSPEED:
 617                 *value = metrics->CurrFanSpeed;
 618                 break;
 619         default:
 620                 *value = UINT_MAX;
 621                 break;
 622         }
 623
 624         mutex_unlock(&smu->metrics_lock);
 625
 626         return ret;
 627 }
 628
 629 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
 630                                        enum smu_clk_type clk_type,
 631                                        uint32_t *value)
 632 {
 633         MetricsMember_t member_type;
 634         int clk_id = 0;
 635
 636         if (!value)
 637                 return -EINVAL;
 638
 639         clk_id = smu_cmn_to_asic_specific_index(smu,
 640                                                 CMN2ASIC_MAPPING_CLK,
 641                                                 clk_type);
 642         if (clk_id < 0)
 643                 return -EINVAL;
 644
 645         switch (clk_id) {
 646         case PPCLK_GFXCLK:
 647                 /*
 648                  * CurrClock[clk_id] can provide accurate
 649                  *   output only when the dpm feature is enabled.
 650                  * We can use Average_* for dpm disabled case.
 651                  *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
 652                  */
 653                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
 654                         member_type = METRICS_CURR_GFXCLK;
 655                 else
 656                         member_type = METRICS_AVERAGE_GFXCLK;
 657                 break;
 658         case PPCLK_UCLK:
 659                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
 660                         member_type = METRICS_CURR_UCLK;
 661                 else
 662                         member_type = METRICS_AVERAGE_UCLK;
 663                 break;
 664         case PPCLK_SOCCLK:
 665                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
 666                         member_type = METRICS_CURR_SOCCLK;
 667                 else
 668                         member_type = METRICS_AVERAGE_SOCCLK;
 669                 break;
 670         case PPCLK_VCLK:
 671                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 672                         member_type = METRICS_CURR_VCLK;
 673                 else
 674                         member_type = METRICS_AVERAGE_VCLK;
 675                 break;
 676         case PPCLK_DCLK:
 677                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 678                         member_type = METRICS_CURR_DCLK;
 679                 else
 680                         member_type = METRICS_AVERAGE_DCLK;
 681                 break;
 682         case PPCLK_FCLK:
 683                 member_type = METRICS_CURR_FCLK;
 684                 break;
 685         default:
 686                 return -EINVAL;
 687         }
 688
 689         return arcturus_get_smu_metrics_data(smu,
 690                                              member_type,
 691                                              value);
 692 }
 693
 694 static int arcturus_print_clk_levels(struct smu_context *smu,
 695                         enum smu_clk_type type, char *buf)
 696 {
 697         int i, now, size = 0;
 698         int ret = 0;
 699         struct pp_clock_levels_with_latency clocks;
 700         struct smu_11_0_dpm_table *single_dpm_table;
 701         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 702         struct smu_11_0_dpm_context *dpm_context = NULL;
 703
 704         if (amdgpu_ras_intr_triggered())
 705                 return snprintf(buf, PAGE_SIZE, "unavailable\n");
 706
 707         dpm_context = smu_dpm->dpm_context;
 708
 709         switch (type) {
 710         case SMU_SCLK:
 711                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
 712                 if (ret) {
 713                         dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
 714                         return ret;
 715                 }
 716
 717                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 718                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 719                 if (ret) {
 720                         dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
 721                         return ret;
 722                 }
 723
 724                 /*
 725                  * For DPM disabled case, there will be only one clock level.
 726                  * And it's safe to assume that is always the current clock.
 727                  */
 728                 for (i = 0; i < clocks.num_levels; i++)
 729                         size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 730                                         clocks.data[i].clocks_in_khz / 1000,
 731                                         (clocks.num_levels == 1) ? "*" :
 732                                         (arcturus_freqs_in_same_level(
 733                                         clocks.data[i].clocks_in_khz / 1000,
 734                                         now) ? "*" : ""));
 735                 break;
 736
 737         case SMU_MCLK:
 738                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
 739                 if (ret) {
 740                         dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
 741                         return ret;
 742                 }
 743
 744                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 745                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 746                 if (ret) {
 747                         dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
 748                         return ret;
 749                 }
 750
 751                 for (i = 0; i < clocks.num_levels; i++)
 752                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 753                                 i, clocks.data[i].clocks_in_khz / 1000,
 754                                 (clocks.num_levels == 1) ? "*" :
 755                                 (arcturus_freqs_in_same_level(
 756                                 clocks.data[i].clocks_in_khz / 1000,
 757                                 now) ? "*" : ""));
 758                 break;
 759
 760         case SMU_SOCCLK:
 761                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
 762                 if (ret) {
 763                         dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
 764                         return ret;
 765                 }
 766
 767                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 768                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 769                 if (ret) {
 770                         dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
 771                         return ret;
 772                 }
 773
 774                 for (i = 0; i < clocks.num_levels; i++)
 775                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 776                                 i, clocks.data[i].clocks_in_khz / 1000,
 777                                 (clocks.num_levels == 1) ? "*" :
 778                                 (arcturus_freqs_in_same_level(
 779                                 clocks.data[i].clocks_in_khz / 1000,
 780                                 now) ? "*" : ""));
 781                 break;
 782
 783         case SMU_FCLK:
 784                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
 785                 if (ret) {
 786                         dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
 787                         return ret;
 788                 }
 789
 790                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 791                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 792                 if (ret) {
 793                         dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
 794                         return ret;
 795                 }
 796
 797                 for (i = 0; i < single_dpm_table->count; i++)
 798                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 799                                 i, single_dpm_table->dpm_levels[i].value,
 800                                 (clocks.num_levels == 1) ? "*" :
 801                                 (arcturus_freqs_in_same_level(
 802                                 clocks.data[i].clocks_in_khz / 1000,
 803                                 now) ? "*" : ""));
 804                 break;
 805
 806         default:
 807                 break;
 808         }
 809
 810         return size;
 811 }
 812
 813 static int arcturus_upload_dpm_level(struct smu_context *smu,
 814                                      bool max,
 815                                      uint32_t feature_mask,
 816                                      uint32_t level)
 817 {
 818         struct smu_11_0_dpm_context *dpm_context =
 819                         smu->smu_dpm.dpm_context;
 820         uint32_t freq;
 821         int ret = 0;
 822
 823         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 824             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 825                 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
 826                 ret = smu_send_smc_msg_with_param(smu,
 827                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 828                         (PPCLK_GFXCLK << 16) | (freq & 0xffff),
 829                         NULL);
 830                 if (ret) {
 831                         dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
 832                                                 max ? "max" : "min");
 833                         return ret;
 834                 }
 835         }
 836
 837         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 838             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 839                 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
 840                 ret = smu_send_smc_msg_with_param(smu,
 841                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 842                         (PPCLK_UCLK << 16) | (freq & 0xffff),
 843                         NULL);
 844                 if (ret) {
 845                         dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
 846                                                 max ? "max" : "min");
 847                         return ret;
 848                 }
 849         }
 850
 851         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 852             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
 853                 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
 854                 ret = smu_send_smc_msg_with_param(smu,
 855                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 856                         (PPCLK_SOCCLK << 16) | (freq & 0xffff),
 857                         NULL);
 858                 if (ret) {
 859                         dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
 860                                                 max ? "max" : "min");
 861                         return ret;
 862                 }
 863         }
 864
 865         return ret;
 866 }
 867
 868 static int arcturus_force_clk_levels(struct smu_context *smu,
 869                         enum smu_clk_type type, uint32_t mask)
 870 {
 871         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 872         struct smu_11_0_dpm_table *single_dpm_table = NULL;
 873         uint32_t soft_min_level, soft_max_level;
 874         uint32_t smu_version;
 875         int ret = 0;
 876
 877         ret = smu_get_smc_version(smu, NULL, &smu_version);
 878         if (ret) {
 879                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
 880                 return ret;
 881         }
 882
 883         if (smu_version >= 0x361200) {
 884                 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
 885                        "54.18 and onwards SMU firmwares\n");
 886                 return -EOPNOTSUPP;
 887         }
 888
 889         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 890         soft_max_level = mask ? (fls(mask) - 1) : 0;
 891
 892         switch (type) {
 893         case SMU_SCLK:
 894                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 895                 if (soft_max_level >= single_dpm_table->count) {
 896                         dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
 897                                         soft_max_level, single_dpm_table->count - 1);
 898                         ret = -EINVAL;
 899                         break;
 900                 }
 901
 902                 ret = arcturus_upload_dpm_level(smu,
 903                                                 false,
 904                                                 FEATURE_DPM_GFXCLK_MASK,
 905                                                 soft_min_level);
 906                 if (ret) {
 907                         dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
 908                         break;
 909                 }
 910
 911                 ret = arcturus_upload_dpm_level(smu,
 912                                                 true,
 913                                                 FEATURE_DPM_GFXCLK_MASK,
 914                                                 soft_max_level);
 915                 if (ret)
 916                         dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
 917
 918                 break;
 919
 920         case SMU_MCLK:
 921         case SMU_SOCCLK:
 922         case SMU_FCLK:
 923                 /*
 924                  * Should not arrive here since Arcturus does not
 925                  * support mclk/socclk/fclk softmin/softmax settings
 926                  */
 927                 ret = -EINVAL;
 928                 break;
 929
 930         default:
 931                 break;
 932         }
 933
 934         return ret;
 935 }
 936
 937 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
 938                                                 struct smu_temperature_range *range)
 939 {
 940         struct smu_table_context *table_context = &smu->smu_table;
 941         struct smu_11_0_powerplay_table *powerplay_table =
 942                                 table_context->power_play_table;
 943         PPTable_t *pptable = smu->smu_table.driver_pptable;
 944
 945         if (!range)
 946                 return -EINVAL;
 947
 948         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
 949
 950         range->max = pptable->TedgeLimit *
 951                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 952         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
 953                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 954         range->hotspot_crit_max = pptable->ThotspotLimit *
 955                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 956         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
 957                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 958         range->mem_crit_max = pptable->TmemLimit *
 959                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 960         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
 961                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 962         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
 963
 964         return 0;
 965 }
 966
 967 static int arcturus_get_current_activity_percent(struct smu_context *smu,
 968                                                  enum amd_pp_sensors sensor,
 969                                                  uint32_t *value)
 970 {
 971         int ret = 0;
 972
 973         if (!value)
 974                 return -EINVAL;
 975
 976         switch (sensor) {
 977         case AMDGPU_PP_SENSOR_GPU_LOAD:
 978                 ret = arcturus_get_smu_metrics_data(smu,
 979                                                     METRICS_AVERAGE_GFXACTIVITY,
 980                                                     value);
 981                 break;
 982         case AMDGPU_PP_SENSOR_MEM_LOAD:
 983                 ret = arcturus_get_smu_metrics_data(smu,
 984                                                     METRICS_AVERAGE_MEMACTIVITY,
 985                                                     value);
 986                 break;
 987         default:
 988                 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
 989                 return -EINVAL;
 990         }
 991
 992         return ret;
 993 }
 994
 995 static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
 996 {
 997         if (!value)
 998                 return -EINVAL;
 999
1000         return arcturus_get_smu_metrics_data(smu,
1001                                              METRICS_AVERAGE_SOCKETPOWER,
1002                                              value);
1003 }
1004
1005 static int arcturus_thermal_get_temperature(struct smu_context *smu,
1006                                             enum amd_pp_sensors sensor,
1007                                             uint32_t *value)
1008 {
1009         int ret = 0;
1010
1011         if (!value)
1012                 return -EINVAL;
1013
1014         switch (sensor) {
1015         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1016                 ret = arcturus_get_smu_metrics_data(smu,
1017                                                     METRICS_TEMPERATURE_HOTSPOT,
1018                                                     value);
1019                 break;
1020         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1021                 ret = arcturus_get_smu_metrics_data(smu,
1022                                                     METRICS_TEMPERATURE_EDGE,
1023                                                     value);
1024                 break;
1025         case AMDGPU_PP_SENSOR_MEM_TEMP:
1026                 ret = arcturus_get_smu_metrics_data(smu,
1027                                                     METRICS_TEMPERATURE_MEM,
1028                                                     value);
1029                 break;
1030         default:
1031                 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1032                 return -EINVAL;
1033         }
1034
1035         return ret;
1036 }
1037
1038 static int arcturus_read_sensor(struct smu_context *smu,
1039                                 enum amd_pp_sensors sensor,
1040                                 void *data, uint32_t *size)
1041 {
1042         struct smu_table_context *table_context = &smu->smu_table;
1043         PPTable_t *pptable = table_context->driver_pptable;
1044         int ret = 0;
1045
1046         if (amdgpu_ras_intr_triggered())
1047                 return 0;
1048
1049         if (!data || !size)
1050                 return -EINVAL;
1051
1052         mutex_lock(&smu->sensor_lock);
1053         switch (sensor) {
1054         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1055                 *(uint32_t *)data = pptable->FanMaximumRpm;
1056                 *size = 4;
1057                 break;
1058         case AMDGPU_PP_SENSOR_MEM_LOAD:
1059         case AMDGPU_PP_SENSOR_GPU_LOAD:
1060                 ret = arcturus_get_current_activity_percent(smu,
1061                                                             sensor,
1062                                                 (uint32_t *)data);
1063                 *size = 4;
1064                 break;
1065         case AMDGPU_PP_SENSOR_GPU_POWER:
1066                 ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
1067                 *size = 4;
1068                 break;
1069         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1070         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1071         case AMDGPU_PP_SENSOR_MEM_TEMP:
1072                 ret = arcturus_thermal_get_temperature(smu, sensor,
1073                                                 (uint32_t *)data);
1074                 *size = 4;
1075                 break;
1076         case AMDGPU_PP_SENSOR_GFX_MCLK:
1077                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1078                 /* the output clock frequency in 10K unit */
1079                 *(uint32_t *)data *= 100;
1080                 *size = 4;
1081                 break;
1082         case AMDGPU_PP_SENSOR_GFX_SCLK:
1083                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1084                 *(uint32_t *)data *= 100;
1085                 *size = 4;
1086                 break;
1087         case AMDGPU_PP_SENSOR_VDDGFX:
1088                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1089                 *size = 4;
1090                 break;
1091         default:
1092                 ret = -EOPNOTSUPP;
1093                 break;
1094         }
1095         mutex_unlock(&smu->sensor_lock);
1096
1097         return ret;
1098 }
1099
1100 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1101                                       uint32_t *speed)
1102 {
1103         if (!speed)
1104                 return -EINVAL;
1105
1106         return arcturus_get_smu_metrics_data(smu,
1107                                              METRICS_CURR_FANSPEED,
1108                                              speed);
1109 }
1110
1111 static int arcturus_get_fan_speed_percent(struct smu_context *smu,
1112                                           uint32_t *speed)
1113 {
1114         PPTable_t *pptable = smu->smu_table.driver_pptable;
1115         uint32_t percent, current_rpm;
1116         int ret = 0;
1117
1118         if (!speed)
1119                 return -EINVAL;
1120
1121         ret = arcturus_get_fan_speed_rpm(smu, &current_rpm);
1122         if (ret)
1123                 return ret;
1124
1125         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1126         *speed = percent > 100 ? 100 : percent;
1127
1128         return ret;
1129 }
1130
1131 static int arcturus_get_power_limit(struct smu_context *smu)
1132 {
1133         struct smu_11_0_powerplay_table *powerplay_table =
1134                 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1135         PPTable_t *pptable = smu->smu_table.driver_pptable;
1136         uint32_t power_limit, od_percent;
1137
1138         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1139                 /* the last hope to figure out the ppt limit */
1140                 if (!pptable) {
1141                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1142                         return -EINVAL;
1143                 }
1144                 power_limit =
1145                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1146         }
1147         smu->current_power_limit = power_limit;
1148
1149         if (smu->od_enabled) {
1150                 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1151
1152                 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1153
1154                 power_limit *= (100 + od_percent);
1155                 power_limit /= 100;
1156         }
1157         smu->max_power_limit = power_limit;
1158
1159         return 0;
1160 }
1161
1162 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1163                                            char *buf)
1164 {
1165         DpmActivityMonitorCoeffInt_t activity_monitor;
1166         static const char *profile_name[] = {
1167                                         "BOOTUP_DEFAULT",
1168                                         "3D_FULL_SCREEN",
1169                                         "POWER_SAVING",
1170                                         "VIDEO",
1171                                         "VR",
1172                                         "COMPUTE",
1173                                         "CUSTOM"};
1174         static const char *title[] = {
1175                         "PROFILE_INDEX(NAME)",
1176                         "CLOCK_TYPE(NAME)",
1177                         "FPS",
1178                         "UseRlcBusy",
1179                         "MinActiveFreqType",
1180                         "MinActiveFreq",
1181                         "BoosterFreqType",
1182                         "BoosterFreq",
1183                         "PD_Data_limit_c",
1184                         "PD_Data_error_coeff",
1185                         "PD_Data_error_rate_coeff"};
1186         uint32_t i, size = 0;
1187         int16_t workload_type = 0;
1188         int result = 0;
1189         uint32_t smu_version;
1190
1191         if (!buf)
1192                 return -EINVAL;
1193
1194         result = smu_get_smc_version(smu, NULL, &smu_version);
1195         if (result)
1196                 return result;
1197
1198         if (smu_version >= 0x360d00)
1199                 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1200                         title[0], title[1], title[2], title[3], title[4], title[5],
1201                         title[6], title[7], title[8], title[9], title[10]);
1202         else
1203                 size += sprintf(buf + size, "%16s\n",
1204                         title[0]);
1205
1206         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1207                 /*
1208                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1209                  * Not all profile modes are supported on arcturus.
1210                  */
1211                 workload_type = smu_cmn_to_asic_specific_index(smu,
1212                                                                CMN2ASIC_MAPPING_WORKLOAD,
1213                                                                i);
1214                 if (workload_type < 0)
1215                         continue;
1216
1217                 if (smu_version >= 0x360d00) {
1218                         result = smu_update_table(smu,
1219                                                   SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1220                                                   workload_type,
1221                                                   (void *)(&activity_monitor),
1222                                                   false);
1223                         if (result) {
1224                                 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1225                                 return result;
1226                         }
1227                 }
1228
1229                 size += sprintf(buf + size, "%2d %14s%s\n",
1230                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1231
1232                 if (smu_version >= 0x360d00) {
1233                         size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1234                                 " ",
1235                                 0,
1236                                 "GFXCLK",
1237                                 activity_monitor.Gfx_FPS,
1238                                 activity_monitor.Gfx_UseRlcBusy,
1239                                 activity_monitor.Gfx_MinActiveFreqType,
1240                                 activity_monitor.Gfx_MinActiveFreq,
1241                                 activity_monitor.Gfx_BoosterFreqType,
1242                                 activity_monitor.Gfx_BoosterFreq,
1243                                 activity_monitor.Gfx_PD_Data_limit_c,
1244                                 activity_monitor.Gfx_PD_Data_error_coeff,
1245                                 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1246
1247                         size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1248                                 " ",
1249                                 1,
1250                                 "UCLK",
1251                                 activity_monitor.Mem_FPS,
1252                                 activity_monitor.Mem_UseRlcBusy,
1253                                 activity_monitor.Mem_MinActiveFreqType,
1254                                 activity_monitor.Mem_MinActiveFreq,
1255                                 activity_monitor.Mem_BoosterFreqType,
1256                                 activity_monitor.Mem_BoosterFreq,
1257                                 activity_monitor.Mem_PD_Data_limit_c,
1258                                 activity_monitor.Mem_PD_Data_error_coeff,
1259                                 activity_monitor.Mem_PD_Data_error_rate_coeff);
1260                 }
1261         }
1262
1263         return size;
1264 }
1265
1266 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1267                                            long *input,
1268                                            uint32_t size)
1269 {
1270         DpmActivityMonitorCoeffInt_t activity_monitor;
1271         int workload_type = 0;
1272         uint32_t profile_mode = input[size];
1273         int ret = 0;
1274         uint32_t smu_version;
1275
1276         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1277                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1278                 return -EINVAL;
1279         }
1280
1281         ret = smu_get_smc_version(smu, NULL, &smu_version);
1282         if (ret)
1283                 return ret;
1284
1285         if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1286              (smu_version >=0x360d00)) {
1287                 ret = smu_update_table(smu,
1288                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1289                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1290                                        (void *)(&activity_monitor),
1291                                        false);
1292                 if (ret) {
1293                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1294                         return ret;
1295                 }
1296
1297                 switch (input[0]) {
1298                 case 0: /* Gfxclk */
1299                         activity_monitor.Gfx_FPS = input[1];
1300                         activity_monitor.Gfx_UseRlcBusy = input[2];
1301                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1302                         activity_monitor.Gfx_MinActiveFreq = input[4];
1303                         activity_monitor.Gfx_BoosterFreqType = input[5];
1304                         activity_monitor.Gfx_BoosterFreq = input[6];
1305                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1306                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1307                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1308                         break;
1309                 case 1: /* Uclk */
1310                         activity_monitor.Mem_FPS = input[1];
1311                         activity_monitor.Mem_UseRlcBusy = input[2];
1312                         activity_monitor.Mem_MinActiveFreqType = input[3];
1313                         activity_monitor.Mem_MinActiveFreq = input[4];
1314                         activity_monitor.Mem_BoosterFreqType = input[5];
1315                         activity_monitor.Mem_BoosterFreq = input[6];
1316                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1317                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1318                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1319                         break;
1320                 }
1321
1322                 ret = smu_update_table(smu,
1323                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1324                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1325                                        (void *)(&activity_monitor),
1326                                        true);
1327                 if (ret) {
1328                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1329                         return ret;
1330                 }
1331         }
1332
1333         /*
1334          * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1335          * Not all profile modes are supported on arcturus.
1336          */
1337         workload_type = smu_cmn_to_asic_specific_index(smu,
1338                                                        CMN2ASIC_MAPPING_WORKLOAD,
1339                                                        profile_mode);
1340         if (workload_type < 0) {
1341                 dev_err(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode);
1342                 return -EINVAL;
1343         }
1344
1345         ret = smu_send_smc_msg_with_param(smu,
1346                                           SMU_MSG_SetWorkloadMask,
1347                                           1 << workload_type,
1348                                           NULL);
1349         if (ret) {
1350                 dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
1351                 return ret;
1352         }
1353
1354         smu->power_profile_mode = profile_mode;
1355
1356         return 0;
1357 }
1358
1359 static int arcturus_set_performance_level(struct smu_context *smu,
1360                                           enum amd_dpm_forced_level level)
1361 {
1362         uint32_t smu_version;
1363         int ret;
1364
1365         ret = smu_get_smc_version(smu, NULL, &smu_version);
1366         if (ret) {
1367                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
1368                 return ret;
1369         }
1370
1371         switch (level) {
1372         case AMD_DPM_FORCED_LEVEL_HIGH:
1373         case AMD_DPM_FORCED_LEVEL_LOW:
1374         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1375         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1376         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1377         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1378                 if (smu_version >= 0x361200) {
1379                         dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1380                                "54.18 and onwards SMU firmwares\n");
1381                         return -EOPNOTSUPP;
1382                 }
1383                 break;
1384         default:
1385                 break;
1386         }
1387
1388         return smu_v11_0_set_performance_level(smu, level);
1389 }
1390
1391 static void arcturus_dump_pptable(struct smu_context *smu)
1392 {
1393         struct smu_table_context *table_context = &smu->smu_table;
1394         PPTable_t *pptable = table_context->driver_pptable;
1395         int i;
1396
1397         dev_info(smu->adev->dev, "Dumped PPTable:\n");
1398
1399         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1400
1401         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1402         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1403
1404         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1405                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1406                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1407         }
1408
1409         dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1410         dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1411         dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1412         dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1413
1414         dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit);
1415         dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit);
1416         dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit);
1417         dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1418         dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1419         dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1420         dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit);
1421
1422         dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1423         dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1424
1425         dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1426
1427         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1428         dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding);
1429
1430         dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1431         dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1432         dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1433         dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1434
1435         dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1436         dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1437         dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1438         dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1439
1440         dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1441         dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1442
1443         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1444                         "  .VoltageMode          = 0x%02x\n"
1445                         "  .SnapToDiscrete       = 0x%02x\n"
1446                         "  .NumDiscreteLevels    = 0x%02x\n"
1447                         "  .padding              = 0x%02x\n"
1448                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1449                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1450                         "  .SsFmin               = 0x%04x\n"
1451                         "  .Padding_16           = 0x%04x\n",
1452                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1453                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1454                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1455                         pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1456                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1457                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1458                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1459                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1460                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1461                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1462                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1463
1464         dev_info(smu->adev->dev, "[PPCLK_VCLK]\n"
1465                         "  .VoltageMode          = 0x%02x\n"
1466                         "  .SnapToDiscrete       = 0x%02x\n"
1467                         "  .NumDiscreteLevels    = 0x%02x\n"
1468                         "  .padding              = 0x%02x\n"
1469                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1470                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1471                         "  .SsFmin               = 0x%04x\n"
1472                         "  .Padding_16           = 0x%04x\n",
1473                         pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1474                         pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1475                         pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1476                         pptable->DpmDescriptor[PPCLK_VCLK].padding,
1477                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1478                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1479                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1480                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1481                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1482                         pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1483                         pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1484
1485         dev_info(smu->adev->dev, "[PPCLK_DCLK]\n"
1486                         "  .VoltageMode          = 0x%02x\n"
1487                         "  .SnapToDiscrete       = 0x%02x\n"
1488                         "  .NumDiscreteLevels    = 0x%02x\n"
1489                         "  .padding              = 0x%02x\n"
1490                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1491                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1492                         "  .SsFmin               = 0x%04x\n"
1493                         "  .Padding_16           = 0x%04x\n",
1494                         pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1495                         pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1496                         pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1497                         pptable->DpmDescriptor[PPCLK_DCLK].padding,
1498                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1499                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1500                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1501                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1502                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1503                         pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1504                         pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1505
1506         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1507                         "  .VoltageMode          = 0x%02x\n"
1508                         "  .SnapToDiscrete       = 0x%02x\n"
1509                         "  .NumDiscreteLevels    = 0x%02x\n"
1510                         "  .padding              = 0x%02x\n"
1511                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1512                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1513                         "  .SsFmin               = 0x%04x\n"
1514                         "  .Padding_16           = 0x%04x\n",
1515                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1516                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1517                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1518                         pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1519                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1520                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1521                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1522                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1523                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1524                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1525                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1526
1527         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1528                         "  .VoltageMode          = 0x%02x\n"
1529                         "  .SnapToDiscrete       = 0x%02x\n"
1530                         "  .NumDiscreteLevels    = 0x%02x\n"
1531                         "  .padding              = 0x%02x\n"
1532                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1533                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1534                         "  .SsFmin               = 0x%04x\n"
1535                         "  .Padding_16           = 0x%04x\n",
1536                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1537                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1538                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1539                         pptable->DpmDescriptor[PPCLK_UCLK].padding,
1540                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1541                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1542                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1543                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1544                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1545                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1546                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1547
1548         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1549                         "  .VoltageMode          = 0x%02x\n"
1550                         "  .SnapToDiscrete       = 0x%02x\n"
1551                         "  .NumDiscreteLevels    = 0x%02x\n"
1552                         "  .padding              = 0x%02x\n"
1553                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1554                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1555                         "  .SsFmin               = 0x%04x\n"
1556                         "  .Padding_16           = 0x%04x\n",
1557                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1558                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1559                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1560                         pptable->DpmDescriptor[PPCLK_FCLK].padding,
1561                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1562                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1563                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1564                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1565                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1566                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1567                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1568
1569
1570         dev_info(smu->adev->dev, "FreqTableGfx\n");
1571         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1572                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1573
1574         dev_info(smu->adev->dev, "FreqTableVclk\n");
1575         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1576                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1577
1578         dev_info(smu->adev->dev, "FreqTableDclk\n");
1579         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1580                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1581
1582         dev_info(smu->adev->dev, "FreqTableSocclk\n");
1583         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1584                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1585
1586         dev_info(smu->adev->dev, "FreqTableUclk\n");
1587         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1588                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1589
1590         dev_info(smu->adev->dev, "FreqTableFclk\n");
1591         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1592                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1593
1594         dev_info(smu->adev->dev, "Mp0clkFreq\n");
1595         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1596                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1597
1598         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
1599         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1600                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1601
1602         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1603         dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1604         dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1605         dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1606         dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1607         dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1608         dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1609         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1610         dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456);
1611
1612         dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm);
1613         dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1614         dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1615         dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1616
1617         dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp);
1618         dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp);
1619
1620         dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge);
1621         dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot);
1622         dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1623         dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1624         dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem);
1625         dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm);
1626
1627         dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin);
1628         dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1629         dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1630         dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1631         dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1632         dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1633         dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1634         dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1635         dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1636
1637         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1638         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1639         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1640         dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1641
1642         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1643         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1644         dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1645         dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1646
1647         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1648                         pptable->dBtcGbGfxPll.a,
1649                         pptable->dBtcGbGfxPll.b,
1650                         pptable->dBtcGbGfxPll.c);
1651         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1652                         pptable->dBtcGbGfxAfll.a,
1653                         pptable->dBtcGbGfxAfll.b,
1654                         pptable->dBtcGbGfxAfll.c);
1655         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1656                         pptable->dBtcGbSoc.a,
1657                         pptable->dBtcGbSoc.b,
1658                         pptable->dBtcGbSoc.c);
1659
1660         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1661                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1662                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1663         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1664                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1665                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1666
1667         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1668                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1669                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1670                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1671         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1672                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1673                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1674                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1675
1676         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1677         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1678
1679         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1680         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1681         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1682         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1683
1684         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1685         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1686         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1687         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1688
1689         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1690         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1691
1692         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
1693         for (i = 0; i < NUM_XGMI_LEVELS; i++)
1694                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1695         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1696         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1697
1698         dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1699         dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1700         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1701         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1702         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1703         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1704         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1705         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1706
1707         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1708         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1709                         pptable->ReservedEquation0.a,
1710                         pptable->ReservedEquation0.b,
1711                         pptable->ReservedEquation0.c);
1712         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1713                         pptable->ReservedEquation1.a,
1714                         pptable->ReservedEquation1.b,
1715                         pptable->ReservedEquation1.c);
1716         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1717                         pptable->ReservedEquation2.a,
1718                         pptable->ReservedEquation2.b,
1719                         pptable->ReservedEquation2.c);
1720         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1721                         pptable->ReservedEquation3.a,
1722                         pptable->ReservedEquation3.b,
1723                         pptable->ReservedEquation3.c);
1724
1725         dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1726         dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv);
1727
1728         dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1729         dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1730         dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1731
1732         dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow);
1733         dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1734
1735         dev_info(smu->adev->dev, "Board Parameters:\n");
1736         dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1737         dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1738
1739         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1740         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1741         dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1742         dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1743
1744         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1745         dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1746
1747         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1748         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
1749         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1750
1751         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1752         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
1753         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1754
1755         dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1756         dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset);
1757         dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1758
1759         dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1760         dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset);
1761         dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1762
1763         dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio);
1764         dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1765         dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio);
1766         dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1767
1768         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1769         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1770         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1771
1772         dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1773         dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1774         dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1775
1776         dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1777         dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1778         dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1779
1780         dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1781         dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1782         dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1783
1784         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1785                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
1786                 dev_info(smu->adev->dev, "                   .Enabled = %d\n",
1787                                 pptable->I2cControllers[i].Enabled);
1788                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
1789                                 pptable->I2cControllers[i].SlaveAddress);
1790                 dev_info(smu->adev->dev, "                   .ControllerPort = %d\n",
1791                                 pptable->I2cControllers[i].ControllerPort);
1792                 dev_info(smu->adev->dev, "                   .ControllerName = %d\n",
1793                                 pptable->I2cControllers[i].ControllerName);
1794                 dev_info(smu->adev->dev, "                   .ThermalThrottler = %d\n",
1795                                 pptable->I2cControllers[i].ThermalThrotter);
1796                 dev_info(smu->adev->dev, "                   .I2cProtocol = %d\n",
1797                                 pptable->I2cControllers[i].I2cProtocol);
1798                 dev_info(smu->adev->dev, "                   .Speed = %d\n",
1799                                 pptable->I2cControllers[i].Speed);
1800         }
1801
1802         dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1803         dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth);
1804
1805         dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower);
1806
1807         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
1808         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1809                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1810         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
1811         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1812                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1813         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
1814         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1815                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1816         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
1817         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1818                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1819
1820 }
1821
1822 static bool arcturus_is_dpm_running(struct smu_context *smu)
1823 {
1824         int ret = 0;
1825         uint32_t feature_mask[2];
1826         unsigned long feature_enabled;
1827         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1828         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1829                            ((uint64_t)feature_mask[1] << 32));
1830         return !!(feature_enabled & SMC_DPM_FEATURE);
1831 }
1832
1833 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1834 {
1835         struct smu_power_context *smu_power = &smu->smu_power;
1836         struct smu_power_gate *power_gate = &smu_power->power_gate;
1837         int ret = 0;
1838
1839         if (enable) {
1840                 if (!smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1841                         ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
1842                         if (ret) {
1843                                 dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
1844                                 return ret;
1845                         }
1846                 }
1847                 power_gate->vcn_gated = false;
1848         } else {
1849                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1850                         ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
1851                         if (ret) {
1852                                 dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
1853                                 return ret;
1854                         }
1855                 }
1856                 power_gate->vcn_gated = true;
1857         }
1858
1859         return ret;
1860 }
1861
1862 static void arcturus_fill_eeprom_i2c_req(SwI2cRequest_t  *req, bool write,
1863                                   uint8_t address, uint32_t numbytes,
1864                                   uint8_t *data)
1865 {
1866         int i;
1867
1868         req->I2CcontrollerPort = 0;
1869         req->I2CSpeed = 2;
1870         req->SlaveAddress = address;
1871         req->NumCmds = numbytes;
1872
1873         for (i = 0; i < numbytes; i++) {
1874                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
1875
1876                 /* First 2 bytes are always write for lower 2b EEPROM address */
1877                 if (i < 2)
1878                         cmd->Cmd = 1;
1879                 else
1880                         cmd->Cmd = write;
1881
1882
1883                 /* Add RESTART for read  after address filled */
1884                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
1885
1886                 /* Add STOP in the end */
1887                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
1888
1889                 /* Fill with data regardless if read or write to simplify code */
1890                 cmd->RegisterAddr = data[i];
1891         }
1892 }
1893
1894 static int arcturus_i2c_eeprom_read_data(struct i2c_adapter *control,
1895                                                uint8_t address,
1896                                                uint8_t *data,
1897                                                uint32_t numbytes)
1898 {
1899         uint32_t  i, ret = 0;
1900         SwI2cRequest_t req;
1901         struct amdgpu_device *adev = to_amdgpu_device(control);
1902         struct smu_table_context *smu_table = &adev->smu.smu_table;
1903         struct smu_table *table = &smu_table->driver_table;
1904
1905         if (numbytes > MAX_SW_I2C_COMMANDS) {
1906                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1907                         numbytes, MAX_SW_I2C_COMMANDS);
1908                 return -EINVAL;
1909         }
1910
1911         memset(&req, 0, sizeof(req));
1912         arcturus_fill_eeprom_i2c_req(&req, false, address, numbytes, data);
1913
1914         mutex_lock(&adev->smu.mutex);
1915         /* Now read data starting with that address */
1916         ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
1917                                         true);
1918         mutex_unlock(&adev->smu.mutex);
1919
1920         if (!ret) {
1921                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
1922
1923                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
1924                 for (i = 0; i < numbytes; i++)
1925                         data[i] = res->SwI2cCmds[i].Data;
1926
1927                 dev_dbg(adev->dev, "arcturus_i2c_eeprom_read_data, address = %x, bytes = %d, data :",
1928                                   (uint16_t)address, numbytes);
1929
1930                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1931                                8, 1, data, numbytes, false);
1932         } else
1933                 dev_err(adev->dev, "arcturus_i2c_eeprom_read_data - error occurred :%x", ret);
1934
1935         return ret;
1936 }
1937
1938 static int arcturus_i2c_eeprom_write_data(struct i2c_adapter *control,
1939                                                 uint8_t address,
1940                                                 uint8_t *data,
1941                                                 uint32_t numbytes)
1942 {
1943         uint32_t ret;
1944         SwI2cRequest_t req;
1945         struct amdgpu_device *adev = to_amdgpu_device(control);
1946
1947         if (numbytes > MAX_SW_I2C_COMMANDS) {
1948                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1949                         numbytes, MAX_SW_I2C_COMMANDS);
1950                 return -EINVAL;
1951         }
1952
1953         memset(&req, 0, sizeof(req));
1954         arcturus_fill_eeprom_i2c_req(&req, true, address, numbytes, data);
1955
1956         mutex_lock(&adev->smu.mutex);
1957         ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
1958         mutex_unlock(&adev->smu.mutex);
1959
1960         if (!ret) {
1961                 dev_dbg(adev->dev, "arcturus_i2c_write(), address = %x, bytes = %d , data: ",
1962                                          (uint16_t)address, numbytes);
1963
1964                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1965                                8, 1, data, numbytes, false);
1966                 /*
1967                  * According to EEPROM spec there is a MAX of 10 ms required for
1968                  * EEPROM to flush internal RX buffer after STOP was issued at the
1969                  * end of write transaction. During this time the EEPROM will not be
1970                  * responsive to any more commands - so wait a bit more.
1971                  */
1972                 msleep(10);
1973
1974         } else
1975                 dev_err(adev->dev, "arcturus_i2c_write- error occurred :%x", ret);
1976
1977         return ret;
1978 }
1979
1980 static int arcturus_i2c_eeprom_i2c_xfer(struct i2c_adapter *i2c_adap,
1981                               struct i2c_msg *msgs, int num)
1982 {
1983         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
1984         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
1985
1986         for (i = 0; i < num; i++) {
1987                 /*
1988                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
1989                  * once and hence the data needs to be spliced into chunks and sent each
1990                  * chunk separately
1991                  */
1992                 data_size = msgs[i].len - 2;
1993                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
1994                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
1995                 data_ptr = msgs[i].buf + 2;
1996
1997                 for (j = 0; j < data_size / data_chunk_size; j++) {
1998                         /* Insert the EEPROM dest addess, bits 0-15 */
1999                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2000                         data_chunk[1] = (next_eeprom_addr & 0xff);
2001
2002                         if (msgs[i].flags & I2C_M_RD) {
2003                                 ret = arcturus_i2c_eeprom_read_data(i2c_adap,
2004                                                                 (uint8_t)msgs[i].addr,
2005                                                                 data_chunk, MAX_SW_I2C_COMMANDS);
2006
2007                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2008                         } else {
2009
2010                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2011
2012                                 ret = arcturus_i2c_eeprom_write_data(i2c_adap,
2013                                                                  (uint8_t)msgs[i].addr,
2014                                                                  data_chunk, MAX_SW_I2C_COMMANDS);
2015                         }
2016
2017                         if (ret) {
2018                                 num = -EIO;
2019                                 goto fail;
2020                         }
2021
2022                         next_eeprom_addr += data_chunk_size;
2023                         data_ptr += data_chunk_size;
2024                 }
2025
2026                 if (data_size % data_chunk_size) {
2027                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2028                         data_chunk[1] = (next_eeprom_addr & 0xff);
2029
2030                         if (msgs[i].flags & I2C_M_RD) {
2031                                 ret = arcturus_i2c_eeprom_read_data(i2c_adap,
2032                                                                 (uint8_t)msgs[i].addr,
2033                                                                 data_chunk, (data_size % data_chunk_size) + 2);
2034
2035                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2036                         } else {
2037                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2038
2039                                 ret = arcturus_i2c_eeprom_write_data(i2c_adap,
2040                                                                  (uint8_t)msgs[i].addr,
2041                                                                  data_chunk, (data_size % data_chunk_size) + 2);
2042                         }
2043
2044                         if (ret) {
2045                                 num = -EIO;
2046                                 goto fail;
2047                         }
2048                 }
2049         }
2050
2051 fail:
2052         return num;
2053 }
2054
2055 static u32 arcturus_i2c_eeprom_i2c_func(struct i2c_adapter *adap)
2056 {
2057         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2058 }
2059
2060
2061 static const struct i2c_algorithm arcturus_i2c_eeprom_i2c_algo = {
2062         .master_xfer = arcturus_i2c_eeprom_i2c_xfer,
2063         .functionality = arcturus_i2c_eeprom_i2c_func,
2064 };
2065
2066 static bool arcturus_i2c_adapter_is_added(struct i2c_adapter *control)
2067 {
2068         struct amdgpu_device *adev = to_amdgpu_device(control);
2069
2070         return control->dev.parent == &adev->pdev->dev;
2071 }
2072
2073 static int arcturus_i2c_eeprom_control_init(struct smu_context *smu, struct i2c_adapter *control)
2074 {
2075         struct amdgpu_device *adev = to_amdgpu_device(control);
2076         int res;
2077
2078         /* smu_i2c_eeprom_init may be called twice in sriov */
2079         if (arcturus_i2c_adapter_is_added(control))
2080                 return 0;
2081
2082         control->owner = THIS_MODULE;
2083         control->class = I2C_CLASS_SPD;
2084         control->dev.parent = &adev->pdev->dev;
2085         control->algo = &arcturus_i2c_eeprom_i2c_algo;
2086         snprintf(control->name, sizeof(control->name), "AMDGPU EEPROM");
2087
2088         res = i2c_add_adapter(control);
2089         if (res)
2090                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2091
2092         return res;
2093 }
2094
2095 static void arcturus_i2c_eeprom_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2096 {
2097         if (!arcturus_i2c_adapter_is_added(control))
2098                 return;
2099
2100         i2c_del_adapter(control);
2101 }
2102
2103 static void arcturus_get_unique_id(struct smu_context *smu)
2104 {
2105         struct amdgpu_device *adev = smu->adev;
2106         uint32_t top32 = 0, bottom32 = 0, smu_version;
2107         uint64_t id;
2108
2109         if (smu_get_smc_version(smu, NULL, &smu_version)) {
2110                 dev_warn(adev->dev, "Failed to get smu version, cannot get unique_id or serial_number\n");
2111                 return;
2112         }
2113
2114         /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
2115         if (smu_version < 0x361700) {
2116                 dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n");
2117                 return;
2118         }
2119
2120         /* Get the SN to turn into a Unique ID */
2121         smu_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2122         smu_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
2123
2124         id = ((uint64_t)bottom32 << 32) | top32;
2125         adev->unique_id = id;
2126         /* For Arcturus-and-later, unique_id == serial_number, so convert it to a
2127          * 16-digit HEX string for convenience and backwards-compatibility
2128          */
2129         sprintf(adev->serial, "%llx", id);
2130 }
2131
2132 static bool arcturus_is_baco_supported(struct smu_context *smu)
2133 {
2134         struct amdgpu_device *adev = smu->adev;
2135         uint32_t val;
2136
2137         if (!smu_v11_0_baco_is_support(smu) || amdgpu_sriov_vf(adev))
2138                 return false;
2139
2140         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
2141         return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
2142 }
2143
2144 static int arcturus_set_df_cstate(struct smu_context *smu,
2145                                   enum pp_df_cstate state)
2146 {
2147         uint32_t smu_version;
2148         int ret;
2149
2150         ret = smu_get_smc_version(smu, NULL, &smu_version);
2151         if (ret) {
2152                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2153                 return ret;
2154         }
2155
2156         /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
2157         if (smu_version < 0x360F00) {
2158                 dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
2159                 return -EINVAL;
2160         }
2161
2162         return smu_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
2163 }
2164
2165 static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en)
2166 {
2167         uint32_t smu_version;
2168         int ret;
2169
2170         ret = smu_get_smc_version(smu, NULL, &smu_version);
2171         if (ret) {
2172                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2173                 return ret;
2174         }
2175
2176         /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */
2177         if (smu_version < 0x00361700) {
2178                 dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");
2179                 return -EINVAL;
2180         }
2181
2182         if (en)
2183                 return smu_send_smc_msg_with_param(smu,
2184                                                    SMU_MSG_GmiPwrDnControl,
2185                                                    1,
2186                                                    NULL);
2187
2188         return smu_send_smc_msg_with_param(smu,
2189                                            SMU_MSG_GmiPwrDnControl,
2190                                            0,
2191                                            NULL);
2192 }
2193
2194 static const struct throttling_logging_label {
2195         uint32_t feature_mask;
2196         const char *label;
2197 } logging_label[] = {
2198         {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
2199         {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
2200         {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
2201         {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
2202         {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
2203         {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"},
2204         {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"},
2205 };
2206 static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
2207 {
2208         int throttler_idx, throtting_events = 0, buf_idx = 0;
2209         struct amdgpu_device *adev = smu->adev;
2210         uint32_t throttler_status;
2211         char log_buf[256];
2212
2213         arcturus_get_smu_metrics_data(smu,
2214                                       METRICS_THROTTLER_STATUS,
2215                                       &throttler_status);
2216
2217         memset(log_buf, 0, sizeof(log_buf));
2218         for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
2219              throttler_idx++) {
2220                 if (throttler_status & logging_label[throttler_idx].feature_mask) {
2221                         throtting_events++;
2222                         buf_idx += snprintf(log_buf + buf_idx,
2223                                             sizeof(log_buf) - buf_idx,
2224                                             "%s%s",
2225                                             throtting_events > 1 ? " and " : "",
2226                                             logging_label[throttler_idx].label);
2227                         if (buf_idx >= sizeof(log_buf)) {
2228                                 dev_err(adev->dev, "buffer overflow!\n");
2229                                 log_buf[sizeof(log_buf) - 1] = '\0';
2230                                 break;
2231                         }
2232                 }
2233         }
2234
2235         dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
2236                         log_buf);
2237 }
2238
2239 static const struct pptable_funcs arcturus_ppt_funcs = {
2240         /* internal structurs allocations */
2241         .tables_init = arcturus_tables_init,
2242         .alloc_dpm_context = arcturus_allocate_dpm_context,
2243         /* init dpm */
2244         .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2245         /* btc */
2246         .run_btc = arcturus_run_btc,
2247         /* dpm/clk tables */
2248         .set_default_dpm_table = arcturus_set_default_dpm_table,
2249         .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2250         .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2251         .print_clk_levels = arcturus_print_clk_levels,
2252         .force_clk_levels = arcturus_force_clk_levels,
2253         .read_sensor = arcturus_read_sensor,
2254         .get_fan_speed_percent = arcturus_get_fan_speed_percent,
2255         .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
2256         .get_power_profile_mode = arcturus_get_power_profile_mode,
2257         .set_power_profile_mode = arcturus_set_power_profile_mode,
2258         .set_performance_level = arcturus_set_performance_level,
2259         /* debug (internal used) */
2260         .dump_pptable = arcturus_dump_pptable,
2261         .get_power_limit = arcturus_get_power_limit,
2262         .is_dpm_running = arcturus_is_dpm_running,
2263         .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
2264         .i2c_eeprom_init = arcturus_i2c_eeprom_control_init,
2265         .i2c_eeprom_fini = arcturus_i2c_eeprom_control_fini,
2266         .get_unique_id = arcturus_get_unique_id,
2267         .init_microcode = smu_v11_0_init_microcode,
2268         .load_microcode = smu_v11_0_load_microcode,
2269         .fini_microcode = smu_v11_0_fini_microcode,
2270         .init_smc_tables = smu_v11_0_init_smc_tables,
2271         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2272         .init_power = smu_v11_0_init_power,
2273         .fini_power = smu_v11_0_fini_power,
2274         .check_fw_status = smu_v11_0_check_fw_status,
2275         /* pptable related */
2276         .setup_pptable = arcturus_setup_pptable,
2277         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2278         .check_fw_version = smu_v11_0_check_fw_version,
2279         .write_pptable = smu_v11_0_write_pptable,
2280         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2281         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2282         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2283         .system_features_control = smu_v11_0_system_features_control,
2284         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2285         .init_display_count = NULL,
2286         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2287         .get_enabled_mask = smu_v11_0_get_enabled_mask,
2288         .notify_display_change = NULL,
2289         .set_power_limit = smu_v11_0_set_power_limit,
2290         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2291         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2292         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2293         .set_min_dcef_deep_sleep = NULL,
2294         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2295         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2296         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2297         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2298         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2299         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2300         .gfx_off_control = smu_v11_0_gfx_off_control,
2301         .register_irq_handler = smu_v11_0_register_irq_handler,
2302         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2303         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2304         .baco_is_support= arcturus_is_baco_supported,
2305         .baco_get_state = smu_v11_0_baco_get_state,
2306         .baco_set_state = smu_v11_0_baco_set_state,
2307         .baco_enter = smu_v11_0_baco_enter,
2308         .baco_exit = smu_v11_0_baco_exit,
2309         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2310         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2311         .set_df_cstate = arcturus_set_df_cstate,
2312         .allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
2313         .log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
2314 };
2315
2316 void arcturus_set_ppt_funcs(struct smu_context *smu)
2317 {
2318         smu->ppt_funcs = &arcturus_ppt_funcs;
2319         smu->message_map = arcturus_message_map;
2320         smu->clock_map = arcturus_clk_map;
2321         smu->feature_map = arcturus_feature_mask_map;
2322         smu->table_map = arcturus_table_map;
2323         smu->pwr_src_map = arcturus_pwr_src_map;
2324         smu->workload_map = arcturus_workload_map;
2325 }