drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/pci.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_internal.h"
  29 #include "smu_v11_0.h"
  30 #include "smu_v12_0.h"
  31 #include "atom.h"
  32 #include "arcturus_ppt.h"
  33 #include "navi10_ppt.h"
  34 #include "sienna_cichlid_ppt.h"
  35 #include "renoir_ppt.h"
  36
  37 /*
  38  * DO NOT use these for err/warn/info/debug messages.
  39  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  40  * They are more MGPU friendly.
  41  */
  42 #undef pr_err
  43 #undef pr_warn
  44 #undef pr_info
  45 #undef pr_debug
  46
  47 #undef __SMU_DUMMY_MAP
  48 #define __SMU_DUMMY_MAP(type)   #type
  49 static const char* __smu_message_names[] = {
  50         SMU_MESSAGE_TYPES
  51 };
  52
  53 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
  54 {
  55         if (type < 0 || type >= SMU_MSG_MAX_COUNT)
  56                 return "unknown smu message";
  57         return __smu_message_names[type];
  58 }
  59
  60 #undef __SMU_DUMMY_MAP
  61 #define __SMU_DUMMY_MAP(fea)    #fea
  62 static const char* __smu_feature_names[] = {
  63         SMU_FEATURE_MASKS
  64 };
  65
  66 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
  67 {
  68         if (feature < 0 || feature >= SMU_FEATURE_COUNT)
  69                 return "unknown smu feature";
  70         return __smu_feature_names[feature];
  71 }
  72
  73 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
  74 {
  75         size_t size = 0;
  76         int ret = 0, i = 0;
  77         uint32_t feature_mask[2] = { 0 };
  78         int32_t feature_index = 0;
  79         uint32_t count = 0;
  80         uint32_t sort_feature[SMU_FEATURE_COUNT];
  81         uint64_t hw_feature_count = 0;
  82
  83         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  84                 return -EOPNOTSUPP;
  85
  86         mutex_lock(&smu->mutex);
  87
  88         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
  89         if (ret)
  90                 goto failed;
  91
  92         size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
  93                         feature_mask[1], feature_mask[0]);
  94
  95         for (i = 0; i < SMU_FEATURE_COUNT; i++) {
  96                 feature_index = smu_feature_get_index(smu, i);
  97                 if (feature_index < 0)
  98                         continue;
  99                 sort_feature[feature_index] = i;
 100                 hw_feature_count++;
 101         }
 102
 103         for (i = 0; i < hw_feature_count; i++) {
 104                 size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
 105                                count++,
 106                                smu_get_feature_name(smu, sort_feature[i]),
 107                                i,
 108                                !!smu_feature_is_enabled(smu, sort_feature[i]) ?
 109                                "enabled" : "disabled");
 110         }
 111
 112 failed:
 113         mutex_unlock(&smu->mutex);
 114
 115         return size;
 116 }
 117
 118 static int smu_feature_update_enable_state(struct smu_context *smu,
 119                                            uint64_t feature_mask,
 120                                            bool enabled)
 121 {
 122         struct smu_feature *feature = &smu->smu_feature;
 123         int ret = 0;
 124
 125         if (enabled) {
 126                 ret = smu_send_smc_msg_with_param(smu,
 127                                                   SMU_MSG_EnableSmuFeaturesLow,
 128                                                   lower_32_bits(feature_mask),
 129                                                   NULL);
 130                 if (ret)
 131                         return ret;
 132                 ret = smu_send_smc_msg_with_param(smu,
 133                                                   SMU_MSG_EnableSmuFeaturesHigh,
 134                                                   upper_32_bits(feature_mask),
 135                                                   NULL);
 136                 if (ret)
 137                         return ret;
 138         } else {
 139                 ret = smu_send_smc_msg_with_param(smu,
 140                                                   SMU_MSG_DisableSmuFeaturesLow,
 141                                                   lower_32_bits(feature_mask),
 142                                                   NULL);
 143                 if (ret)
 144                         return ret;
 145                 ret = smu_send_smc_msg_with_param(smu,
 146                                                   SMU_MSG_DisableSmuFeaturesHigh,
 147                                                   upper_32_bits(feature_mask),
 148                                                   NULL);
 149                 if (ret)
 150                         return ret;
 151         }
 152
 153         mutex_lock(&feature->mutex);
 154         if (enabled)
 155                 bitmap_or(feature->enabled, feature->enabled,
 156                                 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
 157         else
 158                 bitmap_andnot(feature->enabled, feature->enabled,
 159                                 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
 160         mutex_unlock(&feature->mutex);
 161
 162         return ret;
 163 }
 164
 165 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
 166 {
 167         int ret = 0;
 168         uint32_t feature_mask[2] = { 0 };
 169         uint64_t feature_2_enabled = 0;
 170         uint64_t feature_2_disabled = 0;
 171         uint64_t feature_enables = 0;
 172
 173         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 174                 return -EOPNOTSUPP;
 175
 176         mutex_lock(&smu->mutex);
 177
 178         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 179         if (ret)
 180                 goto out;
 181
 182         feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
 183
 184         feature_2_enabled  = ~feature_enables & new_mask;
 185         feature_2_disabled = feature_enables & ~new_mask;
 186
 187         if (feature_2_enabled) {
 188                 ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
 189                 if (ret)
 190                         goto out;
 191         }
 192         if (feature_2_disabled) {
 193                 ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
 194                 if (ret)
 195                         goto out;
 196         }
 197
 198 out:
 199         mutex_unlock(&smu->mutex);
 200
 201         return ret;
 202 }
 203
 204 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
 205 {
 206         int ret = 0;
 207
 208         if (!if_version && !smu_version)
 209                 return -EINVAL;
 210
 211         if (smu->smc_fw_if_version && smu->smc_fw_version)
 212         {
 213                 if (if_version)
 214                         *if_version = smu->smc_fw_if_version;
 215
 216                 if (smu_version)
 217                         *smu_version = smu->smc_fw_version;
 218
 219                 return 0;
 220         }
 221
 222         if (if_version) {
 223                 ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion, if_version);
 224                 if (ret)
 225                         return ret;
 226
 227                 smu->smc_fw_if_version = *if_version;
 228         }
 229
 230         if (smu_version) {
 231                 ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion, smu_version);
 232                 if (ret)
 233                         return ret;
 234
 235                 smu->smc_fw_version = *smu_version;
 236         }
 237
 238         return ret;
 239 }
 240
 241 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 242                             uint32_t min, uint32_t max, bool lock_needed)
 243 {
 244         int ret = 0;
 245
 246         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 247                 return 0;
 248
 249         if (lock_needed)
 250                 mutex_lock(&smu->mutex);
 251         ret = smu_set_soft_freq_limited_range(smu, clk_type, min, max);
 252         if (lock_needed)
 253                 mutex_unlock(&smu->mutex);
 254
 255         return ret;
 256 }
 257
 258 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 259                             uint32_t min, uint32_t max)
 260 {
 261         int ret = 0, clk_id = 0;
 262         uint32_t param;
 263
 264         if (min <= 0 && max <= 0)
 265                 return -EINVAL;
 266
 267         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 268                 return 0;
 269
 270         clk_id = smu_clk_get_index(smu, clk_type);
 271         if (clk_id < 0)
 272                 return clk_id;
 273
 274         if (max > 0) {
 275                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
 276                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
 277                                                   param, NULL);
 278                 if (ret)
 279                         return ret;
 280         }
 281
 282         if (min > 0) {
 283                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
 284                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
 285                                                   param, NULL);
 286                 if (ret)
 287                         return ret;
 288         }
 289
 290
 291         return ret;
 292 }
 293
 294 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 295                            uint32_t *min, uint32_t *max, bool lock_needed)
 296 {
 297         uint32_t clock_limit;
 298         int ret = 0;
 299
 300         if (!min && !max)
 301                 return -EINVAL;
 302
 303         if (lock_needed)
 304                 mutex_lock(&smu->mutex);
 305
 306         if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
 307                 switch (clk_type) {
 308                 case SMU_MCLK:
 309                 case SMU_UCLK:
 310                         clock_limit = smu->smu_table.boot_values.uclk;
 311                         break;
 312                 case SMU_GFXCLK:
 313                 case SMU_SCLK:
 314                         clock_limit = smu->smu_table.boot_values.gfxclk;
 315                         break;
 316                 case SMU_SOCCLK:
 317                         clock_limit = smu->smu_table.boot_values.socclk;
 318                         break;
 319                 default:
 320                         clock_limit = 0;
 321                         break;
 322                 }
 323
 324                 /* clock in Mhz unit */
 325                 if (min)
 326                         *min = clock_limit / 100;
 327                 if (max)
 328                         *max = clock_limit / 100;
 329         } else {
 330                 /*
 331                  * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
 332                  * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
 333                  */
 334                 ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
 335         }
 336
 337         if (lock_needed)
 338                 mutex_unlock(&smu->mutex);
 339
 340         return ret;
 341 }
 342
 343 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
 344                               uint16_t level, uint32_t *value)
 345 {
 346         int ret = 0, clk_id = 0;
 347         uint32_t param;
 348
 349         if (!value)
 350                 return -EINVAL;
 351
 352         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 353                 return 0;
 354
 355         clk_id = smu_clk_get_index(smu, clk_type);
 356         if (clk_id < 0)
 357                 return clk_id;
 358
 359         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
 360
 361         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmFreqByIndex,
 362                                           param, value);
 363         if (ret)
 364                 return ret;
 365
 366         /* BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
 367          * now, we un-support it */
 368         *value = *value & 0x7fffffff;
 369
 370         return ret;
 371 }
 372
 373 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
 374                             uint32_t *value)
 375 {
 376         return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
 377 }
 378
 379 int smu_get_dpm_level_range(struct smu_context *smu, enum smu_clk_type clk_type,
 380                             uint32_t *min_value, uint32_t *max_value)
 381 {
 382         int ret = 0;
 383         uint32_t level_count = 0;
 384
 385         if (!min_value && !max_value)
 386                 return -EINVAL;
 387
 388         if (min_value) {
 389                 /* by default, level 0 clock value as min value */
 390                 ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, min_value);
 391                 if (ret)
 392                         return ret;
 393         }
 394
 395         if (max_value) {
 396                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
 397                 if (ret)
 398                         return ret;
 399
 400                 ret = smu_get_dpm_freq_by_index(smu, clk_type, level_count - 1, max_value);
 401                 if (ret)
 402                         return ret;
 403         }
 404
 405         return ret;
 406 }
 407
 408 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
 409 {
 410         enum smu_feature_mask feature_id = 0;
 411
 412         switch (clk_type) {
 413         case SMU_MCLK:
 414         case SMU_UCLK:
 415                 feature_id = SMU_FEATURE_DPM_UCLK_BIT;
 416                 break;
 417         case SMU_GFXCLK:
 418         case SMU_SCLK:
 419                 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
 420                 break;
 421         case SMU_SOCCLK:
 422                 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
 423                 break;
 424         default:
 425                 return true;
 426         }
 427
 428         if(!smu_feature_is_enabled(smu, feature_id)) {
 429                 return false;
 430         }
 431
 432         return true;
 433 }
 434
 435 /**
 436  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
 437  *
 438  * @smu:        smu_context pointer
 439  * @block_type: the IP block to power gate/ungate
 440  * @gate:       to power gate if true, ungate otherwise
 441  *
 442  * This API uses no smu->mutex lock protection due to:
 443  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
 444  *    This is guarded to be race condition free by the caller.
 445  * 2. Or get called on user setting request of power_dpm_force_performance_level.
 446  *    Under this case, the smu->mutex lock protection is already enforced on
 447  *    the parent API smu_force_performance_level of the call path.
 448  */
 449 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 450                            bool gate)
 451 {
 452         int ret = 0;
 453
 454         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 455                 return -EOPNOTSUPP;
 456
 457         switch (block_type) {
 458         /*
 459          * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
 460          * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
 461          */
 462         case AMD_IP_BLOCK_TYPE_UVD:
 463         case AMD_IP_BLOCK_TYPE_VCN:
 464                 ret = smu_dpm_set_vcn_enable(smu, !gate);
 465                 if (ret)
 466                         dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
 467                                 gate ? "gate" : "ungate");
 468                 break;
 469         case AMD_IP_BLOCK_TYPE_GFX:
 470                 ret = smu_gfx_off_control(smu, gate);
 471                 if (ret)
 472                         dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
 473                                 gate ? "enable" : "disable");
 474                 break;
 475         case AMD_IP_BLOCK_TYPE_SDMA:
 476                 ret = smu_powergate_sdma(smu, gate);
 477                 if (ret)
 478                         dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
 479                                 gate ? "gate" : "ungate");
 480                 break;
 481         case AMD_IP_BLOCK_TYPE_JPEG:
 482                 ret = smu_dpm_set_jpeg_enable(smu, !gate);
 483                 if (ret)
 484                         dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
 485                                 gate ? "gate" : "ungate");
 486                 break;
 487         default:
 488                 dev_err(smu->adev->dev, "Unsupported block type!\n");
 489                 return -EINVAL;
 490         }
 491
 492         return ret;
 493 }
 494
 495 int smu_get_power_num_states(struct smu_context *smu,
 496                              struct pp_states_info *state_info)
 497 {
 498         if (!state_info)
 499                 return -EINVAL;
 500
 501         /* not support power state */
 502         memset(state_info, 0, sizeof(struct pp_states_info));
 503         state_info->nums = 1;
 504         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 505
 506         return 0;
 507 }
 508
 509 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
 510                      void *table_data, bool drv2smu)
 511 {
 512         struct smu_table_context *smu_table = &smu->smu_table;
 513         struct amdgpu_device *adev = smu->adev;
 514         struct smu_table *table = &smu_table->driver_table;
 515         int table_id = smu_table_get_index(smu, table_index);
 516         uint32_t table_size;
 517         int ret = 0;
 518         if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0)
 519                 return -EINVAL;
 520
 521         table_size = smu_table->tables[table_index].size;
 522
 523         if (drv2smu) {
 524                 memcpy(table->cpu_addr, table_data, table_size);
 525                 /*
 526                  * Flush hdp cache: to guard the content seen by
 527                  * GPU is consitent with CPU.
 528                  */
 529                 amdgpu_asic_flush_hdp(adev, NULL);
 530         }
 531
 532         ret = smu_send_smc_msg_with_param(smu, drv2smu ?
 533                                           SMU_MSG_TransferTableDram2Smu :
 534                                           SMU_MSG_TransferTableSmu2Dram,
 535                                           table_id | ((argument & 0xFFFF) << 16),
 536                                           NULL);
 537         if (ret)
 538                 return ret;
 539
 540         if (!drv2smu) {
 541                 amdgpu_asic_flush_hdp(adev, NULL);
 542                 memcpy(table_data, table->cpu_addr, table_size);
 543         }
 544
 545         return ret;
 546 }
 547
 548 bool is_support_sw_smu(struct amdgpu_device *adev)
 549 {
 550         if (adev->asic_type >= CHIP_ARCTURUS)
 551                 return true;
 552
 553         return false;
 554 }
 555
 556 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 557 {
 558         struct smu_table_context *smu_table = &smu->smu_table;
 559         uint32_t powerplay_table_size;
 560
 561         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 562                 return -EOPNOTSUPP;
 563
 564         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 565                 return -EINVAL;
 566
 567         mutex_lock(&smu->mutex);
 568
 569         if (smu_table->hardcode_pptable)
 570                 *table = smu_table->hardcode_pptable;
 571         else
 572                 *table = smu_table->power_play_table;
 573
 574         powerplay_table_size = smu_table->power_play_table_size;
 575
 576         mutex_unlock(&smu->mutex);
 577
 578         return powerplay_table_size;
 579 }
 580
 581 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 582 {
 583         struct smu_table_context *smu_table = &smu->smu_table;
 584         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 585         int ret = 0;
 586
 587         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 588                 return -EOPNOTSUPP;
 589
 590         if (header->usStructureSize != size) {
 591                 dev_err(smu->adev->dev, "pp table size not matched !\n");
 592                 return -EIO;
 593         }
 594
 595         mutex_lock(&smu->mutex);
 596         if (!smu_table->hardcode_pptable)
 597                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 598         if (!smu_table->hardcode_pptable) {
 599                 ret = -ENOMEM;
 600                 goto failed;
 601         }
 602
 603         memcpy(smu_table->hardcode_pptable, buf, size);
 604         smu_table->power_play_table = smu_table->hardcode_pptable;
 605         smu_table->power_play_table_size = size;
 606
 607         /*
 608          * Special hw_fini action(for Navi1x, the DPMs disablement will be
 609          * skipped) may be needed for custom pptable uploading.
 610          */
 611         smu->uploading_custom_pp_table = true;
 612
 613         ret = smu_reset(smu);
 614         if (ret)
 615                 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
 616
 617         smu->uploading_custom_pp_table = false;
 618
 619 failed:
 620         mutex_unlock(&smu->mutex);
 621         return ret;
 622 }
 623
 624 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
 625 {
 626         struct smu_feature *feature = &smu->smu_feature;
 627         int ret = 0;
 628         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 629
 630         mutex_lock(&feature->mutex);
 631         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 632         mutex_unlock(&feature->mutex);
 633
 634         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 635                                              SMU_FEATURE_MAX/32);
 636         if (ret)
 637                 return ret;
 638
 639         mutex_lock(&feature->mutex);
 640         bitmap_or(feature->allowed, feature->allowed,
 641                       (unsigned long *)allowed_feature_mask,
 642                       feature->feature_num);
 643         mutex_unlock(&feature->mutex);
 644
 645         return ret;
 646 }
 647
 648 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
 649 {
 650         struct smu_feature *feature = &smu->smu_feature;
 651         int feature_id;
 652         int ret = 0;
 653
 654         if (smu->is_apu)
 655                 return 1;
 656         feature_id = smu_feature_get_index(smu, mask);
 657         if (feature_id < 0)
 658                 return 0;
 659
 660         WARN_ON(feature_id > feature->feature_num);
 661
 662         mutex_lock(&feature->mutex);
 663         ret = test_bit(feature_id, feature->enabled);
 664         mutex_unlock(&feature->mutex);
 665
 666         return ret;
 667 }
 668
 669 int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
 670                             bool enable)
 671 {
 672         struct smu_feature *feature = &smu->smu_feature;
 673         int feature_id;
 674
 675         feature_id = smu_feature_get_index(smu, mask);
 676         if (feature_id < 0)
 677                 return -EINVAL;
 678
 679         WARN_ON(feature_id > feature->feature_num);
 680
 681         return smu_feature_update_enable_state(smu,
 682                                                1ULL << feature_id,
 683                                                enable);
 684 }
 685
 686 int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
 687 {
 688         struct smu_feature *feature = &smu->smu_feature;
 689         int feature_id;
 690         int ret = 0;
 691
 692         feature_id = smu_feature_get_index(smu, mask);
 693         if (feature_id < 0)
 694                 return 0;
 695
 696         WARN_ON(feature_id > feature->feature_num);
 697
 698         mutex_lock(&feature->mutex);
 699         ret = test_bit(feature_id, feature->supported);
 700         mutex_unlock(&feature->mutex);
 701
 702         return ret;
 703 }
 704
 705 static int smu_set_funcs(struct amdgpu_device *adev)
 706 {
 707         struct smu_context *smu = &adev->smu;
 708
 709         if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 710                 smu->od_enabled = true;
 711
 712         switch (adev->asic_type) {
 713         case CHIP_NAVI10:
 714         case CHIP_NAVI14:
 715         case CHIP_NAVI12:
 716                 navi10_set_ppt_funcs(smu);
 717                 break;
 718         case CHIP_ARCTURUS:
 719                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 720                 arcturus_set_ppt_funcs(smu);
 721                 /* OD is not supported on Arcturus */
 722                 smu->od_enabled =false;
 723                 break;
 724         case CHIP_SIENNA_CICHLID:
 725                 sienna_cichlid_set_ppt_funcs(smu);
 726                 break;
 727         case CHIP_RENOIR:
 728                 renoir_set_ppt_funcs(smu);
 729                 break;
 730         default:
 731                 return -EINVAL;
 732         }
 733
 734         return 0;
 735 }
 736
 737 static int smu_early_init(void *handle)
 738 {
 739         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 740         struct smu_context *smu = &adev->smu;
 741
 742         smu->adev = adev;
 743         smu->pm_enabled = !!amdgpu_dpm;
 744         smu->is_apu = false;
 745         mutex_init(&smu->mutex);
 746
 747         return smu_set_funcs(adev);
 748 }
 749
 750 static int smu_late_init(void *handle)
 751 {
 752         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 753         struct smu_context *smu = &adev->smu;
 754         int ret = 0;
 755
 756         if (!smu->pm_enabled)
 757                 return 0;
 758
 759         ret = smu_set_default_od_settings(smu);
 760         if (ret) {
 761                 dev_err(adev->dev, "Failed to setup default OD settings!\n");
 762                 return ret;
 763         }
 764
 765         /*
 766          * Set initialized values (get from vbios) to dpm tables context such as
 767          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
 768          * type of clks.
 769          */
 770         ret = smu_set_default_dpm_table(smu);
 771         if (ret) {
 772                 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
 773                 return ret;
 774         }
 775
 776         ret = smu_populate_umd_state_clk(smu);
 777         if (ret) {
 778                 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
 779                 return ret;
 780         }
 781
 782         ret = smu_get_asic_power_limits(smu);
 783         if (ret) {
 784                 dev_err(adev->dev, "Failed to get asic power limits!\n");
 785                 return ret;
 786         }
 787
 788         smu_get_unique_id(smu);
 789
 790         smu_handle_task(&adev->smu,
 791                         smu->smu_dpm.dpm_level,
 792                         AMD_PP_TASK_COMPLETE_INIT,
 793                         false);
 794
 795         return 0;
 796 }
 797
 798 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
 799                             uint16_t *size, uint8_t *frev, uint8_t *crev,
 800                             uint8_t **addr)
 801 {
 802         struct amdgpu_device *adev = smu->adev;
 803         uint16_t data_start;
 804
 805         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
 806                                            size, frev, crev, &data_start))
 807                 return -EINVAL;
 808
 809         *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
 810
 811         return 0;
 812 }
 813
 814 static int smu_init_fb_allocations(struct smu_context *smu)
 815 {
 816         struct amdgpu_device *adev = smu->adev;
 817         struct smu_table_context *smu_table = &smu->smu_table;
 818         struct smu_table *tables = smu_table->tables;
 819         struct smu_table *driver_table = &(smu_table->driver_table);
 820         uint32_t max_table_size = 0;
 821         int ret, i;
 822
 823         /* VRAM allocation for tool table */
 824         if (tables[SMU_TABLE_PMSTATUSLOG].size) {
 825                 ret = amdgpu_bo_create_kernel(adev,
 826                                               tables[SMU_TABLE_PMSTATUSLOG].size,
 827                                               tables[SMU_TABLE_PMSTATUSLOG].align,
 828                                               tables[SMU_TABLE_PMSTATUSLOG].domain,
 829                                               &tables[SMU_TABLE_PMSTATUSLOG].bo,
 830                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 831                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 832                 if (ret) {
 833                         dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
 834                         return ret;
 835                 }
 836         }
 837
 838         /* VRAM allocation for driver table */
 839         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 840                 if (tables[i].size == 0)
 841                         continue;
 842
 843                 if (i == SMU_TABLE_PMSTATUSLOG)
 844                         continue;
 845
 846                 if (max_table_size < tables[i].size)
 847                         max_table_size = tables[i].size;
 848         }
 849
 850         driver_table->size = max_table_size;
 851         driver_table->align = PAGE_SIZE;
 852         driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 853
 854         ret = amdgpu_bo_create_kernel(adev,
 855                                       driver_table->size,
 856                                       driver_table->align,
 857                                       driver_table->domain,
 858                                       &driver_table->bo,
 859                                       &driver_table->mc_address,
 860                                       &driver_table->cpu_addr);
 861         if (ret) {
 862                 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
 863                 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 864                         amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 865                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 866                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 867         }
 868
 869         return ret;
 870 }
 871
 872 static int smu_fini_fb_allocations(struct smu_context *smu)
 873 {
 874         struct smu_table_context *smu_table = &smu->smu_table;
 875         struct smu_table *tables = smu_table->tables;
 876         struct smu_table *driver_table = &(smu_table->driver_table);
 877
 878         if (!tables)
 879                 return 0;
 880
 881         if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 882                 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 883                                       &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 884                                       &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 885
 886         amdgpu_bo_free_kernel(&driver_table->bo,
 887                               &driver_table->mc_address,
 888                               &driver_table->cpu_addr);
 889
 890         return 0;
 891 }
 892
 893 /**
 894  * smu_alloc_memory_pool - allocate memory pool in the system memory
 895  *
 896  * @smu: amdgpu_device pointer
 897  *
 898  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
 899  * and DramLogSetDramAddr can notify it changed.
 900  *
 901  * Returns 0 on success, error on failure.
 902  */
 903 static int smu_alloc_memory_pool(struct smu_context *smu)
 904 {
 905         struct amdgpu_device *adev = smu->adev;
 906         struct smu_table_context *smu_table = &smu->smu_table;
 907         struct smu_table *memory_pool = &smu_table->memory_pool;
 908         uint64_t pool_size = smu->pool_size;
 909         int ret = 0;
 910
 911         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
 912                 return ret;
 913
 914         memory_pool->size = pool_size;
 915         memory_pool->align = PAGE_SIZE;
 916         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
 917
 918         switch (pool_size) {
 919         case SMU_MEMORY_POOL_SIZE_256_MB:
 920         case SMU_MEMORY_POOL_SIZE_512_MB:
 921         case SMU_MEMORY_POOL_SIZE_1_GB:
 922         case SMU_MEMORY_POOL_SIZE_2_GB:
 923                 ret = amdgpu_bo_create_kernel(adev,
 924                                               memory_pool->size,
 925                                               memory_pool->align,
 926                                               memory_pool->domain,
 927                                               &memory_pool->bo,
 928                                               &memory_pool->mc_address,
 929                                               &memory_pool->cpu_addr);
 930                 if (ret)
 931                         dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
 932                 break;
 933         default:
 934                 break;
 935         }
 936
 937         return ret;
 938 }
 939
 940 static int smu_free_memory_pool(struct smu_context *smu)
 941 {
 942         struct smu_table_context *smu_table = &smu->smu_table;
 943         struct smu_table *memory_pool = &smu_table->memory_pool;
 944
 945         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
 946                 return 0;
 947
 948         amdgpu_bo_free_kernel(&memory_pool->bo,
 949                               &memory_pool->mc_address,
 950                               &memory_pool->cpu_addr);
 951
 952         memset(memory_pool, 0, sizeof(struct smu_table));
 953
 954         return 0;
 955 }
 956
 957 static int smu_smc_table_sw_init(struct smu_context *smu)
 958 {
 959         int ret;
 960
 961         /**
 962          * Create smu_table structure, and init smc tables such as
 963          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 964          */
 965         ret = smu_init_smc_tables(smu);
 966         if (ret) {
 967                 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
 968                 return ret;
 969         }
 970
 971         /**
 972          * Create smu_power_context structure, and allocate smu_dpm_context and
 973          * context size to fill the smu_power_context data.
 974          */
 975         ret = smu_init_power(smu);
 976         if (ret) {
 977                 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
 978                 return ret;
 979         }
 980
 981         /*
 982          * allocate vram bos to store smc table contents.
 983          */
 984         ret = smu_init_fb_allocations(smu);
 985         if (ret)
 986                 return ret;
 987
 988         ret = smu_alloc_memory_pool(smu);
 989         if (ret)
 990                 return ret;
 991
 992         return 0;
 993 }
 994
 995 static int smu_smc_table_sw_fini(struct smu_context *smu)
 996 {
 997         int ret;
 998
 999         ret = smu_free_memory_pool(smu);
1000         if (ret)
1001                 return ret;
1002
1003         ret = smu_fini_fb_allocations(smu);
1004         if (ret)
1005                 return ret;
1006
1007         ret = smu_fini_power(smu);
1008         if (ret) {
1009                 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
1010                 return ret;
1011         }
1012
1013         ret = smu_fini_smc_tables(smu);
1014         if (ret) {
1015                 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
1016                 return ret;
1017         }
1018
1019         return 0;
1020 }
1021
1022 static void smu_throttling_logging_work_fn(struct work_struct *work)
1023 {
1024         struct smu_context *smu = container_of(work, struct smu_context,
1025                                                throttling_logging_work);
1026
1027         smu_log_thermal_throttling(smu);
1028 }
1029
1030 static int smu_sw_init(void *handle)
1031 {
1032         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1033         struct smu_context *smu = &adev->smu;
1034         int ret;
1035
1036         smu->pool_size = adev->pm.smu_prv_buffer_size;
1037         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
1038         mutex_init(&smu->smu_feature.mutex);
1039         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
1040         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
1041         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
1042
1043         mutex_init(&smu->smu_baco.mutex);
1044         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
1045         smu->smu_baco.platform_support = false;
1046
1047         mutex_init(&smu->sensor_lock);
1048         mutex_init(&smu->metrics_lock);
1049         mutex_init(&smu->message_lock);
1050
1051         INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
1052         smu->watermarks_bitmap = 0;
1053         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1054         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1055
1056         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
1057         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
1058         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
1059         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
1060         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
1061         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
1062         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
1063         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
1064
1065         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1066         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1067         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
1068         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
1069         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
1070         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
1071         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
1072         smu->display_config = &adev->pm.pm_display_cfg;
1073
1074         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1075         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1076         ret = smu_init_microcode(smu);
1077         if (ret) {
1078                 dev_err(adev->dev, "Failed to load smu firmware!\n");
1079                 return ret;
1080         }
1081
1082         ret = smu_smc_table_sw_init(smu);
1083         if (ret) {
1084                 dev_err(adev->dev, "Failed to sw init smc table!\n");
1085                 return ret;
1086         }
1087
1088         ret = smu_register_irq_handler(smu);
1089         if (ret) {
1090                 dev_err(adev->dev, "Failed to register smc irq handler!\n");
1091                 return ret;
1092         }
1093
1094         return 0;
1095 }
1096
1097 static int smu_sw_fini(void *handle)
1098 {
1099         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1100         struct smu_context *smu = &adev->smu;
1101         int ret;
1102
1103         ret = smu_smc_table_sw_fini(smu);
1104         if (ret) {
1105                 dev_err(adev->dev, "Failed to sw fini smc table!\n");
1106                 return ret;
1107         }
1108
1109         smu_fini_microcode(smu);
1110
1111         return 0;
1112 }
1113
1114 static int smu_smc_hw_setup(struct smu_context *smu)
1115 {
1116         struct amdgpu_device *adev = smu->adev;
1117         int ret;
1118
1119         if (smu_is_dpm_running(smu) && adev->in_suspend) {
1120                 dev_info(adev->dev, "dpm has been enabled\n");
1121                 return 0;
1122         }
1123
1124         ret = smu_init_display_count(smu, 0);
1125         if (ret) {
1126                 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
1127                 return ret;
1128         }
1129
1130         ret = smu_set_driver_table_location(smu);
1131         if (ret) {
1132                 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
1133                 return ret;
1134         }
1135
1136         /*
1137          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1138          */
1139         ret = smu_set_tool_table_location(smu);
1140         if (ret) {
1141                 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
1142                 return ret;
1143         }
1144
1145         /*
1146          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1147          * pool location.
1148          */
1149         ret = smu_notify_memory_pool_location(smu);
1150         if (ret) {
1151                 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
1152                 return ret;
1153         }
1154
1155         /* smu_dump_pptable(smu); */
1156         /*
1157          * Copy pptable bo in the vram to smc with SMU MSGs such as
1158          * SetDriverDramAddr and TransferTableDram2Smu.
1159          */
1160         ret = smu_write_pptable(smu);
1161         if (ret) {
1162                 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
1163                 return ret;
1164         }
1165
1166         /* issue Run*Btc msg */
1167         ret = smu_run_btc(smu);
1168         if (ret)
1169                 return ret;
1170
1171         ret = smu_feature_set_allowed_mask(smu);
1172         if (ret) {
1173                 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
1174                 return ret;
1175         }
1176
1177         ret = smu_system_features_control(smu, true);
1178         if (ret) {
1179                 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
1180                 return ret;
1181         }
1182
1183         if (!smu_is_dpm_running(smu))
1184                 dev_info(adev->dev, "dpm has been disabled\n");
1185
1186         ret = smu_override_pcie_parameters(smu);
1187         if (ret)
1188                 return ret;
1189
1190         ret = smu_enable_thermal_alert(smu);
1191         if (ret) {
1192                 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1193                 return ret;
1194         }
1195
1196         ret = smu_i2c_eeprom_init(smu, &adev->pm.smu_i2c);
1197         if (ret)
1198                 return ret;
1199
1200         ret = smu_disable_umc_cdr_12gbps_workaround(smu);
1201         if (ret) {
1202                 dev_err(adev->dev, "Workaround failed to disable UMC CDR feature on 12Gbps SKU!\n");
1203                 return ret;
1204         }
1205
1206         /*
1207          * For Navi1X, manually switch it to AC mode as PMFW
1208          * may boot it with DC mode.
1209          */
1210         ret = smu_set_power_source(smu,
1211                                    adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
1212                                    SMU_POWER_SOURCE_DC);
1213         if (ret) {
1214                 dev_err(adev->dev, "Failed to switch to %s mode!\n", adev->pm.ac_power ? "AC" : "DC");
1215                 return ret;
1216         }
1217
1218         ret = smu_notify_display_change(smu);
1219         if (ret)
1220                 return ret;
1221
1222         /*
1223          * Set min deep sleep dce fclk with bootup value from vbios via
1224          * SetMinDeepSleepDcefclk MSG.
1225          */
1226         ret = smu_set_min_dcef_deep_sleep(smu,
1227                                           smu->smu_table.boot_values.dcefclk / 100);
1228         if (ret)
1229                 return ret;
1230
1231         return ret;
1232 }
1233
1234 static int smu_start_smc_engine(struct smu_context *smu)
1235 {
1236         struct amdgpu_device *adev = smu->adev;
1237         int ret = 0;
1238
1239         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1240                 if (adev->asic_type < CHIP_NAVI10) {
1241                         if (smu->ppt_funcs->load_microcode) {
1242                                 ret = smu->ppt_funcs->load_microcode(smu);
1243                                 if (ret)
1244                                         return ret;
1245                         }
1246                 }
1247         }
1248
1249         if (smu->ppt_funcs->check_fw_status) {
1250                 ret = smu->ppt_funcs->check_fw_status(smu);
1251                 if (ret) {
1252                         dev_err(adev->dev, "SMC is not ready\n");
1253                         return ret;
1254                 }
1255         }
1256
1257         /*
1258          * Send msg GetDriverIfVersion to check if the return value is equal
1259          * with DRIVER_IF_VERSION of smc header.
1260          */
1261         ret = smu_check_fw_version(smu);
1262         if (ret)
1263                 return ret;
1264
1265         return ret;
1266 }
1267
1268 static int smu_hw_init(void *handle)
1269 {
1270         int ret;
1271         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1272         struct smu_context *smu = &adev->smu;
1273
1274         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1275                 smu->pm_enabled = false;
1276                 return 0;
1277         }
1278
1279         ret = smu_start_smc_engine(smu);
1280         if (ret) {
1281                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1282                 return ret;
1283         }
1284
1285         if (smu->is_apu) {
1286                 smu_powergate_sdma(&adev->smu, false);
1287                 smu_dpm_set_vcn_enable(smu, true);
1288                 smu_dpm_set_jpeg_enable(smu, true);
1289                 smu_set_gfx_cgpg(&adev->smu, true);
1290         }
1291
1292         if (!smu->pm_enabled)
1293                 return 0;
1294
1295         /* get boot_values from vbios to set revision, gfxclk, and etc. */
1296         ret = smu_get_vbios_bootup_values(smu);
1297         if (ret) {
1298                 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1299                 return ret;
1300         }
1301
1302         ret = smu_setup_pptable(smu);
1303         if (ret) {
1304                 dev_err(adev->dev, "Failed to setup pptable!\n");
1305                 return ret;
1306         }
1307
1308         ret = smu_get_driver_allowed_feature_mask(smu);
1309         if (ret)
1310                 return ret;
1311
1312         ret = smu_smc_hw_setup(smu);
1313         if (ret) {
1314                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1315                 return ret;
1316         }
1317
1318         /*
1319          * Move maximum sustainable clock retrieving here considering
1320          * 1. It is not needed on resume(from S3).
1321          * 2. DAL settings come between .hw_init and .late_init of SMU.
1322          *    And DAL needs to know the maximum sustainable clocks. Thus
1323          *    it cannot be put in .late_init().
1324          */
1325         ret = smu_init_max_sustainable_clocks(smu);
1326         if (ret) {
1327                 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1328                 return ret;
1329         }
1330
1331         adev->pm.dpm_enabled = true;
1332
1333         dev_info(adev->dev, "SMU is initialized successfully!\n");
1334
1335         return 0;
1336 }
1337
1338 static int smu_disable_dpms(struct smu_context *smu)
1339 {
1340         struct amdgpu_device *adev = smu->adev;
1341         uint64_t features_to_disable;
1342         int ret = 0;
1343         bool use_baco = !smu->is_apu &&
1344                 ((adev->in_gpu_reset &&
1345                   (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1346                  ((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev)));
1347
1348         /*
1349          * For custom pptable uploading, skip the DPM features
1350          * disable process on Navi1x ASICs.
1351          *   - As the gfx related features are under control of
1352          *     RLC on those ASICs. RLC reinitialization will be
1353          *     needed to reenable them. That will cost much more
1354          *     efforts.
1355          *
1356          *   - SMU firmware can handle the DPM reenablement
1357          *     properly.
1358          */
1359         if (smu->uploading_custom_pp_table &&
1360             (adev->asic_type >= CHIP_NAVI10) &&
1361             (adev->asic_type <= CHIP_NAVI12))
1362                 return 0;
1363
1364         /*
1365          * For Sienna_Cichlid, PMFW will handle the features disablement properly
1366          * on BACO in. Driver involvement is unnecessary.
1367          */
1368         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1369              use_baco)
1370                 return 0;
1371
1372         /*
1373          * For gpu reset, runpm and hibernation through BACO,
1374          * BACO feature has to be kept enabled.
1375          */
1376         if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1377                 features_to_disable = U64_MAX &
1378                         ~(1ULL << smu_feature_get_index(smu, SMU_FEATURE_BACO_BIT));
1379                 ret = smu_feature_update_enable_state(smu,
1380                                                       features_to_disable,
1381                                                       0);
1382                 if (ret)
1383                         dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1384         } else {
1385                 ret = smu_system_features_control(smu, false);
1386                 if (ret)
1387                         dev_err(adev->dev, "Failed to disable smu features.\n");
1388         }
1389
1390         if (adev->asic_type >= CHIP_NAVI10 &&
1391             adev->gfx.rlc.funcs->stop)
1392                 adev->gfx.rlc.funcs->stop(adev);
1393
1394         return ret;
1395 }
1396
1397 static int smu_smc_hw_cleanup(struct smu_context *smu)
1398 {
1399         struct amdgpu_device *adev = smu->adev;
1400         int ret = 0;
1401
1402         smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);
1403
1404         cancel_work_sync(&smu->throttling_logging_work);
1405
1406         ret = smu_disable_thermal_alert(smu);
1407         if (ret) {
1408                 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1409                 return ret;
1410         }
1411
1412         ret = smu_disable_dpms(smu);
1413         if (ret) {
1414                 dev_err(adev->dev, "Fail to disable dpm features!\n");
1415                 return ret;
1416         }
1417
1418         return 0;
1419 }
1420
1421 static int smu_hw_fini(void *handle)
1422 {
1423         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1424         struct smu_context *smu = &adev->smu;
1425         int ret = 0;
1426
1427         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1428                 return 0;
1429
1430         if (smu->is_apu) {
1431                 smu_powergate_sdma(&adev->smu, true);
1432                 smu_dpm_set_vcn_enable(smu, false);
1433                 smu_dpm_set_jpeg_enable(smu, false);
1434         }
1435
1436         if (!smu->pm_enabled)
1437                 return 0;
1438
1439         adev->pm.dpm_enabled = false;
1440
1441         ret = smu_smc_hw_cleanup(smu);
1442         if (ret)
1443                 return ret;
1444
1445         return 0;
1446 }
1447
1448 int smu_reset(struct smu_context *smu)
1449 {
1450         struct amdgpu_device *adev = smu->adev;
1451         int ret = 0;
1452
1453         ret = smu_hw_fini(adev);
1454         if (ret)
1455                 return ret;
1456
1457         ret = smu_hw_init(adev);
1458         if (ret)
1459                 return ret;
1460
1461         ret = smu_late_init(adev);
1462
1463         return ret;
1464 }
1465
1466 static int smu_suspend(void *handle)
1467 {
1468         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1469         struct smu_context *smu = &adev->smu;
1470         int ret;
1471
1472         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1473                 return 0;
1474
1475         if (!smu->pm_enabled)
1476                 return 0;
1477
1478         adev->pm.dpm_enabled = false;
1479
1480         ret = smu_smc_hw_cleanup(smu);
1481         if (ret)
1482                 return ret;
1483
1484         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1485
1486         if (smu->is_apu)
1487                 smu_set_gfx_cgpg(&adev->smu, false);
1488
1489         return 0;
1490 }
1491
1492 static int smu_resume(void *handle)
1493 {
1494         int ret;
1495         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1496         struct smu_context *smu = &adev->smu;
1497
1498         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1499                 return 0;
1500
1501         if (!smu->pm_enabled)
1502                 return 0;
1503
1504         dev_info(adev->dev, "SMU is resuming...\n");
1505
1506         ret = smu_start_smc_engine(smu);
1507         if (ret) {
1508                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1509                 return ret;
1510         }
1511
1512         ret = smu_smc_hw_setup(smu);
1513         if (ret) {
1514                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1515                 return ret;
1516         }
1517
1518         if (smu->is_apu)
1519                 smu_set_gfx_cgpg(&adev->smu, true);
1520
1521         smu->disable_uclk_switch = 0;
1522
1523         adev->pm.dpm_enabled = true;
1524
1525         dev_info(adev->dev, "SMU is resumed successfully!\n");
1526
1527         return 0;
1528 }
1529
1530 int smu_display_configuration_change(struct smu_context *smu,
1531                                      const struct amd_pp_display_configuration *display_config)
1532 {
1533         int index = 0;
1534         int num_of_active_display = 0;
1535
1536         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1537                 return -EOPNOTSUPP;
1538
1539         if (!display_config)
1540                 return -EINVAL;
1541
1542         mutex_lock(&smu->mutex);
1543
1544         smu_set_min_dcef_deep_sleep(smu,
1545                                     display_config->min_dcef_deep_sleep_set_clk / 100);
1546
1547         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1548                 if (display_config->displays[index].controller_id != 0)
1549                         num_of_active_display++;
1550         }
1551
1552         smu_set_active_display_count(smu, num_of_active_display);
1553
1554         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1555                            display_config->cpu_cc6_disable,
1556                            display_config->cpu_pstate_disable,
1557                            display_config->nb_pstate_switch_disable);
1558
1559         mutex_unlock(&smu->mutex);
1560
1561         return 0;
1562 }
1563
1564 static int smu_get_clock_info(struct smu_context *smu,
1565                               struct smu_clock_info *clk_info,
1566                               enum smu_perf_level_designation designation)
1567 {
1568         int ret;
1569         struct smu_performance_level level = {0};
1570
1571         if (!clk_info)
1572                 return -EINVAL;
1573
1574         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1575         if (ret)
1576                 return -EINVAL;
1577
1578         clk_info->min_mem_clk = level.memory_clock;
1579         clk_info->min_eng_clk = level.core_clock;
1580         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1581
1582         ret = smu_get_perf_level(smu, designation, &level);
1583         if (ret)
1584                 return -EINVAL;
1585
1586         clk_info->min_mem_clk = level.memory_clock;
1587         clk_info->min_eng_clk = level.core_clock;
1588         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1589
1590         return 0;
1591 }
1592
1593 int smu_get_current_clocks(struct smu_context *smu,
1594                            struct amd_pp_clock_info *clocks)
1595 {
1596         struct amd_pp_simple_clock_info simple_clocks = {0};
1597         struct smu_clock_info hw_clocks;
1598         int ret = 0;
1599
1600         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1601                 return -EOPNOTSUPP;
1602
1603         mutex_lock(&smu->mutex);
1604
1605         smu_get_dal_power_level(smu, &simple_clocks);
1606
1607         if (smu->support_power_containment)
1608                 ret = smu_get_clock_info(smu, &hw_clocks,
1609                                          PERF_LEVEL_POWER_CONTAINMENT);
1610         else
1611                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1612
1613         if (ret) {
1614                 dev_err(smu->adev->dev, "Error in smu_get_clock_info\n");
1615                 goto failed;
1616         }
1617
1618         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1619         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1620         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1621         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1622         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1623         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1624         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1625         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1626
1627         if (simple_clocks.level == 0)
1628                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1629         else
1630                 clocks->max_clocks_state = simple_clocks.level;
1631
1632         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1633                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1634                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1635         }
1636
1637 failed:
1638         mutex_unlock(&smu->mutex);
1639         return ret;
1640 }
1641
1642 static int smu_set_clockgating_state(void *handle,
1643                                      enum amd_clockgating_state state)
1644 {
1645         return 0;
1646 }
1647
1648 static int smu_set_powergating_state(void *handle,
1649                                      enum amd_powergating_state state)
1650 {
1651         return 0;
1652 }
1653
1654 static int smu_enable_umd_pstate(void *handle,
1655                       enum amd_dpm_forced_level *level)
1656 {
1657         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1658                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1659                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1660                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1661
1662         struct smu_context *smu = (struct smu_context*)(handle);
1663         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1664
1665         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1666                 return -EINVAL;
1667
1668         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1669                 /* enter umd pstate, save current level, disable gfx cg*/
1670                 if (*level & profile_mode_mask) {
1671                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1672                         smu_dpm_ctx->enable_umd_pstate = true;
1673                         amdgpu_device_ip_set_powergating_state(smu->adev,
1674                                                                AMD_IP_BLOCK_TYPE_GFX,
1675                                                                AMD_PG_STATE_UNGATE);
1676                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1677                                                                AMD_IP_BLOCK_TYPE_GFX,
1678                                                                AMD_CG_STATE_UNGATE);
1679                 }
1680         } else {
1681                 /* exit umd pstate, restore level, enable gfx cg*/
1682                 if (!(*level & profile_mode_mask)) {
1683                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1684                                 *level = smu_dpm_ctx->saved_dpm_level;
1685                         smu_dpm_ctx->enable_umd_pstate = false;
1686                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1687                                                                AMD_IP_BLOCK_TYPE_GFX,
1688                                                                AMD_CG_STATE_GATE);
1689                         amdgpu_device_ip_set_powergating_state(smu->adev,
1690                                                                AMD_IP_BLOCK_TYPE_GFX,
1691                                                                AMD_PG_STATE_GATE);
1692                 }
1693         }
1694
1695         return 0;
1696 }
1697
1698 int smu_adjust_power_state_dynamic(struct smu_context *smu,
1699                                    enum amd_dpm_forced_level level,
1700                                    bool skip_display_settings)
1701 {
1702         int ret = 0;
1703         int index = 0;
1704         long workload;
1705         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1706
1707         if (!skip_display_settings) {
1708                 ret = smu_display_config_changed(smu);
1709                 if (ret) {
1710                         dev_err(smu->adev->dev, "Failed to change display config!");
1711                         return ret;
1712                 }
1713         }
1714
1715         ret = smu_apply_clocks_adjust_rules(smu);
1716         if (ret) {
1717                 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1718                 return ret;
1719         }
1720
1721         if (!skip_display_settings) {
1722                 ret = smu_notify_smc_display_config(smu);
1723                 if (ret) {
1724                         dev_err(smu->adev->dev, "Failed to notify smc display config!");
1725                         return ret;
1726                 }
1727         }
1728
1729         if (smu_dpm_ctx->dpm_level != level) {
1730                 ret = smu_asic_set_performance_level(smu, level);
1731                 if (ret) {
1732                         dev_err(smu->adev->dev, "Failed to set performance level!");
1733                         return ret;
1734                 }
1735
1736                 /* update the saved copy */
1737                 smu_dpm_ctx->dpm_level = level;
1738         }
1739
1740         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1741                 index = fls(smu->workload_mask);
1742                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1743                 workload = smu->workload_setting[index];
1744
1745                 if (smu->power_profile_mode != workload)
1746                         smu_set_power_profile_mode(smu, &workload, 0, false);
1747         }
1748
1749         return ret;
1750 }
1751
1752 int smu_handle_task(struct smu_context *smu,
1753                     enum amd_dpm_forced_level level,
1754                     enum amd_pp_task task_id,
1755                     bool lock_needed)
1756 {
1757         int ret = 0;
1758
1759         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1760                 return -EOPNOTSUPP;
1761
1762         if (lock_needed)
1763                 mutex_lock(&smu->mutex);
1764
1765         switch (task_id) {
1766         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1767                 ret = smu_pre_display_config_changed(smu);
1768                 if (ret)
1769                         goto out;
1770                 ret = smu_set_cpu_power_state(smu);
1771                 if (ret)
1772                         goto out;
1773                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1774                 break;
1775         case AMD_PP_TASK_COMPLETE_INIT:
1776         case AMD_PP_TASK_READJUST_POWER_STATE:
1777                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1778                 break;
1779         default:
1780                 break;
1781         }
1782
1783 out:
1784         if (lock_needed)
1785                 mutex_unlock(&smu->mutex);
1786
1787         return ret;
1788 }
1789
1790 int smu_switch_power_profile(struct smu_context *smu,
1791                              enum PP_SMC_POWER_PROFILE type,
1792                              bool en)
1793 {
1794         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1795         long workload;
1796         uint32_t index;
1797
1798         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1799                 return -EOPNOTSUPP;
1800
1801         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1802                 return -EINVAL;
1803
1804         mutex_lock(&smu->mutex);
1805
1806         if (!en) {
1807                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1808                 index = fls(smu->workload_mask);
1809                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1810                 workload = smu->workload_setting[index];
1811         } else {
1812                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1813                 index = fls(smu->workload_mask);
1814                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1815                 workload = smu->workload_setting[index];
1816         }
1817
1818         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1819                 smu_set_power_profile_mode(smu, &workload, 0, false);
1820
1821         mutex_unlock(&smu->mutex);
1822
1823         return 0;
1824 }
1825
1826 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1827 {
1828         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1829         enum amd_dpm_forced_level level;
1830
1831         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1832                 return -EOPNOTSUPP;
1833
1834         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1835                 return -EINVAL;
1836
1837         mutex_lock(&(smu->mutex));
1838         level = smu_dpm_ctx->dpm_level;
1839         mutex_unlock(&(smu->mutex));
1840
1841         return level;
1842 }
1843
1844 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1845 {
1846         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1847         int ret = 0;
1848
1849         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1850                 return -EOPNOTSUPP;
1851
1852         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1853                 return -EINVAL;
1854
1855         mutex_lock(&smu->mutex);
1856
1857         ret = smu_enable_umd_pstate(smu, &level);
1858         if (ret) {
1859                 mutex_unlock(&smu->mutex);
1860                 return ret;
1861         }
1862
1863         ret = smu_handle_task(smu, level,
1864                               AMD_PP_TASK_READJUST_POWER_STATE,
1865                               false);
1866
1867         mutex_unlock(&smu->mutex);
1868
1869         return ret;
1870 }
1871
1872 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1873 {
1874         int ret = 0;
1875
1876         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1877                 return -EOPNOTSUPP;
1878
1879         mutex_lock(&smu->mutex);
1880         ret = smu_init_display_count(smu, count);
1881         mutex_unlock(&smu->mutex);
1882
1883         return ret;
1884 }
1885
1886 int smu_force_clk_levels(struct smu_context *smu,
1887                          enum smu_clk_type clk_type,
1888                          uint32_t mask,
1889                          bool lock_needed)
1890 {
1891         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1892         int ret = 0;
1893
1894         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1895                 return -EOPNOTSUPP;
1896
1897         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1898                 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1899                 return -EINVAL;
1900         }
1901
1902         if (lock_needed)
1903                 mutex_lock(&smu->mutex);
1904
1905         if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
1906                 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1907
1908         if (lock_needed)
1909                 mutex_unlock(&smu->mutex);
1910
1911         return ret;
1912 }
1913
1914 /*
1915  * On system suspending or resetting, the dpm_enabled
1916  * flag will be cleared. So that those SMU services which
1917  * are not supported will be gated.
1918  * However, the mp1 state setting should still be granted
1919  * even if the dpm_enabled cleared.
1920  */
1921 int smu_set_mp1_state(struct smu_context *smu,
1922                       enum pp_mp1_state mp1_state)
1923 {
1924         uint16_t msg;
1925         int ret;
1926
1927         if (!smu->pm_enabled)
1928                 return -EOPNOTSUPP;
1929
1930         mutex_lock(&smu->mutex);
1931
1932         switch (mp1_state) {
1933         case PP_MP1_STATE_SHUTDOWN:
1934                 msg = SMU_MSG_PrepareMp1ForShutdown;
1935                 break;
1936         case PP_MP1_STATE_UNLOAD:
1937                 msg = SMU_MSG_PrepareMp1ForUnload;
1938                 break;
1939         case PP_MP1_STATE_RESET:
1940                 msg = SMU_MSG_PrepareMp1ForReset;
1941                 break;
1942         case PP_MP1_STATE_NONE:
1943         default:
1944                 mutex_unlock(&smu->mutex);
1945                 return 0;
1946         }
1947
1948         /* some asics may not support those messages */
1949         if (smu_msg_get_index(smu, msg) < 0) {
1950                 mutex_unlock(&smu->mutex);
1951                 return 0;
1952         }
1953
1954         ret = smu_send_smc_msg(smu, msg, NULL);
1955         if (ret)
1956                 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
1957
1958         mutex_unlock(&smu->mutex);
1959
1960         return ret;
1961 }
1962
1963 int smu_set_df_cstate(struct smu_context *smu,
1964                       enum pp_df_cstate state)
1965 {
1966         int ret = 0;
1967
1968         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1969                 return -EOPNOTSUPP;
1970
1971         if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1972                 return 0;
1973
1974         mutex_lock(&smu->mutex);
1975
1976         ret = smu->ppt_funcs->set_df_cstate(smu, state);
1977         if (ret)
1978                 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
1979
1980         mutex_unlock(&smu->mutex);
1981
1982         return ret;
1983 }
1984
1985 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
1986 {
1987         int ret = 0;
1988
1989         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1990                 return -EOPNOTSUPP;
1991
1992         if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
1993                 return 0;
1994
1995         mutex_lock(&smu->mutex);
1996
1997         ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
1998         if (ret)
1999                 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
2000
2001         mutex_unlock(&smu->mutex);
2002
2003         return ret;
2004 }
2005
2006 int smu_write_watermarks_table(struct smu_context *smu)
2007 {
2008         void *watermarks_table = smu->smu_table.watermarks_table;
2009
2010         if (!watermarks_table)
2011                 return -EINVAL;
2012
2013         return smu_update_table(smu,
2014                                 SMU_TABLE_WATERMARKS,
2015                                 0,
2016                                 watermarks_table,
2017                                 true);
2018 }
2019
2020 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
2021                 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
2022 {
2023         void *table = smu->smu_table.watermarks_table;
2024
2025         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2026                 return -EOPNOTSUPP;
2027
2028         if (!table)
2029                 return -EINVAL;
2030
2031         mutex_lock(&smu->mutex);
2032
2033         if (!smu->disable_watermark &&
2034                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
2035                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
2036                 smu_set_watermarks_table(smu, table, clock_ranges);
2037
2038                 if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
2039                         smu->watermarks_bitmap |= WATERMARKS_EXIST;
2040                         smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
2041                 }
2042         }
2043
2044         mutex_unlock(&smu->mutex);
2045
2046         return 0;
2047 }
2048
2049 int smu_set_ac_dc(struct smu_context *smu)
2050 {
2051         int ret = 0;
2052
2053         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2054                 return -EOPNOTSUPP;
2055
2056         /* controlled by firmware */
2057         if (smu->dc_controlled_by_gpio)
2058                 return 0;
2059
2060         mutex_lock(&smu->mutex);
2061         ret = smu_set_power_source(smu,
2062                                    smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
2063                                    SMU_POWER_SOURCE_DC);
2064         if (ret)
2065                 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
2066                        smu->adev->pm.ac_power ? "AC" : "DC");
2067         mutex_unlock(&smu->mutex);
2068
2069         return ret;
2070 }
2071
2072 const struct amd_ip_funcs smu_ip_funcs = {
2073         .name = "smu",
2074         .early_init = smu_early_init,
2075         .late_init = smu_late_init,
2076         .sw_init = smu_sw_init,
2077         .sw_fini = smu_sw_fini,
2078         .hw_init = smu_hw_init,
2079         .hw_fini = smu_hw_fini,
2080         .suspend = smu_suspend,
2081         .resume = smu_resume,
2082         .is_idle = NULL,
2083         .check_soft_reset = NULL,
2084         .wait_for_idle = NULL,
2085         .soft_reset = NULL,
2086         .set_clockgating_state = smu_set_clockgating_state,
2087         .set_powergating_state = smu_set_powergating_state,
2088         .enable_umd_pstate = smu_enable_umd_pstate,
2089 };
2090
2091 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
2092 {
2093         .type = AMD_IP_BLOCK_TYPE_SMC,
2094         .major = 11,
2095         .minor = 0,
2096         .rev = 0,
2097         .funcs = &smu_ip_funcs,
2098 };
2099
2100 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
2101 {
2102         .type = AMD_IP_BLOCK_TYPE_SMC,
2103         .major = 12,
2104         .minor = 0,
2105         .rev = 0,
2106         .funcs = &smu_ip_funcs,
2107 };
2108
2109 int smu_load_microcode(struct smu_context *smu)
2110 {
2111         int ret = 0;
2112
2113         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2114                 return -EOPNOTSUPP;
2115
2116         mutex_lock(&smu->mutex);
2117
2118         if (smu->ppt_funcs->load_microcode)
2119                 ret = smu->ppt_funcs->load_microcode(smu);
2120
2121         mutex_unlock(&smu->mutex);
2122
2123         return ret;
2124 }
2125
2126 int smu_check_fw_status(struct smu_context *smu)
2127 {
2128         int ret = 0;
2129
2130         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2131                 return -EOPNOTSUPP;
2132
2133         mutex_lock(&smu->mutex);
2134
2135         if (smu->ppt_funcs->check_fw_status)
2136                 ret = smu->ppt_funcs->check_fw_status(smu);
2137
2138         mutex_unlock(&smu->mutex);
2139
2140         return ret;
2141 }
2142
2143 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2144 {
2145         int ret = 0;
2146
2147         mutex_lock(&smu->mutex);
2148
2149         if (smu->ppt_funcs->set_gfx_cgpg)
2150                 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2151
2152         mutex_unlock(&smu->mutex);
2153
2154         return ret;
2155 }
2156
2157 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
2158 {
2159         int ret = 0;
2160
2161         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2162                 return -EOPNOTSUPP;
2163
2164         mutex_lock(&smu->mutex);
2165
2166         if (smu->ppt_funcs->set_fan_speed_rpm)
2167                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2168
2169         mutex_unlock(&smu->mutex);
2170
2171         return ret;
2172 }
2173
2174 int smu_get_power_limit(struct smu_context *smu,
2175                         uint32_t *limit,
2176                         bool max_setting)
2177 {
2178         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2179                 return -EOPNOTSUPP;
2180
2181         mutex_lock(&smu->mutex);
2182
2183         *limit = (max_setting ? smu->max_power_limit : smu->current_power_limit);
2184
2185         mutex_unlock(&smu->mutex);
2186
2187         return 0;
2188 }
2189
2190 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
2191 {
2192         int ret = 0;
2193
2194         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2195                 return -EOPNOTSUPP;
2196
2197         mutex_lock(&smu->mutex);
2198
2199         if (limit > smu->max_power_limit) {
2200                 dev_err(smu->adev->dev,
2201                         "New power limit (%d) is over the max allowed %d\n",
2202                         limit, smu->max_power_limit);
2203                 goto out;
2204         }
2205
2206         if (!limit)
2207                 limit = smu->current_power_limit;
2208
2209         if (smu->ppt_funcs->set_power_limit)
2210                 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2211
2212 out:
2213         mutex_unlock(&smu->mutex);
2214
2215         return ret;
2216 }
2217
2218 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2219 {
2220         int ret = 0;
2221
2222         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2223                 return -EOPNOTSUPP;
2224
2225         mutex_lock(&smu->mutex);
2226
2227         if (smu->ppt_funcs->print_clk_levels)
2228                 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2229
2230         mutex_unlock(&smu->mutex);
2231
2232         return ret;
2233 }
2234
2235 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
2236 {
2237         int ret = 0;
2238
2239         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2240                 return -EOPNOTSUPP;
2241
2242         mutex_lock(&smu->mutex);
2243
2244         if (smu->ppt_funcs->get_od_percentage)
2245                 ret = smu->ppt_funcs->get_od_percentage(smu, type);
2246
2247         mutex_unlock(&smu->mutex);
2248
2249         return ret;
2250 }
2251
2252 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
2253 {
2254         int ret = 0;
2255
2256         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2257                 return -EOPNOTSUPP;
2258
2259         mutex_lock(&smu->mutex);
2260
2261         if (smu->ppt_funcs->set_od_percentage)
2262                 ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
2263
2264         mutex_unlock(&smu->mutex);
2265
2266         return ret;
2267 }
2268
2269 int smu_od_edit_dpm_table(struct smu_context *smu,
2270                           enum PP_OD_DPM_TABLE_COMMAND type,
2271                           long *input, uint32_t size)
2272 {
2273         int ret = 0;
2274
2275         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2276                 return -EOPNOTSUPP;
2277
2278         mutex_lock(&smu->mutex);
2279
2280         if (smu->ppt_funcs->od_edit_dpm_table)
2281                 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2282
2283         mutex_unlock(&smu->mutex);
2284
2285         return ret;
2286 }
2287
2288 int smu_read_sensor(struct smu_context *smu,
2289                     enum amd_pp_sensors sensor,
2290                     void *data, uint32_t *size)
2291 {
2292         int ret = 0;
2293
2294         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2295                 return -EOPNOTSUPP;
2296
2297         if (!data || !size)
2298                 return -EINVAL;
2299
2300         mutex_lock(&smu->mutex);
2301
2302         switch (sensor) {
2303         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2304                 *((uint32_t *)data) = smu->pstate_sclk;
2305                 *size = 4;
2306                 break;
2307         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2308                 *((uint32_t *)data) = smu->pstate_mclk;
2309                 *size = 4;
2310                 break;
2311         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2312                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
2313                 *size = 8;
2314                 break;
2315         case AMDGPU_PP_SENSOR_UVD_POWER:
2316                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2317                 *size = 4;
2318                 break;
2319         case AMDGPU_PP_SENSOR_VCE_POWER:
2320                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2321                 *size = 4;
2322                 break;
2323         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2324                 *(uint32_t *)data = smu->smu_power.power_gate.vcn_gated ? 0 : 1;
2325                 *size = 4;
2326                 break;
2327         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2328                 *(uint32_t *)data = 0;
2329                 *size = 4;
2330                 break;
2331         default:
2332                 if (smu->ppt_funcs->read_sensor)
2333                         ret = smu->ppt_funcs->read_sensor(smu, sensor, data, size);
2334                 break;
2335         }
2336
2337         mutex_unlock(&smu->mutex);
2338
2339         return ret;
2340 }
2341
2342 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2343 {
2344         int ret = 0;
2345
2346         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2347                 return -EOPNOTSUPP;
2348
2349         mutex_lock(&smu->mutex);
2350
2351         if (smu->ppt_funcs->get_power_profile_mode)
2352                 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2353
2354         mutex_unlock(&smu->mutex);
2355
2356         return ret;
2357 }
2358
2359 int smu_set_power_profile_mode(struct smu_context *smu,
2360                                long *param,
2361                                uint32_t param_size,
2362                                bool lock_needed)
2363 {
2364         int ret = 0;
2365
2366         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2367                 return -EOPNOTSUPP;
2368
2369         if (lock_needed)
2370                 mutex_lock(&smu->mutex);
2371
2372         if (smu->ppt_funcs->set_power_profile_mode)
2373                 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2374
2375         if (lock_needed)
2376                 mutex_unlock(&smu->mutex);
2377
2378         return ret;
2379 }
2380
2381
2382 int smu_get_fan_control_mode(struct smu_context *smu)
2383 {
2384         int ret = 0;
2385
2386         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2387                 return -EOPNOTSUPP;
2388
2389         mutex_lock(&smu->mutex);
2390
2391         if (smu->ppt_funcs->get_fan_control_mode)
2392                 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2393
2394         mutex_unlock(&smu->mutex);
2395
2396         return ret;
2397 }
2398
2399 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2400 {
2401         int ret = 0;
2402
2403         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2404                 return -EOPNOTSUPP;
2405
2406         mutex_lock(&smu->mutex);
2407
2408         if (smu->ppt_funcs->set_fan_control_mode)
2409                 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2410
2411         mutex_unlock(&smu->mutex);
2412
2413         return ret;
2414 }
2415
2416 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2417 {
2418         int ret = 0;
2419
2420         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2421                 return -EOPNOTSUPP;
2422
2423         mutex_lock(&smu->mutex);
2424
2425         if (smu->ppt_funcs->get_fan_speed_percent)
2426                 ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
2427
2428         mutex_unlock(&smu->mutex);
2429
2430         return ret;
2431 }
2432
2433 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2434 {
2435         int ret = 0;
2436
2437         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2438                 return -EOPNOTSUPP;
2439
2440         mutex_lock(&smu->mutex);
2441
2442         if (smu->ppt_funcs->set_fan_speed_percent)
2443                 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
2444
2445         mutex_unlock(&smu->mutex);
2446
2447         return ret;
2448 }
2449
2450 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2451 {
2452         int ret = 0;
2453
2454         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2455                 return -EOPNOTSUPP;
2456
2457         mutex_lock(&smu->mutex);
2458
2459         if (smu->ppt_funcs->get_fan_speed_rpm)
2460                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2461
2462         mutex_unlock(&smu->mutex);
2463
2464         return ret;
2465 }
2466
2467 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2468 {
2469         int ret = 0;
2470
2471         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2472                 return -EOPNOTSUPP;
2473
2474         mutex_lock(&smu->mutex);
2475
2476         ret = smu_set_min_dcef_deep_sleep(smu, clk);
2477
2478         mutex_unlock(&smu->mutex);
2479
2480         return ret;
2481 }
2482
2483 int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
2484 {
2485         int ret = 0;
2486
2487         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2488                 return -EOPNOTSUPP;
2489
2490         if (smu->ppt_funcs->set_active_display_count)
2491                 ret = smu->ppt_funcs->set_active_display_count(smu, count);
2492
2493         return ret;
2494 }
2495
2496 int smu_get_clock_by_type(struct smu_context *smu,
2497                           enum amd_pp_clock_type type,
2498                           struct amd_pp_clocks *clocks)
2499 {
2500         int ret = 0;
2501
2502         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2503                 return -EOPNOTSUPP;
2504
2505         mutex_lock(&smu->mutex);
2506
2507         if (smu->ppt_funcs->get_clock_by_type)
2508                 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
2509
2510         mutex_unlock(&smu->mutex);
2511
2512         return ret;
2513 }
2514
2515 int smu_get_max_high_clocks(struct smu_context *smu,
2516                             struct amd_pp_simple_clock_info *clocks)
2517 {
2518         int ret = 0;
2519
2520         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2521                 return -EOPNOTSUPP;
2522
2523         mutex_lock(&smu->mutex);
2524
2525         if (smu->ppt_funcs->get_max_high_clocks)
2526                 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
2527
2528         mutex_unlock(&smu->mutex);
2529
2530         return ret;
2531 }
2532
2533 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2534                                        enum smu_clk_type clk_type,
2535                                        struct pp_clock_levels_with_latency *clocks)
2536 {
2537         int ret = 0;
2538
2539         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2540                 return -EOPNOTSUPP;
2541
2542         mutex_lock(&smu->mutex);
2543
2544         if (smu->ppt_funcs->get_clock_by_type_with_latency)
2545                 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2546
2547         mutex_unlock(&smu->mutex);
2548
2549         return ret;
2550 }
2551
2552 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
2553                                        enum amd_pp_clock_type type,
2554                                        struct pp_clock_levels_with_voltage *clocks)
2555 {
2556         int ret = 0;
2557
2558         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2559                 return -EOPNOTSUPP;
2560
2561         mutex_lock(&smu->mutex);
2562
2563         if (smu->ppt_funcs->get_clock_by_type_with_voltage)
2564                 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
2565
2566         mutex_unlock(&smu->mutex);
2567
2568         return ret;
2569 }
2570
2571
2572 int smu_display_clock_voltage_request(struct smu_context *smu,
2573                                       struct pp_display_clock_request *clock_req)
2574 {
2575         int ret = 0;
2576
2577         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2578                 return -EOPNOTSUPP;
2579
2580         mutex_lock(&smu->mutex);
2581
2582         if (smu->ppt_funcs->display_clock_voltage_request)
2583                 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2584
2585         mutex_unlock(&smu->mutex);
2586
2587         return ret;
2588 }
2589
2590
2591 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2592 {
2593         int ret = -EINVAL;
2594
2595         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2596                 return -EOPNOTSUPP;
2597
2598         mutex_lock(&smu->mutex);
2599
2600         if (smu->ppt_funcs->display_disable_memory_clock_switch)
2601                 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2602
2603         mutex_unlock(&smu->mutex);
2604
2605         return ret;
2606 }
2607
2608 int smu_notify_smu_enable_pwe(struct smu_context *smu)
2609 {
2610         int ret = 0;
2611
2612         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2613                 return -EOPNOTSUPP;
2614
2615         mutex_lock(&smu->mutex);
2616
2617         if (smu->ppt_funcs->notify_smu_enable_pwe)
2618                 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
2619
2620         mutex_unlock(&smu->mutex);
2621
2622         return ret;
2623 }
2624
2625 int smu_set_xgmi_pstate(struct smu_context *smu,
2626                         uint32_t pstate)
2627 {
2628         int ret = 0;
2629
2630         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2631                 return -EOPNOTSUPP;
2632
2633         mutex_lock(&smu->mutex);
2634
2635         if (smu->ppt_funcs->set_xgmi_pstate)
2636                 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2637
2638         mutex_unlock(&smu->mutex);
2639
2640         if(ret)
2641                 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2642
2643         return ret;
2644 }
2645
2646 int smu_set_azalia_d3_pme(struct smu_context *smu)
2647 {
2648         int ret = 0;
2649
2650         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2651                 return -EOPNOTSUPP;
2652
2653         mutex_lock(&smu->mutex);
2654
2655         if (smu->ppt_funcs->set_azalia_d3_pme)
2656                 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2657
2658         mutex_unlock(&smu->mutex);
2659
2660         return ret;
2661 }
2662
2663 /*
2664  * On system suspending or resetting, the dpm_enabled
2665  * flag will be cleared. So that those SMU services which
2666  * are not supported will be gated.
2667  *
2668  * However, the baco/mode1 reset should still be granted
2669  * as they are still supported and necessary.
2670  */
2671 bool smu_baco_is_support(struct smu_context *smu)
2672 {
2673         bool ret = false;
2674
2675         if (!smu->pm_enabled)
2676                 return false;
2677
2678         mutex_lock(&smu->mutex);
2679
2680         if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2681                 ret = smu->ppt_funcs->baco_is_support(smu);
2682
2683         mutex_unlock(&smu->mutex);
2684
2685         return ret;
2686 }
2687
2688 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2689 {
2690         if (smu->ppt_funcs->baco_get_state)
2691                 return -EINVAL;
2692
2693         mutex_lock(&smu->mutex);
2694         *state = smu->ppt_funcs->baco_get_state(smu);
2695         mutex_unlock(&smu->mutex);
2696
2697         return 0;
2698 }
2699
2700 int smu_baco_enter(struct smu_context *smu)
2701 {
2702         int ret = 0;
2703
2704         if (!smu->pm_enabled)
2705                 return -EOPNOTSUPP;
2706
2707         mutex_lock(&smu->mutex);
2708
2709         if (smu->ppt_funcs->baco_enter)
2710                 ret = smu->ppt_funcs->baco_enter(smu);
2711
2712         mutex_unlock(&smu->mutex);
2713
2714         if (ret)
2715                 dev_err(smu->adev->dev, "Failed to enter BACO state!\n");
2716
2717         return ret;
2718 }
2719
2720 int smu_baco_exit(struct smu_context *smu)
2721 {
2722         int ret = 0;
2723
2724         if (!smu->pm_enabled)
2725                 return -EOPNOTSUPP;
2726
2727         mutex_lock(&smu->mutex);
2728
2729         if (smu->ppt_funcs->baco_exit)
2730                 ret = smu->ppt_funcs->baco_exit(smu);
2731
2732         mutex_unlock(&smu->mutex);
2733
2734         if (ret)
2735                 dev_err(smu->adev->dev, "Failed to exit BACO state!\n");
2736
2737         return ret;
2738 }
2739
2740 int smu_mode2_reset(struct smu_context *smu)
2741 {
2742         int ret = 0;
2743
2744         if (!smu->pm_enabled)
2745                 return -EOPNOTSUPP;
2746
2747         mutex_lock(&smu->mutex);
2748
2749         if (smu->ppt_funcs->mode2_reset)
2750                 ret = smu->ppt_funcs->mode2_reset(smu);
2751
2752         mutex_unlock(&smu->mutex);
2753
2754         if (ret)
2755                 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2756
2757         return ret;
2758 }
2759
2760 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2761                                          struct pp_smu_nv_clock_table *max_clocks)
2762 {
2763         int ret = 0;
2764
2765         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2766                 return -EOPNOTSUPP;
2767
2768         mutex_lock(&smu->mutex);
2769
2770         if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2771                 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2772
2773         mutex_unlock(&smu->mutex);
2774
2775         return ret;
2776 }
2777
2778 int smu_get_uclk_dpm_states(struct smu_context *smu,
2779                             unsigned int *clock_values_in_khz,
2780                             unsigned int *num_states)
2781 {
2782         int ret = 0;
2783
2784         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2785                 return -EOPNOTSUPP;
2786
2787         mutex_lock(&smu->mutex);
2788
2789         if (smu->ppt_funcs->get_uclk_dpm_states)
2790                 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2791
2792         mutex_unlock(&smu->mutex);
2793
2794         return ret;
2795 }
2796
2797 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2798 {
2799         enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2800
2801         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2802                 return -EOPNOTSUPP;
2803
2804         mutex_lock(&smu->mutex);
2805
2806         if (smu->ppt_funcs->get_current_power_state)
2807                 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2808
2809         mutex_unlock(&smu->mutex);
2810
2811         return pm_state;
2812 }
2813
2814 int smu_get_dpm_clock_table(struct smu_context *smu,
2815                             struct dpm_clocks *clock_table)
2816 {
2817         int ret = 0;
2818
2819         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2820                 return -EOPNOTSUPP;
2821
2822         mutex_lock(&smu->mutex);
2823
2824         if (smu->ppt_funcs->get_dpm_clock_table)
2825                 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2826
2827         mutex_unlock(&smu->mutex);
2828
2829         return ret;
2830 }