2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/pci.h>
27 #include "amdgpu_smu.h"
28 #include "smu_internal.h"
29 #include "smu_v11_0.h"
30 #include "smu_v12_0.h"
32 #include "arcturus_ppt.h"
33 #include "navi10_ppt.h"
34 #include "sienna_cichlid_ppt.h"
35 #include "renoir_ppt.h"
37 #undef __SMU_DUMMY_MAP
38 #define __SMU_DUMMY_MAP(type) #type
39 static const char* __smu_message_names[] = {
43 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
45 if (type < 0 || type >= SMU_MSG_MAX_COUNT)
46 return "unknown smu message";
47 return __smu_message_names[type];
50 #undef __SMU_DUMMY_MAP
51 #define __SMU_DUMMY_MAP(fea) #fea
52 static const char* __smu_feature_names[] = {
56 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
58 if (feature < 0 || feature >= SMU_FEATURE_COUNT)
59 return "unknown smu feature";
60 return __smu_feature_names[feature];
63 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
67 uint32_t feature_mask[2] = { 0 };
68 int32_t feature_index = 0;
70 uint32_t sort_feature[SMU_FEATURE_COUNT];
71 uint64_t hw_feature_count = 0;
73 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
76 mutex_lock(&smu->mutex);
78 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
82 size = sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
83 feature_mask[1], feature_mask[0]);
85 for (i = 0; i < SMU_FEATURE_COUNT; i++) {
86 feature_index = smu_feature_get_index(smu, i);
87 if (feature_index < 0)
89 sort_feature[feature_index] = i;
93 for (i = 0; i < hw_feature_count; i++) {
94 size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
96 smu_get_feature_name(smu, sort_feature[i]),
98 !!smu_feature_is_enabled(smu, sort_feature[i]) ?
99 "enabled" : "disabled");
103 mutex_unlock(&smu->mutex);
108 static int smu_feature_update_enable_state(struct smu_context *smu,
109 uint64_t feature_mask,
112 struct smu_feature *feature = &smu->smu_feature;
113 uint32_t feature_low = 0, feature_high = 0;
116 feature_low = (feature_mask >> 0 ) & 0xffffffff;
117 feature_high = (feature_mask >> 32) & 0xffffffff;
120 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
124 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
129 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
133 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
139 mutex_lock(&feature->mutex);
141 bitmap_or(feature->enabled, feature->enabled,
142 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
144 bitmap_andnot(feature->enabled, feature->enabled,
145 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
146 mutex_unlock(&feature->mutex);
151 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
154 uint32_t feature_mask[2] = { 0 };
155 uint64_t feature_2_enabled = 0;
156 uint64_t feature_2_disabled = 0;
157 uint64_t feature_enables = 0;
159 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
162 mutex_lock(&smu->mutex);
164 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
168 feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
170 feature_2_enabled = ~feature_enables & new_mask;
171 feature_2_disabled = feature_enables & ~new_mask;
173 if (feature_2_enabled) {
174 ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
178 if (feature_2_disabled) {
179 ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
185 mutex_unlock(&smu->mutex);
190 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
194 if (!if_version && !smu_version)
197 if (smu->smc_fw_if_version && smu->smc_fw_version)
200 *if_version = smu->smc_fw_if_version;
203 *smu_version = smu->smc_fw_version;
209 ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion, if_version);
213 smu->smc_fw_if_version = *if_version;
217 ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion, smu_version);
221 smu->smc_fw_version = *smu_version;
227 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
228 uint32_t min, uint32_t max, bool lock_needed)
232 if (!smu_clk_dpm_is_enabled(smu, clk_type))
236 mutex_lock(&smu->mutex);
237 ret = smu_set_soft_freq_limited_range(smu, clk_type, min, max);
239 mutex_unlock(&smu->mutex);
244 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
245 uint32_t min, uint32_t max)
247 int ret = 0, clk_id = 0;
250 if (min <= 0 && max <= 0)
253 if (!smu_clk_dpm_is_enabled(smu, clk_type))
256 clk_id = smu_clk_get_index(smu, clk_type);
261 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
262 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
269 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
270 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
280 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
281 uint32_t *min, uint32_t *max, bool lock_needed)
283 uint32_t clock_limit;
290 mutex_lock(&smu->mutex);
292 if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
296 clock_limit = smu->smu_table.boot_values.uclk;
300 clock_limit = smu->smu_table.boot_values.gfxclk;
303 clock_limit = smu->smu_table.boot_values.socclk;
310 /* clock in Mhz unit */
312 *min = clock_limit / 100;
314 *max = clock_limit / 100;
317 * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
318 * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
320 ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
324 mutex_unlock(&smu->mutex);
329 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
330 uint16_t level, uint32_t *value)
332 int ret = 0, clk_id = 0;
338 if (!smu_clk_dpm_is_enabled(smu, clk_type))
341 clk_id = smu_clk_get_index(smu, clk_type);
345 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
347 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmFreqByIndex,
352 /* BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
353 * now, we un-support it */
354 *value = *value & 0x7fffffff;
359 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
362 return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
365 int smu_get_dpm_level_range(struct smu_context *smu, enum smu_clk_type clk_type,
366 uint32_t *min_value, uint32_t *max_value)
369 uint32_t level_count = 0;
371 if (!min_value && !max_value)
375 /* by default, level 0 clock value as min value */
376 ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, min_value);
382 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
386 ret = smu_get_dpm_freq_by_index(smu, clk_type, level_count - 1, max_value);
394 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
396 enum smu_feature_mask feature_id = 0;
401 feature_id = SMU_FEATURE_DPM_UCLK_BIT;
405 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
408 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
414 if(!smu_feature_is_enabled(smu, feature_id)) {
422 * smu_dpm_set_power_gate - power gate/ungate the specific IP block
424 * @smu: smu_context pointer
425 * @block_type: the IP block to power gate/ungate
426 * @gate: to power gate if true, ungate otherwise
428 * This API uses no smu->mutex lock protection due to:
429 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
430 * This is guarded to be race condition free by the caller.
431 * 2. Or get called on user setting request of power_dpm_force_performance_level.
432 * Under this case, the smu->mutex lock protection is already enforced on
433 * the parent API smu_force_performance_level of the call path.
435 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
440 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
443 switch (block_type) {
444 case AMD_IP_BLOCK_TYPE_UVD:
445 ret = smu_dpm_set_uvd_enable(smu, !gate);
447 case AMD_IP_BLOCK_TYPE_VCE:
448 ret = smu_dpm_set_vce_enable(smu, !gate);
450 case AMD_IP_BLOCK_TYPE_GFX:
451 ret = smu_gfx_off_control(smu, gate);
453 case AMD_IP_BLOCK_TYPE_SDMA:
454 ret = smu_powergate_sdma(smu, gate);
456 case AMD_IP_BLOCK_TYPE_JPEG:
457 ret = smu_dpm_set_jpeg_enable(smu, !gate);
466 int smu_get_power_num_states(struct smu_context *smu,
467 struct pp_states_info *state_info)
472 /* not support power state */
473 memset(state_info, 0, sizeof(struct pp_states_info));
474 state_info->nums = 1;
475 state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
480 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
481 void *data, uint32_t *size)
483 struct smu_power_context *smu_power = &smu->smu_power;
484 struct smu_power_gate *power_gate = &smu_power->power_gate;
491 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
492 *((uint32_t *)data) = smu->pstate_sclk;
495 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
496 *((uint32_t *)data) = smu->pstate_mclk;
499 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
500 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
503 case AMDGPU_PP_SENSOR_UVD_POWER:
504 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
507 case AMDGPU_PP_SENSOR_VCE_POWER:
508 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
511 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
512 *(uint32_t *)data = power_gate->vcn_gated ? 0 : 1;
526 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
527 void *table_data, bool drv2smu)
529 struct smu_table_context *smu_table = &smu->smu_table;
530 struct amdgpu_device *adev = smu->adev;
531 struct smu_table *table = &smu_table->driver_table;
532 int table_id = smu_table_get_index(smu, table_index);
535 if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0)
538 table_size = smu_table->tables[table_index].size;
541 memcpy(table->cpu_addr, table_data, table_size);
543 * Flush hdp cache: to guard the content seen by
544 * GPU is consitent with CPU.
546 amdgpu_asic_flush_hdp(adev, NULL);
549 ret = smu_send_smc_msg_with_param(smu, drv2smu ?
550 SMU_MSG_TransferTableDram2Smu :
551 SMU_MSG_TransferTableSmu2Dram,
552 table_id | ((argument & 0xFFFF) << 16),
558 amdgpu_asic_flush_hdp(adev, NULL);
559 memcpy(table_data, table->cpu_addr, table_size);
565 bool is_support_sw_smu(struct amdgpu_device *adev)
567 if (adev->asic_type >= CHIP_ARCTURUS)
573 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
575 struct smu_table_context *smu_table = &smu->smu_table;
576 uint32_t powerplay_table_size;
578 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
581 if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
584 mutex_lock(&smu->mutex);
586 if (smu_table->hardcode_pptable)
587 *table = smu_table->hardcode_pptable;
589 *table = smu_table->power_play_table;
591 powerplay_table_size = smu_table->power_play_table_size;
593 mutex_unlock(&smu->mutex);
595 return powerplay_table_size;
598 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
600 struct smu_table_context *smu_table = &smu->smu_table;
601 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
604 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
607 if (header->usStructureSize != size) {
608 pr_err("pp table size not matched !\n");
612 mutex_lock(&smu->mutex);
613 if (!smu_table->hardcode_pptable)
614 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
615 if (!smu_table->hardcode_pptable) {
620 memcpy(smu_table->hardcode_pptable, buf, size);
621 smu_table->power_play_table = smu_table->hardcode_pptable;
622 smu_table->power_play_table_size = size;
625 * Special hw_fini action(for Navi1x, the DPMs disablement will be
626 * skipped) may be needed for custom pptable uploading.
628 smu->uploading_custom_pp_table = true;
630 ret = smu_reset(smu);
632 pr_info("smu reset failed, ret = %d\n", ret);
634 smu->uploading_custom_pp_table = false;
637 mutex_unlock(&smu->mutex);
641 int smu_feature_init_dpm(struct smu_context *smu)
643 struct smu_feature *feature = &smu->smu_feature;
645 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
647 mutex_lock(&feature->mutex);
648 bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
649 mutex_unlock(&feature->mutex);
651 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
656 mutex_lock(&feature->mutex);
657 bitmap_or(feature->allowed, feature->allowed,
658 (unsigned long *)allowed_feature_mask,
659 feature->feature_num);
660 mutex_unlock(&feature->mutex);
666 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
668 struct smu_feature *feature = &smu->smu_feature;
674 feature_id = smu_feature_get_index(smu, mask);
678 WARN_ON(feature_id > feature->feature_num);
680 mutex_lock(&feature->mutex);
681 ret = test_bit(feature_id, feature->enabled);
682 mutex_unlock(&feature->mutex);
687 int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
690 struct smu_feature *feature = &smu->smu_feature;
693 feature_id = smu_feature_get_index(smu, mask);
697 WARN_ON(feature_id > feature->feature_num);
699 return smu_feature_update_enable_state(smu,
704 int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
706 struct smu_feature *feature = &smu->smu_feature;
710 feature_id = smu_feature_get_index(smu, mask);
714 WARN_ON(feature_id > feature->feature_num);
716 mutex_lock(&feature->mutex);
717 ret = test_bit(feature_id, feature->supported);
718 mutex_unlock(&feature->mutex);
723 static int smu_set_funcs(struct amdgpu_device *adev)
725 struct smu_context *smu = &adev->smu;
727 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
728 smu->od_enabled = true;
730 switch (adev->asic_type) {
734 navi10_set_ppt_funcs(smu);
737 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
738 arcturus_set_ppt_funcs(smu);
739 /* OD is not supported on Arcturus */
740 smu->od_enabled =false;
742 case CHIP_SIENNA_CICHLID:
743 sienna_cichlid_set_ppt_funcs(smu);
746 renoir_set_ppt_funcs(smu);
755 static int smu_early_init(void *handle)
757 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
758 struct smu_context *smu = &adev->smu;
761 smu->pm_enabled = !!amdgpu_dpm;
763 mutex_init(&smu->mutex);
765 return smu_set_funcs(adev);
768 static int smu_late_init(void *handle)
770 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
771 struct smu_context *smu = &adev->smu;
773 if (!smu->pm_enabled)
776 smu_get_unique_id(smu);
778 smu_handle_task(&adev->smu,
779 smu->smu_dpm.dpm_level,
780 AMD_PP_TASK_COMPLETE_INIT,
786 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
787 uint16_t *size, uint8_t *frev, uint8_t *crev,
790 struct amdgpu_device *adev = smu->adev;
793 if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
794 size, frev, crev, &data_start))
797 *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
802 static int smu_init_fb_allocations(struct smu_context *smu)
804 struct amdgpu_device *adev = smu->adev;
805 struct smu_table_context *smu_table = &smu->smu_table;
806 struct smu_table *tables = smu_table->tables;
807 struct smu_table *driver_table = &(smu_table->driver_table);
808 uint32_t max_table_size = 0;
811 /* VRAM allocation for tool table */
812 if (tables[SMU_TABLE_PMSTATUSLOG].size) {
813 ret = amdgpu_bo_create_kernel(adev,
814 tables[SMU_TABLE_PMSTATUSLOG].size,
815 tables[SMU_TABLE_PMSTATUSLOG].align,
816 tables[SMU_TABLE_PMSTATUSLOG].domain,
817 &tables[SMU_TABLE_PMSTATUSLOG].bo,
818 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
819 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
821 pr_err("VRAM allocation for tool table failed!\n");
826 /* VRAM allocation for driver table */
827 for (i = 0; i < SMU_TABLE_COUNT; i++) {
828 if (tables[i].size == 0)
831 if (i == SMU_TABLE_PMSTATUSLOG)
834 if (max_table_size < tables[i].size)
835 max_table_size = tables[i].size;
838 driver_table->size = max_table_size;
839 driver_table->align = PAGE_SIZE;
840 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
842 ret = amdgpu_bo_create_kernel(adev,
845 driver_table->domain,
847 &driver_table->mc_address,
848 &driver_table->cpu_addr);
850 pr_err("VRAM allocation for driver table failed!\n");
851 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
852 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
853 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
854 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
860 static int smu_fini_fb_allocations(struct smu_context *smu)
862 struct smu_table_context *smu_table = &smu->smu_table;
863 struct smu_table *tables = smu_table->tables;
864 struct smu_table *driver_table = &(smu_table->driver_table);
869 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
870 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
871 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
872 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
874 amdgpu_bo_free_kernel(&driver_table->bo,
875 &driver_table->mc_address,
876 &driver_table->cpu_addr);
882 * smu_alloc_memory_pool - allocate memory pool in the system memory
884 * @smu: amdgpu_device pointer
886 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
887 * and DramLogSetDramAddr can notify it changed.
889 * Returns 0 on success, error on failure.
891 static int smu_alloc_memory_pool(struct smu_context *smu)
893 struct amdgpu_device *adev = smu->adev;
894 struct smu_table_context *smu_table = &smu->smu_table;
895 struct smu_table *memory_pool = &smu_table->memory_pool;
896 uint64_t pool_size = smu->pool_size;
899 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
902 memory_pool->size = pool_size;
903 memory_pool->align = PAGE_SIZE;
904 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
907 case SMU_MEMORY_POOL_SIZE_256_MB:
908 case SMU_MEMORY_POOL_SIZE_512_MB:
909 case SMU_MEMORY_POOL_SIZE_1_GB:
910 case SMU_MEMORY_POOL_SIZE_2_GB:
911 ret = amdgpu_bo_create_kernel(adev,
916 &memory_pool->mc_address,
917 &memory_pool->cpu_addr);
926 static int smu_free_memory_pool(struct smu_context *smu)
928 struct smu_table_context *smu_table = &smu->smu_table;
929 struct smu_table *memory_pool = &smu_table->memory_pool;
931 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
934 amdgpu_bo_free_kernel(&memory_pool->bo,
935 &memory_pool->mc_address,
936 &memory_pool->cpu_addr);
938 memset(memory_pool, 0, sizeof(struct smu_table));
943 static int smu_smc_table_sw_init(struct smu_context *smu)
948 * Create smu_table structure, and init smc tables such as
949 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
951 ret = smu_init_smc_tables(smu);
953 pr_err("Failed to init smc tables!\n");
958 * Create smu_power_context structure, and allocate smu_dpm_context and
959 * context size to fill the smu_power_context data.
961 ret = smu_init_power(smu);
963 pr_err("Failed to init smu_init_power!\n");
968 * allocate vram bos to store smc table contents.
970 ret = smu_init_fb_allocations(smu);
974 ret = smu_alloc_memory_pool(smu);
981 static int smu_smc_table_sw_fini(struct smu_context *smu)
985 ret = smu_free_memory_pool(smu);
989 ret = smu_fini_fb_allocations(smu);
993 ret = smu_fini_power(smu);
995 pr_err("Failed to init smu_fini_power!\n");
999 ret = smu_fini_smc_tables(smu);
1001 pr_err("Failed to smu_fini_smc_tables!\n");
1008 static int smu_sw_init(void *handle)
1010 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1011 struct smu_context *smu = &adev->smu;
1014 smu->pool_size = adev->pm.smu_prv_buffer_size;
1015 smu->smu_feature.feature_num = SMU_FEATURE_MAX;
1016 mutex_init(&smu->smu_feature.mutex);
1017 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
1018 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
1019 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
1021 mutex_init(&smu->smu_baco.mutex);
1022 smu->smu_baco.state = SMU_BACO_STATE_EXIT;
1023 smu->smu_baco.platform_support = false;
1025 mutex_init(&smu->sensor_lock);
1026 mutex_init(&smu->metrics_lock);
1027 mutex_init(&smu->message_lock);
1029 smu->watermarks_bitmap = 0;
1030 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1031 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1033 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
1034 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
1035 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
1036 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
1037 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
1038 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
1039 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
1040 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
1042 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1043 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1044 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
1045 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
1046 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
1047 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
1048 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
1049 smu->display_config = &adev->pm.pm_display_cfg;
1051 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1052 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1053 ret = smu_init_microcode(smu);
1055 pr_err("Failed to load smu firmware!\n");
1059 ret = smu_smc_table_sw_init(smu);
1061 pr_err("Failed to sw init smc table!\n");
1065 ret = smu_register_irq_handler(smu);
1067 pr_err("Failed to register smc irq handler!\n");
1074 static int smu_sw_fini(void *handle)
1076 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1077 struct smu_context *smu = &adev->smu;
1080 kfree(smu->irq_source);
1081 smu->irq_source = NULL;
1083 ret = smu_smc_table_sw_fini(smu);
1085 pr_err("Failed to sw fini smc table!\n");
1092 static int smu_smc_table_hw_init(struct smu_context *smu,
1095 struct amdgpu_device *adev = smu->adev;
1098 if (smu_is_dpm_running(smu) && adev->in_suspend) {
1099 pr_info("dpm has been enabled\n");
1103 ret = smu_init_display_count(smu, 0);
1108 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1109 ret = smu_get_vbios_bootup_values(smu);
1113 ret = smu_setup_pptable(smu);
1118 * Send msg GetDriverIfVersion to check if the return value is equal
1119 * with DRIVER_IF_VERSION of smc header.
1121 ret = smu_check_fw_version(smu);
1126 ret = smu_set_driver_table_location(smu);
1130 /* smu_dump_pptable(smu); */
1132 * Copy pptable bo in the vram to smc with SMU MSGs such as
1133 * SetDriverDramAddr and TransferTableDram2Smu.
1135 ret = smu_write_pptable(smu);
1139 /* issue Run*Btc msg */
1140 ret = smu_run_btc(smu);
1143 ret = smu_feature_set_allowed_mask(smu);
1147 ret = smu_system_features_control(smu, true);
1151 ret = smu_disable_umc_cdr_12gbps_workaround(smu);
1153 pr_err("Workaround failed to disable UMC CDR feature on 12Gbps SKU!\n");
1158 * For Navi1X, manually switch it to AC mode as PMFW
1159 * may boot it with DC mode.
1161 ret = smu_set_power_source(smu,
1162 adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
1163 SMU_POWER_SOURCE_DC);
1165 pr_err("Failed to switch to %s mode!\n", adev->pm.ac_power ? "AC" : "DC");
1169 ret = smu_notify_display_change(smu);
1174 * Set min deep sleep dce fclk with bootup value from vbios via
1175 * SetMinDeepSleepDcefclk MSG.
1177 ret = smu_set_min_dcef_deep_sleep(smu);
1182 * Set initialized values (get from vbios) to dpm tables context such as
1183 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1187 ret = smu_populate_smc_tables(smu);
1191 ret = smu_init_max_sustainable_clocks(smu);
1196 ret = smu_override_pcie_parameters(smu);
1200 ret = smu_set_default_od_settings(smu, initialize);
1205 ret = smu_populate_umd_state_clk(smu);
1209 ret = smu_get_power_limit(smu, &smu->default_power_limit, false, false);
1215 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1217 ret = smu_set_tool_table_location(smu);
1219 if (!smu_is_dpm_running(smu))
1220 pr_info("dpm has been disabled\n");
1225 static int smu_start_smc_engine(struct smu_context *smu)
1227 struct amdgpu_device *adev = smu->adev;
1230 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1231 if (adev->asic_type < CHIP_NAVI10) {
1232 if (smu->ppt_funcs->load_microcode) {
1233 ret = smu->ppt_funcs->load_microcode(smu);
1240 if (smu->ppt_funcs->check_fw_status) {
1241 ret = smu->ppt_funcs->check_fw_status(smu);
1243 pr_err("SMC is not ready\n");
1249 static int smu_hw_init(void *handle)
1252 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1253 struct smu_context *smu = &adev->smu;
1255 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1258 ret = smu_start_smc_engine(smu);
1260 pr_err("SMU is not ready yet!\n");
1265 smu_powergate_sdma(&adev->smu, false);
1266 smu_powergate_vcn(&adev->smu, false);
1267 smu_powergate_jpeg(&adev->smu, false);
1268 smu_set_gfx_cgpg(&adev->smu, true);
1271 if (!smu->pm_enabled)
1274 ret = smu_feature_init_dpm(smu);
1278 ret = smu_smc_table_hw_init(smu, true);
1283 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1286 ret = smu_notify_memory_pool_location(smu);
1290 ret = smu_enable_thermal_alert(smu);
1294 ret = smu_i2c_eeprom_init(smu, &adev->pm.smu_i2c);
1298 adev->pm.dpm_enabled = true;
1300 pr_info("SMU is initialized successfully!\n");
1308 static int smu_disable_dpms(struct smu_context *smu)
1310 struct amdgpu_device *adev = smu->adev;
1312 bool use_baco = !smu->is_apu &&
1313 ((adev->in_gpu_reset &&
1314 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1315 ((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev)));
1318 * For custom pptable uploading, skip the DPM features
1319 * disable process on Navi1x ASICs.
1320 * - As the gfx related features are under control of
1321 * RLC on those ASICs. RLC reinitialization will be
1322 * needed to reenable them. That will cost much more
1325 * - SMU firmware can handle the DPM reenablement
1328 if (smu->uploading_custom_pp_table &&
1329 (adev->asic_type >= CHIP_NAVI10) &&
1330 (adev->asic_type <= CHIP_NAVI12))
1334 * For Sienna_Cichlid, PMFW will handle the features disablement properly
1335 * on BACO in. Driver involvement is unnecessary.
1337 if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1342 * Disable all enabled SMU features.
1343 * This should be handled in SMU FW, as a backup
1344 * driver can issue call to SMU FW until sequence
1345 * in SMU FW is operational.
1347 ret = smu_system_features_control(smu, false);
1349 pr_err("Failed to disable smu features.\n");
1354 * For baco, need to leave BACO feature enabled
1356 * Correct the way for checking whether SMU_FEATURE_BACO_BIT
1359 * Since 'smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)' will
1360 * always return false as the 'smu_system_features_control(smu, false)'
1361 * was just issued above which disabled all SMU features.
1363 * Thus 'smu_feature_get_index(smu, SMU_FEATURE_BACO_BIT)' is used
1364 * now for the checking.
1366 if (use_baco && (smu_feature_get_index(smu, SMU_FEATURE_BACO_BIT) >= 0)) {
1367 ret = smu_feature_set_enabled(smu, SMU_FEATURE_BACO_BIT, true);
1369 pr_warn("set BACO feature enabled failed, return %d\n", ret);
1374 if (adev->asic_type >= CHIP_NAVI10 &&
1375 adev->gfx.rlc.funcs->stop)
1376 adev->gfx.rlc.funcs->stop(adev);
1381 static int smu_hw_fini(void *handle)
1383 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1384 struct smu_context *smu = &adev->smu;
1387 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1391 smu_powergate_sdma(&adev->smu, true);
1392 smu_powergate_vcn(&adev->smu, true);
1393 smu_powergate_jpeg(&adev->smu, true);
1396 if (!smu->pm_enabled)
1399 adev->pm.dpm_enabled = false;
1401 smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);
1403 ret = smu_disable_thermal_alert(smu);
1405 pr_warn("Fail to stop thermal control!\n");
1409 ret = smu_disable_dpms(smu);
1411 pr_warn("Fail to stop Dpms!\n");
1418 int smu_reset(struct smu_context *smu)
1420 struct amdgpu_device *adev = smu->adev;
1423 ret = smu_hw_fini(adev);
1427 ret = smu_hw_init(adev);
1434 static int smu_suspend(void *handle)
1436 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1437 struct smu_context *smu = &adev->smu;
1440 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1443 if (!smu->pm_enabled)
1446 adev->pm.dpm_enabled = false;
1448 smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);
1450 ret = smu_disable_thermal_alert(smu);
1452 pr_warn("Fail to stop thermal control!\n");
1456 ret = smu_disable_dpms(smu);
1460 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1463 smu_set_gfx_cgpg(&adev->smu, false);
1468 static int smu_resume(void *handle)
1471 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1472 struct smu_context *smu = &adev->smu;
1474 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1477 if (!smu->pm_enabled)
1480 pr_info("SMU is resuming...\n");
1482 ret = smu_start_smc_engine(smu);
1484 pr_err("SMU is not ready yet!\n");
1488 ret = smu_smc_table_hw_init(smu, false);
1492 ret = smu_enable_thermal_alert(smu);
1496 ret = smu_i2c_eeprom_init(smu, &adev->pm.smu_i2c);
1501 smu_set_gfx_cgpg(&adev->smu, true);
1503 smu->disable_uclk_switch = 0;
1505 adev->pm.dpm_enabled = true;
1507 pr_info("SMU is resumed successfully!\n");
1515 int smu_display_configuration_change(struct smu_context *smu,
1516 const struct amd_pp_display_configuration *display_config)
1519 int num_of_active_display = 0;
1521 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1524 if (!display_config)
1527 mutex_lock(&smu->mutex);
1529 if (smu->ppt_funcs->set_deep_sleep_dcefclk)
1530 smu->ppt_funcs->set_deep_sleep_dcefclk(smu,
1531 display_config->min_dcef_deep_sleep_set_clk / 100);
1533 for (index = 0; index < display_config->num_path_including_non_display; index++) {
1534 if (display_config->displays[index].controller_id != 0)
1535 num_of_active_display++;
1538 smu_set_active_display_count(smu, num_of_active_display);
1540 smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1541 display_config->cpu_cc6_disable,
1542 display_config->cpu_pstate_disable,
1543 display_config->nb_pstate_switch_disable);
1545 mutex_unlock(&smu->mutex);
1550 static int smu_get_clock_info(struct smu_context *smu,
1551 struct smu_clock_info *clk_info,
1552 enum smu_perf_level_designation designation)
1555 struct smu_performance_level level = {0};
1560 ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1564 clk_info->min_mem_clk = level.memory_clock;
1565 clk_info->min_eng_clk = level.core_clock;
1566 clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1568 ret = smu_get_perf_level(smu, designation, &level);
1572 clk_info->min_mem_clk = level.memory_clock;
1573 clk_info->min_eng_clk = level.core_clock;
1574 clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1579 int smu_get_current_clocks(struct smu_context *smu,
1580 struct amd_pp_clock_info *clocks)
1582 struct amd_pp_simple_clock_info simple_clocks = {0};
1583 struct smu_clock_info hw_clocks;
1586 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1589 mutex_lock(&smu->mutex);
1591 smu_get_dal_power_level(smu, &simple_clocks);
1593 if (smu->support_power_containment)
1594 ret = smu_get_clock_info(smu, &hw_clocks,
1595 PERF_LEVEL_POWER_CONTAINMENT);
1597 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1600 pr_err("Error in smu_get_clock_info\n");
1604 clocks->min_engine_clock = hw_clocks.min_eng_clk;
1605 clocks->max_engine_clock = hw_clocks.max_eng_clk;
1606 clocks->min_memory_clock = hw_clocks.min_mem_clk;
1607 clocks->max_memory_clock = hw_clocks.max_mem_clk;
1608 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1609 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1610 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1611 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1613 if (simple_clocks.level == 0)
1614 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1616 clocks->max_clocks_state = simple_clocks.level;
1618 if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1619 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1620 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1624 mutex_unlock(&smu->mutex);
1628 static int smu_set_clockgating_state(void *handle,
1629 enum amd_clockgating_state state)
1634 static int smu_set_powergating_state(void *handle,
1635 enum amd_powergating_state state)
1640 static int smu_enable_umd_pstate(void *handle,
1641 enum amd_dpm_forced_level *level)
1643 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1644 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1645 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1646 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1648 struct smu_context *smu = (struct smu_context*)(handle);
1649 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1651 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1654 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1655 /* enter umd pstate, save current level, disable gfx cg*/
1656 if (*level & profile_mode_mask) {
1657 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1658 smu_dpm_ctx->enable_umd_pstate = true;
1659 amdgpu_device_ip_set_powergating_state(smu->adev,
1660 AMD_IP_BLOCK_TYPE_GFX,
1661 AMD_PG_STATE_UNGATE);
1662 amdgpu_device_ip_set_clockgating_state(smu->adev,
1663 AMD_IP_BLOCK_TYPE_GFX,
1664 AMD_CG_STATE_UNGATE);
1667 /* exit umd pstate, restore level, enable gfx cg*/
1668 if (!(*level & profile_mode_mask)) {
1669 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1670 *level = smu_dpm_ctx->saved_dpm_level;
1671 smu_dpm_ctx->enable_umd_pstate = false;
1672 amdgpu_device_ip_set_clockgating_state(smu->adev,
1673 AMD_IP_BLOCK_TYPE_GFX,
1675 amdgpu_device_ip_set_powergating_state(smu->adev,
1676 AMD_IP_BLOCK_TYPE_GFX,
1684 int smu_adjust_power_state_dynamic(struct smu_context *smu,
1685 enum amd_dpm_forced_level level,
1686 bool skip_display_settings)
1691 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1693 if (!skip_display_settings) {
1694 ret = smu_display_config_changed(smu);
1696 pr_err("Failed to change display config!");
1701 ret = smu_apply_clocks_adjust_rules(smu);
1703 pr_err("Failed to apply clocks adjust rules!");
1707 if (!skip_display_settings) {
1708 ret = smu_notify_smc_display_config(smu);
1710 pr_err("Failed to notify smc display config!");
1715 if (smu_dpm_ctx->dpm_level != level) {
1716 ret = smu_asic_set_performance_level(smu, level);
1718 pr_err("Failed to set performance level!");
1722 /* update the saved copy */
1723 smu_dpm_ctx->dpm_level = level;
1726 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1727 index = fls(smu->workload_mask);
1728 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1729 workload = smu->workload_setting[index];
1731 if (smu->power_profile_mode != workload)
1732 smu_set_power_profile_mode(smu, &workload, 0, false);
1738 int smu_handle_task(struct smu_context *smu,
1739 enum amd_dpm_forced_level level,
1740 enum amd_pp_task task_id,
1745 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1749 mutex_lock(&smu->mutex);
1752 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1753 ret = smu_pre_display_config_changed(smu);
1756 ret = smu_set_cpu_power_state(smu);
1759 ret = smu_adjust_power_state_dynamic(smu, level, false);
1761 case AMD_PP_TASK_COMPLETE_INIT:
1762 case AMD_PP_TASK_READJUST_POWER_STATE:
1763 ret = smu_adjust_power_state_dynamic(smu, level, true);
1771 mutex_unlock(&smu->mutex);
1776 int smu_switch_power_profile(struct smu_context *smu,
1777 enum PP_SMC_POWER_PROFILE type,
1780 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1784 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1787 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1790 mutex_lock(&smu->mutex);
1793 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1794 index = fls(smu->workload_mask);
1795 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1796 workload = smu->workload_setting[index];
1798 smu->workload_mask |= (1 << smu->workload_prority[type]);
1799 index = fls(smu->workload_mask);
1800 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1801 workload = smu->workload_setting[index];
1804 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1805 smu_set_power_profile_mode(smu, &workload, 0, false);
1807 mutex_unlock(&smu->mutex);
1812 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1814 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1815 enum amd_dpm_forced_level level;
1817 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1820 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1823 mutex_lock(&(smu->mutex));
1824 level = smu_dpm_ctx->dpm_level;
1825 mutex_unlock(&(smu->mutex));
1830 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1832 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1835 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1838 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1841 mutex_lock(&smu->mutex);
1843 ret = smu_enable_umd_pstate(smu, &level);
1845 mutex_unlock(&smu->mutex);
1849 ret = smu_handle_task(smu, level,
1850 AMD_PP_TASK_READJUST_POWER_STATE,
1853 mutex_unlock(&smu->mutex);
1858 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1862 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1865 mutex_lock(&smu->mutex);
1866 ret = smu_init_display_count(smu, count);
1867 mutex_unlock(&smu->mutex);
1872 int smu_force_clk_levels(struct smu_context *smu,
1873 enum smu_clk_type clk_type,
1877 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1880 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1883 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1884 pr_debug("force clock level is for dpm manual mode only.\n");
1889 mutex_lock(&smu->mutex);
1891 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
1892 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1895 mutex_unlock(&smu->mutex);
1901 * On system suspending or resetting, the dpm_enabled
1902 * flag will be cleared. So that those SMU services which
1903 * are not supported will be gated.
1904 * However, the mp1 state setting should still be granted
1905 * even if the dpm_enabled cleared.
1907 int smu_set_mp1_state(struct smu_context *smu,
1908 enum pp_mp1_state mp1_state)
1913 if (!smu->pm_enabled)
1916 mutex_lock(&smu->mutex);
1918 switch (mp1_state) {
1919 case PP_MP1_STATE_SHUTDOWN:
1920 msg = SMU_MSG_PrepareMp1ForShutdown;
1922 case PP_MP1_STATE_UNLOAD:
1923 msg = SMU_MSG_PrepareMp1ForUnload;
1925 case PP_MP1_STATE_RESET:
1926 msg = SMU_MSG_PrepareMp1ForReset;
1928 case PP_MP1_STATE_NONE:
1930 mutex_unlock(&smu->mutex);
1934 /* some asics may not support those messages */
1935 if (smu_msg_get_index(smu, msg) < 0) {
1936 mutex_unlock(&smu->mutex);
1940 ret = smu_send_smc_msg(smu, msg, NULL);
1942 pr_err("[PrepareMp1] Failed!\n");
1944 mutex_unlock(&smu->mutex);
1949 int smu_set_df_cstate(struct smu_context *smu,
1950 enum pp_df_cstate state)
1954 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1957 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1960 mutex_lock(&smu->mutex);
1962 ret = smu->ppt_funcs->set_df_cstate(smu, state);
1964 pr_err("[SetDfCstate] failed!\n");
1966 mutex_unlock(&smu->mutex);
1971 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
1975 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1978 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
1981 mutex_lock(&smu->mutex);
1983 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
1985 pr_err("[AllowXgmiPowerDown] failed!\n");
1987 mutex_unlock(&smu->mutex);
1992 int smu_write_watermarks_table(struct smu_context *smu)
1994 void *watermarks_table = smu->smu_table.watermarks_table;
1996 if (!watermarks_table)
1999 return smu_update_table(smu,
2000 SMU_TABLE_WATERMARKS,
2006 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
2007 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
2009 void *table = smu->smu_table.watermarks_table;
2011 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2017 mutex_lock(&smu->mutex);
2019 if (!smu->disable_watermark &&
2020 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
2021 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
2022 smu_set_watermarks_table(smu, table, clock_ranges);
2024 if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
2025 smu->watermarks_bitmap |= WATERMARKS_EXIST;
2026 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
2030 mutex_unlock(&smu->mutex);
2035 int smu_set_ac_dc(struct smu_context *smu)
2039 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2042 /* controlled by firmware */
2043 if (smu->dc_controlled_by_gpio)
2046 mutex_lock(&smu->mutex);
2047 ret = smu_set_power_source(smu,
2048 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
2049 SMU_POWER_SOURCE_DC);
2051 pr_err("Failed to switch to %s mode!\n",
2052 smu->adev->pm.ac_power ? "AC" : "DC");
2053 mutex_unlock(&smu->mutex);
2058 const struct amd_ip_funcs smu_ip_funcs = {
2060 .early_init = smu_early_init,
2061 .late_init = smu_late_init,
2062 .sw_init = smu_sw_init,
2063 .sw_fini = smu_sw_fini,
2064 .hw_init = smu_hw_init,
2065 .hw_fini = smu_hw_fini,
2066 .suspend = smu_suspend,
2067 .resume = smu_resume,
2069 .check_soft_reset = NULL,
2070 .wait_for_idle = NULL,
2072 .set_clockgating_state = smu_set_clockgating_state,
2073 .set_powergating_state = smu_set_powergating_state,
2074 .enable_umd_pstate = smu_enable_umd_pstate,
2077 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
2079 .type = AMD_IP_BLOCK_TYPE_SMC,
2083 .funcs = &smu_ip_funcs,
2086 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
2088 .type = AMD_IP_BLOCK_TYPE_SMC,
2092 .funcs = &smu_ip_funcs,
2095 int smu_load_microcode(struct smu_context *smu)
2099 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2102 mutex_lock(&smu->mutex);
2104 if (smu->ppt_funcs->load_microcode)
2105 ret = smu->ppt_funcs->load_microcode(smu);
2107 mutex_unlock(&smu->mutex);
2112 int smu_check_fw_status(struct smu_context *smu)
2116 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2119 mutex_lock(&smu->mutex);
2121 if (smu->ppt_funcs->check_fw_status)
2122 ret = smu->ppt_funcs->check_fw_status(smu);
2124 mutex_unlock(&smu->mutex);
2129 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2133 mutex_lock(&smu->mutex);
2135 if (smu->ppt_funcs->set_gfx_cgpg)
2136 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2138 mutex_unlock(&smu->mutex);
2143 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
2147 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2150 mutex_lock(&smu->mutex);
2152 if (smu->ppt_funcs->set_fan_speed_rpm)
2153 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2155 mutex_unlock(&smu->mutex);
2160 int smu_get_power_limit(struct smu_context *smu,
2168 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2171 mutex_lock(&smu->mutex);
2174 if (smu->ppt_funcs->get_power_limit)
2175 ret = smu->ppt_funcs->get_power_limit(smu, limit, def);
2178 mutex_unlock(&smu->mutex);
2183 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
2187 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2190 mutex_lock(&smu->mutex);
2192 if (smu->ppt_funcs->set_power_limit)
2193 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2195 mutex_unlock(&smu->mutex);
2200 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2204 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2207 mutex_lock(&smu->mutex);
2209 if (smu->ppt_funcs->print_clk_levels)
2210 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2212 mutex_unlock(&smu->mutex);
2217 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
2221 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2224 mutex_lock(&smu->mutex);
2226 if (smu->ppt_funcs->get_od_percentage)
2227 ret = smu->ppt_funcs->get_od_percentage(smu, type);
2229 mutex_unlock(&smu->mutex);
2234 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
2238 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2241 mutex_lock(&smu->mutex);
2243 if (smu->ppt_funcs->set_od_percentage)
2244 ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
2246 mutex_unlock(&smu->mutex);
2251 int smu_od_edit_dpm_table(struct smu_context *smu,
2252 enum PP_OD_DPM_TABLE_COMMAND type,
2253 long *input, uint32_t size)
2257 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2260 mutex_lock(&smu->mutex);
2262 if (smu->ppt_funcs->od_edit_dpm_table)
2263 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2265 mutex_unlock(&smu->mutex);
2270 int smu_read_sensor(struct smu_context *smu,
2271 enum amd_pp_sensors sensor,
2272 void *data, uint32_t *size)
2276 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2279 mutex_lock(&smu->mutex);
2281 if (smu->ppt_funcs->read_sensor)
2282 ret = smu->ppt_funcs->read_sensor(smu, sensor, data, size);
2284 mutex_unlock(&smu->mutex);
2289 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2293 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2296 mutex_lock(&smu->mutex);
2298 if (smu->ppt_funcs->get_power_profile_mode)
2299 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2301 mutex_unlock(&smu->mutex);
2306 int smu_set_power_profile_mode(struct smu_context *smu,
2308 uint32_t param_size,
2313 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2317 mutex_lock(&smu->mutex);
2319 if (smu->ppt_funcs->set_power_profile_mode)
2320 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2323 mutex_unlock(&smu->mutex);
2329 int smu_get_fan_control_mode(struct smu_context *smu)
2333 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2336 mutex_lock(&smu->mutex);
2338 if (smu->ppt_funcs->get_fan_control_mode)
2339 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2341 mutex_unlock(&smu->mutex);
2346 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2350 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2353 mutex_lock(&smu->mutex);
2355 if (smu->ppt_funcs->set_fan_control_mode)
2356 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2358 mutex_unlock(&smu->mutex);
2363 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2367 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2370 mutex_lock(&smu->mutex);
2372 if (smu->ppt_funcs->get_fan_speed_percent)
2373 ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
2375 mutex_unlock(&smu->mutex);
2380 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2384 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2387 mutex_lock(&smu->mutex);
2389 if (smu->ppt_funcs->set_fan_speed_percent)
2390 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
2392 mutex_unlock(&smu->mutex);
2397 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2401 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2404 mutex_lock(&smu->mutex);
2406 if (smu->ppt_funcs->get_fan_speed_rpm)
2407 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2409 mutex_unlock(&smu->mutex);
2414 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2418 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2421 mutex_lock(&smu->mutex);
2423 if (smu->ppt_funcs->set_deep_sleep_dcefclk)
2424 ret = smu->ppt_funcs->set_deep_sleep_dcefclk(smu, clk);
2426 mutex_unlock(&smu->mutex);
2431 int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
2435 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2438 if (smu->ppt_funcs->set_active_display_count)
2439 ret = smu->ppt_funcs->set_active_display_count(smu, count);
2444 int smu_get_clock_by_type(struct smu_context *smu,
2445 enum amd_pp_clock_type type,
2446 struct amd_pp_clocks *clocks)
2450 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2453 mutex_lock(&smu->mutex);
2455 if (smu->ppt_funcs->get_clock_by_type)
2456 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
2458 mutex_unlock(&smu->mutex);
2463 int smu_get_max_high_clocks(struct smu_context *smu,
2464 struct amd_pp_simple_clock_info *clocks)
2468 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2471 mutex_lock(&smu->mutex);
2473 if (smu->ppt_funcs->get_max_high_clocks)
2474 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
2476 mutex_unlock(&smu->mutex);
2481 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2482 enum smu_clk_type clk_type,
2483 struct pp_clock_levels_with_latency *clocks)
2487 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2490 mutex_lock(&smu->mutex);
2492 if (smu->ppt_funcs->get_clock_by_type_with_latency)
2493 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2495 mutex_unlock(&smu->mutex);
2500 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
2501 enum amd_pp_clock_type type,
2502 struct pp_clock_levels_with_voltage *clocks)
2506 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2509 mutex_lock(&smu->mutex);
2511 if (smu->ppt_funcs->get_clock_by_type_with_voltage)
2512 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
2514 mutex_unlock(&smu->mutex);
2520 int smu_display_clock_voltage_request(struct smu_context *smu,
2521 struct pp_display_clock_request *clock_req)
2525 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2528 mutex_lock(&smu->mutex);
2530 if (smu->ppt_funcs->display_clock_voltage_request)
2531 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2533 mutex_unlock(&smu->mutex);
2539 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2543 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2546 mutex_lock(&smu->mutex);
2548 if (smu->ppt_funcs->display_disable_memory_clock_switch)
2549 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2551 mutex_unlock(&smu->mutex);
2556 int smu_notify_smu_enable_pwe(struct smu_context *smu)
2560 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2563 mutex_lock(&smu->mutex);
2565 if (smu->ppt_funcs->notify_smu_enable_pwe)
2566 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
2568 mutex_unlock(&smu->mutex);
2573 int smu_set_xgmi_pstate(struct smu_context *smu,
2578 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2581 mutex_lock(&smu->mutex);
2583 if (smu->ppt_funcs->set_xgmi_pstate)
2584 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2586 mutex_unlock(&smu->mutex);
2591 int smu_set_azalia_d3_pme(struct smu_context *smu)
2595 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2598 mutex_lock(&smu->mutex);
2600 if (smu->ppt_funcs->set_azalia_d3_pme)
2601 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2603 mutex_unlock(&smu->mutex);
2609 * On system suspending or resetting, the dpm_enabled
2610 * flag will be cleared. So that those SMU services which
2611 * are not supported will be gated.
2613 * However, the baco/mode1 reset should still be granted
2614 * as they are still supported and necessary.
2616 bool smu_baco_is_support(struct smu_context *smu)
2620 if (!smu->pm_enabled)
2623 mutex_lock(&smu->mutex);
2625 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2626 ret = smu->ppt_funcs->baco_is_support(smu);
2628 mutex_unlock(&smu->mutex);
2633 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2635 if (smu->ppt_funcs->baco_get_state)
2638 mutex_lock(&smu->mutex);
2639 *state = smu->ppt_funcs->baco_get_state(smu);
2640 mutex_unlock(&smu->mutex);
2645 int smu_baco_enter(struct smu_context *smu)
2649 if (!smu->pm_enabled)
2652 mutex_lock(&smu->mutex);
2654 if (smu->ppt_funcs->baco_enter)
2655 ret = smu->ppt_funcs->baco_enter(smu);
2657 mutex_unlock(&smu->mutex);
2662 int smu_baco_exit(struct smu_context *smu)
2666 if (!smu->pm_enabled)
2669 mutex_lock(&smu->mutex);
2671 if (smu->ppt_funcs->baco_exit)
2672 ret = smu->ppt_funcs->baco_exit(smu);
2674 mutex_unlock(&smu->mutex);
2679 int smu_mode2_reset(struct smu_context *smu)
2683 if (!smu->pm_enabled)
2686 mutex_lock(&smu->mutex);
2688 if (smu->ppt_funcs->mode2_reset)
2689 ret = smu->ppt_funcs->mode2_reset(smu);
2691 mutex_unlock(&smu->mutex);
2696 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2697 struct pp_smu_nv_clock_table *max_clocks)
2701 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2704 mutex_lock(&smu->mutex);
2706 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2707 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2709 mutex_unlock(&smu->mutex);
2714 int smu_get_uclk_dpm_states(struct smu_context *smu,
2715 unsigned int *clock_values_in_khz,
2716 unsigned int *num_states)
2720 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2723 mutex_lock(&smu->mutex);
2725 if (smu->ppt_funcs->get_uclk_dpm_states)
2726 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2728 mutex_unlock(&smu->mutex);
2733 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2735 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2737 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2740 mutex_lock(&smu->mutex);
2742 if (smu->ppt_funcs->get_current_power_state)
2743 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2745 mutex_unlock(&smu->mutex);
2750 int smu_get_dpm_clock_table(struct smu_context *smu,
2751 struct dpm_clocks *clock_table)
2755 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2758 mutex_lock(&smu->mutex);
2760 if (smu->ppt_funcs->get_dpm_clock_table)
2761 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2763 mutex_unlock(&smu->mutex);
2768 uint32_t smu_get_pptable_power_limit(struct smu_context *smu)
2772 if (smu->ppt_funcs->get_pptable_power_limit)
2773 ret = smu->ppt_funcs->get_pptable_power_limit(smu);
2778 int smu_powergate_vcn(struct smu_context *smu, bool gate)
2783 return smu_dpm_set_uvd_enable(smu, !gate);
2786 int smu_powergate_jpeg(struct smu_context *smu, bool gate)
2791 return smu_dpm_set_jpeg_enable(smu, !gate);