drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/pci.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_internal.h"
  29 #include "smu_v11_0.h"
  30 #include "smu_v12_0.h"
  31 #include "atom.h"
  32 #include "arcturus_ppt.h"
  33 #include "navi10_ppt.h"
  34 #include "sienna_cichlid_ppt.h"
  35 #include "renoir_ppt.h"
  36
  37 /*
  38  * DO NOT use these for err/warn/info/debug messages.
  39  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  40  * They are more MGPU friendly.
  41  */
  42 #undef pr_err
  43 #undef pr_warn
  44 #undef pr_info
  45 #undef pr_debug
  46
  47 #undef __SMU_DUMMY_MAP
  48 #define __SMU_DUMMY_MAP(type)   #type
  49 static const char* __smu_message_names[] = {
  50         SMU_MESSAGE_TYPES
  51 };
  52
  53 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
  54 {
  55         if (type < 0 || type >= SMU_MSG_MAX_COUNT)
  56                 return "unknown smu message";
  57         return __smu_message_names[type];
  58 }
  59
  60 #undef __SMU_DUMMY_MAP
  61 #define __SMU_DUMMY_MAP(fea)    #fea
  62 static const char* __smu_feature_names[] = {
  63         SMU_FEATURE_MASKS
  64 };
  65
  66 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
  67 {
  68         if (feature < 0 || feature >= SMU_FEATURE_COUNT)
  69                 return "unknown smu feature";
  70         return __smu_feature_names[feature];
  71 }
  72
  73 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
  74 {
  75         size_t size = 0;
  76         int ret = 0, i = 0;
  77         uint32_t feature_mask[2] = { 0 };
  78         int32_t feature_index = 0;
  79         uint32_t count = 0;
  80         uint32_t sort_feature[SMU_FEATURE_COUNT];
  81         uint64_t hw_feature_count = 0;
  82
  83         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  84                 return -EOPNOTSUPP;
  85
  86         mutex_lock(&smu->mutex);
  87
  88         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
  89         if (ret)
  90                 goto failed;
  91
  92         size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
  93                         feature_mask[1], feature_mask[0]);
  94
  95         for (i = 0; i < SMU_FEATURE_COUNT; i++) {
  96                 feature_index = smu_feature_get_index(smu, i);
  97                 if (feature_index < 0)
  98                         continue;
  99                 sort_feature[feature_index] = i;
 100                 hw_feature_count++;
 101         }
 102
 103         for (i = 0; i < hw_feature_count; i++) {
 104                 size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
 105                                count++,
 106                                smu_get_feature_name(smu, sort_feature[i]),
 107                                i,
 108                                !!smu_feature_is_enabled(smu, sort_feature[i]) ?
 109                                "enabled" : "disabled");
 110         }
 111
 112 failed:
 113         mutex_unlock(&smu->mutex);
 114
 115         return size;
 116 }
 117
 118 static int smu_feature_update_enable_state(struct smu_context *smu,
 119                                            uint64_t feature_mask,
 120                                            bool enabled)
 121 {
 122         struct smu_feature *feature = &smu->smu_feature;
 123         int ret = 0;
 124
 125         if (enabled) {
 126                 ret = smu_send_smc_msg_with_param(smu,
 127                                                   SMU_MSG_EnableSmuFeaturesLow,
 128                                                   lower_32_bits(feature_mask),
 129                                                   NULL);
 130                 if (ret)
 131                         return ret;
 132                 ret = smu_send_smc_msg_with_param(smu,
 133                                                   SMU_MSG_EnableSmuFeaturesHigh,
 134                                                   upper_32_bits(feature_mask),
 135                                                   NULL);
 136                 if (ret)
 137                         return ret;
 138         } else {
 139                 ret = smu_send_smc_msg_with_param(smu,
 140                                                   SMU_MSG_DisableSmuFeaturesLow,
 141                                                   lower_32_bits(feature_mask),
 142                                                   NULL);
 143                 if (ret)
 144                         return ret;
 145                 ret = smu_send_smc_msg_with_param(smu,
 146                                                   SMU_MSG_DisableSmuFeaturesHigh,
 147                                                   upper_32_bits(feature_mask),
 148                                                   NULL);
 149                 if (ret)
 150                         return ret;
 151         }
 152
 153         mutex_lock(&feature->mutex);
 154         if (enabled)
 155                 bitmap_or(feature->enabled, feature->enabled,
 156                                 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
 157         else
 158                 bitmap_andnot(feature->enabled, feature->enabled,
 159                                 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
 160         mutex_unlock(&feature->mutex);
 161
 162         return ret;
 163 }
 164
 165 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
 166 {
 167         int ret = 0;
 168         uint32_t feature_mask[2] = { 0 };
 169         uint64_t feature_2_enabled = 0;
 170         uint64_t feature_2_disabled = 0;
 171         uint64_t feature_enables = 0;
 172
 173         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 174                 return -EOPNOTSUPP;
 175
 176         mutex_lock(&smu->mutex);
 177
 178         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 179         if (ret)
 180                 goto out;
 181
 182         feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
 183
 184         feature_2_enabled  = ~feature_enables & new_mask;
 185         feature_2_disabled = feature_enables & ~new_mask;
 186
 187         if (feature_2_enabled) {
 188                 ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
 189                 if (ret)
 190                         goto out;
 191         }
 192         if (feature_2_disabled) {
 193                 ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
 194                 if (ret)
 195                         goto out;
 196         }
 197
 198 out:
 199         mutex_unlock(&smu->mutex);
 200
 201         return ret;
 202 }
 203
 204 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
 205 {
 206         int ret = 0;
 207
 208         if (!if_version && !smu_version)
 209                 return -EINVAL;
 210
 211         if (smu->smc_fw_if_version && smu->smc_fw_version)
 212         {
 213                 if (if_version)
 214                         *if_version = smu->smc_fw_if_version;
 215
 216                 if (smu_version)
 217                         *smu_version = smu->smc_fw_version;
 218
 219                 return 0;
 220         }
 221
 222         if (if_version) {
 223                 ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion, if_version);
 224                 if (ret)
 225                         return ret;
 226
 227                 smu->smc_fw_if_version = *if_version;
 228         }
 229
 230         if (smu_version) {
 231                 ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion, smu_version);
 232                 if (ret)
 233                         return ret;
 234
 235                 smu->smc_fw_version = *smu_version;
 236         }
 237
 238         return ret;
 239 }
 240
 241 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 242                             uint32_t min, uint32_t max, bool lock_needed)
 243 {
 244         int ret = 0;
 245
 246         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 247                 return 0;
 248
 249         if (lock_needed)
 250                 mutex_lock(&smu->mutex);
 251         ret = smu_set_soft_freq_limited_range(smu, clk_type, min, max);
 252         if (lock_needed)
 253                 mutex_unlock(&smu->mutex);
 254
 255         return ret;
 256 }
 257
 258 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 259                             uint32_t min, uint32_t max)
 260 {
 261         int ret = 0, clk_id = 0;
 262         uint32_t param;
 263
 264         if (min <= 0 && max <= 0)
 265                 return -EINVAL;
 266
 267         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 268                 return 0;
 269
 270         clk_id = smu_clk_get_index(smu, clk_type);
 271         if (clk_id < 0)
 272                 return clk_id;
 273
 274         if (max > 0) {
 275                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
 276                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
 277                                                   param, NULL);
 278                 if (ret)
 279                         return ret;
 280         }
 281
 282         if (min > 0) {
 283                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
 284                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
 285                                                   param, NULL);
 286                 if (ret)
 287                         return ret;
 288         }
 289
 290
 291         return ret;
 292 }
 293
 294 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 295                            uint32_t *min, uint32_t *max, bool lock_needed)
 296 {
 297         uint32_t clock_limit;
 298         int ret = 0;
 299
 300         if (!min && !max)
 301                 return -EINVAL;
 302
 303         if (lock_needed)
 304                 mutex_lock(&smu->mutex);
 305
 306         if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
 307                 switch (clk_type) {
 308                 case SMU_MCLK:
 309                 case SMU_UCLK:
 310                         clock_limit = smu->smu_table.boot_values.uclk;
 311                         break;
 312                 case SMU_GFXCLK:
 313                 case SMU_SCLK:
 314                         clock_limit = smu->smu_table.boot_values.gfxclk;
 315                         break;
 316                 case SMU_SOCCLK:
 317                         clock_limit = smu->smu_table.boot_values.socclk;
 318                         break;
 319                 default:
 320                         clock_limit = 0;
 321                         break;
 322                 }
 323
 324                 /* clock in Mhz unit */
 325                 if (min)
 326                         *min = clock_limit / 100;
 327                 if (max)
 328                         *max = clock_limit / 100;
 329         } else {
 330                 /*
 331                  * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
 332                  * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
 333                  */
 334                 ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
 335         }
 336
 337         if (lock_needed)
 338                 mutex_unlock(&smu->mutex);
 339
 340         return ret;
 341 }
 342
 343 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
 344                               uint16_t level, uint32_t *value)
 345 {
 346         int ret = 0, clk_id = 0;
 347         uint32_t param;
 348
 349         if (!value)
 350                 return -EINVAL;
 351
 352         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 353                 return 0;
 354
 355         clk_id = smu_clk_get_index(smu, clk_type);
 356         if (clk_id < 0)
 357                 return clk_id;
 358
 359         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
 360
 361         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmFreqByIndex,
 362                                           param, value);
 363         if (ret)
 364                 return ret;
 365
 366         /* BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
 367          * now, we un-support it */
 368         *value = *value & 0x7fffffff;
 369
 370         return ret;
 371 }
 372
 373 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
 374                             uint32_t *value)
 375 {
 376         return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
 377 }
 378
 379 int smu_get_dpm_level_range(struct smu_context *smu, enum smu_clk_type clk_type,
 380                             uint32_t *min_value, uint32_t *max_value)
 381 {
 382         int ret = 0;
 383         uint32_t level_count = 0;
 384
 385         if (!min_value && !max_value)
 386                 return -EINVAL;
 387
 388         if (min_value) {
 389                 /* by default, level 0 clock value as min value */
 390                 ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, min_value);
 391                 if (ret)
 392                         return ret;
 393         }
 394
 395         if (max_value) {
 396                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
 397                 if (ret)
 398                         return ret;
 399
 400                 ret = smu_get_dpm_freq_by_index(smu, clk_type, level_count - 1, max_value);
 401                 if (ret)
 402                         return ret;
 403         }
 404
 405         return ret;
 406 }
 407
 408 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
 409 {
 410         enum smu_feature_mask feature_id = 0;
 411
 412         switch (clk_type) {
 413         case SMU_MCLK:
 414         case SMU_UCLK:
 415                 feature_id = SMU_FEATURE_DPM_UCLK_BIT;
 416                 break;
 417         case SMU_GFXCLK:
 418         case SMU_SCLK:
 419                 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
 420                 break;
 421         case SMU_SOCCLK:
 422                 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
 423                 break;
 424         default:
 425                 return true;
 426         }
 427
 428         if(!smu_feature_is_enabled(smu, feature_id)) {
 429                 return false;
 430         }
 431
 432         return true;
 433 }
 434
 435 /**
 436  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
 437  *
 438  * @smu:        smu_context pointer
 439  * @block_type: the IP block to power gate/ungate
 440  * @gate:       to power gate if true, ungate otherwise
 441  *
 442  * This API uses no smu->mutex lock protection due to:
 443  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
 444  *    This is guarded to be race condition free by the caller.
 445  * 2. Or get called on user setting request of power_dpm_force_performance_level.
 446  *    Under this case, the smu->mutex lock protection is already enforced on
 447  *    the parent API smu_force_performance_level of the call path.
 448  */
 449 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 450                            bool gate)
 451 {
 452         int ret = 0;
 453
 454         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 455                 return -EOPNOTSUPP;
 456
 457         switch (block_type) {
 458         case AMD_IP_BLOCK_TYPE_UVD:
 459                 ret = smu_dpm_set_uvd_enable(smu, !gate);
 460                 if (ret)
 461                         dev_err(smu->adev->dev, "Failed to power %s UVD!\n",
 462                                 gate ? "gate" : "ungate");
 463                 break;
 464         case AMD_IP_BLOCK_TYPE_GFX:
 465                 ret = smu_gfx_off_control(smu, gate);
 466                 if (ret)
 467                         dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
 468                                 gate ? "enable" : "disable");
 469                 break;
 470         case AMD_IP_BLOCK_TYPE_SDMA:
 471                 ret = smu_powergate_sdma(smu, gate);
 472                 if (ret)
 473                         dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
 474                                 gate ? "gate" : "ungate");
 475                 break;
 476         case AMD_IP_BLOCK_TYPE_JPEG:
 477                 ret = smu_dpm_set_jpeg_enable(smu, !gate);
 478                 if (ret)
 479                         dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
 480                                 gate ? "gate" : "ungate");
 481                 break;
 482         default:
 483                 dev_err(smu->adev->dev, "Unsupported block type!\n");
 484                 return -EINVAL;
 485         }
 486
 487         return ret;
 488 }
 489
 490 int smu_get_power_num_states(struct smu_context *smu,
 491                              struct pp_states_info *state_info)
 492 {
 493         if (!state_info)
 494                 return -EINVAL;
 495
 496         /* not support power state */
 497         memset(state_info, 0, sizeof(struct pp_states_info));
 498         state_info->nums = 1;
 499         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 500
 501         return 0;
 502 }
 503
 504 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
 505                            void *data, uint32_t *size)
 506 {
 507         struct smu_power_context *smu_power = &smu->smu_power;
 508         struct smu_power_gate *power_gate = &smu_power->power_gate;
 509         int ret = 0;
 510
 511         if(!data || !size)
 512                 return -EINVAL;
 513
 514         switch (sensor) {
 515         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
 516                 *((uint32_t *)data) = smu->pstate_sclk;
 517                 *size = 4;
 518                 break;
 519         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
 520                 *((uint32_t *)data) = smu->pstate_mclk;
 521                 *size = 4;
 522                 break;
 523         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
 524                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
 525                 *size = 8;
 526                 break;
 527         case AMDGPU_PP_SENSOR_UVD_POWER:
 528                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
 529                 *size = 4;
 530                 break;
 531         case AMDGPU_PP_SENSOR_VCE_POWER:
 532                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
 533                 *size = 4;
 534                 break;
 535         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
 536                 *(uint32_t *)data = power_gate->vcn_gated ? 0 : 1;
 537                 *size = 4;
 538                 break;
 539         default:
 540                 ret = -EINVAL;
 541                 break;
 542         }
 543
 544         if (ret)
 545                 *size = 0;
 546
 547         return ret;
 548 }
 549
 550 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
 551                      void *table_data, bool drv2smu)
 552 {
 553         struct smu_table_context *smu_table = &smu->smu_table;
 554         struct amdgpu_device *adev = smu->adev;
 555         struct smu_table *table = &smu_table->driver_table;
 556         int table_id = smu_table_get_index(smu, table_index);
 557         uint32_t table_size;
 558         int ret = 0;
 559         if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0)
 560                 return -EINVAL;
 561
 562         table_size = smu_table->tables[table_index].size;
 563
 564         if (drv2smu) {
 565                 memcpy(table->cpu_addr, table_data, table_size);
 566                 /*
 567                  * Flush hdp cache: to guard the content seen by
 568                  * GPU is consitent with CPU.
 569                  */
 570                 amdgpu_asic_flush_hdp(adev, NULL);
 571         }
 572
 573         ret = smu_send_smc_msg_with_param(smu, drv2smu ?
 574                                           SMU_MSG_TransferTableDram2Smu :
 575                                           SMU_MSG_TransferTableSmu2Dram,
 576                                           table_id | ((argument & 0xFFFF) << 16),
 577                                           NULL);
 578         if (ret)
 579                 return ret;
 580
 581         if (!drv2smu) {
 582                 amdgpu_asic_flush_hdp(adev, NULL);
 583                 memcpy(table_data, table->cpu_addr, table_size);
 584         }
 585
 586         return ret;
 587 }
 588
 589 bool is_support_sw_smu(struct amdgpu_device *adev)
 590 {
 591         if (adev->asic_type >= CHIP_ARCTURUS)
 592                 return true;
 593
 594         return false;
 595 }
 596
 597 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 598 {
 599         struct smu_table_context *smu_table = &smu->smu_table;
 600         uint32_t powerplay_table_size;
 601
 602         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 603                 return -EOPNOTSUPP;
 604
 605         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 606                 return -EINVAL;
 607
 608         mutex_lock(&smu->mutex);
 609
 610         if (smu_table->hardcode_pptable)
 611                 *table = smu_table->hardcode_pptable;
 612         else
 613                 *table = smu_table->power_play_table;
 614
 615         powerplay_table_size = smu_table->power_play_table_size;
 616
 617         mutex_unlock(&smu->mutex);
 618
 619         return powerplay_table_size;
 620 }
 621
 622 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 623 {
 624         struct smu_table_context *smu_table = &smu->smu_table;
 625         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 626         int ret = 0;
 627
 628         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 629                 return -EOPNOTSUPP;
 630
 631         if (header->usStructureSize != size) {
 632                 dev_err(smu->adev->dev, "pp table size not matched !\n");
 633                 return -EIO;
 634         }
 635
 636         mutex_lock(&smu->mutex);
 637         if (!smu_table->hardcode_pptable)
 638                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 639         if (!smu_table->hardcode_pptable) {
 640                 ret = -ENOMEM;
 641                 goto failed;
 642         }
 643
 644         memcpy(smu_table->hardcode_pptable, buf, size);
 645         smu_table->power_play_table = smu_table->hardcode_pptable;
 646         smu_table->power_play_table_size = size;
 647
 648         /*
 649          * Special hw_fini action(for Navi1x, the DPMs disablement will be
 650          * skipped) may be needed for custom pptable uploading.
 651          */
 652         smu->uploading_custom_pp_table = true;
 653
 654         ret = smu_reset(smu);
 655         if (ret)
 656                 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
 657
 658         smu->uploading_custom_pp_table = false;
 659
 660 failed:
 661         mutex_unlock(&smu->mutex);
 662         return ret;
 663 }
 664
 665 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
 666 {
 667         struct smu_feature *feature = &smu->smu_feature;
 668         int ret = 0;
 669         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 670
 671         mutex_lock(&feature->mutex);
 672         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 673         mutex_unlock(&feature->mutex);
 674
 675         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 676                                              SMU_FEATURE_MAX/32);
 677         if (ret)
 678                 return ret;
 679
 680         mutex_lock(&feature->mutex);
 681         bitmap_or(feature->allowed, feature->allowed,
 682                       (unsigned long *)allowed_feature_mask,
 683                       feature->feature_num);
 684         mutex_unlock(&feature->mutex);
 685
 686         return ret;
 687 }
 688
 689 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
 690 {
 691         struct smu_feature *feature = &smu->smu_feature;
 692         int feature_id;
 693         int ret = 0;
 694
 695         if (smu->is_apu)
 696                 return 1;
 697         feature_id = smu_feature_get_index(smu, mask);
 698         if (feature_id < 0)
 699                 return 0;
 700
 701         WARN_ON(feature_id > feature->feature_num);
 702
 703         mutex_lock(&feature->mutex);
 704         ret = test_bit(feature_id, feature->enabled);
 705         mutex_unlock(&feature->mutex);
 706
 707         return ret;
 708 }
 709
 710 int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
 711                             bool enable)
 712 {
 713         struct smu_feature *feature = &smu->smu_feature;
 714         int feature_id;
 715
 716         feature_id = smu_feature_get_index(smu, mask);
 717         if (feature_id < 0)
 718                 return -EINVAL;
 719
 720         WARN_ON(feature_id > feature->feature_num);
 721
 722         return smu_feature_update_enable_state(smu,
 723                                                1ULL << feature_id,
 724                                                enable);
 725 }
 726
 727 int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
 728 {
 729         struct smu_feature *feature = &smu->smu_feature;
 730         int feature_id;
 731         int ret = 0;
 732
 733         feature_id = smu_feature_get_index(smu, mask);
 734         if (feature_id < 0)
 735                 return 0;
 736
 737         WARN_ON(feature_id > feature->feature_num);
 738
 739         mutex_lock(&feature->mutex);
 740         ret = test_bit(feature_id, feature->supported);
 741         mutex_unlock(&feature->mutex);
 742
 743         return ret;
 744 }
 745
 746 static int smu_set_funcs(struct amdgpu_device *adev)
 747 {
 748         struct smu_context *smu = &adev->smu;
 749
 750         if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 751                 smu->od_enabled = true;
 752
 753         switch (adev->asic_type) {
 754         case CHIP_NAVI10:
 755         case CHIP_NAVI14:
 756         case CHIP_NAVI12:
 757                 navi10_set_ppt_funcs(smu);
 758                 break;
 759         case CHIP_ARCTURUS:
 760                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 761                 arcturus_set_ppt_funcs(smu);
 762                 /* OD is not supported on Arcturus */
 763                 smu->od_enabled =false;
 764                 break;
 765         case CHIP_SIENNA_CICHLID:
 766                 sienna_cichlid_set_ppt_funcs(smu);
 767                 break;
 768         case CHIP_RENOIR:
 769                 renoir_set_ppt_funcs(smu);
 770                 break;
 771         default:
 772                 return -EINVAL;
 773         }
 774
 775         return 0;
 776 }
 777
 778 static int smu_early_init(void *handle)
 779 {
 780         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 781         struct smu_context *smu = &adev->smu;
 782
 783         smu->adev = adev;
 784         smu->pm_enabled = !!amdgpu_dpm;
 785         smu->is_apu = false;
 786         mutex_init(&smu->mutex);
 787
 788         return smu_set_funcs(adev);
 789 }
 790
 791 static int smu_late_init(void *handle)
 792 {
 793         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 794         struct smu_context *smu = &adev->smu;
 795         int ret = 0;
 796
 797         if (!smu->pm_enabled)
 798                 return 0;
 799
 800         ret = smu_set_default_od_settings(smu);
 801         if (ret) {
 802                 dev_err(adev->dev, "Failed to setup default OD settings!\n");
 803                 return ret;
 804         }
 805
 806         /*
 807          * Set initialized values (get from vbios) to dpm tables context such as
 808          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
 809          * type of clks.
 810          */
 811         ret = smu_populate_smc_tables(smu);
 812         if (ret) {
 813                 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
 814                 return ret;
 815         }
 816
 817         ret = smu_init_max_sustainable_clocks(smu);
 818         if (ret) {
 819                 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
 820                 return ret;
 821         }
 822
 823         ret = smu_populate_umd_state_clk(smu);
 824         if (ret) {
 825                 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
 826                 return ret;
 827         }
 828
 829         ret = smu_get_power_limit(smu, &smu->default_power_limit, false, false);
 830         if (ret) {
 831                 dev_err(adev->dev, "Failed to get default power limit!\n");
 832                 return ret;
 833         }
 834
 835         smu_get_unique_id(smu);
 836
 837         smu_handle_task(&adev->smu,
 838                         smu->smu_dpm.dpm_level,
 839                         AMD_PP_TASK_COMPLETE_INIT,
 840                         false);
 841
 842         return 0;
 843 }
 844
 845 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
 846                             uint16_t *size, uint8_t *frev, uint8_t *crev,
 847                             uint8_t **addr)
 848 {
 849         struct amdgpu_device *adev = smu->adev;
 850         uint16_t data_start;
 851
 852         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
 853                                            size, frev, crev, &data_start))
 854                 return -EINVAL;
 855
 856         *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
 857
 858         return 0;
 859 }
 860
 861 static int smu_init_fb_allocations(struct smu_context *smu)
 862 {
 863         struct amdgpu_device *adev = smu->adev;
 864         struct smu_table_context *smu_table = &smu->smu_table;
 865         struct smu_table *tables = smu_table->tables;
 866         struct smu_table *driver_table = &(smu_table->driver_table);
 867         uint32_t max_table_size = 0;
 868         int ret, i;
 869
 870         /* VRAM allocation for tool table */
 871         if (tables[SMU_TABLE_PMSTATUSLOG].size) {
 872                 ret = amdgpu_bo_create_kernel(adev,
 873                                               tables[SMU_TABLE_PMSTATUSLOG].size,
 874                                               tables[SMU_TABLE_PMSTATUSLOG].align,
 875                                               tables[SMU_TABLE_PMSTATUSLOG].domain,
 876                                               &tables[SMU_TABLE_PMSTATUSLOG].bo,
 877                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 878                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 879                 if (ret) {
 880                         dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
 881                         return ret;
 882                 }
 883         }
 884
 885         /* VRAM allocation for driver table */
 886         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 887                 if (tables[i].size == 0)
 888                         continue;
 889
 890                 if (i == SMU_TABLE_PMSTATUSLOG)
 891                         continue;
 892
 893                 if (max_table_size < tables[i].size)
 894                         max_table_size = tables[i].size;
 895         }
 896
 897         driver_table->size = max_table_size;
 898         driver_table->align = PAGE_SIZE;
 899         driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 900
 901         ret = amdgpu_bo_create_kernel(adev,
 902                                       driver_table->size,
 903                                       driver_table->align,
 904                                       driver_table->domain,
 905                                       &driver_table->bo,
 906                                       &driver_table->mc_address,
 907                                       &driver_table->cpu_addr);
 908         if (ret) {
 909                 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
 910                 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 911                         amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 912                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 913                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 914         }
 915
 916         return ret;
 917 }
 918
 919 static int smu_fini_fb_allocations(struct smu_context *smu)
 920 {
 921         struct smu_table_context *smu_table = &smu->smu_table;
 922         struct smu_table *tables = smu_table->tables;
 923         struct smu_table *driver_table = &(smu_table->driver_table);
 924
 925         if (!tables)
 926                 return 0;
 927
 928         if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 929                 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 930                                       &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 931                                       &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 932
 933         amdgpu_bo_free_kernel(&driver_table->bo,
 934                               &driver_table->mc_address,
 935                               &driver_table->cpu_addr);
 936
 937         return 0;
 938 }
 939
 940 /**
 941  * smu_alloc_memory_pool - allocate memory pool in the system memory
 942  *
 943  * @smu: amdgpu_device pointer
 944  *
 945  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
 946  * and DramLogSetDramAddr can notify it changed.
 947  *
 948  * Returns 0 on success, error on failure.
 949  */
 950 static int smu_alloc_memory_pool(struct smu_context *smu)
 951 {
 952         struct amdgpu_device *adev = smu->adev;
 953         struct smu_table_context *smu_table = &smu->smu_table;
 954         struct smu_table *memory_pool = &smu_table->memory_pool;
 955         uint64_t pool_size = smu->pool_size;
 956         int ret = 0;
 957
 958         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
 959                 return ret;
 960
 961         memory_pool->size = pool_size;
 962         memory_pool->align = PAGE_SIZE;
 963         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
 964
 965         switch (pool_size) {
 966         case SMU_MEMORY_POOL_SIZE_256_MB:
 967         case SMU_MEMORY_POOL_SIZE_512_MB:
 968         case SMU_MEMORY_POOL_SIZE_1_GB:
 969         case SMU_MEMORY_POOL_SIZE_2_GB:
 970                 ret = amdgpu_bo_create_kernel(adev,
 971                                               memory_pool->size,
 972                                               memory_pool->align,
 973                                               memory_pool->domain,
 974                                               &memory_pool->bo,
 975                                               &memory_pool->mc_address,
 976                                               &memory_pool->cpu_addr);
 977                 if (ret)
 978                         dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
 979                 break;
 980         default:
 981                 break;
 982         }
 983
 984         return ret;
 985 }
 986
 987 static int smu_free_memory_pool(struct smu_context *smu)
 988 {
 989         struct smu_table_context *smu_table = &smu->smu_table;
 990         struct smu_table *memory_pool = &smu_table->memory_pool;
 991
 992         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
 993                 return 0;
 994
 995         amdgpu_bo_free_kernel(&memory_pool->bo,
 996                               &memory_pool->mc_address,
 997                               &memory_pool->cpu_addr);
 998
 999         memset(memory_pool, 0, sizeof(struct smu_table));
1000
1001         return 0;
1002 }
1003
1004 static int smu_smc_table_sw_init(struct smu_context *smu)
1005 {
1006         int ret;
1007
1008         /**
1009          * Create smu_table structure, and init smc tables such as
1010          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
1011          */
1012         ret = smu_init_smc_tables(smu);
1013         if (ret) {
1014                 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
1015                 return ret;
1016         }
1017
1018         /**
1019          * Create smu_power_context structure, and allocate smu_dpm_context and
1020          * context size to fill the smu_power_context data.
1021          */
1022         ret = smu_init_power(smu);
1023         if (ret) {
1024                 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
1025                 return ret;
1026         }
1027
1028         /*
1029          * allocate vram bos to store smc table contents.
1030          */
1031         ret = smu_init_fb_allocations(smu);
1032         if (ret)
1033                 return ret;
1034
1035         ret = smu_alloc_memory_pool(smu);
1036         if (ret)
1037                 return ret;
1038
1039         return 0;
1040 }
1041
1042 static int smu_smc_table_sw_fini(struct smu_context *smu)
1043 {
1044         int ret;
1045
1046         ret = smu_free_memory_pool(smu);
1047         if (ret)
1048                 return ret;
1049
1050         ret = smu_fini_fb_allocations(smu);
1051         if (ret)
1052                 return ret;
1053
1054         ret = smu_fini_power(smu);
1055         if (ret) {
1056                 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
1057                 return ret;
1058         }
1059
1060         ret = smu_fini_smc_tables(smu);
1061         if (ret) {
1062                 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
1063                 return ret;
1064         }
1065
1066         return 0;
1067 }
1068
1069 static void smu_throttling_logging_work_fn(struct work_struct *work)
1070 {
1071         struct smu_context *smu = container_of(work, struct smu_context,
1072                                                throttling_logging_work);
1073
1074         smu_log_thermal_throttling(smu);
1075 }
1076
1077 static int smu_sw_init(void *handle)
1078 {
1079         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1080         struct smu_context *smu = &adev->smu;
1081         int ret;
1082
1083         smu->pool_size = adev->pm.smu_prv_buffer_size;
1084         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
1085         mutex_init(&smu->smu_feature.mutex);
1086         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
1087         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
1088         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
1089
1090         mutex_init(&smu->smu_baco.mutex);
1091         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
1092         smu->smu_baco.platform_support = false;
1093
1094         mutex_init(&smu->sensor_lock);
1095         mutex_init(&smu->metrics_lock);
1096         mutex_init(&smu->message_lock);
1097
1098         INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
1099         smu->watermarks_bitmap = 0;
1100         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1101         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1102
1103         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
1104         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
1105         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
1106         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
1107         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
1108         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
1109         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
1110         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
1111
1112         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1113         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1114         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
1115         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
1116         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
1117         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
1118         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
1119         smu->display_config = &adev->pm.pm_display_cfg;
1120
1121         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1122         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1123         ret = smu_init_microcode(smu);
1124         if (ret) {
1125                 dev_err(adev->dev, "Failed to load smu firmware!\n");
1126                 return ret;
1127         }
1128
1129         ret = smu_smc_table_sw_init(smu);
1130         if (ret) {
1131                 dev_err(adev->dev, "Failed to sw init smc table!\n");
1132                 return ret;
1133         }
1134
1135         ret = smu_register_irq_handler(smu);
1136         if (ret) {
1137                 dev_err(adev->dev, "Failed to register smc irq handler!\n");
1138                 return ret;
1139         }
1140
1141         return 0;
1142 }
1143
1144 static int smu_sw_fini(void *handle)
1145 {
1146         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1147         struct smu_context *smu = &adev->smu;
1148         int ret;
1149
1150         ret = smu_smc_table_sw_fini(smu);
1151         if (ret) {
1152                 dev_err(adev->dev, "Failed to sw fini smc table!\n");
1153                 return ret;
1154         }
1155
1156         smu_fini_microcode(smu);
1157
1158         return 0;
1159 }
1160
1161 static int smu_smc_hw_setup(struct smu_context *smu)
1162 {
1163         struct amdgpu_device *adev = smu->adev;
1164         int ret;
1165
1166         if (smu_is_dpm_running(smu) && adev->in_suspend) {
1167                 dev_info(adev->dev, "dpm has been enabled\n");
1168                 return 0;
1169         }
1170
1171         ret = smu_init_display_count(smu, 0);
1172         if (ret) {
1173                 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
1174                 return ret;
1175         }
1176
1177         ret = smu_set_driver_table_location(smu);
1178         if (ret) {
1179                 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
1180                 return ret;
1181         }
1182
1183         /*
1184          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1185          */
1186         ret = smu_set_tool_table_location(smu);
1187         if (ret) {
1188                 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
1189                 return ret;
1190         }
1191
1192         /*
1193          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1194          * pool location.
1195          */
1196         ret = smu_notify_memory_pool_location(smu);
1197         if (ret) {
1198                 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
1199                 return ret;
1200         }
1201
1202         /* smu_dump_pptable(smu); */
1203         /*
1204          * Copy pptable bo in the vram to smc with SMU MSGs such as
1205          * SetDriverDramAddr and TransferTableDram2Smu.
1206          */
1207         ret = smu_write_pptable(smu);
1208         if (ret) {
1209                 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
1210                 return ret;
1211         }
1212
1213         /* issue Run*Btc msg */
1214         ret = smu_run_btc(smu);
1215         if (ret)
1216                 return ret;
1217
1218         ret = smu_feature_set_allowed_mask(smu);
1219         if (ret) {
1220                 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
1221                 return ret;
1222         }
1223
1224         ret = smu_system_features_control(smu, true);
1225         if (ret) {
1226                 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
1227                 return ret;
1228         }
1229
1230         if (!smu_is_dpm_running(smu))
1231                 dev_info(adev->dev, "dpm has been disabled\n");
1232
1233         ret = smu_override_pcie_parameters(smu);
1234         if (ret)
1235                 return ret;
1236
1237         ret = smu_enable_thermal_alert(smu);
1238         if (ret) {
1239                 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1240                 return ret;
1241         }
1242
1243         ret = smu_i2c_eeprom_init(smu, &adev->pm.smu_i2c);
1244         if (ret)
1245                 return ret;
1246
1247         ret = smu_disable_umc_cdr_12gbps_workaround(smu);
1248         if (ret) {
1249                 dev_err(adev->dev, "Workaround failed to disable UMC CDR feature on 12Gbps SKU!\n");
1250                 return ret;
1251         }
1252
1253         /*
1254          * For Navi1X, manually switch it to AC mode as PMFW
1255          * may boot it with DC mode.
1256          */
1257         ret = smu_set_power_source(smu,
1258                                    adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
1259                                    SMU_POWER_SOURCE_DC);
1260         if (ret) {
1261                 dev_err(adev->dev, "Failed to switch to %s mode!\n", adev->pm.ac_power ? "AC" : "DC");
1262                 return ret;
1263         }
1264
1265         ret = smu_notify_display_change(smu);
1266         if (ret)
1267                 return ret;
1268
1269         /*
1270          * Set min deep sleep dce fclk with bootup value from vbios via
1271          * SetMinDeepSleepDcefclk MSG.
1272          */
1273         ret = smu_set_min_dcef_deep_sleep(smu);
1274         if (ret)
1275                 return ret;
1276
1277         return ret;
1278 }
1279
1280 static int smu_start_smc_engine(struct smu_context *smu)
1281 {
1282         struct amdgpu_device *adev = smu->adev;
1283         int ret = 0;
1284
1285         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1286                 if (adev->asic_type < CHIP_NAVI10) {
1287                         if (smu->ppt_funcs->load_microcode) {
1288                                 ret = smu->ppt_funcs->load_microcode(smu);
1289                                 if (ret)
1290                                         return ret;
1291                         }
1292                 }
1293         }
1294
1295         if (smu->ppt_funcs->check_fw_status) {
1296                 ret = smu->ppt_funcs->check_fw_status(smu);
1297                 if (ret) {
1298                         dev_err(adev->dev, "SMC is not ready\n");
1299                         return ret;
1300                 }
1301         }
1302
1303         /*
1304          * Send msg GetDriverIfVersion to check if the return value is equal
1305          * with DRIVER_IF_VERSION of smc header.
1306          */
1307         ret = smu_check_fw_version(smu);
1308         if (ret)
1309                 return ret;
1310
1311         return ret;
1312 }
1313
1314 static int smu_hw_init(void *handle)
1315 {
1316         int ret;
1317         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1318         struct smu_context *smu = &adev->smu;
1319
1320         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1321                 return 0;
1322
1323         ret = smu_start_smc_engine(smu);
1324         if (ret) {
1325                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1326                 return ret;
1327         }
1328
1329         if (smu->is_apu) {
1330                 smu_powergate_sdma(&adev->smu, false);
1331                 smu_powergate_vcn(&adev->smu, false);
1332                 smu_powergate_jpeg(&adev->smu, false);
1333                 smu_set_gfx_cgpg(&adev->smu, true);
1334         }
1335
1336         if (!smu->pm_enabled)
1337                 return 0;
1338
1339         /* get boot_values from vbios to set revision, gfxclk, and etc. */
1340         ret = smu_get_vbios_bootup_values(smu);
1341         if (ret) {
1342                 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1343                 return ret;
1344         }
1345
1346         ret = smu_setup_pptable(smu);
1347         if (ret) {
1348                 dev_err(adev->dev, "Failed to setup pptable!\n");
1349                 return ret;
1350         }
1351
1352         ret = smu_get_driver_allowed_feature_mask(smu);
1353         if (ret)
1354                 return ret;
1355
1356         ret = smu_smc_hw_setup(smu);
1357         if (ret) {
1358                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1359                 return ret;
1360         }
1361
1362         adev->pm.dpm_enabled = true;
1363
1364         dev_info(adev->dev, "SMU is initialized successfully!\n");
1365
1366         return 0;
1367 }
1368
1369 static int smu_disable_dpms(struct smu_context *smu)
1370 {
1371         struct amdgpu_device *adev = smu->adev;
1372         uint64_t features_to_disable;
1373         int ret = 0;
1374         bool use_baco = !smu->is_apu &&
1375                 ((adev->in_gpu_reset &&
1376                   (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1377                  ((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev)));
1378
1379         /*
1380          * For custom pptable uploading, skip the DPM features
1381          * disable process on Navi1x ASICs.
1382          *   - As the gfx related features are under control of
1383          *     RLC on those ASICs. RLC reinitialization will be
1384          *     needed to reenable them. That will cost much more
1385          *     efforts.
1386          *
1387          *   - SMU firmware can handle the DPM reenablement
1388          *     properly.
1389          */
1390         if (smu->uploading_custom_pp_table &&
1391             (adev->asic_type >= CHIP_NAVI10) &&
1392             (adev->asic_type <= CHIP_NAVI12))
1393                 return 0;
1394
1395         /*
1396          * For Sienna_Cichlid, PMFW will handle the features disablement properly
1397          * on BACO in. Driver involvement is unnecessary.
1398          */
1399         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1400              use_baco)
1401                 return 0;
1402
1403         /*
1404          * For gpu reset, runpm and hibernation through BACO,
1405          * BACO feature has to be kept enabled.
1406          */
1407         if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1408                 features_to_disable = U64_MAX &
1409                         ~(1ULL << smu_feature_get_index(smu, SMU_FEATURE_BACO_BIT));
1410                 ret = smu_feature_update_enable_state(smu,
1411                                                       features_to_disable,
1412                                                       0);
1413                 if (ret)
1414                         dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1415         } else {
1416                 ret = smu_system_features_control(smu, false);
1417                 if (ret)
1418                         dev_err(adev->dev, "Failed to disable smu features.\n");
1419         }
1420
1421         if (adev->asic_type >= CHIP_NAVI10 &&
1422             adev->gfx.rlc.funcs->stop)
1423                 adev->gfx.rlc.funcs->stop(adev);
1424
1425         return ret;
1426 }
1427
1428 static int smu_smc_hw_cleanup(struct smu_context *smu)
1429 {
1430         struct amdgpu_device *adev = smu->adev;
1431         int ret = 0;
1432
1433         smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);
1434
1435         cancel_work_sync(&smu->throttling_logging_work);
1436
1437         ret = smu_disable_thermal_alert(smu);
1438         if (ret) {
1439                 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1440                 return ret;
1441         }
1442
1443         ret = smu_disable_dpms(smu);
1444         if (ret) {
1445                 dev_err(adev->dev, "Fail to disable dpm features!\n");
1446                 return ret;
1447         }
1448
1449         return 0;
1450 }
1451
1452 static int smu_hw_fini(void *handle)
1453 {
1454         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1455         struct smu_context *smu = &adev->smu;
1456         int ret = 0;
1457
1458         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1459                 return 0;
1460
1461         if (smu->is_apu) {
1462                 smu_powergate_sdma(&adev->smu, true);
1463                 smu_powergate_vcn(&adev->smu, true);
1464                 smu_powergate_jpeg(&adev->smu, true);
1465         }
1466
1467         if (!smu->pm_enabled)
1468                 return 0;
1469
1470         adev->pm.dpm_enabled = false;
1471
1472         ret = smu_smc_hw_cleanup(smu);
1473         if (ret)
1474                 return ret;
1475
1476         return 0;
1477 }
1478
1479 int smu_reset(struct smu_context *smu)
1480 {
1481         struct amdgpu_device *adev = smu->adev;
1482         int ret = 0;
1483
1484         ret = smu_hw_fini(adev);
1485         if (ret)
1486                 return ret;
1487
1488         ret = smu_hw_init(adev);
1489         if (ret)
1490                 return ret;
1491
1492         ret = smu_late_init(adev);
1493
1494         return ret;
1495 }
1496
1497 static int smu_suspend(void *handle)
1498 {
1499         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1500         struct smu_context *smu = &adev->smu;
1501         int ret;
1502
1503         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1504                 return 0;
1505
1506         if (!smu->pm_enabled)
1507                 return 0;
1508
1509         adev->pm.dpm_enabled = false;
1510
1511         ret = smu_smc_hw_cleanup(smu);
1512         if (ret)
1513                 return ret;
1514
1515         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1516
1517         if (smu->is_apu)
1518                 smu_set_gfx_cgpg(&adev->smu, false);
1519
1520         return 0;
1521 }
1522
1523 static int smu_resume(void *handle)
1524 {
1525         int ret;
1526         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1527         struct smu_context *smu = &adev->smu;
1528
1529         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1530                 return 0;
1531
1532         if (!smu->pm_enabled)
1533                 return 0;
1534
1535         dev_info(adev->dev, "SMU is resuming...\n");
1536
1537         ret = smu_start_smc_engine(smu);
1538         if (ret) {
1539                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1540                 return ret;
1541         }
1542
1543         ret = smu_smc_hw_setup(smu);
1544         if (ret) {
1545                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1546                 return ret;
1547         }
1548
1549         if (smu->is_apu)
1550                 smu_set_gfx_cgpg(&adev->smu, true);
1551
1552         smu->disable_uclk_switch = 0;
1553
1554         adev->pm.dpm_enabled = true;
1555
1556         dev_info(adev->dev, "SMU is resumed successfully!\n");
1557
1558         return 0;
1559 }
1560
1561 int smu_display_configuration_change(struct smu_context *smu,
1562                                      const struct amd_pp_display_configuration *display_config)
1563 {
1564         int index = 0;
1565         int num_of_active_display = 0;
1566
1567         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1568                 return -EOPNOTSUPP;
1569
1570         if (!display_config)
1571                 return -EINVAL;
1572
1573         mutex_lock(&smu->mutex);
1574
1575         if (smu->ppt_funcs->set_deep_sleep_dcefclk)
1576                 smu->ppt_funcs->set_deep_sleep_dcefclk(smu,
1577                                 display_config->min_dcef_deep_sleep_set_clk / 100);
1578
1579         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1580                 if (display_config->displays[index].controller_id != 0)
1581                         num_of_active_display++;
1582         }
1583
1584         smu_set_active_display_count(smu, num_of_active_display);
1585
1586         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1587                            display_config->cpu_cc6_disable,
1588                            display_config->cpu_pstate_disable,
1589                            display_config->nb_pstate_switch_disable);
1590
1591         mutex_unlock(&smu->mutex);
1592
1593         return 0;
1594 }
1595
1596 static int smu_get_clock_info(struct smu_context *smu,
1597                               struct smu_clock_info *clk_info,
1598                               enum smu_perf_level_designation designation)
1599 {
1600         int ret;
1601         struct smu_performance_level level = {0};
1602
1603         if (!clk_info)
1604                 return -EINVAL;
1605
1606         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1607         if (ret)
1608                 return -EINVAL;
1609
1610         clk_info->min_mem_clk = level.memory_clock;
1611         clk_info->min_eng_clk = level.core_clock;
1612         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1613
1614         ret = smu_get_perf_level(smu, designation, &level);
1615         if (ret)
1616                 return -EINVAL;
1617
1618         clk_info->min_mem_clk = level.memory_clock;
1619         clk_info->min_eng_clk = level.core_clock;
1620         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1621
1622         return 0;
1623 }
1624
1625 int smu_get_current_clocks(struct smu_context *smu,
1626                            struct amd_pp_clock_info *clocks)
1627 {
1628         struct amd_pp_simple_clock_info simple_clocks = {0};
1629         struct smu_clock_info hw_clocks;
1630         int ret = 0;
1631
1632         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1633                 return -EOPNOTSUPP;
1634
1635         mutex_lock(&smu->mutex);
1636
1637         smu_get_dal_power_level(smu, &simple_clocks);
1638
1639         if (smu->support_power_containment)
1640                 ret = smu_get_clock_info(smu, &hw_clocks,
1641                                          PERF_LEVEL_POWER_CONTAINMENT);
1642         else
1643                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1644
1645         if (ret) {
1646                 dev_err(smu->adev->dev, "Error in smu_get_clock_info\n");
1647                 goto failed;
1648         }
1649
1650         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1651         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1652         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1653         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1654         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1655         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1656         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1657         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1658
1659         if (simple_clocks.level == 0)
1660                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1661         else
1662                 clocks->max_clocks_state = simple_clocks.level;
1663
1664         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1665                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1666                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1667         }
1668
1669 failed:
1670         mutex_unlock(&smu->mutex);
1671         return ret;
1672 }
1673
1674 static int smu_set_clockgating_state(void *handle,
1675                                      enum amd_clockgating_state state)
1676 {
1677         return 0;
1678 }
1679
1680 static int smu_set_powergating_state(void *handle,
1681                                      enum amd_powergating_state state)
1682 {
1683         return 0;
1684 }
1685
1686 static int smu_enable_umd_pstate(void *handle,
1687                       enum amd_dpm_forced_level *level)
1688 {
1689         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1690                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1691                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1692                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1693
1694         struct smu_context *smu = (struct smu_context*)(handle);
1695         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1696
1697         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1698                 return -EINVAL;
1699
1700         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1701                 /* enter umd pstate, save current level, disable gfx cg*/
1702                 if (*level & profile_mode_mask) {
1703                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1704                         smu_dpm_ctx->enable_umd_pstate = true;
1705                         amdgpu_device_ip_set_powergating_state(smu->adev,
1706                                                                AMD_IP_BLOCK_TYPE_GFX,
1707                                                                AMD_PG_STATE_UNGATE);
1708                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1709                                                                AMD_IP_BLOCK_TYPE_GFX,
1710                                                                AMD_CG_STATE_UNGATE);
1711                 }
1712         } else {
1713                 /* exit umd pstate, restore level, enable gfx cg*/
1714                 if (!(*level & profile_mode_mask)) {
1715                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1716                                 *level = smu_dpm_ctx->saved_dpm_level;
1717                         smu_dpm_ctx->enable_umd_pstate = false;
1718                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1719                                                                AMD_IP_BLOCK_TYPE_GFX,
1720                                                                AMD_CG_STATE_GATE);
1721                         amdgpu_device_ip_set_powergating_state(smu->adev,
1722                                                                AMD_IP_BLOCK_TYPE_GFX,
1723                                                                AMD_PG_STATE_GATE);
1724                 }
1725         }
1726
1727         return 0;
1728 }
1729
1730 int smu_adjust_power_state_dynamic(struct smu_context *smu,
1731                                    enum amd_dpm_forced_level level,
1732                                    bool skip_display_settings)
1733 {
1734         int ret = 0;
1735         int index = 0;
1736         long workload;
1737         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1738
1739         if (!skip_display_settings) {
1740                 ret = smu_display_config_changed(smu);
1741                 if (ret) {
1742                         dev_err(smu->adev->dev, "Failed to change display config!");
1743                         return ret;
1744                 }
1745         }
1746
1747         ret = smu_apply_clocks_adjust_rules(smu);
1748         if (ret) {
1749                 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1750                 return ret;
1751         }
1752
1753         if (!skip_display_settings) {
1754                 ret = smu_notify_smc_display_config(smu);
1755                 if (ret) {
1756                         dev_err(smu->adev->dev, "Failed to notify smc display config!");
1757                         return ret;
1758                 }
1759         }
1760
1761         if (smu_dpm_ctx->dpm_level != level) {
1762                 ret = smu_asic_set_performance_level(smu, level);
1763                 if (ret) {
1764                         dev_err(smu->adev->dev, "Failed to set performance level!");
1765                         return ret;
1766                 }
1767
1768                 /* update the saved copy */
1769                 smu_dpm_ctx->dpm_level = level;
1770         }
1771
1772         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1773                 index = fls(smu->workload_mask);
1774                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1775                 workload = smu->workload_setting[index];
1776
1777                 if (smu->power_profile_mode != workload)
1778                         smu_set_power_profile_mode(smu, &workload, 0, false);
1779         }
1780
1781         return ret;
1782 }
1783
1784 int smu_handle_task(struct smu_context *smu,
1785                     enum amd_dpm_forced_level level,
1786                     enum amd_pp_task task_id,
1787                     bool lock_needed)
1788 {
1789         int ret = 0;
1790
1791         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1792                 return -EOPNOTSUPP;
1793
1794         if (lock_needed)
1795                 mutex_lock(&smu->mutex);
1796
1797         switch (task_id) {
1798         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1799                 ret = smu_pre_display_config_changed(smu);
1800                 if (ret)
1801                         goto out;
1802                 ret = smu_set_cpu_power_state(smu);
1803                 if (ret)
1804                         goto out;
1805                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1806                 break;
1807         case AMD_PP_TASK_COMPLETE_INIT:
1808         case AMD_PP_TASK_READJUST_POWER_STATE:
1809                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1810                 break;
1811         default:
1812                 break;
1813         }
1814
1815 out:
1816         if (lock_needed)
1817                 mutex_unlock(&smu->mutex);
1818
1819         return ret;
1820 }
1821
1822 int smu_switch_power_profile(struct smu_context *smu,
1823                              enum PP_SMC_POWER_PROFILE type,
1824                              bool en)
1825 {
1826         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1827         long workload;
1828         uint32_t index;
1829
1830         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1831                 return -EOPNOTSUPP;
1832
1833         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1834                 return -EINVAL;
1835
1836         mutex_lock(&smu->mutex);
1837
1838         if (!en) {
1839                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1840                 index = fls(smu->workload_mask);
1841                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1842                 workload = smu->workload_setting[index];
1843         } else {
1844                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1845                 index = fls(smu->workload_mask);
1846                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1847                 workload = smu->workload_setting[index];
1848         }
1849
1850         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1851                 smu_set_power_profile_mode(smu, &workload, 0, false);
1852
1853         mutex_unlock(&smu->mutex);
1854
1855         return 0;
1856 }
1857
1858 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1859 {
1860         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1861         enum amd_dpm_forced_level level;
1862
1863         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1864                 return -EOPNOTSUPP;
1865
1866         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1867                 return -EINVAL;
1868
1869         mutex_lock(&(smu->mutex));
1870         level = smu_dpm_ctx->dpm_level;
1871         mutex_unlock(&(smu->mutex));
1872
1873         return level;
1874 }
1875
1876 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1877 {
1878         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1879         int ret = 0;
1880
1881         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1882                 return -EOPNOTSUPP;
1883
1884         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1885                 return -EINVAL;
1886
1887         mutex_lock(&smu->mutex);
1888
1889         ret = smu_enable_umd_pstate(smu, &level);
1890         if (ret) {
1891                 mutex_unlock(&smu->mutex);
1892                 return ret;
1893         }
1894
1895         ret = smu_handle_task(smu, level,
1896                               AMD_PP_TASK_READJUST_POWER_STATE,
1897                               false);
1898
1899         mutex_unlock(&smu->mutex);
1900
1901         return ret;
1902 }
1903
1904 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1905 {
1906         int ret = 0;
1907
1908         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1909                 return -EOPNOTSUPP;
1910
1911         mutex_lock(&smu->mutex);
1912         ret = smu_init_display_count(smu, count);
1913         mutex_unlock(&smu->mutex);
1914
1915         return ret;
1916 }
1917
1918 int smu_force_clk_levels(struct smu_context *smu,
1919                          enum smu_clk_type clk_type,
1920                          uint32_t mask,
1921                          bool lock_needed)
1922 {
1923         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1924         int ret = 0;
1925
1926         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1927                 return -EOPNOTSUPP;
1928
1929         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1930                 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1931                 return -EINVAL;
1932         }
1933
1934         if (lock_needed)
1935                 mutex_lock(&smu->mutex);
1936
1937         if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
1938                 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1939
1940         if (lock_needed)
1941                 mutex_unlock(&smu->mutex);
1942
1943         return ret;
1944 }
1945
1946 /*
1947  * On system suspending or resetting, the dpm_enabled
1948  * flag will be cleared. So that those SMU services which
1949  * are not supported will be gated.
1950  * However, the mp1 state setting should still be granted
1951  * even if the dpm_enabled cleared.
1952  */
1953 int smu_set_mp1_state(struct smu_context *smu,
1954                       enum pp_mp1_state mp1_state)
1955 {
1956         uint16_t msg;
1957         int ret;
1958
1959         if (!smu->pm_enabled)
1960                 return -EOPNOTSUPP;
1961
1962         mutex_lock(&smu->mutex);
1963
1964         switch (mp1_state) {
1965         case PP_MP1_STATE_SHUTDOWN:
1966                 msg = SMU_MSG_PrepareMp1ForShutdown;
1967                 break;
1968         case PP_MP1_STATE_UNLOAD:
1969                 msg = SMU_MSG_PrepareMp1ForUnload;
1970                 break;
1971         case PP_MP1_STATE_RESET:
1972                 msg = SMU_MSG_PrepareMp1ForReset;
1973                 break;
1974         case PP_MP1_STATE_NONE:
1975         default:
1976                 mutex_unlock(&smu->mutex);
1977                 return 0;
1978         }
1979
1980         /* some asics may not support those messages */
1981         if (smu_msg_get_index(smu, msg) < 0) {
1982                 mutex_unlock(&smu->mutex);
1983                 return 0;
1984         }
1985
1986         ret = smu_send_smc_msg(smu, msg, NULL);
1987         if (ret)
1988                 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
1989
1990         mutex_unlock(&smu->mutex);
1991
1992         return ret;
1993 }
1994
1995 int smu_set_df_cstate(struct smu_context *smu,
1996                       enum pp_df_cstate state)
1997 {
1998         int ret = 0;
1999
2000         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2001                 return -EOPNOTSUPP;
2002
2003         if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
2004                 return 0;
2005
2006         mutex_lock(&smu->mutex);
2007
2008         ret = smu->ppt_funcs->set_df_cstate(smu, state);
2009         if (ret)
2010                 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
2011
2012         mutex_unlock(&smu->mutex);
2013
2014         return ret;
2015 }
2016
2017 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
2018 {
2019         int ret = 0;
2020
2021         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2022                 return -EOPNOTSUPP;
2023
2024         if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
2025                 return 0;
2026
2027         mutex_lock(&smu->mutex);
2028
2029         ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
2030         if (ret)
2031                 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
2032
2033         mutex_unlock(&smu->mutex);
2034
2035         return ret;
2036 }
2037
2038 int smu_write_watermarks_table(struct smu_context *smu)
2039 {
2040         void *watermarks_table = smu->smu_table.watermarks_table;
2041
2042         if (!watermarks_table)
2043                 return -EINVAL;
2044
2045         return smu_update_table(smu,
2046                                 SMU_TABLE_WATERMARKS,
2047                                 0,
2048                                 watermarks_table,
2049                                 true);
2050 }
2051
2052 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
2053                 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
2054 {
2055         void *table = smu->smu_table.watermarks_table;
2056
2057         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2058                 return -EOPNOTSUPP;
2059
2060         if (!table)
2061                 return -EINVAL;
2062
2063         mutex_lock(&smu->mutex);
2064
2065         if (!smu->disable_watermark &&
2066                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
2067                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
2068                 smu_set_watermarks_table(smu, table, clock_ranges);
2069
2070                 if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
2071                         smu->watermarks_bitmap |= WATERMARKS_EXIST;
2072                         smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
2073                 }
2074         }
2075
2076         mutex_unlock(&smu->mutex);
2077
2078         return 0;
2079 }
2080
2081 int smu_set_ac_dc(struct smu_context *smu)
2082 {
2083         int ret = 0;
2084
2085         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2086                 return -EOPNOTSUPP;
2087
2088         /* controlled by firmware */
2089         if (smu->dc_controlled_by_gpio)
2090                 return 0;
2091
2092         mutex_lock(&smu->mutex);
2093         ret = smu_set_power_source(smu,
2094                                    smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
2095                                    SMU_POWER_SOURCE_DC);
2096         if (ret)
2097                 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
2098                        smu->adev->pm.ac_power ? "AC" : "DC");
2099         mutex_unlock(&smu->mutex);
2100
2101         return ret;
2102 }
2103
2104 const struct amd_ip_funcs smu_ip_funcs = {
2105         .name = "smu",
2106         .early_init = smu_early_init,
2107         .late_init = smu_late_init,
2108         .sw_init = smu_sw_init,
2109         .sw_fini = smu_sw_fini,
2110         .hw_init = smu_hw_init,
2111         .hw_fini = smu_hw_fini,
2112         .suspend = smu_suspend,
2113         .resume = smu_resume,
2114         .is_idle = NULL,
2115         .check_soft_reset = NULL,
2116         .wait_for_idle = NULL,
2117         .soft_reset = NULL,
2118         .set_clockgating_state = smu_set_clockgating_state,
2119         .set_powergating_state = smu_set_powergating_state,
2120         .enable_umd_pstate = smu_enable_umd_pstate,
2121 };
2122
2123 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
2124 {
2125         .type = AMD_IP_BLOCK_TYPE_SMC,
2126         .major = 11,
2127         .minor = 0,
2128         .rev = 0,
2129         .funcs = &smu_ip_funcs,
2130 };
2131
2132 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
2133 {
2134         .type = AMD_IP_BLOCK_TYPE_SMC,
2135         .major = 12,
2136         .minor = 0,
2137         .rev = 0,
2138         .funcs = &smu_ip_funcs,
2139 };
2140
2141 int smu_load_microcode(struct smu_context *smu)
2142 {
2143         int ret = 0;
2144
2145         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2146                 return -EOPNOTSUPP;
2147
2148         mutex_lock(&smu->mutex);
2149
2150         if (smu->ppt_funcs->load_microcode)
2151                 ret = smu->ppt_funcs->load_microcode(smu);
2152
2153         mutex_unlock(&smu->mutex);
2154
2155         return ret;
2156 }
2157
2158 int smu_check_fw_status(struct smu_context *smu)
2159 {
2160         int ret = 0;
2161
2162         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2163                 return -EOPNOTSUPP;
2164
2165         mutex_lock(&smu->mutex);
2166
2167         if (smu->ppt_funcs->check_fw_status)
2168                 ret = smu->ppt_funcs->check_fw_status(smu);
2169
2170         mutex_unlock(&smu->mutex);
2171
2172         return ret;
2173 }
2174
2175 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2176 {
2177         int ret = 0;
2178
2179         mutex_lock(&smu->mutex);
2180
2181         if (smu->ppt_funcs->set_gfx_cgpg)
2182                 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2183
2184         mutex_unlock(&smu->mutex);
2185
2186         return ret;
2187 }
2188
2189 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
2190 {
2191         int ret = 0;
2192
2193         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2194                 return -EOPNOTSUPP;
2195
2196         mutex_lock(&smu->mutex);
2197
2198         if (smu->ppt_funcs->set_fan_speed_rpm)
2199                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2200
2201         mutex_unlock(&smu->mutex);
2202
2203         return ret;
2204 }
2205
2206 int smu_get_power_limit(struct smu_context *smu,
2207                         uint32_t *limit,
2208                         bool def,
2209                         bool lock_needed)
2210 {
2211         int ret = 0;
2212
2213         if (lock_needed) {
2214                 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2215                         return -EOPNOTSUPP;
2216
2217                 mutex_lock(&smu->mutex);
2218         }
2219
2220         if (smu->ppt_funcs->get_power_limit)
2221                 ret = smu->ppt_funcs->get_power_limit(smu, limit, def);
2222
2223         if (lock_needed)
2224                 mutex_unlock(&smu->mutex);
2225
2226         return ret;
2227 }
2228
2229 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
2230 {
2231         int ret = 0;
2232
2233         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2234                 return -EOPNOTSUPP;
2235
2236         mutex_lock(&smu->mutex);
2237
2238         if (smu->ppt_funcs->set_power_limit)
2239                 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2240
2241         mutex_unlock(&smu->mutex);
2242
2243         return ret;
2244 }
2245
2246 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2247 {
2248         int ret = 0;
2249
2250         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2251                 return -EOPNOTSUPP;
2252
2253         mutex_lock(&smu->mutex);
2254
2255         if (smu->ppt_funcs->print_clk_levels)
2256                 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2257
2258         mutex_unlock(&smu->mutex);
2259
2260         return ret;
2261 }
2262
2263 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
2264 {
2265         int ret = 0;
2266
2267         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2268                 return -EOPNOTSUPP;
2269
2270         mutex_lock(&smu->mutex);
2271
2272         if (smu->ppt_funcs->get_od_percentage)
2273                 ret = smu->ppt_funcs->get_od_percentage(smu, type);
2274
2275         mutex_unlock(&smu->mutex);
2276
2277         return ret;
2278 }
2279
2280 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
2281 {
2282         int ret = 0;
2283
2284         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2285                 return -EOPNOTSUPP;
2286
2287         mutex_lock(&smu->mutex);
2288
2289         if (smu->ppt_funcs->set_od_percentage)
2290                 ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
2291
2292         mutex_unlock(&smu->mutex);
2293
2294         return ret;
2295 }
2296
2297 int smu_od_edit_dpm_table(struct smu_context *smu,
2298                           enum PP_OD_DPM_TABLE_COMMAND type,
2299                           long *input, uint32_t size)
2300 {
2301         int ret = 0;
2302
2303         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2304                 return -EOPNOTSUPP;
2305
2306         mutex_lock(&smu->mutex);
2307
2308         if (smu->ppt_funcs->od_edit_dpm_table)
2309                 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2310
2311         mutex_unlock(&smu->mutex);
2312
2313         return ret;
2314 }
2315
2316 int smu_read_sensor(struct smu_context *smu,
2317                     enum amd_pp_sensors sensor,
2318                     void *data, uint32_t *size)
2319 {
2320         int ret = 0;
2321
2322         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2323                 return -EOPNOTSUPP;
2324
2325         mutex_lock(&smu->mutex);
2326
2327         if (smu->ppt_funcs->read_sensor)
2328                 ret = smu->ppt_funcs->read_sensor(smu, sensor, data, size);
2329
2330         mutex_unlock(&smu->mutex);
2331
2332         return ret;
2333 }
2334
2335 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2336 {
2337         int ret = 0;
2338
2339         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2340                 return -EOPNOTSUPP;
2341
2342         mutex_lock(&smu->mutex);
2343
2344         if (smu->ppt_funcs->get_power_profile_mode)
2345                 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2346
2347         mutex_unlock(&smu->mutex);
2348
2349         return ret;
2350 }
2351
2352 int smu_set_power_profile_mode(struct smu_context *smu,
2353                                long *param,
2354                                uint32_t param_size,
2355                                bool lock_needed)
2356 {
2357         int ret = 0;
2358
2359         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2360                 return -EOPNOTSUPP;
2361
2362         if (lock_needed)
2363                 mutex_lock(&smu->mutex);
2364
2365         if (smu->ppt_funcs->set_power_profile_mode)
2366                 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2367
2368         if (lock_needed)
2369                 mutex_unlock(&smu->mutex);
2370
2371         return ret;
2372 }
2373
2374
2375 int smu_get_fan_control_mode(struct smu_context *smu)
2376 {
2377         int ret = 0;
2378
2379         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2380                 return -EOPNOTSUPP;
2381
2382         mutex_lock(&smu->mutex);
2383
2384         if (smu->ppt_funcs->get_fan_control_mode)
2385                 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2386
2387         mutex_unlock(&smu->mutex);
2388
2389         return ret;
2390 }
2391
2392 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2393 {
2394         int ret = 0;
2395
2396         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2397                 return -EOPNOTSUPP;
2398
2399         mutex_lock(&smu->mutex);
2400
2401         if (smu->ppt_funcs->set_fan_control_mode)
2402                 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2403
2404         mutex_unlock(&smu->mutex);
2405
2406         return ret;
2407 }
2408
2409 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2410 {
2411         int ret = 0;
2412
2413         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2414                 return -EOPNOTSUPP;
2415
2416         mutex_lock(&smu->mutex);
2417
2418         if (smu->ppt_funcs->get_fan_speed_percent)
2419                 ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
2420
2421         mutex_unlock(&smu->mutex);
2422
2423         return ret;
2424 }
2425
2426 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2427 {
2428         int ret = 0;
2429
2430         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2431                 return -EOPNOTSUPP;
2432
2433         mutex_lock(&smu->mutex);
2434
2435         if (smu->ppt_funcs->set_fan_speed_percent)
2436                 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
2437
2438         mutex_unlock(&smu->mutex);
2439
2440         return ret;
2441 }
2442
2443 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2444 {
2445         int ret = 0;
2446
2447         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2448                 return -EOPNOTSUPP;
2449
2450         mutex_lock(&smu->mutex);
2451
2452         if (smu->ppt_funcs->get_fan_speed_rpm)
2453                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2454
2455         mutex_unlock(&smu->mutex);
2456
2457         return ret;
2458 }
2459
2460 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2461 {
2462         int ret = 0;
2463
2464         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2465                 return -EOPNOTSUPP;
2466
2467         mutex_lock(&smu->mutex);
2468
2469         if (smu->ppt_funcs->set_deep_sleep_dcefclk)
2470                 ret = smu->ppt_funcs->set_deep_sleep_dcefclk(smu, clk);
2471
2472         mutex_unlock(&smu->mutex);
2473
2474         return ret;
2475 }
2476
2477 int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
2478 {
2479         int ret = 0;
2480
2481         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2482                 return -EOPNOTSUPP;
2483
2484         if (smu->ppt_funcs->set_active_display_count)
2485                 ret = smu->ppt_funcs->set_active_display_count(smu, count);
2486
2487         return ret;
2488 }
2489
2490 int smu_get_clock_by_type(struct smu_context *smu,
2491                           enum amd_pp_clock_type type,
2492                           struct amd_pp_clocks *clocks)
2493 {
2494         int ret = 0;
2495
2496         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2497                 return -EOPNOTSUPP;
2498
2499         mutex_lock(&smu->mutex);
2500
2501         if (smu->ppt_funcs->get_clock_by_type)
2502                 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
2503
2504         mutex_unlock(&smu->mutex);
2505
2506         return ret;
2507 }
2508
2509 int smu_get_max_high_clocks(struct smu_context *smu,
2510                             struct amd_pp_simple_clock_info *clocks)
2511 {
2512         int ret = 0;
2513
2514         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2515                 return -EOPNOTSUPP;
2516
2517         mutex_lock(&smu->mutex);
2518
2519         if (smu->ppt_funcs->get_max_high_clocks)
2520                 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
2521
2522         mutex_unlock(&smu->mutex);
2523
2524         return ret;
2525 }
2526
2527 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2528                                        enum smu_clk_type clk_type,
2529                                        struct pp_clock_levels_with_latency *clocks)
2530 {
2531         int ret = 0;
2532
2533         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2534                 return -EOPNOTSUPP;
2535
2536         mutex_lock(&smu->mutex);
2537
2538         if (smu->ppt_funcs->get_clock_by_type_with_latency)
2539                 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2540
2541         mutex_unlock(&smu->mutex);
2542
2543         return ret;
2544 }
2545
2546 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
2547                                        enum amd_pp_clock_type type,
2548                                        struct pp_clock_levels_with_voltage *clocks)
2549 {
2550         int ret = 0;
2551
2552         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2553                 return -EOPNOTSUPP;
2554
2555         mutex_lock(&smu->mutex);
2556
2557         if (smu->ppt_funcs->get_clock_by_type_with_voltage)
2558                 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
2559
2560         mutex_unlock(&smu->mutex);
2561
2562         return ret;
2563 }
2564
2565
2566 int smu_display_clock_voltage_request(struct smu_context *smu,
2567                                       struct pp_display_clock_request *clock_req)
2568 {
2569         int ret = 0;
2570
2571         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2572                 return -EOPNOTSUPP;
2573
2574         mutex_lock(&smu->mutex);
2575
2576         if (smu->ppt_funcs->display_clock_voltage_request)
2577                 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2578
2579         mutex_unlock(&smu->mutex);
2580
2581         return ret;
2582 }
2583
2584
2585 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2586 {
2587         int ret = -EINVAL;
2588
2589         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2590                 return -EOPNOTSUPP;
2591
2592         mutex_lock(&smu->mutex);
2593
2594         if (smu->ppt_funcs->display_disable_memory_clock_switch)
2595                 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2596
2597         mutex_unlock(&smu->mutex);
2598
2599         return ret;
2600 }
2601
2602 int smu_notify_smu_enable_pwe(struct smu_context *smu)
2603 {
2604         int ret = 0;
2605
2606         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2607                 return -EOPNOTSUPP;
2608
2609         mutex_lock(&smu->mutex);
2610
2611         if (smu->ppt_funcs->notify_smu_enable_pwe)
2612                 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
2613
2614         mutex_unlock(&smu->mutex);
2615
2616         return ret;
2617 }
2618
2619 int smu_set_xgmi_pstate(struct smu_context *smu,
2620                         uint32_t pstate)
2621 {
2622         int ret = 0;
2623
2624         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2625                 return -EOPNOTSUPP;
2626
2627         mutex_lock(&smu->mutex);
2628
2629         if (smu->ppt_funcs->set_xgmi_pstate)
2630                 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2631
2632         mutex_unlock(&smu->mutex);
2633
2634         if(ret)
2635                 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2636
2637         return ret;
2638 }
2639
2640 int smu_set_azalia_d3_pme(struct smu_context *smu)
2641 {
2642         int ret = 0;
2643
2644         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2645                 return -EOPNOTSUPP;
2646
2647         mutex_lock(&smu->mutex);
2648
2649         if (smu->ppt_funcs->set_azalia_d3_pme)
2650                 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2651
2652         mutex_unlock(&smu->mutex);
2653
2654         return ret;
2655 }
2656
2657 /*
2658  * On system suspending or resetting, the dpm_enabled
2659  * flag will be cleared. So that those SMU services which
2660  * are not supported will be gated.
2661  *
2662  * However, the baco/mode1 reset should still be granted
2663  * as they are still supported and necessary.
2664  */
2665 bool smu_baco_is_support(struct smu_context *smu)
2666 {
2667         bool ret = false;
2668
2669         if (!smu->pm_enabled)
2670                 return false;
2671
2672         mutex_lock(&smu->mutex);
2673
2674         if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2675                 ret = smu->ppt_funcs->baco_is_support(smu);
2676
2677         mutex_unlock(&smu->mutex);
2678
2679         return ret;
2680 }
2681
2682 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2683 {
2684         if (smu->ppt_funcs->baco_get_state)
2685                 return -EINVAL;
2686
2687         mutex_lock(&smu->mutex);
2688         *state = smu->ppt_funcs->baco_get_state(smu);
2689         mutex_unlock(&smu->mutex);
2690
2691         return 0;
2692 }
2693
2694 int smu_baco_enter(struct smu_context *smu)
2695 {
2696         int ret = 0;
2697
2698         if (!smu->pm_enabled)
2699                 return -EOPNOTSUPP;
2700
2701         mutex_lock(&smu->mutex);
2702
2703         if (smu->ppt_funcs->baco_enter)
2704                 ret = smu->ppt_funcs->baco_enter(smu);
2705
2706         mutex_unlock(&smu->mutex);
2707
2708         if (ret)
2709                 dev_err(smu->adev->dev, "Failed to enter BACO state!\n");
2710
2711         return ret;
2712 }
2713
2714 int smu_baco_exit(struct smu_context *smu)
2715 {
2716         int ret = 0;
2717
2718         if (!smu->pm_enabled)
2719                 return -EOPNOTSUPP;
2720
2721         mutex_lock(&smu->mutex);
2722
2723         if (smu->ppt_funcs->baco_exit)
2724                 ret = smu->ppt_funcs->baco_exit(smu);
2725
2726         mutex_unlock(&smu->mutex);
2727
2728         if (ret)
2729                 dev_err(smu->adev->dev, "Failed to exit BACO state!\n");
2730
2731         return ret;
2732 }
2733
2734 int smu_mode2_reset(struct smu_context *smu)
2735 {
2736         int ret = 0;
2737
2738         if (!smu->pm_enabled)
2739                 return -EOPNOTSUPP;
2740
2741         mutex_lock(&smu->mutex);
2742
2743         if (smu->ppt_funcs->mode2_reset)
2744                 ret = smu->ppt_funcs->mode2_reset(smu);
2745
2746         mutex_unlock(&smu->mutex);
2747
2748         if (ret)
2749                 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2750
2751         return ret;
2752 }
2753
2754 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2755                                          struct pp_smu_nv_clock_table *max_clocks)
2756 {
2757         int ret = 0;
2758
2759         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2760                 return -EOPNOTSUPP;
2761
2762         mutex_lock(&smu->mutex);
2763
2764         if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2765                 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2766
2767         mutex_unlock(&smu->mutex);
2768
2769         return ret;
2770 }
2771
2772 int smu_get_uclk_dpm_states(struct smu_context *smu,
2773                             unsigned int *clock_values_in_khz,
2774                             unsigned int *num_states)
2775 {
2776         int ret = 0;
2777
2778         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2779                 return -EOPNOTSUPP;
2780
2781         mutex_lock(&smu->mutex);
2782
2783         if (smu->ppt_funcs->get_uclk_dpm_states)
2784                 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2785
2786         mutex_unlock(&smu->mutex);
2787
2788         return ret;
2789 }
2790
2791 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2792 {
2793         enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2794
2795         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2796                 return -EOPNOTSUPP;
2797
2798         mutex_lock(&smu->mutex);
2799
2800         if (smu->ppt_funcs->get_current_power_state)
2801                 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2802
2803         mutex_unlock(&smu->mutex);
2804
2805         return pm_state;
2806 }
2807
2808 int smu_get_dpm_clock_table(struct smu_context *smu,
2809                             struct dpm_clocks *clock_table)
2810 {
2811         int ret = 0;
2812
2813         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2814                 return -EOPNOTSUPP;
2815
2816         mutex_lock(&smu->mutex);
2817
2818         if (smu->ppt_funcs->get_dpm_clock_table)
2819                 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2820
2821         mutex_unlock(&smu->mutex);
2822
2823         return ret;
2824 }
2825
2826 uint32_t smu_get_pptable_power_limit(struct smu_context *smu)
2827 {
2828         uint32_t ret = 0;
2829
2830         if (smu->ppt_funcs->get_pptable_power_limit)
2831                 ret = smu->ppt_funcs->get_pptable_power_limit(smu);
2832
2833         return ret;
2834 }
2835
2836 int smu_powergate_vcn(struct smu_context *smu, bool gate)
2837 {
2838         if (!smu->is_apu)
2839                 return 0;
2840
2841         return smu_dpm_set_uvd_enable(smu, !gate);
2842 }
2843
2844 int smu_powergate_jpeg(struct smu_context *smu, bool gate)
2845 {
2846         if (!smu->is_apu)
2847                 return 0;
2848
2849         return smu_dpm_set_jpeg_enable(smu, !gate);
2850 }