drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "pp_debug.h"
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "soc15_common.h"
  29 #include "smu_v11_0.h"
  30 #include "atom.h"
  31 #include "amd_pcie.h"
  32
  33 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
  34 {
  35         int ret = 0;
  36
  37         if (!if_version && !smu_version)
  38                 return -EINVAL;
  39
  40         if (if_version) {
  41                 ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
  42                 if (ret)
  43                         return ret;
  44
  45                 ret = smu_read_smc_arg(smu, if_version);
  46                 if (ret)
  47                         return ret;
  48         }
  49
  50         if (smu_version) {
  51                 ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion);
  52                 if (ret)
  53                         return ret;
  54
  55                 ret = smu_read_smc_arg(smu, smu_version);
  56                 if (ret)
  57                         return ret;
  58         }
  59
  60         return ret;
  61 }
  62
  63 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
  64                            bool gate)
  65 {
  66         int ret = 0;
  67
  68         switch (block_type) {
  69         case AMD_IP_BLOCK_TYPE_UVD:
  70                 ret = smu_dpm_set_uvd_enable(smu, gate);
  71                 break;
  72         case AMD_IP_BLOCK_TYPE_VCE:
  73                 ret = smu_dpm_set_vce_enable(smu, gate);
  74                 break;
  75         default:
  76                 break;
  77         }
  78
  79         return ret;
  80 }
  81
  82 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
  83 {
  84         /* not support power state */
  85         return POWER_STATE_TYPE_DEFAULT;
  86 }
  87
  88 int smu_get_power_num_states(struct smu_context *smu,
  89                              struct pp_states_info *state_info)
  90 {
  91         if (!state_info)
  92                 return -EINVAL;
  93
  94         /* not support power state */
  95         memset(state_info, 0, sizeof(struct pp_states_info));
  96         state_info->nums = 0;
  97
  98         return 0;
  99 }
 100
 101 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
 102                            void *data, uint32_t *size)
 103 {
 104         int ret = 0;
 105
 106         switch (sensor) {
 107         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
 108                 *((uint32_t *)data) = smu->pstate_sclk;
 109                 *size = 4;
 110                 break;
 111         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
 112                 *((uint32_t *)data) = smu->pstate_mclk;
 113                 *size = 4;
 114                 break;
 115         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
 116                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
 117                 *size = 8;
 118                 break;
 119         default:
 120                 ret = -EINVAL;
 121                 break;
 122         }
 123
 124         if (ret)
 125                 *size = 0;
 126
 127         return ret;
 128 }
 129
 130 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index,
 131                      void *table_data, bool drv2smu)
 132 {
 133         struct smu_table_context *smu_table = &smu->smu_table;
 134         struct smu_table *table = NULL;
 135         int ret = 0;
 136         int table_id = smu_table_get_index(smu, table_index);
 137
 138         if (!table_data || table_id >= smu_table->table_count)
 139                 return -EINVAL;
 140
 141         table = &smu_table->tables[table_index];
 142
 143         if (drv2smu)
 144                 memcpy(table->cpu_addr, table_data, table->size);
 145
 146         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrHigh,
 147                                           upper_32_bits(table->mc_address));
 148         if (ret)
 149                 return ret;
 150         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrLow,
 151                                           lower_32_bits(table->mc_address));
 152         if (ret)
 153                 return ret;
 154         ret = smu_send_smc_msg_with_param(smu, drv2smu ?
 155                                           SMU_MSG_TransferTableDram2Smu :
 156                                           SMU_MSG_TransferTableSmu2Dram,
 157                                           table_id);
 158         if (ret)
 159                 return ret;
 160
 161         if (!drv2smu)
 162                 memcpy(table_data, table->cpu_addr, table->size);
 163
 164         return ret;
 165 }
 166
 167 bool is_support_sw_smu(struct amdgpu_device *adev)
 168 {
 169         if (adev->asic_type == CHIP_VEGA20)
 170                 return (amdgpu_dpm == 2) ? true : false;
 171         else if (adev->asic_type >= CHIP_NAVI10)
 172                 return true;
 173         else
 174                 return false;
 175 }
 176
 177 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 178 {
 179         struct smu_table_context *smu_table = &smu->smu_table;
 180
 181         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 182                 return -EINVAL;
 183
 184         if (smu_table->hardcode_pptable)
 185                 *table = smu_table->hardcode_pptable;
 186         else
 187                 *table = smu_table->power_play_table;
 188
 189         return smu_table->power_play_table_size;
 190 }
 191
 192 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 193 {
 194         struct smu_table_context *smu_table = &smu->smu_table;
 195         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 196         int ret = 0;
 197
 198         if (!smu->pm_enabled)
 199                 return -EINVAL;
 200         if (header->usStructureSize != size) {
 201                 pr_err("pp table size not matched !\n");
 202                 return -EIO;
 203         }
 204
 205         mutex_lock(&smu->mutex);
 206         if (!smu_table->hardcode_pptable)
 207                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 208         if (!smu_table->hardcode_pptable) {
 209                 ret = -ENOMEM;
 210                 goto failed;
 211         }
 212
 213         memcpy(smu_table->hardcode_pptable, buf, size);
 214         smu_table->power_play_table = smu_table->hardcode_pptable;
 215         smu_table->power_play_table_size = size;
 216         mutex_unlock(&smu->mutex);
 217
 218         ret = smu_reset(smu);
 219         if (ret)
 220                 pr_info("smu reset failed, ret = %d\n", ret);
 221
 222         return ret;
 223
 224 failed:
 225         mutex_unlock(&smu->mutex);
 226         return ret;
 227 }
 228
 229 int smu_feature_init_dpm(struct smu_context *smu)
 230 {
 231         struct smu_feature *feature = &smu->smu_feature;
 232         int ret = 0;
 233         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 234
 235         if (!smu->pm_enabled)
 236                 return ret;
 237         mutex_lock(&feature->mutex);
 238         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 239         mutex_unlock(&feature->mutex);
 240
 241         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 242                                              SMU_FEATURE_MAX/32);
 243         if (ret)
 244                 return ret;
 245
 246         mutex_lock(&feature->mutex);
 247         bitmap_or(feature->allowed, feature->allowed,
 248                       (unsigned long *)allowed_feature_mask,
 249                       feature->feature_num);
 250         mutex_unlock(&feature->mutex);
 251
 252         return ret;
 253 }
 254
 255 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
 256 {
 257         struct smu_feature *feature = &smu->smu_feature;
 258         uint32_t feature_id;
 259         int ret = 0;
 260
 261         feature_id = smu_feature_get_index(smu, mask);
 262
 263         WARN_ON(feature_id > feature->feature_num);
 264
 265         mutex_lock(&feature->mutex);
 266         ret = test_bit(feature_id, feature->enabled);
 267         mutex_unlock(&feature->mutex);
 268
 269         return ret;
 270 }
 271
 272 int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
 273                             bool enable)
 274 {
 275         struct smu_feature *feature = &smu->smu_feature;
 276         uint32_t feature_id;
 277         int ret = 0;
 278
 279         feature_id = smu_feature_get_index(smu, mask);
 280
 281         WARN_ON(feature_id > feature->feature_num);
 282
 283         mutex_lock(&feature->mutex);
 284         ret = smu_feature_update_enable_state(smu, feature_id, enable);
 285         if (ret)
 286                 goto failed;
 287
 288         if (enable)
 289                 test_and_set_bit(feature_id, feature->enabled);
 290         else
 291                 test_and_clear_bit(feature_id, feature->enabled);
 292
 293 failed:
 294         mutex_unlock(&feature->mutex);
 295
 296         return ret;
 297 }
 298
 299 int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
 300 {
 301         struct smu_feature *feature = &smu->smu_feature;
 302         uint32_t feature_id;
 303         int ret = 0;
 304
 305         feature_id = smu_feature_get_index(smu, mask);
 306
 307         WARN_ON(feature_id > feature->feature_num);
 308
 309         mutex_lock(&feature->mutex);
 310         ret = test_bit(feature_id, feature->supported);
 311         mutex_unlock(&feature->mutex);
 312
 313         return ret;
 314 }
 315
 316 int smu_feature_set_supported(struct smu_context *smu,
 317                               enum smu_feature_mask mask,
 318                               bool enable)
 319 {
 320         struct smu_feature *feature = &smu->smu_feature;
 321         uint32_t feature_id;
 322         int ret = 0;
 323
 324         feature_id = smu_feature_get_index(smu, mask);
 325
 326         WARN_ON(feature_id > feature->feature_num);
 327
 328         mutex_lock(&feature->mutex);
 329         if (enable)
 330                 test_and_set_bit(feature_id, feature->supported);
 331         else
 332                 test_and_clear_bit(feature_id, feature->supported);
 333         mutex_unlock(&feature->mutex);
 334
 335         return ret;
 336 }
 337
 338 static int smu_set_funcs(struct amdgpu_device *adev)
 339 {
 340         struct smu_context *smu = &adev->smu;
 341
 342         switch (adev->asic_type) {
 343         case CHIP_VEGA20:
 344         case CHIP_NAVI10:
 345                 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 346                         smu->od_enabled = true;
 347                 smu_v11_0_set_smu_funcs(smu);
 348                 break;
 349         default:
 350                 return -EINVAL;
 351         }
 352
 353         return 0;
 354 }
 355
 356 static int smu_early_init(void *handle)
 357 {
 358         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 359         struct smu_context *smu = &adev->smu;
 360
 361         smu->adev = adev;
 362         smu->pm_enabled = !!amdgpu_dpm;
 363         mutex_init(&smu->mutex);
 364
 365         return smu_set_funcs(adev);
 366 }
 367
 368 static int smu_late_init(void *handle)
 369 {
 370         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 371         struct smu_context *smu = &adev->smu;
 372
 373         if (!smu->pm_enabled)
 374                 return 0;
 375         mutex_lock(&smu->mutex);
 376         smu_handle_task(&adev->smu,
 377                         smu->smu_dpm.dpm_level,
 378                         AMD_PP_TASK_COMPLETE_INIT);
 379         mutex_unlock(&smu->mutex);
 380
 381         return 0;
 382 }
 383
 384 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
 385                             uint16_t *size, uint8_t *frev, uint8_t *crev,
 386                             uint8_t **addr)
 387 {
 388         struct amdgpu_device *adev = smu->adev;
 389         uint16_t data_start;
 390
 391         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
 392                                            size, frev, crev, &data_start))
 393                 return -EINVAL;
 394
 395         *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
 396
 397         return 0;
 398 }
 399
 400 static int smu_initialize_pptable(struct smu_context *smu)
 401 {
 402         /* TODO */
 403         return 0;
 404 }
 405
 406 static int smu_smc_table_sw_init(struct smu_context *smu)
 407 {
 408         int ret;
 409
 410         ret = smu_initialize_pptable(smu);
 411         if (ret) {
 412                 pr_err("Failed to init smu_initialize_pptable!\n");
 413                 return ret;
 414         }
 415
 416         /**
 417          * Create smu_table structure, and init smc tables such as
 418          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 419          */
 420         ret = smu_init_smc_tables(smu);
 421         if (ret) {
 422                 pr_err("Failed to init smc tables!\n");
 423                 return ret;
 424         }
 425
 426         /**
 427          * Create smu_power_context structure, and allocate smu_dpm_context and
 428          * context size to fill the smu_power_context data.
 429          */
 430         ret = smu_init_power(smu);
 431         if (ret) {
 432                 pr_err("Failed to init smu_init_power!\n");
 433                 return ret;
 434         }
 435
 436         return 0;
 437 }
 438
 439 static int smu_smc_table_sw_fini(struct smu_context *smu)
 440 {
 441         int ret;
 442
 443         ret = smu_fini_smc_tables(smu);
 444         if (ret) {
 445                 pr_err("Failed to smu_fini_smc_tables!\n");
 446                 return ret;
 447         }
 448
 449         return 0;
 450 }
 451
 452 static int smu_sw_init(void *handle)
 453 {
 454         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 455         struct smu_context *smu = &adev->smu;
 456         int ret;
 457
 458         smu->pool_size = adev->pm.smu_prv_buffer_size;
 459         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
 460         mutex_init(&smu->smu_feature.mutex);
 461         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
 462         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
 463         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 464         smu->watermarks_bitmap = 0;
 465         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 466         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 467
 468         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 469         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 470         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
 471         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
 472         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
 473         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
 474         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
 475         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
 476
 477         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 478         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 479         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
 480         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
 481         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
 482         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 483         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
 484         smu->display_config = &adev->pm.pm_display_cfg;
 485
 486         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 487         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 488         ret = smu_init_microcode(smu);
 489         if (ret) {
 490                 pr_err("Failed to load smu firmware!\n");
 491                 return ret;
 492         }
 493
 494         ret = smu_smc_table_sw_init(smu);
 495         if (ret) {
 496                 pr_err("Failed to sw init smc table!\n");
 497                 return ret;
 498         }
 499
 500         return 0;
 501 }
 502
 503 static int smu_sw_fini(void *handle)
 504 {
 505         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 506         struct smu_context *smu = &adev->smu;
 507         int ret;
 508
 509         ret = smu_smc_table_sw_fini(smu);
 510         if (ret) {
 511                 pr_err("Failed to sw fini smc table!\n");
 512                 return ret;
 513         }
 514
 515         ret = smu_fini_power(smu);
 516         if (ret) {
 517                 pr_err("Failed to init smu_fini_power!\n");
 518                 return ret;
 519         }
 520
 521         return 0;
 522 }
 523
 524 static int smu_init_fb_allocations(struct smu_context *smu)
 525 {
 526         struct amdgpu_device *adev = smu->adev;
 527         struct smu_table_context *smu_table = &smu->smu_table;
 528         struct smu_table *tables = smu_table->tables;
 529         uint32_t table_count = smu_table->table_count;
 530         uint32_t i = 0;
 531         int32_t ret = 0;
 532
 533         if (table_count <= 0)
 534                 return -EINVAL;
 535
 536         for (i = 0 ; i < table_count; i++) {
 537                 if (tables[i].size == 0)
 538                         continue;
 539                 ret = amdgpu_bo_create_kernel(adev,
 540                                               tables[i].size,
 541                                               tables[i].align,
 542                                               tables[i].domain,
 543                                               &tables[i].bo,
 544                                               &tables[i].mc_address,
 545                                               &tables[i].cpu_addr);
 546                 if (ret)
 547                         goto failed;
 548         }
 549
 550         return 0;
 551 failed:
 552         for (; i > 0; i--) {
 553                 if (tables[i].size == 0)
 554                         continue;
 555                 amdgpu_bo_free_kernel(&tables[i].bo,
 556                                       &tables[i].mc_address,
 557                                       &tables[i].cpu_addr);
 558
 559         }
 560         return ret;
 561 }
 562
 563 static int smu_fini_fb_allocations(struct smu_context *smu)
 564 {
 565         struct smu_table_context *smu_table = &smu->smu_table;
 566         struct smu_table *tables = smu_table->tables;
 567         uint32_t table_count = smu_table->table_count;
 568         uint32_t i = 0;
 569
 570         if (table_count == 0 || tables == NULL)
 571                 return 0;
 572
 573         for (i = 0 ; i < table_count; i++) {
 574                 if (tables[i].size == 0)
 575                         continue;
 576                 amdgpu_bo_free_kernel(&tables[i].bo,
 577                                       &tables[i].mc_address,
 578                                       &tables[i].cpu_addr);
 579         }
 580
 581         return 0;
 582 }
 583
 584 static int smu_override_pcie_parameters(struct smu_context *smu)
 585 {
 586         struct amdgpu_device *adev = smu->adev;
 587         uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
 588         int ret;
 589
 590         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
 591                 pcie_gen = 3;
 592         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 593                 pcie_gen = 2;
 594         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
 595                 pcie_gen = 1;
 596         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
 597                 pcie_gen = 0;
 598
 599         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
 600          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
 601          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
 602          */
 603         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
 604                 pcie_width = 6;
 605         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
 606                 pcie_width = 5;
 607         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
 608                 pcie_width = 4;
 609         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
 610                 pcie_width = 3;
 611         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
 612                 pcie_width = 2;
 613         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
 614                 pcie_width = 1;
 615
 616         smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
 617         ret = smu_send_smc_msg_with_param(smu,
 618                                           SMU_MSG_OverridePcieParameters,
 619                                           smu_pcie_arg);
 620         if (ret)
 621                 pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
 622         return ret;
 623 }
 624
 625 static int smu_smc_table_hw_init(struct smu_context *smu,
 626                                  bool initialize)
 627 {
 628         struct amdgpu_device *adev = smu->adev;
 629         int ret;
 630
 631         if (smu_is_dpm_running(smu) && adev->in_suspend) {
 632                 pr_info("dpm has been enabled\n");
 633                 return 0;
 634         }
 635
 636         ret = smu_init_display(smu);
 637         if (ret)
 638                 return ret;
 639
 640         if (initialize) {
 641                 /* get boot_values from vbios to set revision, gfxclk, and etc. */
 642                 ret = smu_get_vbios_bootup_values(smu);
 643                 if (ret)
 644                         return ret;
 645
 646                 ret = smu_setup_pptable(smu);
 647                 if (ret)
 648                         return ret;
 649
 650                 /*
 651                  * check if the format_revision in vbios is up to pptable header
 652                  * version, and the structure size is not 0.
 653                  */
 654                 ret = smu_check_pptable(smu);
 655                 if (ret)
 656                         return ret;
 657
 658                 /*
 659                  * allocate vram bos to store smc table contents.
 660                  */
 661                 ret = smu_init_fb_allocations(smu);
 662                 if (ret)
 663                         return ret;
 664
 665                 /*
 666                  * Parse pptable format and fill PPTable_t smc_pptable to
 667                  * smu_table_context structure. And read the smc_dpm_table from vbios,
 668                  * then fill it into smc_pptable.
 669                  */
 670                 ret = smu_parse_pptable(smu);
 671                 if (ret)
 672                         return ret;
 673
 674                 /*
 675                  * Send msg GetDriverIfVersion to check if the return value is equal
 676                  * with DRIVER_IF_VERSION of smc header.
 677                  */
 678                 ret = smu_check_fw_version(smu);
 679                 if (ret)
 680                         return ret;
 681         }
 682
 683         /*
 684          * Copy pptable bo in the vram to smc with SMU MSGs such as
 685          * SetDriverDramAddr and TransferTableDram2Smu.
 686          */
 687         ret = smu_write_pptable(smu);
 688         if (ret)
 689                 return ret;
 690
 691         /* issue RunAfllBtc msg */
 692         ret = smu_run_afll_btc(smu);
 693         if (ret)
 694                 return ret;
 695
 696         ret = smu_feature_set_allowed_mask(smu);
 697         if (ret)
 698                 return ret;
 699
 700         ret = smu_system_features_control(smu, true);
 701         if (ret)
 702                 return ret;
 703
 704         ret = smu_override_pcie_parameters(smu);
 705         if (ret)
 706                 return ret;
 707
 708         ret = smu_notify_display_change(smu);
 709         if (ret)
 710                 return ret;
 711
 712         /*
 713          * Set min deep sleep dce fclk with bootup value from vbios via
 714          * SetMinDeepSleepDcefclk MSG.
 715          */
 716         ret = smu_set_min_dcef_deep_sleep(smu);
 717         if (ret)
 718                 return ret;
 719
 720         /*
 721          * Set initialized values (get from vbios) to dpm tables context such as
 722          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
 723          * type of clks.
 724          */
 725         if (initialize) {
 726                 ret = smu_populate_smc_pptable(smu);
 727                 if (ret)
 728                         return ret;
 729
 730                 ret = smu_init_max_sustainable_clocks(smu);
 731                 if (ret)
 732                         return ret;
 733         }
 734
 735         ret = smu_set_od8_default_settings(smu, initialize);
 736         if (ret)
 737                 return ret;
 738
 739         if (initialize) {
 740                 ret = smu_populate_umd_state_clk(smu);
 741                 if (ret)
 742                         return ret;
 743
 744                 ret = smu_get_power_limit(smu, &smu->default_power_limit, false);
 745                 if (ret)
 746                         return ret;
 747         }
 748
 749         /*
 750          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
 751          */
 752         ret = smu_set_tool_table_location(smu);
 753
 754         if (!smu_is_dpm_running(smu))
 755                 pr_info("dpm has been disabled\n");
 756
 757         return ret;
 758 }
 759
 760 /**
 761  * smu_alloc_memory_pool - allocate memory pool in the system memory
 762  *
 763  * @smu: amdgpu_device pointer
 764  *
 765  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
 766  * and DramLogSetDramAddr can notify it changed.
 767  *
 768  * Returns 0 on success, error on failure.
 769  */
 770 static int smu_alloc_memory_pool(struct smu_context *smu)
 771 {
 772         struct amdgpu_device *adev = smu->adev;
 773         struct smu_table_context *smu_table = &smu->smu_table;
 774         struct smu_table *memory_pool = &smu_table->memory_pool;
 775         uint64_t pool_size = smu->pool_size;
 776         int ret = 0;
 777
 778         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
 779                 return ret;
 780
 781         memory_pool->size = pool_size;
 782         memory_pool->align = PAGE_SIZE;
 783         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
 784
 785         switch (pool_size) {
 786         case SMU_MEMORY_POOL_SIZE_256_MB:
 787         case SMU_MEMORY_POOL_SIZE_512_MB:
 788         case SMU_MEMORY_POOL_SIZE_1_GB:
 789         case SMU_MEMORY_POOL_SIZE_2_GB:
 790                 ret = amdgpu_bo_create_kernel(adev,
 791                                               memory_pool->size,
 792                                               memory_pool->align,
 793                                               memory_pool->domain,
 794                                               &memory_pool->bo,
 795                                               &memory_pool->mc_address,
 796                                               &memory_pool->cpu_addr);
 797                 break;
 798         default:
 799                 break;
 800         }
 801
 802         return ret;
 803 }
 804
 805 static int smu_free_memory_pool(struct smu_context *smu)
 806 {
 807         struct smu_table_context *smu_table = &smu->smu_table;
 808         struct smu_table *memory_pool = &smu_table->memory_pool;
 809         int ret = 0;
 810
 811         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
 812                 return ret;
 813
 814         amdgpu_bo_free_kernel(&memory_pool->bo,
 815                               &memory_pool->mc_address,
 816                               &memory_pool->cpu_addr);
 817
 818         memset(memory_pool, 0, sizeof(struct smu_table));
 819
 820         return ret;
 821 }
 822
 823 static int smu_hw_init(void *handle)
 824 {
 825         int ret;
 826         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 827         struct smu_context *smu = &adev->smu;
 828
 829         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 830                 ret = smu_check_fw_status(smu);
 831                 if (ret) {
 832                         pr_err("SMC firmware status is not correct\n");
 833                         return ret;
 834                 }
 835         }
 836
 837         mutex_lock(&smu->mutex);
 838
 839         ret = smu_feature_init_dpm(smu);
 840         if (ret)
 841                 goto failed;
 842
 843         ret = smu_smc_table_hw_init(smu, true);
 844         if (ret)
 845                 goto failed;
 846
 847         ret = smu_alloc_memory_pool(smu);
 848         if (ret)
 849                 goto failed;
 850
 851         /*
 852          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
 853          * pool location.
 854          */
 855         ret = smu_notify_memory_pool_location(smu);
 856         if (ret)
 857                 goto failed;
 858
 859         ret = smu_start_thermal_control(smu);
 860         if (ret)
 861                 goto failed;
 862
 863         mutex_unlock(&smu->mutex);
 864
 865         if (!smu->pm_enabled)
 866                 adev->pm.dpm_enabled = false;
 867         else
 868                 adev->pm.dpm_enabled = true;
 869
 870         pr_info("SMU is initialized successfully!\n");
 871
 872         return 0;
 873
 874 failed:
 875         mutex_unlock(&smu->mutex);
 876         return ret;
 877 }
 878
 879 static int smu_hw_fini(void *handle)
 880 {
 881         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 882         struct smu_context *smu = &adev->smu;
 883         struct smu_table_context *table_context = &smu->smu_table;
 884         int ret = 0;
 885
 886         kfree(table_context->driver_pptable);
 887         table_context->driver_pptable = NULL;
 888
 889         kfree(table_context->max_sustainable_clocks);
 890         table_context->max_sustainable_clocks = NULL;
 891
 892         kfree(table_context->od_feature_capabilities);
 893         table_context->od_feature_capabilities = NULL;
 894
 895         kfree(table_context->od_settings_max);
 896         table_context->od_settings_max = NULL;
 897
 898         kfree(table_context->od_settings_min);
 899         table_context->od_settings_min = NULL;
 900
 901         kfree(table_context->overdrive_table);
 902         table_context->overdrive_table = NULL;
 903
 904         kfree(table_context->od8_settings);
 905         table_context->od8_settings = NULL;
 906
 907         ret = smu_fini_fb_allocations(smu);
 908         if (ret)
 909                 return ret;
 910
 911         ret = smu_free_memory_pool(smu);
 912         if (ret)
 913                 return ret;
 914
 915         return 0;
 916 }
 917
 918 int smu_reset(struct smu_context *smu)
 919 {
 920         struct amdgpu_device *adev = smu->adev;
 921         int ret = 0;
 922
 923         ret = smu_hw_fini(adev);
 924         if (ret)
 925                 return ret;
 926
 927         ret = smu_hw_init(adev);
 928         if (ret)
 929                 return ret;
 930
 931         return ret;
 932 }
 933
 934 static int smu_suspend(void *handle)
 935 {
 936         int ret;
 937         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 938         struct smu_context *smu = &adev->smu;
 939
 940         ret = smu_system_features_control(smu, false);
 941         if (ret)
 942                 return ret;
 943
 944         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
 945
 946         return 0;
 947 }
 948
 949 static int smu_resume(void *handle)
 950 {
 951         int ret;
 952         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 953         struct smu_context *smu = &adev->smu;
 954
 955         pr_info("SMU is resuming...\n");
 956
 957         mutex_lock(&smu->mutex);
 958
 959         ret = smu_smc_table_hw_init(smu, false);
 960         if (ret)
 961                 goto failed;
 962
 963         ret = smu_start_thermal_control(smu);
 964         if (ret)
 965                 goto failed;
 966
 967         mutex_unlock(&smu->mutex);
 968
 969         pr_info("SMU is resumed successfully!\n");
 970
 971         return 0;
 972 failed:
 973         mutex_unlock(&smu->mutex);
 974         return ret;
 975 }
 976
 977 int smu_display_configuration_change(struct smu_context *smu,
 978                                      const struct amd_pp_display_configuration *display_config)
 979 {
 980         int index = 0;
 981         int num_of_active_display = 0;
 982
 983         if (!smu->pm_enabled || !is_support_sw_smu(smu->adev))
 984                 return -EINVAL;
 985
 986         if (!display_config)
 987                 return -EINVAL;
 988
 989         mutex_lock(&smu->mutex);
 990
 991         smu_set_deep_sleep_dcefclk(smu,
 992                                    display_config->min_dcef_deep_sleep_set_clk / 100);
 993
 994         for (index = 0; index < display_config->num_path_including_non_display; index++) {
 995                 if (display_config->displays[index].controller_id != 0)
 996                         num_of_active_display++;
 997         }
 998
 999         smu_set_active_display_count(smu, num_of_active_display);
1000
1001         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1002                            display_config->cpu_cc6_disable,
1003                            display_config->cpu_pstate_disable,
1004                            display_config->nb_pstate_switch_disable);
1005
1006         mutex_unlock(&smu->mutex);
1007
1008         return 0;
1009 }
1010
1011 static int smu_get_clock_info(struct smu_context *smu,
1012                               struct smu_clock_info *clk_info,
1013                               enum smu_perf_level_designation designation)
1014 {
1015         int ret;
1016         struct smu_performance_level level = {0};
1017
1018         if (!clk_info)
1019                 return -EINVAL;
1020
1021         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1022         if (ret)
1023                 return -EINVAL;
1024
1025         clk_info->min_mem_clk = level.memory_clock;
1026         clk_info->min_eng_clk = level.core_clock;
1027         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1028
1029         ret = smu_get_perf_level(smu, designation, &level);
1030         if (ret)
1031                 return -EINVAL;
1032
1033         clk_info->min_mem_clk = level.memory_clock;
1034         clk_info->min_eng_clk = level.core_clock;
1035         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1036
1037         return 0;
1038 }
1039
1040 int smu_get_current_clocks(struct smu_context *smu,
1041                            struct amd_pp_clock_info *clocks)
1042 {
1043         struct amd_pp_simple_clock_info simple_clocks = {0};
1044         struct smu_clock_info hw_clocks;
1045         int ret = 0;
1046
1047         if (!is_support_sw_smu(smu->adev))
1048                 return -EINVAL;
1049
1050         mutex_lock(&smu->mutex);
1051
1052         smu_get_dal_power_level(smu, &simple_clocks);
1053
1054         if (smu->support_power_containment)
1055                 ret = smu_get_clock_info(smu, &hw_clocks,
1056                                          PERF_LEVEL_POWER_CONTAINMENT);
1057         else
1058                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1059
1060         if (ret) {
1061                 pr_err("Error in smu_get_clock_info\n");
1062                 goto failed;
1063         }
1064
1065         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1066         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1067         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1068         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1069         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1070         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1071         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1072         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1073
1074         if (simple_clocks.level == 0)
1075                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1076         else
1077                 clocks->max_clocks_state = simple_clocks.level;
1078
1079         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1080                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1081                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1082         }
1083
1084 failed:
1085         mutex_unlock(&smu->mutex);
1086         return ret;
1087 }
1088
1089 static int smu_set_clockgating_state(void *handle,
1090                                      enum amd_clockgating_state state)
1091 {
1092         return 0;
1093 }
1094
1095 static int smu_set_powergating_state(void *handle,
1096                                      enum amd_powergating_state state)
1097 {
1098         return 0;
1099 }
1100
1101 static int smu_enable_umd_pstate(void *handle,
1102                       enum amd_dpm_forced_level *level)
1103 {
1104         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1105                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1106                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1107                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1108
1109         struct smu_context *smu = (struct smu_context*)(handle);
1110         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1111         if (!smu->pm_enabled || !smu_dpm_ctx->dpm_context)
1112                 return -EINVAL;
1113
1114         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1115                 /* enter umd pstate, save current level, disable gfx cg*/
1116                 if (*level & profile_mode_mask) {
1117                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1118                         smu_dpm_ctx->enable_umd_pstate = true;
1119                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1120                                                                AMD_IP_BLOCK_TYPE_GFX,
1121                                                                AMD_CG_STATE_UNGATE);
1122                         amdgpu_device_ip_set_powergating_state(smu->adev,
1123                                                                AMD_IP_BLOCK_TYPE_GFX,
1124                                                                AMD_PG_STATE_UNGATE);
1125                 }
1126         } else {
1127                 /* exit umd pstate, restore level, enable gfx cg*/
1128                 if (!(*level & profile_mode_mask)) {
1129                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1130                                 *level = smu_dpm_ctx->saved_dpm_level;
1131                         smu_dpm_ctx->enable_umd_pstate = false;
1132                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1133                                                                AMD_IP_BLOCK_TYPE_GFX,
1134                                                                AMD_CG_STATE_GATE);
1135                         amdgpu_device_ip_set_powergating_state(smu->adev,
1136                                                                AMD_IP_BLOCK_TYPE_GFX,
1137                                                                AMD_PG_STATE_GATE);
1138                 }
1139         }
1140
1141         return 0;
1142 }
1143
1144 int smu_adjust_power_state_dynamic(struct smu_context *smu,
1145                                    enum amd_dpm_forced_level level,
1146                                    bool skip_display_settings)
1147 {
1148         int ret = 0;
1149         int index = 0;
1150         uint32_t sclk_mask, mclk_mask, soc_mask;
1151         long workload;
1152         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1153
1154         if (!smu->pm_enabled)
1155                 return -EINVAL;
1156         if (!skip_display_settings) {
1157                 ret = smu_display_config_changed(smu);
1158                 if (ret) {
1159                         pr_err("Failed to change display config!");
1160                         return ret;
1161                 }
1162         }
1163
1164         if (!smu->pm_enabled)
1165                 return -EINVAL;
1166         ret = smu_apply_clocks_adjust_rules(smu);
1167         if (ret) {
1168                 pr_err("Failed to apply clocks adjust rules!");
1169                 return ret;
1170         }
1171
1172         if (!skip_display_settings) {
1173                 ret = smu_notify_smc_dispaly_config(smu);
1174                 if (ret) {
1175                         pr_err("Failed to notify smc display config!");
1176                         return ret;
1177                 }
1178         }
1179
1180         if (smu_dpm_ctx->dpm_level != level) {
1181                 switch (level) {
1182                 case AMD_DPM_FORCED_LEVEL_HIGH:
1183                         ret = smu_force_dpm_limit_value(smu, true);
1184                         break;
1185                 case AMD_DPM_FORCED_LEVEL_LOW:
1186                         ret = smu_force_dpm_limit_value(smu, false);
1187                         break;
1188
1189                 case AMD_DPM_FORCED_LEVEL_AUTO:
1190                         ret = smu_unforce_dpm_levels(smu);
1191                         break;
1192
1193                 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1194                 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1195                 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1196                 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1197                         ret = smu_get_profiling_clk_mask(smu, level,
1198                                                          &sclk_mask,
1199                                                          &mclk_mask,
1200                                                          &soc_mask);
1201                         if (ret)
1202                                 return ret;
1203                         smu_force_clk_levels(smu, PP_SCLK, 1 << sclk_mask);
1204                         smu_force_clk_levels(smu, PP_MCLK, 1 << mclk_mask);
1205                         break;
1206
1207                 case AMD_DPM_FORCED_LEVEL_MANUAL:
1208                 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1209                 default:
1210                         break;
1211                 }
1212
1213                 if (!ret)
1214                         smu_dpm_ctx->dpm_level = level;
1215         }
1216
1217         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1218                 index = fls(smu->workload_mask);
1219                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1220                 workload = smu->workload_setting[index];
1221
1222                 if (smu->power_profile_mode != workload)
1223                         smu_set_power_profile_mode(smu, &workload, 0);
1224         }
1225
1226         return ret;
1227 }
1228
1229 int smu_handle_task(struct smu_context *smu,
1230                     enum amd_dpm_forced_level level,
1231                     enum amd_pp_task task_id)
1232 {
1233         int ret = 0;
1234
1235         switch (task_id) {
1236         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1237                 ret = smu_pre_display_config_changed(smu);
1238                 if (ret)
1239                         return ret;
1240                 ret = smu_set_cpu_power_state(smu);
1241                 if (ret)
1242                         return ret;
1243                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1244                 break;
1245         case AMD_PP_TASK_COMPLETE_INIT:
1246         case AMD_PP_TASK_READJUST_POWER_STATE:
1247                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1248                 break;
1249         default:
1250                 break;
1251         }
1252
1253         return ret;
1254 }
1255
1256 const struct amd_ip_funcs smu_ip_funcs = {
1257         .name = "smu",
1258         .early_init = smu_early_init,
1259         .late_init = smu_late_init,
1260         .sw_init = smu_sw_init,
1261         .sw_fini = smu_sw_fini,
1262         .hw_init = smu_hw_init,
1263         .hw_fini = smu_hw_fini,
1264         .suspend = smu_suspend,
1265         .resume = smu_resume,
1266         .is_idle = NULL,
1267         .check_soft_reset = NULL,
1268         .wait_for_idle = NULL,
1269         .soft_reset = NULL,
1270         .set_clockgating_state = smu_set_clockgating_state,
1271         .set_powergating_state = smu_set_powergating_state,
1272         .enable_umd_pstate = smu_enable_umd_pstate,
1273 };
1274
1275 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1276 {
1277         .type = AMD_IP_BLOCK_TYPE_SMC,
1278         .major = 11,
1279         .minor = 0,
1280         .rev = 0,
1281         .funcs = &smu_ip_funcs,
1282 };