drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24
  25 #include "pp_debug.h"
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "soc15_common.h"
  29 #include "smu_v11_0.h"
  30 #include "smu_v12_0.h"
  31 #include "atom.h"
  32 #include "amd_pcie.h"
  33
  34 #undef __SMU_DUMMY_MAP
  35 #define __SMU_DUMMY_MAP(type)   #type
  36 static const char* __smu_message_names[] = {
  37         SMU_MESSAGE_TYPES
  38 };
  39
  40 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
  41 {
  42         if (type < 0 || type >= SMU_MSG_MAX_COUNT)
  43                 return "unknown smu message";
  44         return __smu_message_names[type];
  45 }
  46
  47 #undef __SMU_DUMMY_MAP
  48 #define __SMU_DUMMY_MAP(fea)    #fea
  49 static const char* __smu_feature_names[] = {
  50         SMU_FEATURE_MASKS
  51 };
  52
  53 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
  54 {
  55         if (feature < 0 || feature >= SMU_FEATURE_COUNT)
  56                 return "unknown smu feature";
  57         return __smu_feature_names[feature];
  58 }
  59
  60 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
  61 {
  62         size_t size = 0;
  63         int ret = 0, i = 0;
  64         uint32_t feature_mask[2] = { 0 };
  65         int32_t feature_index = 0;
  66         uint32_t count = 0;
  67         uint32_t sort_feature[SMU_FEATURE_COUNT];
  68         uint64_t hw_feature_count = 0;
  69
  70         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
  71         if (ret)
  72                 goto failed;
  73
  74         size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
  75                         feature_mask[1], feature_mask[0]);
  76
  77         for (i = 0; i < SMU_FEATURE_COUNT; i++) {
  78                 feature_index = smu_feature_get_index(smu, i);
  79                 if (feature_index < 0)
  80                         continue;
  81                 sort_feature[feature_index] = i;
  82                 hw_feature_count++;
  83         }
  84
  85         for (i = 0; i < hw_feature_count; i++) {
  86                 size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
  87                                count++,
  88                                smu_get_feature_name(smu, sort_feature[i]),
  89                                i,
  90                                !!smu_feature_is_enabled(smu, sort_feature[i]) ?
  91                                "enabled" : "disabled");
  92         }
  93
  94 failed:
  95         return size;
  96 }
  97
  98 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
  99 {
 100         int ret = 0;
 101         uint32_t feature_mask[2] = { 0 };
 102         uint64_t feature_2_enabled = 0;
 103         uint64_t feature_2_disabled = 0;
 104         uint64_t feature_enables = 0;
 105
 106         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 107         if (ret)
 108                 return ret;
 109
 110         feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
 111
 112         feature_2_enabled  = ~feature_enables & new_mask;
 113         feature_2_disabled = feature_enables & ~new_mask;
 114
 115         if (feature_2_enabled) {
 116                 ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
 117                 if (ret)
 118                         return ret;
 119         }
 120         if (feature_2_disabled) {
 121                 ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
 122                 if (ret)
 123                         return ret;
 124         }
 125
 126         return ret;
 127 }
 128
 129 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
 130 {
 131         int ret = 0;
 132
 133         if (!if_version && !smu_version)
 134                 return -EINVAL;
 135
 136         if (if_version) {
 137                 ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
 138                 if (ret)
 139                         return ret;
 140
 141                 ret = smu_read_smc_arg(smu, if_version);
 142                 if (ret)
 143                         return ret;
 144         }
 145
 146         if (smu_version) {
 147                 ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion);
 148                 if (ret)
 149                         return ret;
 150
 151                 ret = smu_read_smc_arg(smu, smu_version);
 152                 if (ret)
 153                         return ret;
 154         }
 155
 156         return ret;
 157 }
 158
 159 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 160                             uint32_t min, uint32_t max)
 161 {
 162         int ret = 0, clk_id = 0;
 163         uint32_t param;
 164
 165         if (min <= 0 && max <= 0)
 166                 return -EINVAL;
 167
 168         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 169                 return 0;
 170
 171         clk_id = smu_clk_get_index(smu, clk_type);
 172         if (clk_id < 0)
 173                 return clk_id;
 174
 175         if (max > 0) {
 176                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
 177                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
 178                                                   param);
 179                 if (ret)
 180                         return ret;
 181         }
 182
 183         if (min > 0) {
 184                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
 185                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
 186                                                   param);
 187                 if (ret)
 188                         return ret;
 189         }
 190
 191
 192         return ret;
 193 }
 194
 195 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 196                             uint32_t min, uint32_t max)
 197 {
 198         int ret = 0, clk_id = 0;
 199         uint32_t param;
 200
 201         if (min <= 0 && max <= 0)
 202                 return -EINVAL;
 203
 204         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 205                 return 0;
 206
 207         clk_id = smu_clk_get_index(smu, clk_type);
 208         if (clk_id < 0)
 209                 return clk_id;
 210
 211         if (max > 0) {
 212                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
 213                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
 214                                                   param);
 215                 if (ret)
 216                         return ret;
 217         }
 218
 219         if (min > 0) {
 220                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
 221                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
 222                                                   param);
 223                 if (ret)
 224                         return ret;
 225         }
 226
 227
 228         return ret;
 229 }
 230
 231 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 232                            uint32_t *min, uint32_t *max)
 233 {
 234         int ret = 0, clk_id = 0;
 235         uint32_t param = 0;
 236         uint32_t clock_limit;
 237
 238         if (!min && !max)
 239                 return -EINVAL;
 240
 241         if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
 242                 switch (clk_type) {
 243                 case SMU_MCLK:
 244                 case SMU_UCLK:
 245                         clock_limit = smu->smu_table.boot_values.uclk;
 246                         break;
 247                 case SMU_GFXCLK:
 248                 case SMU_SCLK:
 249                         clock_limit = smu->smu_table.boot_values.gfxclk;
 250                         break;
 251                 case SMU_SOCCLK:
 252                         clock_limit = smu->smu_table.boot_values.socclk;
 253                         break;
 254                 default:
 255                         clock_limit = 0;
 256                         break;
 257                 }
 258
 259                 /* clock in Mhz unit */
 260                 if (min)
 261                         *min = clock_limit / 100;
 262                 if (max)
 263                         *max = clock_limit / 100;
 264
 265                 return 0;
 266         }
 267
 268         mutex_lock(&smu->mutex);
 269         clk_id = smu_clk_get_index(smu, clk_type);
 270         if (clk_id < 0) {
 271                 ret = -EINVAL;
 272                 goto failed;
 273         }
 274
 275         param = (clk_id & 0xffff) << 16;
 276
 277         if (max) {
 278                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param);
 279                 if (ret)
 280                         goto failed;
 281                 ret = smu_read_smc_arg(smu, max);
 282                 if (ret)
 283                         goto failed;
 284         }
 285
 286         if (min) {
 287                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param);
 288                 if (ret)
 289                         goto failed;
 290                 ret = smu_read_smc_arg(smu, min);
 291                 if (ret)
 292                         goto failed;
 293         }
 294
 295 failed:
 296         mutex_unlock(&smu->mutex);
 297         return ret;
 298 }
 299
 300 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
 301                               uint16_t level, uint32_t *value)
 302 {
 303         int ret = 0, clk_id = 0;
 304         uint32_t param;
 305
 306         if (!value)
 307                 return -EINVAL;
 308
 309         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 310                 return 0;
 311
 312         clk_id = smu_clk_get_index(smu, clk_type);
 313         if (clk_id < 0)
 314                 return clk_id;
 315
 316         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
 317
 318         ret = smu_send_smc_msg_with_param(smu,SMU_MSG_GetDpmFreqByIndex,
 319                                           param);
 320         if (ret)
 321                 return ret;
 322
 323         ret = smu_read_smc_arg(smu, &param);
 324         if (ret)
 325                 return ret;
 326
 327         /* BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
 328          * now, we un-support it */
 329         *value = param & 0x7fffffff;
 330
 331         return ret;
 332 }
 333
 334 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
 335                             uint32_t *value)
 336 {
 337         return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
 338 }
 339
 340 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
 341 {
 342         enum smu_feature_mask feature_id = 0;
 343
 344         switch (clk_type) {
 345         case SMU_MCLK:
 346         case SMU_UCLK:
 347                 feature_id = SMU_FEATURE_DPM_UCLK_BIT;
 348                 break;
 349         case SMU_GFXCLK:
 350         case SMU_SCLK:
 351                 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
 352                 break;
 353         case SMU_SOCCLK:
 354                 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
 355                 break;
 356         default:
 357                 return true;
 358         }
 359
 360         if(!smu_feature_is_enabled(smu, feature_id)) {
 361                 return false;
 362         }
 363
 364         return true;
 365 }
 366
 367
 368 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 369                            bool gate)
 370 {
 371         int ret = 0;
 372
 373         switch (block_type) {
 374         case AMD_IP_BLOCK_TYPE_UVD:
 375                 ret = smu_dpm_set_uvd_enable(smu, gate);
 376                 break;
 377         case AMD_IP_BLOCK_TYPE_VCE:
 378                 ret = smu_dpm_set_vce_enable(smu, gate);
 379                 break;
 380         case AMD_IP_BLOCK_TYPE_GFX:
 381                 ret = smu_gfx_off_control(smu, gate);
 382                 break;
 383         default:
 384                 break;
 385         }
 386
 387         return ret;
 388 }
 389
 390 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
 391 {
 392         /* not support power state */
 393         return POWER_STATE_TYPE_DEFAULT;
 394 }
 395
 396 int smu_get_power_num_states(struct smu_context *smu,
 397                              struct pp_states_info *state_info)
 398 {
 399         if (!state_info)
 400                 return -EINVAL;
 401
 402         /* not support power state */
 403         memset(state_info, 0, sizeof(struct pp_states_info));
 404         state_info->nums = 1;
 405         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 406
 407         return 0;
 408 }
 409
 410 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
 411                            void *data, uint32_t *size)
 412 {
 413         struct smu_power_context *smu_power = &smu->smu_power;
 414         struct smu_power_gate *power_gate = &smu_power->power_gate;
 415         int ret = 0;
 416
 417         if(!data || !size)
 418                 return -EINVAL;
 419
 420         switch (sensor) {
 421         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
 422                 *((uint32_t *)data) = smu->pstate_sclk;
 423                 *size = 4;
 424                 break;
 425         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
 426                 *((uint32_t *)data) = smu->pstate_mclk;
 427                 *size = 4;
 428                 break;
 429         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
 430                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
 431                 *size = 8;
 432                 break;
 433         case AMDGPU_PP_SENSOR_UVD_POWER:
 434                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
 435                 *size = 4;
 436                 break;
 437         case AMDGPU_PP_SENSOR_VCE_POWER:
 438                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
 439                 *size = 4;
 440                 break;
 441         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
 442                 *(uint32_t *)data = power_gate->vcn_gated ? 0 : 1;
 443                 *size = 4;
 444                 break;
 445         default:
 446                 ret = -EINVAL;
 447                 break;
 448         }
 449
 450         if (ret)
 451                 *size = 0;
 452
 453         return ret;
 454 }
 455
 456 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
 457                      void *table_data, bool drv2smu)
 458 {
 459         struct smu_table_context *smu_table = &smu->smu_table;
 460         struct amdgpu_device *adev = smu->adev;
 461         struct smu_table *table = NULL;
 462         int ret = 0;
 463         int table_id = smu_table_get_index(smu, table_index);
 464
 465         if (!table_data || table_id >= smu_table->table_count || table_id < 0)
 466                 return -EINVAL;
 467
 468         table = &smu_table->tables[table_index];
 469
 470         if (drv2smu)
 471                 memcpy(table->cpu_addr, table_data, table->size);
 472
 473         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrHigh,
 474                                           upper_32_bits(table->mc_address));
 475         if (ret)
 476                 return ret;
 477         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrLow,
 478                                           lower_32_bits(table->mc_address));
 479         if (ret)
 480                 return ret;
 481         ret = smu_send_smc_msg_with_param(smu, drv2smu ?
 482                                           SMU_MSG_TransferTableDram2Smu :
 483                                           SMU_MSG_TransferTableSmu2Dram,
 484                                           table_id | ((argument & 0xFFFF) << 16));
 485         if (ret)
 486                 return ret;
 487
 488         /* flush hdp cache */
 489         adev->nbio_funcs->hdp_flush(adev, NULL);
 490
 491         if (!drv2smu)
 492                 memcpy(table_data, table->cpu_addr, table->size);
 493
 494         return ret;
 495 }
 496
 497 bool is_support_sw_smu(struct amdgpu_device *adev)
 498 {
 499         if (adev->asic_type == CHIP_VEGA20)
 500                 return (amdgpu_dpm == 2) ? true : false;
 501         else if (adev->asic_type >= CHIP_ARCTURUS)
 502                 return true;
 503         else
 504                 return false;
 505 }
 506
 507 bool is_support_sw_smu_xgmi(struct amdgpu_device *adev)
 508 {
 509         if (amdgpu_dpm != 1)
 510                 return false;
 511
 512         if (adev->asic_type == CHIP_VEGA20)
 513                 return true;
 514
 515         return false;
 516 }
 517
 518 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 519 {
 520         struct smu_table_context *smu_table = &smu->smu_table;
 521
 522         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 523                 return -EINVAL;
 524
 525         if (smu_table->hardcode_pptable)
 526                 *table = smu_table->hardcode_pptable;
 527         else
 528                 *table = smu_table->power_play_table;
 529
 530         return smu_table->power_play_table_size;
 531 }
 532
 533 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 534 {
 535         struct smu_table_context *smu_table = &smu->smu_table;
 536         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 537         int ret = 0;
 538
 539         if (!smu->pm_enabled)
 540                 return -EINVAL;
 541         if (header->usStructureSize != size) {
 542                 pr_err("pp table size not matched !\n");
 543                 return -EIO;
 544         }
 545
 546         mutex_lock(&smu->mutex);
 547         if (!smu_table->hardcode_pptable)
 548                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 549         if (!smu_table->hardcode_pptable) {
 550                 ret = -ENOMEM;
 551                 goto failed;
 552         }
 553
 554         memcpy(smu_table->hardcode_pptable, buf, size);
 555         smu_table->power_play_table = smu_table->hardcode_pptable;
 556         smu_table->power_play_table_size = size;
 557         mutex_unlock(&smu->mutex);
 558
 559         ret = smu_reset(smu);
 560         if (ret)
 561                 pr_info("smu reset failed, ret = %d\n", ret);
 562
 563         return ret;
 564
 565 failed:
 566         mutex_unlock(&smu->mutex);
 567         return ret;
 568 }
 569
 570 int smu_feature_init_dpm(struct smu_context *smu)
 571 {
 572         struct smu_feature *feature = &smu->smu_feature;
 573         int ret = 0;
 574         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 575
 576         if (!smu->pm_enabled)
 577                 return ret;
 578         mutex_lock(&feature->mutex);
 579         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 580         mutex_unlock(&feature->mutex);
 581
 582         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 583                                              SMU_FEATURE_MAX/32);
 584         if (ret)
 585                 return ret;
 586
 587         mutex_lock(&feature->mutex);
 588         bitmap_or(feature->allowed, feature->allowed,
 589                       (unsigned long *)allowed_feature_mask,
 590                       feature->feature_num);
 591         mutex_unlock(&feature->mutex);
 592
 593         return ret;
 594 }
 595 int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled)
 596 {
 597         uint32_t feature_low = 0, feature_high = 0;
 598         int ret = 0;
 599
 600         if (!smu->pm_enabled)
 601                 return ret;
 602
 603         feature_low = (feature_mask >> 0 ) & 0xffffffff;
 604         feature_high = (feature_mask >> 32) & 0xffffffff;
 605
 606         if (enabled) {
 607                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
 608                                                   feature_low);
 609                 if (ret)
 610                         return ret;
 611                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
 612                                                   feature_high);
 613                 if (ret)
 614                         return ret;
 615
 616         } else {
 617                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
 618                                                   feature_low);
 619                 if (ret)
 620                         return ret;
 621                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
 622                                                   feature_high);
 623                 if (ret)
 624                         return ret;
 625
 626         }
 627
 628         return ret;
 629 }
 630
 631 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
 632 {
 633         struct smu_feature *feature = &smu->smu_feature;
 634         int feature_id;
 635         int ret = 0;
 636
 637         feature_id = smu_feature_get_index(smu, mask);
 638         if (feature_id < 0)
 639                 return 0;
 640
 641         WARN_ON(feature_id > feature->feature_num);
 642
 643         mutex_lock(&feature->mutex);
 644         ret = test_bit(feature_id, feature->enabled);
 645         mutex_unlock(&feature->mutex);
 646
 647         return ret;
 648 }
 649
 650 int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
 651                             bool enable)
 652 {
 653         struct smu_feature *feature = &smu->smu_feature;
 654         int feature_id;
 655         uint64_t feature_mask = 0;
 656         int ret = 0;
 657
 658         feature_id = smu_feature_get_index(smu, mask);
 659         if (feature_id < 0)
 660                 return -EINVAL;
 661
 662         WARN_ON(feature_id > feature->feature_num);
 663
 664         feature_mask = 1ULL << feature_id;
 665
 666         mutex_lock(&feature->mutex);
 667         ret = smu_feature_update_enable_state(smu, feature_mask, enable);
 668         if (ret)
 669                 goto failed;
 670
 671         if (enable)
 672                 test_and_set_bit(feature_id, feature->enabled);
 673         else
 674                 test_and_clear_bit(feature_id, feature->enabled);
 675
 676 failed:
 677         mutex_unlock(&feature->mutex);
 678
 679         return ret;
 680 }
 681
 682 int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
 683 {
 684         struct smu_feature *feature = &smu->smu_feature;
 685         int feature_id;
 686         int ret = 0;
 687
 688         feature_id = smu_feature_get_index(smu, mask);
 689         if (feature_id < 0)
 690                 return 0;
 691
 692         WARN_ON(feature_id > feature->feature_num);
 693
 694         mutex_lock(&feature->mutex);
 695         ret = test_bit(feature_id, feature->supported);
 696         mutex_unlock(&feature->mutex);
 697
 698         return ret;
 699 }
 700
 701 int smu_feature_set_supported(struct smu_context *smu,
 702                               enum smu_feature_mask mask,
 703                               bool enable)
 704 {
 705         struct smu_feature *feature = &smu->smu_feature;
 706         int feature_id;
 707         int ret = 0;
 708
 709         feature_id = smu_feature_get_index(smu, mask);
 710         if (feature_id < 0)
 711                 return -EINVAL;
 712
 713         WARN_ON(feature_id > feature->feature_num);
 714
 715         mutex_lock(&feature->mutex);
 716         if (enable)
 717                 test_and_set_bit(feature_id, feature->supported);
 718         else
 719                 test_and_clear_bit(feature_id, feature->supported);
 720         mutex_unlock(&feature->mutex);
 721
 722         return ret;
 723 }
 724
 725 static int smu_set_funcs(struct amdgpu_device *adev)
 726 {
 727         struct smu_context *smu = &adev->smu;
 728
 729         switch (adev->asic_type) {
 730         case CHIP_VEGA20:
 731         case CHIP_NAVI10:
 732         case CHIP_NAVI14:
 733         case CHIP_NAVI12:
 734         case CHIP_ARCTURUS:
 735                 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 736                         smu->od_enabled = true;
 737                 smu_v11_0_set_smu_funcs(smu);
 738                 break;
 739         case CHIP_RENOIR:
 740                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 741                 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 742                         smu->od_enabled = true;
 743                 smu_v12_0_set_smu_funcs(smu);
 744                 break;
 745         default:
 746                 return -EINVAL;
 747         }
 748
 749         return 0;
 750 }
 751
 752 static int smu_early_init(void *handle)
 753 {
 754         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 755         struct smu_context *smu = &adev->smu;
 756
 757         smu->adev = adev;
 758         smu->pm_enabled = !!amdgpu_dpm;
 759         mutex_init(&smu->mutex);
 760
 761         return smu_set_funcs(adev);
 762 }
 763
 764 static int smu_late_init(void *handle)
 765 {
 766         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 767         struct smu_context *smu = &adev->smu;
 768
 769         if (!smu->pm_enabled)
 770                 return 0;
 771         mutex_lock(&smu->mutex);
 772         smu_handle_task(&adev->smu,
 773                         smu->smu_dpm.dpm_level,
 774                         AMD_PP_TASK_COMPLETE_INIT);
 775         mutex_unlock(&smu->mutex);
 776
 777         return 0;
 778 }
 779
 780 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
 781                             uint16_t *size, uint8_t *frev, uint8_t *crev,
 782                             uint8_t **addr)
 783 {
 784         struct amdgpu_device *adev = smu->adev;
 785         uint16_t data_start;
 786
 787         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
 788                                            size, frev, crev, &data_start))
 789                 return -EINVAL;
 790
 791         *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
 792
 793         return 0;
 794 }
 795
 796 static int smu_initialize_pptable(struct smu_context *smu)
 797 {
 798         /* TODO */
 799         return 0;
 800 }
 801
 802 static int smu_smc_table_sw_init(struct smu_context *smu)
 803 {
 804         int ret;
 805
 806         ret = smu_initialize_pptable(smu);
 807         if (ret) {
 808                 pr_err("Failed to init smu_initialize_pptable!\n");
 809                 return ret;
 810         }
 811
 812         /**
 813          * Create smu_table structure, and init smc tables such as
 814          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 815          */
 816         ret = smu_init_smc_tables(smu);
 817         if (ret) {
 818                 pr_err("Failed to init smc tables!\n");
 819                 return ret;
 820         }
 821
 822         /**
 823          * Create smu_power_context structure, and allocate smu_dpm_context and
 824          * context size to fill the smu_power_context data.
 825          */
 826         ret = smu_init_power(smu);
 827         if (ret) {
 828                 pr_err("Failed to init smu_init_power!\n");
 829                 return ret;
 830         }
 831
 832         return 0;
 833 }
 834
 835 static int smu_smc_table_sw_fini(struct smu_context *smu)
 836 {
 837         int ret;
 838
 839         ret = smu_fini_smc_tables(smu);
 840         if (ret) {
 841                 pr_err("Failed to smu_fini_smc_tables!\n");
 842                 return ret;
 843         }
 844
 845         return 0;
 846 }
 847
 848 static int smu_sw_init(void *handle)
 849 {
 850         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 851         struct smu_context *smu = &adev->smu;
 852         int ret;
 853
 854         smu->pool_size = adev->pm.smu_prv_buffer_size;
 855         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
 856         mutex_init(&smu->smu_feature.mutex);
 857         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
 858         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
 859         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 860
 861         mutex_init(&smu->smu_baco.mutex);
 862         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
 863         smu->smu_baco.platform_support = false;
 864
 865         smu->watermarks_bitmap = 0;
 866         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 867         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 868
 869         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 870         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 871         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
 872         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
 873         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
 874         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
 875         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
 876         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
 877
 878         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 879         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 880         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
 881         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
 882         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
 883         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 884         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
 885         smu->display_config = &adev->pm.pm_display_cfg;
 886
 887         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 888         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 889         ret = smu_init_microcode(smu);
 890         if (ret) {
 891                 pr_err("Failed to load smu firmware!\n");
 892                 return ret;
 893         }
 894
 895         ret = smu_smc_table_sw_init(smu);
 896         if (ret) {
 897                 pr_err("Failed to sw init smc table!\n");
 898                 return ret;
 899         }
 900
 901         ret = smu_register_irq_handler(smu);
 902         if (ret) {
 903                 pr_err("Failed to register smc irq handler!\n");
 904                 return ret;
 905         }
 906
 907         return 0;
 908 }
 909
 910 static int smu_sw_fini(void *handle)
 911 {
 912         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 913         struct smu_context *smu = &adev->smu;
 914         int ret;
 915
 916         kfree(smu->irq_source);
 917         smu->irq_source = NULL;
 918
 919         ret = smu_smc_table_sw_fini(smu);
 920         if (ret) {
 921                 pr_err("Failed to sw fini smc table!\n");
 922                 return ret;
 923         }
 924
 925         ret = smu_fini_power(smu);
 926         if (ret) {
 927                 pr_err("Failed to init smu_fini_power!\n");
 928                 return ret;
 929         }
 930
 931         return 0;
 932 }
 933
 934 static int smu_init_fb_allocations(struct smu_context *smu)
 935 {
 936         struct amdgpu_device *adev = smu->adev;
 937         struct smu_table_context *smu_table = &smu->smu_table;
 938         struct smu_table *tables = smu_table->tables;
 939         uint32_t table_count = smu_table->table_count;
 940         uint32_t i = 0;
 941         int32_t ret = 0;
 942
 943         if (table_count <= 0)
 944                 return -EINVAL;
 945
 946         for (i = 0 ; i < table_count; i++) {
 947                 if (tables[i].size == 0)
 948                         continue;
 949                 ret = amdgpu_bo_create_kernel(adev,
 950                                               tables[i].size,
 951                                               tables[i].align,
 952                                               tables[i].domain,
 953                                               &tables[i].bo,
 954                                               &tables[i].mc_address,
 955                                               &tables[i].cpu_addr);
 956                 if (ret)
 957                         goto failed;
 958         }
 959
 960         return 0;
 961 failed:
 962         for (; i > 0; i--) {
 963                 if (tables[i].size == 0)
 964                         continue;
 965                 amdgpu_bo_free_kernel(&tables[i].bo,
 966                                       &tables[i].mc_address,
 967                                       &tables[i].cpu_addr);
 968
 969         }
 970         return ret;
 971 }
 972
 973 static int smu_fini_fb_allocations(struct smu_context *smu)
 974 {
 975         struct smu_table_context *smu_table = &smu->smu_table;
 976         struct smu_table *tables = smu_table->tables;
 977         uint32_t table_count = smu_table->table_count;
 978         uint32_t i = 0;
 979
 980         if (table_count == 0 || tables == NULL)
 981                 return 0;
 982
 983         for (i = 0 ; i < table_count; i++) {
 984                 if (tables[i].size == 0)
 985                         continue;
 986                 amdgpu_bo_free_kernel(&tables[i].bo,
 987                                       &tables[i].mc_address,
 988                                       &tables[i].cpu_addr);
 989         }
 990
 991         return 0;
 992 }
 993
 994 static int smu_override_pcie_parameters(struct smu_context *smu)
 995 {
 996         struct amdgpu_device *adev = smu->adev;
 997         uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
 998         int ret;
 999
1000         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1001                 pcie_gen = 3;
1002         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1003                 pcie_gen = 2;
1004         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1005                 pcie_gen = 1;
1006         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1007                 pcie_gen = 0;
1008
1009         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1010          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1011          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
1012          */
1013         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1014                 pcie_width = 6;
1015         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1016                 pcie_width = 5;
1017         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1018                 pcie_width = 4;
1019         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1020                 pcie_width = 3;
1021         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1022                 pcie_width = 2;
1023         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1024                 pcie_width = 1;
1025
1026         smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
1027         ret = smu_send_smc_msg_with_param(smu,
1028                                           SMU_MSG_OverridePcieParameters,
1029                                           smu_pcie_arg);
1030         if (ret)
1031                 pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
1032         return ret;
1033 }
1034
1035 static int smu_smc_table_hw_init(struct smu_context *smu,
1036                                  bool initialize)
1037 {
1038         struct amdgpu_device *adev = smu->adev;
1039         int ret;
1040
1041         if (adev->flags & AMD_IS_APU)
1042                 return 0;
1043
1044         if (smu_is_dpm_running(smu) && adev->in_suspend) {
1045                 pr_info("dpm has been enabled\n");
1046                 return 0;
1047         }
1048
1049         if (adev->asic_type != CHIP_ARCTURUS) {
1050                 ret = smu_init_display_count(smu, 0);
1051                 if (ret)
1052                         return ret;
1053         }
1054
1055         if (initialize) {
1056                 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1057                 ret = smu_get_vbios_bootup_values(smu);
1058                 if (ret)
1059                         return ret;
1060
1061                 ret = smu_setup_pptable(smu);
1062                 if (ret)
1063                         return ret;
1064
1065                 ret = smu_get_clk_info_from_vbios(smu);
1066                 if (ret)
1067                         return ret;
1068
1069                 /*
1070                  * check if the format_revision in vbios is up to pptable header
1071                  * version, and the structure size is not 0.
1072                  */
1073                 ret = smu_check_pptable(smu);
1074                 if (ret)
1075                         return ret;
1076
1077                 /*
1078                  * allocate vram bos to store smc table contents.
1079                  */
1080                 ret = smu_init_fb_allocations(smu);
1081                 if (ret)
1082                         return ret;
1083
1084                 /*
1085                  * Parse pptable format and fill PPTable_t smc_pptable to
1086                  * smu_table_context structure. And read the smc_dpm_table from vbios,
1087                  * then fill it into smc_pptable.
1088                  */
1089                 ret = smu_parse_pptable(smu);
1090                 if (ret)
1091                         return ret;
1092
1093                 /*
1094                  * Send msg GetDriverIfVersion to check if the return value is equal
1095                  * with DRIVER_IF_VERSION of smc header.
1096                  */
1097                 ret = smu_check_fw_version(smu);
1098                 if (ret)
1099                         return ret;
1100         }
1101
1102         /* smu_dump_pptable(smu); */
1103
1104         /*
1105          * Copy pptable bo in the vram to smc with SMU MSGs such as
1106          * SetDriverDramAddr and TransferTableDram2Smu.
1107          */
1108         ret = smu_write_pptable(smu);
1109         if (ret)
1110                 return ret;
1111
1112         /* issue RunAfllBtc msg */
1113         ret = smu_run_afll_btc(smu);
1114         if (ret)
1115                 return ret;
1116
1117         ret = smu_feature_set_allowed_mask(smu);
1118         if (ret)
1119                 return ret;
1120
1121         ret = smu_system_features_control(smu, true);
1122         if (ret)
1123                 return ret;
1124
1125         if (adev->asic_type != CHIP_ARCTURUS) {
1126                 ret = smu_override_pcie_parameters(smu);
1127                 if (ret)
1128                         return ret;
1129
1130                 ret = smu_notify_display_change(smu);
1131                 if (ret)
1132                         return ret;
1133
1134                 /*
1135                  * Set min deep sleep dce fclk with bootup value from vbios via
1136                  * SetMinDeepSleepDcefclk MSG.
1137                  */
1138                 ret = smu_set_min_dcef_deep_sleep(smu);
1139                 if (ret)
1140                         return ret;
1141         }
1142
1143         /*
1144          * Set initialized values (get from vbios) to dpm tables context such as
1145          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1146          * type of clks.
1147          */
1148         if (initialize) {
1149                 ret = smu_populate_smc_pptable(smu);
1150                 if (ret)
1151                         return ret;
1152
1153                 ret = smu_init_max_sustainable_clocks(smu);
1154                 if (ret)
1155                         return ret;
1156         }
1157
1158         ret = smu_set_default_od_settings(smu, initialize);
1159         if (ret)
1160                 return ret;
1161
1162         if (initialize) {
1163                 ret = smu_populate_umd_state_clk(smu);
1164                 if (ret)
1165                         return ret;
1166
1167                 ret = smu_get_power_limit(smu, &smu->default_power_limit, true);
1168                 if (ret)
1169                         return ret;
1170         }
1171
1172         /*
1173          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1174          */
1175         ret = smu_set_tool_table_location(smu);
1176
1177         if (!smu_is_dpm_running(smu))
1178                 pr_info("dpm has been disabled\n");
1179
1180         return ret;
1181 }
1182
1183 /**
1184  * smu_alloc_memory_pool - allocate memory pool in the system memory
1185  *
1186  * @smu: amdgpu_device pointer
1187  *
1188  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
1189  * and DramLogSetDramAddr can notify it changed.
1190  *
1191  * Returns 0 on success, error on failure.
1192  */
1193 static int smu_alloc_memory_pool(struct smu_context *smu)
1194 {
1195         struct amdgpu_device *adev = smu->adev;
1196         struct smu_table_context *smu_table = &smu->smu_table;
1197         struct smu_table *memory_pool = &smu_table->memory_pool;
1198         uint64_t pool_size = smu->pool_size;
1199         int ret = 0;
1200
1201         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
1202                 return ret;
1203
1204         memory_pool->size = pool_size;
1205         memory_pool->align = PAGE_SIZE;
1206         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
1207
1208         switch (pool_size) {
1209         case SMU_MEMORY_POOL_SIZE_256_MB:
1210         case SMU_MEMORY_POOL_SIZE_512_MB:
1211         case SMU_MEMORY_POOL_SIZE_1_GB:
1212         case SMU_MEMORY_POOL_SIZE_2_GB:
1213                 ret = amdgpu_bo_create_kernel(adev,
1214                                               memory_pool->size,
1215                                               memory_pool->align,
1216                                               memory_pool->domain,
1217                                               &memory_pool->bo,
1218                                               &memory_pool->mc_address,
1219                                               &memory_pool->cpu_addr);
1220                 break;
1221         default:
1222                 break;
1223         }
1224
1225         return ret;
1226 }
1227
1228 static int smu_free_memory_pool(struct smu_context *smu)
1229 {
1230         struct smu_table_context *smu_table = &smu->smu_table;
1231         struct smu_table *memory_pool = &smu_table->memory_pool;
1232         int ret = 0;
1233
1234         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
1235                 return ret;
1236
1237         amdgpu_bo_free_kernel(&memory_pool->bo,
1238                               &memory_pool->mc_address,
1239                               &memory_pool->cpu_addr);
1240
1241         memset(memory_pool, 0, sizeof(struct smu_table));
1242
1243         return ret;
1244 }
1245
1246 static int smu_hw_init(void *handle)
1247 {
1248         int ret;
1249         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1250         struct smu_context *smu = &adev->smu;
1251
1252         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1253                 if (adev->asic_type < CHIP_NAVI10) {
1254                         ret = smu_load_microcode(smu);
1255                         if (ret)
1256                                 return ret;
1257                 }
1258         }
1259
1260         ret = smu_check_fw_status(smu);
1261         if (ret) {
1262                 pr_err("SMC firmware status is not correct\n");
1263                 return ret;
1264         }
1265
1266         if (!smu->pm_enabled)
1267                 return 0;
1268
1269         ret = smu_feature_init_dpm(smu);
1270         if (ret)
1271                 goto failed;
1272
1273         ret = smu_smc_table_hw_init(smu, true);
1274         if (ret)
1275                 goto failed;
1276
1277         ret = smu_alloc_memory_pool(smu);
1278         if (ret)
1279                 goto failed;
1280
1281         /*
1282          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1283          * pool location.
1284          */
1285         ret = smu_notify_memory_pool_location(smu);
1286         if (ret)
1287                 goto failed;
1288
1289         ret = smu_start_thermal_control(smu);
1290         if (ret)
1291                 goto failed;
1292
1293         if (!smu->pm_enabled)
1294                 adev->pm.dpm_enabled = false;
1295         else
1296                 adev->pm.dpm_enabled = true;    /* TODO: will set dpm_enabled flag while VCN and DAL DPM is workable */
1297
1298         pr_info("SMU is initialized successfully!\n");
1299
1300         return 0;
1301
1302 failed:
1303         return ret;
1304 }
1305
1306 static int smu_hw_fini(void *handle)
1307 {
1308         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1309         struct smu_context *smu = &adev->smu;
1310         struct smu_table_context *table_context = &smu->smu_table;
1311         int ret = 0;
1312
1313         kfree(table_context->driver_pptable);
1314         table_context->driver_pptable = NULL;
1315
1316         kfree(table_context->max_sustainable_clocks);
1317         table_context->max_sustainable_clocks = NULL;
1318
1319         kfree(table_context->overdrive_table);
1320         table_context->overdrive_table = NULL;
1321
1322         ret = smu_fini_fb_allocations(smu);
1323         if (ret)
1324                 return ret;
1325
1326         ret = smu_free_memory_pool(smu);
1327         if (ret)
1328                 return ret;
1329
1330         return 0;
1331 }
1332
1333 int smu_reset(struct smu_context *smu)
1334 {
1335         struct amdgpu_device *adev = smu->adev;
1336         int ret = 0;
1337
1338         ret = smu_hw_fini(adev);
1339         if (ret)
1340                 return ret;
1341
1342         ret = smu_hw_init(adev);
1343         if (ret)
1344                 return ret;
1345
1346         return ret;
1347 }
1348
1349 static int smu_suspend(void *handle)
1350 {
1351         int ret;
1352         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1353         struct smu_context *smu = &adev->smu;
1354         bool baco_feature_is_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT);
1355
1356         ret = smu_system_features_control(smu, false);
1357         if (ret)
1358                 return ret;
1359
1360         if (adev->in_gpu_reset && baco_feature_is_enabled) {
1361                 ret = smu_feature_set_enabled(smu, SMU_FEATURE_BACO_BIT, true);
1362                 if (ret) {
1363                         pr_warn("set BACO feature enabled failed, return %d\n", ret);
1364                         return ret;
1365                 }
1366         }
1367
1368         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1369
1370         if (adev->asic_type >= CHIP_NAVI10 &&
1371             adev->gfx.rlc.funcs->stop)
1372                 adev->gfx.rlc.funcs->stop(adev);
1373
1374         return 0;
1375 }
1376
1377 static int smu_resume(void *handle)
1378 {
1379         int ret;
1380         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1381         struct smu_context *smu = &adev->smu;
1382
1383         pr_info("SMU is resuming...\n");
1384
1385         mutex_lock(&smu->mutex);
1386
1387         ret = smu_smc_table_hw_init(smu, false);
1388         if (ret)
1389                 goto failed;
1390
1391         ret = smu_start_thermal_control(smu);
1392         if (ret)
1393                 goto failed;
1394
1395         mutex_unlock(&smu->mutex);
1396
1397         pr_info("SMU is resumed successfully!\n");
1398
1399         return 0;
1400 failed:
1401         mutex_unlock(&smu->mutex);
1402         return ret;
1403 }
1404
1405 int smu_display_configuration_change(struct smu_context *smu,
1406                                      const struct amd_pp_display_configuration *display_config)
1407 {
1408         int index = 0;
1409         int num_of_active_display = 0;
1410
1411         if (!smu->pm_enabled || !is_support_sw_smu(smu->adev))
1412                 return -EINVAL;
1413
1414         if (!display_config)
1415                 return -EINVAL;
1416
1417         mutex_lock(&smu->mutex);
1418
1419         smu_set_deep_sleep_dcefclk(smu,
1420                                    display_config->min_dcef_deep_sleep_set_clk / 100);
1421
1422         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1423                 if (display_config->displays[index].controller_id != 0)
1424                         num_of_active_display++;
1425         }
1426
1427         smu_set_active_display_count(smu, num_of_active_display);
1428
1429         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1430                            display_config->cpu_cc6_disable,
1431                            display_config->cpu_pstate_disable,
1432                            display_config->nb_pstate_switch_disable);
1433
1434         mutex_unlock(&smu->mutex);
1435
1436         return 0;
1437 }
1438
1439 static int smu_get_clock_info(struct smu_context *smu,
1440                               struct smu_clock_info *clk_info,
1441                               enum smu_perf_level_designation designation)
1442 {
1443         int ret;
1444         struct smu_performance_level level = {0};
1445
1446         if (!clk_info)
1447                 return -EINVAL;
1448
1449         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1450         if (ret)
1451                 return -EINVAL;
1452
1453         clk_info->min_mem_clk = level.memory_clock;
1454         clk_info->min_eng_clk = level.core_clock;
1455         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1456
1457         ret = smu_get_perf_level(smu, designation, &level);
1458         if (ret)
1459                 return -EINVAL;
1460
1461         clk_info->min_mem_clk = level.memory_clock;
1462         clk_info->min_eng_clk = level.core_clock;
1463         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1464
1465         return 0;
1466 }
1467
1468 int smu_get_current_clocks(struct smu_context *smu,
1469                            struct amd_pp_clock_info *clocks)
1470 {
1471         struct amd_pp_simple_clock_info simple_clocks = {0};
1472         struct smu_clock_info hw_clocks;
1473         int ret = 0;
1474
1475         if (!is_support_sw_smu(smu->adev))
1476                 return -EINVAL;
1477
1478         mutex_lock(&smu->mutex);
1479
1480         smu_get_dal_power_level(smu, &simple_clocks);
1481
1482         if (smu->support_power_containment)
1483                 ret = smu_get_clock_info(smu, &hw_clocks,
1484                                          PERF_LEVEL_POWER_CONTAINMENT);
1485         else
1486                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1487
1488         if (ret) {
1489                 pr_err("Error in smu_get_clock_info\n");
1490                 goto failed;
1491         }
1492
1493         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1494         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1495         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1496         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1497         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1498         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1499         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1500         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1501
1502         if (simple_clocks.level == 0)
1503                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1504         else
1505                 clocks->max_clocks_state = simple_clocks.level;
1506
1507         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1508                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1509                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1510         }
1511
1512 failed:
1513         mutex_unlock(&smu->mutex);
1514         return ret;
1515 }
1516
1517 static int smu_set_clockgating_state(void *handle,
1518                                      enum amd_clockgating_state state)
1519 {
1520         return 0;
1521 }
1522
1523 static int smu_set_powergating_state(void *handle,
1524                                      enum amd_powergating_state state)
1525 {
1526         return 0;
1527 }
1528
1529 static int smu_enable_umd_pstate(void *handle,
1530                       enum amd_dpm_forced_level *level)
1531 {
1532         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1533                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1534                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1535                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1536
1537         struct smu_context *smu = (struct smu_context*)(handle);
1538         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1539         if (!smu->pm_enabled || !smu_dpm_ctx->dpm_context)
1540                 return -EINVAL;
1541
1542         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1543                 /* enter umd pstate, save current level, disable gfx cg*/
1544                 if (*level & profile_mode_mask) {
1545                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1546                         smu_dpm_ctx->enable_umd_pstate = true;
1547                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1548                                                                AMD_IP_BLOCK_TYPE_GFX,
1549                                                                AMD_CG_STATE_UNGATE);
1550                         amdgpu_device_ip_set_powergating_state(smu->adev,
1551                                                                AMD_IP_BLOCK_TYPE_GFX,
1552                                                                AMD_PG_STATE_UNGATE);
1553                 }
1554         } else {
1555                 /* exit umd pstate, restore level, enable gfx cg*/
1556                 if (!(*level & profile_mode_mask)) {
1557                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1558                                 *level = smu_dpm_ctx->saved_dpm_level;
1559                         smu_dpm_ctx->enable_umd_pstate = false;
1560                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1561                                                                AMD_IP_BLOCK_TYPE_GFX,
1562                                                                AMD_CG_STATE_GATE);
1563                         amdgpu_device_ip_set_powergating_state(smu->adev,
1564                                                                AMD_IP_BLOCK_TYPE_GFX,
1565                                                                AMD_PG_STATE_GATE);
1566                 }
1567         }
1568
1569         return 0;
1570 }
1571
1572 static int smu_default_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1573 {
1574         int ret = 0;
1575         uint32_t sclk_mask, mclk_mask, soc_mask;
1576
1577         switch (level) {
1578         case AMD_DPM_FORCED_LEVEL_HIGH:
1579                 ret = smu_force_dpm_limit_value(smu, true);
1580                 break;
1581         case AMD_DPM_FORCED_LEVEL_LOW:
1582                 ret = smu_force_dpm_limit_value(smu, false);
1583                 break;
1584         case AMD_DPM_FORCED_LEVEL_AUTO:
1585         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1586                 ret = smu_unforce_dpm_levels(smu);
1587                 break;
1588         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1589         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1590         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1591                 ret = smu_get_profiling_clk_mask(smu, level,
1592                                                  &sclk_mask,
1593                                                  &mclk_mask,
1594                                                  &soc_mask);
1595                 if (ret)
1596                         return ret;
1597                 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
1598                 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
1599                 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
1600                 break;
1601         case AMD_DPM_FORCED_LEVEL_MANUAL:
1602         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1603         default:
1604                 break;
1605         }
1606         return ret;
1607 }
1608
1609 int smu_adjust_power_state_dynamic(struct smu_context *smu,
1610                                    enum amd_dpm_forced_level level,
1611                                    bool skip_display_settings)
1612 {
1613         int ret = 0;
1614         int index = 0;
1615         long workload;
1616         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1617
1618         if (!smu->pm_enabled)
1619                 return -EINVAL;
1620
1621         if (!skip_display_settings) {
1622                 ret = smu_display_config_changed(smu);
1623                 if (ret) {
1624                         pr_err("Failed to change display config!");
1625                         return ret;
1626                 }
1627         }
1628
1629         ret = smu_apply_clocks_adjust_rules(smu);
1630         if (ret) {
1631                 pr_err("Failed to apply clocks adjust rules!");
1632                 return ret;
1633         }
1634
1635         if (!skip_display_settings) {
1636                 ret = smu_notify_smc_dispaly_config(smu);
1637                 if (ret) {
1638                         pr_err("Failed to notify smc display config!");
1639                         return ret;
1640                 }
1641         }
1642
1643         if (smu_dpm_ctx->dpm_level != level) {
1644                 ret = smu_asic_set_performance_level(smu, level);
1645                 if (ret) {
1646                         ret = smu_default_set_performance_level(smu, level);
1647                         if (ret) {
1648                                 pr_err("Failed to set performance level!");
1649                                 return ret;
1650                         }
1651                 }
1652
1653                 /* update the saved copy */
1654                 smu_dpm_ctx->dpm_level = level;
1655         }
1656
1657         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1658                 index = fls(smu->workload_mask);
1659                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1660                 workload = smu->workload_setting[index];
1661
1662                 if (smu->power_profile_mode != workload)
1663                         smu_set_power_profile_mode(smu, &workload, 0);
1664         }
1665
1666         return ret;
1667 }
1668
1669 int smu_handle_task(struct smu_context *smu,
1670                     enum amd_dpm_forced_level level,
1671                     enum amd_pp_task task_id)
1672 {
1673         int ret = 0;
1674
1675         switch (task_id) {
1676         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1677                 ret = smu_pre_display_config_changed(smu);
1678                 if (ret)
1679                         return ret;
1680                 ret = smu_set_cpu_power_state(smu);
1681                 if (ret)
1682                         return ret;
1683                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1684                 break;
1685         case AMD_PP_TASK_COMPLETE_INIT:
1686         case AMD_PP_TASK_READJUST_POWER_STATE:
1687                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1688                 break;
1689         default:
1690                 break;
1691         }
1692
1693         return ret;
1694 }
1695
1696 int smu_switch_power_profile(struct smu_context *smu,
1697                              enum PP_SMC_POWER_PROFILE type,
1698                              bool en)
1699 {
1700         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1701         long workload;
1702         uint32_t index;
1703
1704         if (!smu->pm_enabled)
1705                 return -EINVAL;
1706
1707         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1708                 return -EINVAL;
1709
1710         mutex_lock(&smu->mutex);
1711
1712         if (!en) {
1713                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1714                 index = fls(smu->workload_mask);
1715                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1716                 workload = smu->workload_setting[index];
1717         } else {
1718                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1719                 index = fls(smu->workload_mask);
1720                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1721                 workload = smu->workload_setting[index];
1722         }
1723
1724         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1725                 smu_set_power_profile_mode(smu, &workload, 0);
1726
1727         mutex_unlock(&smu->mutex);
1728
1729         return 0;
1730 }
1731
1732 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1733 {
1734         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1735         enum amd_dpm_forced_level level;
1736
1737         if (!smu_dpm_ctx->dpm_context)
1738                 return -EINVAL;
1739
1740         mutex_lock(&(smu->mutex));
1741         level = smu_dpm_ctx->dpm_level;
1742         mutex_unlock(&(smu->mutex));
1743
1744         return level;
1745 }
1746
1747 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1748 {
1749         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1750         int ret = 0;
1751
1752         if (!smu_dpm_ctx->dpm_context)
1753                 return -EINVAL;
1754
1755         ret = smu_enable_umd_pstate(smu, &level);
1756         if (ret)
1757                 return ret;
1758
1759         ret = smu_handle_task(smu, level,
1760                               AMD_PP_TASK_READJUST_POWER_STATE);
1761
1762         return ret;
1763 }
1764
1765 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1766 {
1767         int ret = 0;
1768
1769         mutex_lock(&smu->mutex);
1770         ret = smu_init_display_count(smu, count);
1771         mutex_unlock(&smu->mutex);
1772
1773         return ret;
1774 }
1775
1776 const struct amd_ip_funcs smu_ip_funcs = {
1777         .name = "smu",
1778         .early_init = smu_early_init,
1779         .late_init = smu_late_init,
1780         .sw_init = smu_sw_init,
1781         .sw_fini = smu_sw_fini,
1782         .hw_init = smu_hw_init,
1783         .hw_fini = smu_hw_fini,
1784         .suspend = smu_suspend,
1785         .resume = smu_resume,
1786         .is_idle = NULL,
1787         .check_soft_reset = NULL,
1788         .wait_for_idle = NULL,
1789         .soft_reset = NULL,
1790         .set_clockgating_state = smu_set_clockgating_state,
1791         .set_powergating_state = smu_set_powergating_state,
1792         .enable_umd_pstate = smu_enable_umd_pstate,
1793 };
1794
1795 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1796 {
1797         .type = AMD_IP_BLOCK_TYPE_SMC,
1798         .major = 11,
1799         .minor = 0,
1800         .rev = 0,
1801         .funcs = &smu_ip_funcs,
1802 };
1803
1804 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
1805 {
1806         .type = AMD_IP_BLOCK_TYPE_SMC,
1807         .major = 12,
1808         .minor = 0,
1809         .rev = 0,
1810         .funcs = &smu_ip_funcs,
1811 };