drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/pci.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_internal.h"
  29 #include "smu_v11_0.h"
  30 #include "smu_v12_0.h"
  31 #include "atom.h"
  32 #include "arcturus_ppt.h"
  33 #include "navi10_ppt.h"
  34 #include "sienna_cichlid_ppt.h"
  35 #include "renoir_ppt.h"
  36
  37 #undef __SMU_DUMMY_MAP
  38 #define __SMU_DUMMY_MAP(type)   #type
  39 static const char* __smu_message_names[] = {
  40         SMU_MESSAGE_TYPES
  41 };
  42
  43 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
  44 {
  45         if (type < 0 || type >= SMU_MSG_MAX_COUNT)
  46                 return "unknown smu message";
  47         return __smu_message_names[type];
  48 }
  49
  50 #undef __SMU_DUMMY_MAP
  51 #define __SMU_DUMMY_MAP(fea)    #fea
  52 static const char* __smu_feature_names[] = {
  53         SMU_FEATURE_MASKS
  54 };
  55
  56 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
  57 {
  58         if (feature < 0 || feature >= SMU_FEATURE_COUNT)
  59                 return "unknown smu feature";
  60         return __smu_feature_names[feature];
  61 }
  62
  63 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
  64 {
  65         size_t size = 0;
  66         int ret = 0, i = 0;
  67         uint32_t feature_mask[2] = { 0 };
  68         int32_t feature_index = 0;
  69         uint32_t count = 0;
  70         uint32_t sort_feature[SMU_FEATURE_COUNT];
  71         uint64_t hw_feature_count = 0;
  72
  73         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  74                 return -EOPNOTSUPP;
  75
  76         mutex_lock(&smu->mutex);
  77
  78         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
  79         if (ret)
  80                 goto failed;
  81
  82         size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
  83                         feature_mask[1], feature_mask[0]);
  84
  85         for (i = 0; i < SMU_FEATURE_COUNT; i++) {
  86                 feature_index = smu_feature_get_index(smu, i);
  87                 if (feature_index < 0)
  88                         continue;
  89                 sort_feature[feature_index] = i;
  90                 hw_feature_count++;
  91         }
  92
  93         for (i = 0; i < hw_feature_count; i++) {
  94                 size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
  95                                count++,
  96                                smu_get_feature_name(smu, sort_feature[i]),
  97                                i,
  98                                !!smu_feature_is_enabled(smu, sort_feature[i]) ?
  99                                "enabled" : "disabled");
 100         }
 101
 102 failed:
 103         mutex_unlock(&smu->mutex);
 104
 105         return size;
 106 }
 107
 108 static int smu_feature_update_enable_state(struct smu_context *smu,
 109                                            uint64_t feature_mask,
 110                                            bool enabled)
 111 {
 112         struct smu_feature *feature = &smu->smu_feature;
 113         int ret = 0;
 114
 115         if (enabled) {
 116                 ret = smu_send_smc_msg_with_param(smu,
 117                                                   SMU_MSG_EnableSmuFeaturesLow,
 118                                                   lower_32_bits(feature_mask),
 119                                                   NULL);
 120                 if (ret)
 121                         return ret;
 122                 ret = smu_send_smc_msg_with_param(smu,
 123                                                   SMU_MSG_EnableSmuFeaturesHigh,
 124                                                   upper_32_bits(feature_mask),
 125                                                   NULL);
 126                 if (ret)
 127                         return ret;
 128         } else {
 129                 ret = smu_send_smc_msg_with_param(smu,
 130                                                   SMU_MSG_DisableSmuFeaturesLow,
 131                                                   lower_32_bits(feature_mask),
 132                                                   NULL);
 133                 if (ret)
 134                         return ret;
 135                 ret = smu_send_smc_msg_with_param(smu,
 136                                                   SMU_MSG_DisableSmuFeaturesHigh,
 137                                                   upper_32_bits(feature_mask),
 138                                                   NULL);
 139                 if (ret)
 140                         return ret;
 141         }
 142
 143         mutex_lock(&feature->mutex);
 144         if (enabled)
 145                 bitmap_or(feature->enabled, feature->enabled,
 146                                 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
 147         else
 148                 bitmap_andnot(feature->enabled, feature->enabled,
 149                                 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
 150         mutex_unlock(&feature->mutex);
 151
 152         return ret;
 153 }
 154
 155 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
 156 {
 157         int ret = 0;
 158         uint32_t feature_mask[2] = { 0 };
 159         uint64_t feature_2_enabled = 0;
 160         uint64_t feature_2_disabled = 0;
 161         uint64_t feature_enables = 0;
 162
 163         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 164                 return -EOPNOTSUPP;
 165
 166         mutex_lock(&smu->mutex);
 167
 168         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 169         if (ret)
 170                 goto out;
 171
 172         feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
 173
 174         feature_2_enabled  = ~feature_enables & new_mask;
 175         feature_2_disabled = feature_enables & ~new_mask;
 176
 177         if (feature_2_enabled) {
 178                 ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
 179                 if (ret)
 180                         goto out;
 181         }
 182         if (feature_2_disabled) {
 183                 ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
 184                 if (ret)
 185                         goto out;
 186         }
 187
 188 out:
 189         mutex_unlock(&smu->mutex);
 190
 191         return ret;
 192 }
 193
 194 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
 195 {
 196         int ret = 0;
 197
 198         if (!if_version && !smu_version)
 199                 return -EINVAL;
 200
 201         if (smu->smc_fw_if_version && smu->smc_fw_version)
 202         {
 203                 if (if_version)
 204                         *if_version = smu->smc_fw_if_version;
 205
 206                 if (smu_version)
 207                         *smu_version = smu->smc_fw_version;
 208
 209                 return 0;
 210         }
 211
 212         if (if_version) {
 213                 ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion, if_version);
 214                 if (ret)
 215                         return ret;
 216
 217                 smu->smc_fw_if_version = *if_version;
 218         }
 219
 220         if (smu_version) {
 221                 ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion, smu_version);
 222                 if (ret)
 223                         return ret;
 224
 225                 smu->smc_fw_version = *smu_version;
 226         }
 227
 228         return ret;
 229 }
 230
 231 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 232                             uint32_t min, uint32_t max, bool lock_needed)
 233 {
 234         int ret = 0;
 235
 236         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 237                 return 0;
 238
 239         if (lock_needed)
 240                 mutex_lock(&smu->mutex);
 241         ret = smu_set_soft_freq_limited_range(smu, clk_type, min, max);
 242         if (lock_needed)
 243                 mutex_unlock(&smu->mutex);
 244
 245         return ret;
 246 }
 247
 248 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 249                             uint32_t min, uint32_t max)
 250 {
 251         int ret = 0, clk_id = 0;
 252         uint32_t param;
 253
 254         if (min <= 0 && max <= 0)
 255                 return -EINVAL;
 256
 257         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 258                 return 0;
 259
 260         clk_id = smu_clk_get_index(smu, clk_type);
 261         if (clk_id < 0)
 262                 return clk_id;
 263
 264         if (max > 0) {
 265                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
 266                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
 267                                                   param, NULL);
 268                 if (ret)
 269                         return ret;
 270         }
 271
 272         if (min > 0) {
 273                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
 274                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
 275                                                   param, NULL);
 276                 if (ret)
 277                         return ret;
 278         }
 279
 280
 281         return ret;
 282 }
 283
 284 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 285                            uint32_t *min, uint32_t *max, bool lock_needed)
 286 {
 287         uint32_t clock_limit;
 288         int ret = 0;
 289
 290         if (!min && !max)
 291                 return -EINVAL;
 292
 293         if (lock_needed)
 294                 mutex_lock(&smu->mutex);
 295
 296         if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
 297                 switch (clk_type) {
 298                 case SMU_MCLK:
 299                 case SMU_UCLK:
 300                         clock_limit = smu->smu_table.boot_values.uclk;
 301                         break;
 302                 case SMU_GFXCLK:
 303                 case SMU_SCLK:
 304                         clock_limit = smu->smu_table.boot_values.gfxclk;
 305                         break;
 306                 case SMU_SOCCLK:
 307                         clock_limit = smu->smu_table.boot_values.socclk;
 308                         break;
 309                 default:
 310                         clock_limit = 0;
 311                         break;
 312                 }
 313
 314                 /* clock in Mhz unit */
 315                 if (min)
 316                         *min = clock_limit / 100;
 317                 if (max)
 318                         *max = clock_limit / 100;
 319         } else {
 320                 /*
 321                  * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
 322                  * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
 323                  */
 324                 ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
 325         }
 326
 327         if (lock_needed)
 328                 mutex_unlock(&smu->mutex);
 329
 330         return ret;
 331 }
 332
 333 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
 334                               uint16_t level, uint32_t *value)
 335 {
 336         int ret = 0, clk_id = 0;
 337         uint32_t param;
 338
 339         if (!value)
 340                 return -EINVAL;
 341
 342         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 343                 return 0;
 344
 345         clk_id = smu_clk_get_index(smu, clk_type);
 346         if (clk_id < 0)
 347                 return clk_id;
 348
 349         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
 350
 351         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmFreqByIndex,
 352                                           param, value);
 353         if (ret)
 354                 return ret;
 355
 356         /* BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
 357          * now, we un-support it */
 358         *value = *value & 0x7fffffff;
 359
 360         return ret;
 361 }
 362
 363 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
 364                             uint32_t *value)
 365 {
 366         return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
 367 }
 368
 369 int smu_get_dpm_level_range(struct smu_context *smu, enum smu_clk_type clk_type,
 370                             uint32_t *min_value, uint32_t *max_value)
 371 {
 372         int ret = 0;
 373         uint32_t level_count = 0;
 374
 375         if (!min_value && !max_value)
 376                 return -EINVAL;
 377
 378         if (min_value) {
 379                 /* by default, level 0 clock value as min value */
 380                 ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, min_value);
 381                 if (ret)
 382                         return ret;
 383         }
 384
 385         if (max_value) {
 386                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
 387                 if (ret)
 388                         return ret;
 389
 390                 ret = smu_get_dpm_freq_by_index(smu, clk_type, level_count - 1, max_value);
 391                 if (ret)
 392                         return ret;
 393         }
 394
 395         return ret;
 396 }
 397
 398 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
 399 {
 400         enum smu_feature_mask feature_id = 0;
 401
 402         switch (clk_type) {
 403         case SMU_MCLK:
 404         case SMU_UCLK:
 405                 feature_id = SMU_FEATURE_DPM_UCLK_BIT;
 406                 break;
 407         case SMU_GFXCLK:
 408         case SMU_SCLK:
 409                 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
 410                 break;
 411         case SMU_SOCCLK:
 412                 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
 413                 break;
 414         default:
 415                 return true;
 416         }
 417
 418         if(!smu_feature_is_enabled(smu, feature_id)) {
 419                 return false;
 420         }
 421
 422         return true;
 423 }
 424
 425 /**
 426  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
 427  *
 428  * @smu:        smu_context pointer
 429  * @block_type: the IP block to power gate/ungate
 430  * @gate:       to power gate if true, ungate otherwise
 431  *
 432  * This API uses no smu->mutex lock protection due to:
 433  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
 434  *    This is guarded to be race condition free by the caller.
 435  * 2. Or get called on user setting request of power_dpm_force_performance_level.
 436  *    Under this case, the smu->mutex lock protection is already enforced on
 437  *    the parent API smu_force_performance_level of the call path.
 438  */
 439 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 440                            bool gate)
 441 {
 442         int ret = 0;
 443
 444         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 445                 return -EOPNOTSUPP;
 446
 447         switch (block_type) {
 448         case AMD_IP_BLOCK_TYPE_UVD:
 449                 ret = smu_dpm_set_uvd_enable(smu, !gate);
 450                 break;
 451         case AMD_IP_BLOCK_TYPE_VCE:
 452                 ret = smu_dpm_set_vce_enable(smu, !gate);
 453                 break;
 454         case AMD_IP_BLOCK_TYPE_GFX:
 455                 ret = smu_gfx_off_control(smu, gate);
 456                 break;
 457         case AMD_IP_BLOCK_TYPE_SDMA:
 458                 ret = smu_powergate_sdma(smu, gate);
 459                 break;
 460         case AMD_IP_BLOCK_TYPE_JPEG:
 461                 ret = smu_dpm_set_jpeg_enable(smu, !gate);
 462                 break;
 463         default:
 464                 break;
 465         }
 466
 467         return ret;
 468 }
 469
 470 int smu_get_power_num_states(struct smu_context *smu,
 471                              struct pp_states_info *state_info)
 472 {
 473         if (!state_info)
 474                 return -EINVAL;
 475
 476         /* not support power state */
 477         memset(state_info, 0, sizeof(struct pp_states_info));
 478         state_info->nums = 1;
 479         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 480
 481         return 0;
 482 }
 483
 484 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
 485                            void *data, uint32_t *size)
 486 {
 487         struct smu_power_context *smu_power = &smu->smu_power;
 488         struct smu_power_gate *power_gate = &smu_power->power_gate;
 489         int ret = 0;
 490
 491         if(!data || !size)
 492                 return -EINVAL;
 493
 494         switch (sensor) {
 495         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
 496                 *((uint32_t *)data) = smu->pstate_sclk;
 497                 *size = 4;
 498                 break;
 499         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
 500                 *((uint32_t *)data) = smu->pstate_mclk;
 501                 *size = 4;
 502                 break;
 503         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
 504                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
 505                 *size = 8;
 506                 break;
 507         case AMDGPU_PP_SENSOR_UVD_POWER:
 508                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
 509                 *size = 4;
 510                 break;
 511         case AMDGPU_PP_SENSOR_VCE_POWER:
 512                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
 513                 *size = 4;
 514                 break;
 515         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
 516                 *(uint32_t *)data = power_gate->vcn_gated ? 0 : 1;
 517                 *size = 4;
 518                 break;
 519         default:
 520                 ret = -EINVAL;
 521                 break;
 522         }
 523
 524         if (ret)
 525                 *size = 0;
 526
 527         return ret;
 528 }
 529
 530 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
 531                      void *table_data, bool drv2smu)
 532 {
 533         struct smu_table_context *smu_table = &smu->smu_table;
 534         struct amdgpu_device *adev = smu->adev;
 535         struct smu_table *table = &smu_table->driver_table;
 536         int table_id = smu_table_get_index(smu, table_index);
 537         uint32_t table_size;
 538         int ret = 0;
 539         if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0)
 540                 return -EINVAL;
 541
 542         table_size = smu_table->tables[table_index].size;
 543
 544         if (drv2smu) {
 545                 memcpy(table->cpu_addr, table_data, table_size);
 546                 /*
 547                  * Flush hdp cache: to guard the content seen by
 548                  * GPU is consitent with CPU.
 549                  */
 550                 amdgpu_asic_flush_hdp(adev, NULL);
 551         }
 552
 553         ret = smu_send_smc_msg_with_param(smu, drv2smu ?
 554                                           SMU_MSG_TransferTableDram2Smu :
 555                                           SMU_MSG_TransferTableSmu2Dram,
 556                                           table_id | ((argument & 0xFFFF) << 16),
 557                                           NULL);
 558         if (ret)
 559                 return ret;
 560
 561         if (!drv2smu) {
 562                 amdgpu_asic_flush_hdp(adev, NULL);
 563                 memcpy(table_data, table->cpu_addr, table_size);
 564         }
 565
 566         return ret;
 567 }
 568
 569 bool is_support_sw_smu(struct amdgpu_device *adev)
 570 {
 571         if (adev->asic_type >= CHIP_ARCTURUS)
 572                 return true;
 573
 574         return false;
 575 }
 576
 577 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 578 {
 579         struct smu_table_context *smu_table = &smu->smu_table;
 580         uint32_t powerplay_table_size;
 581
 582         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 583                 return -EOPNOTSUPP;
 584
 585         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 586                 return -EINVAL;
 587
 588         mutex_lock(&smu->mutex);
 589
 590         if (smu_table->hardcode_pptable)
 591                 *table = smu_table->hardcode_pptable;
 592         else
 593                 *table = smu_table->power_play_table;
 594
 595         powerplay_table_size = smu_table->power_play_table_size;
 596
 597         mutex_unlock(&smu->mutex);
 598
 599         return powerplay_table_size;
 600 }
 601
 602 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 603 {
 604         struct smu_table_context *smu_table = &smu->smu_table;
 605         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 606         int ret = 0;
 607
 608         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 609                 return -EOPNOTSUPP;
 610
 611         if (header->usStructureSize != size) {
 612                 pr_err("pp table size not matched !\n");
 613                 return -EIO;
 614         }
 615
 616         mutex_lock(&smu->mutex);
 617         if (!smu_table->hardcode_pptable)
 618                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 619         if (!smu_table->hardcode_pptable) {
 620                 ret = -ENOMEM;
 621                 goto failed;
 622         }
 623
 624         memcpy(smu_table->hardcode_pptable, buf, size);
 625         smu_table->power_play_table = smu_table->hardcode_pptable;
 626         smu_table->power_play_table_size = size;
 627
 628         /*
 629          * Special hw_fini action(for Navi1x, the DPMs disablement will be
 630          * skipped) may be needed for custom pptable uploading.
 631          */
 632         smu->uploading_custom_pp_table = true;
 633
 634         ret = smu_reset(smu);
 635         if (ret)
 636                 pr_info("smu reset failed, ret = %d\n", ret);
 637
 638         smu->uploading_custom_pp_table = false;
 639
 640 failed:
 641         mutex_unlock(&smu->mutex);
 642         return ret;
 643 }
 644
 645 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
 646 {
 647         struct smu_feature *feature = &smu->smu_feature;
 648         int ret = 0;
 649         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 650
 651         mutex_lock(&feature->mutex);
 652         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 653         mutex_unlock(&feature->mutex);
 654
 655         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 656                                              SMU_FEATURE_MAX/32);
 657         if (ret)
 658                 return ret;
 659
 660         mutex_lock(&feature->mutex);
 661         bitmap_or(feature->allowed, feature->allowed,
 662                       (unsigned long *)allowed_feature_mask,
 663                       feature->feature_num);
 664         mutex_unlock(&feature->mutex);
 665
 666         return ret;
 667 }
 668
 669 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
 670 {
 671         struct smu_feature *feature = &smu->smu_feature;
 672         int feature_id;
 673         int ret = 0;
 674
 675         if (smu->is_apu)
 676                 return 1;
 677         feature_id = smu_feature_get_index(smu, mask);
 678         if (feature_id < 0)
 679                 return 0;
 680
 681         WARN_ON(feature_id > feature->feature_num);
 682
 683         mutex_lock(&feature->mutex);
 684         ret = test_bit(feature_id, feature->enabled);
 685         mutex_unlock(&feature->mutex);
 686
 687         return ret;
 688 }
 689
 690 int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
 691                             bool enable)
 692 {
 693         struct smu_feature *feature = &smu->smu_feature;
 694         int feature_id;
 695
 696         feature_id = smu_feature_get_index(smu, mask);
 697         if (feature_id < 0)
 698                 return -EINVAL;
 699
 700         WARN_ON(feature_id > feature->feature_num);
 701
 702         return smu_feature_update_enable_state(smu,
 703                                                1ULL << feature_id,
 704                                                enable);
 705 }
 706
 707 int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
 708 {
 709         struct smu_feature *feature = &smu->smu_feature;
 710         int feature_id;
 711         int ret = 0;
 712
 713         feature_id = smu_feature_get_index(smu, mask);
 714         if (feature_id < 0)
 715                 return 0;
 716
 717         WARN_ON(feature_id > feature->feature_num);
 718
 719         mutex_lock(&feature->mutex);
 720         ret = test_bit(feature_id, feature->supported);
 721         mutex_unlock(&feature->mutex);
 722
 723         return ret;
 724 }
 725
 726 static int smu_set_funcs(struct amdgpu_device *adev)
 727 {
 728         struct smu_context *smu = &adev->smu;
 729
 730         if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 731                 smu->od_enabled = true;
 732
 733         switch (adev->asic_type) {
 734         case CHIP_NAVI10:
 735         case CHIP_NAVI14:
 736         case CHIP_NAVI12:
 737                 navi10_set_ppt_funcs(smu);
 738                 break;
 739         case CHIP_ARCTURUS:
 740                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 741                 arcturus_set_ppt_funcs(smu);
 742                 /* OD is not supported on Arcturus */
 743                 smu->od_enabled =false;
 744                 break;
 745         case CHIP_SIENNA_CICHLID:
 746                 sienna_cichlid_set_ppt_funcs(smu);
 747                 break;
 748         case CHIP_RENOIR:
 749                 renoir_set_ppt_funcs(smu);
 750                 break;
 751         default:
 752                 return -EINVAL;
 753         }
 754
 755         return 0;
 756 }
 757
 758 static int smu_early_init(void *handle)
 759 {
 760         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 761         struct smu_context *smu = &adev->smu;
 762
 763         smu->adev = adev;
 764         smu->pm_enabled = !!amdgpu_dpm;
 765         smu->is_apu = false;
 766         mutex_init(&smu->mutex);
 767
 768         return smu_set_funcs(adev);
 769 }
 770
 771 static int smu_late_init(void *handle)
 772 {
 773         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 774         struct smu_context *smu = &adev->smu;
 775         int ret = 0;
 776
 777         if (!smu->pm_enabled)
 778                 return 0;
 779
 780         ret = smu_set_default_od_settings(smu);
 781         if (ret)
 782                 return ret;
 783
 784         /*
 785          * Set initialized values (get from vbios) to dpm tables context such as
 786          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
 787          * type of clks.
 788          */
 789         ret = smu_populate_smc_tables(smu);
 790         if (ret)
 791                 return ret;
 792
 793         ret = smu_init_max_sustainable_clocks(smu);
 794         if (ret)
 795                 return ret;
 796
 797         ret = smu_populate_umd_state_clk(smu);
 798         if (ret)
 799                 return ret;
 800
 801         ret = smu_get_power_limit(smu, &smu->default_power_limit, false, false);
 802         if (ret)
 803                 return ret;
 804
 805         smu_get_unique_id(smu);
 806
 807         smu_handle_task(&adev->smu,
 808                         smu->smu_dpm.dpm_level,
 809                         AMD_PP_TASK_COMPLETE_INIT,
 810                         false);
 811
 812         return 0;
 813 }
 814
 815 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
 816                             uint16_t *size, uint8_t *frev, uint8_t *crev,
 817                             uint8_t **addr)
 818 {
 819         struct amdgpu_device *adev = smu->adev;
 820         uint16_t data_start;
 821
 822         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
 823                                            size, frev, crev, &data_start))
 824                 return -EINVAL;
 825
 826         *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
 827
 828         return 0;
 829 }
 830
 831 static int smu_init_fb_allocations(struct smu_context *smu)
 832 {
 833         struct amdgpu_device *adev = smu->adev;
 834         struct smu_table_context *smu_table = &smu->smu_table;
 835         struct smu_table *tables = smu_table->tables;
 836         struct smu_table *driver_table = &(smu_table->driver_table);
 837         uint32_t max_table_size = 0;
 838         int ret, i;
 839
 840         /* VRAM allocation for tool table */
 841         if (tables[SMU_TABLE_PMSTATUSLOG].size) {
 842                 ret = amdgpu_bo_create_kernel(adev,
 843                                               tables[SMU_TABLE_PMSTATUSLOG].size,
 844                                               tables[SMU_TABLE_PMSTATUSLOG].align,
 845                                               tables[SMU_TABLE_PMSTATUSLOG].domain,
 846                                               &tables[SMU_TABLE_PMSTATUSLOG].bo,
 847                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 848                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 849                 if (ret) {
 850                         pr_err("VRAM allocation for tool table failed!\n");
 851                         return ret;
 852                 }
 853         }
 854
 855         /* VRAM allocation for driver table */
 856         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 857                 if (tables[i].size == 0)
 858                         continue;
 859
 860                 if (i == SMU_TABLE_PMSTATUSLOG)
 861                         continue;
 862
 863                 if (max_table_size < tables[i].size)
 864                         max_table_size = tables[i].size;
 865         }
 866
 867         driver_table->size = max_table_size;
 868         driver_table->align = PAGE_SIZE;
 869         driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 870
 871         ret = amdgpu_bo_create_kernel(adev,
 872                                       driver_table->size,
 873                                       driver_table->align,
 874                                       driver_table->domain,
 875                                       &driver_table->bo,
 876                                       &driver_table->mc_address,
 877                                       &driver_table->cpu_addr);
 878         if (ret) {
 879                 pr_err("VRAM allocation for driver table failed!\n");
 880                 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 881                         amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 882                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 883                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 884         }
 885
 886         return ret;
 887 }
 888
 889 static int smu_fini_fb_allocations(struct smu_context *smu)
 890 {
 891         struct smu_table_context *smu_table = &smu->smu_table;
 892         struct smu_table *tables = smu_table->tables;
 893         struct smu_table *driver_table = &(smu_table->driver_table);
 894
 895         if (!tables)
 896                 return 0;
 897
 898         if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 899                 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 900                                       &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 901                                       &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 902
 903         amdgpu_bo_free_kernel(&driver_table->bo,
 904                               &driver_table->mc_address,
 905                               &driver_table->cpu_addr);
 906
 907         return 0;
 908 }
 909
 910 /**
 911  * smu_alloc_memory_pool - allocate memory pool in the system memory
 912  *
 913  * @smu: amdgpu_device pointer
 914  *
 915  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
 916  * and DramLogSetDramAddr can notify it changed.
 917  *
 918  * Returns 0 on success, error on failure.
 919  */
 920 static int smu_alloc_memory_pool(struct smu_context *smu)
 921 {
 922         struct amdgpu_device *adev = smu->adev;
 923         struct smu_table_context *smu_table = &smu->smu_table;
 924         struct smu_table *memory_pool = &smu_table->memory_pool;
 925         uint64_t pool_size = smu->pool_size;
 926         int ret = 0;
 927
 928         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
 929                 return ret;
 930
 931         memory_pool->size = pool_size;
 932         memory_pool->align = PAGE_SIZE;
 933         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
 934
 935         switch (pool_size) {
 936         case SMU_MEMORY_POOL_SIZE_256_MB:
 937         case SMU_MEMORY_POOL_SIZE_512_MB:
 938         case SMU_MEMORY_POOL_SIZE_1_GB:
 939         case SMU_MEMORY_POOL_SIZE_2_GB:
 940                 ret = amdgpu_bo_create_kernel(adev,
 941                                               memory_pool->size,
 942                                               memory_pool->align,
 943                                               memory_pool->domain,
 944                                               &memory_pool->bo,
 945                                               &memory_pool->mc_address,
 946                                               &memory_pool->cpu_addr);
 947                 break;
 948         default:
 949                 break;
 950         }
 951
 952         return ret;
 953 }
 954
 955 static int smu_free_memory_pool(struct smu_context *smu)
 956 {
 957         struct smu_table_context *smu_table = &smu->smu_table;
 958         struct smu_table *memory_pool = &smu_table->memory_pool;
 959
 960         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
 961                 return 0;
 962
 963         amdgpu_bo_free_kernel(&memory_pool->bo,
 964                               &memory_pool->mc_address,
 965                               &memory_pool->cpu_addr);
 966
 967         memset(memory_pool, 0, sizeof(struct smu_table));
 968
 969         return 0;
 970 }
 971
 972 static int smu_smc_table_sw_init(struct smu_context *smu)
 973 {
 974         int ret;
 975
 976         /**
 977          * Create smu_table structure, and init smc tables such as
 978          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 979          */
 980         ret = smu_init_smc_tables(smu);
 981         if (ret) {
 982                 pr_err("Failed to init smc tables!\n");
 983                 return ret;
 984         }
 985
 986         /**
 987          * Create smu_power_context structure, and allocate smu_dpm_context and
 988          * context size to fill the smu_power_context data.
 989          */
 990         ret = smu_init_power(smu);
 991         if (ret) {
 992                 pr_err("Failed to init smu_init_power!\n");
 993                 return ret;
 994         }
 995
 996         /*
 997          * allocate vram bos to store smc table contents.
 998          */
 999         ret = smu_init_fb_allocations(smu);
1000         if (ret)
1001                 return ret;
1002
1003         ret = smu_alloc_memory_pool(smu);
1004         if (ret)
1005                 return ret;
1006
1007         return 0;
1008 }
1009
1010 static int smu_smc_table_sw_fini(struct smu_context *smu)
1011 {
1012         int ret;
1013
1014         ret = smu_free_memory_pool(smu);
1015         if (ret)
1016                 return ret;
1017
1018         ret = smu_fini_fb_allocations(smu);
1019         if (ret)
1020                 return ret;
1021
1022         ret = smu_fini_power(smu);
1023         if (ret) {
1024                 pr_err("Failed to init smu_fini_power!\n");
1025                 return ret;
1026         }
1027
1028         ret = smu_fini_smc_tables(smu);
1029         if (ret) {
1030                 pr_err("Failed to smu_fini_smc_tables!\n");
1031                 return ret;
1032         }
1033
1034         return 0;
1035 }
1036
1037 static int smu_sw_init(void *handle)
1038 {
1039         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1040         struct smu_context *smu = &adev->smu;
1041         int ret;
1042
1043         smu->pool_size = adev->pm.smu_prv_buffer_size;
1044         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
1045         mutex_init(&smu->smu_feature.mutex);
1046         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
1047         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
1048         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
1049
1050         mutex_init(&smu->smu_baco.mutex);
1051         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
1052         smu->smu_baco.platform_support = false;
1053
1054         mutex_init(&smu->sensor_lock);
1055         mutex_init(&smu->metrics_lock);
1056         mutex_init(&smu->message_lock);
1057
1058         smu->watermarks_bitmap = 0;
1059         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1060         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1061
1062         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
1063         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
1064         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
1065         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
1066         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
1067         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
1068         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
1069         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
1070
1071         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1072         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1073         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
1074         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
1075         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
1076         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
1077         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
1078         smu->display_config = &adev->pm.pm_display_cfg;
1079
1080         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1081         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1082         ret = smu_init_microcode(smu);
1083         if (ret) {
1084                 pr_err("Failed to load smu firmware!\n");
1085                 return ret;
1086         }
1087
1088         ret = smu_smc_table_sw_init(smu);
1089         if (ret) {
1090                 pr_err("Failed to sw init smc table!\n");
1091                 return ret;
1092         }
1093
1094         ret = smu_register_irq_handler(smu);
1095         if (ret) {
1096                 pr_err("Failed to register smc irq handler!\n");
1097                 return ret;
1098         }
1099
1100         return 0;
1101 }
1102
1103 static int smu_sw_fini(void *handle)
1104 {
1105         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1106         struct smu_context *smu = &adev->smu;
1107         int ret;
1108
1109         ret = smu_smc_table_sw_fini(smu);
1110         if (ret) {
1111                 pr_err("Failed to sw fini smc table!\n");
1112                 return ret;
1113         }
1114
1115         smu_fini_microcode(smu);
1116
1117         return 0;
1118 }
1119
1120 static int smu_smc_hw_setup(struct smu_context *smu)
1121 {
1122         struct amdgpu_device *adev = smu->adev;
1123         int ret;
1124
1125         if (smu_is_dpm_running(smu) && adev->in_suspend) {
1126                 pr_info("dpm has been enabled\n");
1127                 return 0;
1128         }
1129
1130         ret = smu_init_display_count(smu, 0);
1131         if (ret)
1132                 return ret;
1133
1134         ret = smu_set_driver_table_location(smu);
1135         if (ret)
1136                 return ret;
1137
1138         /*
1139          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1140          */
1141         ret = smu_set_tool_table_location(smu);
1142         if (ret)
1143                 return ret;
1144
1145         /*
1146          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1147          * pool location.
1148          */
1149         ret = smu_notify_memory_pool_location(smu);
1150         if (ret)
1151                 return ret;
1152
1153         /* smu_dump_pptable(smu); */
1154         /*
1155          * Copy pptable bo in the vram to smc with SMU MSGs such as
1156          * SetDriverDramAddr and TransferTableDram2Smu.
1157          */
1158         ret = smu_write_pptable(smu);
1159         if (ret)
1160                 return ret;
1161
1162         /* issue Run*Btc msg */
1163         ret = smu_run_btc(smu);
1164         if (ret)
1165                 return ret;
1166
1167         ret = smu_feature_set_allowed_mask(smu);
1168         if (ret)
1169                 return ret;
1170
1171         ret = smu_system_features_control(smu, true);
1172         if (ret)
1173                 return ret;
1174
1175         if (!smu_is_dpm_running(smu))
1176                 pr_info("dpm has been disabled\n");
1177
1178         ret = smu_override_pcie_parameters(smu);
1179         if (ret)
1180                 return ret;
1181
1182         ret = smu_enable_thermal_alert(smu);
1183         if (ret)
1184                 return ret;
1185
1186         ret = smu_i2c_eeprom_init(smu, &adev->pm.smu_i2c);
1187         if (ret)
1188                 return ret;
1189
1190         ret = smu_disable_umc_cdr_12gbps_workaround(smu);
1191         if (ret) {
1192                 pr_err("Workaround failed to disable UMC CDR feature on 12Gbps SKU!\n");
1193                 return ret;
1194         }
1195
1196         /*
1197          * For Navi1X, manually switch it to AC mode as PMFW
1198          * may boot it with DC mode.
1199          */
1200         ret = smu_set_power_source(smu,
1201                                    adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
1202                                    SMU_POWER_SOURCE_DC);
1203         if (ret) {
1204                 pr_err("Failed to switch to %s mode!\n", adev->pm.ac_power ? "AC" : "DC");
1205                 return ret;
1206         }
1207
1208         ret = smu_notify_display_change(smu);
1209         if (ret)
1210                 return ret;
1211
1212         /*
1213          * Set min deep sleep dce fclk with bootup value from vbios via
1214          * SetMinDeepSleepDcefclk MSG.
1215          */
1216         ret = smu_set_min_dcef_deep_sleep(smu);
1217         if (ret)
1218                 return ret;
1219
1220         return ret;
1221 }
1222
1223 static int smu_start_smc_engine(struct smu_context *smu)
1224 {
1225         struct amdgpu_device *adev = smu->adev;
1226         int ret = 0;
1227
1228         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1229                 if (adev->asic_type < CHIP_NAVI10) {
1230                         if (smu->ppt_funcs->load_microcode) {
1231                                 ret = smu->ppt_funcs->load_microcode(smu);
1232                                 if (ret)
1233                                         return ret;
1234                         }
1235                 }
1236         }
1237
1238         if (smu->ppt_funcs->check_fw_status) {
1239                 ret = smu->ppt_funcs->check_fw_status(smu);
1240                 if (ret) {
1241                         pr_err("SMC is not ready\n");
1242                         return ret;
1243                 }
1244         }
1245
1246         /*
1247          * Send msg GetDriverIfVersion to check if the return value is equal
1248          * with DRIVER_IF_VERSION of smc header.
1249          */
1250         ret = smu_check_fw_version(smu);
1251         if (ret)
1252                 return ret;
1253
1254         return ret;
1255 }
1256
1257 static int smu_hw_init(void *handle)
1258 {
1259         int ret;
1260         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1261         struct smu_context *smu = &adev->smu;
1262
1263         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1264                 return 0;
1265
1266         ret = smu_start_smc_engine(smu);
1267         if (ret) {
1268                 pr_err("SMU is not ready yet!\n");
1269                 return ret;
1270         }
1271
1272         if (smu->is_apu) {
1273                 smu_powergate_sdma(&adev->smu, false);
1274                 smu_powergate_vcn(&adev->smu, false);
1275                 smu_powergate_jpeg(&adev->smu, false);
1276                 smu_set_gfx_cgpg(&adev->smu, true);
1277         }
1278
1279         if (!smu->pm_enabled)
1280                 return 0;
1281
1282         /* get boot_values from vbios to set revision, gfxclk, and etc. */
1283         ret = smu_get_vbios_bootup_values(smu);
1284         if (ret)
1285                 return ret;
1286
1287         ret = smu_setup_pptable(smu);
1288         if (ret)
1289                 return ret;
1290
1291         ret = smu_get_driver_allowed_feature_mask(smu);
1292         if (ret)
1293                 goto failed;
1294
1295         ret = smu_smc_hw_setup(smu);
1296         if (ret)
1297                 goto failed;
1298
1299         adev->pm.dpm_enabled = true;
1300
1301         pr_info("SMU is initialized successfully!\n");
1302
1303         return 0;
1304
1305 failed:
1306         return ret;
1307 }
1308
1309 static int smu_disable_dpms(struct smu_context *smu)
1310 {
1311         struct amdgpu_device *adev = smu->adev;
1312         uint64_t features_to_disable;
1313         int ret = 0;
1314         bool use_baco = !smu->is_apu &&
1315                 ((adev->in_gpu_reset &&
1316                   (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1317                  ((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev)));
1318
1319         /*
1320          * For custom pptable uploading, skip the DPM features
1321          * disable process on Navi1x ASICs.
1322          *   - As the gfx related features are under control of
1323          *     RLC on those ASICs. RLC reinitialization will be
1324          *     needed to reenable them. That will cost much more
1325          *     efforts.
1326          *
1327          *   - SMU firmware can handle the DPM reenablement
1328          *     properly.
1329          */
1330         if (smu->uploading_custom_pp_table &&
1331             (adev->asic_type >= CHIP_NAVI10) &&
1332             (adev->asic_type <= CHIP_NAVI12))
1333                 return 0;
1334
1335         /*
1336          * For Sienna_Cichlid, PMFW will handle the features disablement properly
1337          * on BACO in. Driver involvement is unnecessary.
1338          */
1339         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1340              use_baco)
1341                 return 0;
1342
1343         /*
1344          * For gpu reset, runpm and hibernation through BACO,
1345          * BACO feature has to be kept enabled.
1346          */
1347         if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1348                 features_to_disable = U64_MAX &
1349                         ~(1ULL << smu_feature_get_index(smu, SMU_FEATURE_BACO_BIT));
1350                 ret = smu_feature_update_enable_state(smu,
1351                                                       features_to_disable,
1352                                                       0);
1353                 if (ret)
1354                         pr_err("Failed to disable smu features except BACO.\n");
1355         } else {
1356                 ret = smu_system_features_control(smu, false);
1357                 if (ret)
1358                         pr_err("Failed to disable smu features.\n");
1359         }
1360
1361         if (adev->asic_type >= CHIP_NAVI10 &&
1362             adev->gfx.rlc.funcs->stop)
1363                 adev->gfx.rlc.funcs->stop(adev);
1364
1365         return ret;
1366 }
1367
1368 static int smu_smc_hw_cleanup(struct smu_context *smu)
1369 {
1370         struct amdgpu_device *adev = smu->adev;
1371         int ret = 0;
1372
1373         smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);
1374
1375         ret = smu_disable_thermal_alert(smu);
1376         if (ret) {
1377                 pr_warn("Fail to stop thermal control!\n");
1378                 return ret;
1379         }
1380
1381         ret = smu_disable_dpms(smu);
1382         if (ret)
1383                 return ret;
1384
1385         return 0;
1386 }
1387
1388 static int smu_hw_fini(void *handle)
1389 {
1390         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1391         struct smu_context *smu = &adev->smu;
1392         int ret = 0;
1393
1394         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1395                 return 0;
1396
1397         if (smu->is_apu) {
1398                 smu_powergate_sdma(&adev->smu, true);
1399                 smu_powergate_vcn(&adev->smu, true);
1400                 smu_powergate_jpeg(&adev->smu, true);
1401         }
1402
1403         if (!smu->pm_enabled)
1404                 return 0;
1405
1406         adev->pm.dpm_enabled = false;
1407
1408         ret = smu_smc_hw_cleanup(smu);
1409         if (ret)
1410                 return ret;
1411
1412         return 0;
1413 }
1414
1415 int smu_reset(struct smu_context *smu)
1416 {
1417         struct amdgpu_device *adev = smu->adev;
1418         int ret = 0;
1419
1420         ret = smu_hw_fini(adev);
1421         if (ret)
1422                 return ret;
1423
1424         ret = smu_hw_init(adev);
1425         if (ret)
1426                 return ret;
1427
1428         ret = smu_late_init(adev);
1429
1430         return ret;
1431 }
1432
1433 static int smu_suspend(void *handle)
1434 {
1435         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1436         struct smu_context *smu = &adev->smu;
1437         int ret;
1438
1439         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1440                 return 0;
1441
1442         if (!smu->pm_enabled)
1443                 return 0;
1444
1445         adev->pm.dpm_enabled = false;
1446
1447         ret = smu_smc_hw_cleanup(smu);
1448         if (ret)
1449                 return ret;
1450
1451         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1452
1453         if (smu->is_apu)
1454                 smu_set_gfx_cgpg(&adev->smu, false);
1455
1456         return 0;
1457 }
1458
1459 static int smu_resume(void *handle)
1460 {
1461         int ret;
1462         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1463         struct smu_context *smu = &adev->smu;
1464
1465         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1466                 return 0;
1467
1468         if (!smu->pm_enabled)
1469                 return 0;
1470
1471         pr_info("SMU is resuming...\n");
1472
1473         ret = smu_start_smc_engine(smu);
1474         if (ret) {
1475                 pr_err("SMU is not ready yet!\n");
1476                 goto failed;
1477         }
1478
1479         ret = smu_smc_hw_setup(smu);
1480         if (ret)
1481                 goto failed;
1482
1483         if (smu->is_apu)
1484                 smu_set_gfx_cgpg(&adev->smu, true);
1485
1486         smu->disable_uclk_switch = 0;
1487
1488         adev->pm.dpm_enabled = true;
1489
1490         pr_info("SMU is resumed successfully!\n");
1491
1492         return 0;
1493
1494 failed:
1495         return ret;
1496 }
1497
1498 int smu_display_configuration_change(struct smu_context *smu,
1499                                      const struct amd_pp_display_configuration *display_config)
1500 {
1501         int index = 0;
1502         int num_of_active_display = 0;
1503
1504         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1505                 return -EOPNOTSUPP;
1506
1507         if (!display_config)
1508                 return -EINVAL;
1509
1510         mutex_lock(&smu->mutex);
1511
1512         if (smu->ppt_funcs->set_deep_sleep_dcefclk)
1513                 smu->ppt_funcs->set_deep_sleep_dcefclk(smu,
1514                                 display_config->min_dcef_deep_sleep_set_clk / 100);
1515
1516         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1517                 if (display_config->displays[index].controller_id != 0)
1518                         num_of_active_display++;
1519         }
1520
1521         smu_set_active_display_count(smu, num_of_active_display);
1522
1523         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1524                            display_config->cpu_cc6_disable,
1525                            display_config->cpu_pstate_disable,
1526                            display_config->nb_pstate_switch_disable);
1527
1528         mutex_unlock(&smu->mutex);
1529
1530         return 0;
1531 }
1532
1533 static int smu_get_clock_info(struct smu_context *smu,
1534                               struct smu_clock_info *clk_info,
1535                               enum smu_perf_level_designation designation)
1536 {
1537         int ret;
1538         struct smu_performance_level level = {0};
1539
1540         if (!clk_info)
1541                 return -EINVAL;
1542
1543         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1544         if (ret)
1545                 return -EINVAL;
1546
1547         clk_info->min_mem_clk = level.memory_clock;
1548         clk_info->min_eng_clk = level.core_clock;
1549         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1550
1551         ret = smu_get_perf_level(smu, designation, &level);
1552         if (ret)
1553                 return -EINVAL;
1554
1555         clk_info->min_mem_clk = level.memory_clock;
1556         clk_info->min_eng_clk = level.core_clock;
1557         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1558
1559         return 0;
1560 }
1561
1562 int smu_get_current_clocks(struct smu_context *smu,
1563                            struct amd_pp_clock_info *clocks)
1564 {
1565         struct amd_pp_simple_clock_info simple_clocks = {0};
1566         struct smu_clock_info hw_clocks;
1567         int ret = 0;
1568
1569         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1570                 return -EOPNOTSUPP;
1571
1572         mutex_lock(&smu->mutex);
1573
1574         smu_get_dal_power_level(smu, &simple_clocks);
1575
1576         if (smu->support_power_containment)
1577                 ret = smu_get_clock_info(smu, &hw_clocks,
1578                                          PERF_LEVEL_POWER_CONTAINMENT);
1579         else
1580                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1581
1582         if (ret) {
1583                 pr_err("Error in smu_get_clock_info\n");
1584                 goto failed;
1585         }
1586
1587         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1588         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1589         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1590         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1591         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1592         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1593         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1594         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1595
1596         if (simple_clocks.level == 0)
1597                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1598         else
1599                 clocks->max_clocks_state = simple_clocks.level;
1600
1601         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1602                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1603                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1604         }
1605
1606 failed:
1607         mutex_unlock(&smu->mutex);
1608         return ret;
1609 }
1610
1611 static int smu_set_clockgating_state(void *handle,
1612                                      enum amd_clockgating_state state)
1613 {
1614         return 0;
1615 }
1616
1617 static int smu_set_powergating_state(void *handle,
1618                                      enum amd_powergating_state state)
1619 {
1620         return 0;
1621 }
1622
1623 static int smu_enable_umd_pstate(void *handle,
1624                       enum amd_dpm_forced_level *level)
1625 {
1626         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1627                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1628                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1629                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1630
1631         struct smu_context *smu = (struct smu_context*)(handle);
1632         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1633
1634         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1635                 return -EINVAL;
1636
1637         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1638                 /* enter umd pstate, save current level, disable gfx cg*/
1639                 if (*level & profile_mode_mask) {
1640                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1641                         smu_dpm_ctx->enable_umd_pstate = true;
1642                         amdgpu_device_ip_set_powergating_state(smu->adev,
1643                                                                AMD_IP_BLOCK_TYPE_GFX,
1644                                                                AMD_PG_STATE_UNGATE);
1645                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1646                                                                AMD_IP_BLOCK_TYPE_GFX,
1647                                                                AMD_CG_STATE_UNGATE);
1648                 }
1649         } else {
1650                 /* exit umd pstate, restore level, enable gfx cg*/
1651                 if (!(*level & profile_mode_mask)) {
1652                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1653                                 *level = smu_dpm_ctx->saved_dpm_level;
1654                         smu_dpm_ctx->enable_umd_pstate = false;
1655                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1656                                                                AMD_IP_BLOCK_TYPE_GFX,
1657                                                                AMD_CG_STATE_GATE);
1658                         amdgpu_device_ip_set_powergating_state(smu->adev,
1659                                                                AMD_IP_BLOCK_TYPE_GFX,
1660                                                                AMD_PG_STATE_GATE);
1661                 }
1662         }
1663
1664         return 0;
1665 }
1666
1667 int smu_adjust_power_state_dynamic(struct smu_context *smu,
1668                                    enum amd_dpm_forced_level level,
1669                                    bool skip_display_settings)
1670 {
1671         int ret = 0;
1672         int index = 0;
1673         long workload;
1674         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1675
1676         if (!skip_display_settings) {
1677                 ret = smu_display_config_changed(smu);
1678                 if (ret) {
1679                         pr_err("Failed to change display config!");
1680                         return ret;
1681                 }
1682         }
1683
1684         ret = smu_apply_clocks_adjust_rules(smu);
1685         if (ret) {
1686                 pr_err("Failed to apply clocks adjust rules!");
1687                 return ret;
1688         }
1689
1690         if (!skip_display_settings) {
1691                 ret = smu_notify_smc_display_config(smu);
1692                 if (ret) {
1693                         pr_err("Failed to notify smc display config!");
1694                         return ret;
1695                 }
1696         }
1697
1698         if (smu_dpm_ctx->dpm_level != level) {
1699                 ret = smu_asic_set_performance_level(smu, level);
1700                 if (ret) {
1701                         pr_err("Failed to set performance level!");
1702                         return ret;
1703                 }
1704
1705                 /* update the saved copy */
1706                 smu_dpm_ctx->dpm_level = level;
1707         }
1708
1709         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1710                 index = fls(smu->workload_mask);
1711                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1712                 workload = smu->workload_setting[index];
1713
1714                 if (smu->power_profile_mode != workload)
1715                         smu_set_power_profile_mode(smu, &workload, 0, false);
1716         }
1717
1718         return ret;
1719 }
1720
1721 int smu_handle_task(struct smu_context *smu,
1722                     enum amd_dpm_forced_level level,
1723                     enum amd_pp_task task_id,
1724                     bool lock_needed)
1725 {
1726         int ret = 0;
1727
1728         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1729                 return -EOPNOTSUPP;
1730
1731         if (lock_needed)
1732                 mutex_lock(&smu->mutex);
1733
1734         switch (task_id) {
1735         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1736                 ret = smu_pre_display_config_changed(smu);
1737                 if (ret)
1738                         goto out;
1739                 ret = smu_set_cpu_power_state(smu);
1740                 if (ret)
1741                         goto out;
1742                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1743                 break;
1744         case AMD_PP_TASK_COMPLETE_INIT:
1745         case AMD_PP_TASK_READJUST_POWER_STATE:
1746                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1747                 break;
1748         default:
1749                 break;
1750         }
1751
1752 out:
1753         if (lock_needed)
1754                 mutex_unlock(&smu->mutex);
1755
1756         return ret;
1757 }
1758
1759 int smu_switch_power_profile(struct smu_context *smu,
1760                              enum PP_SMC_POWER_PROFILE type,
1761                              bool en)
1762 {
1763         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1764         long workload;
1765         uint32_t index;
1766
1767         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1768                 return -EOPNOTSUPP;
1769
1770         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1771                 return -EINVAL;
1772
1773         mutex_lock(&smu->mutex);
1774
1775         if (!en) {
1776                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1777                 index = fls(smu->workload_mask);
1778                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1779                 workload = smu->workload_setting[index];
1780         } else {
1781                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1782                 index = fls(smu->workload_mask);
1783                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1784                 workload = smu->workload_setting[index];
1785         }
1786
1787         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1788                 smu_set_power_profile_mode(smu, &workload, 0, false);
1789
1790         mutex_unlock(&smu->mutex);
1791
1792         return 0;
1793 }
1794
1795 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1796 {
1797         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1798         enum amd_dpm_forced_level level;
1799
1800         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1801                 return -EOPNOTSUPP;
1802
1803         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1804                 return -EINVAL;
1805
1806         mutex_lock(&(smu->mutex));
1807         level = smu_dpm_ctx->dpm_level;
1808         mutex_unlock(&(smu->mutex));
1809
1810         return level;
1811 }
1812
1813 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1814 {
1815         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1816         int ret = 0;
1817
1818         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1819                 return -EOPNOTSUPP;
1820
1821         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1822                 return -EINVAL;
1823
1824         mutex_lock(&smu->mutex);
1825
1826         ret = smu_enable_umd_pstate(smu, &level);
1827         if (ret) {
1828                 mutex_unlock(&smu->mutex);
1829                 return ret;
1830         }
1831
1832         ret = smu_handle_task(smu, level,
1833                               AMD_PP_TASK_READJUST_POWER_STATE,
1834                               false);
1835
1836         mutex_unlock(&smu->mutex);
1837
1838         return ret;
1839 }
1840
1841 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1842 {
1843         int ret = 0;
1844
1845         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1846                 return -EOPNOTSUPP;
1847
1848         mutex_lock(&smu->mutex);
1849         ret = smu_init_display_count(smu, count);
1850         mutex_unlock(&smu->mutex);
1851
1852         return ret;
1853 }
1854
1855 int smu_force_clk_levels(struct smu_context *smu,
1856                          enum smu_clk_type clk_type,
1857                          uint32_t mask,
1858                          bool lock_needed)
1859 {
1860         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1861         int ret = 0;
1862
1863         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1864                 return -EOPNOTSUPP;
1865
1866         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1867                 pr_debug("force clock level is for dpm manual mode only.\n");
1868                 return -EINVAL;
1869         }
1870
1871         if (lock_needed)
1872                 mutex_lock(&smu->mutex);
1873
1874         if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
1875                 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1876
1877         if (lock_needed)
1878                 mutex_unlock(&smu->mutex);
1879
1880         return ret;
1881 }
1882
1883 /*
1884  * On system suspending or resetting, the dpm_enabled
1885  * flag will be cleared. So that those SMU services which
1886  * are not supported will be gated.
1887  * However, the mp1 state setting should still be granted
1888  * even if the dpm_enabled cleared.
1889  */
1890 int smu_set_mp1_state(struct smu_context *smu,
1891                       enum pp_mp1_state mp1_state)
1892 {
1893         uint16_t msg;
1894         int ret;
1895
1896         if (!smu->pm_enabled)
1897                 return -EOPNOTSUPP;
1898
1899         mutex_lock(&smu->mutex);
1900
1901         switch (mp1_state) {
1902         case PP_MP1_STATE_SHUTDOWN:
1903                 msg = SMU_MSG_PrepareMp1ForShutdown;
1904                 break;
1905         case PP_MP1_STATE_UNLOAD:
1906                 msg = SMU_MSG_PrepareMp1ForUnload;
1907                 break;
1908         case PP_MP1_STATE_RESET:
1909                 msg = SMU_MSG_PrepareMp1ForReset;
1910                 break;
1911         case PP_MP1_STATE_NONE:
1912         default:
1913                 mutex_unlock(&smu->mutex);
1914                 return 0;
1915         }
1916
1917         /* some asics may not support those messages */
1918         if (smu_msg_get_index(smu, msg) < 0) {
1919                 mutex_unlock(&smu->mutex);
1920                 return 0;
1921         }
1922
1923         ret = smu_send_smc_msg(smu, msg, NULL);
1924         if (ret)
1925                 pr_err("[PrepareMp1] Failed!\n");
1926
1927         mutex_unlock(&smu->mutex);
1928
1929         return ret;
1930 }
1931
1932 int smu_set_df_cstate(struct smu_context *smu,
1933                       enum pp_df_cstate state)
1934 {
1935         int ret = 0;
1936
1937         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1938                 return -EOPNOTSUPP;
1939
1940         if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1941                 return 0;
1942
1943         mutex_lock(&smu->mutex);
1944
1945         ret = smu->ppt_funcs->set_df_cstate(smu, state);
1946         if (ret)
1947                 pr_err("[SetDfCstate] failed!\n");
1948
1949         mutex_unlock(&smu->mutex);
1950
1951         return ret;
1952 }
1953
1954 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
1955 {
1956         int ret = 0;
1957
1958         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1959                 return -EOPNOTSUPP;
1960
1961         if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
1962                 return 0;
1963
1964         mutex_lock(&smu->mutex);
1965
1966         ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
1967         if (ret)
1968                 pr_err("[AllowXgmiPowerDown] failed!\n");
1969
1970         mutex_unlock(&smu->mutex);
1971
1972         return ret;
1973 }
1974
1975 int smu_write_watermarks_table(struct smu_context *smu)
1976 {
1977         void *watermarks_table = smu->smu_table.watermarks_table;
1978
1979         if (!watermarks_table)
1980                 return -EINVAL;
1981
1982         return smu_update_table(smu,
1983                                 SMU_TABLE_WATERMARKS,
1984                                 0,
1985                                 watermarks_table,
1986                                 true);
1987 }
1988
1989 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
1990                 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
1991 {
1992         void *table = smu->smu_table.watermarks_table;
1993
1994         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1995                 return -EOPNOTSUPP;
1996
1997         if (!table)
1998                 return -EINVAL;
1999
2000         mutex_lock(&smu->mutex);
2001
2002         if (!smu->disable_watermark &&
2003                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
2004                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
2005                 smu_set_watermarks_table(smu, table, clock_ranges);
2006
2007                 if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
2008                         smu->watermarks_bitmap |= WATERMARKS_EXIST;
2009                         smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
2010                 }
2011         }
2012
2013         mutex_unlock(&smu->mutex);
2014
2015         return 0;
2016 }
2017
2018 int smu_set_ac_dc(struct smu_context *smu)
2019 {
2020         int ret = 0;
2021
2022         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2023                 return -EOPNOTSUPP;
2024
2025         /* controlled by firmware */
2026         if (smu->dc_controlled_by_gpio)
2027                 return 0;
2028
2029         mutex_lock(&smu->mutex);
2030         ret = smu_set_power_source(smu,
2031                                    smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
2032                                    SMU_POWER_SOURCE_DC);
2033         if (ret)
2034                 pr_err("Failed to switch to %s mode!\n",
2035                        smu->adev->pm.ac_power ? "AC" : "DC");
2036         mutex_unlock(&smu->mutex);
2037
2038         return ret;
2039 }
2040
2041 const struct amd_ip_funcs smu_ip_funcs = {
2042         .name = "smu",
2043         .early_init = smu_early_init,
2044         .late_init = smu_late_init,
2045         .sw_init = smu_sw_init,
2046         .sw_fini = smu_sw_fini,
2047         .hw_init = smu_hw_init,
2048         .hw_fini = smu_hw_fini,
2049         .suspend = smu_suspend,
2050         .resume = smu_resume,
2051         .is_idle = NULL,
2052         .check_soft_reset = NULL,
2053         .wait_for_idle = NULL,
2054         .soft_reset = NULL,
2055         .set_clockgating_state = smu_set_clockgating_state,
2056         .set_powergating_state = smu_set_powergating_state,
2057         .enable_umd_pstate = smu_enable_umd_pstate,
2058 };
2059
2060 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
2061 {
2062         .type = AMD_IP_BLOCK_TYPE_SMC,
2063         .major = 11,
2064         .minor = 0,
2065         .rev = 0,
2066         .funcs = &smu_ip_funcs,
2067 };
2068
2069 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
2070 {
2071         .type = AMD_IP_BLOCK_TYPE_SMC,
2072         .major = 12,
2073         .minor = 0,
2074         .rev = 0,
2075         .funcs = &smu_ip_funcs,
2076 };
2077
2078 int smu_load_microcode(struct smu_context *smu)
2079 {
2080         int ret = 0;
2081
2082         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2083                 return -EOPNOTSUPP;
2084
2085         mutex_lock(&smu->mutex);
2086
2087         if (smu->ppt_funcs->load_microcode)
2088                 ret = smu->ppt_funcs->load_microcode(smu);
2089
2090         mutex_unlock(&smu->mutex);
2091
2092         return ret;
2093 }
2094
2095 int smu_check_fw_status(struct smu_context *smu)
2096 {
2097         int ret = 0;
2098
2099         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2100                 return -EOPNOTSUPP;
2101
2102         mutex_lock(&smu->mutex);
2103
2104         if (smu->ppt_funcs->check_fw_status)
2105                 ret = smu->ppt_funcs->check_fw_status(smu);
2106
2107         mutex_unlock(&smu->mutex);
2108
2109         return ret;
2110 }
2111
2112 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2113 {
2114         int ret = 0;
2115
2116         mutex_lock(&smu->mutex);
2117
2118         if (smu->ppt_funcs->set_gfx_cgpg)
2119                 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2120
2121         mutex_unlock(&smu->mutex);
2122
2123         return ret;
2124 }
2125
2126 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
2127 {
2128         int ret = 0;
2129
2130         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2131                 return -EOPNOTSUPP;
2132
2133         mutex_lock(&smu->mutex);
2134
2135         if (smu->ppt_funcs->set_fan_speed_rpm)
2136                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2137
2138         mutex_unlock(&smu->mutex);
2139
2140         return ret;
2141 }
2142
2143 int smu_get_power_limit(struct smu_context *smu,
2144                         uint32_t *limit,
2145                         bool def,
2146                         bool lock_needed)
2147 {
2148         int ret = 0;
2149
2150         if (lock_needed) {
2151                 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2152                         return -EOPNOTSUPP;
2153
2154                 mutex_lock(&smu->mutex);
2155         }
2156
2157         if (smu->ppt_funcs->get_power_limit)
2158                 ret = smu->ppt_funcs->get_power_limit(smu, limit, def);
2159
2160         if (lock_needed)
2161                 mutex_unlock(&smu->mutex);
2162
2163         return ret;
2164 }
2165
2166 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
2167 {
2168         int ret = 0;
2169
2170         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2171                 return -EOPNOTSUPP;
2172
2173         mutex_lock(&smu->mutex);
2174
2175         if (smu->ppt_funcs->set_power_limit)
2176                 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2177
2178         mutex_unlock(&smu->mutex);
2179
2180         return ret;
2181 }
2182
2183 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2184 {
2185         int ret = 0;
2186
2187         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2188                 return -EOPNOTSUPP;
2189
2190         mutex_lock(&smu->mutex);
2191
2192         if (smu->ppt_funcs->print_clk_levels)
2193                 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2194
2195         mutex_unlock(&smu->mutex);
2196
2197         return ret;
2198 }
2199
2200 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
2201 {
2202         int ret = 0;
2203
2204         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2205                 return -EOPNOTSUPP;
2206
2207         mutex_lock(&smu->mutex);
2208
2209         if (smu->ppt_funcs->get_od_percentage)
2210                 ret = smu->ppt_funcs->get_od_percentage(smu, type);
2211
2212         mutex_unlock(&smu->mutex);
2213
2214         return ret;
2215 }
2216
2217 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
2218 {
2219         int ret = 0;
2220
2221         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2222                 return -EOPNOTSUPP;
2223
2224         mutex_lock(&smu->mutex);
2225
2226         if (smu->ppt_funcs->set_od_percentage)
2227                 ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
2228
2229         mutex_unlock(&smu->mutex);
2230
2231         return ret;
2232 }
2233
2234 int smu_od_edit_dpm_table(struct smu_context *smu,
2235                           enum PP_OD_DPM_TABLE_COMMAND type,
2236                           long *input, uint32_t size)
2237 {
2238         int ret = 0;
2239
2240         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2241                 return -EOPNOTSUPP;
2242
2243         mutex_lock(&smu->mutex);
2244
2245         if (smu->ppt_funcs->od_edit_dpm_table)
2246                 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2247
2248         mutex_unlock(&smu->mutex);
2249
2250         return ret;
2251 }
2252
2253 int smu_read_sensor(struct smu_context *smu,
2254                     enum amd_pp_sensors sensor,
2255                     void *data, uint32_t *size)
2256 {
2257         int ret = 0;
2258
2259         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2260                 return -EOPNOTSUPP;
2261
2262         mutex_lock(&smu->mutex);
2263
2264         if (smu->ppt_funcs->read_sensor)
2265                 ret = smu->ppt_funcs->read_sensor(smu, sensor, data, size);
2266
2267         mutex_unlock(&smu->mutex);
2268
2269         return ret;
2270 }
2271
2272 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2273 {
2274         int ret = 0;
2275
2276         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2277                 return -EOPNOTSUPP;
2278
2279         mutex_lock(&smu->mutex);
2280
2281         if (smu->ppt_funcs->get_power_profile_mode)
2282                 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2283
2284         mutex_unlock(&smu->mutex);
2285
2286         return ret;
2287 }
2288
2289 int smu_set_power_profile_mode(struct smu_context *smu,
2290                                long *param,
2291                                uint32_t param_size,
2292                                bool lock_needed)
2293 {
2294         int ret = 0;
2295
2296         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2297                 return -EOPNOTSUPP;
2298
2299         if (lock_needed)
2300                 mutex_lock(&smu->mutex);
2301
2302         if (smu->ppt_funcs->set_power_profile_mode)
2303                 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2304
2305         if (lock_needed)
2306                 mutex_unlock(&smu->mutex);
2307
2308         return ret;
2309 }
2310
2311
2312 int smu_get_fan_control_mode(struct smu_context *smu)
2313 {
2314         int ret = 0;
2315
2316         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2317                 return -EOPNOTSUPP;
2318
2319         mutex_lock(&smu->mutex);
2320
2321         if (smu->ppt_funcs->get_fan_control_mode)
2322                 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2323
2324         mutex_unlock(&smu->mutex);
2325
2326         return ret;
2327 }
2328
2329 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2330 {
2331         int ret = 0;
2332
2333         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2334                 return -EOPNOTSUPP;
2335
2336         mutex_lock(&smu->mutex);
2337
2338         if (smu->ppt_funcs->set_fan_control_mode)
2339                 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2340
2341         mutex_unlock(&smu->mutex);
2342
2343         return ret;
2344 }
2345
2346 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2347 {
2348         int ret = 0;
2349
2350         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2351                 return -EOPNOTSUPP;
2352
2353         mutex_lock(&smu->mutex);
2354
2355         if (smu->ppt_funcs->get_fan_speed_percent)
2356                 ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
2357
2358         mutex_unlock(&smu->mutex);
2359
2360         return ret;
2361 }
2362
2363 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2364 {
2365         int ret = 0;
2366
2367         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2368                 return -EOPNOTSUPP;
2369
2370         mutex_lock(&smu->mutex);
2371
2372         if (smu->ppt_funcs->set_fan_speed_percent)
2373                 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
2374
2375         mutex_unlock(&smu->mutex);
2376
2377         return ret;
2378 }
2379
2380 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2381 {
2382         int ret = 0;
2383
2384         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2385                 return -EOPNOTSUPP;
2386
2387         mutex_lock(&smu->mutex);
2388
2389         if (smu->ppt_funcs->get_fan_speed_rpm)
2390                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2391
2392         mutex_unlock(&smu->mutex);
2393
2394         return ret;
2395 }
2396
2397 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2398 {
2399         int ret = 0;
2400
2401         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2402                 return -EOPNOTSUPP;
2403
2404         mutex_lock(&smu->mutex);
2405
2406         if (smu->ppt_funcs->set_deep_sleep_dcefclk)
2407                 ret = smu->ppt_funcs->set_deep_sleep_dcefclk(smu, clk);
2408
2409         mutex_unlock(&smu->mutex);
2410
2411         return ret;
2412 }
2413
2414 int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
2415 {
2416         int ret = 0;
2417
2418         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2419                 return -EOPNOTSUPP;
2420
2421         if (smu->ppt_funcs->set_active_display_count)
2422                 ret = smu->ppt_funcs->set_active_display_count(smu, count);
2423
2424         return ret;
2425 }
2426
2427 int smu_get_clock_by_type(struct smu_context *smu,
2428                           enum amd_pp_clock_type type,
2429                           struct amd_pp_clocks *clocks)
2430 {
2431         int ret = 0;
2432
2433         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2434                 return -EOPNOTSUPP;
2435
2436         mutex_lock(&smu->mutex);
2437
2438         if (smu->ppt_funcs->get_clock_by_type)
2439                 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
2440
2441         mutex_unlock(&smu->mutex);
2442
2443         return ret;
2444 }
2445
2446 int smu_get_max_high_clocks(struct smu_context *smu,
2447                             struct amd_pp_simple_clock_info *clocks)
2448 {
2449         int ret = 0;
2450
2451         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2452                 return -EOPNOTSUPP;
2453
2454         mutex_lock(&smu->mutex);
2455
2456         if (smu->ppt_funcs->get_max_high_clocks)
2457                 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
2458
2459         mutex_unlock(&smu->mutex);
2460
2461         return ret;
2462 }
2463
2464 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2465                                        enum smu_clk_type clk_type,
2466                                        struct pp_clock_levels_with_latency *clocks)
2467 {
2468         int ret = 0;
2469
2470         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2471                 return -EOPNOTSUPP;
2472
2473         mutex_lock(&smu->mutex);
2474
2475         if (smu->ppt_funcs->get_clock_by_type_with_latency)
2476                 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2477
2478         mutex_unlock(&smu->mutex);
2479
2480         return ret;
2481 }
2482
2483 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
2484                                        enum amd_pp_clock_type type,
2485                                        struct pp_clock_levels_with_voltage *clocks)
2486 {
2487         int ret = 0;
2488
2489         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2490                 return -EOPNOTSUPP;
2491
2492         mutex_lock(&smu->mutex);
2493
2494         if (smu->ppt_funcs->get_clock_by_type_with_voltage)
2495                 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
2496
2497         mutex_unlock(&smu->mutex);
2498
2499         return ret;
2500 }
2501
2502
2503 int smu_display_clock_voltage_request(struct smu_context *smu,
2504                                       struct pp_display_clock_request *clock_req)
2505 {
2506         int ret = 0;
2507
2508         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2509                 return -EOPNOTSUPP;
2510
2511         mutex_lock(&smu->mutex);
2512
2513         if (smu->ppt_funcs->display_clock_voltage_request)
2514                 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2515
2516         mutex_unlock(&smu->mutex);
2517
2518         return ret;
2519 }
2520
2521
2522 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2523 {
2524         int ret = -EINVAL;
2525
2526         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2527                 return -EOPNOTSUPP;
2528
2529         mutex_lock(&smu->mutex);
2530
2531         if (smu->ppt_funcs->display_disable_memory_clock_switch)
2532                 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2533
2534         mutex_unlock(&smu->mutex);
2535
2536         return ret;
2537 }
2538
2539 int smu_notify_smu_enable_pwe(struct smu_context *smu)
2540 {
2541         int ret = 0;
2542
2543         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2544                 return -EOPNOTSUPP;
2545
2546         mutex_lock(&smu->mutex);
2547
2548         if (smu->ppt_funcs->notify_smu_enable_pwe)
2549                 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
2550
2551         mutex_unlock(&smu->mutex);
2552
2553         return ret;
2554 }
2555
2556 int smu_set_xgmi_pstate(struct smu_context *smu,
2557                         uint32_t pstate)
2558 {
2559         int ret = 0;
2560
2561         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2562                 return -EOPNOTSUPP;
2563
2564         mutex_lock(&smu->mutex);
2565
2566         if (smu->ppt_funcs->set_xgmi_pstate)
2567                 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2568
2569         mutex_unlock(&smu->mutex);
2570
2571         return ret;
2572 }
2573
2574 int smu_set_azalia_d3_pme(struct smu_context *smu)
2575 {
2576         int ret = 0;
2577
2578         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2579                 return -EOPNOTSUPP;
2580
2581         mutex_lock(&smu->mutex);
2582
2583         if (smu->ppt_funcs->set_azalia_d3_pme)
2584                 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2585
2586         mutex_unlock(&smu->mutex);
2587
2588         return ret;
2589 }
2590
2591 /*
2592  * On system suspending or resetting, the dpm_enabled
2593  * flag will be cleared. So that those SMU services which
2594  * are not supported will be gated.
2595  *
2596  * However, the baco/mode1 reset should still be granted
2597  * as they are still supported and necessary.
2598  */
2599 bool smu_baco_is_support(struct smu_context *smu)
2600 {
2601         bool ret = false;
2602
2603         if (!smu->pm_enabled)
2604                 return false;
2605
2606         mutex_lock(&smu->mutex);
2607
2608         if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2609                 ret = smu->ppt_funcs->baco_is_support(smu);
2610
2611         mutex_unlock(&smu->mutex);
2612
2613         return ret;
2614 }
2615
2616 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2617 {
2618         if (smu->ppt_funcs->baco_get_state)
2619                 return -EINVAL;
2620
2621         mutex_lock(&smu->mutex);
2622         *state = smu->ppt_funcs->baco_get_state(smu);
2623         mutex_unlock(&smu->mutex);
2624
2625         return 0;
2626 }
2627
2628 int smu_baco_enter(struct smu_context *smu)
2629 {
2630         int ret = 0;
2631
2632         if (!smu->pm_enabled)
2633                 return -EOPNOTSUPP;
2634
2635         mutex_lock(&smu->mutex);
2636
2637         if (smu->ppt_funcs->baco_enter)
2638                 ret = smu->ppt_funcs->baco_enter(smu);
2639
2640         mutex_unlock(&smu->mutex);
2641
2642         return ret;
2643 }
2644
2645 int smu_baco_exit(struct smu_context *smu)
2646 {
2647         int ret = 0;
2648
2649         if (!smu->pm_enabled)
2650                 return -EOPNOTSUPP;
2651
2652         mutex_lock(&smu->mutex);
2653
2654         if (smu->ppt_funcs->baco_exit)
2655                 ret = smu->ppt_funcs->baco_exit(smu);
2656
2657         mutex_unlock(&smu->mutex);
2658
2659         return ret;
2660 }
2661
2662 int smu_mode2_reset(struct smu_context *smu)
2663 {
2664         int ret = 0;
2665
2666         if (!smu->pm_enabled)
2667                 return -EOPNOTSUPP;
2668
2669         mutex_lock(&smu->mutex);
2670
2671         if (smu->ppt_funcs->mode2_reset)
2672                 ret = smu->ppt_funcs->mode2_reset(smu);
2673
2674         mutex_unlock(&smu->mutex);
2675
2676         return ret;
2677 }
2678
2679 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2680                                          struct pp_smu_nv_clock_table *max_clocks)
2681 {
2682         int ret = 0;
2683
2684         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2685                 return -EOPNOTSUPP;
2686
2687         mutex_lock(&smu->mutex);
2688
2689         if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2690                 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2691
2692         mutex_unlock(&smu->mutex);
2693
2694         return ret;
2695 }
2696
2697 int smu_get_uclk_dpm_states(struct smu_context *smu,
2698                             unsigned int *clock_values_in_khz,
2699                             unsigned int *num_states)
2700 {
2701         int ret = 0;
2702
2703         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2704                 return -EOPNOTSUPP;
2705
2706         mutex_lock(&smu->mutex);
2707
2708         if (smu->ppt_funcs->get_uclk_dpm_states)
2709                 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2710
2711         mutex_unlock(&smu->mutex);
2712
2713         return ret;
2714 }
2715
2716 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2717 {
2718         enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2719
2720         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2721                 return -EOPNOTSUPP;
2722
2723         mutex_lock(&smu->mutex);
2724
2725         if (smu->ppt_funcs->get_current_power_state)
2726                 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2727
2728         mutex_unlock(&smu->mutex);
2729
2730         return pm_state;
2731 }
2732
2733 int smu_get_dpm_clock_table(struct smu_context *smu,
2734                             struct dpm_clocks *clock_table)
2735 {
2736         int ret = 0;
2737
2738         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2739                 return -EOPNOTSUPP;
2740
2741         mutex_lock(&smu->mutex);
2742
2743         if (smu->ppt_funcs->get_dpm_clock_table)
2744                 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2745
2746         mutex_unlock(&smu->mutex);
2747
2748         return ret;
2749 }
2750
2751 uint32_t smu_get_pptable_power_limit(struct smu_context *smu)
2752 {
2753         uint32_t ret = 0;
2754
2755         if (smu->ppt_funcs->get_pptable_power_limit)
2756                 ret = smu->ppt_funcs->get_pptable_power_limit(smu);
2757
2758         return ret;
2759 }
2760
2761 int smu_powergate_vcn(struct smu_context *smu, bool gate)
2762 {
2763         if (!smu->is_apu)
2764                 return 0;
2765
2766         return smu_dpm_set_uvd_enable(smu, !gate);
2767 }
2768
2769 int smu_powergate_jpeg(struct smu_context *smu, bool gate)
2770 {
2771         if (!smu->is_apu)
2772                 return 0;
2773
2774         return smu_dpm_set_jpeg_enable(smu, !gate);
2775 }