2 * Copyright 2023 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
28 #define SWSMU_CODE_LAYER_L3
31 #include "amdgpu_smu.h"
32 #include "atomfirmware.h"
33 #include "amdgpu_atomfirmware.h"
34 #include "amdgpu_atombios.h"
35 #include "smu_v14_0.h"
36 #include "soc15_common.h"
38 #include "amdgpu_ras.h"
41 #include "asic_reg/mp/mp_14_0_0_offset.h"
42 #include "asic_reg/mp/mp_14_0_0_sh_mask.h"
45 * DO NOT use these for err/warn/info/debug messages.
46 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
47 * They are more MGPU friendly.
54 MODULE_FIRMWARE("amdgpu/smu_14_0_2.bin");
56 int smu_v14_0_init_microcode(struct smu_context *smu)
58 struct amdgpu_device *adev = smu->adev;
60 char ucode_prefix[15];
62 const struct smc_firmware_header_v1_0 *hdr;
63 const struct common_firmware_header *header;
64 struct amdgpu_firmware_info *ucode = NULL;
66 /* doesn't need to load smu firmware in IOV mode */
67 if (amdgpu_sriov_vf(adev))
70 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
72 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);
74 err = amdgpu_ucode_request(adev, &adev->pm.fw, fw_name);
78 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
79 amdgpu_ucode_print_smc_hdr(&hdr->header);
80 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
82 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
83 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
84 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
85 ucode->fw = adev->pm.fw;
86 header = (const struct common_firmware_header *)ucode->fw->data;
87 adev->firmware.fw_size +=
88 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
93 amdgpu_ucode_release(&adev->pm.fw);
97 void smu_v14_0_fini_microcode(struct smu_context *smu)
99 struct amdgpu_device *adev = smu->adev;
101 amdgpu_ucode_release(&adev->pm.fw);
102 adev->pm.fw_version = 0;
105 int smu_v14_0_load_microcode(struct smu_context *smu)
108 struct amdgpu_device *adev = smu->adev;
110 const struct smc_firmware_header_v1_0 *hdr;
111 uint32_t addr_start = MP1_SRAM;
113 uint32_t smc_fw_size;
114 uint32_t mp1_fw_flags;
116 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
117 src = (const uint32_t *)(adev->pm.fw->data +
118 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
119 smc_fw_size = hdr->header.ucode_size_bytes;
121 for (i = 1; i < smc_fw_size/4 - 1; i++) {
122 WREG32_PCIE(addr_start, src[i]);
126 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
127 1 & MP1_SMN_PUB_CTRL__LX3_RESET_MASK);
128 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
129 1 & ~MP1_SMN_PUB_CTRL__LX3_RESET_MASK);
131 for (i = 0; i < adev->usec_timeout; i++) {
132 mp1_fw_flags = RREG32_PCIE(MP1_Public |
133 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
134 if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
135 MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
140 if (i == adev->usec_timeout)
148 int smu_v14_0_init_pptable_microcode(struct smu_context *smu)
150 struct amdgpu_device *adev = smu->adev;
151 struct amdgpu_firmware_info *ucode = NULL;
152 uint32_t size = 0, pptable_id = 0;
156 /* doesn't need to load smu firmware in IOV mode */
157 if (amdgpu_sriov_vf(adev))
160 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
163 if (!adev->scpm_enabled)
166 /* override pptable_id from driver parameter */
167 if (amdgpu_smu_pptable_id >= 0) {
168 pptable_id = amdgpu_smu_pptable_id;
169 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
171 pptable_id = smu->smu_table.boot_values.pp_table_id;
174 /* "pptable_id == 0" means vbios carries the pptable. */
178 ret = smu_v14_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
182 smu->pptable_firmware.data = table;
183 smu->pptable_firmware.size = size;
185 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
186 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
187 ucode->fw = &smu->pptable_firmware;
188 adev->firmware.fw_size +=
189 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
194 int smu_v14_0_check_fw_status(struct smu_context *smu)
196 struct amdgpu_device *adev = smu->adev;
197 uint32_t mp1_fw_flags;
199 mp1_fw_flags = RREG32_PCIE(MP1_Public |
200 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
202 if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
203 MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
209 int smu_v14_0_check_fw_version(struct smu_context *smu)
211 struct amdgpu_device *adev = smu->adev;
212 uint32_t if_version = 0xff, smu_version = 0xff;
213 uint8_t smu_program, smu_major, smu_minor, smu_debug;
216 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
220 smu_program = (smu_version >> 24) & 0xff;
221 smu_major = (smu_version >> 16) & 0xff;
222 smu_minor = (smu_version >> 8) & 0xff;
223 smu_debug = (smu_version >> 0) & 0xff;
225 adev->pm.fw_version = smu_version;
227 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
228 case IP_VERSION(14, 0, 2):
229 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_2;
231 case IP_VERSION(14, 0, 0):
232 if ((smu->smc_fw_version < 0x5d3a00))
233 dev_warn(smu->adev->dev, "The PMFW version(%x) is behind in this BIOS!\n", smu->smc_fw_version);
234 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_0;
237 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
238 amdgpu_ip_version(adev, MP1_HWIP, 0));
239 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_INV;
244 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
245 smu_program, smu_version, smu_major, smu_minor, smu_debug);
248 * 1. if_version mismatch is not critical as our fw is designed
249 * to be backward compatible.
250 * 2. New fw usually brings some optimizations. But that's visible
251 * only on the paired driver.
252 * Considering above, we just leave user a verbal message instead
253 * of halt driver loading.
255 if (if_version != smu->smc_driver_if_version) {
256 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
257 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
258 smu->smc_driver_if_version, if_version,
259 smu_program, smu_version, smu_major, smu_minor, smu_debug);
260 dev_info(adev->dev, "SMU driver if version not matched\n");
266 static int smu_v14_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
268 struct amdgpu_device *adev = smu->adev;
269 uint32_t ppt_offset_bytes;
270 const struct smc_firmware_header_v2_0 *v2;
272 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
274 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
275 *size = le32_to_cpu(v2->ppt_size_bytes);
276 *table = (uint8_t *)v2 + ppt_offset_bytes;
281 static int smu_v14_0_set_pptable_v2_1(struct smu_context *smu, void **table,
282 uint32_t *size, uint32_t pptable_id)
284 struct amdgpu_device *adev = smu->adev;
285 const struct smc_firmware_header_v2_1 *v2_1;
286 struct smc_soft_pptable_entry *entries;
287 uint32_t pptable_count = 0;
290 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
291 entries = (struct smc_soft_pptable_entry *)
292 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
293 pptable_count = le32_to_cpu(v2_1->pptable_count);
294 for (i = 0; i < pptable_count; i++) {
295 if (le32_to_cpu(entries[i].id) == pptable_id) {
296 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
297 *size = le32_to_cpu(entries[i].ppt_size_bytes);
302 if (i == pptable_count)
308 static int smu_v14_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
310 struct amdgpu_device *adev = smu->adev;
311 uint16_t atom_table_size;
315 dev_info(adev->dev, "use vbios provided pptable\n");
316 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
319 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
325 *size = atom_table_size;
330 int smu_v14_0_get_pptable_from_firmware(struct smu_context *smu,
335 const struct smc_firmware_header_v1_0 *hdr;
336 struct amdgpu_device *adev = smu->adev;
337 uint16_t version_major, version_minor;
340 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
344 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
346 version_major = le16_to_cpu(hdr->header.header_version_major);
347 version_minor = le16_to_cpu(hdr->header.header_version_minor);
348 if (version_major != 2) {
349 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
350 version_major, version_minor);
354 switch (version_minor) {
356 ret = smu_v14_0_set_pptable_v2_0(smu, table, size);
359 ret = smu_v14_0_set_pptable_v2_1(smu, table, size, pptable_id);
369 int smu_v14_0_setup_pptable(struct smu_context *smu)
371 struct amdgpu_device *adev = smu->adev;
372 uint32_t size = 0, pptable_id = 0;
376 /* override pptable_id from driver parameter */
377 if (amdgpu_smu_pptable_id >= 0) {
378 pptable_id = amdgpu_smu_pptable_id;
379 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
381 pptable_id = smu->smu_table.boot_values.pp_table_id;
384 /* force using vbios pptable in sriov mode */
385 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
386 ret = smu_v14_0_get_pptable_from_vbios(smu, &table, &size);
388 ret = smu_v14_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
393 if (!smu->smu_table.power_play_table)
394 smu->smu_table.power_play_table = table;
395 if (!smu->smu_table.power_play_table_size)
396 smu->smu_table.power_play_table_size = size;
401 int smu_v14_0_init_smc_tables(struct smu_context *smu)
403 struct smu_table_context *smu_table = &smu->smu_table;
404 struct smu_table *tables = smu_table->tables;
407 smu_table->driver_pptable =
408 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
409 if (!smu_table->driver_pptable) {
414 smu_table->max_sustainable_clocks =
415 kzalloc(sizeof(struct smu_14_0_max_sustainable_clocks), GFP_KERNEL);
416 if (!smu_table->max_sustainable_clocks) {
421 if (tables[SMU_TABLE_OVERDRIVE].size) {
422 smu_table->overdrive_table =
423 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
424 if (!smu_table->overdrive_table) {
429 smu_table->boot_overdrive_table =
430 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
431 if (!smu_table->boot_overdrive_table) {
437 smu_table->combo_pptable =
438 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
439 if (!smu_table->combo_pptable) {
447 kfree(smu_table->boot_overdrive_table);
449 kfree(smu_table->overdrive_table);
451 kfree(smu_table->max_sustainable_clocks);
453 kfree(smu_table->driver_pptable);
458 int smu_v14_0_fini_smc_tables(struct smu_context *smu)
460 struct smu_table_context *smu_table = &smu->smu_table;
461 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
463 kfree(smu_table->gpu_metrics_table);
464 kfree(smu_table->combo_pptable);
465 kfree(smu_table->boot_overdrive_table);
466 kfree(smu_table->overdrive_table);
467 kfree(smu_table->max_sustainable_clocks);
468 kfree(smu_table->driver_pptable);
469 smu_table->gpu_metrics_table = NULL;
470 smu_table->combo_pptable = NULL;
471 smu_table->boot_overdrive_table = NULL;
472 smu_table->overdrive_table = NULL;
473 smu_table->max_sustainable_clocks = NULL;
474 smu_table->driver_pptable = NULL;
475 kfree(smu_table->hardcode_pptable);
476 smu_table->hardcode_pptable = NULL;
478 kfree(smu_table->ecc_table);
479 kfree(smu_table->metrics_table);
480 kfree(smu_table->watermarks_table);
481 smu_table->ecc_table = NULL;
482 smu_table->metrics_table = NULL;
483 smu_table->watermarks_table = NULL;
484 smu_table->metrics_time = 0;
486 kfree(smu_dpm->dpm_context);
487 kfree(smu_dpm->golden_dpm_context);
488 kfree(smu_dpm->dpm_current_power_state);
489 kfree(smu_dpm->dpm_request_power_state);
490 smu_dpm->dpm_context = NULL;
491 smu_dpm->golden_dpm_context = NULL;
492 smu_dpm->dpm_context_size = 0;
493 smu_dpm->dpm_current_power_state = NULL;
494 smu_dpm->dpm_request_power_state = NULL;
499 int smu_v14_0_init_power(struct smu_context *smu)
501 struct smu_power_context *smu_power = &smu->smu_power;
503 if (smu_power->power_context || smu_power->power_context_size != 0)
506 smu_power->power_context = kzalloc(sizeof(struct smu_14_0_dpm_context),
508 if (!smu_power->power_context)
510 smu_power->power_context_size = sizeof(struct smu_14_0_dpm_context);
515 int smu_v14_0_fini_power(struct smu_context *smu)
517 struct smu_power_context *smu_power = &smu->smu_power;
519 if (!smu_power->power_context || smu_power->power_context_size == 0)
522 kfree(smu_power->power_context);
523 smu_power->power_context = NULL;
524 smu_power->power_context_size = 0;
529 int smu_v14_0_get_vbios_bootup_values(struct smu_context *smu)
534 struct atom_common_table_header *header;
535 struct atom_firmware_info_v3_4 *v_3_4;
536 struct atom_firmware_info_v3_3 *v_3_3;
537 struct atom_firmware_info_v3_1 *v_3_1;
538 struct atom_smu_info_v3_6 *smu_info_v3_6;
539 struct atom_smu_info_v4_0 *smu_info_v4_0;
541 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
544 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
545 (uint8_t **)&header);
549 if (header->format_revision != 3) {
550 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu14\n");
554 switch (header->content_revision) {
558 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
559 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
560 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
561 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
562 smu->smu_table.boot_values.socclk = 0;
563 smu->smu_table.boot_values.dcefclk = 0;
564 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
565 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
566 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
567 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
568 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
569 smu->smu_table.boot_values.pp_table_id = 0;
572 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
573 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
574 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
575 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
576 smu->smu_table.boot_values.socclk = 0;
577 smu->smu_table.boot_values.dcefclk = 0;
578 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
579 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
580 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
581 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
582 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
583 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
587 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
588 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
589 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
590 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
591 smu->smu_table.boot_values.socclk = 0;
592 smu->smu_table.boot_values.dcefclk = 0;
593 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
594 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
595 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
596 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
597 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
598 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
602 smu->smu_table.boot_values.format_revision = header->format_revision;
603 smu->smu_table.boot_values.content_revision = header->content_revision;
605 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
607 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
608 (uint8_t **)&header)) {
610 if ((frev == 3) && (crev == 6)) {
611 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
613 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
614 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
615 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
616 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
617 } else if ((frev == 3) && (crev == 1)) {
619 } else if ((frev == 4) && (crev == 0)) {
620 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
622 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
623 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
624 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
625 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
626 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
628 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
629 (uint32_t)frev, (uint32_t)crev);
637 int smu_v14_0_notify_memory_pool_location(struct smu_context *smu)
639 struct smu_table_context *smu_table = &smu->smu_table;
640 struct smu_table *memory_pool = &smu_table->memory_pool;
643 uint32_t address_low, address_high;
645 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
648 address = memory_pool->mc_address;
649 address_high = (uint32_t)upper_32_bits(address);
650 address_low = (uint32_t)lower_32_bits(address);
652 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
656 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
660 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
661 (uint32_t)memory_pool->size, NULL);
668 int smu_v14_0_set_driver_table_location(struct smu_context *smu)
670 struct smu_table *driver_table = &smu->smu_table.driver_table;
673 if (driver_table->mc_address) {
674 ret = smu_cmn_send_smc_msg_with_param(smu,
675 SMU_MSG_SetDriverDramAddrHigh,
676 upper_32_bits(driver_table->mc_address),
679 ret = smu_cmn_send_smc_msg_with_param(smu,
680 SMU_MSG_SetDriverDramAddrLow,
681 lower_32_bits(driver_table->mc_address),
688 int smu_v14_0_set_tool_table_location(struct smu_context *smu)
691 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
693 if (tool_table->mc_address) {
694 ret = smu_cmn_send_smc_msg_with_param(smu,
695 SMU_MSG_SetToolsDramAddrHigh,
696 upper_32_bits(tool_table->mc_address),
699 ret = smu_cmn_send_smc_msg_with_param(smu,
700 SMU_MSG_SetToolsDramAddrLow,
701 lower_32_bits(tool_table->mc_address),
708 int smu_v14_0_set_allowed_mask(struct smu_context *smu)
710 struct smu_feature *feature = &smu->smu_feature;
712 uint32_t feature_mask[2];
714 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
715 feature->feature_num < 64)
718 bitmap_to_arr32(feature_mask, feature->allowed, 64);
720 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
721 feature_mask[1], NULL);
725 return smu_cmn_send_smc_msg_with_param(smu,
726 SMU_MSG_SetAllowedFeaturesMaskLow,
731 int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable)
734 struct amdgpu_device *adev = smu->adev;
736 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
737 case IP_VERSION(14, 0, 2):
738 case IP_VERSION(14, 0, 0):
739 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
742 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
744 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
753 int smu_v14_0_system_features_control(struct smu_context *smu,
756 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
757 SMU_MSG_DisableAllSmuFeatures), NULL);
760 int smu_v14_0_notify_display_change(struct smu_context *smu)
764 if (!smu->pm_enabled)
767 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
768 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
769 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
774 int smu_v14_0_get_current_power_limit(struct smu_context *smu,
775 uint32_t *power_limit)
780 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
783 power_src = smu_cmn_to_asic_specific_index(smu,
784 CMN2ASIC_MAPPING_PWR,
785 smu->adev->pm.ac_power ?
786 SMU_POWER_SOURCE_AC :
787 SMU_POWER_SOURCE_DC);
791 ret = smu_cmn_send_smc_msg_with_param(smu,
796 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
801 int smu_v14_0_set_power_limit(struct smu_context *smu,
802 enum smu_ppt_limit_type limit_type,
807 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
810 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
811 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
815 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
817 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
821 smu->current_power_limit = limit;
826 static int smu_v14_0_set_irq_state(struct amdgpu_device *adev,
827 struct amdgpu_irq_src *source,
829 enum amdgpu_interrupt_state state)
834 case AMDGPU_IRQ_STATE_DISABLE:
838 /* For MP1 SW irqs */
839 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
840 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
841 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
844 case AMDGPU_IRQ_STATE_ENABLE:
848 /* For MP1 SW irqs */
849 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
850 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
851 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
852 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
854 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
855 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
856 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
866 static int smu_v14_0_irq_process(struct amdgpu_device *adev,
867 struct amdgpu_irq_src *source,
868 struct amdgpu_iv_entry *entry)
875 static const struct amdgpu_irq_src_funcs smu_v14_0_irq_funcs = {
876 .set = smu_v14_0_set_irq_state,
877 .process = smu_v14_0_irq_process,
880 int smu_v14_0_register_irq_handler(struct smu_context *smu)
882 struct amdgpu_device *adev = smu->adev;
883 struct amdgpu_irq_src *irq_src = &smu->irq_source;
886 if (amdgpu_sriov_vf(adev))
889 irq_src->num_types = 1;
890 irq_src->funcs = &smu_v14_0_irq_funcs;
894 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
903 static int smu_v14_0_wait_for_reset_complete(struct smu_context *smu,
908 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
909 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
914 int smu_v14_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
920 case SMU_EVENT_RESET_COMPLETE:
921 ret = smu_v14_0_wait_for_reset_complete(smu, event_arg);
930 int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
931 uint32_t *min, uint32_t *max)
933 int ret = 0, clk_id = 0;
935 uint32_t clock_limit;
937 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
941 clock_limit = smu->smu_table.boot_values.uclk;
945 clock_limit = smu->smu_table.boot_values.gfxclk;
948 clock_limit = smu->smu_table.boot_values.socclk;
955 /* clock in Mhz unit */
957 *min = clock_limit / 100;
959 *max = clock_limit / 100;
964 clk_id = smu_cmn_to_asic_specific_index(smu,
965 CMN2ASIC_MAPPING_CLK,
971 param = (clk_id & 0xffff) << 16;
974 if (smu->adev->pm.ac_power)
975 ret = smu_cmn_send_smc_msg_with_param(smu,
976 SMU_MSG_GetMaxDpmFreq,
980 ret = smu_cmn_send_smc_msg_with_param(smu,
981 SMU_MSG_GetDcModeMaxDpmFreq,
989 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
998 int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu,
999 enum smu_clk_type clk_type,
1003 int ret = 0, clk_id = 0;
1006 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1009 clk_id = smu_cmn_to_asic_specific_index(smu,
1010 CMN2ASIC_MAPPING_CLK,
1016 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1017 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1024 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1025 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1035 int smu_v14_0_set_hard_freq_limited_range(struct smu_context *smu,
1036 enum smu_clk_type clk_type,
1040 int ret = 0, clk_id = 0;
1043 if (min <= 0 && max <= 0)
1046 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1049 clk_id = smu_cmn_to_asic_specific_index(smu,
1050 CMN2ASIC_MAPPING_CLK,
1056 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1057 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1064 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1065 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1074 int smu_v14_0_set_performance_level(struct smu_context *smu,
1075 enum amd_dpm_forced_level level)
1077 struct smu_14_0_dpm_context *dpm_context =
1078 smu->smu_dpm.dpm_context;
1079 struct smu_14_0_dpm_table *gfx_table =
1080 &dpm_context->dpm_tables.gfx_table;
1081 struct smu_14_0_dpm_table *mem_table =
1082 &dpm_context->dpm_tables.uclk_table;
1083 struct smu_14_0_dpm_table *soc_table =
1084 &dpm_context->dpm_tables.soc_table;
1085 struct smu_14_0_dpm_table *vclk_table =
1086 &dpm_context->dpm_tables.vclk_table;
1087 struct smu_14_0_dpm_table *dclk_table =
1088 &dpm_context->dpm_tables.dclk_table;
1089 struct smu_14_0_dpm_table *fclk_table =
1090 &dpm_context->dpm_tables.fclk_table;
1091 struct smu_umd_pstate_table *pstate_table =
1093 struct amdgpu_device *adev = smu->adev;
1094 uint32_t sclk_min = 0, sclk_max = 0;
1095 uint32_t mclk_min = 0, mclk_max = 0;
1096 uint32_t socclk_min = 0, socclk_max = 0;
1097 uint32_t vclk_min = 0, vclk_max = 0;
1098 uint32_t dclk_min = 0, dclk_max = 0;
1099 uint32_t fclk_min = 0, fclk_max = 0;
1103 case AMD_DPM_FORCED_LEVEL_HIGH:
1104 sclk_min = sclk_max = gfx_table->max;
1105 mclk_min = mclk_max = mem_table->max;
1106 socclk_min = socclk_max = soc_table->max;
1107 vclk_min = vclk_max = vclk_table->max;
1108 dclk_min = dclk_max = dclk_table->max;
1109 fclk_min = fclk_max = fclk_table->max;
1111 case AMD_DPM_FORCED_LEVEL_LOW:
1112 sclk_min = sclk_max = gfx_table->min;
1113 mclk_min = mclk_max = mem_table->min;
1114 socclk_min = socclk_max = soc_table->min;
1115 vclk_min = vclk_max = vclk_table->min;
1116 dclk_min = dclk_max = dclk_table->min;
1117 fclk_min = fclk_max = fclk_table->min;
1119 case AMD_DPM_FORCED_LEVEL_AUTO:
1120 sclk_min = gfx_table->min;
1121 sclk_max = gfx_table->max;
1122 mclk_min = mem_table->min;
1123 mclk_max = mem_table->max;
1124 socclk_min = soc_table->min;
1125 socclk_max = soc_table->max;
1126 vclk_min = vclk_table->min;
1127 vclk_max = vclk_table->max;
1128 dclk_min = dclk_table->min;
1129 dclk_max = dclk_table->max;
1130 fclk_min = fclk_table->min;
1131 fclk_max = fclk_table->max;
1133 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1134 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1135 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1136 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1137 vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1138 dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1139 fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1141 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1142 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1144 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1145 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1147 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1148 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1149 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1150 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1151 vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1152 dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1153 fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1155 case AMD_DPM_FORCED_LEVEL_MANUAL:
1156 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1159 dev_err(adev->dev, "Invalid performance level %d\n", level);
1163 if (sclk_min && sclk_max) {
1164 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1171 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1172 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1175 if (mclk_min && mclk_max) {
1176 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1183 pstate_table->uclk_pstate.curr.min = mclk_min;
1184 pstate_table->uclk_pstate.curr.max = mclk_max;
1187 if (socclk_min && socclk_max) {
1188 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1195 pstate_table->socclk_pstate.curr.min = socclk_min;
1196 pstate_table->socclk_pstate.curr.max = socclk_max;
1199 if (vclk_min && vclk_max) {
1200 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1201 if (adev->vcn.harvest_config & (1 << i))
1203 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1204 i ? SMU_VCLK1 : SMU_VCLK,
1210 pstate_table->vclk_pstate.curr.min = vclk_min;
1211 pstate_table->vclk_pstate.curr.max = vclk_max;
1214 if (dclk_min && dclk_max) {
1215 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1216 if (adev->vcn.harvest_config & (1 << i))
1218 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1219 i ? SMU_DCLK1 : SMU_DCLK,
1225 pstate_table->dclk_pstate.curr.min = dclk_min;
1226 pstate_table->dclk_pstate.curr.max = dclk_max;
1229 if (fclk_min && fclk_max) {
1230 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1237 pstate_table->fclk_pstate.curr.min = fclk_min;
1238 pstate_table->fclk_pstate.curr.max = fclk_max;
1244 int smu_v14_0_set_power_source(struct smu_context *smu,
1245 enum smu_power_src_type power_src)
1249 pwr_source = smu_cmn_to_asic_specific_index(smu,
1250 CMN2ASIC_MAPPING_PWR,
1251 (uint32_t)power_src);
1255 return smu_cmn_send_smc_msg_with_param(smu,
1256 SMU_MSG_NotifyPowerSource,
1261 static int smu_v14_0_get_dpm_freq_by_index(struct smu_context *smu,
1262 enum smu_clk_type clk_type,
1266 int ret = 0, clk_id = 0;
1272 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1275 clk_id = smu_cmn_to_asic_specific_index(smu,
1276 CMN2ASIC_MAPPING_CLK,
1281 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1283 ret = smu_cmn_send_smc_msg_with_param(smu,
1284 SMU_MSG_GetDpmFreqByIndex,
1290 *value = *value & 0x7fffffff;
1295 static int smu_v14_0_get_dpm_level_count(struct smu_context *smu,
1296 enum smu_clk_type clk_type,
1301 ret = smu_v14_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1306 static int smu_v14_0_get_fine_grained_status(struct smu_context *smu,
1307 enum smu_clk_type clk_type,
1308 bool *is_fine_grained_dpm)
1310 int ret = 0, clk_id = 0;
1314 if (!is_fine_grained_dpm)
1317 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1320 clk_id = smu_cmn_to_asic_specific_index(smu,
1321 CMN2ASIC_MAPPING_CLK,
1326 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
1328 ret = smu_cmn_send_smc_msg_with_param(smu,
1329 SMU_MSG_GetDpmFreqByIndex,
1336 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM
1337 * now, we un-support it
1339 *is_fine_grained_dpm = value & 0x80000000;
1344 int smu_v14_0_set_single_dpm_table(struct smu_context *smu,
1345 enum smu_clk_type clk_type,
1346 struct smu_14_0_dpm_table *single_dpm_table)
1352 ret = smu_v14_0_get_dpm_level_count(smu,
1354 &single_dpm_table->count);
1356 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1360 ret = smu_v14_0_get_fine_grained_status(smu,
1362 &single_dpm_table->is_fine_grained);
1364 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
1368 for (i = 0; i < single_dpm_table->count; i++) {
1369 ret = smu_v14_0_get_dpm_freq_by_index(smu,
1374 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1378 single_dpm_table->dpm_levels[i].value = clk;
1379 single_dpm_table->dpm_levels[i].enabled = true;
1382 single_dpm_table->min = clk;
1383 else if (i == single_dpm_table->count - 1)
1384 single_dpm_table->max = clk;
1390 int smu_v14_0_set_vcn_enable(struct smu_context *smu,
1393 struct amdgpu_device *adev = smu->adev;
1396 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1397 if (adev->vcn.harvest_config & (1 << i))
1400 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1401 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1410 int smu_v14_0_set_jpeg_enable(struct smu_context *smu,
1413 return smu_cmn_send_smc_msg_with_param(smu, enable ?
1414 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
1418 int smu_v14_0_run_btc(struct smu_context *smu)
1422 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
1424 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
1429 int smu_v14_0_gpo_control(struct smu_context *smu,
1434 res = smu_cmn_send_smc_msg_with_param(smu,
1439 dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement);
1444 int smu_v14_0_deep_sleep_control(struct smu_context *smu,
1447 struct amdgpu_device *adev = smu->adev;
1450 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
1451 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
1453 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
1458 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
1459 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
1461 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
1466 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
1467 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
1469 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
1474 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
1475 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
1477 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
1482 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
1483 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
1485 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
1490 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
1491 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
1493 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
1498 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
1499 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
1501 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
1506 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
1507 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
1509 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
1517 int smu_v14_0_gfx_ulv_control(struct smu_context *smu,
1522 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
1523 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
1528 int smu_v14_0_baco_set_armd3_sequence(struct smu_context *smu,
1529 enum smu_baco_seq baco_seq)
1531 struct smu_baco_context *smu_baco = &smu->smu_baco;
1534 ret = smu_cmn_send_smc_msg_with_param(smu,
1541 if (baco_seq == BACO_SEQ_BAMACO ||
1542 baco_seq == BACO_SEQ_BACO)
1543 smu_baco->state = SMU_BACO_STATE_ENTER;
1545 smu_baco->state = SMU_BACO_STATE_EXIT;
1550 bool smu_v14_0_baco_is_support(struct smu_context *smu)
1552 struct smu_baco_context *smu_baco = &smu->smu_baco;
1554 if (amdgpu_sriov_vf(smu->adev) ||
1555 !smu_baco->platform_support)
1558 /* return true if ASIC is in BACO state already */
1559 if (smu_v14_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
1562 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1563 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1569 enum smu_baco_state smu_v14_0_baco_get_state(struct smu_context *smu)
1571 struct smu_baco_context *smu_baco = &smu->smu_baco;
1573 return smu_baco->state;
1576 int smu_v14_0_baco_set_state(struct smu_context *smu,
1577 enum smu_baco_state state)
1579 struct smu_baco_context *smu_baco = &smu->smu_baco;
1580 struct amdgpu_device *adev = smu->adev;
1583 if (smu_v14_0_baco_get_state(smu) == state)
1586 if (state == SMU_BACO_STATE_ENTER) {
1587 ret = smu_cmn_send_smc_msg_with_param(smu,
1589 smu_baco->maco_support ?
1590 BACO_SEQ_BAMACO : BACO_SEQ_BACO,
1593 ret = smu_cmn_send_smc_msg(smu,
1599 /* clear vbios scratch 6 and 7 for coming asic reinit */
1600 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1601 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1605 smu_baco->state = state;
1610 int smu_v14_0_baco_enter(struct smu_context *smu)
1614 ret = smu_v14_0_baco_set_state(smu,
1615 SMU_BACO_STATE_ENTER);
1624 int smu_v14_0_baco_exit(struct smu_context *smu)
1626 return smu_v14_0_baco_set_state(smu,
1627 SMU_BACO_STATE_EXIT);
1630 int smu_v14_0_set_gfx_power_up_by_imu(struct smu_context *smu)
1634 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
1635 SMU_MSG_EnableGfxImu);
1636 /* Param 1 to tell PMFW to enable GFXOFF feature */
1637 return smu_cmn_send_msg_without_waiting(smu, index, 1);
1640 int smu_v14_0_set_default_dpm_tables(struct smu_context *smu)
1642 struct smu_table_context *smu_table = &smu->smu_table;
1644 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
1645 smu_table->clocks_table, false);
1648 int smu_v14_0_od_edit_dpm_table(struct smu_context *smu,
1649 enum PP_OD_DPM_TABLE_COMMAND type,
1650 long input[], uint32_t size)
1652 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1655 /* Only allowed in manual mode */
1656 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1660 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1662 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1666 if (input[0] == 0) {
1667 if (input[1] < smu->gfx_default_hard_min_freq) {
1668 dev_warn(smu->adev->dev,
1669 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
1670 input[1], smu->gfx_default_hard_min_freq);
1673 smu->gfx_actual_hard_min_freq = input[1];
1674 } else if (input[0] == 1) {
1675 if (input[1] > smu->gfx_default_soft_max_freq) {
1676 dev_warn(smu->adev->dev,
1677 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
1678 input[1], smu->gfx_default_soft_max_freq);
1681 smu->gfx_actual_soft_max_freq = input[1];
1686 case PP_OD_RESTORE_DEFAULT_TABLE:
1688 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1691 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1692 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1694 case PP_OD_COMMIT_DPM_TABLE:
1696 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1699 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
1700 dev_err(smu->adev->dev,
1701 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
1702 smu->gfx_actual_hard_min_freq,
1703 smu->gfx_actual_soft_max_freq);
1707 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
1708 smu->gfx_actual_hard_min_freq,
1711 dev_err(smu->adev->dev, "Set hard min sclk failed!");
1715 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1716 smu->gfx_actual_soft_max_freq,
1719 dev_err(smu->adev->dev, "Set soft max sclk failed!");