drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_smu.h"
  31 #include "atomfirmware.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "amdgpu_atombios.h"
  34 #include "smu_v13_0.h"
  35 #include "smu13_driver_if_v13_0_7.h"
  36 #include "soc15_common.h"
  37 #include "atom.h"
  38 #include "smu_v13_0_7_ppt.h"
  39 #include "smu_v13_0_7_pptable.h"
  40 #include "smu_v13_0_7_ppsmc.h"
  41 #include "nbio/nbio_4_3_0_offset.h"
  42 #include "nbio/nbio_4_3_0_sh_mask.h"
  43 #include "mp/mp_13_0_0_offset.h"
  44 #include "mp/mp_13_0_0_sh_mask.h"
  45
  46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h"
  47 #include "smu_cmn.h"
  48 #include "amdgpu_ras.h"
  49
  50 /*
  51  * DO NOT use these for err/warn/info/debug messages.
  52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53  * They are more MGPU friendly.
  54  */
  55 #undef pr_err
  56 #undef pr_warn
  57 #undef pr_info
  58 #undef pr_debug
  59
  60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  61
  62 #define FEATURE_MASK(feature) (1ULL << feature)
  63 #define SMC_DPM_FEATURE ( \
  64         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  65         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  66         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  67         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  68         FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  69         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
  70
  71 #define smnMP1_FIRMWARE_FLAGS_SMU_13_0_7   0x3b10028
  72
  73 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE   0x4000
  74
  75 static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] = {
  76         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                 1),
  77         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,               1),
  78         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,          1),
  79         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,   0),
  80         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,  0),
  81         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,        0),
  82         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,       0),
  83         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,        1),
  84         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,       1),
  85         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,       1),
  86         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,      1),
  87         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow,    1),
  88         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
  89         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,             1),
  90         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                 0),
  91         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,       1),
  92         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,        1),
  93         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,        0),
  94         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,         0),
  95         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,       1),
  96         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,       0),
  97         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,           0),
  98         MSG_MAP(RunDcBtc,                       PPSMC_MSG_RunDcBtc,                    0),
  99         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                   0),
 100         MSG_MAP(ExitBaco,           PPSMC_MSG_ExitBaco,                            0),
 101         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            1),
 102         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            1),
 103         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,            1),
 104         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,            0),
 105         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,               1),
 106         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,               1),
 107         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,           1),
 108         MSG_MAP(PowerUpVcn,                             PPSMC_MSG_PowerUpVcn,                  0),
 109         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                0),
 110         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                 0),
 111         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,               0),
 112         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,         1),
 113         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,      0),
 114         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,       0),
 115         MSG_MAP(AllowIHHostInterrupt,           PPSMC_MSG_AllowIHHostInterrupt,       0),
 116         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh,      0),
 117         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow,       0),
 118         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize,          0),
 119         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                 0),
 120         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,              0),
 121         MSG_MAP(Mode1Reset,             PPSMC_MSG_Mode1Reset,                  0),
 122         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,         0),
 123         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
 124 };
 125
 126 static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
 127         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 128         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 129         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 130         CLK_MAP(FCLK,           PPCLK_FCLK),
 131         CLK_MAP(UCLK,           PPCLK_UCLK),
 132         CLK_MAP(MCLK,           PPCLK_UCLK),
 133         CLK_MAP(VCLK,           PPCLK_VCLK_0),
 134         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 135         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 136         CLK_MAP(DCLK1,          PPCLK_DCLK_1),
 137 };
 138
 139 static struct cmn2asic_mapping smu_v13_0_7_feature_mask_map[SMU_FEATURE_COUNT] = {
 140         FEA_MAP(FW_DATA_READ),
 141         FEA_MAP(DPM_GFXCLK),
 142         FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
 143         FEA_MAP(DPM_UCLK),
 144         FEA_MAP(DPM_FCLK),
 145         FEA_MAP(DPM_SOCCLK),
 146         FEA_MAP(DPM_MP0CLK),
 147         FEA_MAP(DPM_LINK),
 148         FEA_MAP(DPM_DCN),
 149         FEA_MAP(VMEMP_SCALING),
 150         FEA_MAP(VDDIO_MEM_SCALING),
 151         FEA_MAP(DS_GFXCLK),
 152         FEA_MAP(DS_SOCCLK),
 153         FEA_MAP(DS_FCLK),
 154         FEA_MAP(DS_LCLK),
 155         FEA_MAP(DS_DCFCLK),
 156         FEA_MAP(DS_UCLK),
 157         FEA_MAP(GFX_ULV),
 158         FEA_MAP(FW_DSTATE),
 159         FEA_MAP(GFXOFF),
 160         FEA_MAP(BACO),
 161         FEA_MAP(MM_DPM),
 162         FEA_MAP(SOC_MPCLK_DS),
 163         FEA_MAP(BACO_MPCLK_DS),
 164         FEA_MAP(THROTTLERS),
 165         FEA_MAP(SMARTSHIFT),
 166         FEA_MAP(GTHR),
 167         FEA_MAP(ACDC),
 168         FEA_MAP(VR0HOT),
 169         FEA_MAP(FW_CTF),
 170         FEA_MAP(FAN_CONTROL),
 171         FEA_MAP(GFX_DCS),
 172         FEA_MAP(GFX_READ_MARGIN),
 173         FEA_MAP(LED_DISPLAY),
 174         FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
 175         FEA_MAP(OUT_OF_BAND_MONITOR),
 176         FEA_MAP(OPTIMIZED_VMIN),
 177         FEA_MAP(GFX_IMU),
 178         FEA_MAP(BOOT_TIME_CAL),
 179         FEA_MAP(GFX_PCC_DFLL),
 180         FEA_MAP(SOC_CG),
 181         FEA_MAP(DF_CSTATE),
 182         FEA_MAP(GFX_EDC),
 183         FEA_MAP(BOOT_POWER_OPT),
 184         FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
 185         FEA_MAP(DS_VCN),
 186         FEA_MAP(BACO_CG),
 187         FEA_MAP(MEM_TEMP_READ),
 188         FEA_MAP(ATHUB_MMHUB_PG),
 189         FEA_MAP(SOC_PCC),
 190 };
 191
 192 static struct cmn2asic_mapping smu_v13_0_7_table_map[SMU_TABLE_COUNT] = {
 193         TAB_MAP(PPTABLE),
 194         TAB_MAP(WATERMARKS),
 195         TAB_MAP(AVFS_PSM_DEBUG),
 196         TAB_MAP(PMSTATUSLOG),
 197         TAB_MAP(SMU_METRICS),
 198         TAB_MAP(DRIVER_SMU_CONFIG),
 199         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 200         [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
 201 };
 202
 203 static struct cmn2asic_mapping smu_v13_0_7_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 204         PWR_MAP(AC),
 205         PWR_MAP(DC),
 206 };
 207
 208 static struct cmn2asic_mapping smu_v13_0_7_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 209         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 210         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 211         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 212         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 213         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 214         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 215         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 216         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D,             WORKLOAD_PPLIB_WINDOW_3D_BIT),
 217 };
 218
 219 static const uint8_t smu_v13_0_7_throttler_map[] = {
 220         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 221         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 222         [THROTTLER_PPT2_BIT]            = (SMU_THROTTLER_PPT2_BIT),
 223         [THROTTLER_PPT3_BIT]            = (SMU_THROTTLER_PPT3_BIT),
 224         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 225         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 226         [THROTTLER_TEMP_EDGE_BIT]       = (SMU_THROTTLER_TEMP_EDGE_BIT),
 227         [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 228         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 229         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 230         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 231         [THROTTLER_TEMP_VR_MEM0_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 232         [THROTTLER_TEMP_VR_MEM1_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
 233         [THROTTLER_TEMP_LIQUID0_BIT]    = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
 234         [THROTTLER_TEMP_LIQUID1_BIT]    = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
 235         [THROTTLER_GFX_APCC_PLUS_BIT]   = (SMU_THROTTLER_APCC_BIT),
 236         [THROTTLER_FIT_BIT]             = (SMU_THROTTLER_FIT_BIT),
 237 };
 238
 239 static int
 240 smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu,
 241                                   uint32_t *feature_mask, uint32_t num)
 242 {
 243         struct amdgpu_device *adev = smu->adev;
 244
 245         if (num > 2)
 246                 return -EINVAL;
 247
 248         memset(feature_mask, 0, sizeof(uint32_t) * num);
 249
 250         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT);
 251
 252         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
 253                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 254                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
 255                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);
 256         }
 257
 258         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 259                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 260
 261         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {
 262                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
 263                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT);
 264                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
 265                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
 266         }
 267
 268         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 269
 270         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 271                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 272
 273         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 274                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 275
 276         if (adev->pm.pp_feature & PP_ULV_MASK)
 277                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 278
 279         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
 280         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT);
 281         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT);
 282         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT);
 283         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT);
 284         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT);
 285         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT);
 286         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT);
 287         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT);
 288         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT);
 289         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
 290         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT);
 291         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT);
 292         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
 293         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT);
 294         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT);
 295         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT);
 296         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT);
 297         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT);
 298
 299         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 300                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT);
 301
 302         if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) &&
 303             (adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
 304                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
 305
 306         return 0;
 307 }
 308
 309 static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu)
 310 {
 311         struct smu_table_context *table_context = &smu->smu_table;
 312         struct smu_13_0_7_powerplay_table *powerplay_table =
 313                 table_context->power_play_table;
 314         struct smu_baco_context *smu_baco = &smu->smu_baco;
 315         PPTable_t *smc_pptable = table_context->driver_pptable;
 316         BoardTable_t *BoardTable = &smc_pptable->BoardTable;
 317
 318         if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC)
 319                 smu->dc_controlled_by_gpio = true;
 320
 321         if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO ||
 322             powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO)
 323                 smu_baco->platform_support = true;
 324
 325         if (smu_baco->platform_support && (BoardTable->HsrEnabled || BoardTable->VddqOffEnabled))
 326                 smu_baco->maco_support = true;
 327
 328         table_context->thermal_controller_type =
 329                 powerplay_table->thermal_controller_type;
 330
 331         /*
 332          * Instead of having its own buffer space and get overdrive_table copied,
 333          * smu->od_settings just points to the actual overdrive_table
 334          */
 335         smu->od_settings = &powerplay_table->overdrive_table;
 336
 337         return 0;
 338 }
 339
 340 static int smu_v13_0_7_store_powerplay_table(struct smu_context *smu)
 341 {
 342         struct smu_table_context *table_context = &smu->smu_table;
 343         struct smu_13_0_7_powerplay_table *powerplay_table =
 344                 table_context->power_play_table;
 345         struct amdgpu_device *adev = smu->adev;
 346
 347         if (adev->pdev->device == 0x51)
 348                 powerplay_table->smc_pptable.SkuTable.DebugOverrides |= 0x00000080;
 349
 350         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 351                sizeof(PPTable_t));
 352
 353         return 0;
 354 }
 355
 356 static int smu_v13_0_7_check_fw_status(struct smu_context *smu)
 357 {
 358         struct amdgpu_device *adev = smu->adev;
 359         uint32_t mp1_fw_flags;
 360
 361         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 362                                    (smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 & 0xffffffff));
 363
 364         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 365                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 366                 return 0;
 367
 368         return -EIO;
 369 }
 370
 371 #ifndef atom_smc_dpm_info_table_13_0_7
 372 struct atom_smc_dpm_info_table_13_0_7
 373 {
 374         struct atom_common_table_header table_header;
 375         BoardTable_t BoardTable;
 376 };
 377 #endif
 378
 379 static int smu_v13_0_7_append_powerplay_table(struct smu_context *smu)
 380 {
 381         struct smu_table_context *table_context = &smu->smu_table;
 382
 383         PPTable_t *smc_pptable = table_context->driver_pptable;
 384
 385         struct atom_smc_dpm_info_table_13_0_7 *smc_dpm_table;
 386
 387         BoardTable_t *BoardTable = &smc_pptable->BoardTable;
 388
 389         int index, ret;
 390
 391         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 392         smc_dpm_info);
 393
 394         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 395                         (uint8_t **)&smc_dpm_table);
 396         if (ret)
 397                 return ret;
 398
 399         memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t));
 400
 401         return 0;
 402 }
 403
 404 static int smu_v13_0_7_get_pptable_from_pmfw(struct smu_context *smu,
 405                                              void **table,
 406                                              uint32_t *size)
 407 {
 408         struct smu_table_context *smu_table = &smu->smu_table;
 409         void *combo_pptable = smu_table->combo_pptable;
 410         int ret = 0;
 411
 412         ret = smu_cmn_get_combo_pptable(smu);
 413         if (ret)
 414                 return ret;
 415
 416         *table = combo_pptable;
 417         *size = sizeof(struct smu_13_0_7_powerplay_table);
 418
 419         return 0;
 420 }
 421
 422 static int smu_v13_0_7_setup_pptable(struct smu_context *smu)
 423 {
 424         struct smu_table_context *smu_table = &smu->smu_table;
 425         struct amdgpu_device *adev = smu->adev;
 426         int ret = 0;
 427
 428         /*
 429          * With SCPM enabled, the pptable used will be signed. It cannot
 430          * be used directly by driver. To get the raw pptable, we need to
 431          * rely on the combo pptable(and its revelant SMU message).
 432          */
 433         ret = smu_v13_0_7_get_pptable_from_pmfw(smu,
 434                                                 &smu_table->power_play_table,
 435                                                 &smu_table->power_play_table_size);
 436         if (ret)
 437                 return ret;
 438
 439         ret = smu_v13_0_7_store_powerplay_table(smu);
 440         if (ret)
 441                 return ret;
 442
 443         /*
 444          * With SCPM enabled, the operation below will be handled
 445          * by PSP. Driver involvment is unnecessary and useless.
 446          */
 447         if (!adev->scpm_enabled) {
 448                 ret = smu_v13_0_7_append_powerplay_table(smu);
 449                 if (ret)
 450                         return ret;
 451         }
 452
 453         ret = smu_v13_0_7_check_powerplay_table(smu);
 454         if (ret)
 455                 return ret;
 456
 457         return ret;
 458 }
 459
 460 static int smu_v13_0_7_tables_init(struct smu_context *smu)
 461 {
 462         struct smu_table_context *smu_table = &smu->smu_table;
 463         struct smu_table *tables = smu_table->tables;
 464
 465         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 466                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 467
 468         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 469                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 470         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
 471                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 472         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 473                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 474         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 475                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 476         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
 477                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 478         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 479                        sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
 480                        AMDGPU_GEM_DOMAIN_VRAM);
 481         SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
 482                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 483
 484         smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
 485         if (!smu_table->metrics_table)
 486                 goto err0_out;
 487         smu_table->metrics_time = 0;
 488
 489         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 490         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 491         if (!smu_table->gpu_metrics_table)
 492                 goto err1_out;
 493
 494         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 495         if (!smu_table->watermarks_table)
 496                 goto err2_out;
 497
 498         return 0;
 499
 500 err2_out:
 501         kfree(smu_table->gpu_metrics_table);
 502 err1_out:
 503         kfree(smu_table->metrics_table);
 504 err0_out:
 505         return -ENOMEM;
 506 }
 507
 508 static int smu_v13_0_7_allocate_dpm_context(struct smu_context *smu)
 509 {
 510         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 511
 512         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
 513                                        GFP_KERNEL);
 514         if (!smu_dpm->dpm_context)
 515                 return -ENOMEM;
 516
 517         smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
 518
 519         return 0;
 520 }
 521
 522 static int smu_v13_0_7_init_smc_tables(struct smu_context *smu)
 523 {
 524         int ret = 0;
 525
 526         ret = smu_v13_0_7_tables_init(smu);
 527         if (ret)
 528                 return ret;
 529
 530         ret = smu_v13_0_7_allocate_dpm_context(smu);
 531         if (ret)
 532                 return ret;
 533
 534         return smu_v13_0_init_smc_tables(smu);
 535 }
 536
 537 static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu)
 538 {
 539         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 540         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 541         SkuTable_t *skutable = &driver_ppt->SkuTable;
 542         struct smu_13_0_dpm_table *dpm_table;
 543         struct smu_13_0_pcie_table *pcie_table;
 544         uint32_t link_level;
 545         int ret = 0;
 546
 547         /* socclk dpm table setup */
 548         dpm_table = &dpm_context->dpm_tables.soc_table;
 549         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 550                 ret = smu_v13_0_set_single_dpm_table(smu,
 551                                                      SMU_SOCCLK,
 552                                                      dpm_table);
 553                 if (ret)
 554                         return ret;
 555         } else {
 556                 dpm_table->count = 1;
 557                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 558                 dpm_table->dpm_levels[0].enabled = true;
 559                 dpm_table->min = dpm_table->dpm_levels[0].value;
 560                 dpm_table->max = dpm_table->dpm_levels[0].value;
 561         }
 562
 563         /* gfxclk dpm table setup */
 564         dpm_table = &dpm_context->dpm_tables.gfx_table;
 565         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 566                 ret = smu_v13_0_set_single_dpm_table(smu,
 567                                                      SMU_GFXCLK,
 568                                                      dpm_table);
 569                 if (ret)
 570                         return ret;
 571         } else {
 572                 dpm_table->count = 1;
 573                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 574                 dpm_table->dpm_levels[0].enabled = true;
 575                 dpm_table->min = dpm_table->dpm_levels[0].value;
 576                 dpm_table->max = dpm_table->dpm_levels[0].value;
 577         }
 578
 579         /* uclk dpm table setup */
 580         dpm_table = &dpm_context->dpm_tables.uclk_table;
 581         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 582                 ret = smu_v13_0_set_single_dpm_table(smu,
 583                                                      SMU_UCLK,
 584                                                      dpm_table);
 585                 if (ret)
 586                         return ret;
 587         } else {
 588                 dpm_table->count = 1;
 589                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 590                 dpm_table->dpm_levels[0].enabled = true;
 591                 dpm_table->min = dpm_table->dpm_levels[0].value;
 592                 dpm_table->max = dpm_table->dpm_levels[0].value;
 593         }
 594
 595         /* fclk dpm table setup */
 596         dpm_table = &dpm_context->dpm_tables.fclk_table;
 597         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 598                 ret = smu_v13_0_set_single_dpm_table(smu,
 599                                                      SMU_FCLK,
 600                                                      dpm_table);
 601                 if (ret)
 602                         return ret;
 603         } else {
 604                 dpm_table->count = 1;
 605                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 606                 dpm_table->dpm_levels[0].enabled = true;
 607                 dpm_table->min = dpm_table->dpm_levels[0].value;
 608                 dpm_table->max = dpm_table->dpm_levels[0].value;
 609         }
 610
 611         /* vclk dpm table setup */
 612         dpm_table = &dpm_context->dpm_tables.vclk_table;
 613         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
 614                 ret = smu_v13_0_set_single_dpm_table(smu,
 615                                                      SMU_VCLK,
 616                                                      dpm_table);
 617                 if (ret)
 618                         return ret;
 619         } else {
 620                 dpm_table->count = 1;
 621                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
 622                 dpm_table->dpm_levels[0].enabled = true;
 623                 dpm_table->min = dpm_table->dpm_levels[0].value;
 624                 dpm_table->max = dpm_table->dpm_levels[0].value;
 625         }
 626
 627         /* dclk dpm table setup */
 628         dpm_table = &dpm_context->dpm_tables.dclk_table;
 629         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
 630                 ret = smu_v13_0_set_single_dpm_table(smu,
 631                                                      SMU_DCLK,
 632                                                      dpm_table);
 633                 if (ret)
 634                         return ret;
 635         } else {
 636                 dpm_table->count = 1;
 637                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
 638                 dpm_table->dpm_levels[0].enabled = true;
 639                 dpm_table->min = dpm_table->dpm_levels[0].value;
 640                 dpm_table->max = dpm_table->dpm_levels[0].value;
 641         }
 642
 643         /* lclk dpm table setup */
 644         pcie_table = &dpm_context->dpm_tables.pcie_table;
 645         pcie_table->num_of_link_levels = 0;
 646         for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
 647                 if (!skutable->PcieGenSpeed[link_level] &&
 648                     !skutable->PcieLaneCount[link_level] &&
 649                     !skutable->LclkFreq[link_level])
 650                         continue;
 651
 652                 pcie_table->pcie_gen[pcie_table->num_of_link_levels] =
 653                                         skutable->PcieGenSpeed[link_level];
 654                 pcie_table->pcie_lane[pcie_table->num_of_link_levels] =
 655                                         skutable->PcieLaneCount[link_level];
 656                 pcie_table->clk_freq[pcie_table->num_of_link_levels] =
 657                                         skutable->LclkFreq[link_level];
 658                 pcie_table->num_of_link_levels++;
 659         }
 660
 661         return 0;
 662 }
 663
 664 static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu)
 665 {
 666         int ret = 0;
 667         uint64_t feature_enabled;
 668
 669         ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
 670         if (ret)
 671                 return false;
 672
 673         return !!(feature_enabled & SMC_DPM_FEATURE);
 674 }
 675
 676 static void smu_v13_0_7_dump_pptable(struct smu_context *smu)
 677 {
 678        struct smu_table_context *table_context = &smu->smu_table;
 679        PPTable_t *pptable = table_context->driver_pptable;
 680        SkuTable_t *skutable = &pptable->SkuTable;
 681
 682        dev_info(smu->adev->dev, "Dumped PPTable:\n");
 683
 684        dev_info(smu->adev->dev, "Version = 0x%08x\n", skutable->Version);
 685        dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", skutable->FeaturesToRun[0]);
 686        dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", skutable->FeaturesToRun[1]);
 687 }
 688
 689 static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics)
 690 {
 691         uint32_t throttler_status = 0;
 692         int i;
 693
 694         for (i = 0; i < THROTTLER_COUNT; i++)
 695                 throttler_status |=
 696                         (metrics->ThrottlingPercentage[i] ? 1U << i : 0);
 697
 698         return throttler_status;
 699 }
 700
 701 #define SMU_13_0_7_BUSY_THRESHOLD       15
 702 static int smu_v13_0_7_get_smu_metrics_data(struct smu_context *smu,
 703                                             MetricsMember_t member,
 704                                             uint32_t *value)
 705 {
 706         struct smu_table_context *smu_table= &smu->smu_table;
 707         SmuMetrics_t *metrics =
 708                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
 709         int ret = 0;
 710
 711         ret = smu_cmn_get_metrics_table(smu,
 712                                         NULL,
 713                                         false);
 714         if (ret)
 715                 return ret;
 716
 717         switch (member) {
 718         case METRICS_CURR_GFXCLK:
 719                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 720                 break;
 721         case METRICS_CURR_SOCCLK:
 722                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 723                 break;
 724         case METRICS_CURR_UCLK:
 725                 *value = metrics->CurrClock[PPCLK_UCLK];
 726                 break;
 727         case METRICS_CURR_VCLK:
 728                 *value = metrics->CurrClock[PPCLK_VCLK_0];
 729                 break;
 730         case METRICS_CURR_VCLK1:
 731                 *value = metrics->CurrClock[PPCLK_VCLK_1];
 732                 break;
 733         case METRICS_CURR_DCLK:
 734                 *value = metrics->CurrClock[PPCLK_DCLK_0];
 735                 break;
 736         case METRICS_CURR_DCLK1:
 737                 *value = metrics->CurrClock[PPCLK_DCLK_1];
 738                 break;
 739         case METRICS_CURR_FCLK:
 740                 *value = metrics->CurrClock[PPCLK_FCLK];
 741                 break;
 742         case METRICS_AVERAGE_GFXCLK:
 743                 *value = metrics->AverageGfxclkFrequencyPreDs;
 744                 break;
 745         case METRICS_AVERAGE_FCLK:
 746                 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD)
 747                         *value = metrics->AverageFclkFrequencyPostDs;
 748                 else
 749                         *value = metrics->AverageFclkFrequencyPreDs;
 750                 break;
 751         case METRICS_AVERAGE_UCLK:
 752                 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD)
 753                         *value = metrics->AverageMemclkFrequencyPostDs;
 754                 else
 755                         *value = metrics->AverageMemclkFrequencyPreDs;
 756                 break;
 757         case METRICS_AVERAGE_VCLK:
 758                 *value = metrics->AverageVclk0Frequency;
 759                 break;
 760         case METRICS_AVERAGE_DCLK:
 761                 *value = metrics->AverageDclk0Frequency;
 762                 break;
 763         case METRICS_AVERAGE_VCLK1:
 764                 *value = metrics->AverageVclk1Frequency;
 765                 break;
 766         case METRICS_AVERAGE_DCLK1:
 767                 *value = metrics->AverageDclk1Frequency;
 768                 break;
 769         case METRICS_AVERAGE_GFXACTIVITY:
 770                 *value = metrics->AverageGfxActivity;
 771                 break;
 772         case METRICS_AVERAGE_MEMACTIVITY:
 773                 *value = metrics->AverageUclkActivity;
 774                 break;
 775         case METRICS_AVERAGE_SOCKETPOWER:
 776                 *value = metrics->AverageSocketPower << 8;
 777                 break;
 778         case METRICS_TEMPERATURE_EDGE:
 779                 *value = metrics->AvgTemperature[TEMP_EDGE] *
 780                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 781                 break;
 782         case METRICS_TEMPERATURE_HOTSPOT:
 783                 *value = metrics->AvgTemperature[TEMP_HOTSPOT] *
 784                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 785                 break;
 786         case METRICS_TEMPERATURE_MEM:
 787                 *value = metrics->AvgTemperature[TEMP_MEM] *
 788                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 789                 break;
 790         case METRICS_TEMPERATURE_VRGFX:
 791                 *value = metrics->AvgTemperature[TEMP_VR_GFX] *
 792                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 793                 break;
 794         case METRICS_TEMPERATURE_VRSOC:
 795                 *value = metrics->AvgTemperature[TEMP_VR_SOC] *
 796                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 797                 break;
 798         case METRICS_THROTTLER_STATUS:
 799                 *value = smu_v13_0_7_get_throttler_status(metrics);
 800                 break;
 801         case METRICS_CURR_FANSPEED:
 802                 *value = metrics->AvgFanRpm;
 803                 break;
 804         case METRICS_CURR_FANPWM:
 805                 *value = metrics->AvgFanPwm;
 806                 break;
 807         case METRICS_VOLTAGE_VDDGFX:
 808                 *value = metrics->AvgVoltage[SVI_PLANE_GFX];
 809                 break;
 810         case METRICS_PCIE_RATE:
 811                 *value = metrics->PcieRate;
 812                 break;
 813         case METRICS_PCIE_WIDTH:
 814                 *value = metrics->PcieWidth;
 815                 break;
 816         default:
 817                 *value = UINT_MAX;
 818                 break;
 819         }
 820
 821         return ret;
 822 }
 823
 824 static int smu_v13_0_7_read_sensor(struct smu_context *smu,
 825                                    enum amd_pp_sensors sensor,
 826                                    void *data,
 827                                    uint32_t *size)
 828 {
 829         struct smu_table_context *table_context = &smu->smu_table;
 830         PPTable_t *smc_pptable = table_context->driver_pptable;
 831         int ret = 0;
 832
 833         switch (sensor) {
 834         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
 835                 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm;
 836                 *size = 4;
 837                 break;
 838         case AMDGPU_PP_SENSOR_MEM_LOAD:
 839                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
 840                                                        METRICS_AVERAGE_MEMACTIVITY,
 841                                                        (uint32_t *)data);
 842                 *size = 4;
 843                 break;
 844         case AMDGPU_PP_SENSOR_GPU_LOAD:
 845                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
 846                                                        METRICS_AVERAGE_GFXACTIVITY,
 847                                                        (uint32_t *)data);
 848                 *size = 4;
 849                 break;
 850         case AMDGPU_PP_SENSOR_GPU_POWER:
 851                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
 852                                                        METRICS_AVERAGE_SOCKETPOWER,
 853                                                        (uint32_t *)data);
 854                 *size = 4;
 855                 break;
 856         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 857                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
 858                                                        METRICS_TEMPERATURE_HOTSPOT,
 859                                                        (uint32_t *)data);
 860                 *size = 4;
 861                 break;
 862         case AMDGPU_PP_SENSOR_EDGE_TEMP:
 863                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
 864                                                        METRICS_TEMPERATURE_EDGE,
 865                                                        (uint32_t *)data);
 866                 *size = 4;
 867                 break;
 868         case AMDGPU_PP_SENSOR_MEM_TEMP:
 869                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
 870                                                        METRICS_TEMPERATURE_MEM,
 871                                                        (uint32_t *)data);
 872                 *size = 4;
 873                 break;
 874         case AMDGPU_PP_SENSOR_GFX_MCLK:
 875                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
 876                                                        METRICS_AVERAGE_UCLK,
 877                                                        (uint32_t *)data);
 878                 *(uint32_t *)data *= 100;
 879                 *size = 4;
 880                 break;
 881         case AMDGPU_PP_SENSOR_GFX_SCLK:
 882                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
 883                                                        METRICS_AVERAGE_GFXCLK,
 884                                                        (uint32_t *)data);
 885                 *(uint32_t *)data *= 100;
 886                 *size = 4;
 887                 break;
 888         case AMDGPU_PP_SENSOR_VDDGFX:
 889                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
 890                                                        METRICS_VOLTAGE_VDDGFX,
 891                                                        (uint32_t *)data);
 892                 *size = 4;
 893                 break;
 894         default:
 895                 ret = -EOPNOTSUPP;
 896                 break;
 897         }
 898
 899         return ret;
 900 }
 901
 902 static int smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context *smu,
 903                                                      enum smu_clk_type clk_type,
 904                                                      uint32_t *value)
 905 {
 906         MetricsMember_t member_type;
 907         int clk_id = 0;
 908
 909         clk_id = smu_cmn_to_asic_specific_index(smu,
 910                                                 CMN2ASIC_MAPPING_CLK,
 911                                                 clk_type);
 912         if (clk_id < 0)
 913                 return -EINVAL;
 914
 915         switch (clk_id) {
 916         case PPCLK_GFXCLK:
 917                 member_type = METRICS_AVERAGE_GFXCLK;
 918                 break;
 919         case PPCLK_UCLK:
 920                 member_type = METRICS_CURR_UCLK;
 921                 break;
 922         case PPCLK_FCLK:
 923                 member_type = METRICS_CURR_FCLK;
 924                 break;
 925         case PPCLK_SOCCLK:
 926                 member_type = METRICS_CURR_SOCCLK;
 927                 break;
 928         case PPCLK_VCLK_0:
 929                 member_type = METRICS_CURR_VCLK;
 930                 break;
 931         case PPCLK_DCLK_0:
 932                 member_type = METRICS_CURR_DCLK;
 933                 break;
 934         case PPCLK_VCLK_1:
 935                 member_type = METRICS_CURR_VCLK1;
 936                 break;
 937         case PPCLK_DCLK_1:
 938                 member_type = METRICS_CURR_DCLK1;
 939                 break;
 940         default:
 941                 return -EINVAL;
 942         }
 943
 944         return smu_v13_0_7_get_smu_metrics_data(smu,
 945                                                 member_type,
 946                                                 value);
 947 }
 948
 949 static int smu_v13_0_7_print_clk_levels(struct smu_context *smu,
 950                                         enum smu_clk_type clk_type,
 951                                         char *buf)
 952 {
 953         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 954         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 955         struct smu_13_0_dpm_table *single_dpm_table;
 956         struct smu_13_0_pcie_table *pcie_table;
 957         uint32_t gen_speed, lane_width;
 958         int i, curr_freq, size = 0;
 959         int ret = 0;
 960
 961         smu_cmn_get_sysfs_buf(&buf, &size);
 962
 963         if (amdgpu_ras_intr_triggered()) {
 964                 size += sysfs_emit_at(buf, size, "unavailable\n");
 965                 return size;
 966         }
 967
 968         switch (clk_type) {
 969         case SMU_SCLK:
 970                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 971                 break;
 972         case SMU_MCLK:
 973                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 974                 break;
 975         case SMU_SOCCLK:
 976                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 977                 break;
 978         case SMU_FCLK:
 979                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 980                 break;
 981         case SMU_VCLK:
 982         case SMU_VCLK1:
 983                 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
 984                 break;
 985         case SMU_DCLK:
 986         case SMU_DCLK1:
 987                 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
 988                 break;
 989         default:
 990                 break;
 991         }
 992
 993         switch (clk_type) {
 994         case SMU_SCLK:
 995         case SMU_MCLK:
 996         case SMU_SOCCLK:
 997         case SMU_FCLK:
 998         case SMU_VCLK:
 999         case SMU_VCLK1:
1000         case SMU_DCLK:
1001         case SMU_DCLK1:
1002                 ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
1003                 if (ret) {
1004                         dev_err(smu->adev->dev, "Failed to get current clock freq!");
1005                         return ret;
1006                 }
1007
1008                 if (single_dpm_table->is_fine_grained) {
1009                         /*
1010                          * For fine grained dpms, there are only two dpm levels:
1011                          *   - level 0 -> min clock freq
1012                          *   - level 1 -> max clock freq
1013                          * And the current clock frequency can be any value between them.
1014                          * So, if the current clock frequency is not at level 0 or level 1,
1015                          * we will fake it as three dpm levels:
1016                          *   - level 0 -> min clock freq
1017                          *   - level 1 -> current actual clock freq
1018                          *   - level 2 -> max clock freq
1019                          */
1020                         if ((single_dpm_table->dpm_levels[0].value != curr_freq) &&
1021                              (single_dpm_table->dpm_levels[1].value != curr_freq)) {
1022                                 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1023                                                 single_dpm_table->dpm_levels[0].value);
1024                                 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1025                                                 curr_freq);
1026                                 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1027                                                 single_dpm_table->dpm_levels[1].value);
1028                         } else {
1029                                 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1030                                                 single_dpm_table->dpm_levels[0].value,
1031                                                 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : "");
1032                                 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1033                                                 single_dpm_table->dpm_levels[1].value,
1034                                                 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : "");
1035                         }
1036                 } else {
1037                         for (i = 0; i < single_dpm_table->count; i++)
1038                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
1039                                                 i, single_dpm_table->dpm_levels[i].value,
1040                                                 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : "");
1041                 }
1042                 break;
1043         case SMU_PCIE:
1044                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
1045                                                        METRICS_PCIE_RATE,
1046                                                        &gen_speed);
1047                 if (ret)
1048                         return ret;
1049
1050                 ret = smu_v13_0_7_get_smu_metrics_data(smu,
1051                                                        METRICS_PCIE_WIDTH,
1052                                                        &lane_width);
1053                 if (ret)
1054                         return ret;
1055
1056                 pcie_table = &(dpm_context->dpm_tables.pcie_table);
1057                 for (i = 0; i < pcie_table->num_of_link_levels; i++)
1058                         size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1059                                         (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," :
1060                                         (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," :
1061                                         (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," :
1062                                         (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "",
1063                                         (pcie_table->pcie_lane[i] == 1) ? "x1" :
1064                                         (pcie_table->pcie_lane[i] == 2) ? "x2" :
1065                                         (pcie_table->pcie_lane[i] == 3) ? "x4" :
1066                                         (pcie_table->pcie_lane[i] == 4) ? "x8" :
1067                                         (pcie_table->pcie_lane[i] == 5) ? "x12" :
1068                                         (pcie_table->pcie_lane[i] == 6) ? "x16" : "",
1069                                         pcie_table->clk_freq[i],
1070                                         (gen_speed == pcie_table->pcie_gen[i]) &&
1071                                         (lane_width == pcie_table->pcie_lane[i]) ?
1072                                         "*" : "");
1073                 break;
1074
1075         default:
1076                 break;
1077         }
1078
1079         return size;
1080 }
1081
1082 static int smu_v13_0_7_force_clk_levels(struct smu_context *smu,
1083                                         enum smu_clk_type clk_type,
1084                                         uint32_t mask)
1085 {
1086         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1087         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1088         struct smu_13_0_dpm_table *single_dpm_table;
1089         uint32_t soft_min_level, soft_max_level;
1090         uint32_t min_freq, max_freq;
1091         int ret = 0;
1092
1093         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1094         soft_max_level = mask ? (fls(mask) - 1) : 0;
1095
1096         switch (clk_type) {
1097         case SMU_GFXCLK:
1098         case SMU_SCLK:
1099                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1100                 break;
1101         case SMU_MCLK:
1102         case SMU_UCLK:
1103                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1104                 break;
1105         case SMU_SOCCLK:
1106                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1107                 break;
1108         case SMU_FCLK:
1109                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1110                 break;
1111         case SMU_VCLK:
1112         case SMU_VCLK1:
1113                 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1114                 break;
1115         case SMU_DCLK:
1116         case SMU_DCLK1:
1117                 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1118                 break;
1119         default:
1120                 break;
1121         }
1122
1123         switch (clk_type) {
1124         case SMU_GFXCLK:
1125         case SMU_SCLK:
1126         case SMU_MCLK:
1127         case SMU_UCLK:
1128         case SMU_SOCCLK:
1129         case SMU_FCLK:
1130         case SMU_VCLK:
1131         case SMU_VCLK1:
1132         case SMU_DCLK:
1133         case SMU_DCLK1:
1134                 if (single_dpm_table->is_fine_grained) {
1135                         /* There is only 2 levels for fine grained DPM */
1136                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1137                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1138                 } else {
1139                         if ((soft_max_level >= single_dpm_table->count) ||
1140                             (soft_min_level >= single_dpm_table->count))
1141                                 return -EINVAL;
1142                 }
1143
1144                 min_freq = single_dpm_table->dpm_levels[soft_min_level].value;
1145                 max_freq = single_dpm_table->dpm_levels[soft_max_level].value;
1146
1147                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1148                                                             clk_type,
1149                                                             min_freq,
1150                                                             max_freq);
1151                 break;
1152         case SMU_DCEFCLK:
1153         case SMU_PCIE:
1154         default:
1155                 break;
1156         }
1157
1158         return ret;
1159 }
1160
1161 static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu,
1162                                               uint32_t pcie_gen_cap,
1163                                               uint32_t pcie_width_cap)
1164 {
1165         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1166         struct smu_13_0_pcie_table *pcie_table =
1167                                 &dpm_context->dpm_tables.pcie_table;
1168         uint32_t smu_pcie_arg;
1169         int ret, i;
1170
1171         for (i = 0; i < pcie_table->num_of_link_levels; i++) {
1172                 if (pcie_table->pcie_gen[i] > pcie_gen_cap)
1173                         pcie_table->pcie_gen[i] = pcie_gen_cap;
1174                 if (pcie_table->pcie_lane[i] > pcie_width_cap)
1175                         pcie_table->pcie_lane[i] = pcie_width_cap;
1176
1177                 smu_pcie_arg = i << 16;
1178                 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
1179                 smu_pcie_arg |= pcie_table->pcie_lane[i];
1180
1181                 ret = smu_cmn_send_smc_msg_with_param(smu,
1182                                                       SMU_MSG_OverridePcieParameters,
1183                                                       smu_pcie_arg,
1184                                                       NULL);
1185                 if (ret)
1186                         return ret;
1187         }
1188
1189         return 0;
1190 }
1191
1192 static const struct smu_temperature_range smu13_thermal_policy[] =
1193 {
1194         {-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
1195         { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
1196 };
1197
1198 static int smu_v13_0_7_get_thermal_temperature_range(struct smu_context *smu,
1199                                                      struct smu_temperature_range *range)
1200 {
1201         struct smu_table_context *table_context = &smu->smu_table;
1202         struct smu_13_0_7_powerplay_table *powerplay_table =
1203                 table_context->power_play_table;
1204         PPTable_t *pptable = smu->smu_table.driver_pptable;
1205
1206         if (!range)
1207                 return -EINVAL;
1208
1209         memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
1210
1211         range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] *
1212                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1213         range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1214                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1215         range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] *
1216                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1217         range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1218                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1219         range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] *
1220                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1221         range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
1222                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1223         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1224
1225         return 0;
1226 }
1227
1228 #define MAX(a, b)       ((a) > (b) ? (a) : (b))
1229 static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu,
1230                                            void **table)
1231 {
1232         struct smu_table_context *smu_table = &smu->smu_table;
1233         struct gpu_metrics_v1_3 *gpu_metrics =
1234                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1235         SmuMetricsExternal_t metrics_ext;
1236         SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
1237         int ret = 0;
1238
1239         ret = smu_cmn_get_metrics_table(smu,
1240                                         &metrics_ext,
1241                                         true);
1242         if (ret)
1243                 return ret;
1244
1245         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1246
1247         gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
1248         gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
1249         gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
1250         gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
1251         gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
1252         gpu_metrics->temperature_vrmem = MAX(metrics->AvgTemperature[TEMP_VR_MEM0],
1253                                              metrics->AvgTemperature[TEMP_VR_MEM1]);
1254
1255         gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
1256         gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
1257         gpu_metrics->average_mm_activity = MAX(metrics->Vcn0ActivityPercentage,
1258                                                metrics->Vcn1ActivityPercentage);
1259
1260         gpu_metrics->average_socket_power = metrics->AverageSocketPower;
1261         gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
1262
1263         if (metrics->AverageGfxActivity <= SMU_13_0_7_BUSY_THRESHOLD)
1264                 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
1265         else
1266                 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
1267
1268         if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD)
1269                 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
1270         else
1271                 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
1272
1273         gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
1274         gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
1275         gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
1276         gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
1277
1278         gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK];
1279         gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
1280         gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
1281         gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
1282         gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
1283
1284         gpu_metrics->throttle_status =
1285                         smu_v13_0_7_get_throttler_status(metrics);
1286         gpu_metrics->indep_throttle_status =
1287                         smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
1288                                                            smu_v13_0_7_throttler_map);
1289
1290         gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
1291
1292         gpu_metrics->pcie_link_width = metrics->PcieWidth;
1293         gpu_metrics->pcie_link_speed = metrics->PcieRate;
1294
1295         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1296
1297         gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX];
1298         gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC];
1299         gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP];
1300
1301         *table = (void *)gpu_metrics;
1302
1303         return sizeof(struct gpu_metrics_v1_3);
1304 }
1305
1306 static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu)
1307 {
1308         struct smu_13_0_dpm_context *dpm_context =
1309                                 smu->smu_dpm.dpm_context;
1310         struct smu_13_0_dpm_table *gfx_table =
1311                                 &dpm_context->dpm_tables.gfx_table;
1312         struct smu_13_0_dpm_table *mem_table =
1313                                 &dpm_context->dpm_tables.uclk_table;
1314         struct smu_13_0_dpm_table *soc_table =
1315                                 &dpm_context->dpm_tables.soc_table;
1316         struct smu_13_0_dpm_table *vclk_table =
1317                                 &dpm_context->dpm_tables.vclk_table;
1318         struct smu_13_0_dpm_table *dclk_table =
1319                                 &dpm_context->dpm_tables.dclk_table;
1320         struct smu_13_0_dpm_table *fclk_table =
1321                                 &dpm_context->dpm_tables.fclk_table;
1322         struct smu_umd_pstate_table *pstate_table =
1323                                 &smu->pstate_table;
1324
1325         pstate_table->gfxclk_pstate.min = gfx_table->min;
1326         pstate_table->gfxclk_pstate.peak = gfx_table->max;
1327
1328         pstate_table->uclk_pstate.min = mem_table->min;
1329         pstate_table->uclk_pstate.peak = mem_table->max;
1330
1331         pstate_table->socclk_pstate.min = soc_table->min;
1332         pstate_table->socclk_pstate.peak = soc_table->max;
1333
1334         pstate_table->vclk_pstate.min = vclk_table->min;
1335         pstate_table->vclk_pstate.peak = vclk_table->max;
1336
1337         pstate_table->dclk_pstate.min = dclk_table->min;
1338         pstate_table->dclk_pstate.peak = dclk_table->max;
1339
1340         pstate_table->fclk_pstate.min = fclk_table->min;
1341         pstate_table->fclk_pstate.peak = fclk_table->max;
1342
1343         /*
1344          * For now, just use the mininum clock frequency.
1345          * TODO: update them when the real pstate settings available
1346          */
1347         pstate_table->gfxclk_pstate.standard = gfx_table->min;
1348         pstate_table->uclk_pstate.standard = mem_table->min;
1349         pstate_table->socclk_pstate.standard = soc_table->min;
1350         pstate_table->vclk_pstate.standard = vclk_table->min;
1351         pstate_table->dclk_pstate.standard = dclk_table->min;
1352         pstate_table->fclk_pstate.standard = fclk_table->min;
1353
1354         return 0;
1355 }
1356
1357 static int smu_v13_0_7_get_fan_speed_pwm(struct smu_context *smu,
1358                                          uint32_t *speed)
1359 {
1360         if (!speed)
1361                 return -EINVAL;
1362
1363         return smu_v13_0_7_get_smu_metrics_data(smu,
1364                                                 METRICS_CURR_FANPWM,
1365                                                 speed);
1366 }
1367
1368 static int smu_v13_0_7_get_fan_speed_rpm(struct smu_context *smu,
1369                                          uint32_t *speed)
1370 {
1371         if (!speed)
1372                 return -EINVAL;
1373
1374         return smu_v13_0_7_get_smu_metrics_data(smu,
1375                                                 METRICS_CURR_FANSPEED,
1376                                                 speed);
1377 }
1378
1379 static int smu_v13_0_7_enable_mgpu_fan_boost(struct smu_context *smu)
1380 {
1381         struct smu_table_context *table_context = &smu->smu_table;
1382         PPTable_t *pptable = table_context->driver_pptable;
1383         SkuTable_t *skutable = &pptable->SkuTable;
1384
1385         /*
1386          * Skip the MGpuFanBoost setting for those ASICs
1387          * which do not support it
1388          */
1389         if (skutable->MGpuAcousticLimitRpmThreshold == 0)
1390                 return 0;
1391
1392         return smu_cmn_send_smc_msg_with_param(smu,
1393                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
1394                                                0,
1395                                                NULL);
1396 }
1397
1398 static int smu_v13_0_7_get_power_limit(struct smu_context *smu,
1399                                        uint32_t *current_power_limit,
1400                                        uint32_t *default_power_limit,
1401                                        uint32_t *max_power_limit)
1402 {
1403         struct smu_table_context *table_context = &smu->smu_table;
1404         struct smu_13_0_7_powerplay_table *powerplay_table =
1405                 (struct smu_13_0_7_powerplay_table *)table_context->power_play_table;
1406         PPTable_t *pptable = table_context->driver_pptable;
1407         SkuTable_t *skutable = &pptable->SkuTable;
1408         uint32_t power_limit, od_percent;
1409
1410         if (smu_v13_0_get_current_power_limit(smu, &power_limit))
1411                 power_limit = smu->adev->pm.ac_power ?
1412                               skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
1413                               skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
1414
1415         if (current_power_limit)
1416                 *current_power_limit = power_limit;
1417         if (default_power_limit)
1418                 *default_power_limit = power_limit;
1419
1420         if (max_power_limit) {
1421                 if (smu->od_enabled) {
1422                         od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);
1423
1424                         dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1425
1426                         power_limit *= (100 + od_percent);
1427                         power_limit /= 100;
1428                 }
1429                 *max_power_limit = power_limit;
1430         }
1431
1432         return 0;
1433 }
1434
1435 static int smu_v13_0_7_get_power_profile_mode(struct smu_context *smu, char *buf)
1436 {
1437         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external[PP_SMC_POWER_PROFILE_COUNT];
1438         uint32_t i, j, size = 0;
1439         int16_t workload_type = 0;
1440         int result = 0;
1441
1442         if (!buf)
1443                 return -EINVAL;
1444
1445         size += sysfs_emit_at(buf, size, "                              ");
1446         for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++)
1447                 size += sysfs_emit_at(buf, size, "%-14s%s", amdgpu_pp_profile_name[i],
1448                         (i == smu->power_profile_mode) ? "* " : "  ");
1449
1450         size += sysfs_emit_at(buf, size, "\n");
1451
1452         for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++) {
1453                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1454                 workload_type = smu_cmn_to_asic_specific_index(smu,
1455                                                                CMN2ASIC_MAPPING_WORKLOAD,
1456                                                                i);
1457                 if (workload_type < 0)
1458                         return -EINVAL;
1459
1460                 result = smu_cmn_update_table(smu,
1461                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1462                                           (void *)(&activity_monitor_external[i]), false);
1463                 if (result) {
1464                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1465                         return result;
1466                 }
1467         }
1468
1469 #define PRINT_DPM_MONITOR(field)                                                                        \
1470 do {                                                                                                    \
1471         size += sysfs_emit_at(buf, size, "%-30s", #field);                                              \
1472         for (j = 0; j <= PP_SMC_POWER_PROFILE_WINDOW3D; j++)                                            \
1473                 size += sysfs_emit_at(buf, size, "%-16d", activity_monitor_external[j].DpmActivityMonitorCoeffInt.field);               \
1474         size += sysfs_emit_at(buf, size, "\n");                                                         \
1475 } while (0)
1476
1477         PRINT_DPM_MONITOR(Gfx_ActiveHystLimit);
1478         PRINT_DPM_MONITOR(Gfx_IdleHystLimit);
1479         PRINT_DPM_MONITOR(Gfx_FPS);
1480         PRINT_DPM_MONITOR(Gfx_MinActiveFreqType);
1481         PRINT_DPM_MONITOR(Gfx_BoosterFreqType);
1482         PRINT_DPM_MONITOR(Gfx_MinActiveFreq);
1483         PRINT_DPM_MONITOR(Gfx_BoosterFreq);
1484         PRINT_DPM_MONITOR(Fclk_ActiveHystLimit);
1485         PRINT_DPM_MONITOR(Fclk_IdleHystLimit);
1486         PRINT_DPM_MONITOR(Fclk_FPS);
1487         PRINT_DPM_MONITOR(Fclk_MinActiveFreqType);
1488         PRINT_DPM_MONITOR(Fclk_BoosterFreqType);
1489         PRINT_DPM_MONITOR(Fclk_MinActiveFreq);
1490         PRINT_DPM_MONITOR(Fclk_BoosterFreq);
1491 #undef PRINT_DPM_MONITOR
1492
1493         return size;
1494 }
1495
1496 static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1497 {
1498
1499         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1500         DpmActivityMonitorCoeffInt_t *activity_monitor =
1501                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1502         int workload_type, ret = 0;
1503
1504         smu->power_profile_mode = input[size];
1505
1506         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_WINDOW3D) {
1507                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1508                 return -EINVAL;
1509         }
1510
1511         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1512
1513                 ret = smu_cmn_update_table(smu,
1514                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1515                                        (void *)(&activity_monitor_external), false);
1516                 if (ret) {
1517                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1518                         return ret;
1519                 }
1520
1521                 switch (input[0]) {
1522                 case 0: /* Gfxclk */
1523                         activity_monitor->Gfx_ActiveHystLimit = input[1];
1524                         activity_monitor->Gfx_IdleHystLimit = input[2];
1525                         activity_monitor->Gfx_FPS = input[3];
1526                         activity_monitor->Gfx_MinActiveFreqType = input[4];
1527                         activity_monitor->Gfx_BoosterFreqType = input[5];
1528                         activity_monitor->Gfx_MinActiveFreq = input[6];
1529                         activity_monitor->Gfx_BoosterFreq = input[7];
1530                         break;
1531                 case 1: /* Fclk */
1532                         activity_monitor->Fclk_ActiveHystLimit = input[1];
1533                         activity_monitor->Fclk_IdleHystLimit = input[2];
1534                         activity_monitor->Fclk_FPS = input[3];
1535                         activity_monitor->Fclk_MinActiveFreqType = input[4];
1536                         activity_monitor->Fclk_BoosterFreqType = input[5];
1537                         activity_monitor->Fclk_MinActiveFreq = input[6];
1538                         activity_monitor->Fclk_BoosterFreq = input[7];
1539                         break;
1540                 }
1541
1542                 ret = smu_cmn_update_table(smu,
1543                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1544                                        (void *)(&activity_monitor_external), true);
1545                 if (ret) {
1546                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1547                         return ret;
1548                 }
1549         }
1550
1551         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1552         workload_type = smu_cmn_to_asic_specific_index(smu,
1553                                                        CMN2ASIC_MAPPING_WORKLOAD,
1554                                                        smu->power_profile_mode);
1555         if (workload_type < 0)
1556                 return -EINVAL;
1557         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1558                                     1 << workload_type, NULL);
1559
1560         return ret;
1561 }
1562
1563 static int smu_v13_0_7_set_mp1_state(struct smu_context *smu,
1564                                      enum pp_mp1_state mp1_state)
1565 {
1566         int ret;
1567
1568         switch (mp1_state) {
1569         case PP_MP1_STATE_UNLOAD:
1570                 ret = smu_cmn_set_mp1_state(smu, mp1_state);
1571                 break;
1572         default:
1573                 /* Ignore others */
1574                 ret = 0;
1575         }
1576
1577         return ret;
1578 }
1579
1580 static bool smu_v13_0_7_is_mode1_reset_supported(struct smu_context *smu)
1581 {
1582         struct amdgpu_device *adev = smu->adev;
1583
1584         /* SRIOV does not support SMU mode1 reset */
1585         if (amdgpu_sriov_vf(adev))
1586                 return false;
1587
1588         return true;
1589 }
1590 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
1591         .get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask,
1592         .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
1593         .is_dpm_running = smu_v13_0_7_is_dpm_running,
1594         .dump_pptable = smu_v13_0_7_dump_pptable,
1595         .init_microcode = smu_v13_0_init_microcode,
1596         .load_microcode = smu_v13_0_load_microcode,
1597         .fini_microcode = smu_v13_0_fini_microcode,
1598         .init_smc_tables = smu_v13_0_7_init_smc_tables,
1599         .fini_smc_tables = smu_v13_0_fini_smc_tables,
1600         .init_power = smu_v13_0_init_power,
1601         .fini_power = smu_v13_0_fini_power,
1602         .check_fw_status = smu_v13_0_7_check_fw_status,
1603         .setup_pptable = smu_v13_0_7_setup_pptable,
1604         .check_fw_version = smu_v13_0_check_fw_version,
1605         .write_pptable = smu_cmn_write_pptable,
1606         .set_driver_table_location = smu_v13_0_set_driver_table_location,
1607         .system_features_control = smu_v13_0_system_features_control,
1608         .set_allowed_mask = smu_v13_0_set_allowed_mask,
1609         .get_enabled_mask = smu_cmn_get_enabled_mask,
1610         .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
1611         .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
1612         .init_pptable_microcode = smu_v13_0_init_pptable_microcode,
1613         .populate_umd_state_clk = smu_v13_0_7_populate_umd_state_clk,
1614         .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
1615         .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1616         .read_sensor = smu_v13_0_7_read_sensor,
1617         .feature_is_enabled = smu_cmn_feature_is_enabled,
1618         .print_clk_levels = smu_v13_0_7_print_clk_levels,
1619         .force_clk_levels = smu_v13_0_7_force_clk_levels,
1620         .update_pcie_parameters = smu_v13_0_7_update_pcie_parameters,
1621         .get_thermal_temperature_range = smu_v13_0_7_get_thermal_temperature_range,
1622         .register_irq_handler = smu_v13_0_register_irq_handler,
1623         .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
1624         .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
1625         .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
1626         .get_gpu_metrics = smu_v13_0_7_get_gpu_metrics,
1627         .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range,
1628         .set_performance_level = smu_v13_0_set_performance_level,
1629         .gfx_off_control = smu_v13_0_gfx_off_control,
1630         .get_fan_speed_pwm = smu_v13_0_7_get_fan_speed_pwm,
1631         .get_fan_speed_rpm = smu_v13_0_7_get_fan_speed_rpm,
1632         .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm,
1633         .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm,
1634         .get_fan_control_mode = smu_v13_0_get_fan_control_mode,
1635         .set_fan_control_mode = smu_v13_0_set_fan_control_mode,
1636         .enable_mgpu_fan_boost = smu_v13_0_7_enable_mgpu_fan_boost,
1637         .get_power_limit = smu_v13_0_7_get_power_limit,
1638         .set_power_limit = smu_v13_0_set_power_limit,
1639         .get_power_profile_mode = smu_v13_0_7_get_power_profile_mode,
1640         .set_power_profile_mode = smu_v13_0_7_set_power_profile_mode,
1641         .set_tool_table_location = smu_v13_0_set_tool_table_location,
1642         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1643         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1644         .baco_is_support = smu_v13_0_baco_is_support,
1645         .baco_get_state = smu_v13_0_baco_get_state,
1646         .baco_set_state = smu_v13_0_baco_set_state,
1647         .baco_enter = smu_v13_0_baco_enter,
1648         .baco_exit = smu_v13_0_baco_exit,
1649         .mode1_reset_is_support = smu_v13_0_7_is_mode1_reset_supported,
1650         .mode1_reset = smu_v13_0_mode1_reset,
1651         .set_mp1_state = smu_v13_0_7_set_mp1_state,
1652 };
1653
1654 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
1655 {
1656         smu->ppt_funcs = &smu_v13_0_7_ppt_funcs;
1657         smu->message_map = smu_v13_0_7_message_map;
1658         smu->clock_map = smu_v13_0_7_clk_map;
1659         smu->feature_map = smu_v13_0_7_feature_mask_map;
1660         smu->table_map = smu_v13_0_7_table_map;
1661         smu->pwr_src_map = smu_v13_0_7_pwr_src_map;
1662         smu->workload_map = smu_v13_0_7_workload_map;
1663         smu_v13_0_set_smu_mailbox_registers(smu);
1664 }